diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/OpenFPGAEngine.info b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/OpenFPGAEngine.info deleted file mode 100644 index c459498..0000000 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/OpenFPGAEngine.info +++ /dev/null @@ -1,60 +0,0 @@ -commit 520e54d7abecebf75310bb901ce702532148d686 -Merge: 4a53640c 056b7c0c -Author: Laboratory for Nano Integrated Systems (LNIS) <40280375+LNIS-Projects@users.noreply.github.com> -Date: Fri Nov 6 13:25:29 2020 -0700 - - Merge pull request #118 from LNIS-Projects/dev - - Remove the restrictions on requiring two outputs for configurable memory circuits - -commit 056b7c0c7997d2d12473f2fc4b7915e25ff74820 -Author: tangxifan -Date: Fri Nov 6 12:22:22 2020 -0700 - - [Doc] Update documentation about CCFF circuit model examples - -commit 70734abc35347dbc27113200908858c9a66e9945 -Author: tangxifan -Date: Fri Nov 6 11:20:13 2020 -0700 - - [Arch] Remove QN from stdcell arch - -commit 1a79a556467ae8d9d4d791b94462e168e15635ca -Author: tangxifan -Date: Fri Nov 6 11:19:19 2020 -0700 - - [HDL] Add DFF cell with reset but only 1 output - -commit 0a273ffab65b1f503d6e63da59c93644375dc3b1 -Author: tangxifan -Date: Fri Nov 6 11:16:46 2020 -0700 - - [Tool] Bug fix in the tight requirements on CCFF circuit model -On branch master -Your branch is up to date with 'origin/master'. - -Untracked files: - (use "git add ..." to include in what will be committed) - openfpga/openfpga - openfpga_flow/tasks/FPGA1212_FC_HD_SKY_task - openfpga_flow/tasks/FPGA1212_HIER_SKY_SC_MS_task - openfpga_flow/tasks/FPGA128128_FLAT_task - openfpga_flow/tasks/FPGA1616_FLAT_task - openfpga_flow/tasks/FPGA22_FLAT_task - openfpga_flow/tasks/FPGA22_FRAME_task - openfpga_flow/tasks/FPGA22_HIER_SKY_SC_MS_task - openfpga_flow/tasks/FPGA22_HIER_SKY_task - openfpga_flow/tasks/FPGA22_HIER_task - openfpga_flow/tasks/FPGA22_MB_task - openfpga_flow/tasks/FPGA22_MODULAR_task - openfpga_flow/tasks/FPGA22_SPY_task - openfpga_flow/tasks/FPGA3232_FLAT_task - openfpga_flow/tasks/FPGA44_FLAT_task - openfpga_flow/tasks/FPGA6464_FLAT_task - openfpga_flow/tasks/FPGA66_FLAT_task - openfpga_flow/tasks/FPGA88_FLAT_task - openfpga_flow/tasks/routing_test/ - openfpga_flow/tasks/skywater_openfpga_task - vpr/vpr - -nothing added to commit but untracked files present (use "git add" to track) diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/InstancesMap.txt b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/InstancesMap.txt deleted file mode 100644 index b431eb5..0000000 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/InstancesMap.txt +++ /dev/null @@ -1 +0,0 @@ -{"grid_clb": ["grid_clb_1__1_", "grid_clb_1__2_", "grid_clb_2__1_", "grid_clb_2__2_"], "grid_io_top": ["grid_io_top_1__3_", "grid_io_top_2__3_"], "grid_io_right": ["grid_io_right_3__1_", "grid_io_right_3__2_"], "grid_io_bottom": ["grid_io_bottom_1__0_", "grid_io_bottom_2__0_"], "grid_io_left": ["grid_io_left_0__1_", "grid_io_left_0__2_"], "sb_0__0_": ["sb_0__0_"], "sb_0__1_": ["sb_0__1_"], "sb_0__2_": ["sb_0__2_"], "sb_1__0_": ["sb_1__0_"], "sb_1__1_": ["sb_1__1_"], "sb_1__2_": ["sb_1__2_"], "sb_2__0_": ["sb_2__0_"], "sb_2__1_": ["sb_2__1_"], "sb_2__2_": ["sb_2__2_"], "cbx_1__0_": ["cbx_1__0_", "cbx_2__0_"], "cbx_1__1_": ["cbx_1__1_", "cbx_2__1_"], "cbx_1__2_": ["cbx_1__2_", "cbx_2__2_"], "cby_0__1_": ["cby_0__1_", "cby_0__2_"], "cby_1__1_": ["cby_1__1_", "cby_1__2_"], "cby_2__1_": ["cby_2__1_", "cby_2__2_"], "direct_interc": ["direct_interc_0_", "direct_interc_1_", "direct_interc_2_", "direct_interc_3_", "direct_interc_4_", "direct_interc_5_"]} \ No newline at end of file diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/define_simulation.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/define_simulation.v deleted file mode 100644 index 8cbaaf5..0000000 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/define_simulation.v +++ /dev/null @@ -1,18 +0,0 @@ -// -// -// -// -// -// -// -// -`timescale 1ns / 1ps - -`define INITIAL_SIMULATION 1 - -`define AUTOCHECKED_SIMULATION 1 - -`define ENABLE_FORMAL_VERIFICATION 1 - -`define FORMAL_SIMULATION 1 - diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/fabric_netlists.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/fabric_netlists.v deleted file mode 100644 index f1a9d36..0000000 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/fabric_netlists.v +++ /dev/null @@ -1,67 +0,0 @@ -// -// -// -// -// -// -// -// -`timescale 1ns / 1ps - -// -`include "./SRC/fpga_defines.v" - -// -`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_1.v" -`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_2.v" -`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_4.v" -`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_2.v" -`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_1.v" -`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_1.v" -`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/sdfxtp/sky130_fd_sc_hd__sdfxtp_1.v" -`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/dfxtp/sky130_fd_sc_hd__dfxtp_1.v" -`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/sc_verilog/digital_io_hd.v" -// -`include "./SRC/sub_module/inv_buf_passgate.v" -`include "./SRC/sub_module/arch_encoder.v" -`include "./SRC/sub_module/local_encoder.v" -`include "./SRC/sub_module/muxes.v" -`include "./SRC/sub_module/luts.v" -`include "./SRC/sub_module/wires.v" -`include "./SRC/sub_module/memories.v" - -// -`include "./SRC/lb/logical_tile_io_mode_physical__iopad.v" -`include "./SRC/lb/logical_tile_io_mode_io_.v" -`include "./SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4.v" -`include "./SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.v" -`include "./SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v" -`include "./SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v" -`include "./SRC/lb/logical_tile_clb_mode_default__fle.v" -`include "./SRC/lb/logical_tile_clb_mode_clb_.v" -`include "./SRC/lb/grid_io_top_top.v" -`include "./SRC/lb/grid_io_right_right.v" -`include "./SRC/lb/grid_io_bottom_bottom.v" -`include "./SRC/lb/grid_io_left_left.v" -`include "./SRC/lb/grid_clb.v" - -// -`include "./SRC/routing/sb_0__0_.v" -`include "./SRC/routing/sb_0__1_.v" -`include "./SRC/routing/sb_0__2_.v" -`include "./SRC/routing/sb_1__0_.v" -`include "./SRC/routing/sb_1__1_.v" -`include "./SRC/routing/sb_1__2_.v" -`include "./SRC/routing/sb_2__0_.v" -`include "./SRC/routing/sb_2__1_.v" -`include "./SRC/routing/sb_2__2_.v" -`include "./SRC/routing/cbx_1__0_.v" -`include "./SRC/routing/cbx_1__1_.v" -`include "./SRC/routing/cbx_1__2_.v" -`include "./SRC/routing/cby_0__1_.v" -`include "./SRC/routing/cby_1__1_.v" -`include "./SRC/routing/cby_2__1_.v" - -// -`include "./SRC/fpga_top.v" - diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/fpga_core.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/fpga_core.v deleted file mode 100644 index a1e1538..0000000 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/fpga_core.v +++ /dev/null @@ -1,1489 +0,0 @@ - - -module fpga_core -( prog_clk, Test_en, clk, gfpga_pad_EMBEDDED_IO_SOC_IN, gfpga_pad_EMBEDDED_IO_SOC_OUT, gfpga_pad_EMBEDDED_IO_SOC_DIR, ccff_head, ccff_tail, sc_head, sc_tail ); - input [0:0] prog_clk; - input [0:0] Test_en; - input [0:0] clk; - input [0:17] gfpga_pad_EMBEDDED_IO_SOC_IN; - output [0:17] gfpga_pad_EMBEDDED_IO_SOC_OUT; - output [0:17] gfpga_pad_EMBEDDED_IO_SOC_DIR; - input [0:0] ccff_head; - output [0:0] ccff_tail; - input sc_head; - output sc_tail; - - wire [0:0] cbx_1__0__0_bottom_grid_pin_0_; - wire [0:0] cbx_1__0__0_bottom_grid_pin_10_; - wire [0:0] cbx_1__0__0_bottom_grid_pin_2_; - wire [0:0] cbx_1__0__0_bottom_grid_pin_4_; - wire [0:0] cbx_1__0__0_bottom_grid_pin_6_; - wire [0:0] cbx_1__0__0_bottom_grid_pin_8_; - wire [0:0] cbx_1__0__0_ccff_tail; - wire [0:19] cbx_1__0__0_chanx_left_out; - wire [0:19] cbx_1__0__0_chanx_right_out; - wire [0:0] cbx_1__0__1_bottom_grid_pin_0_; - wire [0:0] cbx_1__0__1_bottom_grid_pin_10_; - wire [0:0] cbx_1__0__1_bottom_grid_pin_2_; - wire [0:0] cbx_1__0__1_bottom_grid_pin_4_; - wire [0:0] cbx_1__0__1_bottom_grid_pin_6_; - wire [0:0] cbx_1__0__1_bottom_grid_pin_8_; - wire [0:0] cbx_1__0__1_ccff_tail; - wire [0:19] cbx_1__0__1_chanx_left_out; - wire [0:19] cbx_1__0__1_chanx_right_out; - wire [0:0] cbx_1__1__0_bottom_grid_pin_0_; - wire [0:0] cbx_1__1__0_bottom_grid_pin_10_; - wire [0:0] cbx_1__1__0_bottom_grid_pin_11_; - wire [0:0] cbx_1__1__0_bottom_grid_pin_12_; - wire [0:0] cbx_1__1__0_bottom_grid_pin_13_; - wire [0:0] cbx_1__1__0_bottom_grid_pin_14_; - wire [0:0] cbx_1__1__0_bottom_grid_pin_15_; - wire [0:0] cbx_1__1__0_bottom_grid_pin_1_; - wire [0:0] cbx_1__1__0_bottom_grid_pin_2_; - wire [0:0] cbx_1__1__0_bottom_grid_pin_3_; - wire [0:0] cbx_1__1__0_bottom_grid_pin_4_; - wire [0:0] cbx_1__1__0_bottom_grid_pin_5_; - wire [0:0] cbx_1__1__0_bottom_grid_pin_6_; - wire [0:0] cbx_1__1__0_bottom_grid_pin_7_; - wire [0:0] cbx_1__1__0_bottom_grid_pin_8_; - wire [0:0] cbx_1__1__0_bottom_grid_pin_9_; - wire [0:0] cbx_1__1__0_ccff_tail; - wire [0:19] cbx_1__1__0_chanx_left_out; - wire [0:19] cbx_1__1__0_chanx_right_out; - wire [0:0] cbx_1__1__1_bottom_grid_pin_0_; - wire [0:0] cbx_1__1__1_bottom_grid_pin_10_; - wire [0:0] cbx_1__1__1_bottom_grid_pin_11_; - wire [0:0] cbx_1__1__1_bottom_grid_pin_12_; - wire [0:0] cbx_1__1__1_bottom_grid_pin_13_; - wire [0:0] cbx_1__1__1_bottom_grid_pin_14_; - wire [0:0] cbx_1__1__1_bottom_grid_pin_15_; - wire [0:0] cbx_1__1__1_bottom_grid_pin_1_; - wire [0:0] cbx_1__1__1_bottom_grid_pin_2_; - wire [0:0] cbx_1__1__1_bottom_grid_pin_3_; - wire [0:0] cbx_1__1__1_bottom_grid_pin_4_; - wire [0:0] cbx_1__1__1_bottom_grid_pin_5_; - wire [0:0] cbx_1__1__1_bottom_grid_pin_6_; - wire [0:0] cbx_1__1__1_bottom_grid_pin_7_; - wire [0:0] cbx_1__1__1_bottom_grid_pin_8_; - wire [0:0] cbx_1__1__1_bottom_grid_pin_9_; - wire [0:0] cbx_1__1__1_ccff_tail; - wire [0:19] cbx_1__1__1_chanx_left_out; - wire [0:19] cbx_1__1__1_chanx_right_out; - wire [0:0] cbx_1__2__0_bottom_grid_pin_0_; - wire [0:0] cbx_1__2__0_bottom_grid_pin_10_; - wire [0:0] cbx_1__2__0_bottom_grid_pin_11_; - wire [0:0] cbx_1__2__0_bottom_grid_pin_12_; - wire [0:0] cbx_1__2__0_bottom_grid_pin_13_; - wire [0:0] cbx_1__2__0_bottom_grid_pin_14_; - wire [0:0] cbx_1__2__0_bottom_grid_pin_15_; - wire [0:0] cbx_1__2__0_bottom_grid_pin_1_; - wire [0:0] cbx_1__2__0_bottom_grid_pin_2_; - wire [0:0] cbx_1__2__0_bottom_grid_pin_3_; - wire [0:0] cbx_1__2__0_bottom_grid_pin_4_; - wire [0:0] cbx_1__2__0_bottom_grid_pin_5_; - wire [0:0] cbx_1__2__0_bottom_grid_pin_6_; - wire [0:0] cbx_1__2__0_bottom_grid_pin_7_; - wire [0:0] cbx_1__2__0_bottom_grid_pin_8_; - wire [0:0] cbx_1__2__0_bottom_grid_pin_9_; - wire [0:0] cbx_1__2__0_ccff_tail; - wire [0:19] cbx_1__2__0_chanx_left_out; - wire [0:19] cbx_1__2__0_chanx_right_out; - wire [0:0] cbx_1__2__0_top_grid_pin_0_; - wire [0:0] cbx_1__2__1_bottom_grid_pin_0_; - wire [0:0] cbx_1__2__1_bottom_grid_pin_10_; - wire [0:0] cbx_1__2__1_bottom_grid_pin_11_; - wire [0:0] cbx_1__2__1_bottom_grid_pin_12_; - wire [0:0] cbx_1__2__1_bottom_grid_pin_13_; - wire [0:0] cbx_1__2__1_bottom_grid_pin_14_; - wire [0:0] cbx_1__2__1_bottom_grid_pin_15_; - wire [0:0] cbx_1__2__1_bottom_grid_pin_1_; - wire [0:0] cbx_1__2__1_bottom_grid_pin_2_; - wire [0:0] cbx_1__2__1_bottom_grid_pin_3_; - wire [0:0] cbx_1__2__1_bottom_grid_pin_4_; - wire [0:0] cbx_1__2__1_bottom_grid_pin_5_; - wire [0:0] cbx_1__2__1_bottom_grid_pin_6_; - wire [0:0] cbx_1__2__1_bottom_grid_pin_7_; - wire [0:0] cbx_1__2__1_bottom_grid_pin_8_; - wire [0:0] cbx_1__2__1_bottom_grid_pin_9_; - wire [0:0] cbx_1__2__1_ccff_tail; - wire [0:19] cbx_1__2__1_chanx_left_out; - wire [0:19] cbx_1__2__1_chanx_right_out; - wire [0:0] cbx_1__2__1_top_grid_pin_0_; - wire [0:0] cby_0__1__0_ccff_tail; - wire [0:19] cby_0__1__0_chany_bottom_out; - wire [0:19] cby_0__1__0_chany_top_out; - wire [0:0] cby_0__1__0_left_grid_pin_0_; - wire [0:0] cby_0__1__1_ccff_tail; - wire [0:19] cby_0__1__1_chany_bottom_out; - wire [0:19] cby_0__1__1_chany_top_out; - wire [0:0] cby_0__1__1_left_grid_pin_0_; - wire [0:0] cby_1__1__0_ccff_tail; - wire [0:19] cby_1__1__0_chany_bottom_out; - wire [0:19] cby_1__1__0_chany_top_out; - wire [0:0] cby_1__1__0_left_grid_pin_16_; - wire [0:0] cby_1__1__0_left_grid_pin_17_; - wire [0:0] cby_1__1__0_left_grid_pin_18_; - wire [0:0] cby_1__1__0_left_grid_pin_19_; - wire [0:0] cby_1__1__0_left_grid_pin_20_; - wire [0:0] cby_1__1__0_left_grid_pin_21_; - wire [0:0] cby_1__1__0_left_grid_pin_22_; - wire [0:0] cby_1__1__0_left_grid_pin_23_; - wire [0:0] cby_1__1__0_left_grid_pin_24_; - wire [0:0] cby_1__1__0_left_grid_pin_25_; - wire [0:0] cby_1__1__0_left_grid_pin_26_; - wire [0:0] cby_1__1__0_left_grid_pin_27_; - wire [0:0] cby_1__1__0_left_grid_pin_28_; - wire [0:0] cby_1__1__0_left_grid_pin_29_; - wire [0:0] cby_1__1__0_left_grid_pin_30_; - wire [0:0] cby_1__1__0_left_grid_pin_31_; - wire [0:0] cby_1__1__1_ccff_tail; - wire [0:19] cby_1__1__1_chany_bottom_out; - wire [0:19] cby_1__1__1_chany_top_out; - wire [0:0] cby_1__1__1_left_grid_pin_16_; - wire [0:0] cby_1__1__1_left_grid_pin_17_; - wire [0:0] cby_1__1__1_left_grid_pin_18_; - wire [0:0] cby_1__1__1_left_grid_pin_19_; - wire [0:0] cby_1__1__1_left_grid_pin_20_; - wire [0:0] cby_1__1__1_left_grid_pin_21_; - wire [0:0] cby_1__1__1_left_grid_pin_22_; - wire [0:0] cby_1__1__1_left_grid_pin_23_; - wire [0:0] cby_1__1__1_left_grid_pin_24_; - wire [0:0] cby_1__1__1_left_grid_pin_25_; - wire [0:0] cby_1__1__1_left_grid_pin_26_; - wire [0:0] cby_1__1__1_left_grid_pin_27_; - wire [0:0] cby_1__1__1_left_grid_pin_28_; - wire [0:0] cby_1__1__1_left_grid_pin_29_; - wire [0:0] cby_1__1__1_left_grid_pin_30_; - wire [0:0] cby_1__1__1_left_grid_pin_31_; - wire [0:0] cby_2__1__0_ccff_tail; - wire [0:19] cby_2__1__0_chany_bottom_out; - wire [0:19] cby_2__1__0_chany_top_out; - wire [0:0] cby_2__1__0_left_grid_pin_16_; - wire [0:0] cby_2__1__0_left_grid_pin_17_; - wire [0:0] cby_2__1__0_left_grid_pin_18_; - wire [0:0] cby_2__1__0_left_grid_pin_19_; - wire [0:0] cby_2__1__0_left_grid_pin_20_; - wire [0:0] cby_2__1__0_left_grid_pin_21_; - wire [0:0] cby_2__1__0_left_grid_pin_22_; - wire [0:0] cby_2__1__0_left_grid_pin_23_; - wire [0:0] cby_2__1__0_left_grid_pin_24_; - wire [0:0] cby_2__1__0_left_grid_pin_25_; - wire [0:0] cby_2__1__0_left_grid_pin_26_; - wire [0:0] cby_2__1__0_left_grid_pin_27_; - wire [0:0] cby_2__1__0_left_grid_pin_28_; - wire [0:0] cby_2__1__0_left_grid_pin_29_; - wire [0:0] cby_2__1__0_left_grid_pin_30_; - wire [0:0] cby_2__1__0_left_grid_pin_31_; - wire [0:0] cby_2__1__0_right_grid_pin_0_; - wire [0:0] cby_2__1__1_ccff_tail; - wire [0:19] cby_2__1__1_chany_bottom_out; - wire [0:19] cby_2__1__1_chany_top_out; - wire [0:0] cby_2__1__1_left_grid_pin_16_; - wire [0:0] cby_2__1__1_left_grid_pin_17_; - wire [0:0] cby_2__1__1_left_grid_pin_18_; - wire [0:0] cby_2__1__1_left_grid_pin_19_; - wire [0:0] cby_2__1__1_left_grid_pin_20_; - wire [0:0] cby_2__1__1_left_grid_pin_21_; - wire [0:0] cby_2__1__1_left_grid_pin_22_; - wire [0:0] cby_2__1__1_left_grid_pin_23_; - wire [0:0] cby_2__1__1_left_grid_pin_24_; - wire [0:0] cby_2__1__1_left_grid_pin_25_; - wire [0:0] cby_2__1__1_left_grid_pin_26_; - wire [0:0] cby_2__1__1_left_grid_pin_27_; - wire [0:0] cby_2__1__1_left_grid_pin_28_; - wire [0:0] cby_2__1__1_left_grid_pin_29_; - wire [0:0] cby_2__1__1_left_grid_pin_30_; - wire [0:0] cby_2__1__1_left_grid_pin_31_; - wire [0:0] cby_2__1__1_right_grid_pin_0_; - wire [0:0] direct_interc_0_out; - wire [0:0] direct_interc_1_out; - wire [0:0] direct_interc_2_out; - wire [0:0] direct_interc_3_out; - wire [0:0] direct_interc_4_out; - wire [0:0] direct_interc_5_out; - wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_50_; - wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_51_; - wire [0:0] grid_clb_0_ccff_tail; - wire [0:0] grid_clb_0_right_width_0_height_0__pin_42_lower; - wire [0:0] grid_clb_0_right_width_0_height_0__pin_42_upper; - wire [0:0] grid_clb_0_right_width_0_height_0__pin_43_lower; - wire [0:0] grid_clb_0_right_width_0_height_0__pin_43_upper; - wire [0:0] grid_clb_0_right_width_0_height_0__pin_44_lower; - wire [0:0] grid_clb_0_right_width_0_height_0__pin_44_upper; - wire [0:0] grid_clb_0_right_width_0_height_0__pin_45_lower; - wire [0:0] grid_clb_0_right_width_0_height_0__pin_45_upper; - wire [0:0] grid_clb_0_right_width_0_height_0__pin_46_lower; - wire [0:0] grid_clb_0_right_width_0_height_0__pin_46_upper; - wire [0:0] grid_clb_0_right_width_0_height_0__pin_47_lower; - wire [0:0] grid_clb_0_right_width_0_height_0__pin_47_upper; - wire [0:0] grid_clb_0_right_width_0_height_0__pin_48_lower; - wire [0:0] grid_clb_0_right_width_0_height_0__pin_48_upper; - wire [0:0] grid_clb_0_right_width_0_height_0__pin_49_lower; - wire [0:0] grid_clb_0_right_width_0_height_0__pin_49_upper; - wire [0:0] grid_clb_0_top_width_0_height_0__pin_34_lower; - wire [0:0] grid_clb_0_top_width_0_height_0__pin_34_upper; - wire [0:0] grid_clb_0_top_width_0_height_0__pin_35_lower; - wire [0:0] grid_clb_0_top_width_0_height_0__pin_35_upper; - wire [0:0] grid_clb_0_top_width_0_height_0__pin_36_lower; - wire [0:0] grid_clb_0_top_width_0_height_0__pin_36_upper; - wire [0:0] grid_clb_0_top_width_0_height_0__pin_37_lower; - wire [0:0] grid_clb_0_top_width_0_height_0__pin_37_upper; - wire [0:0] grid_clb_0_top_width_0_height_0__pin_38_lower; - wire [0:0] grid_clb_0_top_width_0_height_0__pin_38_upper; - wire [0:0] grid_clb_0_top_width_0_height_0__pin_39_lower; - wire [0:0] grid_clb_0_top_width_0_height_0__pin_39_upper; - wire [0:0] grid_clb_0_top_width_0_height_0__pin_40_lower; - wire [0:0] grid_clb_0_top_width_0_height_0__pin_40_upper; - wire [0:0] grid_clb_0_top_width_0_height_0__pin_41_lower; - wire [0:0] grid_clb_0_top_width_0_height_0__pin_41_upper; - wire [0:0] grid_clb_1__1__undriven_left_width_0_height_0__pin_52_; - wire [0:0] grid_clb_1__2__undriven_left_width_0_height_0__pin_52_; - wire [0:0] grid_clb_1__2__undriven_top_width_0_height_0__pin_32_; - wire [0:0] grid_clb_1__2__undriven_top_width_0_height_0__pin_33_; - wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_50_; - wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_51_; - wire [0:0] grid_clb_1_ccff_tail; - wire [0:0] grid_clb_1_right_width_0_height_0__pin_42_lower; - wire [0:0] grid_clb_1_right_width_0_height_0__pin_42_upper; - wire [0:0] grid_clb_1_right_width_0_height_0__pin_43_lower; - wire [0:0] grid_clb_1_right_width_0_height_0__pin_43_upper; - wire [0:0] grid_clb_1_right_width_0_height_0__pin_44_lower; - wire [0:0] grid_clb_1_right_width_0_height_0__pin_44_upper; - wire [0:0] grid_clb_1_right_width_0_height_0__pin_45_lower; - wire [0:0] grid_clb_1_right_width_0_height_0__pin_45_upper; - wire [0:0] grid_clb_1_right_width_0_height_0__pin_46_lower; - wire [0:0] grid_clb_1_right_width_0_height_0__pin_46_upper; - wire [0:0] grid_clb_1_right_width_0_height_0__pin_47_lower; - wire [0:0] grid_clb_1_right_width_0_height_0__pin_47_upper; - wire [0:0] grid_clb_1_right_width_0_height_0__pin_48_lower; - wire [0:0] grid_clb_1_right_width_0_height_0__pin_48_upper; - wire [0:0] grid_clb_1_right_width_0_height_0__pin_49_lower; - wire [0:0] grid_clb_1_right_width_0_height_0__pin_49_upper; - wire [0:0] grid_clb_1_top_width_0_height_0__pin_34_lower; - wire [0:0] grid_clb_1_top_width_0_height_0__pin_34_upper; - wire [0:0] grid_clb_1_top_width_0_height_0__pin_35_lower; - wire [0:0] grid_clb_1_top_width_0_height_0__pin_35_upper; - wire [0:0] grid_clb_1_top_width_0_height_0__pin_36_lower; - wire [0:0] grid_clb_1_top_width_0_height_0__pin_36_upper; - wire [0:0] grid_clb_1_top_width_0_height_0__pin_37_lower; - wire [0:0] grid_clb_1_top_width_0_height_0__pin_37_upper; - wire [0:0] grid_clb_1_top_width_0_height_0__pin_38_lower; - wire [0:0] grid_clb_1_top_width_0_height_0__pin_38_upper; - wire [0:0] grid_clb_1_top_width_0_height_0__pin_39_lower; - wire [0:0] grid_clb_1_top_width_0_height_0__pin_39_upper; - wire [0:0] grid_clb_1_top_width_0_height_0__pin_40_lower; - wire [0:0] grid_clb_1_top_width_0_height_0__pin_40_upper; - wire [0:0] grid_clb_1_top_width_0_height_0__pin_41_lower; - wire [0:0] grid_clb_1_top_width_0_height_0__pin_41_upper; - wire [0:0] grid_clb_2__1__undriven_bottom_width_0_height_0__pin_50_; - wire [0:0] grid_clb_2__1__undriven_bottom_width_0_height_0__pin_51_; - wire [0:0] grid_clb_2__1__undriven_left_width_0_height_0__pin_52_; - wire [0:0] grid_clb_2__2__undriven_left_width_0_height_0__pin_52_; - wire [0:0] grid_clb_2_ccff_tail; - wire [0:0] grid_clb_2_right_width_0_height_0__pin_42_lower; - wire [0:0] grid_clb_2_right_width_0_height_0__pin_42_upper; - wire [0:0] grid_clb_2_right_width_0_height_0__pin_43_lower; - wire [0:0] grid_clb_2_right_width_0_height_0__pin_43_upper; - wire [0:0] grid_clb_2_right_width_0_height_0__pin_44_lower; - wire [0:0] grid_clb_2_right_width_0_height_0__pin_44_upper; - wire [0:0] grid_clb_2_right_width_0_height_0__pin_45_lower; - wire [0:0] grid_clb_2_right_width_0_height_0__pin_45_upper; - wire [0:0] grid_clb_2_right_width_0_height_0__pin_46_lower; - wire [0:0] grid_clb_2_right_width_0_height_0__pin_46_upper; - wire [0:0] grid_clb_2_right_width_0_height_0__pin_47_lower; - wire [0:0] grid_clb_2_right_width_0_height_0__pin_47_upper; - wire [0:0] grid_clb_2_right_width_0_height_0__pin_48_lower; - wire [0:0] grid_clb_2_right_width_0_height_0__pin_48_upper; - wire [0:0] grid_clb_2_right_width_0_height_0__pin_49_lower; - wire [0:0] grid_clb_2_right_width_0_height_0__pin_49_upper; - wire [0:0] grid_clb_2_top_width_0_height_0__pin_34_lower; - wire [0:0] grid_clb_2_top_width_0_height_0__pin_34_upper; - wire [0:0] grid_clb_2_top_width_0_height_0__pin_35_lower; - wire [0:0] grid_clb_2_top_width_0_height_0__pin_35_upper; - wire [0:0] grid_clb_2_top_width_0_height_0__pin_36_lower; - wire [0:0] grid_clb_2_top_width_0_height_0__pin_36_upper; - wire [0:0] grid_clb_2_top_width_0_height_0__pin_37_lower; - wire [0:0] grid_clb_2_top_width_0_height_0__pin_37_upper; - wire [0:0] grid_clb_2_top_width_0_height_0__pin_38_lower; - wire [0:0] grid_clb_2_top_width_0_height_0__pin_38_upper; - wire [0:0] grid_clb_2_top_width_0_height_0__pin_39_lower; - wire [0:0] grid_clb_2_top_width_0_height_0__pin_39_upper; - wire [0:0] grid_clb_2_top_width_0_height_0__pin_40_lower; - wire [0:0] grid_clb_2_top_width_0_height_0__pin_40_upper; - wire [0:0] grid_clb_2_top_width_0_height_0__pin_41_lower; - wire [0:0] grid_clb_2_top_width_0_height_0__pin_41_upper; - wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_50_; - wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_51_; - wire [0:0] grid_clb_3_ccff_tail; - wire [0:0] grid_clb_3_right_width_0_height_0__pin_42_lower; - wire [0:0] grid_clb_3_right_width_0_height_0__pin_42_upper; - wire [0:0] grid_clb_3_right_width_0_height_0__pin_43_lower; - wire [0:0] grid_clb_3_right_width_0_height_0__pin_43_upper; - wire [0:0] grid_clb_3_right_width_0_height_0__pin_44_lower; - wire [0:0] grid_clb_3_right_width_0_height_0__pin_44_upper; - wire [0:0] grid_clb_3_right_width_0_height_0__pin_45_lower; - wire [0:0] grid_clb_3_right_width_0_height_0__pin_45_upper; - wire [0:0] grid_clb_3_right_width_0_height_0__pin_46_lower; - wire [0:0] grid_clb_3_right_width_0_height_0__pin_46_upper; - wire [0:0] grid_clb_3_right_width_0_height_0__pin_47_lower; - wire [0:0] grid_clb_3_right_width_0_height_0__pin_47_upper; - wire [0:0] grid_clb_3_right_width_0_height_0__pin_48_lower; - wire [0:0] grid_clb_3_right_width_0_height_0__pin_48_upper; - wire [0:0] grid_clb_3_right_width_0_height_0__pin_49_lower; - wire [0:0] grid_clb_3_right_width_0_height_0__pin_49_upper; - wire [0:0] grid_clb_3_top_width_0_height_0__pin_34_lower; - wire [0:0] grid_clb_3_top_width_0_height_0__pin_34_upper; - wire [0:0] grid_clb_3_top_width_0_height_0__pin_35_lower; - wire [0:0] grid_clb_3_top_width_0_height_0__pin_35_upper; - wire [0:0] grid_clb_3_top_width_0_height_0__pin_36_lower; - wire [0:0] grid_clb_3_top_width_0_height_0__pin_36_upper; - wire [0:0] grid_clb_3_top_width_0_height_0__pin_37_lower; - wire [0:0] grid_clb_3_top_width_0_height_0__pin_37_upper; - wire [0:0] grid_clb_3_top_width_0_height_0__pin_38_lower; - wire [0:0] grid_clb_3_top_width_0_height_0__pin_38_upper; - wire [0:0] grid_clb_3_top_width_0_height_0__pin_39_lower; - wire [0:0] grid_clb_3_top_width_0_height_0__pin_39_upper; - wire [0:0] grid_clb_3_top_width_0_height_0__pin_40_lower; - wire [0:0] grid_clb_3_top_width_0_height_0__pin_40_upper; - wire [0:0] grid_clb_3_top_width_0_height_0__pin_41_lower; - wire [0:0] grid_clb_3_top_width_0_height_0__pin_41_upper; - wire [0:0] grid_io_bottom_0_ccff_tail; - wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_11_lower; - wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_11_upper; - wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_1_lower; - wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_1_upper; - wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_3_lower; - wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_3_upper; - wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_5_lower; - wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_5_upper; - wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_7_lower; - wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_7_upper; - wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_9_lower; - wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_9_upper; - wire [0:0] grid_io_bottom_1_ccff_tail; - wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_11_lower; - wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_11_upper; - wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_1_lower; - wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_1_upper; - wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_3_lower; - wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_3_upper; - wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_5_lower; - wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_5_upper; - wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_7_lower; - wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_7_upper; - wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_9_lower; - wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_9_upper; - wire [0:0] grid_io_left_0_ccff_tail; - wire [0:0] grid_io_left_0_right_width_0_height_0__pin_1_lower; - wire [0:0] grid_io_left_0_right_width_0_height_0__pin_1_upper; - wire [0:0] grid_io_left_1_ccff_tail; - wire [0:0] grid_io_left_1_right_width_0_height_0__pin_1_lower; - wire [0:0] grid_io_left_1_right_width_0_height_0__pin_1_upper; - wire [0:0] grid_io_right_0_ccff_tail; - wire [0:0] grid_io_right_0_left_width_0_height_0__pin_1_lower; - wire [0:0] grid_io_right_0_left_width_0_height_0__pin_1_upper; - wire [0:0] grid_io_right_1_ccff_tail; - wire [0:0] grid_io_right_1_left_width_0_height_0__pin_1_lower; - wire [0:0] grid_io_right_1_left_width_0_height_0__pin_1_upper; - wire [0:0] grid_io_top_0_bottom_width_0_height_0__pin_1_lower; - wire [0:0] grid_io_top_0_bottom_width_0_height_0__pin_1_upper; - wire [0:0] grid_io_top_0_ccff_tail; - wire [0:0] grid_io_top_1_bottom_width_0_height_0__pin_1_lower; - wire [0:0] grid_io_top_1_bottom_width_0_height_0__pin_1_upper; - wire [0:0] grid_io_top_1_ccff_tail; - wire [0:19] sb_0__0__0_chanx_right_out; - wire [0:19] sb_0__0__0_chany_top_out; - wire [0:0] sb_0__1__0_ccff_tail; - wire [0:19] sb_0__1__0_chanx_right_out; - wire [0:19] sb_0__1__0_chany_bottom_out; - wire [0:19] sb_0__1__0_chany_top_out; - wire [0:0] sb_0__2__0_ccff_tail; - wire [0:19] sb_0__2__0_chanx_right_out; - wire [0:19] sb_0__2__0_chany_bottom_out; - wire [0:0] sb_1__0__0_ccff_tail; - wire [0:19] sb_1__0__0_chanx_left_out; - wire [0:19] sb_1__0__0_chanx_right_out; - wire [0:19] sb_1__0__0_chany_top_out; - wire [0:0] sb_1__1__0_ccff_tail; - wire [0:19] sb_1__1__0_chanx_left_out; - wire [0:19] sb_1__1__0_chanx_right_out; - wire [0:19] sb_1__1__0_chany_bottom_out; - wire [0:19] sb_1__1__0_chany_top_out; - wire [0:0] sb_1__2__0_ccff_tail; - wire [0:19] sb_1__2__0_chanx_left_out; - wire [0:19] sb_1__2__0_chanx_right_out; - wire [0:19] sb_1__2__0_chany_bottom_out; - wire [0:0] sb_2__0__0_ccff_tail; - wire [0:19] sb_2__0__0_chanx_left_out; - wire [0:19] sb_2__0__0_chany_top_out; - wire [0:0] sb_2__1__0_ccff_tail; - wire [0:19] sb_2__1__0_chanx_left_out; - wire [0:19] sb_2__1__0_chany_bottom_out; - wire [0:19] sb_2__1__0_chany_top_out; - wire [0:0] sb_2__2__0_ccff_tail; - wire [0:19] sb_2__2__0_chanx_left_out; - wire [0:19] sb_2__2__0_chany_bottom_out; - wire [1:0] UNCONN; - wire [12:0] scff_Wires; - - grid_clb - grid_clb_1__1_ - ( - .SC_OUT_BOT(scff_Wires[5]), - .SC_IN_TOP(scff_Wires[3]), - .prog_clk(prog_clk[0]), - .Test_en(Test_en[0]), - .clk(clk[0]), - .top_width_0_height_0__pin_0_(cbx_1__1__0_bottom_grid_pin_0_[0]), - .top_width_0_height_0__pin_1_(cbx_1__1__0_bottom_grid_pin_1_[0]), - .top_width_0_height_0__pin_2_(cbx_1__1__0_bottom_grid_pin_2_[0]), - .top_width_0_height_0__pin_3_(cbx_1__1__0_bottom_grid_pin_3_[0]), - .top_width_0_height_0__pin_4_(cbx_1__1__0_bottom_grid_pin_4_[0]), - .top_width_0_height_0__pin_5_(cbx_1__1__0_bottom_grid_pin_5_[0]), - .top_width_0_height_0__pin_6_(cbx_1__1__0_bottom_grid_pin_6_[0]), - .top_width_0_height_0__pin_7_(cbx_1__1__0_bottom_grid_pin_7_[0]), - .top_width_0_height_0__pin_8_(cbx_1__1__0_bottom_grid_pin_8_[0]), - .top_width_0_height_0__pin_9_(cbx_1__1__0_bottom_grid_pin_9_[0]), - .top_width_0_height_0__pin_10_(cbx_1__1__0_bottom_grid_pin_10_[0]), - .top_width_0_height_0__pin_11_(cbx_1__1__0_bottom_grid_pin_11_[0]), - .top_width_0_height_0__pin_12_(cbx_1__1__0_bottom_grid_pin_12_[0]), - .top_width_0_height_0__pin_13_(cbx_1__1__0_bottom_grid_pin_13_[0]), - .top_width_0_height_0__pin_14_(cbx_1__1__0_bottom_grid_pin_14_[0]), - .top_width_0_height_0__pin_15_(cbx_1__1__0_bottom_grid_pin_15_[0]), - .top_width_0_height_0__pin_32_(direct_interc_0_out[0]), - .right_width_0_height_0__pin_16_(cby_1__1__0_left_grid_pin_16_[0]), - .right_width_0_height_0__pin_17_(cby_1__1__0_left_grid_pin_17_[0]), - .right_width_0_height_0__pin_18_(cby_1__1__0_left_grid_pin_18_[0]), - .right_width_0_height_0__pin_19_(cby_1__1__0_left_grid_pin_19_[0]), - .right_width_0_height_0__pin_20_(cby_1__1__0_left_grid_pin_20_[0]), - .right_width_0_height_0__pin_21_(cby_1__1__0_left_grid_pin_21_[0]), - .right_width_0_height_0__pin_22_(cby_1__1__0_left_grid_pin_22_[0]), - .right_width_0_height_0__pin_23_(cby_1__1__0_left_grid_pin_23_[0]), - .right_width_0_height_0__pin_24_(cby_1__1__0_left_grid_pin_24_[0]), - .right_width_0_height_0__pin_25_(cby_1__1__0_left_grid_pin_25_[0]), - .right_width_0_height_0__pin_26_(cby_1__1__0_left_grid_pin_26_[0]), - .right_width_0_height_0__pin_27_(cby_1__1__0_left_grid_pin_27_[0]), - .right_width_0_height_0__pin_28_(cby_1__1__0_left_grid_pin_28_[0]), - .right_width_0_height_0__pin_29_(cby_1__1__0_left_grid_pin_29_[0]), - .right_width_0_height_0__pin_30_(cby_1__1__0_left_grid_pin_30_[0]), - .right_width_0_height_0__pin_31_(cby_1__1__0_left_grid_pin_31_[0]), - .left_width_0_height_0__pin_52_(grid_clb_1__1__undriven_left_width_0_height_0__pin_52_[0]), - .ccff_head(grid_io_left_0_ccff_tail[0]), - .top_width_0_height_0__pin_34_upper(grid_clb_0_top_width_0_height_0__pin_34_upper[0]), - .top_width_0_height_0__pin_34_lower(grid_clb_0_top_width_0_height_0__pin_34_lower[0]), - .top_width_0_height_0__pin_35_upper(grid_clb_0_top_width_0_height_0__pin_35_upper[0]), - .top_width_0_height_0__pin_35_lower(grid_clb_0_top_width_0_height_0__pin_35_lower[0]), - .top_width_0_height_0__pin_36_upper(grid_clb_0_top_width_0_height_0__pin_36_upper[0]), - .top_width_0_height_0__pin_36_lower(grid_clb_0_top_width_0_height_0__pin_36_lower[0]), - .top_width_0_height_0__pin_37_upper(grid_clb_0_top_width_0_height_0__pin_37_upper[0]), - .top_width_0_height_0__pin_37_lower(grid_clb_0_top_width_0_height_0__pin_37_lower[0]), - .top_width_0_height_0__pin_38_upper(grid_clb_0_top_width_0_height_0__pin_38_upper[0]), - .top_width_0_height_0__pin_38_lower(grid_clb_0_top_width_0_height_0__pin_38_lower[0]), - .top_width_0_height_0__pin_39_upper(grid_clb_0_top_width_0_height_0__pin_39_upper[0]), - .top_width_0_height_0__pin_39_lower(grid_clb_0_top_width_0_height_0__pin_39_lower[0]), - .top_width_0_height_0__pin_40_upper(grid_clb_0_top_width_0_height_0__pin_40_upper[0]), - .top_width_0_height_0__pin_40_lower(grid_clb_0_top_width_0_height_0__pin_40_lower[0]), - .top_width_0_height_0__pin_41_upper(grid_clb_0_top_width_0_height_0__pin_41_upper[0]), - .top_width_0_height_0__pin_41_lower(grid_clb_0_top_width_0_height_0__pin_41_lower[0]), - .right_width_0_height_0__pin_42_upper(grid_clb_0_right_width_0_height_0__pin_42_upper[0]), - .right_width_0_height_0__pin_42_lower(grid_clb_0_right_width_0_height_0__pin_42_lower[0]), - .right_width_0_height_0__pin_43_upper(grid_clb_0_right_width_0_height_0__pin_43_upper[0]), - .right_width_0_height_0__pin_43_lower(grid_clb_0_right_width_0_height_0__pin_43_lower[0]), - .right_width_0_height_0__pin_44_upper(grid_clb_0_right_width_0_height_0__pin_44_upper[0]), - .right_width_0_height_0__pin_44_lower(grid_clb_0_right_width_0_height_0__pin_44_lower[0]), - .right_width_0_height_0__pin_45_upper(grid_clb_0_right_width_0_height_0__pin_45_upper[0]), - .right_width_0_height_0__pin_45_lower(grid_clb_0_right_width_0_height_0__pin_45_lower[0]), - .right_width_0_height_0__pin_46_upper(grid_clb_0_right_width_0_height_0__pin_46_upper[0]), - .right_width_0_height_0__pin_46_lower(grid_clb_0_right_width_0_height_0__pin_46_lower[0]), - .right_width_0_height_0__pin_47_upper(grid_clb_0_right_width_0_height_0__pin_47_upper[0]), - .right_width_0_height_0__pin_47_lower(grid_clb_0_right_width_0_height_0__pin_47_lower[0]), - .right_width_0_height_0__pin_48_upper(grid_clb_0_right_width_0_height_0__pin_48_upper[0]), - .right_width_0_height_0__pin_48_lower(grid_clb_0_right_width_0_height_0__pin_48_lower[0]), - .right_width_0_height_0__pin_49_upper(grid_clb_0_right_width_0_height_0__pin_49_upper[0]), - .right_width_0_height_0__pin_49_lower(grid_clb_0_right_width_0_height_0__pin_49_lower[0]), - .bottom_width_0_height_0__pin_50_(grid_clb_0_bottom_width_0_height_0__pin_50_[0]), - .ccff_tail(grid_clb_0_ccff_tail[0]) - ); - - - grid_clb - grid_clb_1__2_ - ( - .SC_OUT_BOT(scff_Wires[2]), - .SC_IN_TOP(scff_Wires[1]), - .prog_clk(prog_clk[0]), - .Test_en(Test_en[0]), - .clk(clk[0]), - .top_width_0_height_0__pin_0_(cbx_1__2__0_bottom_grid_pin_0_[0]), - .top_width_0_height_0__pin_1_(cbx_1__2__0_bottom_grid_pin_1_[0]), - .top_width_0_height_0__pin_2_(cbx_1__2__0_bottom_grid_pin_2_[0]), - .top_width_0_height_0__pin_3_(cbx_1__2__0_bottom_grid_pin_3_[0]), - .top_width_0_height_0__pin_4_(cbx_1__2__0_bottom_grid_pin_4_[0]), - .top_width_0_height_0__pin_5_(cbx_1__2__0_bottom_grid_pin_5_[0]), - .top_width_0_height_0__pin_6_(cbx_1__2__0_bottom_grid_pin_6_[0]), - .top_width_0_height_0__pin_7_(cbx_1__2__0_bottom_grid_pin_7_[0]), - .top_width_0_height_0__pin_8_(cbx_1__2__0_bottom_grid_pin_8_[0]), - .top_width_0_height_0__pin_9_(cbx_1__2__0_bottom_grid_pin_9_[0]), - .top_width_0_height_0__pin_10_(cbx_1__2__0_bottom_grid_pin_10_[0]), - .top_width_0_height_0__pin_11_(cbx_1__2__0_bottom_grid_pin_11_[0]), - .top_width_0_height_0__pin_12_(cbx_1__2__0_bottom_grid_pin_12_[0]), - .top_width_0_height_0__pin_13_(cbx_1__2__0_bottom_grid_pin_13_[0]), - .top_width_0_height_0__pin_14_(cbx_1__2__0_bottom_grid_pin_14_[0]), - .top_width_0_height_0__pin_15_(cbx_1__2__0_bottom_grid_pin_15_[0]), - .top_width_0_height_0__pin_32_(grid_clb_1__2__undriven_top_width_0_height_0__pin_32_[0]), - .right_width_0_height_0__pin_16_(cby_1__1__1_left_grid_pin_16_[0]), - .right_width_0_height_0__pin_17_(cby_1__1__1_left_grid_pin_17_[0]), - .right_width_0_height_0__pin_18_(cby_1__1__1_left_grid_pin_18_[0]), - .right_width_0_height_0__pin_19_(cby_1__1__1_left_grid_pin_19_[0]), - .right_width_0_height_0__pin_20_(cby_1__1__1_left_grid_pin_20_[0]), - .right_width_0_height_0__pin_21_(cby_1__1__1_left_grid_pin_21_[0]), - .right_width_0_height_0__pin_22_(cby_1__1__1_left_grid_pin_22_[0]), - .right_width_0_height_0__pin_23_(cby_1__1__1_left_grid_pin_23_[0]), - .right_width_0_height_0__pin_24_(cby_1__1__1_left_grid_pin_24_[0]), - .right_width_0_height_0__pin_25_(cby_1__1__1_left_grid_pin_25_[0]), - .right_width_0_height_0__pin_26_(cby_1__1__1_left_grid_pin_26_[0]), - .right_width_0_height_0__pin_27_(cby_1__1__1_left_grid_pin_27_[0]), - .right_width_0_height_0__pin_28_(cby_1__1__1_left_grid_pin_28_[0]), - .right_width_0_height_0__pin_29_(cby_1__1__1_left_grid_pin_29_[0]), - .right_width_0_height_0__pin_30_(cby_1__1__1_left_grid_pin_30_[0]), - .right_width_0_height_0__pin_31_(cby_1__1__1_left_grid_pin_31_[0]), - .left_width_0_height_0__pin_52_(grid_clb_1__2__undriven_left_width_0_height_0__pin_52_[0]), - .ccff_head(grid_io_left_1_ccff_tail[0]), - .top_width_0_height_0__pin_34_upper(grid_clb_1_top_width_0_height_0__pin_34_upper[0]), - .top_width_0_height_0__pin_34_lower(grid_clb_1_top_width_0_height_0__pin_34_lower[0]), - .top_width_0_height_0__pin_35_upper(grid_clb_1_top_width_0_height_0__pin_35_upper[0]), - .top_width_0_height_0__pin_35_lower(grid_clb_1_top_width_0_height_0__pin_35_lower[0]), - .top_width_0_height_0__pin_36_upper(grid_clb_1_top_width_0_height_0__pin_36_upper[0]), - .top_width_0_height_0__pin_36_lower(grid_clb_1_top_width_0_height_0__pin_36_lower[0]), - .top_width_0_height_0__pin_37_upper(grid_clb_1_top_width_0_height_0__pin_37_upper[0]), - .top_width_0_height_0__pin_37_lower(grid_clb_1_top_width_0_height_0__pin_37_lower[0]), - .top_width_0_height_0__pin_38_upper(grid_clb_1_top_width_0_height_0__pin_38_upper[0]), - .top_width_0_height_0__pin_38_lower(grid_clb_1_top_width_0_height_0__pin_38_lower[0]), - .top_width_0_height_0__pin_39_upper(grid_clb_1_top_width_0_height_0__pin_39_upper[0]), - .top_width_0_height_0__pin_39_lower(grid_clb_1_top_width_0_height_0__pin_39_lower[0]), - .top_width_0_height_0__pin_40_upper(grid_clb_1_top_width_0_height_0__pin_40_upper[0]), - .top_width_0_height_0__pin_40_lower(grid_clb_1_top_width_0_height_0__pin_40_lower[0]), - .top_width_0_height_0__pin_41_upper(grid_clb_1_top_width_0_height_0__pin_41_upper[0]), - .top_width_0_height_0__pin_41_lower(grid_clb_1_top_width_0_height_0__pin_41_lower[0]), - .right_width_0_height_0__pin_42_upper(grid_clb_1_right_width_0_height_0__pin_42_upper[0]), - .right_width_0_height_0__pin_42_lower(grid_clb_1_right_width_0_height_0__pin_42_lower[0]), - .right_width_0_height_0__pin_43_upper(grid_clb_1_right_width_0_height_0__pin_43_upper[0]), - .right_width_0_height_0__pin_43_lower(grid_clb_1_right_width_0_height_0__pin_43_lower[0]), - .right_width_0_height_0__pin_44_upper(grid_clb_1_right_width_0_height_0__pin_44_upper[0]), - .right_width_0_height_0__pin_44_lower(grid_clb_1_right_width_0_height_0__pin_44_lower[0]), - .right_width_0_height_0__pin_45_upper(grid_clb_1_right_width_0_height_0__pin_45_upper[0]), - .right_width_0_height_0__pin_45_lower(grid_clb_1_right_width_0_height_0__pin_45_lower[0]), - .right_width_0_height_0__pin_46_upper(grid_clb_1_right_width_0_height_0__pin_46_upper[0]), - .right_width_0_height_0__pin_46_lower(grid_clb_1_right_width_0_height_0__pin_46_lower[0]), - .right_width_0_height_0__pin_47_upper(grid_clb_1_right_width_0_height_0__pin_47_upper[0]), - .right_width_0_height_0__pin_47_lower(grid_clb_1_right_width_0_height_0__pin_47_lower[0]), - .right_width_0_height_0__pin_48_upper(grid_clb_1_right_width_0_height_0__pin_48_upper[0]), - .right_width_0_height_0__pin_48_lower(grid_clb_1_right_width_0_height_0__pin_48_lower[0]), - .right_width_0_height_0__pin_49_upper(grid_clb_1_right_width_0_height_0__pin_49_upper[0]), - .right_width_0_height_0__pin_49_lower(grid_clb_1_right_width_0_height_0__pin_49_lower[0]), - .bottom_width_0_height_0__pin_50_(grid_clb_1_bottom_width_0_height_0__pin_50_[0]), - .ccff_tail(grid_clb_1_ccff_tail[0]) - ); - - - grid_clb - grid_clb_2__1_ - ( - .SC_OUT_TOP(scff_Wires[9]), - .SC_IN_BOT(scff_Wires[8]), - .prog_clk(prog_clk[0]), - .Test_en(Test_en[0]), - .clk(clk[0]), - .top_width_0_height_0__pin_0_(cbx_1__1__1_bottom_grid_pin_0_[0]), - .top_width_0_height_0__pin_1_(cbx_1__1__1_bottom_grid_pin_1_[0]), - .top_width_0_height_0__pin_2_(cbx_1__1__1_bottom_grid_pin_2_[0]), - .top_width_0_height_0__pin_3_(cbx_1__1__1_bottom_grid_pin_3_[0]), - .top_width_0_height_0__pin_4_(cbx_1__1__1_bottom_grid_pin_4_[0]), - .top_width_0_height_0__pin_5_(cbx_1__1__1_bottom_grid_pin_5_[0]), - .top_width_0_height_0__pin_6_(cbx_1__1__1_bottom_grid_pin_6_[0]), - .top_width_0_height_0__pin_7_(cbx_1__1__1_bottom_grid_pin_7_[0]), - .top_width_0_height_0__pin_8_(cbx_1__1__1_bottom_grid_pin_8_[0]), - .top_width_0_height_0__pin_9_(cbx_1__1__1_bottom_grid_pin_9_[0]), - .top_width_0_height_0__pin_10_(cbx_1__1__1_bottom_grid_pin_10_[0]), - .top_width_0_height_0__pin_11_(cbx_1__1__1_bottom_grid_pin_11_[0]), - .top_width_0_height_0__pin_12_(cbx_1__1__1_bottom_grid_pin_12_[0]), - .top_width_0_height_0__pin_13_(cbx_1__1__1_bottom_grid_pin_13_[0]), - .top_width_0_height_0__pin_14_(cbx_1__1__1_bottom_grid_pin_14_[0]), - .top_width_0_height_0__pin_15_(cbx_1__1__1_bottom_grid_pin_15_[0]), - .top_width_0_height_0__pin_32_(direct_interc_1_out[0]), - .right_width_0_height_0__pin_16_(cby_2__1__0_left_grid_pin_16_[0]), - .right_width_0_height_0__pin_17_(cby_2__1__0_left_grid_pin_17_[0]), - .right_width_0_height_0__pin_18_(cby_2__1__0_left_grid_pin_18_[0]), - .right_width_0_height_0__pin_19_(cby_2__1__0_left_grid_pin_19_[0]), - .right_width_0_height_0__pin_20_(cby_2__1__0_left_grid_pin_20_[0]), - .right_width_0_height_0__pin_21_(cby_2__1__0_left_grid_pin_21_[0]), - .right_width_0_height_0__pin_22_(cby_2__1__0_left_grid_pin_22_[0]), - .right_width_0_height_0__pin_23_(cby_2__1__0_left_grid_pin_23_[0]), - .right_width_0_height_0__pin_24_(cby_2__1__0_left_grid_pin_24_[0]), - .right_width_0_height_0__pin_25_(cby_2__1__0_left_grid_pin_25_[0]), - .right_width_0_height_0__pin_26_(cby_2__1__0_left_grid_pin_26_[0]), - .right_width_0_height_0__pin_27_(cby_2__1__0_left_grid_pin_27_[0]), - .right_width_0_height_0__pin_28_(cby_2__1__0_left_grid_pin_28_[0]), - .right_width_0_height_0__pin_29_(cby_2__1__0_left_grid_pin_29_[0]), - .right_width_0_height_0__pin_30_(cby_2__1__0_left_grid_pin_30_[0]), - .right_width_0_height_0__pin_31_(cby_2__1__0_left_grid_pin_31_[0]), - .left_width_0_height_0__pin_52_(grid_clb_2__1__undriven_left_width_0_height_0__pin_52_[0]), - .ccff_head(cby_1__1__0_ccff_tail[0]), - .top_width_0_height_0__pin_34_upper(grid_clb_2_top_width_0_height_0__pin_34_upper[0]), - .top_width_0_height_0__pin_34_lower(grid_clb_2_top_width_0_height_0__pin_34_lower[0]), - .top_width_0_height_0__pin_35_upper(grid_clb_2_top_width_0_height_0__pin_35_upper[0]), - .top_width_0_height_0__pin_35_lower(grid_clb_2_top_width_0_height_0__pin_35_lower[0]), - .top_width_0_height_0__pin_36_upper(grid_clb_2_top_width_0_height_0__pin_36_upper[0]), - .top_width_0_height_0__pin_36_lower(grid_clb_2_top_width_0_height_0__pin_36_lower[0]), - .top_width_0_height_0__pin_37_upper(grid_clb_2_top_width_0_height_0__pin_37_upper[0]), - .top_width_0_height_0__pin_37_lower(grid_clb_2_top_width_0_height_0__pin_37_lower[0]), - .top_width_0_height_0__pin_38_upper(grid_clb_2_top_width_0_height_0__pin_38_upper[0]), - .top_width_0_height_0__pin_38_lower(grid_clb_2_top_width_0_height_0__pin_38_lower[0]), - .top_width_0_height_0__pin_39_upper(grid_clb_2_top_width_0_height_0__pin_39_upper[0]), - .top_width_0_height_0__pin_39_lower(grid_clb_2_top_width_0_height_0__pin_39_lower[0]), - .top_width_0_height_0__pin_40_upper(grid_clb_2_top_width_0_height_0__pin_40_upper[0]), - .top_width_0_height_0__pin_40_lower(grid_clb_2_top_width_0_height_0__pin_40_lower[0]), - .top_width_0_height_0__pin_41_upper(grid_clb_2_top_width_0_height_0__pin_41_upper[0]), - .top_width_0_height_0__pin_41_lower(grid_clb_2_top_width_0_height_0__pin_41_lower[0]), - .right_width_0_height_0__pin_42_upper(grid_clb_2_right_width_0_height_0__pin_42_upper[0]), - .right_width_0_height_0__pin_42_lower(grid_clb_2_right_width_0_height_0__pin_42_lower[0]), - .right_width_0_height_0__pin_43_upper(grid_clb_2_right_width_0_height_0__pin_43_upper[0]), - .right_width_0_height_0__pin_43_lower(grid_clb_2_right_width_0_height_0__pin_43_lower[0]), - .right_width_0_height_0__pin_44_upper(grid_clb_2_right_width_0_height_0__pin_44_upper[0]), - .right_width_0_height_0__pin_44_lower(grid_clb_2_right_width_0_height_0__pin_44_lower[0]), - .right_width_0_height_0__pin_45_upper(grid_clb_2_right_width_0_height_0__pin_45_upper[0]), - .right_width_0_height_0__pin_45_lower(grid_clb_2_right_width_0_height_0__pin_45_lower[0]), - .right_width_0_height_0__pin_46_upper(grid_clb_2_right_width_0_height_0__pin_46_upper[0]), - .right_width_0_height_0__pin_46_lower(grid_clb_2_right_width_0_height_0__pin_46_lower[0]), - .right_width_0_height_0__pin_47_upper(grid_clb_2_right_width_0_height_0__pin_47_upper[0]), - .right_width_0_height_0__pin_47_lower(grid_clb_2_right_width_0_height_0__pin_47_lower[0]), - .right_width_0_height_0__pin_48_upper(grid_clb_2_right_width_0_height_0__pin_48_upper[0]), - .right_width_0_height_0__pin_48_lower(grid_clb_2_right_width_0_height_0__pin_48_lower[0]), - .right_width_0_height_0__pin_49_upper(grid_clb_2_right_width_0_height_0__pin_49_upper[0]), - .right_width_0_height_0__pin_49_lower(grid_clb_2_right_width_0_height_0__pin_49_lower[0]), - .bottom_width_0_height_0__pin_50_(grid_clb_2__1__undriven_bottom_width_0_height_0__pin_50_[0]), - .ccff_tail(grid_clb_2_ccff_tail[0]) - ); - - - grid_clb - grid_clb_2__2_ - ( - .SC_OUT_TOP(scff_Wires[11]), - .SC_IN_BOT(scff_Wires[10]), - .prog_clk(prog_clk[0]), - .Test_en(Test_en[0]), - .clk(clk[0]), - .top_width_0_height_0__pin_0_(cbx_1__2__1_bottom_grid_pin_0_[0]), - .top_width_0_height_0__pin_1_(cbx_1__2__1_bottom_grid_pin_1_[0]), - .top_width_0_height_0__pin_2_(cbx_1__2__1_bottom_grid_pin_2_[0]), - .top_width_0_height_0__pin_3_(cbx_1__2__1_bottom_grid_pin_3_[0]), - .top_width_0_height_0__pin_4_(cbx_1__2__1_bottom_grid_pin_4_[0]), - .top_width_0_height_0__pin_5_(cbx_1__2__1_bottom_grid_pin_5_[0]), - .top_width_0_height_0__pin_6_(cbx_1__2__1_bottom_grid_pin_6_[0]), - .top_width_0_height_0__pin_7_(cbx_1__2__1_bottom_grid_pin_7_[0]), - .top_width_0_height_0__pin_8_(cbx_1__2__1_bottom_grid_pin_8_[0]), - .top_width_0_height_0__pin_9_(cbx_1__2__1_bottom_grid_pin_9_[0]), - .top_width_0_height_0__pin_10_(cbx_1__2__1_bottom_grid_pin_10_[0]), - .top_width_0_height_0__pin_11_(cbx_1__2__1_bottom_grid_pin_11_[0]), - .top_width_0_height_0__pin_12_(cbx_1__2__1_bottom_grid_pin_12_[0]), - .top_width_0_height_0__pin_13_(cbx_1__2__1_bottom_grid_pin_13_[0]), - .top_width_0_height_0__pin_14_(cbx_1__2__1_bottom_grid_pin_14_[0]), - .top_width_0_height_0__pin_15_(cbx_1__2__1_bottom_grid_pin_15_[0]), - .top_width_0_height_0__pin_32_(direct_interc_2_out[0]), - .right_width_0_height_0__pin_16_(cby_2__1__1_left_grid_pin_16_[0]), - .right_width_0_height_0__pin_17_(cby_2__1__1_left_grid_pin_17_[0]), - .right_width_0_height_0__pin_18_(cby_2__1__1_left_grid_pin_18_[0]), - .right_width_0_height_0__pin_19_(cby_2__1__1_left_grid_pin_19_[0]), - .right_width_0_height_0__pin_20_(cby_2__1__1_left_grid_pin_20_[0]), - .right_width_0_height_0__pin_21_(cby_2__1__1_left_grid_pin_21_[0]), - .right_width_0_height_0__pin_22_(cby_2__1__1_left_grid_pin_22_[0]), - .right_width_0_height_0__pin_23_(cby_2__1__1_left_grid_pin_23_[0]), - .right_width_0_height_0__pin_24_(cby_2__1__1_left_grid_pin_24_[0]), - .right_width_0_height_0__pin_25_(cby_2__1__1_left_grid_pin_25_[0]), - .right_width_0_height_0__pin_26_(cby_2__1__1_left_grid_pin_26_[0]), - .right_width_0_height_0__pin_27_(cby_2__1__1_left_grid_pin_27_[0]), - .right_width_0_height_0__pin_28_(cby_2__1__1_left_grid_pin_28_[0]), - .right_width_0_height_0__pin_29_(cby_2__1__1_left_grid_pin_29_[0]), - .right_width_0_height_0__pin_30_(cby_2__1__1_left_grid_pin_30_[0]), - .right_width_0_height_0__pin_31_(cby_2__1__1_left_grid_pin_31_[0]), - .left_width_0_height_0__pin_52_(grid_clb_2__2__undriven_left_width_0_height_0__pin_52_[0]), - .ccff_head(cby_1__1__1_ccff_tail[0]), - .top_width_0_height_0__pin_34_upper(grid_clb_3_top_width_0_height_0__pin_34_upper[0]), - .top_width_0_height_0__pin_34_lower(grid_clb_3_top_width_0_height_0__pin_34_lower[0]), - .top_width_0_height_0__pin_35_upper(grid_clb_3_top_width_0_height_0__pin_35_upper[0]), - .top_width_0_height_0__pin_35_lower(grid_clb_3_top_width_0_height_0__pin_35_lower[0]), - .top_width_0_height_0__pin_36_upper(grid_clb_3_top_width_0_height_0__pin_36_upper[0]), - .top_width_0_height_0__pin_36_lower(grid_clb_3_top_width_0_height_0__pin_36_lower[0]), - .top_width_0_height_0__pin_37_upper(grid_clb_3_top_width_0_height_0__pin_37_upper[0]), - .top_width_0_height_0__pin_37_lower(grid_clb_3_top_width_0_height_0__pin_37_lower[0]), - .top_width_0_height_0__pin_38_upper(grid_clb_3_top_width_0_height_0__pin_38_upper[0]), - .top_width_0_height_0__pin_38_lower(grid_clb_3_top_width_0_height_0__pin_38_lower[0]), - .top_width_0_height_0__pin_39_upper(grid_clb_3_top_width_0_height_0__pin_39_upper[0]), - .top_width_0_height_0__pin_39_lower(grid_clb_3_top_width_0_height_0__pin_39_lower[0]), - .top_width_0_height_0__pin_40_upper(grid_clb_3_top_width_0_height_0__pin_40_upper[0]), - .top_width_0_height_0__pin_40_lower(grid_clb_3_top_width_0_height_0__pin_40_lower[0]), - .top_width_0_height_0__pin_41_upper(grid_clb_3_top_width_0_height_0__pin_41_upper[0]), - .top_width_0_height_0__pin_41_lower(grid_clb_3_top_width_0_height_0__pin_41_lower[0]), - .right_width_0_height_0__pin_42_upper(grid_clb_3_right_width_0_height_0__pin_42_upper[0]), - .right_width_0_height_0__pin_42_lower(grid_clb_3_right_width_0_height_0__pin_42_lower[0]), - .right_width_0_height_0__pin_43_upper(grid_clb_3_right_width_0_height_0__pin_43_upper[0]), - .right_width_0_height_0__pin_43_lower(grid_clb_3_right_width_0_height_0__pin_43_lower[0]), - .right_width_0_height_0__pin_44_upper(grid_clb_3_right_width_0_height_0__pin_44_upper[0]), - .right_width_0_height_0__pin_44_lower(grid_clb_3_right_width_0_height_0__pin_44_lower[0]), - .right_width_0_height_0__pin_45_upper(grid_clb_3_right_width_0_height_0__pin_45_upper[0]), - .right_width_0_height_0__pin_45_lower(grid_clb_3_right_width_0_height_0__pin_45_lower[0]), - .right_width_0_height_0__pin_46_upper(grid_clb_3_right_width_0_height_0__pin_46_upper[0]), - .right_width_0_height_0__pin_46_lower(grid_clb_3_right_width_0_height_0__pin_46_lower[0]), - .right_width_0_height_0__pin_47_upper(grid_clb_3_right_width_0_height_0__pin_47_upper[0]), - .right_width_0_height_0__pin_47_lower(grid_clb_3_right_width_0_height_0__pin_47_lower[0]), - .right_width_0_height_0__pin_48_upper(grid_clb_3_right_width_0_height_0__pin_48_upper[0]), - .right_width_0_height_0__pin_48_lower(grid_clb_3_right_width_0_height_0__pin_48_lower[0]), - .right_width_0_height_0__pin_49_upper(grid_clb_3_right_width_0_height_0__pin_49_upper[0]), - .right_width_0_height_0__pin_49_lower(grid_clb_3_right_width_0_height_0__pin_49_lower[0]), - .bottom_width_0_height_0__pin_50_(grid_clb_3_bottom_width_0_height_0__pin_50_[0]), - .ccff_tail(grid_clb_3_ccff_tail[0]) - ); - - - sb_0__0_ - sb_0__0_ - ( - .prog_clk(prog_clk[0]), - .chany_top_in(cby_0__1__0_chany_bottom_out[0:19]), - .top_left_grid_pin_1_(grid_io_left_0_right_width_0_height_0__pin_1_lower[0]), - .chanx_right_in(cbx_1__0__0_chanx_left_out[0:19]), - .right_bottom_grid_pin_1_(grid_io_bottom_0_top_width_0_height_0__pin_1_upper[0]), - .right_bottom_grid_pin_3_(grid_io_bottom_0_top_width_0_height_0__pin_3_upper[0]), - .right_bottom_grid_pin_5_(grid_io_bottom_0_top_width_0_height_0__pin_5_upper[0]), - .right_bottom_grid_pin_7_(grid_io_bottom_0_top_width_0_height_0__pin_7_upper[0]), - .right_bottom_grid_pin_9_(grid_io_bottom_0_top_width_0_height_0__pin_9_upper[0]), - .right_bottom_grid_pin_11_(grid_io_bottom_0_top_width_0_height_0__pin_11_upper[0]), - .ccff_head(grid_io_bottom_0_ccff_tail[0]), - .chany_top_out(sb_0__0__0_chany_top_out[0:19]), - .chanx_right_out(sb_0__0__0_chanx_right_out[0:19]), - .ccff_tail(ccff_tail[0]) - ); - - - sb_0__1_ - sb_0__1_ - ( - .prog_clk(prog_clk[0]), - .chany_top_in(cby_0__1__1_chany_bottom_out[0:19]), - .top_left_grid_pin_1_(grid_io_left_1_right_width_0_height_0__pin_1_lower[0]), - .chanx_right_in(cbx_1__1__0_chanx_left_out[0:19]), - .right_bottom_grid_pin_34_(grid_clb_0_top_width_0_height_0__pin_34_upper[0]), - .right_bottom_grid_pin_35_(grid_clb_0_top_width_0_height_0__pin_35_upper[0]), - .right_bottom_grid_pin_36_(grid_clb_0_top_width_0_height_0__pin_36_upper[0]), - .right_bottom_grid_pin_37_(grid_clb_0_top_width_0_height_0__pin_37_upper[0]), - .right_bottom_grid_pin_38_(grid_clb_0_top_width_0_height_0__pin_38_upper[0]), - .right_bottom_grid_pin_39_(grid_clb_0_top_width_0_height_0__pin_39_upper[0]), - .right_bottom_grid_pin_40_(grid_clb_0_top_width_0_height_0__pin_40_upper[0]), - .right_bottom_grid_pin_41_(grid_clb_0_top_width_0_height_0__pin_41_upper[0]), - .chany_bottom_in(cby_0__1__0_chany_top_out[0:19]), - .bottom_left_grid_pin_1_(grid_io_left_0_right_width_0_height_0__pin_1_upper[0]), - .ccff_head(cbx_1__1__0_ccff_tail[0]), - .chany_top_out(sb_0__1__0_chany_top_out[0:19]), - .chanx_right_out(sb_0__1__0_chanx_right_out[0:19]), - .chany_bottom_out(sb_0__1__0_chany_bottom_out[0:19]), - .ccff_tail(sb_0__1__0_ccff_tail[0]) - ); - - - sb_0__2_ - sb_0__2_ - ( - .SC_OUT_BOT(scff_Wires[0]), - .SC_IN_TOP(sc_head), - .prog_clk(prog_clk[0]), - .chanx_right_in(cbx_1__2__0_chanx_left_out[0:19]), - .right_top_grid_pin_1_(grid_io_top_0_bottom_width_0_height_0__pin_1_upper[0]), - .right_bottom_grid_pin_34_(grid_clb_1_top_width_0_height_0__pin_34_upper[0]), - .right_bottom_grid_pin_35_(grid_clb_1_top_width_0_height_0__pin_35_upper[0]), - .right_bottom_grid_pin_36_(grid_clb_1_top_width_0_height_0__pin_36_upper[0]), - .right_bottom_grid_pin_37_(grid_clb_1_top_width_0_height_0__pin_37_upper[0]), - .right_bottom_grid_pin_38_(grid_clb_1_top_width_0_height_0__pin_38_upper[0]), - .right_bottom_grid_pin_39_(grid_clb_1_top_width_0_height_0__pin_39_upper[0]), - .right_bottom_grid_pin_40_(grid_clb_1_top_width_0_height_0__pin_40_upper[0]), - .right_bottom_grid_pin_41_(grid_clb_1_top_width_0_height_0__pin_41_upper[0]), - .chany_bottom_in(cby_0__1__1_chany_top_out[0:19]), - .bottom_left_grid_pin_1_(grid_io_left_1_right_width_0_height_0__pin_1_upper[0]), - .ccff_head(grid_io_top_0_ccff_tail[0]), - .chanx_right_out(sb_0__2__0_chanx_right_out[0:19]), - .chany_bottom_out(sb_0__2__0_chany_bottom_out[0:19]), - .ccff_tail(sb_0__2__0_ccff_tail[0]) - ); - - - sb_1__0_ - sb_1__0_ - ( - .SC_OUT_BOT(scff_Wires[7]), - .SC_IN_TOP(scff_Wires[6]), - .prog_clk(prog_clk[0]), - .chany_top_in(cby_1__1__0_chany_bottom_out[0:19]), - .top_left_grid_pin_42_(grid_clb_0_right_width_0_height_0__pin_42_lower[0]), - .top_left_grid_pin_43_(grid_clb_0_right_width_0_height_0__pin_43_lower[0]), - .top_left_grid_pin_44_(grid_clb_0_right_width_0_height_0__pin_44_lower[0]), - .top_left_grid_pin_45_(grid_clb_0_right_width_0_height_0__pin_45_lower[0]), - .top_left_grid_pin_46_(grid_clb_0_right_width_0_height_0__pin_46_lower[0]), - .top_left_grid_pin_47_(grid_clb_0_right_width_0_height_0__pin_47_lower[0]), - .top_left_grid_pin_48_(grid_clb_0_right_width_0_height_0__pin_48_lower[0]), - .top_left_grid_pin_49_(grid_clb_0_right_width_0_height_0__pin_49_lower[0]), - .chanx_right_in(cbx_1__0__1_chanx_left_out[0:19]), - .right_bottom_grid_pin_1_(grid_io_bottom_1_top_width_0_height_0__pin_1_upper[0]), - .right_bottom_grid_pin_3_(grid_io_bottom_1_top_width_0_height_0__pin_3_upper[0]), - .right_bottom_grid_pin_5_(grid_io_bottom_1_top_width_0_height_0__pin_5_upper[0]), - .right_bottom_grid_pin_7_(grid_io_bottom_1_top_width_0_height_0__pin_7_upper[0]), - .right_bottom_grid_pin_9_(grid_io_bottom_1_top_width_0_height_0__pin_9_upper[0]), - .right_bottom_grid_pin_11_(grid_io_bottom_1_top_width_0_height_0__pin_11_upper[0]), - .chanx_left_in(cbx_1__0__0_chanx_right_out[0:19]), - .left_bottom_grid_pin_1_(grid_io_bottom_0_top_width_0_height_0__pin_1_lower[0]), - .left_bottom_grid_pin_3_(grid_io_bottom_0_top_width_0_height_0__pin_3_lower[0]), - .left_bottom_grid_pin_5_(grid_io_bottom_0_top_width_0_height_0__pin_5_lower[0]), - .left_bottom_grid_pin_7_(grid_io_bottom_0_top_width_0_height_0__pin_7_lower[0]), - .left_bottom_grid_pin_9_(grid_io_bottom_0_top_width_0_height_0__pin_9_lower[0]), - .left_bottom_grid_pin_11_(grid_io_bottom_0_top_width_0_height_0__pin_11_lower[0]), - .ccff_head(grid_io_bottom_1_ccff_tail[0]), - .chany_top_out(sb_1__0__0_chany_top_out[0:19]), - .chanx_right_out(sb_1__0__0_chanx_right_out[0:19]), - .chanx_left_out(sb_1__0__0_chanx_left_out[0:19]), - .ccff_tail(sb_1__0__0_ccff_tail[0]) - ); - - - sb_1__1_ - sb_1__1_ - ( - .prog_clk(prog_clk[0]), - .chany_top_in(cby_1__1__1_chany_bottom_out[0:19]), - .top_left_grid_pin_42_(grid_clb_1_right_width_0_height_0__pin_42_lower[0]), - .top_left_grid_pin_43_(grid_clb_1_right_width_0_height_0__pin_43_lower[0]), - .top_left_grid_pin_44_(grid_clb_1_right_width_0_height_0__pin_44_lower[0]), - .top_left_grid_pin_45_(grid_clb_1_right_width_0_height_0__pin_45_lower[0]), - .top_left_grid_pin_46_(grid_clb_1_right_width_0_height_0__pin_46_lower[0]), - .top_left_grid_pin_47_(grid_clb_1_right_width_0_height_0__pin_47_lower[0]), - .top_left_grid_pin_48_(grid_clb_1_right_width_0_height_0__pin_48_lower[0]), - .top_left_grid_pin_49_(grid_clb_1_right_width_0_height_0__pin_49_lower[0]), - .chanx_right_in(cbx_1__1__1_chanx_left_out[0:19]), - .right_bottom_grid_pin_34_(grid_clb_2_top_width_0_height_0__pin_34_upper[0]), - .right_bottom_grid_pin_35_(grid_clb_2_top_width_0_height_0__pin_35_upper[0]), - .right_bottom_grid_pin_36_(grid_clb_2_top_width_0_height_0__pin_36_upper[0]), - .right_bottom_grid_pin_37_(grid_clb_2_top_width_0_height_0__pin_37_upper[0]), - .right_bottom_grid_pin_38_(grid_clb_2_top_width_0_height_0__pin_38_upper[0]), - .right_bottom_grid_pin_39_(grid_clb_2_top_width_0_height_0__pin_39_upper[0]), - .right_bottom_grid_pin_40_(grid_clb_2_top_width_0_height_0__pin_40_upper[0]), - .right_bottom_grid_pin_41_(grid_clb_2_top_width_0_height_0__pin_41_upper[0]), - .chany_bottom_in(cby_1__1__0_chany_top_out[0:19]), - .bottom_left_grid_pin_42_(grid_clb_0_right_width_0_height_0__pin_42_upper[0]), - .bottom_left_grid_pin_43_(grid_clb_0_right_width_0_height_0__pin_43_upper[0]), - .bottom_left_grid_pin_44_(grid_clb_0_right_width_0_height_0__pin_44_upper[0]), - .bottom_left_grid_pin_45_(grid_clb_0_right_width_0_height_0__pin_45_upper[0]), - .bottom_left_grid_pin_46_(grid_clb_0_right_width_0_height_0__pin_46_upper[0]), - .bottom_left_grid_pin_47_(grid_clb_0_right_width_0_height_0__pin_47_upper[0]), - .bottom_left_grid_pin_48_(grid_clb_0_right_width_0_height_0__pin_48_upper[0]), - .bottom_left_grid_pin_49_(grid_clb_0_right_width_0_height_0__pin_49_upper[0]), - .chanx_left_in(cbx_1__1__0_chanx_right_out[0:19]), - .left_bottom_grid_pin_34_(grid_clb_0_top_width_0_height_0__pin_34_lower[0]), - .left_bottom_grid_pin_35_(grid_clb_0_top_width_0_height_0__pin_35_lower[0]), - .left_bottom_grid_pin_36_(grid_clb_0_top_width_0_height_0__pin_36_lower[0]), - .left_bottom_grid_pin_37_(grid_clb_0_top_width_0_height_0__pin_37_lower[0]), - .left_bottom_grid_pin_38_(grid_clb_0_top_width_0_height_0__pin_38_lower[0]), - .left_bottom_grid_pin_39_(grid_clb_0_top_width_0_height_0__pin_39_lower[0]), - .left_bottom_grid_pin_40_(grid_clb_0_top_width_0_height_0__pin_40_lower[0]), - .left_bottom_grid_pin_41_(grid_clb_0_top_width_0_height_0__pin_41_lower[0]), - .ccff_head(cbx_1__1__1_ccff_tail[0]), - .chany_top_out(sb_1__1__0_chany_top_out[0:19]), - .chanx_right_out(sb_1__1__0_chanx_right_out[0:19]), - .chany_bottom_out(sb_1__1__0_chany_bottom_out[0:19]), - .chanx_left_out(sb_1__1__0_chanx_left_out[0:19]), - .ccff_tail(sb_1__1__0_ccff_tail[0]) - ); - - - sb_1__2_ - sb_1__2_ - ( - .prog_clk(prog_clk[0]), - .chanx_right_in(cbx_1__2__1_chanx_left_out[0:19]), - .right_top_grid_pin_1_(grid_io_top_1_bottom_width_0_height_0__pin_1_upper[0]), - .right_bottom_grid_pin_34_(grid_clb_3_top_width_0_height_0__pin_34_upper[0]), - .right_bottom_grid_pin_35_(grid_clb_3_top_width_0_height_0__pin_35_upper[0]), - .right_bottom_grid_pin_36_(grid_clb_3_top_width_0_height_0__pin_36_upper[0]), - .right_bottom_grid_pin_37_(grid_clb_3_top_width_0_height_0__pin_37_upper[0]), - .right_bottom_grid_pin_38_(grid_clb_3_top_width_0_height_0__pin_38_upper[0]), - .right_bottom_grid_pin_39_(grid_clb_3_top_width_0_height_0__pin_39_upper[0]), - .right_bottom_grid_pin_40_(grid_clb_3_top_width_0_height_0__pin_40_upper[0]), - .right_bottom_grid_pin_41_(grid_clb_3_top_width_0_height_0__pin_41_upper[0]), - .chany_bottom_in(cby_1__1__1_chany_top_out[0:19]), - .bottom_left_grid_pin_42_(grid_clb_1_right_width_0_height_0__pin_42_upper[0]), - .bottom_left_grid_pin_43_(grid_clb_1_right_width_0_height_0__pin_43_upper[0]), - .bottom_left_grid_pin_44_(grid_clb_1_right_width_0_height_0__pin_44_upper[0]), - .bottom_left_grid_pin_45_(grid_clb_1_right_width_0_height_0__pin_45_upper[0]), - .bottom_left_grid_pin_46_(grid_clb_1_right_width_0_height_0__pin_46_upper[0]), - .bottom_left_grid_pin_47_(grid_clb_1_right_width_0_height_0__pin_47_upper[0]), - .bottom_left_grid_pin_48_(grid_clb_1_right_width_0_height_0__pin_48_upper[0]), - .bottom_left_grid_pin_49_(grid_clb_1_right_width_0_height_0__pin_49_upper[0]), - .chanx_left_in(cbx_1__2__0_chanx_right_out[0:19]), - .left_top_grid_pin_1_(grid_io_top_0_bottom_width_0_height_0__pin_1_lower[0]), - .left_bottom_grid_pin_34_(grid_clb_1_top_width_0_height_0__pin_34_lower[0]), - .left_bottom_grid_pin_35_(grid_clb_1_top_width_0_height_0__pin_35_lower[0]), - .left_bottom_grid_pin_36_(grid_clb_1_top_width_0_height_0__pin_36_lower[0]), - .left_bottom_grid_pin_37_(grid_clb_1_top_width_0_height_0__pin_37_lower[0]), - .left_bottom_grid_pin_38_(grid_clb_1_top_width_0_height_0__pin_38_lower[0]), - .left_bottom_grid_pin_39_(grid_clb_1_top_width_0_height_0__pin_39_lower[0]), - .left_bottom_grid_pin_40_(grid_clb_1_top_width_0_height_0__pin_40_lower[0]), - .left_bottom_grid_pin_41_(grid_clb_1_top_width_0_height_0__pin_41_lower[0]), - .ccff_head(grid_io_top_1_ccff_tail[0]), - .chanx_right_out(sb_1__2__0_chanx_right_out[0:19]), - .chany_bottom_out(sb_1__2__0_chany_bottom_out[0:19]), - .chanx_left_out(sb_1__2__0_chanx_left_out[0:19]), - .ccff_tail(sb_1__2__0_ccff_tail[0]) - ); - - - sb_2__0_ - sb_2__0_ - ( - .prog_clk(prog_clk[0]), - .chany_top_in(cby_2__1__0_chany_bottom_out[0:19]), - .top_left_grid_pin_42_(grid_clb_2_right_width_0_height_0__pin_42_lower[0]), - .top_left_grid_pin_43_(grid_clb_2_right_width_0_height_0__pin_43_lower[0]), - .top_left_grid_pin_44_(grid_clb_2_right_width_0_height_0__pin_44_lower[0]), - .top_left_grid_pin_45_(grid_clb_2_right_width_0_height_0__pin_45_lower[0]), - .top_left_grid_pin_46_(grid_clb_2_right_width_0_height_0__pin_46_lower[0]), - .top_left_grid_pin_47_(grid_clb_2_right_width_0_height_0__pin_47_lower[0]), - .top_left_grid_pin_48_(grid_clb_2_right_width_0_height_0__pin_48_lower[0]), - .top_left_grid_pin_49_(grid_clb_2_right_width_0_height_0__pin_49_lower[0]), - .top_right_grid_pin_1_(grid_io_right_0_left_width_0_height_0__pin_1_lower[0]), - .chanx_left_in(cbx_1__0__1_chanx_right_out[0:19]), - .left_bottom_grid_pin_1_(grid_io_bottom_1_top_width_0_height_0__pin_1_lower[0]), - .left_bottom_grid_pin_3_(grid_io_bottom_1_top_width_0_height_0__pin_3_lower[0]), - .left_bottom_grid_pin_5_(grid_io_bottom_1_top_width_0_height_0__pin_5_lower[0]), - .left_bottom_grid_pin_7_(grid_io_bottom_1_top_width_0_height_0__pin_7_lower[0]), - .left_bottom_grid_pin_9_(grid_io_bottom_1_top_width_0_height_0__pin_9_lower[0]), - .left_bottom_grid_pin_11_(grid_io_bottom_1_top_width_0_height_0__pin_11_lower[0]), - .ccff_head(grid_io_right_0_ccff_tail[0]), - .chany_top_out(sb_2__0__0_chany_top_out[0:19]), - .chanx_left_out(sb_2__0__0_chanx_left_out[0:19]), - .ccff_tail(sb_2__0__0_ccff_tail[0]) - ); - - - sb_2__1_ - sb_2__1_ - ( - .prog_clk(prog_clk[0]), - .chany_top_in(cby_2__1__1_chany_bottom_out[0:19]), - .top_left_grid_pin_42_(grid_clb_3_right_width_0_height_0__pin_42_lower[0]), - .top_left_grid_pin_43_(grid_clb_3_right_width_0_height_0__pin_43_lower[0]), - .top_left_grid_pin_44_(grid_clb_3_right_width_0_height_0__pin_44_lower[0]), - .top_left_grid_pin_45_(grid_clb_3_right_width_0_height_0__pin_45_lower[0]), - .top_left_grid_pin_46_(grid_clb_3_right_width_0_height_0__pin_46_lower[0]), - .top_left_grid_pin_47_(grid_clb_3_right_width_0_height_0__pin_47_lower[0]), - .top_left_grid_pin_48_(grid_clb_3_right_width_0_height_0__pin_48_lower[0]), - .top_left_grid_pin_49_(grid_clb_3_right_width_0_height_0__pin_49_lower[0]), - .top_right_grid_pin_1_(grid_io_right_1_left_width_0_height_0__pin_1_lower[0]), - .chany_bottom_in(cby_2__1__0_chany_top_out[0:19]), - .bottom_right_grid_pin_1_(grid_io_right_0_left_width_0_height_0__pin_1_upper[0]), - .bottom_left_grid_pin_42_(grid_clb_2_right_width_0_height_0__pin_42_upper[0]), - .bottom_left_grid_pin_43_(grid_clb_2_right_width_0_height_0__pin_43_upper[0]), - .bottom_left_grid_pin_44_(grid_clb_2_right_width_0_height_0__pin_44_upper[0]), - .bottom_left_grid_pin_45_(grid_clb_2_right_width_0_height_0__pin_45_upper[0]), - .bottom_left_grid_pin_46_(grid_clb_2_right_width_0_height_0__pin_46_upper[0]), - .bottom_left_grid_pin_47_(grid_clb_2_right_width_0_height_0__pin_47_upper[0]), - .bottom_left_grid_pin_48_(grid_clb_2_right_width_0_height_0__pin_48_upper[0]), - .bottom_left_grid_pin_49_(grid_clb_2_right_width_0_height_0__pin_49_upper[0]), - .chanx_left_in(cbx_1__1__1_chanx_right_out[0:19]), - .left_bottom_grid_pin_34_(grid_clb_2_top_width_0_height_0__pin_34_lower[0]), - .left_bottom_grid_pin_35_(grid_clb_2_top_width_0_height_0__pin_35_lower[0]), - .left_bottom_grid_pin_36_(grid_clb_2_top_width_0_height_0__pin_36_lower[0]), - .left_bottom_grid_pin_37_(grid_clb_2_top_width_0_height_0__pin_37_lower[0]), - .left_bottom_grid_pin_38_(grid_clb_2_top_width_0_height_0__pin_38_lower[0]), - .left_bottom_grid_pin_39_(grid_clb_2_top_width_0_height_0__pin_39_lower[0]), - .left_bottom_grid_pin_40_(grid_clb_2_top_width_0_height_0__pin_40_lower[0]), - .left_bottom_grid_pin_41_(grid_clb_2_top_width_0_height_0__pin_41_lower[0]), - .ccff_head(grid_io_right_1_ccff_tail[0]), - .chany_top_out(sb_2__1__0_chany_top_out[0:19]), - .chany_bottom_out(sb_2__1__0_chany_bottom_out[0:19]), - .chanx_left_out(sb_2__1__0_chanx_left_out[0:19]), - .ccff_tail(sb_2__1__0_ccff_tail[0]) - ); - - - sb_2__2_ - sb_2__2_ - ( - .SC_OUT_TOP(sc_tail), - .SC_IN_TOP(scff_Wires[12]), - .prog_clk(prog_clk[0]), - .chany_bottom_in(cby_2__1__1_chany_top_out[0:19]), - .bottom_right_grid_pin_1_(grid_io_right_1_left_width_0_height_0__pin_1_upper[0]), - .bottom_left_grid_pin_42_(grid_clb_3_right_width_0_height_0__pin_42_upper[0]), - .bottom_left_grid_pin_43_(grid_clb_3_right_width_0_height_0__pin_43_upper[0]), - .bottom_left_grid_pin_44_(grid_clb_3_right_width_0_height_0__pin_44_upper[0]), - .bottom_left_grid_pin_45_(grid_clb_3_right_width_0_height_0__pin_45_upper[0]), - .bottom_left_grid_pin_46_(grid_clb_3_right_width_0_height_0__pin_46_upper[0]), - .bottom_left_grid_pin_47_(grid_clb_3_right_width_0_height_0__pin_47_upper[0]), - .bottom_left_grid_pin_48_(grid_clb_3_right_width_0_height_0__pin_48_upper[0]), - .bottom_left_grid_pin_49_(grid_clb_3_right_width_0_height_0__pin_49_upper[0]), - .chanx_left_in(cbx_1__2__1_chanx_right_out[0:19]), - .left_top_grid_pin_1_(grid_io_top_1_bottom_width_0_height_0__pin_1_lower[0]), - .left_bottom_grid_pin_34_(grid_clb_3_top_width_0_height_0__pin_34_lower[0]), - .left_bottom_grid_pin_35_(grid_clb_3_top_width_0_height_0__pin_35_lower[0]), - .left_bottom_grid_pin_36_(grid_clb_3_top_width_0_height_0__pin_36_lower[0]), - .left_bottom_grid_pin_37_(grid_clb_3_top_width_0_height_0__pin_37_lower[0]), - .left_bottom_grid_pin_38_(grid_clb_3_top_width_0_height_0__pin_38_lower[0]), - .left_bottom_grid_pin_39_(grid_clb_3_top_width_0_height_0__pin_39_lower[0]), - .left_bottom_grid_pin_40_(grid_clb_3_top_width_0_height_0__pin_40_lower[0]), - .left_bottom_grid_pin_41_(grid_clb_3_top_width_0_height_0__pin_41_lower[0]), - .ccff_head(ccff_head[0]), - .chany_bottom_out(sb_2__2__0_chany_bottom_out[0:19]), - .chanx_left_out(sb_2__2__0_chanx_left_out[0:19]), - .ccff_tail(sb_2__2__0_ccff_tail[0]) - ); - - - cbx_1__0_ - cbx_1__0_ - ( - .SC_OUT_BOT(scff_Wires[6]), - .SC_IN_TOP(scff_Wires[5]), - .top_width_0_height_0__pin_11_lower(grid_io_bottom_0_top_width_0_height_0__pin_11_lower[0]), - .top_width_0_height_0__pin_11_upper(grid_io_bottom_0_top_width_0_height_0__pin_11_upper[0]), - .top_width_0_height_0__pin_9_lower(grid_io_bottom_0_top_width_0_height_0__pin_9_lower[0]), - .top_width_0_height_0__pin_9_upper(grid_io_bottom_0_top_width_0_height_0__pin_9_upper[0]), - .top_width_0_height_0__pin_7_lower(grid_io_bottom_0_top_width_0_height_0__pin_7_lower[0]), - .top_width_0_height_0__pin_7_upper(grid_io_bottom_0_top_width_0_height_0__pin_7_upper[0]), - .top_width_0_height_0__pin_5_lower(grid_io_bottom_0_top_width_0_height_0__pin_5_lower[0]), - .top_width_0_height_0__pin_5_upper(grid_io_bottom_0_top_width_0_height_0__pin_5_upper[0]), - .top_width_0_height_0__pin_3_lower(grid_io_bottom_0_top_width_0_height_0__pin_3_lower[0]), - .top_width_0_height_0__pin_3_upper(grid_io_bottom_0_top_width_0_height_0__pin_3_upper[0]), - .top_width_0_height_0__pin_1_lower(grid_io_bottom_0_top_width_0_height_0__pin_1_lower[0]), - .top_width_0_height_0__pin_1_upper(grid_io_bottom_0_top_width_0_height_0__pin_1_upper[0]), - .top_width_0_height_0__pin_10_(cbx_1__0__0_bottom_grid_pin_10_[0]), - .top_width_0_height_0__pin_8_(cbx_1__0__0_bottom_grid_pin_8_[0]), - .top_width_0_height_0__pin_6_(cbx_1__0__0_bottom_grid_pin_6_[0]), - .top_width_0_height_0__pin_4_(cbx_1__0__0_bottom_grid_pin_4_[0]), - .top_width_0_height_0__pin_2_(cbx_1__0__0_bottom_grid_pin_2_[0]), - .top_width_0_height_0__pin_0_(cbx_1__0__0_bottom_grid_pin_0_[0]), - .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[4:9]), - .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[4:9]), - .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[4:9]), - .prog_clk(prog_clk[0]), - .chanx_left_in(sb_0__0__0_chanx_right_out[0:19]), - .chanx_right_in(sb_1__0__0_chanx_left_out[0:19]), - .ccff_head(sb_1__0__0_ccff_tail[0]), - .chanx_left_out(cbx_1__0__0_chanx_left_out[0:19]), - .chanx_right_out(cbx_1__0__0_chanx_right_out[0:19]), - .bottom_grid_pin_0_(cbx_1__0__0_bottom_grid_pin_0_[0]), - .bottom_grid_pin_2_(cbx_1__0__0_bottom_grid_pin_2_[0]), - .bottom_grid_pin_4_(cbx_1__0__0_bottom_grid_pin_4_[0]), - .bottom_grid_pin_6_(cbx_1__0__0_bottom_grid_pin_6_[0]), - .bottom_grid_pin_8_(cbx_1__0__0_bottom_grid_pin_8_[0]), - .bottom_grid_pin_10_(cbx_1__0__0_bottom_grid_pin_10_[0]), - .ccff_tail(grid_io_bottom_0_ccff_tail[0]) - ); - - - cbx_1__0_ - cbx_2__0_ - ( - .SC_OUT_TOP(scff_Wires[8]), - .SC_IN_TOP(scff_Wires[7]), - .top_width_0_height_0__pin_11_lower(grid_io_bottom_1_top_width_0_height_0__pin_11_lower[0]), - .top_width_0_height_0__pin_11_upper(grid_io_bottom_1_top_width_0_height_0__pin_11_upper[0]), - .top_width_0_height_0__pin_9_lower(grid_io_bottom_1_top_width_0_height_0__pin_9_lower[0]), - .top_width_0_height_0__pin_9_upper(grid_io_bottom_1_top_width_0_height_0__pin_9_upper[0]), - .top_width_0_height_0__pin_7_lower(grid_io_bottom_1_top_width_0_height_0__pin_7_lower[0]), - .top_width_0_height_0__pin_7_upper(grid_io_bottom_1_top_width_0_height_0__pin_7_upper[0]), - .top_width_0_height_0__pin_5_lower(grid_io_bottom_1_top_width_0_height_0__pin_5_lower[0]), - .top_width_0_height_0__pin_5_upper(grid_io_bottom_1_top_width_0_height_0__pin_5_upper[0]), - .top_width_0_height_0__pin_3_lower(grid_io_bottom_1_top_width_0_height_0__pin_3_lower[0]), - .top_width_0_height_0__pin_3_upper(grid_io_bottom_1_top_width_0_height_0__pin_3_upper[0]), - .top_width_0_height_0__pin_1_lower(grid_io_bottom_1_top_width_0_height_0__pin_1_lower[0]), - .top_width_0_height_0__pin_1_upper(grid_io_bottom_1_top_width_0_height_0__pin_1_upper[0]), - .top_width_0_height_0__pin_10_(cbx_1__0__1_bottom_grid_pin_10_[0]), - .top_width_0_height_0__pin_8_(cbx_1__0__1_bottom_grid_pin_8_[0]), - .top_width_0_height_0__pin_6_(cbx_1__0__1_bottom_grid_pin_6_[0]), - .top_width_0_height_0__pin_4_(cbx_1__0__1_bottom_grid_pin_4_[0]), - .top_width_0_height_0__pin_2_(cbx_1__0__1_bottom_grid_pin_2_[0]), - .top_width_0_height_0__pin_0_(cbx_1__0__1_bottom_grid_pin_0_[0]), - .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[10:15]), - .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[10:15]), - .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[10:15]), - .prog_clk(prog_clk[0]), - .chanx_left_in(sb_1__0__0_chanx_right_out[0:19]), - .chanx_right_in(sb_2__0__0_chanx_left_out[0:19]), - .ccff_head(sb_2__0__0_ccff_tail[0]), - .chanx_left_out(cbx_1__0__1_chanx_left_out[0:19]), - .chanx_right_out(cbx_1__0__1_chanx_right_out[0:19]), - .bottom_grid_pin_0_(cbx_1__0__1_bottom_grid_pin_0_[0]), - .bottom_grid_pin_2_(cbx_1__0__1_bottom_grid_pin_2_[0]), - .bottom_grid_pin_4_(cbx_1__0__1_bottom_grid_pin_4_[0]), - .bottom_grid_pin_6_(cbx_1__0__1_bottom_grid_pin_6_[0]), - .bottom_grid_pin_8_(cbx_1__0__1_bottom_grid_pin_8_[0]), - .bottom_grid_pin_10_(cbx_1__0__1_bottom_grid_pin_10_[0]), - .ccff_tail(grid_io_bottom_1_ccff_tail[0]) - ); - - - cbx_1__1_ - cbx_1__1_ - ( - .SC_OUT_BOT(scff_Wires[3]), - .SC_IN_TOP(scff_Wires[2]), - .prog_clk(prog_clk[0]), - .chanx_left_in(sb_0__1__0_chanx_right_out[0:19]), - .chanx_right_in(sb_1__1__0_chanx_left_out[0:19]), - .ccff_head(sb_1__1__0_ccff_tail[0]), - .chanx_left_out(cbx_1__1__0_chanx_left_out[0:19]), - .chanx_right_out(cbx_1__1__0_chanx_right_out[0:19]), - .bottom_grid_pin_0_(cbx_1__1__0_bottom_grid_pin_0_[0]), - .bottom_grid_pin_1_(cbx_1__1__0_bottom_grid_pin_1_[0]), - .bottom_grid_pin_2_(cbx_1__1__0_bottom_grid_pin_2_[0]), - .bottom_grid_pin_3_(cbx_1__1__0_bottom_grid_pin_3_[0]), - .bottom_grid_pin_4_(cbx_1__1__0_bottom_grid_pin_4_[0]), - .bottom_grid_pin_5_(cbx_1__1__0_bottom_grid_pin_5_[0]), - .bottom_grid_pin_6_(cbx_1__1__0_bottom_grid_pin_6_[0]), - .bottom_grid_pin_7_(cbx_1__1__0_bottom_grid_pin_7_[0]), - .bottom_grid_pin_8_(cbx_1__1__0_bottom_grid_pin_8_[0]), - .bottom_grid_pin_9_(cbx_1__1__0_bottom_grid_pin_9_[0]), - .bottom_grid_pin_10_(cbx_1__1__0_bottom_grid_pin_10_[0]), - .bottom_grid_pin_11_(cbx_1__1__0_bottom_grid_pin_11_[0]), - .bottom_grid_pin_12_(cbx_1__1__0_bottom_grid_pin_12_[0]), - .bottom_grid_pin_13_(cbx_1__1__0_bottom_grid_pin_13_[0]), - .bottom_grid_pin_14_(cbx_1__1__0_bottom_grid_pin_14_[0]), - .bottom_grid_pin_15_(cbx_1__1__0_bottom_grid_pin_15_[0]), - .ccff_tail(cbx_1__1__0_ccff_tail[0]) - ); - - - cbx_1__1_ - cbx_2__1_ - ( - .SC_OUT_TOP(scff_Wires[10]), - .SC_IN_BOT(scff_Wires[9]), - .prog_clk(prog_clk[0]), - .chanx_left_in(sb_1__1__0_chanx_right_out[0:19]), - .chanx_right_in(sb_2__1__0_chanx_left_out[0:19]), - .ccff_head(sb_2__1__0_ccff_tail[0]), - .chanx_left_out(cbx_1__1__1_chanx_left_out[0:19]), - .chanx_right_out(cbx_1__1__1_chanx_right_out[0:19]), - .bottom_grid_pin_0_(cbx_1__1__1_bottom_grid_pin_0_[0]), - .bottom_grid_pin_1_(cbx_1__1__1_bottom_grid_pin_1_[0]), - .bottom_grid_pin_2_(cbx_1__1__1_bottom_grid_pin_2_[0]), - .bottom_grid_pin_3_(cbx_1__1__1_bottom_grid_pin_3_[0]), - .bottom_grid_pin_4_(cbx_1__1__1_bottom_grid_pin_4_[0]), - .bottom_grid_pin_5_(cbx_1__1__1_bottom_grid_pin_5_[0]), - .bottom_grid_pin_6_(cbx_1__1__1_bottom_grid_pin_6_[0]), - .bottom_grid_pin_7_(cbx_1__1__1_bottom_grid_pin_7_[0]), - .bottom_grid_pin_8_(cbx_1__1__1_bottom_grid_pin_8_[0]), - .bottom_grid_pin_9_(cbx_1__1__1_bottom_grid_pin_9_[0]), - .bottom_grid_pin_10_(cbx_1__1__1_bottom_grid_pin_10_[0]), - .bottom_grid_pin_11_(cbx_1__1__1_bottom_grid_pin_11_[0]), - .bottom_grid_pin_12_(cbx_1__1__1_bottom_grid_pin_12_[0]), - .bottom_grid_pin_13_(cbx_1__1__1_bottom_grid_pin_13_[0]), - .bottom_grid_pin_14_(cbx_1__1__1_bottom_grid_pin_14_[0]), - .bottom_grid_pin_15_(cbx_1__1__1_bottom_grid_pin_15_[0]), - .ccff_tail(cbx_1__1__1_ccff_tail[0]) - ); - - - cbx_1__2_ - cbx_1__2_ - ( - .SC_OUT_BOT(scff_Wires[1]), - .SC_IN_TOP(scff_Wires[0]), - .bottom_width_0_height_0__pin_1_lower(grid_io_top_0_bottom_width_0_height_0__pin_1_lower[0]), - .bottom_width_0_height_0__pin_1_upper(grid_io_top_0_bottom_width_0_height_0__pin_1_upper[0]), - .bottom_width_0_height_0__pin_0_(cbx_1__2__0_top_grid_pin_0_[0]), - .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[0]), - .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[0]), - .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[0]), - .prog_clk(prog_clk[0]), - .chanx_left_in(sb_0__2__0_chanx_right_out[0:19]), - .chanx_right_in(sb_1__2__0_chanx_left_out[0:19]), - .ccff_head(sb_1__2__0_ccff_tail[0]), - .chanx_left_out(cbx_1__2__0_chanx_left_out[0:19]), - .chanx_right_out(cbx_1__2__0_chanx_right_out[0:19]), - .top_grid_pin_0_(cbx_1__2__0_top_grid_pin_0_[0]), - .bottom_grid_pin_0_(cbx_1__2__0_bottom_grid_pin_0_[0]), - .bottom_grid_pin_1_(cbx_1__2__0_bottom_grid_pin_1_[0]), - .bottom_grid_pin_2_(cbx_1__2__0_bottom_grid_pin_2_[0]), - .bottom_grid_pin_3_(cbx_1__2__0_bottom_grid_pin_3_[0]), - .bottom_grid_pin_4_(cbx_1__2__0_bottom_grid_pin_4_[0]), - .bottom_grid_pin_5_(cbx_1__2__0_bottom_grid_pin_5_[0]), - .bottom_grid_pin_6_(cbx_1__2__0_bottom_grid_pin_6_[0]), - .bottom_grid_pin_7_(cbx_1__2__0_bottom_grid_pin_7_[0]), - .bottom_grid_pin_8_(cbx_1__2__0_bottom_grid_pin_8_[0]), - .bottom_grid_pin_9_(cbx_1__2__0_bottom_grid_pin_9_[0]), - .bottom_grid_pin_10_(cbx_1__2__0_bottom_grid_pin_10_[0]), - .bottom_grid_pin_11_(cbx_1__2__0_bottom_grid_pin_11_[0]), - .bottom_grid_pin_12_(cbx_1__2__0_bottom_grid_pin_12_[0]), - .bottom_grid_pin_13_(cbx_1__2__0_bottom_grid_pin_13_[0]), - .bottom_grid_pin_14_(cbx_1__2__0_bottom_grid_pin_14_[0]), - .bottom_grid_pin_15_(cbx_1__2__0_bottom_grid_pin_15_[0]), - .ccff_tail(grid_io_top_0_ccff_tail[0]) - ); - - - cbx_1__2_ - cbx_2__2_ - ( - .SC_OUT_BOT(scff_Wires[12]), - .SC_IN_BOT(scff_Wires[11]), - .bottom_width_0_height_0__pin_1_lower(grid_io_top_1_bottom_width_0_height_0__pin_1_lower[0]), - .bottom_width_0_height_0__pin_1_upper(grid_io_top_1_bottom_width_0_height_0__pin_1_upper[0]), - .bottom_width_0_height_0__pin_0_(cbx_1__2__1_top_grid_pin_0_[0]), - .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[1]), - .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[1]), - .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[1]), - .prog_clk(prog_clk[0]), - .chanx_left_in(sb_1__2__0_chanx_right_out[0:19]), - .chanx_right_in(sb_2__2__0_chanx_left_out[0:19]), - .ccff_head(sb_2__2__0_ccff_tail[0]), - .chanx_left_out(cbx_1__2__1_chanx_left_out[0:19]), - .chanx_right_out(cbx_1__2__1_chanx_right_out[0:19]), - .top_grid_pin_0_(cbx_1__2__1_top_grid_pin_0_[0]), - .bottom_grid_pin_0_(cbx_1__2__1_bottom_grid_pin_0_[0]), - .bottom_grid_pin_1_(cbx_1__2__1_bottom_grid_pin_1_[0]), - .bottom_grid_pin_2_(cbx_1__2__1_bottom_grid_pin_2_[0]), - .bottom_grid_pin_3_(cbx_1__2__1_bottom_grid_pin_3_[0]), - .bottom_grid_pin_4_(cbx_1__2__1_bottom_grid_pin_4_[0]), - .bottom_grid_pin_5_(cbx_1__2__1_bottom_grid_pin_5_[0]), - .bottom_grid_pin_6_(cbx_1__2__1_bottom_grid_pin_6_[0]), - .bottom_grid_pin_7_(cbx_1__2__1_bottom_grid_pin_7_[0]), - .bottom_grid_pin_8_(cbx_1__2__1_bottom_grid_pin_8_[0]), - .bottom_grid_pin_9_(cbx_1__2__1_bottom_grid_pin_9_[0]), - .bottom_grid_pin_10_(cbx_1__2__1_bottom_grid_pin_10_[0]), - .bottom_grid_pin_11_(cbx_1__2__1_bottom_grid_pin_11_[0]), - .bottom_grid_pin_12_(cbx_1__2__1_bottom_grid_pin_12_[0]), - .bottom_grid_pin_13_(cbx_1__2__1_bottom_grid_pin_13_[0]), - .bottom_grid_pin_14_(cbx_1__2__1_bottom_grid_pin_14_[0]), - .bottom_grid_pin_15_(cbx_1__2__1_bottom_grid_pin_15_[0]), - .ccff_tail(grid_io_top_1_ccff_tail[0]) - ); - - - cby_0__1_ - cby_0__1_ - ( - .right_width_0_height_0__pin_1_lower(grid_io_left_0_right_width_0_height_0__pin_1_lower[0]), - .right_width_0_height_0__pin_1_upper(grid_io_left_0_right_width_0_height_0__pin_1_upper[0]), - .right_width_0_height_0__pin_0_(cby_0__1__0_left_grid_pin_0_[0]), - .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[16]), - .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[16]), - .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[16]), - .prog_clk(prog_clk[0]), - .chany_bottom_in(sb_0__0__0_chany_top_out[0:19]), - .chany_top_in(sb_0__1__0_chany_bottom_out[0:19]), - .ccff_head(sb_0__1__0_ccff_tail[0]), - .chany_bottom_out(cby_0__1__0_chany_bottom_out[0:19]), - .chany_top_out(cby_0__1__0_chany_top_out[0:19]), - .left_grid_pin_0_(cby_0__1__0_left_grid_pin_0_[0]), - .ccff_tail(grid_io_left_0_ccff_tail[0]) - ); - - - cby_0__1_ - cby_0__2_ - ( - .right_width_0_height_0__pin_1_lower(grid_io_left_1_right_width_0_height_0__pin_1_lower[0]), - .right_width_0_height_0__pin_1_upper(grid_io_left_1_right_width_0_height_0__pin_1_upper[0]), - .right_width_0_height_0__pin_0_(cby_0__1__1_left_grid_pin_0_[0]), - .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[17]), - .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[17]), - .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[17]), - .prog_clk(prog_clk[0]), - .chany_bottom_in(sb_0__1__0_chany_top_out[0:19]), - .chany_top_in(sb_0__2__0_chany_bottom_out[0:19]), - .ccff_head(sb_0__2__0_ccff_tail[0]), - .chany_bottom_out(cby_0__1__1_chany_bottom_out[0:19]), - .chany_top_out(cby_0__1__1_chany_top_out[0:19]), - .left_grid_pin_0_(cby_0__1__1_left_grid_pin_0_[0]), - .ccff_tail(grid_io_left_1_ccff_tail[0]) - ); - - - cby_1__1_ - cby_1__1_ - ( - .prog_clk(prog_clk[0]), - .chany_bottom_in(sb_1__0__0_chany_top_out[0:19]), - .chany_top_in(sb_1__1__0_chany_bottom_out[0:19]), - .ccff_head(grid_clb_0_ccff_tail[0]), - .chany_bottom_out(cby_1__1__0_chany_bottom_out[0:19]), - .chany_top_out(cby_1__1__0_chany_top_out[0:19]), - .left_grid_pin_16_(cby_1__1__0_left_grid_pin_16_[0]), - .left_grid_pin_17_(cby_1__1__0_left_grid_pin_17_[0]), - .left_grid_pin_18_(cby_1__1__0_left_grid_pin_18_[0]), - .left_grid_pin_19_(cby_1__1__0_left_grid_pin_19_[0]), - .left_grid_pin_20_(cby_1__1__0_left_grid_pin_20_[0]), - .left_grid_pin_21_(cby_1__1__0_left_grid_pin_21_[0]), - .left_grid_pin_22_(cby_1__1__0_left_grid_pin_22_[0]), - .left_grid_pin_23_(cby_1__1__0_left_grid_pin_23_[0]), - .left_grid_pin_24_(cby_1__1__0_left_grid_pin_24_[0]), - .left_grid_pin_25_(cby_1__1__0_left_grid_pin_25_[0]), - .left_grid_pin_26_(cby_1__1__0_left_grid_pin_26_[0]), - .left_grid_pin_27_(cby_1__1__0_left_grid_pin_27_[0]), - .left_grid_pin_28_(cby_1__1__0_left_grid_pin_28_[0]), - .left_grid_pin_29_(cby_1__1__0_left_grid_pin_29_[0]), - .left_grid_pin_30_(cby_1__1__0_left_grid_pin_30_[0]), - .left_grid_pin_31_(cby_1__1__0_left_grid_pin_31_[0]), - .ccff_tail(cby_1__1__0_ccff_tail[0]) - ); - - - cby_1__1_ - cby_1__2_ - ( - .prog_clk(prog_clk[0]), - .chany_bottom_in(sb_1__1__0_chany_top_out[0:19]), - .chany_top_in(sb_1__2__0_chany_bottom_out[0:19]), - .ccff_head(grid_clb_1_ccff_tail[0]), - .chany_bottom_out(cby_1__1__1_chany_bottom_out[0:19]), - .chany_top_out(cby_1__1__1_chany_top_out[0:19]), - .left_grid_pin_16_(cby_1__1__1_left_grid_pin_16_[0]), - .left_grid_pin_17_(cby_1__1__1_left_grid_pin_17_[0]), - .left_grid_pin_18_(cby_1__1__1_left_grid_pin_18_[0]), - .left_grid_pin_19_(cby_1__1__1_left_grid_pin_19_[0]), - .left_grid_pin_20_(cby_1__1__1_left_grid_pin_20_[0]), - .left_grid_pin_21_(cby_1__1__1_left_grid_pin_21_[0]), - .left_grid_pin_22_(cby_1__1__1_left_grid_pin_22_[0]), - .left_grid_pin_23_(cby_1__1__1_left_grid_pin_23_[0]), - .left_grid_pin_24_(cby_1__1__1_left_grid_pin_24_[0]), - .left_grid_pin_25_(cby_1__1__1_left_grid_pin_25_[0]), - .left_grid_pin_26_(cby_1__1__1_left_grid_pin_26_[0]), - .left_grid_pin_27_(cby_1__1__1_left_grid_pin_27_[0]), - .left_grid_pin_28_(cby_1__1__1_left_grid_pin_28_[0]), - .left_grid_pin_29_(cby_1__1__1_left_grid_pin_29_[0]), - .left_grid_pin_30_(cby_1__1__1_left_grid_pin_30_[0]), - .left_grid_pin_31_(cby_1__1__1_left_grid_pin_31_[0]), - .ccff_tail(cby_1__1__1_ccff_tail[0]) - ); - - - cby_2__1_ - cby_2__1_ - ( - .left_width_0_height_0__pin_1_lower(grid_io_right_0_left_width_0_height_0__pin_1_lower[0]), - .left_width_0_height_0__pin_1_upper(grid_io_right_0_left_width_0_height_0__pin_1_upper[0]), - .left_width_0_height_0__pin_0_(cby_2__1__0_right_grid_pin_0_[0]), - .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[2]), - .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[2]), - .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[2]), - .prog_clk(prog_clk[0]), - .chany_bottom_in(sb_2__0__0_chany_top_out[0:19]), - .chany_top_in(sb_2__1__0_chany_bottom_out[0:19]), - .ccff_head(grid_clb_2_ccff_tail[0]), - .chany_bottom_out(cby_2__1__0_chany_bottom_out[0:19]), - .chany_top_out(cby_2__1__0_chany_top_out[0:19]), - .right_grid_pin_0_(cby_2__1__0_right_grid_pin_0_[0]), - .left_grid_pin_16_(cby_2__1__0_left_grid_pin_16_[0]), - .left_grid_pin_17_(cby_2__1__0_left_grid_pin_17_[0]), - .left_grid_pin_18_(cby_2__1__0_left_grid_pin_18_[0]), - .left_grid_pin_19_(cby_2__1__0_left_grid_pin_19_[0]), - .left_grid_pin_20_(cby_2__1__0_left_grid_pin_20_[0]), - .left_grid_pin_21_(cby_2__1__0_left_grid_pin_21_[0]), - .left_grid_pin_22_(cby_2__1__0_left_grid_pin_22_[0]), - .left_grid_pin_23_(cby_2__1__0_left_grid_pin_23_[0]), - .left_grid_pin_24_(cby_2__1__0_left_grid_pin_24_[0]), - .left_grid_pin_25_(cby_2__1__0_left_grid_pin_25_[0]), - .left_grid_pin_26_(cby_2__1__0_left_grid_pin_26_[0]), - .left_grid_pin_27_(cby_2__1__0_left_grid_pin_27_[0]), - .left_grid_pin_28_(cby_2__1__0_left_grid_pin_28_[0]), - .left_grid_pin_29_(cby_2__1__0_left_grid_pin_29_[0]), - .left_grid_pin_30_(cby_2__1__0_left_grid_pin_30_[0]), - .left_grid_pin_31_(cby_2__1__0_left_grid_pin_31_[0]), - .ccff_tail(grid_io_right_0_ccff_tail[0]) - ); - - - cby_2__1_ - cby_2__2_ - ( - .left_width_0_height_0__pin_1_lower(grid_io_right_1_left_width_0_height_0__pin_1_lower[0]), - .left_width_0_height_0__pin_1_upper(grid_io_right_1_left_width_0_height_0__pin_1_upper[0]), - .left_width_0_height_0__pin_0_(cby_2__1__1_right_grid_pin_0_[0]), - .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[3]), - .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[3]), - .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[3]), - .prog_clk(prog_clk[0]), - .chany_bottom_in(sb_2__1__0_chany_top_out[0:19]), - .chany_top_in(sb_2__2__0_chany_bottom_out[0:19]), - .ccff_head(grid_clb_3_ccff_tail[0]), - .chany_bottom_out(cby_2__1__1_chany_bottom_out[0:19]), - .chany_top_out(cby_2__1__1_chany_top_out[0:19]), - .right_grid_pin_0_(cby_2__1__1_right_grid_pin_0_[0]), - .left_grid_pin_16_(cby_2__1__1_left_grid_pin_16_[0]), - .left_grid_pin_17_(cby_2__1__1_left_grid_pin_17_[0]), - .left_grid_pin_18_(cby_2__1__1_left_grid_pin_18_[0]), - .left_grid_pin_19_(cby_2__1__1_left_grid_pin_19_[0]), - .left_grid_pin_20_(cby_2__1__1_left_grid_pin_20_[0]), - .left_grid_pin_21_(cby_2__1__1_left_grid_pin_21_[0]), - .left_grid_pin_22_(cby_2__1__1_left_grid_pin_22_[0]), - .left_grid_pin_23_(cby_2__1__1_left_grid_pin_23_[0]), - .left_grid_pin_24_(cby_2__1__1_left_grid_pin_24_[0]), - .left_grid_pin_25_(cby_2__1__1_left_grid_pin_25_[0]), - .left_grid_pin_26_(cby_2__1__1_left_grid_pin_26_[0]), - .left_grid_pin_27_(cby_2__1__1_left_grid_pin_27_[0]), - .left_grid_pin_28_(cby_2__1__1_left_grid_pin_28_[0]), - .left_grid_pin_29_(cby_2__1__1_left_grid_pin_29_[0]), - .left_grid_pin_30_(cby_2__1__1_left_grid_pin_30_[0]), - .left_grid_pin_31_(cby_2__1__1_left_grid_pin_31_[0]), - .ccff_tail(grid_io_right_1_ccff_tail[0]) - ); - - - direct_interc - direct_interc_0_ - ( - .in(grid_clb_1_bottom_width_0_height_0__pin_50_[0]), - .out(direct_interc_0_out[0]) - ); - - - direct_interc - direct_interc_1_ - ( - .in(grid_clb_3_bottom_width_0_height_0__pin_50_[0]), - .out(direct_interc_1_out[0]) - ); - - - direct_interc - direct_interc_2_ - ( - .in(grid_clb_0_bottom_width_0_height_0__pin_50_[0]), - .out(direct_interc_2_out[0]) - ); - - - direct_interc - direct_interc_3_ - ( - .in(grid_clb_1_bottom_width_0_height_0__pin_51_[0]), - .out(direct_interc_3_out[0]) - ); - - - direct_interc - direct_interc_4_ - ( - .in(grid_clb_3_bottom_width_0_height_0__pin_51_[0]), - .out(direct_interc_4_out[0]) - ); - - - direct_interc - direct_interc_5_ - ( - .in(grid_clb_0_bottom_width_0_height_0__pin_51_[0]), - .out(direct_interc_5_out[0]) - ); - - -endmodule - diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/fpga_defines.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/fpga_defines.v deleted file mode 100644 index 48f3ef2..0000000 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/fpga_defines.v +++ /dev/null @@ -1,16 +0,0 @@ -// -// -// -// -// -// -// -// -`timescale 1ns / 1ps - -`define ENABLE_TIMING 1 - -`define ENABLE_SIGNAL_INITIALIZATION 1 - -`define ICARUS_SIMULATOR 1 - diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/fpga_top.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/fpga_top.v deleted file mode 100644 index b283491..0000000 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/fpga_top.v +++ /dev/null @@ -1,1422 +0,0 @@ -// -// -// -// -// -// -// -// -`timescale 1ns / 1ps - -// -module fpga_top(prog_clk, - Test_en, - clk, - gfpga_pad_EMBEDDED_IO_SOC_IN, - gfpga_pad_EMBEDDED_IO_SOC_OUT, - gfpga_pad_EMBEDDED_IO_SOC_DIR, - ccff_head, - ccff_tail); -// -input [0:0] prog_clk; -// -input [0:0] Test_en; -// -input [0:0] clk; -// -input [0:17] gfpga_pad_EMBEDDED_IO_SOC_IN; -// -output [0:17] gfpga_pad_EMBEDDED_IO_SOC_OUT; -// -output [0:17] gfpga_pad_EMBEDDED_IO_SOC_DIR; -// -input [0:0] ccff_head; -// -output [0:0] ccff_tail; - -// -// - - -// -// - - -wire [0:0] cbx_1__0__0_bottom_grid_pin_0_; -wire [0:0] cbx_1__0__0_bottom_grid_pin_10_; -wire [0:0] cbx_1__0__0_bottom_grid_pin_2_; -wire [0:0] cbx_1__0__0_bottom_grid_pin_4_; -wire [0:0] cbx_1__0__0_bottom_grid_pin_6_; -wire [0:0] cbx_1__0__0_bottom_grid_pin_8_; -wire [0:0] cbx_1__0__0_ccff_tail; -wire [0:19] cbx_1__0__0_chanx_left_out; -wire [0:19] cbx_1__0__0_chanx_right_out; -wire [0:0] cbx_1__0__1_bottom_grid_pin_0_; -wire [0:0] cbx_1__0__1_bottom_grid_pin_10_; -wire [0:0] cbx_1__0__1_bottom_grid_pin_2_; -wire [0:0] cbx_1__0__1_bottom_grid_pin_4_; -wire [0:0] cbx_1__0__1_bottom_grid_pin_6_; -wire [0:0] cbx_1__0__1_bottom_grid_pin_8_; -wire [0:0] cbx_1__0__1_ccff_tail; -wire [0:19] cbx_1__0__1_chanx_left_out; -wire [0:19] cbx_1__0__1_chanx_right_out; -wire [0:0] cbx_1__1__0_bottom_grid_pin_0_; -wire [0:0] cbx_1__1__0_bottom_grid_pin_10_; -wire [0:0] cbx_1__1__0_bottom_grid_pin_11_; -wire [0:0] cbx_1__1__0_bottom_grid_pin_12_; -wire [0:0] cbx_1__1__0_bottom_grid_pin_13_; -wire [0:0] cbx_1__1__0_bottom_grid_pin_14_; -wire [0:0] cbx_1__1__0_bottom_grid_pin_15_; -wire [0:0] cbx_1__1__0_bottom_grid_pin_1_; -wire [0:0] cbx_1__1__0_bottom_grid_pin_2_; -wire [0:0] cbx_1__1__0_bottom_grid_pin_3_; -wire [0:0] cbx_1__1__0_bottom_grid_pin_4_; -wire [0:0] cbx_1__1__0_bottom_grid_pin_5_; -wire [0:0] cbx_1__1__0_bottom_grid_pin_6_; -wire [0:0] cbx_1__1__0_bottom_grid_pin_7_; -wire [0:0] cbx_1__1__0_bottom_grid_pin_8_; -wire [0:0] cbx_1__1__0_bottom_grid_pin_9_; -wire [0:0] cbx_1__1__0_ccff_tail; -wire [0:19] cbx_1__1__0_chanx_left_out; -wire [0:19] cbx_1__1__0_chanx_right_out; -wire [0:0] cbx_1__1__1_bottom_grid_pin_0_; -wire [0:0] cbx_1__1__1_bottom_grid_pin_10_; -wire [0:0] cbx_1__1__1_bottom_grid_pin_11_; -wire [0:0] cbx_1__1__1_bottom_grid_pin_12_; -wire [0:0] cbx_1__1__1_bottom_grid_pin_13_; -wire [0:0] cbx_1__1__1_bottom_grid_pin_14_; -wire [0:0] cbx_1__1__1_bottom_grid_pin_15_; -wire [0:0] cbx_1__1__1_bottom_grid_pin_1_; -wire [0:0] cbx_1__1__1_bottom_grid_pin_2_; -wire [0:0] cbx_1__1__1_bottom_grid_pin_3_; -wire [0:0] cbx_1__1__1_bottom_grid_pin_4_; -wire [0:0] cbx_1__1__1_bottom_grid_pin_5_; -wire [0:0] cbx_1__1__1_bottom_grid_pin_6_; -wire [0:0] cbx_1__1__1_bottom_grid_pin_7_; -wire [0:0] cbx_1__1__1_bottom_grid_pin_8_; -wire [0:0] cbx_1__1__1_bottom_grid_pin_9_; -wire [0:0] cbx_1__1__1_ccff_tail; -wire [0:19] cbx_1__1__1_chanx_left_out; -wire [0:19] cbx_1__1__1_chanx_right_out; -wire [0:0] cbx_1__2__0_bottom_grid_pin_0_; -wire [0:0] cbx_1__2__0_bottom_grid_pin_10_; -wire [0:0] cbx_1__2__0_bottom_grid_pin_11_; -wire [0:0] cbx_1__2__0_bottom_grid_pin_12_; -wire [0:0] cbx_1__2__0_bottom_grid_pin_13_; -wire [0:0] cbx_1__2__0_bottom_grid_pin_14_; -wire [0:0] cbx_1__2__0_bottom_grid_pin_15_; -wire [0:0] cbx_1__2__0_bottom_grid_pin_1_; -wire [0:0] cbx_1__2__0_bottom_grid_pin_2_; -wire [0:0] cbx_1__2__0_bottom_grid_pin_3_; -wire [0:0] cbx_1__2__0_bottom_grid_pin_4_; -wire [0:0] cbx_1__2__0_bottom_grid_pin_5_; -wire [0:0] cbx_1__2__0_bottom_grid_pin_6_; -wire [0:0] cbx_1__2__0_bottom_grid_pin_7_; -wire [0:0] cbx_1__2__0_bottom_grid_pin_8_; -wire [0:0] cbx_1__2__0_bottom_grid_pin_9_; -wire [0:0] cbx_1__2__0_ccff_tail; -wire [0:19] cbx_1__2__0_chanx_left_out; -wire [0:19] cbx_1__2__0_chanx_right_out; -wire [0:0] cbx_1__2__0_top_grid_pin_0_; -wire [0:0] cbx_1__2__1_bottom_grid_pin_0_; -wire [0:0] cbx_1__2__1_bottom_grid_pin_10_; -wire [0:0] cbx_1__2__1_bottom_grid_pin_11_; -wire [0:0] cbx_1__2__1_bottom_grid_pin_12_; -wire [0:0] cbx_1__2__1_bottom_grid_pin_13_; -wire [0:0] cbx_1__2__1_bottom_grid_pin_14_; -wire [0:0] cbx_1__2__1_bottom_grid_pin_15_; -wire [0:0] cbx_1__2__1_bottom_grid_pin_1_; -wire [0:0] cbx_1__2__1_bottom_grid_pin_2_; -wire [0:0] cbx_1__2__1_bottom_grid_pin_3_; -wire [0:0] cbx_1__2__1_bottom_grid_pin_4_; -wire [0:0] cbx_1__2__1_bottom_grid_pin_5_; -wire [0:0] cbx_1__2__1_bottom_grid_pin_6_; -wire [0:0] cbx_1__2__1_bottom_grid_pin_7_; -wire [0:0] cbx_1__2__1_bottom_grid_pin_8_; -wire [0:0] cbx_1__2__1_bottom_grid_pin_9_; -wire [0:0] cbx_1__2__1_ccff_tail; -wire [0:19] cbx_1__2__1_chanx_left_out; -wire [0:19] cbx_1__2__1_chanx_right_out; -wire [0:0] cbx_1__2__1_top_grid_pin_0_; -wire [0:0] cby_0__1__0_ccff_tail; -wire [0:19] cby_0__1__0_chany_bottom_out; -wire [0:19] cby_0__1__0_chany_top_out; -wire [0:0] cby_0__1__0_left_grid_pin_0_; -wire [0:0] cby_0__1__1_ccff_tail; -wire [0:19] cby_0__1__1_chany_bottom_out; -wire [0:19] cby_0__1__1_chany_top_out; -wire [0:0] cby_0__1__1_left_grid_pin_0_; -wire [0:0] cby_1__1__0_ccff_tail; -wire [0:19] cby_1__1__0_chany_bottom_out; -wire [0:19] cby_1__1__0_chany_top_out; -wire [0:0] cby_1__1__0_left_grid_pin_16_; -wire [0:0] cby_1__1__0_left_grid_pin_17_; -wire [0:0] cby_1__1__0_left_grid_pin_18_; -wire [0:0] cby_1__1__0_left_grid_pin_19_; -wire [0:0] cby_1__1__0_left_grid_pin_20_; -wire [0:0] cby_1__1__0_left_grid_pin_21_; -wire [0:0] cby_1__1__0_left_grid_pin_22_; -wire [0:0] cby_1__1__0_left_grid_pin_23_; -wire [0:0] cby_1__1__0_left_grid_pin_24_; -wire [0:0] cby_1__1__0_left_grid_pin_25_; -wire [0:0] cby_1__1__0_left_grid_pin_26_; -wire [0:0] cby_1__1__0_left_grid_pin_27_; -wire [0:0] cby_1__1__0_left_grid_pin_28_; -wire [0:0] cby_1__1__0_left_grid_pin_29_; -wire [0:0] cby_1__1__0_left_grid_pin_30_; -wire [0:0] cby_1__1__0_left_grid_pin_31_; -wire [0:0] cby_1__1__1_ccff_tail; -wire [0:19] cby_1__1__1_chany_bottom_out; -wire [0:19] cby_1__1__1_chany_top_out; -wire [0:0] cby_1__1__1_left_grid_pin_16_; -wire [0:0] cby_1__1__1_left_grid_pin_17_; -wire [0:0] cby_1__1__1_left_grid_pin_18_; -wire [0:0] cby_1__1__1_left_grid_pin_19_; -wire [0:0] cby_1__1__1_left_grid_pin_20_; -wire [0:0] cby_1__1__1_left_grid_pin_21_; -wire [0:0] cby_1__1__1_left_grid_pin_22_; -wire [0:0] cby_1__1__1_left_grid_pin_23_; -wire [0:0] cby_1__1__1_left_grid_pin_24_; -wire [0:0] cby_1__1__1_left_grid_pin_25_; -wire [0:0] cby_1__1__1_left_grid_pin_26_; -wire [0:0] cby_1__1__1_left_grid_pin_27_; -wire [0:0] cby_1__1__1_left_grid_pin_28_; -wire [0:0] cby_1__1__1_left_grid_pin_29_; -wire [0:0] cby_1__1__1_left_grid_pin_30_; -wire [0:0] cby_1__1__1_left_grid_pin_31_; -wire [0:0] cby_2__1__0_ccff_tail; -wire [0:19] cby_2__1__0_chany_bottom_out; -wire [0:19] cby_2__1__0_chany_top_out; -wire [0:0] cby_2__1__0_left_grid_pin_16_; -wire [0:0] cby_2__1__0_left_grid_pin_17_; -wire [0:0] cby_2__1__0_left_grid_pin_18_; -wire [0:0] cby_2__1__0_left_grid_pin_19_; -wire [0:0] cby_2__1__0_left_grid_pin_20_; -wire [0:0] cby_2__1__0_left_grid_pin_21_; -wire [0:0] cby_2__1__0_left_grid_pin_22_; -wire [0:0] cby_2__1__0_left_grid_pin_23_; -wire [0:0] cby_2__1__0_left_grid_pin_24_; -wire [0:0] cby_2__1__0_left_grid_pin_25_; -wire [0:0] cby_2__1__0_left_grid_pin_26_; -wire [0:0] cby_2__1__0_left_grid_pin_27_; -wire [0:0] cby_2__1__0_left_grid_pin_28_; -wire [0:0] cby_2__1__0_left_grid_pin_29_; -wire [0:0] cby_2__1__0_left_grid_pin_30_; -wire [0:0] cby_2__1__0_left_grid_pin_31_; -wire [0:0] cby_2__1__0_right_grid_pin_0_; -wire [0:0] cby_2__1__1_ccff_tail; -wire [0:19] cby_2__1__1_chany_bottom_out; -wire [0:19] cby_2__1__1_chany_top_out; -wire [0:0] cby_2__1__1_left_grid_pin_16_; -wire [0:0] cby_2__1__1_left_grid_pin_17_; -wire [0:0] cby_2__1__1_left_grid_pin_18_; -wire [0:0] cby_2__1__1_left_grid_pin_19_; -wire [0:0] cby_2__1__1_left_grid_pin_20_; -wire [0:0] cby_2__1__1_left_grid_pin_21_; -wire [0:0] cby_2__1__1_left_grid_pin_22_; -wire [0:0] cby_2__1__1_left_grid_pin_23_; -wire [0:0] cby_2__1__1_left_grid_pin_24_; -wire [0:0] cby_2__1__1_left_grid_pin_25_; -wire [0:0] cby_2__1__1_left_grid_pin_26_; -wire [0:0] cby_2__1__1_left_grid_pin_27_; -wire [0:0] cby_2__1__1_left_grid_pin_28_; -wire [0:0] cby_2__1__1_left_grid_pin_29_; -wire [0:0] cby_2__1__1_left_grid_pin_30_; -wire [0:0] cby_2__1__1_left_grid_pin_31_; -wire [0:0] cby_2__1__1_right_grid_pin_0_; -wire [0:0] direct_interc_0_out; -wire [0:0] direct_interc_1_out; -wire [0:0] direct_interc_2_out; -wire [0:0] direct_interc_3_out; -wire [0:0] direct_interc_4_out; -wire [0:0] direct_interc_5_out; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_50_; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_51_; -wire [0:0] grid_clb_0_ccff_tail; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_42_lower; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_42_upper; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_43_lower; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_43_upper; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_44_lower; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_44_upper; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_45_lower; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_45_upper; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_46_lower; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_46_upper; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_47_lower; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_47_upper; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_48_lower; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_48_upper; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_49_lower; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_49_upper; -wire [0:0] grid_clb_0_top_width_0_height_0__pin_34_lower; -wire [0:0] grid_clb_0_top_width_0_height_0__pin_34_upper; -wire [0:0] grid_clb_0_top_width_0_height_0__pin_35_lower; -wire [0:0] grid_clb_0_top_width_0_height_0__pin_35_upper; -wire [0:0] grid_clb_0_top_width_0_height_0__pin_36_lower; -wire [0:0] grid_clb_0_top_width_0_height_0__pin_36_upper; -wire [0:0] grid_clb_0_top_width_0_height_0__pin_37_lower; -wire [0:0] grid_clb_0_top_width_0_height_0__pin_37_upper; -wire [0:0] grid_clb_0_top_width_0_height_0__pin_38_lower; -wire [0:0] grid_clb_0_top_width_0_height_0__pin_38_upper; -wire [0:0] grid_clb_0_top_width_0_height_0__pin_39_lower; -wire [0:0] grid_clb_0_top_width_0_height_0__pin_39_upper; -wire [0:0] grid_clb_0_top_width_0_height_0__pin_40_lower; -wire [0:0] grid_clb_0_top_width_0_height_0__pin_40_upper; -wire [0:0] grid_clb_0_top_width_0_height_0__pin_41_lower; -wire [0:0] grid_clb_0_top_width_0_height_0__pin_41_upper; -wire [0:0] grid_clb_1__1__undriven_left_width_0_height_0__pin_52_; -wire [0:0] grid_clb_1__2__undriven_left_width_0_height_0__pin_52_; -wire [0:0] grid_clb_1__2__undriven_top_width_0_height_0__pin_32_; -wire [0:0] grid_clb_1__2__undriven_top_width_0_height_0__pin_33_; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_50_; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_51_; -wire [0:0] grid_clb_1_ccff_tail; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_42_lower; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_42_upper; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_43_lower; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_43_upper; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_44_lower; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_44_upper; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_45_lower; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_45_upper; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_46_lower; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_46_upper; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_47_lower; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_47_upper; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_48_lower; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_48_upper; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_49_lower; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_49_upper; -wire [0:0] grid_clb_1_top_width_0_height_0__pin_34_lower; -wire [0:0] grid_clb_1_top_width_0_height_0__pin_34_upper; -wire [0:0] grid_clb_1_top_width_0_height_0__pin_35_lower; -wire [0:0] grid_clb_1_top_width_0_height_0__pin_35_upper; -wire [0:0] grid_clb_1_top_width_0_height_0__pin_36_lower; -wire [0:0] grid_clb_1_top_width_0_height_0__pin_36_upper; -wire [0:0] grid_clb_1_top_width_0_height_0__pin_37_lower; -wire [0:0] grid_clb_1_top_width_0_height_0__pin_37_upper; -wire [0:0] grid_clb_1_top_width_0_height_0__pin_38_lower; -wire [0:0] grid_clb_1_top_width_0_height_0__pin_38_upper; -wire [0:0] grid_clb_1_top_width_0_height_0__pin_39_lower; -wire [0:0] grid_clb_1_top_width_0_height_0__pin_39_upper; -wire [0:0] grid_clb_1_top_width_0_height_0__pin_40_lower; -wire [0:0] grid_clb_1_top_width_0_height_0__pin_40_upper; -wire [0:0] grid_clb_1_top_width_0_height_0__pin_41_lower; -wire [0:0] grid_clb_1_top_width_0_height_0__pin_41_upper; -wire [0:0] grid_clb_2__1__undriven_bottom_width_0_height_0__pin_50_; -wire [0:0] grid_clb_2__1__undriven_bottom_width_0_height_0__pin_51_; -wire [0:0] grid_clb_2__1__undriven_left_width_0_height_0__pin_52_; -wire [0:0] grid_clb_2__2__undriven_left_width_0_height_0__pin_52_; -wire [0:0] grid_clb_2_ccff_tail; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_42_lower; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_42_upper; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_43_lower; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_43_upper; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_44_lower; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_44_upper; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_45_lower; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_45_upper; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_46_lower; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_46_upper; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_47_lower; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_47_upper; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_48_lower; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_48_upper; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_49_lower; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_49_upper; -wire [0:0] grid_clb_2_top_width_0_height_0__pin_34_lower; -wire [0:0] grid_clb_2_top_width_0_height_0__pin_34_upper; -wire [0:0] grid_clb_2_top_width_0_height_0__pin_35_lower; -wire [0:0] grid_clb_2_top_width_0_height_0__pin_35_upper; -wire [0:0] grid_clb_2_top_width_0_height_0__pin_36_lower; -wire [0:0] grid_clb_2_top_width_0_height_0__pin_36_upper; -wire [0:0] grid_clb_2_top_width_0_height_0__pin_37_lower; -wire [0:0] grid_clb_2_top_width_0_height_0__pin_37_upper; -wire [0:0] grid_clb_2_top_width_0_height_0__pin_38_lower; -wire [0:0] grid_clb_2_top_width_0_height_0__pin_38_upper; -wire [0:0] grid_clb_2_top_width_0_height_0__pin_39_lower; -wire [0:0] grid_clb_2_top_width_0_height_0__pin_39_upper; -wire [0:0] grid_clb_2_top_width_0_height_0__pin_40_lower; -wire [0:0] grid_clb_2_top_width_0_height_0__pin_40_upper; -wire [0:0] grid_clb_2_top_width_0_height_0__pin_41_lower; -wire [0:0] grid_clb_2_top_width_0_height_0__pin_41_upper; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_50_; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_51_; -wire [0:0] grid_clb_3_ccff_tail; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_42_lower; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_42_upper; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_43_lower; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_43_upper; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_44_lower; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_44_upper; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_45_lower; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_45_upper; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_46_lower; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_46_upper; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_47_lower; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_47_upper; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_48_lower; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_48_upper; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_49_lower; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_49_upper; -wire [0:0] grid_clb_3_top_width_0_height_0__pin_34_lower; -wire [0:0] grid_clb_3_top_width_0_height_0__pin_34_upper; -wire [0:0] grid_clb_3_top_width_0_height_0__pin_35_lower; -wire [0:0] grid_clb_3_top_width_0_height_0__pin_35_upper; -wire [0:0] grid_clb_3_top_width_0_height_0__pin_36_lower; -wire [0:0] grid_clb_3_top_width_0_height_0__pin_36_upper; -wire [0:0] grid_clb_3_top_width_0_height_0__pin_37_lower; -wire [0:0] grid_clb_3_top_width_0_height_0__pin_37_upper; -wire [0:0] grid_clb_3_top_width_0_height_0__pin_38_lower; -wire [0:0] grid_clb_3_top_width_0_height_0__pin_38_upper; -wire [0:0] grid_clb_3_top_width_0_height_0__pin_39_lower; -wire [0:0] grid_clb_3_top_width_0_height_0__pin_39_upper; -wire [0:0] grid_clb_3_top_width_0_height_0__pin_40_lower; -wire [0:0] grid_clb_3_top_width_0_height_0__pin_40_upper; -wire [0:0] grid_clb_3_top_width_0_height_0__pin_41_lower; -wire [0:0] grid_clb_3_top_width_0_height_0__pin_41_upper; -wire [0:0] grid_io_bottom_bottom_0_ccff_tail; -wire [0:0] grid_io_bottom_bottom_0_top_width_0_height_0__pin_11_lower; -wire [0:0] grid_io_bottom_bottom_0_top_width_0_height_0__pin_11_upper; -wire [0:0] grid_io_bottom_bottom_0_top_width_0_height_0__pin_1_lower; -wire [0:0] grid_io_bottom_bottom_0_top_width_0_height_0__pin_1_upper; -wire [0:0] grid_io_bottom_bottom_0_top_width_0_height_0__pin_3_lower; -wire [0:0] grid_io_bottom_bottom_0_top_width_0_height_0__pin_3_upper; -wire [0:0] grid_io_bottom_bottom_0_top_width_0_height_0__pin_5_lower; -wire [0:0] grid_io_bottom_bottom_0_top_width_0_height_0__pin_5_upper; -wire [0:0] grid_io_bottom_bottom_0_top_width_0_height_0__pin_7_lower; -wire [0:0] grid_io_bottom_bottom_0_top_width_0_height_0__pin_7_upper; -wire [0:0] grid_io_bottom_bottom_0_top_width_0_height_0__pin_9_lower; -wire [0:0] grid_io_bottom_bottom_0_top_width_0_height_0__pin_9_upper; -wire [0:0] grid_io_bottom_bottom_1_ccff_tail; -wire [0:0] grid_io_bottom_bottom_1_top_width_0_height_0__pin_11_lower; -wire [0:0] grid_io_bottom_bottom_1_top_width_0_height_0__pin_11_upper; -wire [0:0] grid_io_bottom_bottom_1_top_width_0_height_0__pin_1_lower; -wire [0:0] grid_io_bottom_bottom_1_top_width_0_height_0__pin_1_upper; -wire [0:0] grid_io_bottom_bottom_1_top_width_0_height_0__pin_3_lower; -wire [0:0] grid_io_bottom_bottom_1_top_width_0_height_0__pin_3_upper; -wire [0:0] grid_io_bottom_bottom_1_top_width_0_height_0__pin_5_lower; -wire [0:0] grid_io_bottom_bottom_1_top_width_0_height_0__pin_5_upper; -wire [0:0] grid_io_bottom_bottom_1_top_width_0_height_0__pin_7_lower; -wire [0:0] grid_io_bottom_bottom_1_top_width_0_height_0__pin_7_upper; -wire [0:0] grid_io_bottom_bottom_1_top_width_0_height_0__pin_9_lower; -wire [0:0] grid_io_bottom_bottom_1_top_width_0_height_0__pin_9_upper; -wire [0:0] grid_io_left_left_0_ccff_tail; -wire [0:0] grid_io_left_left_0_right_width_0_height_0__pin_1_lower; -wire [0:0] grid_io_left_left_0_right_width_0_height_0__pin_1_upper; -wire [0:0] grid_io_left_left_1_ccff_tail; -wire [0:0] grid_io_left_left_1_right_width_0_height_0__pin_1_lower; -wire [0:0] grid_io_left_left_1_right_width_0_height_0__pin_1_upper; -wire [0:0] grid_io_right_right_0_ccff_tail; -wire [0:0] grid_io_right_right_0_left_width_0_height_0__pin_1_lower; -wire [0:0] grid_io_right_right_0_left_width_0_height_0__pin_1_upper; -wire [0:0] grid_io_right_right_1_ccff_tail; -wire [0:0] grid_io_right_right_1_left_width_0_height_0__pin_1_lower; -wire [0:0] grid_io_right_right_1_left_width_0_height_0__pin_1_upper; -wire [0:0] grid_io_top_top_0_bottom_width_0_height_0__pin_1_lower; -wire [0:0] grid_io_top_top_0_bottom_width_0_height_0__pin_1_upper; -wire [0:0] grid_io_top_top_0_ccff_tail; -wire [0:0] grid_io_top_top_1_bottom_width_0_height_0__pin_1_lower; -wire [0:0] grid_io_top_top_1_bottom_width_0_height_0__pin_1_upper; -wire [0:0] grid_io_top_top_1_ccff_tail; -wire [0:19] sb_0__0__0_chanx_right_out; -wire [0:19] sb_0__0__0_chany_top_out; -wire [0:0] sb_0__1__0_ccff_tail; -wire [0:19] sb_0__1__0_chanx_right_out; -wire [0:19] sb_0__1__0_chany_bottom_out; -wire [0:19] sb_0__1__0_chany_top_out; -wire [0:0] sb_0__2__0_ccff_tail; -wire [0:19] sb_0__2__0_chanx_right_out; -wire [0:19] sb_0__2__0_chany_bottom_out; -wire [0:0] sb_1__0__0_ccff_tail; -wire [0:19] sb_1__0__0_chanx_left_out; -wire [0:19] sb_1__0__0_chanx_right_out; -wire [0:19] sb_1__0__0_chany_top_out; -wire [0:0] sb_1__1__0_ccff_tail; -wire [0:19] sb_1__1__0_chanx_left_out; -wire [0:19] sb_1__1__0_chanx_right_out; -wire [0:19] sb_1__1__0_chany_bottom_out; -wire [0:19] sb_1__1__0_chany_top_out; -wire [0:0] sb_1__2__0_ccff_tail; -wire [0:19] sb_1__2__0_chanx_left_out; -wire [0:19] sb_1__2__0_chanx_right_out; -wire [0:19] sb_1__2__0_chany_bottom_out; -wire [0:0] sb_2__0__0_ccff_tail; -wire [0:19] sb_2__0__0_chanx_left_out; -wire [0:19] sb_2__0__0_chany_top_out; -wire [0:0] sb_2__1__0_ccff_tail; -wire [0:19] sb_2__1__0_chanx_left_out; -wire [0:19] sb_2__1__0_chany_bottom_out; -wire [0:19] sb_2__1__0_chany_top_out; -wire [0:0] sb_2__2__0_ccff_tail; -wire [0:19] sb_2__2__0_chanx_left_out; -wire [0:19] sb_2__2__0_chany_bottom_out; - -// -// -// -// - - grid_clb grid_clb_1__1_ ( - .prog_clk(prog_clk[0]), - .Test_en(Test_en[0]), - .clk(clk[0]), - .top_width_0_height_0__pin_0_(cbx_1__1__0_bottom_grid_pin_0_[0]), - .top_width_0_height_0__pin_1_(cbx_1__1__0_bottom_grid_pin_1_[0]), - .top_width_0_height_0__pin_2_(cbx_1__1__0_bottom_grid_pin_2_[0]), - .top_width_0_height_0__pin_3_(cbx_1__1__0_bottom_grid_pin_3_[0]), - .top_width_0_height_0__pin_4_(cbx_1__1__0_bottom_grid_pin_4_[0]), - .top_width_0_height_0__pin_5_(cbx_1__1__0_bottom_grid_pin_5_[0]), - .top_width_0_height_0__pin_6_(cbx_1__1__0_bottom_grid_pin_6_[0]), - .top_width_0_height_0__pin_7_(cbx_1__1__0_bottom_grid_pin_7_[0]), - .top_width_0_height_0__pin_8_(cbx_1__1__0_bottom_grid_pin_8_[0]), - .top_width_0_height_0__pin_9_(cbx_1__1__0_bottom_grid_pin_9_[0]), - .top_width_0_height_0__pin_10_(cbx_1__1__0_bottom_grid_pin_10_[0]), - .top_width_0_height_0__pin_11_(cbx_1__1__0_bottom_grid_pin_11_[0]), - .top_width_0_height_0__pin_12_(cbx_1__1__0_bottom_grid_pin_12_[0]), - .top_width_0_height_0__pin_13_(cbx_1__1__0_bottom_grid_pin_13_[0]), - .top_width_0_height_0__pin_14_(cbx_1__1__0_bottom_grid_pin_14_[0]), - .top_width_0_height_0__pin_15_(cbx_1__1__0_bottom_grid_pin_15_[0]), - .top_width_0_height_0__pin_32_(direct_interc_0_out[0]), - .top_width_0_height_0__pin_33_(direct_interc_3_out[0]), - .right_width_0_height_0__pin_16_(cby_1__1__0_left_grid_pin_16_[0]), - .right_width_0_height_0__pin_17_(cby_1__1__0_left_grid_pin_17_[0]), - .right_width_0_height_0__pin_18_(cby_1__1__0_left_grid_pin_18_[0]), - .right_width_0_height_0__pin_19_(cby_1__1__0_left_grid_pin_19_[0]), - .right_width_0_height_0__pin_20_(cby_1__1__0_left_grid_pin_20_[0]), - .right_width_0_height_0__pin_21_(cby_1__1__0_left_grid_pin_21_[0]), - .right_width_0_height_0__pin_22_(cby_1__1__0_left_grid_pin_22_[0]), - .right_width_0_height_0__pin_23_(cby_1__1__0_left_grid_pin_23_[0]), - .right_width_0_height_0__pin_24_(cby_1__1__0_left_grid_pin_24_[0]), - .right_width_0_height_0__pin_25_(cby_1__1__0_left_grid_pin_25_[0]), - .right_width_0_height_0__pin_26_(cby_1__1__0_left_grid_pin_26_[0]), - .right_width_0_height_0__pin_27_(cby_1__1__0_left_grid_pin_27_[0]), - .right_width_0_height_0__pin_28_(cby_1__1__0_left_grid_pin_28_[0]), - .right_width_0_height_0__pin_29_(cby_1__1__0_left_grid_pin_29_[0]), - .right_width_0_height_0__pin_30_(cby_1__1__0_left_grid_pin_30_[0]), - .right_width_0_height_0__pin_31_(cby_1__1__0_left_grid_pin_31_[0]), - .left_width_0_height_0__pin_52_(grid_clb_1__1__undriven_left_width_0_height_0__pin_52_[0]), - .ccff_head(grid_io_left_left_0_ccff_tail[0]), - .top_width_0_height_0__pin_34_upper(grid_clb_0_top_width_0_height_0__pin_34_upper[0]), - .top_width_0_height_0__pin_34_lower(grid_clb_0_top_width_0_height_0__pin_34_lower[0]), - .top_width_0_height_0__pin_35_upper(grid_clb_0_top_width_0_height_0__pin_35_upper[0]), - .top_width_0_height_0__pin_35_lower(grid_clb_0_top_width_0_height_0__pin_35_lower[0]), - .top_width_0_height_0__pin_36_upper(grid_clb_0_top_width_0_height_0__pin_36_upper[0]), - .top_width_0_height_0__pin_36_lower(grid_clb_0_top_width_0_height_0__pin_36_lower[0]), - .top_width_0_height_0__pin_37_upper(grid_clb_0_top_width_0_height_0__pin_37_upper[0]), - .top_width_0_height_0__pin_37_lower(grid_clb_0_top_width_0_height_0__pin_37_lower[0]), - .top_width_0_height_0__pin_38_upper(grid_clb_0_top_width_0_height_0__pin_38_upper[0]), - .top_width_0_height_0__pin_38_lower(grid_clb_0_top_width_0_height_0__pin_38_lower[0]), - .top_width_0_height_0__pin_39_upper(grid_clb_0_top_width_0_height_0__pin_39_upper[0]), - .top_width_0_height_0__pin_39_lower(grid_clb_0_top_width_0_height_0__pin_39_lower[0]), - .top_width_0_height_0__pin_40_upper(grid_clb_0_top_width_0_height_0__pin_40_upper[0]), - .top_width_0_height_0__pin_40_lower(grid_clb_0_top_width_0_height_0__pin_40_lower[0]), - .top_width_0_height_0__pin_41_upper(grid_clb_0_top_width_0_height_0__pin_41_upper[0]), - .top_width_0_height_0__pin_41_lower(grid_clb_0_top_width_0_height_0__pin_41_lower[0]), - .right_width_0_height_0__pin_42_upper(grid_clb_0_right_width_0_height_0__pin_42_upper[0]), - .right_width_0_height_0__pin_42_lower(grid_clb_0_right_width_0_height_0__pin_42_lower[0]), - .right_width_0_height_0__pin_43_upper(grid_clb_0_right_width_0_height_0__pin_43_upper[0]), - .right_width_0_height_0__pin_43_lower(grid_clb_0_right_width_0_height_0__pin_43_lower[0]), - .right_width_0_height_0__pin_44_upper(grid_clb_0_right_width_0_height_0__pin_44_upper[0]), - .right_width_0_height_0__pin_44_lower(grid_clb_0_right_width_0_height_0__pin_44_lower[0]), - .right_width_0_height_0__pin_45_upper(grid_clb_0_right_width_0_height_0__pin_45_upper[0]), - .right_width_0_height_0__pin_45_lower(grid_clb_0_right_width_0_height_0__pin_45_lower[0]), - .right_width_0_height_0__pin_46_upper(grid_clb_0_right_width_0_height_0__pin_46_upper[0]), - .right_width_0_height_0__pin_46_lower(grid_clb_0_right_width_0_height_0__pin_46_lower[0]), - .right_width_0_height_0__pin_47_upper(grid_clb_0_right_width_0_height_0__pin_47_upper[0]), - .right_width_0_height_0__pin_47_lower(grid_clb_0_right_width_0_height_0__pin_47_lower[0]), - .right_width_0_height_0__pin_48_upper(grid_clb_0_right_width_0_height_0__pin_48_upper[0]), - .right_width_0_height_0__pin_48_lower(grid_clb_0_right_width_0_height_0__pin_48_lower[0]), - .right_width_0_height_0__pin_49_upper(grid_clb_0_right_width_0_height_0__pin_49_upper[0]), - .right_width_0_height_0__pin_49_lower(grid_clb_0_right_width_0_height_0__pin_49_lower[0]), - .bottom_width_0_height_0__pin_50_(grid_clb_0_bottom_width_0_height_0__pin_50_[0]), - .bottom_width_0_height_0__pin_51_(grid_clb_0_bottom_width_0_height_0__pin_51_[0]), - .ccff_tail(grid_clb_0_ccff_tail[0])); - - grid_clb grid_clb_1__2_ ( - .prog_clk(prog_clk[0]), - .Test_en(Test_en[0]), - .clk(clk[0]), - .top_width_0_height_0__pin_0_(cbx_1__2__0_bottom_grid_pin_0_[0]), - .top_width_0_height_0__pin_1_(cbx_1__2__0_bottom_grid_pin_1_[0]), - .top_width_0_height_0__pin_2_(cbx_1__2__0_bottom_grid_pin_2_[0]), - .top_width_0_height_0__pin_3_(cbx_1__2__0_bottom_grid_pin_3_[0]), - .top_width_0_height_0__pin_4_(cbx_1__2__0_bottom_grid_pin_4_[0]), - .top_width_0_height_0__pin_5_(cbx_1__2__0_bottom_grid_pin_5_[0]), - .top_width_0_height_0__pin_6_(cbx_1__2__0_bottom_grid_pin_6_[0]), - .top_width_0_height_0__pin_7_(cbx_1__2__0_bottom_grid_pin_7_[0]), - .top_width_0_height_0__pin_8_(cbx_1__2__0_bottom_grid_pin_8_[0]), - .top_width_0_height_0__pin_9_(cbx_1__2__0_bottom_grid_pin_9_[0]), - .top_width_0_height_0__pin_10_(cbx_1__2__0_bottom_grid_pin_10_[0]), - .top_width_0_height_0__pin_11_(cbx_1__2__0_bottom_grid_pin_11_[0]), - .top_width_0_height_0__pin_12_(cbx_1__2__0_bottom_grid_pin_12_[0]), - .top_width_0_height_0__pin_13_(cbx_1__2__0_bottom_grid_pin_13_[0]), - .top_width_0_height_0__pin_14_(cbx_1__2__0_bottom_grid_pin_14_[0]), - .top_width_0_height_0__pin_15_(cbx_1__2__0_bottom_grid_pin_15_[0]), - .top_width_0_height_0__pin_32_(grid_clb_1__2__undriven_top_width_0_height_0__pin_32_[0]), - .top_width_0_height_0__pin_33_(grid_clb_1__2__undriven_top_width_0_height_0__pin_33_[0]), - .right_width_0_height_0__pin_16_(cby_1__1__1_left_grid_pin_16_[0]), - .right_width_0_height_0__pin_17_(cby_1__1__1_left_grid_pin_17_[0]), - .right_width_0_height_0__pin_18_(cby_1__1__1_left_grid_pin_18_[0]), - .right_width_0_height_0__pin_19_(cby_1__1__1_left_grid_pin_19_[0]), - .right_width_0_height_0__pin_20_(cby_1__1__1_left_grid_pin_20_[0]), - .right_width_0_height_0__pin_21_(cby_1__1__1_left_grid_pin_21_[0]), - .right_width_0_height_0__pin_22_(cby_1__1__1_left_grid_pin_22_[0]), - .right_width_0_height_0__pin_23_(cby_1__1__1_left_grid_pin_23_[0]), - .right_width_0_height_0__pin_24_(cby_1__1__1_left_grid_pin_24_[0]), - .right_width_0_height_0__pin_25_(cby_1__1__1_left_grid_pin_25_[0]), - .right_width_0_height_0__pin_26_(cby_1__1__1_left_grid_pin_26_[0]), - .right_width_0_height_0__pin_27_(cby_1__1__1_left_grid_pin_27_[0]), - .right_width_0_height_0__pin_28_(cby_1__1__1_left_grid_pin_28_[0]), - .right_width_0_height_0__pin_29_(cby_1__1__1_left_grid_pin_29_[0]), - .right_width_0_height_0__pin_30_(cby_1__1__1_left_grid_pin_30_[0]), - .right_width_0_height_0__pin_31_(cby_1__1__1_left_grid_pin_31_[0]), - .left_width_0_height_0__pin_52_(grid_clb_1__2__undriven_left_width_0_height_0__pin_52_[0]), - .ccff_head(grid_io_left_left_1_ccff_tail[0]), - .top_width_0_height_0__pin_34_upper(grid_clb_1_top_width_0_height_0__pin_34_upper[0]), - .top_width_0_height_0__pin_34_lower(grid_clb_1_top_width_0_height_0__pin_34_lower[0]), - .top_width_0_height_0__pin_35_upper(grid_clb_1_top_width_0_height_0__pin_35_upper[0]), - .top_width_0_height_0__pin_35_lower(grid_clb_1_top_width_0_height_0__pin_35_lower[0]), - .top_width_0_height_0__pin_36_upper(grid_clb_1_top_width_0_height_0__pin_36_upper[0]), - .top_width_0_height_0__pin_36_lower(grid_clb_1_top_width_0_height_0__pin_36_lower[0]), - .top_width_0_height_0__pin_37_upper(grid_clb_1_top_width_0_height_0__pin_37_upper[0]), - .top_width_0_height_0__pin_37_lower(grid_clb_1_top_width_0_height_0__pin_37_lower[0]), - .top_width_0_height_0__pin_38_upper(grid_clb_1_top_width_0_height_0__pin_38_upper[0]), - .top_width_0_height_0__pin_38_lower(grid_clb_1_top_width_0_height_0__pin_38_lower[0]), - .top_width_0_height_0__pin_39_upper(grid_clb_1_top_width_0_height_0__pin_39_upper[0]), - .top_width_0_height_0__pin_39_lower(grid_clb_1_top_width_0_height_0__pin_39_lower[0]), - .top_width_0_height_0__pin_40_upper(grid_clb_1_top_width_0_height_0__pin_40_upper[0]), - .top_width_0_height_0__pin_40_lower(grid_clb_1_top_width_0_height_0__pin_40_lower[0]), - .top_width_0_height_0__pin_41_upper(grid_clb_1_top_width_0_height_0__pin_41_upper[0]), - .top_width_0_height_0__pin_41_lower(grid_clb_1_top_width_0_height_0__pin_41_lower[0]), - .right_width_0_height_0__pin_42_upper(grid_clb_1_right_width_0_height_0__pin_42_upper[0]), - .right_width_0_height_0__pin_42_lower(grid_clb_1_right_width_0_height_0__pin_42_lower[0]), - .right_width_0_height_0__pin_43_upper(grid_clb_1_right_width_0_height_0__pin_43_upper[0]), - .right_width_0_height_0__pin_43_lower(grid_clb_1_right_width_0_height_0__pin_43_lower[0]), - .right_width_0_height_0__pin_44_upper(grid_clb_1_right_width_0_height_0__pin_44_upper[0]), - .right_width_0_height_0__pin_44_lower(grid_clb_1_right_width_0_height_0__pin_44_lower[0]), - .right_width_0_height_0__pin_45_upper(grid_clb_1_right_width_0_height_0__pin_45_upper[0]), - .right_width_0_height_0__pin_45_lower(grid_clb_1_right_width_0_height_0__pin_45_lower[0]), - .right_width_0_height_0__pin_46_upper(grid_clb_1_right_width_0_height_0__pin_46_upper[0]), - .right_width_0_height_0__pin_46_lower(grid_clb_1_right_width_0_height_0__pin_46_lower[0]), - .right_width_0_height_0__pin_47_upper(grid_clb_1_right_width_0_height_0__pin_47_upper[0]), - .right_width_0_height_0__pin_47_lower(grid_clb_1_right_width_0_height_0__pin_47_lower[0]), - .right_width_0_height_0__pin_48_upper(grid_clb_1_right_width_0_height_0__pin_48_upper[0]), - .right_width_0_height_0__pin_48_lower(grid_clb_1_right_width_0_height_0__pin_48_lower[0]), - .right_width_0_height_0__pin_49_upper(grid_clb_1_right_width_0_height_0__pin_49_upper[0]), - .right_width_0_height_0__pin_49_lower(grid_clb_1_right_width_0_height_0__pin_49_lower[0]), - .bottom_width_0_height_0__pin_50_(grid_clb_1_bottom_width_0_height_0__pin_50_[0]), - .bottom_width_0_height_0__pin_51_(grid_clb_1_bottom_width_0_height_0__pin_51_[0]), - .ccff_tail(grid_clb_1_ccff_tail[0])); - - grid_clb grid_clb_2__1_ ( - .prog_clk(prog_clk[0]), - .Test_en(Test_en[0]), - .clk(clk[0]), - .top_width_0_height_0__pin_0_(cbx_1__1__1_bottom_grid_pin_0_[0]), - .top_width_0_height_0__pin_1_(cbx_1__1__1_bottom_grid_pin_1_[0]), - .top_width_0_height_0__pin_2_(cbx_1__1__1_bottom_grid_pin_2_[0]), - .top_width_0_height_0__pin_3_(cbx_1__1__1_bottom_grid_pin_3_[0]), - .top_width_0_height_0__pin_4_(cbx_1__1__1_bottom_grid_pin_4_[0]), - .top_width_0_height_0__pin_5_(cbx_1__1__1_bottom_grid_pin_5_[0]), - .top_width_0_height_0__pin_6_(cbx_1__1__1_bottom_grid_pin_6_[0]), - .top_width_0_height_0__pin_7_(cbx_1__1__1_bottom_grid_pin_7_[0]), - .top_width_0_height_0__pin_8_(cbx_1__1__1_bottom_grid_pin_8_[0]), - .top_width_0_height_0__pin_9_(cbx_1__1__1_bottom_grid_pin_9_[0]), - .top_width_0_height_0__pin_10_(cbx_1__1__1_bottom_grid_pin_10_[0]), - .top_width_0_height_0__pin_11_(cbx_1__1__1_bottom_grid_pin_11_[0]), - .top_width_0_height_0__pin_12_(cbx_1__1__1_bottom_grid_pin_12_[0]), - .top_width_0_height_0__pin_13_(cbx_1__1__1_bottom_grid_pin_13_[0]), - .top_width_0_height_0__pin_14_(cbx_1__1__1_bottom_grid_pin_14_[0]), - .top_width_0_height_0__pin_15_(cbx_1__1__1_bottom_grid_pin_15_[0]), - .top_width_0_height_0__pin_32_(direct_interc_1_out[0]), - .top_width_0_height_0__pin_33_(direct_interc_4_out[0]), - .right_width_0_height_0__pin_16_(cby_2__1__0_left_grid_pin_16_[0]), - .right_width_0_height_0__pin_17_(cby_2__1__0_left_grid_pin_17_[0]), - .right_width_0_height_0__pin_18_(cby_2__1__0_left_grid_pin_18_[0]), - .right_width_0_height_0__pin_19_(cby_2__1__0_left_grid_pin_19_[0]), - .right_width_0_height_0__pin_20_(cby_2__1__0_left_grid_pin_20_[0]), - .right_width_0_height_0__pin_21_(cby_2__1__0_left_grid_pin_21_[0]), - .right_width_0_height_0__pin_22_(cby_2__1__0_left_grid_pin_22_[0]), - .right_width_0_height_0__pin_23_(cby_2__1__0_left_grid_pin_23_[0]), - .right_width_0_height_0__pin_24_(cby_2__1__0_left_grid_pin_24_[0]), - .right_width_0_height_0__pin_25_(cby_2__1__0_left_grid_pin_25_[0]), - .right_width_0_height_0__pin_26_(cby_2__1__0_left_grid_pin_26_[0]), - .right_width_0_height_0__pin_27_(cby_2__1__0_left_grid_pin_27_[0]), - .right_width_0_height_0__pin_28_(cby_2__1__0_left_grid_pin_28_[0]), - .right_width_0_height_0__pin_29_(cby_2__1__0_left_grid_pin_29_[0]), - .right_width_0_height_0__pin_30_(cby_2__1__0_left_grid_pin_30_[0]), - .right_width_0_height_0__pin_31_(cby_2__1__0_left_grid_pin_31_[0]), - .left_width_0_height_0__pin_52_(grid_clb_2__1__undriven_left_width_0_height_0__pin_52_[0]), - .ccff_head(cby_1__1__0_ccff_tail[0]), - .top_width_0_height_0__pin_34_upper(grid_clb_2_top_width_0_height_0__pin_34_upper[0]), - .top_width_0_height_0__pin_34_lower(grid_clb_2_top_width_0_height_0__pin_34_lower[0]), - .top_width_0_height_0__pin_35_upper(grid_clb_2_top_width_0_height_0__pin_35_upper[0]), - .top_width_0_height_0__pin_35_lower(grid_clb_2_top_width_0_height_0__pin_35_lower[0]), - .top_width_0_height_0__pin_36_upper(grid_clb_2_top_width_0_height_0__pin_36_upper[0]), - .top_width_0_height_0__pin_36_lower(grid_clb_2_top_width_0_height_0__pin_36_lower[0]), - .top_width_0_height_0__pin_37_upper(grid_clb_2_top_width_0_height_0__pin_37_upper[0]), - .top_width_0_height_0__pin_37_lower(grid_clb_2_top_width_0_height_0__pin_37_lower[0]), - .top_width_0_height_0__pin_38_upper(grid_clb_2_top_width_0_height_0__pin_38_upper[0]), - .top_width_0_height_0__pin_38_lower(grid_clb_2_top_width_0_height_0__pin_38_lower[0]), - .top_width_0_height_0__pin_39_upper(grid_clb_2_top_width_0_height_0__pin_39_upper[0]), - .top_width_0_height_0__pin_39_lower(grid_clb_2_top_width_0_height_0__pin_39_lower[0]), - .top_width_0_height_0__pin_40_upper(grid_clb_2_top_width_0_height_0__pin_40_upper[0]), - .top_width_0_height_0__pin_40_lower(grid_clb_2_top_width_0_height_0__pin_40_lower[0]), - .top_width_0_height_0__pin_41_upper(grid_clb_2_top_width_0_height_0__pin_41_upper[0]), - .top_width_0_height_0__pin_41_lower(grid_clb_2_top_width_0_height_0__pin_41_lower[0]), - .right_width_0_height_0__pin_42_upper(grid_clb_2_right_width_0_height_0__pin_42_upper[0]), - .right_width_0_height_0__pin_42_lower(grid_clb_2_right_width_0_height_0__pin_42_lower[0]), - .right_width_0_height_0__pin_43_upper(grid_clb_2_right_width_0_height_0__pin_43_upper[0]), - .right_width_0_height_0__pin_43_lower(grid_clb_2_right_width_0_height_0__pin_43_lower[0]), - .right_width_0_height_0__pin_44_upper(grid_clb_2_right_width_0_height_0__pin_44_upper[0]), - .right_width_0_height_0__pin_44_lower(grid_clb_2_right_width_0_height_0__pin_44_lower[0]), - .right_width_0_height_0__pin_45_upper(grid_clb_2_right_width_0_height_0__pin_45_upper[0]), - .right_width_0_height_0__pin_45_lower(grid_clb_2_right_width_0_height_0__pin_45_lower[0]), - .right_width_0_height_0__pin_46_upper(grid_clb_2_right_width_0_height_0__pin_46_upper[0]), - .right_width_0_height_0__pin_46_lower(grid_clb_2_right_width_0_height_0__pin_46_lower[0]), - .right_width_0_height_0__pin_47_upper(grid_clb_2_right_width_0_height_0__pin_47_upper[0]), - .right_width_0_height_0__pin_47_lower(grid_clb_2_right_width_0_height_0__pin_47_lower[0]), - .right_width_0_height_0__pin_48_upper(grid_clb_2_right_width_0_height_0__pin_48_upper[0]), - .right_width_0_height_0__pin_48_lower(grid_clb_2_right_width_0_height_0__pin_48_lower[0]), - .right_width_0_height_0__pin_49_upper(grid_clb_2_right_width_0_height_0__pin_49_upper[0]), - .right_width_0_height_0__pin_49_lower(grid_clb_2_right_width_0_height_0__pin_49_lower[0]), - .bottom_width_0_height_0__pin_50_(grid_clb_2__1__undriven_bottom_width_0_height_0__pin_50_[0]), - .bottom_width_0_height_0__pin_51_(grid_clb_2__1__undriven_bottom_width_0_height_0__pin_51_[0]), - .ccff_tail(grid_clb_2_ccff_tail[0])); - - grid_clb grid_clb_2__2_ ( - .prog_clk(prog_clk[0]), - .Test_en(Test_en[0]), - .clk(clk[0]), - .top_width_0_height_0__pin_0_(cbx_1__2__1_bottom_grid_pin_0_[0]), - .top_width_0_height_0__pin_1_(cbx_1__2__1_bottom_grid_pin_1_[0]), - .top_width_0_height_0__pin_2_(cbx_1__2__1_bottom_grid_pin_2_[0]), - .top_width_0_height_0__pin_3_(cbx_1__2__1_bottom_grid_pin_3_[0]), - .top_width_0_height_0__pin_4_(cbx_1__2__1_bottom_grid_pin_4_[0]), - .top_width_0_height_0__pin_5_(cbx_1__2__1_bottom_grid_pin_5_[0]), - .top_width_0_height_0__pin_6_(cbx_1__2__1_bottom_grid_pin_6_[0]), - .top_width_0_height_0__pin_7_(cbx_1__2__1_bottom_grid_pin_7_[0]), - .top_width_0_height_0__pin_8_(cbx_1__2__1_bottom_grid_pin_8_[0]), - .top_width_0_height_0__pin_9_(cbx_1__2__1_bottom_grid_pin_9_[0]), - .top_width_0_height_0__pin_10_(cbx_1__2__1_bottom_grid_pin_10_[0]), - .top_width_0_height_0__pin_11_(cbx_1__2__1_bottom_grid_pin_11_[0]), - .top_width_0_height_0__pin_12_(cbx_1__2__1_bottom_grid_pin_12_[0]), - .top_width_0_height_0__pin_13_(cbx_1__2__1_bottom_grid_pin_13_[0]), - .top_width_0_height_0__pin_14_(cbx_1__2__1_bottom_grid_pin_14_[0]), - .top_width_0_height_0__pin_15_(cbx_1__2__1_bottom_grid_pin_15_[0]), - .top_width_0_height_0__pin_32_(direct_interc_2_out[0]), - .top_width_0_height_0__pin_33_(direct_interc_5_out[0]), - .right_width_0_height_0__pin_16_(cby_2__1__1_left_grid_pin_16_[0]), - .right_width_0_height_0__pin_17_(cby_2__1__1_left_grid_pin_17_[0]), - .right_width_0_height_0__pin_18_(cby_2__1__1_left_grid_pin_18_[0]), - .right_width_0_height_0__pin_19_(cby_2__1__1_left_grid_pin_19_[0]), - .right_width_0_height_0__pin_20_(cby_2__1__1_left_grid_pin_20_[0]), - .right_width_0_height_0__pin_21_(cby_2__1__1_left_grid_pin_21_[0]), - .right_width_0_height_0__pin_22_(cby_2__1__1_left_grid_pin_22_[0]), - .right_width_0_height_0__pin_23_(cby_2__1__1_left_grid_pin_23_[0]), - .right_width_0_height_0__pin_24_(cby_2__1__1_left_grid_pin_24_[0]), - .right_width_0_height_0__pin_25_(cby_2__1__1_left_grid_pin_25_[0]), - .right_width_0_height_0__pin_26_(cby_2__1__1_left_grid_pin_26_[0]), - .right_width_0_height_0__pin_27_(cby_2__1__1_left_grid_pin_27_[0]), - .right_width_0_height_0__pin_28_(cby_2__1__1_left_grid_pin_28_[0]), - .right_width_0_height_0__pin_29_(cby_2__1__1_left_grid_pin_29_[0]), - .right_width_0_height_0__pin_30_(cby_2__1__1_left_grid_pin_30_[0]), - .right_width_0_height_0__pin_31_(cby_2__1__1_left_grid_pin_31_[0]), - .left_width_0_height_0__pin_52_(grid_clb_2__2__undriven_left_width_0_height_0__pin_52_[0]), - .ccff_head(cby_1__1__1_ccff_tail[0]), - .top_width_0_height_0__pin_34_upper(grid_clb_3_top_width_0_height_0__pin_34_upper[0]), - .top_width_0_height_0__pin_34_lower(grid_clb_3_top_width_0_height_0__pin_34_lower[0]), - .top_width_0_height_0__pin_35_upper(grid_clb_3_top_width_0_height_0__pin_35_upper[0]), - .top_width_0_height_0__pin_35_lower(grid_clb_3_top_width_0_height_0__pin_35_lower[0]), - .top_width_0_height_0__pin_36_upper(grid_clb_3_top_width_0_height_0__pin_36_upper[0]), - .top_width_0_height_0__pin_36_lower(grid_clb_3_top_width_0_height_0__pin_36_lower[0]), - .top_width_0_height_0__pin_37_upper(grid_clb_3_top_width_0_height_0__pin_37_upper[0]), - .top_width_0_height_0__pin_37_lower(grid_clb_3_top_width_0_height_0__pin_37_lower[0]), - .top_width_0_height_0__pin_38_upper(grid_clb_3_top_width_0_height_0__pin_38_upper[0]), - .top_width_0_height_0__pin_38_lower(grid_clb_3_top_width_0_height_0__pin_38_lower[0]), - .top_width_0_height_0__pin_39_upper(grid_clb_3_top_width_0_height_0__pin_39_upper[0]), - .top_width_0_height_0__pin_39_lower(grid_clb_3_top_width_0_height_0__pin_39_lower[0]), - .top_width_0_height_0__pin_40_upper(grid_clb_3_top_width_0_height_0__pin_40_upper[0]), - .top_width_0_height_0__pin_40_lower(grid_clb_3_top_width_0_height_0__pin_40_lower[0]), - .top_width_0_height_0__pin_41_upper(grid_clb_3_top_width_0_height_0__pin_41_upper[0]), - .top_width_0_height_0__pin_41_lower(grid_clb_3_top_width_0_height_0__pin_41_lower[0]), - .right_width_0_height_0__pin_42_upper(grid_clb_3_right_width_0_height_0__pin_42_upper[0]), - .right_width_0_height_0__pin_42_lower(grid_clb_3_right_width_0_height_0__pin_42_lower[0]), - .right_width_0_height_0__pin_43_upper(grid_clb_3_right_width_0_height_0__pin_43_upper[0]), - .right_width_0_height_0__pin_43_lower(grid_clb_3_right_width_0_height_0__pin_43_lower[0]), - .right_width_0_height_0__pin_44_upper(grid_clb_3_right_width_0_height_0__pin_44_upper[0]), - .right_width_0_height_0__pin_44_lower(grid_clb_3_right_width_0_height_0__pin_44_lower[0]), - .right_width_0_height_0__pin_45_upper(grid_clb_3_right_width_0_height_0__pin_45_upper[0]), - .right_width_0_height_0__pin_45_lower(grid_clb_3_right_width_0_height_0__pin_45_lower[0]), - .right_width_0_height_0__pin_46_upper(grid_clb_3_right_width_0_height_0__pin_46_upper[0]), - .right_width_0_height_0__pin_46_lower(grid_clb_3_right_width_0_height_0__pin_46_lower[0]), - .right_width_0_height_0__pin_47_upper(grid_clb_3_right_width_0_height_0__pin_47_upper[0]), - .right_width_0_height_0__pin_47_lower(grid_clb_3_right_width_0_height_0__pin_47_lower[0]), - .right_width_0_height_0__pin_48_upper(grid_clb_3_right_width_0_height_0__pin_48_upper[0]), - .right_width_0_height_0__pin_48_lower(grid_clb_3_right_width_0_height_0__pin_48_lower[0]), - .right_width_0_height_0__pin_49_upper(grid_clb_3_right_width_0_height_0__pin_49_upper[0]), - .right_width_0_height_0__pin_49_lower(grid_clb_3_right_width_0_height_0__pin_49_lower[0]), - .bottom_width_0_height_0__pin_50_(grid_clb_3_bottom_width_0_height_0__pin_50_[0]), - .bottom_width_0_height_0__pin_51_(grid_clb_3_bottom_width_0_height_0__pin_51_[0]), - .ccff_tail(grid_clb_3_ccff_tail[0])); - - grid_io_top_top grid_io_top_top_1__3_ ( - .prog_clk(prog_clk[0]), - .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[0]), - .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[0]), - .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[0]), - .bottom_width_0_height_0__pin_0_(cbx_1__2__0_top_grid_pin_0_[0]), - .ccff_head(cbx_1__2__0_ccff_tail[0]), - .bottom_width_0_height_0__pin_1_upper(grid_io_top_top_0_bottom_width_0_height_0__pin_1_upper[0]), - .bottom_width_0_height_0__pin_1_lower(grid_io_top_top_0_bottom_width_0_height_0__pin_1_lower[0]), - .ccff_tail(grid_io_top_top_0_ccff_tail[0])); - - grid_io_top_top grid_io_top_top_2__3_ ( - .prog_clk(prog_clk[0]), - .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[1]), - .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[1]), - .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[1]), - .bottom_width_0_height_0__pin_0_(cbx_1__2__1_top_grid_pin_0_[0]), - .ccff_head(cbx_1__2__1_ccff_tail[0]), - .bottom_width_0_height_0__pin_1_upper(grid_io_top_top_1_bottom_width_0_height_0__pin_1_upper[0]), - .bottom_width_0_height_0__pin_1_lower(grid_io_top_top_1_bottom_width_0_height_0__pin_1_lower[0]), - .ccff_tail(grid_io_top_top_1_ccff_tail[0])); - - grid_io_right_right grid_io_right_right_3__1_ ( - .prog_clk(prog_clk[0]), - .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[2]), - .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[2]), - .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[2]), - .left_width_0_height_0__pin_0_(cby_2__1__0_right_grid_pin_0_[0]), - .ccff_head(cby_2__1__0_ccff_tail[0]), - .left_width_0_height_0__pin_1_upper(grid_io_right_right_0_left_width_0_height_0__pin_1_upper[0]), - .left_width_0_height_0__pin_1_lower(grid_io_right_right_0_left_width_0_height_0__pin_1_lower[0]), - .ccff_tail(grid_io_right_right_0_ccff_tail[0])); - - grid_io_right_right grid_io_right_right_3__2_ ( - .prog_clk(prog_clk[0]), - .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[3]), - .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[3]), - .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[3]), - .left_width_0_height_0__pin_0_(cby_2__1__1_right_grid_pin_0_[0]), - .ccff_head(cby_2__1__1_ccff_tail[0]), - .left_width_0_height_0__pin_1_upper(grid_io_right_right_1_left_width_0_height_0__pin_1_upper[0]), - .left_width_0_height_0__pin_1_lower(grid_io_right_right_1_left_width_0_height_0__pin_1_lower[0]), - .ccff_tail(grid_io_right_right_1_ccff_tail[0])); - - grid_io_bottom_bottom grid_io_bottom_bottom_1__0_ ( - .prog_clk(prog_clk[0]), - .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[4:9]), - .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[4:9]), - .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[4:9]), - .top_width_0_height_0__pin_0_(cbx_1__0__0_bottom_grid_pin_0_[0]), - .top_width_0_height_0__pin_2_(cbx_1__0__0_bottom_grid_pin_2_[0]), - .top_width_0_height_0__pin_4_(cbx_1__0__0_bottom_grid_pin_4_[0]), - .top_width_0_height_0__pin_6_(cbx_1__0__0_bottom_grid_pin_6_[0]), - .top_width_0_height_0__pin_8_(cbx_1__0__0_bottom_grid_pin_8_[0]), - .top_width_0_height_0__pin_10_(cbx_1__0__0_bottom_grid_pin_10_[0]), - .ccff_head(cbx_1__0__0_ccff_tail[0]), - .top_width_0_height_0__pin_1_upper(grid_io_bottom_bottom_0_top_width_0_height_0__pin_1_upper[0]), - .top_width_0_height_0__pin_1_lower(grid_io_bottom_bottom_0_top_width_0_height_0__pin_1_lower[0]), - .top_width_0_height_0__pin_3_upper(grid_io_bottom_bottom_0_top_width_0_height_0__pin_3_upper[0]), - .top_width_0_height_0__pin_3_lower(grid_io_bottom_bottom_0_top_width_0_height_0__pin_3_lower[0]), - .top_width_0_height_0__pin_5_upper(grid_io_bottom_bottom_0_top_width_0_height_0__pin_5_upper[0]), - .top_width_0_height_0__pin_5_lower(grid_io_bottom_bottom_0_top_width_0_height_0__pin_5_lower[0]), - .top_width_0_height_0__pin_7_upper(grid_io_bottom_bottom_0_top_width_0_height_0__pin_7_upper[0]), - .top_width_0_height_0__pin_7_lower(grid_io_bottom_bottom_0_top_width_0_height_0__pin_7_lower[0]), - .top_width_0_height_0__pin_9_upper(grid_io_bottom_bottom_0_top_width_0_height_0__pin_9_upper[0]), - .top_width_0_height_0__pin_9_lower(grid_io_bottom_bottom_0_top_width_0_height_0__pin_9_lower[0]), - .top_width_0_height_0__pin_11_upper(grid_io_bottom_bottom_0_top_width_0_height_0__pin_11_upper[0]), - .top_width_0_height_0__pin_11_lower(grid_io_bottom_bottom_0_top_width_0_height_0__pin_11_lower[0]), - .ccff_tail(grid_io_bottom_bottom_0_ccff_tail[0])); - - grid_io_bottom_bottom grid_io_bottom_bottom_2__0_ ( - .prog_clk(prog_clk[0]), - .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[10:15]), - .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[10:15]), - .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[10:15]), - .top_width_0_height_0__pin_0_(cbx_1__0__1_bottom_grid_pin_0_[0]), - .top_width_0_height_0__pin_2_(cbx_1__0__1_bottom_grid_pin_2_[0]), - .top_width_0_height_0__pin_4_(cbx_1__0__1_bottom_grid_pin_4_[0]), - .top_width_0_height_0__pin_6_(cbx_1__0__1_bottom_grid_pin_6_[0]), - .top_width_0_height_0__pin_8_(cbx_1__0__1_bottom_grid_pin_8_[0]), - .top_width_0_height_0__pin_10_(cbx_1__0__1_bottom_grid_pin_10_[0]), - .ccff_head(cbx_1__0__1_ccff_tail[0]), - .top_width_0_height_0__pin_1_upper(grid_io_bottom_bottom_1_top_width_0_height_0__pin_1_upper[0]), - .top_width_0_height_0__pin_1_lower(grid_io_bottom_bottom_1_top_width_0_height_0__pin_1_lower[0]), - .top_width_0_height_0__pin_3_upper(grid_io_bottom_bottom_1_top_width_0_height_0__pin_3_upper[0]), - .top_width_0_height_0__pin_3_lower(grid_io_bottom_bottom_1_top_width_0_height_0__pin_3_lower[0]), - .top_width_0_height_0__pin_5_upper(grid_io_bottom_bottom_1_top_width_0_height_0__pin_5_upper[0]), - .top_width_0_height_0__pin_5_lower(grid_io_bottom_bottom_1_top_width_0_height_0__pin_5_lower[0]), - .top_width_0_height_0__pin_7_upper(grid_io_bottom_bottom_1_top_width_0_height_0__pin_7_upper[0]), - .top_width_0_height_0__pin_7_lower(grid_io_bottom_bottom_1_top_width_0_height_0__pin_7_lower[0]), - .top_width_0_height_0__pin_9_upper(grid_io_bottom_bottom_1_top_width_0_height_0__pin_9_upper[0]), - .top_width_0_height_0__pin_9_lower(grid_io_bottom_bottom_1_top_width_0_height_0__pin_9_lower[0]), - .top_width_0_height_0__pin_11_upper(grid_io_bottom_bottom_1_top_width_0_height_0__pin_11_upper[0]), - .top_width_0_height_0__pin_11_lower(grid_io_bottom_bottom_1_top_width_0_height_0__pin_11_lower[0]), - .ccff_tail(grid_io_bottom_bottom_1_ccff_tail[0])); - - grid_io_left_left grid_io_left_left_0__1_ ( - .prog_clk(prog_clk[0]), - .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[16]), - .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[16]), - .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[16]), - .right_width_0_height_0__pin_0_(cby_0__1__0_left_grid_pin_0_[0]), - .ccff_head(cby_0__1__0_ccff_tail[0]), - .right_width_0_height_0__pin_1_upper(grid_io_left_left_0_right_width_0_height_0__pin_1_upper[0]), - .right_width_0_height_0__pin_1_lower(grid_io_left_left_0_right_width_0_height_0__pin_1_lower[0]), - .ccff_tail(grid_io_left_left_0_ccff_tail[0])); - - grid_io_left_left grid_io_left_left_0__2_ ( - .prog_clk(prog_clk[0]), - .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[17]), - .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[17]), - .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[17]), - .right_width_0_height_0__pin_0_(cby_0__1__1_left_grid_pin_0_[0]), - .ccff_head(cby_0__1__1_ccff_tail[0]), - .right_width_0_height_0__pin_1_upper(grid_io_left_left_1_right_width_0_height_0__pin_1_upper[0]), - .right_width_0_height_0__pin_1_lower(grid_io_left_left_1_right_width_0_height_0__pin_1_lower[0]), - .ccff_tail(grid_io_left_left_1_ccff_tail[0])); - - sb_0__0_ sb_0__0_ ( - .prog_clk(prog_clk[0]), - .chany_top_in(cby_0__1__0_chany_bottom_out[0:19]), - .top_left_grid_pin_1_(grid_io_left_left_0_right_width_0_height_0__pin_1_lower[0]), - .chanx_right_in(cbx_1__0__0_chanx_left_out[0:19]), - .right_bottom_grid_pin_1_(grid_io_bottom_bottom_0_top_width_0_height_0__pin_1_upper[0]), - .right_bottom_grid_pin_3_(grid_io_bottom_bottom_0_top_width_0_height_0__pin_3_upper[0]), - .right_bottom_grid_pin_5_(grid_io_bottom_bottom_0_top_width_0_height_0__pin_5_upper[0]), - .right_bottom_grid_pin_7_(grid_io_bottom_bottom_0_top_width_0_height_0__pin_7_upper[0]), - .right_bottom_grid_pin_9_(grid_io_bottom_bottom_0_top_width_0_height_0__pin_9_upper[0]), - .right_bottom_grid_pin_11_(grid_io_bottom_bottom_0_top_width_0_height_0__pin_11_upper[0]), - .ccff_head(grid_io_bottom_bottom_0_ccff_tail[0]), - .chany_top_out(sb_0__0__0_chany_top_out[0:19]), - .chanx_right_out(sb_0__0__0_chanx_right_out[0:19]), - .ccff_tail(ccff_tail[0])); - - sb_0__1_ sb_0__1_ ( - .prog_clk(prog_clk[0]), - .chany_top_in(cby_0__1__1_chany_bottom_out[0:19]), - .top_left_grid_pin_1_(grid_io_left_left_1_right_width_0_height_0__pin_1_lower[0]), - .chanx_right_in(cbx_1__1__0_chanx_left_out[0:19]), - .right_bottom_grid_pin_34_(grid_clb_0_top_width_0_height_0__pin_34_upper[0]), - .right_bottom_grid_pin_35_(grid_clb_0_top_width_0_height_0__pin_35_upper[0]), - .right_bottom_grid_pin_36_(grid_clb_0_top_width_0_height_0__pin_36_upper[0]), - .right_bottom_grid_pin_37_(grid_clb_0_top_width_0_height_0__pin_37_upper[0]), - .right_bottom_grid_pin_38_(grid_clb_0_top_width_0_height_0__pin_38_upper[0]), - .right_bottom_grid_pin_39_(grid_clb_0_top_width_0_height_0__pin_39_upper[0]), - .right_bottom_grid_pin_40_(grid_clb_0_top_width_0_height_0__pin_40_upper[0]), - .right_bottom_grid_pin_41_(grid_clb_0_top_width_0_height_0__pin_41_upper[0]), - .chany_bottom_in(cby_0__1__0_chany_top_out[0:19]), - .bottom_left_grid_pin_1_(grid_io_left_left_0_right_width_0_height_0__pin_1_upper[0]), - .ccff_head(cbx_1__1__0_ccff_tail[0]), - .chany_top_out(sb_0__1__0_chany_top_out[0:19]), - .chanx_right_out(sb_0__1__0_chanx_right_out[0:19]), - .chany_bottom_out(sb_0__1__0_chany_bottom_out[0:19]), - .ccff_tail(sb_0__1__0_ccff_tail[0])); - - sb_0__2_ sb_0__2_ ( - .prog_clk(prog_clk[0]), - .chanx_right_in(cbx_1__2__0_chanx_left_out[0:19]), - .right_top_grid_pin_1_(grid_io_top_top_0_bottom_width_0_height_0__pin_1_upper[0]), - .right_bottom_grid_pin_34_(grid_clb_1_top_width_0_height_0__pin_34_upper[0]), - .right_bottom_grid_pin_35_(grid_clb_1_top_width_0_height_0__pin_35_upper[0]), - .right_bottom_grid_pin_36_(grid_clb_1_top_width_0_height_0__pin_36_upper[0]), - .right_bottom_grid_pin_37_(grid_clb_1_top_width_0_height_0__pin_37_upper[0]), - .right_bottom_grid_pin_38_(grid_clb_1_top_width_0_height_0__pin_38_upper[0]), - .right_bottom_grid_pin_39_(grid_clb_1_top_width_0_height_0__pin_39_upper[0]), - .right_bottom_grid_pin_40_(grid_clb_1_top_width_0_height_0__pin_40_upper[0]), - .right_bottom_grid_pin_41_(grid_clb_1_top_width_0_height_0__pin_41_upper[0]), - .chany_bottom_in(cby_0__1__1_chany_top_out[0:19]), - .bottom_left_grid_pin_1_(grid_io_left_left_1_right_width_0_height_0__pin_1_upper[0]), - .ccff_head(grid_io_top_top_0_ccff_tail[0]), - .chanx_right_out(sb_0__2__0_chanx_right_out[0:19]), - .chany_bottom_out(sb_0__2__0_chany_bottom_out[0:19]), - .ccff_tail(sb_0__2__0_ccff_tail[0])); - - sb_1__0_ sb_1__0_ ( - .prog_clk(prog_clk[0]), - .chany_top_in(cby_1__1__0_chany_bottom_out[0:19]), - .top_left_grid_pin_42_(grid_clb_0_right_width_0_height_0__pin_42_lower[0]), - .top_left_grid_pin_43_(grid_clb_0_right_width_0_height_0__pin_43_lower[0]), - .top_left_grid_pin_44_(grid_clb_0_right_width_0_height_0__pin_44_lower[0]), - .top_left_grid_pin_45_(grid_clb_0_right_width_0_height_0__pin_45_lower[0]), - .top_left_grid_pin_46_(grid_clb_0_right_width_0_height_0__pin_46_lower[0]), - .top_left_grid_pin_47_(grid_clb_0_right_width_0_height_0__pin_47_lower[0]), - .top_left_grid_pin_48_(grid_clb_0_right_width_0_height_0__pin_48_lower[0]), - .top_left_grid_pin_49_(grid_clb_0_right_width_0_height_0__pin_49_lower[0]), - .chanx_right_in(cbx_1__0__1_chanx_left_out[0:19]), - .right_bottom_grid_pin_1_(grid_io_bottom_bottom_1_top_width_0_height_0__pin_1_upper[0]), - .right_bottom_grid_pin_3_(grid_io_bottom_bottom_1_top_width_0_height_0__pin_3_upper[0]), - .right_bottom_grid_pin_5_(grid_io_bottom_bottom_1_top_width_0_height_0__pin_5_upper[0]), - .right_bottom_grid_pin_7_(grid_io_bottom_bottom_1_top_width_0_height_0__pin_7_upper[0]), - .right_bottom_grid_pin_9_(grid_io_bottom_bottom_1_top_width_0_height_0__pin_9_upper[0]), - .right_bottom_grid_pin_11_(grid_io_bottom_bottom_1_top_width_0_height_0__pin_11_upper[0]), - .chanx_left_in(cbx_1__0__0_chanx_right_out[0:19]), - .left_bottom_grid_pin_1_(grid_io_bottom_bottom_0_top_width_0_height_0__pin_1_lower[0]), - .left_bottom_grid_pin_3_(grid_io_bottom_bottom_0_top_width_0_height_0__pin_3_lower[0]), - .left_bottom_grid_pin_5_(grid_io_bottom_bottom_0_top_width_0_height_0__pin_5_lower[0]), - .left_bottom_grid_pin_7_(grid_io_bottom_bottom_0_top_width_0_height_0__pin_7_lower[0]), - .left_bottom_grid_pin_9_(grid_io_bottom_bottom_0_top_width_0_height_0__pin_9_lower[0]), - .left_bottom_grid_pin_11_(grid_io_bottom_bottom_0_top_width_0_height_0__pin_11_lower[0]), - .ccff_head(grid_io_bottom_bottom_1_ccff_tail[0]), - .chany_top_out(sb_1__0__0_chany_top_out[0:19]), - .chanx_right_out(sb_1__0__0_chanx_right_out[0:19]), - .chanx_left_out(sb_1__0__0_chanx_left_out[0:19]), - .ccff_tail(sb_1__0__0_ccff_tail[0])); - - sb_1__1_ sb_1__1_ ( - .prog_clk(prog_clk[0]), - .chany_top_in(cby_1__1__1_chany_bottom_out[0:19]), - .top_left_grid_pin_42_(grid_clb_1_right_width_0_height_0__pin_42_lower[0]), - .top_left_grid_pin_43_(grid_clb_1_right_width_0_height_0__pin_43_lower[0]), - .top_left_grid_pin_44_(grid_clb_1_right_width_0_height_0__pin_44_lower[0]), - .top_left_grid_pin_45_(grid_clb_1_right_width_0_height_0__pin_45_lower[0]), - .top_left_grid_pin_46_(grid_clb_1_right_width_0_height_0__pin_46_lower[0]), - .top_left_grid_pin_47_(grid_clb_1_right_width_0_height_0__pin_47_lower[0]), - .top_left_grid_pin_48_(grid_clb_1_right_width_0_height_0__pin_48_lower[0]), - .top_left_grid_pin_49_(grid_clb_1_right_width_0_height_0__pin_49_lower[0]), - .chanx_right_in(cbx_1__1__1_chanx_left_out[0:19]), - .right_bottom_grid_pin_34_(grid_clb_2_top_width_0_height_0__pin_34_upper[0]), - .right_bottom_grid_pin_35_(grid_clb_2_top_width_0_height_0__pin_35_upper[0]), - .right_bottom_grid_pin_36_(grid_clb_2_top_width_0_height_0__pin_36_upper[0]), - .right_bottom_grid_pin_37_(grid_clb_2_top_width_0_height_0__pin_37_upper[0]), - .right_bottom_grid_pin_38_(grid_clb_2_top_width_0_height_0__pin_38_upper[0]), - .right_bottom_grid_pin_39_(grid_clb_2_top_width_0_height_0__pin_39_upper[0]), - .right_bottom_grid_pin_40_(grid_clb_2_top_width_0_height_0__pin_40_upper[0]), - .right_bottom_grid_pin_41_(grid_clb_2_top_width_0_height_0__pin_41_upper[0]), - .chany_bottom_in(cby_1__1__0_chany_top_out[0:19]), - .bottom_left_grid_pin_42_(grid_clb_0_right_width_0_height_0__pin_42_upper[0]), - .bottom_left_grid_pin_43_(grid_clb_0_right_width_0_height_0__pin_43_upper[0]), - .bottom_left_grid_pin_44_(grid_clb_0_right_width_0_height_0__pin_44_upper[0]), - .bottom_left_grid_pin_45_(grid_clb_0_right_width_0_height_0__pin_45_upper[0]), - .bottom_left_grid_pin_46_(grid_clb_0_right_width_0_height_0__pin_46_upper[0]), - .bottom_left_grid_pin_47_(grid_clb_0_right_width_0_height_0__pin_47_upper[0]), - .bottom_left_grid_pin_48_(grid_clb_0_right_width_0_height_0__pin_48_upper[0]), - .bottom_left_grid_pin_49_(grid_clb_0_right_width_0_height_0__pin_49_upper[0]), - .chanx_left_in(cbx_1__1__0_chanx_right_out[0:19]), - .left_bottom_grid_pin_34_(grid_clb_0_top_width_0_height_0__pin_34_lower[0]), - .left_bottom_grid_pin_35_(grid_clb_0_top_width_0_height_0__pin_35_lower[0]), - .left_bottom_grid_pin_36_(grid_clb_0_top_width_0_height_0__pin_36_lower[0]), - .left_bottom_grid_pin_37_(grid_clb_0_top_width_0_height_0__pin_37_lower[0]), - .left_bottom_grid_pin_38_(grid_clb_0_top_width_0_height_0__pin_38_lower[0]), - .left_bottom_grid_pin_39_(grid_clb_0_top_width_0_height_0__pin_39_lower[0]), - .left_bottom_grid_pin_40_(grid_clb_0_top_width_0_height_0__pin_40_lower[0]), - .left_bottom_grid_pin_41_(grid_clb_0_top_width_0_height_0__pin_41_lower[0]), - .ccff_head(cbx_1__1__1_ccff_tail[0]), - .chany_top_out(sb_1__1__0_chany_top_out[0:19]), - .chanx_right_out(sb_1__1__0_chanx_right_out[0:19]), - .chany_bottom_out(sb_1__1__0_chany_bottom_out[0:19]), - .chanx_left_out(sb_1__1__0_chanx_left_out[0:19]), - .ccff_tail(sb_1__1__0_ccff_tail[0])); - - sb_1__2_ sb_1__2_ ( - .prog_clk(prog_clk[0]), - .chanx_right_in(cbx_1__2__1_chanx_left_out[0:19]), - .right_top_grid_pin_1_(grid_io_top_top_1_bottom_width_0_height_0__pin_1_upper[0]), - .right_bottom_grid_pin_34_(grid_clb_3_top_width_0_height_0__pin_34_upper[0]), - .right_bottom_grid_pin_35_(grid_clb_3_top_width_0_height_0__pin_35_upper[0]), - .right_bottom_grid_pin_36_(grid_clb_3_top_width_0_height_0__pin_36_upper[0]), - .right_bottom_grid_pin_37_(grid_clb_3_top_width_0_height_0__pin_37_upper[0]), - .right_bottom_grid_pin_38_(grid_clb_3_top_width_0_height_0__pin_38_upper[0]), - .right_bottom_grid_pin_39_(grid_clb_3_top_width_0_height_0__pin_39_upper[0]), - .right_bottom_grid_pin_40_(grid_clb_3_top_width_0_height_0__pin_40_upper[0]), - .right_bottom_grid_pin_41_(grid_clb_3_top_width_0_height_0__pin_41_upper[0]), - .chany_bottom_in(cby_1__1__1_chany_top_out[0:19]), - .bottom_left_grid_pin_42_(grid_clb_1_right_width_0_height_0__pin_42_upper[0]), - .bottom_left_grid_pin_43_(grid_clb_1_right_width_0_height_0__pin_43_upper[0]), - .bottom_left_grid_pin_44_(grid_clb_1_right_width_0_height_0__pin_44_upper[0]), - .bottom_left_grid_pin_45_(grid_clb_1_right_width_0_height_0__pin_45_upper[0]), - .bottom_left_grid_pin_46_(grid_clb_1_right_width_0_height_0__pin_46_upper[0]), - .bottom_left_grid_pin_47_(grid_clb_1_right_width_0_height_0__pin_47_upper[0]), - .bottom_left_grid_pin_48_(grid_clb_1_right_width_0_height_0__pin_48_upper[0]), - .bottom_left_grid_pin_49_(grid_clb_1_right_width_0_height_0__pin_49_upper[0]), - .chanx_left_in(cbx_1__2__0_chanx_right_out[0:19]), - .left_top_grid_pin_1_(grid_io_top_top_0_bottom_width_0_height_0__pin_1_lower[0]), - .left_bottom_grid_pin_34_(grid_clb_1_top_width_0_height_0__pin_34_lower[0]), - .left_bottom_grid_pin_35_(grid_clb_1_top_width_0_height_0__pin_35_lower[0]), - .left_bottom_grid_pin_36_(grid_clb_1_top_width_0_height_0__pin_36_lower[0]), - .left_bottom_grid_pin_37_(grid_clb_1_top_width_0_height_0__pin_37_lower[0]), - .left_bottom_grid_pin_38_(grid_clb_1_top_width_0_height_0__pin_38_lower[0]), - .left_bottom_grid_pin_39_(grid_clb_1_top_width_0_height_0__pin_39_lower[0]), - .left_bottom_grid_pin_40_(grid_clb_1_top_width_0_height_0__pin_40_lower[0]), - .left_bottom_grid_pin_41_(grid_clb_1_top_width_0_height_0__pin_41_lower[0]), - .ccff_head(grid_io_top_top_1_ccff_tail[0]), - .chanx_right_out(sb_1__2__0_chanx_right_out[0:19]), - .chany_bottom_out(sb_1__2__0_chany_bottom_out[0:19]), - .chanx_left_out(sb_1__2__0_chanx_left_out[0:19]), - .ccff_tail(sb_1__2__0_ccff_tail[0])); - - sb_2__0_ sb_2__0_ ( - .prog_clk(prog_clk[0]), - .chany_top_in(cby_2__1__0_chany_bottom_out[0:19]), - .top_left_grid_pin_42_(grid_clb_2_right_width_0_height_0__pin_42_lower[0]), - .top_left_grid_pin_43_(grid_clb_2_right_width_0_height_0__pin_43_lower[0]), - .top_left_grid_pin_44_(grid_clb_2_right_width_0_height_0__pin_44_lower[0]), - .top_left_grid_pin_45_(grid_clb_2_right_width_0_height_0__pin_45_lower[0]), - .top_left_grid_pin_46_(grid_clb_2_right_width_0_height_0__pin_46_lower[0]), - .top_left_grid_pin_47_(grid_clb_2_right_width_0_height_0__pin_47_lower[0]), - .top_left_grid_pin_48_(grid_clb_2_right_width_0_height_0__pin_48_lower[0]), - .top_left_grid_pin_49_(grid_clb_2_right_width_0_height_0__pin_49_lower[0]), - .top_right_grid_pin_1_(grid_io_right_right_0_left_width_0_height_0__pin_1_lower[0]), - .chanx_left_in(cbx_1__0__1_chanx_right_out[0:19]), - .left_bottom_grid_pin_1_(grid_io_bottom_bottom_1_top_width_0_height_0__pin_1_lower[0]), - .left_bottom_grid_pin_3_(grid_io_bottom_bottom_1_top_width_0_height_0__pin_3_lower[0]), - .left_bottom_grid_pin_5_(grid_io_bottom_bottom_1_top_width_0_height_0__pin_5_lower[0]), - .left_bottom_grid_pin_7_(grid_io_bottom_bottom_1_top_width_0_height_0__pin_7_lower[0]), - .left_bottom_grid_pin_9_(grid_io_bottom_bottom_1_top_width_0_height_0__pin_9_lower[0]), - .left_bottom_grid_pin_11_(grid_io_bottom_bottom_1_top_width_0_height_0__pin_11_lower[0]), - .ccff_head(grid_io_right_right_0_ccff_tail[0]), - .chany_top_out(sb_2__0__0_chany_top_out[0:19]), - .chanx_left_out(sb_2__0__0_chanx_left_out[0:19]), - .ccff_tail(sb_2__0__0_ccff_tail[0])); - - sb_2__1_ sb_2__1_ ( - .prog_clk(prog_clk[0]), - .chany_top_in(cby_2__1__1_chany_bottom_out[0:19]), - .top_left_grid_pin_42_(grid_clb_3_right_width_0_height_0__pin_42_lower[0]), - .top_left_grid_pin_43_(grid_clb_3_right_width_0_height_0__pin_43_lower[0]), - .top_left_grid_pin_44_(grid_clb_3_right_width_0_height_0__pin_44_lower[0]), - .top_left_grid_pin_45_(grid_clb_3_right_width_0_height_0__pin_45_lower[0]), - .top_left_grid_pin_46_(grid_clb_3_right_width_0_height_0__pin_46_lower[0]), - .top_left_grid_pin_47_(grid_clb_3_right_width_0_height_0__pin_47_lower[0]), - .top_left_grid_pin_48_(grid_clb_3_right_width_0_height_0__pin_48_lower[0]), - .top_left_grid_pin_49_(grid_clb_3_right_width_0_height_0__pin_49_lower[0]), - .top_right_grid_pin_1_(grid_io_right_right_1_left_width_0_height_0__pin_1_lower[0]), - .chany_bottom_in(cby_2__1__0_chany_top_out[0:19]), - .bottom_right_grid_pin_1_(grid_io_right_right_0_left_width_0_height_0__pin_1_upper[0]), - .bottom_left_grid_pin_42_(grid_clb_2_right_width_0_height_0__pin_42_upper[0]), - .bottom_left_grid_pin_43_(grid_clb_2_right_width_0_height_0__pin_43_upper[0]), - .bottom_left_grid_pin_44_(grid_clb_2_right_width_0_height_0__pin_44_upper[0]), - .bottom_left_grid_pin_45_(grid_clb_2_right_width_0_height_0__pin_45_upper[0]), - .bottom_left_grid_pin_46_(grid_clb_2_right_width_0_height_0__pin_46_upper[0]), - .bottom_left_grid_pin_47_(grid_clb_2_right_width_0_height_0__pin_47_upper[0]), - .bottom_left_grid_pin_48_(grid_clb_2_right_width_0_height_0__pin_48_upper[0]), - .bottom_left_grid_pin_49_(grid_clb_2_right_width_0_height_0__pin_49_upper[0]), - .chanx_left_in(cbx_1__1__1_chanx_right_out[0:19]), - .left_bottom_grid_pin_34_(grid_clb_2_top_width_0_height_0__pin_34_lower[0]), - .left_bottom_grid_pin_35_(grid_clb_2_top_width_0_height_0__pin_35_lower[0]), - .left_bottom_grid_pin_36_(grid_clb_2_top_width_0_height_0__pin_36_lower[0]), - .left_bottom_grid_pin_37_(grid_clb_2_top_width_0_height_0__pin_37_lower[0]), - .left_bottom_grid_pin_38_(grid_clb_2_top_width_0_height_0__pin_38_lower[0]), - .left_bottom_grid_pin_39_(grid_clb_2_top_width_0_height_0__pin_39_lower[0]), - .left_bottom_grid_pin_40_(grid_clb_2_top_width_0_height_0__pin_40_lower[0]), - .left_bottom_grid_pin_41_(grid_clb_2_top_width_0_height_0__pin_41_lower[0]), - .ccff_head(grid_io_right_right_1_ccff_tail[0]), - .chany_top_out(sb_2__1__0_chany_top_out[0:19]), - .chany_bottom_out(sb_2__1__0_chany_bottom_out[0:19]), - .chanx_left_out(sb_2__1__0_chanx_left_out[0:19]), - .ccff_tail(sb_2__1__0_ccff_tail[0])); - - sb_2__2_ sb_2__2_ ( - .prog_clk(prog_clk[0]), - .chany_bottom_in(cby_2__1__1_chany_top_out[0:19]), - .bottom_right_grid_pin_1_(grid_io_right_right_1_left_width_0_height_0__pin_1_upper[0]), - .bottom_left_grid_pin_42_(grid_clb_3_right_width_0_height_0__pin_42_upper[0]), - .bottom_left_grid_pin_43_(grid_clb_3_right_width_0_height_0__pin_43_upper[0]), - .bottom_left_grid_pin_44_(grid_clb_3_right_width_0_height_0__pin_44_upper[0]), - .bottom_left_grid_pin_45_(grid_clb_3_right_width_0_height_0__pin_45_upper[0]), - .bottom_left_grid_pin_46_(grid_clb_3_right_width_0_height_0__pin_46_upper[0]), - .bottom_left_grid_pin_47_(grid_clb_3_right_width_0_height_0__pin_47_upper[0]), - .bottom_left_grid_pin_48_(grid_clb_3_right_width_0_height_0__pin_48_upper[0]), - .bottom_left_grid_pin_49_(grid_clb_3_right_width_0_height_0__pin_49_upper[0]), - .chanx_left_in(cbx_1__2__1_chanx_right_out[0:19]), - .left_top_grid_pin_1_(grid_io_top_top_1_bottom_width_0_height_0__pin_1_lower[0]), - .left_bottom_grid_pin_34_(grid_clb_3_top_width_0_height_0__pin_34_lower[0]), - .left_bottom_grid_pin_35_(grid_clb_3_top_width_0_height_0__pin_35_lower[0]), - .left_bottom_grid_pin_36_(grid_clb_3_top_width_0_height_0__pin_36_lower[0]), - .left_bottom_grid_pin_37_(grid_clb_3_top_width_0_height_0__pin_37_lower[0]), - .left_bottom_grid_pin_38_(grid_clb_3_top_width_0_height_0__pin_38_lower[0]), - .left_bottom_grid_pin_39_(grid_clb_3_top_width_0_height_0__pin_39_lower[0]), - .left_bottom_grid_pin_40_(grid_clb_3_top_width_0_height_0__pin_40_lower[0]), - .left_bottom_grid_pin_41_(grid_clb_3_top_width_0_height_0__pin_41_lower[0]), - .ccff_head(ccff_head[0]), - .chany_bottom_out(sb_2__2__0_chany_bottom_out[0:19]), - .chanx_left_out(sb_2__2__0_chanx_left_out[0:19]), - .ccff_tail(sb_2__2__0_ccff_tail[0])); - - cbx_1__0_ cbx_1__0_ ( - .prog_clk(prog_clk[0]), - .chanx_left_in(sb_0__0__0_chanx_right_out[0:19]), - .chanx_right_in(sb_1__0__0_chanx_left_out[0:19]), - .ccff_head(sb_1__0__0_ccff_tail[0]), - .chanx_left_out(cbx_1__0__0_chanx_left_out[0:19]), - .chanx_right_out(cbx_1__0__0_chanx_right_out[0:19]), - .bottom_grid_pin_0_(cbx_1__0__0_bottom_grid_pin_0_[0]), - .bottom_grid_pin_2_(cbx_1__0__0_bottom_grid_pin_2_[0]), - .bottom_grid_pin_4_(cbx_1__0__0_bottom_grid_pin_4_[0]), - .bottom_grid_pin_6_(cbx_1__0__0_bottom_grid_pin_6_[0]), - .bottom_grid_pin_8_(cbx_1__0__0_bottom_grid_pin_8_[0]), - .bottom_grid_pin_10_(cbx_1__0__0_bottom_grid_pin_10_[0]), - .ccff_tail(cbx_1__0__0_ccff_tail[0])); - - cbx_1__0_ cbx_2__0_ ( - .prog_clk(prog_clk[0]), - .chanx_left_in(sb_1__0__0_chanx_right_out[0:19]), - .chanx_right_in(sb_2__0__0_chanx_left_out[0:19]), - .ccff_head(sb_2__0__0_ccff_tail[0]), - .chanx_left_out(cbx_1__0__1_chanx_left_out[0:19]), - .chanx_right_out(cbx_1__0__1_chanx_right_out[0:19]), - .bottom_grid_pin_0_(cbx_1__0__1_bottom_grid_pin_0_[0]), - .bottom_grid_pin_2_(cbx_1__0__1_bottom_grid_pin_2_[0]), - .bottom_grid_pin_4_(cbx_1__0__1_bottom_grid_pin_4_[0]), - .bottom_grid_pin_6_(cbx_1__0__1_bottom_grid_pin_6_[0]), - .bottom_grid_pin_8_(cbx_1__0__1_bottom_grid_pin_8_[0]), - .bottom_grid_pin_10_(cbx_1__0__1_bottom_grid_pin_10_[0]), - .ccff_tail(cbx_1__0__1_ccff_tail[0])); - - cbx_1__1_ cbx_1__1_ ( - .prog_clk(prog_clk[0]), - .chanx_left_in(sb_0__1__0_chanx_right_out[0:19]), - .chanx_right_in(sb_1__1__0_chanx_left_out[0:19]), - .ccff_head(sb_1__1__0_ccff_tail[0]), - .chanx_left_out(cbx_1__1__0_chanx_left_out[0:19]), - .chanx_right_out(cbx_1__1__0_chanx_right_out[0:19]), - .bottom_grid_pin_0_(cbx_1__1__0_bottom_grid_pin_0_[0]), - .bottom_grid_pin_1_(cbx_1__1__0_bottom_grid_pin_1_[0]), - .bottom_grid_pin_2_(cbx_1__1__0_bottom_grid_pin_2_[0]), - .bottom_grid_pin_3_(cbx_1__1__0_bottom_grid_pin_3_[0]), - .bottom_grid_pin_4_(cbx_1__1__0_bottom_grid_pin_4_[0]), - .bottom_grid_pin_5_(cbx_1__1__0_bottom_grid_pin_5_[0]), - .bottom_grid_pin_6_(cbx_1__1__0_bottom_grid_pin_6_[0]), - .bottom_grid_pin_7_(cbx_1__1__0_bottom_grid_pin_7_[0]), - .bottom_grid_pin_8_(cbx_1__1__0_bottom_grid_pin_8_[0]), - .bottom_grid_pin_9_(cbx_1__1__0_bottom_grid_pin_9_[0]), - .bottom_grid_pin_10_(cbx_1__1__0_bottom_grid_pin_10_[0]), - .bottom_grid_pin_11_(cbx_1__1__0_bottom_grid_pin_11_[0]), - .bottom_grid_pin_12_(cbx_1__1__0_bottom_grid_pin_12_[0]), - .bottom_grid_pin_13_(cbx_1__1__0_bottom_grid_pin_13_[0]), - .bottom_grid_pin_14_(cbx_1__1__0_bottom_grid_pin_14_[0]), - .bottom_grid_pin_15_(cbx_1__1__0_bottom_grid_pin_15_[0]), - .ccff_tail(cbx_1__1__0_ccff_tail[0])); - - cbx_1__1_ cbx_2__1_ ( - .prog_clk(prog_clk[0]), - .chanx_left_in(sb_1__1__0_chanx_right_out[0:19]), - .chanx_right_in(sb_2__1__0_chanx_left_out[0:19]), - .ccff_head(sb_2__1__0_ccff_tail[0]), - .chanx_left_out(cbx_1__1__1_chanx_left_out[0:19]), - .chanx_right_out(cbx_1__1__1_chanx_right_out[0:19]), - .bottom_grid_pin_0_(cbx_1__1__1_bottom_grid_pin_0_[0]), - .bottom_grid_pin_1_(cbx_1__1__1_bottom_grid_pin_1_[0]), - .bottom_grid_pin_2_(cbx_1__1__1_bottom_grid_pin_2_[0]), - .bottom_grid_pin_3_(cbx_1__1__1_bottom_grid_pin_3_[0]), - .bottom_grid_pin_4_(cbx_1__1__1_bottom_grid_pin_4_[0]), - .bottom_grid_pin_5_(cbx_1__1__1_bottom_grid_pin_5_[0]), - .bottom_grid_pin_6_(cbx_1__1__1_bottom_grid_pin_6_[0]), - .bottom_grid_pin_7_(cbx_1__1__1_bottom_grid_pin_7_[0]), - .bottom_grid_pin_8_(cbx_1__1__1_bottom_grid_pin_8_[0]), - .bottom_grid_pin_9_(cbx_1__1__1_bottom_grid_pin_9_[0]), - .bottom_grid_pin_10_(cbx_1__1__1_bottom_grid_pin_10_[0]), - .bottom_grid_pin_11_(cbx_1__1__1_bottom_grid_pin_11_[0]), - .bottom_grid_pin_12_(cbx_1__1__1_bottom_grid_pin_12_[0]), - .bottom_grid_pin_13_(cbx_1__1__1_bottom_grid_pin_13_[0]), - .bottom_grid_pin_14_(cbx_1__1__1_bottom_grid_pin_14_[0]), - .bottom_grid_pin_15_(cbx_1__1__1_bottom_grid_pin_15_[0]), - .ccff_tail(cbx_1__1__1_ccff_tail[0])); - - cbx_1__2_ cbx_1__2_ ( - .prog_clk(prog_clk[0]), - .chanx_left_in(sb_0__2__0_chanx_right_out[0:19]), - .chanx_right_in(sb_1__2__0_chanx_left_out[0:19]), - .ccff_head(sb_1__2__0_ccff_tail[0]), - .chanx_left_out(cbx_1__2__0_chanx_left_out[0:19]), - .chanx_right_out(cbx_1__2__0_chanx_right_out[0:19]), - .top_grid_pin_0_(cbx_1__2__0_top_grid_pin_0_[0]), - .bottom_grid_pin_0_(cbx_1__2__0_bottom_grid_pin_0_[0]), - .bottom_grid_pin_1_(cbx_1__2__0_bottom_grid_pin_1_[0]), - .bottom_grid_pin_2_(cbx_1__2__0_bottom_grid_pin_2_[0]), - .bottom_grid_pin_3_(cbx_1__2__0_bottom_grid_pin_3_[0]), - .bottom_grid_pin_4_(cbx_1__2__0_bottom_grid_pin_4_[0]), - .bottom_grid_pin_5_(cbx_1__2__0_bottom_grid_pin_5_[0]), - .bottom_grid_pin_6_(cbx_1__2__0_bottom_grid_pin_6_[0]), - .bottom_grid_pin_7_(cbx_1__2__0_bottom_grid_pin_7_[0]), - .bottom_grid_pin_8_(cbx_1__2__0_bottom_grid_pin_8_[0]), - .bottom_grid_pin_9_(cbx_1__2__0_bottom_grid_pin_9_[0]), - .bottom_grid_pin_10_(cbx_1__2__0_bottom_grid_pin_10_[0]), - .bottom_grid_pin_11_(cbx_1__2__0_bottom_grid_pin_11_[0]), - .bottom_grid_pin_12_(cbx_1__2__0_bottom_grid_pin_12_[0]), - .bottom_grid_pin_13_(cbx_1__2__0_bottom_grid_pin_13_[0]), - .bottom_grid_pin_14_(cbx_1__2__0_bottom_grid_pin_14_[0]), - .bottom_grid_pin_15_(cbx_1__2__0_bottom_grid_pin_15_[0]), - .ccff_tail(cbx_1__2__0_ccff_tail[0])); - - cbx_1__2_ cbx_2__2_ ( - .prog_clk(prog_clk[0]), - .chanx_left_in(sb_1__2__0_chanx_right_out[0:19]), - .chanx_right_in(sb_2__2__0_chanx_left_out[0:19]), - .ccff_head(sb_2__2__0_ccff_tail[0]), - .chanx_left_out(cbx_1__2__1_chanx_left_out[0:19]), - .chanx_right_out(cbx_1__2__1_chanx_right_out[0:19]), - .top_grid_pin_0_(cbx_1__2__1_top_grid_pin_0_[0]), - .bottom_grid_pin_0_(cbx_1__2__1_bottom_grid_pin_0_[0]), - .bottom_grid_pin_1_(cbx_1__2__1_bottom_grid_pin_1_[0]), - .bottom_grid_pin_2_(cbx_1__2__1_bottom_grid_pin_2_[0]), - .bottom_grid_pin_3_(cbx_1__2__1_bottom_grid_pin_3_[0]), - .bottom_grid_pin_4_(cbx_1__2__1_bottom_grid_pin_4_[0]), - .bottom_grid_pin_5_(cbx_1__2__1_bottom_grid_pin_5_[0]), - .bottom_grid_pin_6_(cbx_1__2__1_bottom_grid_pin_6_[0]), - .bottom_grid_pin_7_(cbx_1__2__1_bottom_grid_pin_7_[0]), - .bottom_grid_pin_8_(cbx_1__2__1_bottom_grid_pin_8_[0]), - .bottom_grid_pin_9_(cbx_1__2__1_bottom_grid_pin_9_[0]), - .bottom_grid_pin_10_(cbx_1__2__1_bottom_grid_pin_10_[0]), - .bottom_grid_pin_11_(cbx_1__2__1_bottom_grid_pin_11_[0]), - .bottom_grid_pin_12_(cbx_1__2__1_bottom_grid_pin_12_[0]), - .bottom_grid_pin_13_(cbx_1__2__1_bottom_grid_pin_13_[0]), - .bottom_grid_pin_14_(cbx_1__2__1_bottom_grid_pin_14_[0]), - .bottom_grid_pin_15_(cbx_1__2__1_bottom_grid_pin_15_[0]), - .ccff_tail(cbx_1__2__1_ccff_tail[0])); - - cby_0__1_ cby_0__1_ ( - .prog_clk(prog_clk[0]), - .chany_bottom_in(sb_0__0__0_chany_top_out[0:19]), - .chany_top_in(sb_0__1__0_chany_bottom_out[0:19]), - .ccff_head(sb_0__1__0_ccff_tail[0]), - .chany_bottom_out(cby_0__1__0_chany_bottom_out[0:19]), - .chany_top_out(cby_0__1__0_chany_top_out[0:19]), - .left_grid_pin_0_(cby_0__1__0_left_grid_pin_0_[0]), - .ccff_tail(cby_0__1__0_ccff_tail[0])); - - cby_0__1_ cby_0__2_ ( - .prog_clk(prog_clk[0]), - .chany_bottom_in(sb_0__1__0_chany_top_out[0:19]), - .chany_top_in(sb_0__2__0_chany_bottom_out[0:19]), - .ccff_head(sb_0__2__0_ccff_tail[0]), - .chany_bottom_out(cby_0__1__1_chany_bottom_out[0:19]), - .chany_top_out(cby_0__1__1_chany_top_out[0:19]), - .left_grid_pin_0_(cby_0__1__1_left_grid_pin_0_[0]), - .ccff_tail(cby_0__1__1_ccff_tail[0])); - - cby_1__1_ cby_1__1_ ( - .prog_clk(prog_clk[0]), - .chany_bottom_in(sb_1__0__0_chany_top_out[0:19]), - .chany_top_in(sb_1__1__0_chany_bottom_out[0:19]), - .ccff_head(grid_clb_0_ccff_tail[0]), - .chany_bottom_out(cby_1__1__0_chany_bottom_out[0:19]), - .chany_top_out(cby_1__1__0_chany_top_out[0:19]), - .left_grid_pin_16_(cby_1__1__0_left_grid_pin_16_[0]), - .left_grid_pin_17_(cby_1__1__0_left_grid_pin_17_[0]), - .left_grid_pin_18_(cby_1__1__0_left_grid_pin_18_[0]), - .left_grid_pin_19_(cby_1__1__0_left_grid_pin_19_[0]), - .left_grid_pin_20_(cby_1__1__0_left_grid_pin_20_[0]), - .left_grid_pin_21_(cby_1__1__0_left_grid_pin_21_[0]), - .left_grid_pin_22_(cby_1__1__0_left_grid_pin_22_[0]), - .left_grid_pin_23_(cby_1__1__0_left_grid_pin_23_[0]), - .left_grid_pin_24_(cby_1__1__0_left_grid_pin_24_[0]), - .left_grid_pin_25_(cby_1__1__0_left_grid_pin_25_[0]), - .left_grid_pin_26_(cby_1__1__0_left_grid_pin_26_[0]), - .left_grid_pin_27_(cby_1__1__0_left_grid_pin_27_[0]), - .left_grid_pin_28_(cby_1__1__0_left_grid_pin_28_[0]), - .left_grid_pin_29_(cby_1__1__0_left_grid_pin_29_[0]), - .left_grid_pin_30_(cby_1__1__0_left_grid_pin_30_[0]), - .left_grid_pin_31_(cby_1__1__0_left_grid_pin_31_[0]), - .ccff_tail(cby_1__1__0_ccff_tail[0])); - - cby_1__1_ cby_1__2_ ( - .prog_clk(prog_clk[0]), - .chany_bottom_in(sb_1__1__0_chany_top_out[0:19]), - .chany_top_in(sb_1__2__0_chany_bottom_out[0:19]), - .ccff_head(grid_clb_1_ccff_tail[0]), - .chany_bottom_out(cby_1__1__1_chany_bottom_out[0:19]), - .chany_top_out(cby_1__1__1_chany_top_out[0:19]), - .left_grid_pin_16_(cby_1__1__1_left_grid_pin_16_[0]), - .left_grid_pin_17_(cby_1__1__1_left_grid_pin_17_[0]), - .left_grid_pin_18_(cby_1__1__1_left_grid_pin_18_[0]), - .left_grid_pin_19_(cby_1__1__1_left_grid_pin_19_[0]), - .left_grid_pin_20_(cby_1__1__1_left_grid_pin_20_[0]), - .left_grid_pin_21_(cby_1__1__1_left_grid_pin_21_[0]), - .left_grid_pin_22_(cby_1__1__1_left_grid_pin_22_[0]), - .left_grid_pin_23_(cby_1__1__1_left_grid_pin_23_[0]), - .left_grid_pin_24_(cby_1__1__1_left_grid_pin_24_[0]), - .left_grid_pin_25_(cby_1__1__1_left_grid_pin_25_[0]), - .left_grid_pin_26_(cby_1__1__1_left_grid_pin_26_[0]), - .left_grid_pin_27_(cby_1__1__1_left_grid_pin_27_[0]), - .left_grid_pin_28_(cby_1__1__1_left_grid_pin_28_[0]), - .left_grid_pin_29_(cby_1__1__1_left_grid_pin_29_[0]), - .left_grid_pin_30_(cby_1__1__1_left_grid_pin_30_[0]), - .left_grid_pin_31_(cby_1__1__1_left_grid_pin_31_[0]), - .ccff_tail(cby_1__1__1_ccff_tail[0])); - - cby_2__1_ cby_2__1_ ( - .prog_clk(prog_clk[0]), - .chany_bottom_in(sb_2__0__0_chany_top_out[0:19]), - .chany_top_in(sb_2__1__0_chany_bottom_out[0:19]), - .ccff_head(grid_clb_2_ccff_tail[0]), - .chany_bottom_out(cby_2__1__0_chany_bottom_out[0:19]), - .chany_top_out(cby_2__1__0_chany_top_out[0:19]), - .right_grid_pin_0_(cby_2__1__0_right_grid_pin_0_[0]), - .left_grid_pin_16_(cby_2__1__0_left_grid_pin_16_[0]), - .left_grid_pin_17_(cby_2__1__0_left_grid_pin_17_[0]), - .left_grid_pin_18_(cby_2__1__0_left_grid_pin_18_[0]), - .left_grid_pin_19_(cby_2__1__0_left_grid_pin_19_[0]), - .left_grid_pin_20_(cby_2__1__0_left_grid_pin_20_[0]), - .left_grid_pin_21_(cby_2__1__0_left_grid_pin_21_[0]), - .left_grid_pin_22_(cby_2__1__0_left_grid_pin_22_[0]), - .left_grid_pin_23_(cby_2__1__0_left_grid_pin_23_[0]), - .left_grid_pin_24_(cby_2__1__0_left_grid_pin_24_[0]), - .left_grid_pin_25_(cby_2__1__0_left_grid_pin_25_[0]), - .left_grid_pin_26_(cby_2__1__0_left_grid_pin_26_[0]), - .left_grid_pin_27_(cby_2__1__0_left_grid_pin_27_[0]), - .left_grid_pin_28_(cby_2__1__0_left_grid_pin_28_[0]), - .left_grid_pin_29_(cby_2__1__0_left_grid_pin_29_[0]), - .left_grid_pin_30_(cby_2__1__0_left_grid_pin_30_[0]), - .left_grid_pin_31_(cby_2__1__0_left_grid_pin_31_[0]), - .ccff_tail(cby_2__1__0_ccff_tail[0])); - - cby_2__1_ cby_2__2_ ( - .prog_clk(prog_clk[0]), - .chany_bottom_in(sb_2__1__0_chany_top_out[0:19]), - .chany_top_in(sb_2__2__0_chany_bottom_out[0:19]), - .ccff_head(grid_clb_3_ccff_tail[0]), - .chany_bottom_out(cby_2__1__1_chany_bottom_out[0:19]), - .chany_top_out(cby_2__1__1_chany_top_out[0:19]), - .right_grid_pin_0_(cby_2__1__1_right_grid_pin_0_[0]), - .left_grid_pin_16_(cby_2__1__1_left_grid_pin_16_[0]), - .left_grid_pin_17_(cby_2__1__1_left_grid_pin_17_[0]), - .left_grid_pin_18_(cby_2__1__1_left_grid_pin_18_[0]), - .left_grid_pin_19_(cby_2__1__1_left_grid_pin_19_[0]), - .left_grid_pin_20_(cby_2__1__1_left_grid_pin_20_[0]), - .left_grid_pin_21_(cby_2__1__1_left_grid_pin_21_[0]), - .left_grid_pin_22_(cby_2__1__1_left_grid_pin_22_[0]), - .left_grid_pin_23_(cby_2__1__1_left_grid_pin_23_[0]), - .left_grid_pin_24_(cby_2__1__1_left_grid_pin_24_[0]), - .left_grid_pin_25_(cby_2__1__1_left_grid_pin_25_[0]), - .left_grid_pin_26_(cby_2__1__1_left_grid_pin_26_[0]), - .left_grid_pin_27_(cby_2__1__1_left_grid_pin_27_[0]), - .left_grid_pin_28_(cby_2__1__1_left_grid_pin_28_[0]), - .left_grid_pin_29_(cby_2__1__1_left_grid_pin_29_[0]), - .left_grid_pin_30_(cby_2__1__1_left_grid_pin_30_[0]), - .left_grid_pin_31_(cby_2__1__1_left_grid_pin_31_[0]), - .ccff_tail(cby_2__1__1_ccff_tail[0])); - - direct_interc direct_interc_0_ ( - .in(grid_clb_1_bottom_width_0_height_0__pin_50_[0]), - .out(direct_interc_0_out[0])); - - direct_interc direct_interc_1_ ( - .in(grid_clb_3_bottom_width_0_height_0__pin_50_[0]), - .out(direct_interc_1_out[0])); - - direct_interc direct_interc_2_ ( - .in(grid_clb_0_bottom_width_0_height_0__pin_50_[0]), - .out(direct_interc_2_out[0])); - - direct_interc direct_interc_3_ ( - .in(grid_clb_1_bottom_width_0_height_0__pin_51_[0]), - .out(direct_interc_3_out[0])); - - direct_interc direct_interc_4_ ( - .in(grid_clb_3_bottom_width_0_height_0__pin_51_[0]), - .out(direct_interc_4_out[0])); - - direct_interc direct_interc_5_ ( - .in(grid_clb_0_bottom_width_0_height_0__pin_51_[0]), - .out(direct_interc_5_out[0])); - -endmodule -// - - - diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/grid_clb.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/grid_clb.v deleted file mode 100644 index 47bb2d6..0000000 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/grid_clb.v +++ /dev/null @@ -1,137 +0,0 @@ - - -module grid_clb -( prog_clk, Test_en, clk, top_width_0_height_0__pin_0_, top_width_0_height_0__pin_1_, top_width_0_height_0__pin_2_, top_width_0_height_0__pin_3_, top_width_0_height_0__pin_4_, top_width_0_height_0__pin_5_, top_width_0_height_0__pin_6_, top_width_0_height_0__pin_7_, top_width_0_height_0__pin_8_, top_width_0_height_0__pin_9_, top_width_0_height_0__pin_10_, top_width_0_height_0__pin_11_, top_width_0_height_0__pin_12_, top_width_0_height_0__pin_13_, top_width_0_height_0__pin_14_, top_width_0_height_0__pin_15_, top_width_0_height_0__pin_32_, top_width_0_height_0__pin_33_, right_width_0_height_0__pin_16_, right_width_0_height_0__pin_17_, right_width_0_height_0__pin_18_, right_width_0_height_0__pin_19_, right_width_0_height_0__pin_20_, right_width_0_height_0__pin_21_, right_width_0_height_0__pin_22_, right_width_0_height_0__pin_23_, right_width_0_height_0__pin_24_, right_width_0_height_0__pin_25_, right_width_0_height_0__pin_26_, right_width_0_height_0__pin_27_, right_width_0_height_0__pin_28_, right_width_0_height_0__pin_29_, right_width_0_height_0__pin_30_, right_width_0_height_0__pin_31_, left_width_0_height_0__pin_52_, ccff_head, top_width_0_height_0__pin_34_upper, top_width_0_height_0__pin_34_lower, top_width_0_height_0__pin_35_upper, top_width_0_height_0__pin_35_lower, top_width_0_height_0__pin_36_upper, top_width_0_height_0__pin_36_lower, top_width_0_height_0__pin_37_upper, top_width_0_height_0__pin_37_lower, top_width_0_height_0__pin_38_upper, top_width_0_height_0__pin_38_lower, top_width_0_height_0__pin_39_upper, top_width_0_height_0__pin_39_lower, top_width_0_height_0__pin_40_upper, top_width_0_height_0__pin_40_lower, top_width_0_height_0__pin_41_upper, top_width_0_height_0__pin_41_lower, right_width_0_height_0__pin_42_upper, right_width_0_height_0__pin_42_lower, right_width_0_height_0__pin_43_upper, right_width_0_height_0__pin_43_lower, right_width_0_height_0__pin_44_upper, right_width_0_height_0__pin_44_lower, right_width_0_height_0__pin_45_upper, right_width_0_height_0__pin_45_lower, right_width_0_height_0__pin_46_upper, right_width_0_height_0__pin_46_lower, right_width_0_height_0__pin_47_upper, right_width_0_height_0__pin_47_lower, right_width_0_height_0__pin_48_upper, right_width_0_height_0__pin_48_lower, right_width_0_height_0__pin_49_upper, right_width_0_height_0__pin_49_lower, bottom_width_0_height_0__pin_50_, bottom_width_0_height_0__pin_51_, ccff_tail, SC_IN_TOP, SC_IN_BOT, SC_OUT_TOP, SC_OUT_BOT ); - input [0:0] prog_clk; - input [0:0] Test_en; - input [0:0] clk; - input [0:0] top_width_0_height_0__pin_0_; - input [0:0] top_width_0_height_0__pin_1_; - input [0:0] top_width_0_height_0__pin_2_; - input [0:0] top_width_0_height_0__pin_3_; - input [0:0] top_width_0_height_0__pin_4_; - input [0:0] top_width_0_height_0__pin_5_; - input [0:0] top_width_0_height_0__pin_6_; - input [0:0] top_width_0_height_0__pin_7_; - input [0:0] top_width_0_height_0__pin_8_; - input [0:0] top_width_0_height_0__pin_9_; - input [0:0] top_width_0_height_0__pin_10_; - input [0:0] top_width_0_height_0__pin_11_; - input [0:0] top_width_0_height_0__pin_12_; - input [0:0] top_width_0_height_0__pin_13_; - input [0:0] top_width_0_height_0__pin_14_; - input [0:0] top_width_0_height_0__pin_15_; - input [0:0] top_width_0_height_0__pin_32_; - input [0:0] top_width_0_height_0__pin_33_; - input [0:0] right_width_0_height_0__pin_16_; - input [0:0] right_width_0_height_0__pin_17_; - input [0:0] right_width_0_height_0__pin_18_; - input [0:0] right_width_0_height_0__pin_19_; - input [0:0] right_width_0_height_0__pin_20_; - input [0:0] right_width_0_height_0__pin_21_; - input [0:0] right_width_0_height_0__pin_22_; - input [0:0] right_width_0_height_0__pin_23_; - input [0:0] right_width_0_height_0__pin_24_; - input [0:0] right_width_0_height_0__pin_25_; - input [0:0] right_width_0_height_0__pin_26_; - input [0:0] right_width_0_height_0__pin_27_; - input [0:0] right_width_0_height_0__pin_28_; - input [0:0] right_width_0_height_0__pin_29_; - input [0:0] right_width_0_height_0__pin_30_; - input [0:0] right_width_0_height_0__pin_31_; - input [0:0] left_width_0_height_0__pin_52_; - input [0:0] ccff_head; - output [0:0] top_width_0_height_0__pin_34_upper; - output [0:0] top_width_0_height_0__pin_34_lower; - output [0:0] top_width_0_height_0__pin_35_upper; - output [0:0] top_width_0_height_0__pin_35_lower; - output [0:0] top_width_0_height_0__pin_36_upper; - output [0:0] top_width_0_height_0__pin_36_lower; - output [0:0] top_width_0_height_0__pin_37_upper; - output [0:0] top_width_0_height_0__pin_37_lower; - output [0:0] top_width_0_height_0__pin_38_upper; - output [0:0] top_width_0_height_0__pin_38_lower; - output [0:0] top_width_0_height_0__pin_39_upper; - output [0:0] top_width_0_height_0__pin_39_lower; - output [0:0] top_width_0_height_0__pin_40_upper; - output [0:0] top_width_0_height_0__pin_40_lower; - output [0:0] top_width_0_height_0__pin_41_upper; - output [0:0] top_width_0_height_0__pin_41_lower; - output [0:0] right_width_0_height_0__pin_42_upper; - output [0:0] right_width_0_height_0__pin_42_lower; - output [0:0] right_width_0_height_0__pin_43_upper; - output [0:0] right_width_0_height_0__pin_43_lower; - output [0:0] right_width_0_height_0__pin_44_upper; - output [0:0] right_width_0_height_0__pin_44_lower; - output [0:0] right_width_0_height_0__pin_45_upper; - output [0:0] right_width_0_height_0__pin_45_lower; - output [0:0] right_width_0_height_0__pin_46_upper; - output [0:0] right_width_0_height_0__pin_46_lower; - output [0:0] right_width_0_height_0__pin_47_upper; - output [0:0] right_width_0_height_0__pin_47_lower; - output [0:0] right_width_0_height_0__pin_48_upper; - output [0:0] right_width_0_height_0__pin_48_lower; - output [0:0] right_width_0_height_0__pin_49_upper; - output [0:0] right_width_0_height_0__pin_49_lower; - output [0:0] bottom_width_0_height_0__pin_50_; - output [0:0] bottom_width_0_height_0__pin_51_; - output [0:0] ccff_tail; - input SC_IN_TOP; - input SC_IN_BOT; - output SC_OUT_TOP; - output SC_OUT_BOT; - - assign top_width_0_height_0__pin_34_lower[0] = top_width_0_height_0__pin_34_upper[0]; - assign top_width_0_height_0__pin_35_lower[0] = top_width_0_height_0__pin_35_upper[0]; - assign top_width_0_height_0__pin_36_lower[0] = top_width_0_height_0__pin_36_upper[0]; - assign top_width_0_height_0__pin_37_lower[0] = top_width_0_height_0__pin_37_upper[0]; - assign top_width_0_height_0__pin_38_lower[0] = top_width_0_height_0__pin_38_upper[0]; - assign top_width_0_height_0__pin_39_lower[0] = top_width_0_height_0__pin_39_upper[0]; - assign top_width_0_height_0__pin_40_lower[0] = top_width_0_height_0__pin_40_upper[0]; - assign top_width_0_height_0__pin_41_lower[0] = top_width_0_height_0__pin_41_upper[0]; - assign right_width_0_height_0__pin_42_lower[0] = right_width_0_height_0__pin_42_upper[0]; - assign right_width_0_height_0__pin_43_lower[0] = right_width_0_height_0__pin_43_upper[0]; - assign right_width_0_height_0__pin_44_lower[0] = right_width_0_height_0__pin_44_upper[0]; - assign right_width_0_height_0__pin_45_lower[0] = right_width_0_height_0__pin_45_upper[0]; - assign right_width_0_height_0__pin_46_lower[0] = right_width_0_height_0__pin_46_upper[0]; - assign right_width_0_height_0__pin_47_lower[0] = right_width_0_height_0__pin_47_upper[0]; - assign right_width_0_height_0__pin_48_lower[0] = right_width_0_height_0__pin_48_upper[0]; - assign right_width_0_height_0__pin_49_lower[0] = right_width_0_height_0__pin_49_upper[0]; - assign SC_IN_TOP = SC_IN_BOT; - assign SC_OUT_TOP = SC_OUT_BOT; - - logical_tile_clb_mode_clb_ - logical_tile_clb_mode_clb__0 - ( - .prog_clk(prog_clk[0]), - .Test_en(Test_en[0]), - .clk(clk[0]), - .clb_I0({ top_width_0_height_0__pin_0_[0], top_width_0_height_0__pin_1_[0], top_width_0_height_0__pin_2_[0] }), - .clb_I0i(top_width_0_height_0__pin_3_[0]), - .clb_I1({ top_width_0_height_0__pin_4_[0], top_width_0_height_0__pin_5_[0], top_width_0_height_0__pin_6_[0] }), - .clb_I1i(top_width_0_height_0__pin_7_[0]), - .clb_I2({ top_width_0_height_0__pin_8_[0], top_width_0_height_0__pin_9_[0], top_width_0_height_0__pin_10_[0] }), - .clb_I2i(top_width_0_height_0__pin_11_[0]), - .clb_I3({ top_width_0_height_0__pin_12_[0], top_width_0_height_0__pin_13_[0], top_width_0_height_0__pin_14_[0] }), - .clb_I3i(top_width_0_height_0__pin_15_[0]), - .clb_I4({ right_width_0_height_0__pin_16_[0], right_width_0_height_0__pin_17_[0], right_width_0_height_0__pin_18_[0] }), - .clb_I4i(right_width_0_height_0__pin_19_[0]), - .clb_I5({ right_width_0_height_0__pin_20_[0], right_width_0_height_0__pin_21_[0], right_width_0_height_0__pin_22_[0] }), - .clb_I5i(right_width_0_height_0__pin_23_[0]), - .clb_I6({ right_width_0_height_0__pin_24_[0], right_width_0_height_0__pin_25_[0], right_width_0_height_0__pin_26_[0] }), - .clb_I6i(right_width_0_height_0__pin_27_[0]), - .clb_I7({ right_width_0_height_0__pin_28_[0], right_width_0_height_0__pin_29_[0], right_width_0_height_0__pin_30_[0] }), - .clb_I7i(right_width_0_height_0__pin_31_[0]), - .clb_regin(top_width_0_height_0__pin_32_[0]), - .clb_sc_in(SC_IN_TOP), - .clb_clk(left_width_0_height_0__pin_52_[0]), - .ccff_head(ccff_head[0]), - .clb_O({ top_width_0_height_0__pin_34_upper[0], top_width_0_height_0__pin_35_upper[0], top_width_0_height_0__pin_36_upper[0], top_width_0_height_0__pin_37_upper[0], top_width_0_height_0__pin_38_upper[0], top_width_0_height_0__pin_39_upper[0], top_width_0_height_0__pin_40_upper[0], top_width_0_height_0__pin_41_upper[0], right_width_0_height_0__pin_42_upper[0], right_width_0_height_0__pin_43_upper[0], right_width_0_height_0__pin_44_upper[0], right_width_0_height_0__pin_45_upper[0], right_width_0_height_0__pin_46_upper[0], right_width_0_height_0__pin_47_upper[0], right_width_0_height_0__pin_48_upper[0], right_width_0_height_0__pin_49_upper[0] }), - .clb_regout(bottom_width_0_height_0__pin_50_[0]), - .clb_sc_out(SC_OUT_BOT), - .ccff_tail(ccff_tail[0]) - ); - - -endmodule - diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_clb_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_clb_.v deleted file mode 100644 index 3a475bf..0000000 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_clb_.v +++ /dev/null @@ -1,630 +0,0 @@ -// -// -// -// -// -// -// -// -`timescale 1ns / 1ps - -// -// -module logical_tile_clb_mode_clb_(prog_clk, - Test_en, - clk, - clb_I0, - clb_I0i, - clb_I1, - clb_I1i, - clb_I2, - clb_I2i, - clb_I3, - clb_I3i, - clb_I4, - clb_I4i, - clb_I5, - clb_I5i, - clb_I6, - clb_I6i, - clb_I7, - clb_I7i, - clb_regin, - clb_sc_in, - clb_clk, - ccff_head, - clb_O, - clb_regout, - clb_sc_out, - ccff_tail); -// -input [0:0] prog_clk; -// -input [0:0] Test_en; -// -input [0:0] clk; -// -input [0:2] clb_I0; -// -input [0:0] clb_I0i; -// -input [0:2] clb_I1; -// -input [0:0] clb_I1i; -// -input [0:2] clb_I2; -// -input [0:0] clb_I2i; -// -input [0:2] clb_I3; -// -input [0:0] clb_I3i; -// -input [0:2] clb_I4; -// -input [0:0] clb_I4i; -// -input [0:2] clb_I5; -// -input [0:0] clb_I5i; -// -input [0:2] clb_I6; -// -input [0:0] clb_I6i; -// -input [0:2] clb_I7; -// -input [0:0] clb_I7i; -// -input [0:0] clb_regin; -// -input [0:0] clb_sc_in; -// -input [0:0] clb_clk; -// -input [0:0] ccff_head; -// -output [0:15] clb_O; -// -output [0:0] clb_regout; -// -output [0:0] clb_sc_out; -// -output [0:0] ccff_tail; - -// -wire [0:2] clb_I0; -wire [0:0] clb_I0i; -wire [0:2] clb_I1; -wire [0:0] clb_I1i; -wire [0:2] clb_I2; -wire [0:0] clb_I2i; -wire [0:2] clb_I3; -wire [0:0] clb_I3i; -wire [0:2] clb_I4; -wire [0:0] clb_I4i; -wire [0:2] clb_I5; -wire [0:0] clb_I5i; -wire [0:2] clb_I6; -wire [0:0] clb_I6i; -wire [0:2] clb_I7; -wire [0:0] clb_I7i; -wire [0:0] clb_regin; -wire [0:0] clb_sc_in; -wire [0:0] clb_clk; -wire [0:15] clb_O; -wire [0:0] clb_regout; -wire [0:0] clb_sc_out; -// - - -// -// - - -wire [0:0] direct_interc_18_out; -wire [0:0] direct_interc_19_out; -wire [0:0] direct_interc_20_out; -wire [0:0] direct_interc_21_out; -wire [0:0] direct_interc_22_out; -wire [0:0] direct_interc_23_out; -wire [0:0] direct_interc_24_out; -wire [0:0] direct_interc_25_out; -wire [0:0] direct_interc_26_out; -wire [0:0] direct_interc_27_out; -wire [0:0] direct_interc_28_out; -wire [0:0] direct_interc_29_out; -wire [0:0] direct_interc_30_out; -wire [0:0] direct_interc_31_out; -wire [0:0] direct_interc_32_out; -wire [0:0] direct_interc_33_out; -wire [0:0] direct_interc_34_out; -wire [0:0] direct_interc_35_out; -wire [0:0] direct_interc_36_out; -wire [0:0] direct_interc_37_out; -wire [0:0] direct_interc_38_out; -wire [0:0] direct_interc_39_out; -wire [0:0] direct_interc_40_out; -wire [0:0] direct_interc_41_out; -wire [0:0] direct_interc_42_out; -wire [0:0] direct_interc_43_out; -wire [0:0] direct_interc_44_out; -wire [0:0] direct_interc_45_out; -wire [0:0] direct_interc_46_out; -wire [0:0] direct_interc_47_out; -wire [0:0] direct_interc_48_out; -wire [0:0] direct_interc_49_out; -wire [0:0] direct_interc_50_out; -wire [0:0] direct_interc_51_out; -wire [0:0] direct_interc_52_out; -wire [0:0] direct_interc_53_out; -wire [0:0] direct_interc_54_out; -wire [0:0] direct_interc_55_out; -wire [0:0] direct_interc_56_out; -wire [0:0] direct_interc_57_out; -wire [0:0] direct_interc_58_out; -wire [0:0] direct_interc_59_out; -wire [0:0] direct_interc_60_out; -wire [0:0] direct_interc_61_out; -wire [0:0] direct_interc_62_out; -wire [0:0] direct_interc_63_out; -wire [0:0] direct_interc_64_out; -wire [0:0] direct_interc_65_out; -wire [0:0] direct_interc_66_out; -wire [0:0] direct_interc_67_out; -wire [0:0] direct_interc_68_out; -wire [0:0] direct_interc_69_out; -wire [0:0] direct_interc_70_out; -wire [0:0] direct_interc_71_out; -wire [0:0] direct_interc_72_out; -wire [0:0] direct_interc_73_out; -wire [0:0] logical_tile_clb_mode_default__fle_0_ccff_tail; -wire [0:1] logical_tile_clb_mode_default__fle_0_fle_out; -wire [0:0] logical_tile_clb_mode_default__fle_0_fle_regout; -wire [0:0] logical_tile_clb_mode_default__fle_0_fle_sc_out; -wire [0:0] logical_tile_clb_mode_default__fle_1_ccff_tail; -wire [0:1] logical_tile_clb_mode_default__fle_1_fle_out; -wire [0:0] logical_tile_clb_mode_default__fle_1_fle_regout; -wire [0:0] logical_tile_clb_mode_default__fle_1_fle_sc_out; -wire [0:0] logical_tile_clb_mode_default__fle_2_ccff_tail; -wire [0:1] logical_tile_clb_mode_default__fle_2_fle_out; -wire [0:0] logical_tile_clb_mode_default__fle_2_fle_regout; -wire [0:0] logical_tile_clb_mode_default__fle_2_fle_sc_out; -wire [0:0] logical_tile_clb_mode_default__fle_3_ccff_tail; -wire [0:1] logical_tile_clb_mode_default__fle_3_fle_out; -wire [0:0] logical_tile_clb_mode_default__fle_3_fle_regout; -wire [0:0] logical_tile_clb_mode_default__fle_3_fle_sc_out; -wire [0:0] logical_tile_clb_mode_default__fle_4_ccff_tail; -wire [0:1] logical_tile_clb_mode_default__fle_4_fle_out; -wire [0:0] logical_tile_clb_mode_default__fle_4_fle_regout; -wire [0:0] logical_tile_clb_mode_default__fle_4_fle_sc_out; -wire [0:0] logical_tile_clb_mode_default__fle_5_ccff_tail; -wire [0:1] logical_tile_clb_mode_default__fle_5_fle_out; -wire [0:0] logical_tile_clb_mode_default__fle_5_fle_regout; -wire [0:0] logical_tile_clb_mode_default__fle_5_fle_sc_out; -wire [0:0] logical_tile_clb_mode_default__fle_6_ccff_tail; -wire [0:1] logical_tile_clb_mode_default__fle_6_fle_out; -wire [0:0] logical_tile_clb_mode_default__fle_6_fle_regout; -wire [0:0] logical_tile_clb_mode_default__fle_6_fle_sc_out; -wire [0:1] logical_tile_clb_mode_default__fle_7_fle_out; -wire [0:0] logical_tile_clb_mode_default__fle_7_fle_regout; -wire [0:0] logical_tile_clb_mode_default__fle_7_fle_sc_out; - -// -// -// -// - - logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_0 ( - .prog_clk(prog_clk[0]), - .Test_en(Test_en[0]), - .clk(clk[0]), - .fle_in({direct_interc_18_out[0], direct_interc_19_out[0], direct_interc_20_out[0], direct_interc_21_out[0]}), - .fle_regin(direct_interc_22_out[0]), - .fle_sc_in(direct_interc_23_out[0]), - .fle_clk(direct_interc_24_out[0]), - .ccff_head(ccff_head[0]), - .fle_out(logical_tile_clb_mode_default__fle_0_fle_out[0:1]), - .fle_regout(logical_tile_clb_mode_default__fle_0_fle_regout[0]), - .fle_sc_out(logical_tile_clb_mode_default__fle_0_fle_sc_out[0]), - .ccff_tail(logical_tile_clb_mode_default__fle_0_ccff_tail[0])); - - logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_1 ( - .prog_clk(prog_clk[0]), - .Test_en(Test_en[0]), - .clk(clk[0]), - .fle_in({direct_interc_25_out[0], direct_interc_26_out[0], direct_interc_27_out[0], direct_interc_28_out[0]}), - .fle_regin(direct_interc_29_out[0]), - .fle_sc_in(direct_interc_30_out[0]), - .fle_clk(direct_interc_31_out[0]), - .ccff_head(logical_tile_clb_mode_default__fle_0_ccff_tail[0]), - .fle_out(logical_tile_clb_mode_default__fle_1_fle_out[0:1]), - .fle_regout(logical_tile_clb_mode_default__fle_1_fle_regout[0]), - .fle_sc_out(logical_tile_clb_mode_default__fle_1_fle_sc_out[0]), - .ccff_tail(logical_tile_clb_mode_default__fle_1_ccff_tail[0])); - - logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_2 ( - .prog_clk(prog_clk[0]), - .Test_en(Test_en[0]), - .clk(clk[0]), - .fle_in({direct_interc_32_out[0], direct_interc_33_out[0], direct_interc_34_out[0], direct_interc_35_out[0]}), - .fle_regin(direct_interc_36_out[0]), - .fle_sc_in(direct_interc_37_out[0]), - .fle_clk(direct_interc_38_out[0]), - .ccff_head(logical_tile_clb_mode_default__fle_1_ccff_tail[0]), - .fle_out(logical_tile_clb_mode_default__fle_2_fle_out[0:1]), - .fle_regout(logical_tile_clb_mode_default__fle_2_fle_regout[0]), - .fle_sc_out(logical_tile_clb_mode_default__fle_2_fle_sc_out[0]), - .ccff_tail(logical_tile_clb_mode_default__fle_2_ccff_tail[0])); - - logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_3 ( - .prog_clk(prog_clk[0]), - .Test_en(Test_en[0]), - .clk(clk[0]), - .fle_in({direct_interc_39_out[0], direct_interc_40_out[0], direct_interc_41_out[0], direct_interc_42_out[0]}), - .fle_regin(direct_interc_43_out[0]), - .fle_sc_in(direct_interc_44_out[0]), - .fle_clk(direct_interc_45_out[0]), - .ccff_head(logical_tile_clb_mode_default__fle_2_ccff_tail[0]), - .fle_out(logical_tile_clb_mode_default__fle_3_fle_out[0:1]), - .fle_regout(logical_tile_clb_mode_default__fle_3_fle_regout[0]), - .fle_sc_out(logical_tile_clb_mode_default__fle_3_fle_sc_out[0]), - .ccff_tail(logical_tile_clb_mode_default__fle_3_ccff_tail[0])); - - logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_4 ( - .prog_clk(prog_clk[0]), - .Test_en(Test_en[0]), - .clk(clk[0]), - .fle_in({direct_interc_46_out[0], direct_interc_47_out[0], direct_interc_48_out[0], direct_interc_49_out[0]}), - .fle_regin(direct_interc_50_out[0]), - .fle_sc_in(direct_interc_51_out[0]), - .fle_clk(direct_interc_52_out[0]), - .ccff_head(logical_tile_clb_mode_default__fle_3_ccff_tail[0]), - .fle_out(logical_tile_clb_mode_default__fle_4_fle_out[0:1]), - .fle_regout(logical_tile_clb_mode_default__fle_4_fle_regout[0]), - .fle_sc_out(logical_tile_clb_mode_default__fle_4_fle_sc_out[0]), - .ccff_tail(logical_tile_clb_mode_default__fle_4_ccff_tail[0])); - - logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_5 ( - .prog_clk(prog_clk[0]), - .Test_en(Test_en[0]), - .clk(clk[0]), - .fle_in({direct_interc_53_out[0], direct_interc_54_out[0], direct_interc_55_out[0], direct_interc_56_out[0]}), - .fle_regin(direct_interc_57_out[0]), - .fle_sc_in(direct_interc_58_out[0]), - .fle_clk(direct_interc_59_out[0]), - .ccff_head(logical_tile_clb_mode_default__fle_4_ccff_tail[0]), - .fle_out(logical_tile_clb_mode_default__fle_5_fle_out[0:1]), - .fle_regout(logical_tile_clb_mode_default__fle_5_fle_regout[0]), - .fle_sc_out(logical_tile_clb_mode_default__fle_5_fle_sc_out[0]), - .ccff_tail(logical_tile_clb_mode_default__fle_5_ccff_tail[0])); - - logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_6 ( - .prog_clk(prog_clk[0]), - .Test_en(Test_en[0]), - .clk(clk[0]), - .fle_in({direct_interc_60_out[0], direct_interc_61_out[0], direct_interc_62_out[0], direct_interc_63_out[0]}), - .fle_regin(direct_interc_64_out[0]), - .fle_sc_in(direct_interc_65_out[0]), - .fle_clk(direct_interc_66_out[0]), - .ccff_head(logical_tile_clb_mode_default__fle_5_ccff_tail[0]), - .fle_out(logical_tile_clb_mode_default__fle_6_fle_out[0:1]), - .fle_regout(logical_tile_clb_mode_default__fle_6_fle_regout[0]), - .fle_sc_out(logical_tile_clb_mode_default__fle_6_fle_sc_out[0]), - .ccff_tail(logical_tile_clb_mode_default__fle_6_ccff_tail[0])); - - logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_7 ( - .prog_clk(prog_clk[0]), - .Test_en(Test_en[0]), - .clk(clk[0]), - .fle_in({direct_interc_67_out[0], direct_interc_68_out[0], direct_interc_69_out[0], direct_interc_70_out[0]}), - .fle_regin(direct_interc_71_out[0]), - .fle_sc_in(direct_interc_72_out[0]), - .fle_clk(direct_interc_73_out[0]), - .ccff_head(logical_tile_clb_mode_default__fle_6_ccff_tail[0]), - .fle_out(logical_tile_clb_mode_default__fle_7_fle_out[0:1]), - .fle_regout(logical_tile_clb_mode_default__fle_7_fle_regout[0]), - .fle_sc_out(logical_tile_clb_mode_default__fle_7_fle_sc_out[0]), - .ccff_tail(ccff_tail[0])); - - direct_interc direct_interc_0_ ( - .in(logical_tile_clb_mode_default__fle_0_fle_out[1]), - .out(clb_O[0])); - - direct_interc direct_interc_1_ ( - .in(logical_tile_clb_mode_default__fle_0_fle_out[0]), - .out(clb_O[1])); - - direct_interc direct_interc_2_ ( - .in(logical_tile_clb_mode_default__fle_1_fle_out[1]), - .out(clb_O[2])); - - direct_interc direct_interc_3_ ( - .in(logical_tile_clb_mode_default__fle_1_fle_out[0]), - .out(clb_O[3])); - - direct_interc direct_interc_4_ ( - .in(logical_tile_clb_mode_default__fle_2_fle_out[1]), - .out(clb_O[4])); - - direct_interc direct_interc_5_ ( - .in(logical_tile_clb_mode_default__fle_2_fle_out[0]), - .out(clb_O[5])); - - direct_interc direct_interc_6_ ( - .in(logical_tile_clb_mode_default__fle_3_fle_out[1]), - .out(clb_O[6])); - - direct_interc direct_interc_7_ ( - .in(logical_tile_clb_mode_default__fle_3_fle_out[0]), - .out(clb_O[7])); - - direct_interc direct_interc_8_ ( - .in(logical_tile_clb_mode_default__fle_4_fle_out[1]), - .out(clb_O[8])); - - direct_interc direct_interc_9_ ( - .in(logical_tile_clb_mode_default__fle_4_fle_out[0]), - .out(clb_O[9])); - - direct_interc direct_interc_10_ ( - .in(logical_tile_clb_mode_default__fle_5_fle_out[1]), - .out(clb_O[10])); - - direct_interc direct_interc_11_ ( - .in(logical_tile_clb_mode_default__fle_5_fle_out[0]), - .out(clb_O[11])); - - direct_interc direct_interc_12_ ( - .in(logical_tile_clb_mode_default__fle_6_fle_out[1]), - .out(clb_O[12])); - - direct_interc direct_interc_13_ ( - .in(logical_tile_clb_mode_default__fle_6_fle_out[0]), - .out(clb_O[13])); - - direct_interc direct_interc_14_ ( - .in(logical_tile_clb_mode_default__fle_7_fle_out[1]), - .out(clb_O[14])); - - direct_interc direct_interc_15_ ( - .in(logical_tile_clb_mode_default__fle_7_fle_out[0]), - .out(clb_O[15])); - - direct_interc direct_interc_16_ ( - .in(logical_tile_clb_mode_default__fle_7_fle_regout[0]), - .out(clb_regout[0])); - - direct_interc direct_interc_17_ ( - .in(logical_tile_clb_mode_default__fle_7_fle_sc_out[0]), - .out(clb_sc_out[0])); - - direct_interc direct_interc_18_ ( - .in(clb_I0[0]), - .out(direct_interc_18_out[0])); - - direct_interc direct_interc_19_ ( - .in(clb_I0[1]), - .out(direct_interc_19_out[0])); - - direct_interc direct_interc_20_ ( - .in(clb_I0[2]), - .out(direct_interc_20_out[0])); - - direct_interc direct_interc_21_ ( - .in(clb_I0i[0]), - .out(direct_interc_21_out[0])); - - direct_interc direct_interc_22_ ( - .in(clb_regin[0]), - .out(direct_interc_22_out[0])); - - direct_interc direct_interc_23_ ( - .in(clb_sc_in[0]), - .out(direct_interc_23_out[0])); - - direct_interc direct_interc_24_ ( - .in(clb_clk[0]), - .out(direct_interc_24_out[0])); - - direct_interc direct_interc_25_ ( - .in(clb_I1[0]), - .out(direct_interc_25_out[0])); - - direct_interc direct_interc_26_ ( - .in(clb_I1[1]), - .out(direct_interc_26_out[0])); - - direct_interc direct_interc_27_ ( - .in(clb_I1[2]), - .out(direct_interc_27_out[0])); - - direct_interc direct_interc_28_ ( - .in(clb_I1i[0]), - .out(direct_interc_28_out[0])); - - direct_interc direct_interc_29_ ( - .in(logical_tile_clb_mode_default__fle_0_fle_regout[0]), - .out(direct_interc_29_out[0])); - - direct_interc direct_interc_30_ ( - .in(logical_tile_clb_mode_default__fle_0_fle_sc_out[0]), - .out(direct_interc_30_out[0])); - - direct_interc direct_interc_31_ ( - .in(clb_clk[0]), - .out(direct_interc_31_out[0])); - - direct_interc direct_interc_32_ ( - .in(clb_I2[0]), - .out(direct_interc_32_out[0])); - - direct_interc direct_interc_33_ ( - .in(clb_I2[1]), - .out(direct_interc_33_out[0])); - - direct_interc direct_interc_34_ ( - .in(clb_I2[2]), - .out(direct_interc_34_out[0])); - - direct_interc direct_interc_35_ ( - .in(clb_I2i[0]), - .out(direct_interc_35_out[0])); - - direct_interc direct_interc_36_ ( - .in(logical_tile_clb_mode_default__fle_1_fle_regout[0]), - .out(direct_interc_36_out[0])); - - direct_interc direct_interc_37_ ( - .in(logical_tile_clb_mode_default__fle_1_fle_sc_out[0]), - .out(direct_interc_37_out[0])); - - direct_interc direct_interc_38_ ( - .in(clb_clk[0]), - .out(direct_interc_38_out[0])); - - direct_interc direct_interc_39_ ( - .in(clb_I3[0]), - .out(direct_interc_39_out[0])); - - direct_interc direct_interc_40_ ( - .in(clb_I3[1]), - .out(direct_interc_40_out[0])); - - direct_interc direct_interc_41_ ( - .in(clb_I3[2]), - .out(direct_interc_41_out[0])); - - direct_interc direct_interc_42_ ( - .in(clb_I3i[0]), - .out(direct_interc_42_out[0])); - - direct_interc direct_interc_43_ ( - .in(logical_tile_clb_mode_default__fle_2_fle_regout[0]), - .out(direct_interc_43_out[0])); - - direct_interc direct_interc_44_ ( - .in(logical_tile_clb_mode_default__fle_2_fle_sc_out[0]), - .out(direct_interc_44_out[0])); - - direct_interc direct_interc_45_ ( - .in(clb_clk[0]), - .out(direct_interc_45_out[0])); - - direct_interc direct_interc_46_ ( - .in(clb_I4[0]), - .out(direct_interc_46_out[0])); - - direct_interc direct_interc_47_ ( - .in(clb_I4[1]), - .out(direct_interc_47_out[0])); - - direct_interc direct_interc_48_ ( - .in(clb_I4[2]), - .out(direct_interc_48_out[0])); - - direct_interc direct_interc_49_ ( - .in(clb_I4i[0]), - .out(direct_interc_49_out[0])); - - direct_interc direct_interc_50_ ( - .in(logical_tile_clb_mode_default__fle_3_fle_regout[0]), - .out(direct_interc_50_out[0])); - - direct_interc direct_interc_51_ ( - .in(logical_tile_clb_mode_default__fle_3_fle_sc_out[0]), - .out(direct_interc_51_out[0])); - - direct_interc direct_interc_52_ ( - .in(clb_clk[0]), - .out(direct_interc_52_out[0])); - - direct_interc direct_interc_53_ ( - .in(clb_I5[0]), - .out(direct_interc_53_out[0])); - - direct_interc direct_interc_54_ ( - .in(clb_I5[1]), - .out(direct_interc_54_out[0])); - - direct_interc direct_interc_55_ ( - .in(clb_I5[2]), - .out(direct_interc_55_out[0])); - - direct_interc direct_interc_56_ ( - .in(clb_I5i[0]), - .out(direct_interc_56_out[0])); - - direct_interc direct_interc_57_ ( - .in(logical_tile_clb_mode_default__fle_4_fle_regout[0]), - .out(direct_interc_57_out[0])); - - direct_interc direct_interc_58_ ( - .in(logical_tile_clb_mode_default__fle_4_fle_sc_out[0]), - .out(direct_interc_58_out[0])); - - direct_interc direct_interc_59_ ( - .in(clb_clk[0]), - .out(direct_interc_59_out[0])); - - direct_interc direct_interc_60_ ( - .in(clb_I6[0]), - .out(direct_interc_60_out[0])); - - direct_interc direct_interc_61_ ( - .in(clb_I6[1]), - .out(direct_interc_61_out[0])); - - direct_interc direct_interc_62_ ( - .in(clb_I6[2]), - .out(direct_interc_62_out[0])); - - direct_interc direct_interc_63_ ( - .in(clb_I6i[0]), - .out(direct_interc_63_out[0])); - - direct_interc direct_interc_64_ ( - .in(logical_tile_clb_mode_default__fle_5_fle_regout[0]), - .out(direct_interc_64_out[0])); - - direct_interc direct_interc_65_ ( - .in(logical_tile_clb_mode_default__fle_5_fle_sc_out[0]), - .out(direct_interc_65_out[0])); - - direct_interc direct_interc_66_ ( - .in(clb_clk[0]), - .out(direct_interc_66_out[0])); - - direct_interc direct_interc_67_ ( - .in(clb_I7[0]), - .out(direct_interc_67_out[0])); - - direct_interc direct_interc_68_ ( - .in(clb_I7[1]), - .out(direct_interc_68_out[0])); - - direct_interc direct_interc_69_ ( - .in(clb_I7[2]), - .out(direct_interc_69_out[0])); - - direct_interc direct_interc_70_ ( - .in(clb_I7i[0]), - .out(direct_interc_70_out[0])); - - direct_interc direct_interc_71_ ( - .in(logical_tile_clb_mode_default__fle_6_fle_regout[0]), - .out(direct_interc_71_out[0])); - - direct_interc direct_interc_72_ ( - .in(logical_tile_clb_mode_default__fle_6_fle_sc_out[0]), - .out(direct_interc_72_out[0])); - - direct_interc direct_interc_73_ ( - .in(clb_clk[0]), - .out(direct_interc_73_out[0])); - -endmodule -// - - -// diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle.v deleted file mode 100644 index 7eb2470..0000000 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle.v +++ /dev/null @@ -1,143 +0,0 @@ -// -// -// -// -// -// -// -// -`timescale 1ns / 1ps - -// -// -module logical_tile_clb_mode_default__fle(prog_clk, - Test_en, - clk, - fle_in, - fle_regin, - fle_sc_in, - fle_clk, - ccff_head, - fle_out, - fle_regout, - fle_sc_out, - ccff_tail); -// -input [0:0] prog_clk; -// -input [0:0] Test_en; -// -input [0:0] clk; -// -input [0:3] fle_in; -// -input [0:0] fle_regin; -// -input [0:0] fle_sc_in; -// -input [0:0] fle_clk; -// -input [0:0] ccff_head; -// -output [0:1] fle_out; -// -output [0:0] fle_regout; -// -output [0:0] fle_sc_out; -// -output [0:0] ccff_tail; - -// -wire [0:3] fle_in; -wire [0:0] fle_regin; -wire [0:0] fle_sc_in; -wire [0:0] fle_clk; -wire [0:1] fle_out; -wire [0:0] fle_regout; -wire [0:0] fle_sc_out; -// - - -// -// - - -wire [0:0] direct_interc_10_out; -wire [0:0] direct_interc_4_out; -wire [0:0] direct_interc_5_out; -wire [0:0] direct_interc_6_out; -wire [0:0] direct_interc_7_out; -wire [0:0] direct_interc_8_out; -wire [0:0] direct_interc_9_out; -wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_out; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_regout; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_sc_out; - -// -// -// -// - - logical_tile_clb_mode_default__fle_mode_physical__fabric logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( - .prog_clk(prog_clk[0]), - .Test_en(Test_en[0]), - .clk(clk[0]), - .fabric_in({direct_interc_4_out[0], direct_interc_5_out[0], direct_interc_6_out[0], direct_interc_7_out[0]}), - .fabric_regin(direct_interc_8_out[0]), - .fabric_sc_in(direct_interc_9_out[0]), - .fabric_clk(direct_interc_10_out[0]), - .ccff_head(ccff_head[0]), - .fabric_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_out[0:1]), - .fabric_regout(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_regout[0]), - .fabric_sc_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_sc_out[0]), - .ccff_tail(ccff_tail[0])); - - direct_interc direct_interc_0_ ( - .in(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_out[0]), - .out(fle_out[0])); - - direct_interc direct_interc_1_ ( - .in(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_out[1]), - .out(fle_out[1])); - - direct_interc direct_interc_2_ ( - .in(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_regout[0]), - .out(fle_regout[0])); - - direct_interc direct_interc_3_ ( - .in(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_sc_out[0]), - .out(fle_sc_out[0])); - - direct_interc direct_interc_4_ ( - .in(fle_in[0]), - .out(direct_interc_4_out[0])); - - direct_interc direct_interc_5_ ( - .in(fle_in[1]), - .out(direct_interc_5_out[0])); - - direct_interc direct_interc_6_ ( - .in(fle_in[2]), - .out(direct_interc_6_out[0])); - - direct_interc direct_interc_7_ ( - .in(fle_in[3]), - .out(direct_interc_7_out[0])); - - direct_interc direct_interc_8_ ( - .in(fle_regin[0]), - .out(direct_interc_8_out[0])); - - direct_interc direct_interc_9_ ( - .in(fle_sc_in[0]), - .out(direct_interc_9_out[0])); - - direct_interc direct_interc_10_ ( - .in(fle_clk[0]), - .out(direct_interc_10_out[0])); - -endmodule -// - - -// diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v deleted file mode 100644 index 6fd6b63..0000000 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v +++ /dev/null @@ -1,200 +0,0 @@ -// -// -// -// -// -// -// -// -`timescale 1ns / 1ps - -// -// -module logical_tile_clb_mode_default__fle_mode_physical__fabric(prog_clk, - Test_en, - clk, - fabric_in, - fabric_regin, - fabric_sc_in, - fabric_clk, - ccff_head, - fabric_out, - fabric_regout, - fabric_sc_out, - ccff_tail); -// -input [0:0] prog_clk; -// -input [0:0] Test_en; -// -input [0:0] clk; -// -input [0:3] fabric_in; -// -input [0:0] fabric_regin; -// -input [0:0] fabric_sc_in; -// -input [0:0] fabric_clk; -// -input [0:0] ccff_head; -// -output [0:1] fabric_out; -// -output [0:0] fabric_regout; -// -output [0:0] fabric_sc_out; -// -output [0:0] ccff_tail; - -// -wire [0:3] fabric_in; -wire [0:0] fabric_regin; -wire [0:0] fabric_sc_in; -wire [0:0] fabric_clk; -wire [0:1] fabric_out; -wire [0:0] fabric_regout; -wire [0:0] fabric_sc_out; -// - - -// -// - - -wire [0:0] direct_interc_10_out; -wire [0:0] direct_interc_2_out; -wire [0:0] direct_interc_3_out; -wire [0:0] direct_interc_4_out; -wire [0:0] direct_interc_5_out; -wire [0:0] direct_interc_6_out; -wire [0:0] direct_interc_7_out; -wire [0:0] direct_interc_8_out; -wire [0:0] direct_interc_9_out; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail; -wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out; -wire [0:1] mux_fabric_out_0_undriven_sram_inv; -wire [0:1] mux_fabric_out_1_undriven_sram_inv; -wire [0:1] mux_ff_0_D_0_undriven_sram_inv; -wire [0:1] mux_tree_size2_0_sram; -wire [0:1] mux_tree_size2_1_sram; -wire [0:0] mux_tree_size2_2_out; -wire [0:1] mux_tree_size2_2_sram; -wire [0:0] mux_tree_size2_mem_0_ccff_tail; -wire [0:0] mux_tree_size2_mem_1_ccff_tail; - -// -// -// -// - - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( - .prog_clk(prog_clk[0]), - .frac_logic_in({direct_interc_2_out[0], direct_interc_3_out[0], direct_interc_4_out[0], direct_interc_5_out[0]}), - .ccff_head(ccff_head[0]), - .frac_logic_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0:1]), - .ccff_tail(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail[0])); - - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( - .Test_en(Test_en[0]), - .clk(clk[0]), - .ff_D(mux_tree_size2_2_out[0]), - .ff_DI(direct_interc_6_out[0]), - .ff_Q(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0]), - .ff_clk(direct_interc_7_out[0])); - - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( - .Test_en(Test_en[0]), - .clk(clk[0]), - .ff_D(direct_interc_8_out[0]), - .ff_DI(direct_interc_9_out[0]), - .ff_Q(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q[0]), - .ff_clk(direct_interc_10_out[0])); - - mux_tree_size2 mux_fabric_out_0 ( - .in({logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0], logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0]}), - .sram(mux_tree_size2_0_sram[0:1]), - .sram_inv(mux_fabric_out_0_undriven_sram_inv[0:1]), - .out(fabric_out[0])); - - mux_tree_size2 mux_fabric_out_1 ( - .in({logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q[0], logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1]}), - .sram(mux_tree_size2_1_sram[0:1]), - .sram_inv(mux_fabric_out_1_undriven_sram_inv[0:1]), - .out(fabric_out[1])); - - mux_tree_size2 mux_ff_0_D_0 ( - .in({logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0], fabric_regin[0]}), - .sram(mux_tree_size2_2_sram[0:1]), - .sram_inv(mux_ff_0_D_0_undriven_sram_inv[0:1]), - .out(mux_tree_size2_2_out[0])); - - mux_tree_size2_mem mem_fabric_out_0 ( - .prog_clk(prog_clk[0]), - .ccff_head(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail[0]), - .ccff_tail(mux_tree_size2_mem_0_ccff_tail[0]), - .mem_out(mux_tree_size2_0_sram[0:1])); - - mux_tree_size2_mem mem_fabric_out_1 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_size2_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_size2_mem_1_ccff_tail[0]), - .mem_out(mux_tree_size2_1_sram[0:1])); - - mux_tree_size2_mem mem_ff_0_D_0 ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_size2_mem_1_ccff_tail[0]), - .ccff_tail(ccff_tail[0]), - .mem_out(mux_tree_size2_2_sram[0:1])); - - direct_interc direct_interc_0_ ( - .in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q[0]), - .out(fabric_regout[0])); - - direct_interc direct_interc_1_ ( - .in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q[0]), - .out(fabric_sc_out[0])); - - direct_interc direct_interc_2_ ( - .in(fabric_in[0]), - .out(direct_interc_2_out[0])); - - direct_interc direct_interc_3_ ( - .in(fabric_in[1]), - .out(direct_interc_3_out[0])); - - direct_interc direct_interc_4_ ( - .in(fabric_in[2]), - .out(direct_interc_4_out[0])); - - direct_interc direct_interc_5_ ( - .in(fabric_in[3]), - .out(direct_interc_5_out[0])); - - direct_interc direct_interc_6_ ( - .in(fabric_sc_in[0]), - .out(direct_interc_6_out[0])); - - direct_interc direct_interc_7_ ( - .in(fabric_clk[0]), - .out(direct_interc_7_out[0])); - - direct_interc direct_interc_8_ ( - .in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1]), - .out(direct_interc_8_out[0])); - - direct_interc direct_interc_9_ ( - .in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0]), - .out(direct_interc_9_out[0])); - - direct_interc direct_interc_10_ ( - .in(fabric_clk[0]), - .out(direct_interc_10_out[0])); - -endmodule -// - - -// diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v deleted file mode 100644 index e484d05..0000000 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v +++ /dev/null @@ -1,59 +0,0 @@ -// -// -// -// -// -// -// -// -`timescale 1ns / 1ps - -// -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff(Test_en, - clk, - ff_D, - ff_DI, - ff_Q, - ff_clk); -// -input [0:0] Test_en; -// -input [0:0] clk; -// -input [0:0] ff_D; -// -input [0:0] ff_DI; -// -output [0:0] ff_Q; -// -input [0:0] ff_clk; - -// -wire [0:0] ff_D; -wire [0:0] ff_DI; -wire [0:0] ff_Q; -wire [0:0] ff_clk; -// - - -// -// - - - -// -// -// -// - - sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( - .SCE(Test_en[0]), - .CLK(clk[0]), - .D(ff_D[0]), - .SCD(ff_DI[0]), - .Q(ff_Q[0])); - -endmodule -// - - diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.v deleted file mode 100644 index fc0f064..0000000 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.v +++ /dev/null @@ -1,98 +0,0 @@ -// -// -// -// -// -// -// -// -`timescale 1ns / 1ps - -// -// -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic(prog_clk, - frac_logic_in, - ccff_head, - frac_logic_out, - ccff_tail); -// -input [0:0] prog_clk; -// -input [0:3] frac_logic_in; -// -input [0:0] ccff_head; -// -output [0:1] frac_logic_out; -// -output [0:0] ccff_tail; - -// -wire [0:3] frac_logic_in; -wire [0:1] frac_logic_out; -// - - -// -// - - -wire [0:0] direct_interc_1_out; -wire [0:0] direct_interc_2_out; -wire [0:0] direct_interc_3_out; -wire [0:0] direct_interc_4_out; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail; -wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out; -wire [0:1] mux_frac_logic_out_0_undriven_sram_inv; -wire [0:1] mux_tree_size2_0_sram; - -// -// -// -// - - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( - .prog_clk(prog_clk[0]), - .frac_lut4_in({direct_interc_1_out[0], direct_interc_2_out[0], direct_interc_3_out[0], direct_interc_4_out[0]}), - .ccff_head(ccff_head[0]), - .frac_lut4_lut3_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0:1]), - .frac_lut4_lut4_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0]), - .ccff_tail(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail[0])); - - mux_tree_size2 mux_frac_logic_out_0 ( - .in({logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0], logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0]}), - .sram(mux_tree_size2_0_sram[0:1]), - .sram_inv(mux_frac_logic_out_0_undriven_sram_inv[0:1]), - .out(frac_logic_out[0])); - - mux_tree_size2_mem mem_frac_logic_out_0 ( - .prog_clk(prog_clk[0]), - .ccff_head(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail[0]), - .ccff_tail(ccff_tail[0]), - .mem_out(mux_tree_size2_0_sram[0:1])); - - direct_interc direct_interc_0_ ( - .in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[1]), - .out(frac_logic_out[1])); - - direct_interc direct_interc_1_ ( - .in(frac_logic_in[0]), - .out(direct_interc_1_out[0])); - - direct_interc direct_interc_2_ ( - .in(frac_logic_in[1]), - .out(direct_interc_2_out[0])); - - direct_interc direct_interc_3_ ( - .in(frac_logic_in[2]), - .out(direct_interc_3_out[0])); - - direct_interc direct_interc_4_ ( - .in(frac_logic_in[3]), - .out(direct_interc_4_out[0])); - -endmodule -// - - -// diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4.v deleted file mode 100644 index ba910ab..0000000 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4.v +++ /dev/null @@ -1,70 +0,0 @@ -// -// -// -// -// -// -// -// -`timescale 1ns / 1ps - -// -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4(prog_clk, - frac_lut4_in, - ccff_head, - frac_lut4_lut3_out, - frac_lut4_lut4_out, - ccff_tail); -// -input [0:0] prog_clk; -// -input [0:3] frac_lut4_in; -// -input [0:0] ccff_head; -// -output [0:1] frac_lut4_lut3_out; -// -output [0:0] frac_lut4_lut4_out; -// -output [0:0] ccff_tail; - -// -wire [0:3] frac_lut4_in; -wire [0:1] frac_lut4_lut3_out; -wire [0:0] frac_lut4_lut4_out; -// - - -// -// - - -wire [0:0] frac_lut4_0__undriven_mode_inv; -wire [0:15] frac_lut4_0__undriven_sram_inv; -wire [0:0] frac_lut4_0_mode; -wire [0:15] frac_lut4_0_sram; - -// -// -// -// - - frac_lut4 frac_lut4_0_ ( - .in(frac_lut4_in[0:3]), - .sram(frac_lut4_0_sram[0:15]), - .sram_inv(frac_lut4_0__undriven_sram_inv[0:15]), - .mode(frac_lut4_0_mode[0]), - .mode_inv(frac_lut4_0__undriven_mode_inv[0]), - .lut3_out(frac_lut4_lut3_out[0:1]), - .lut4_out(frac_lut4_lut4_out[0])); - - frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem ( - .prog_clk(prog_clk[0]), - .ccff_head(ccff_head[0]), - .ccff_tail(ccff_tail[0]), - .mem_out({frac_lut4_0_sram[0:15], frac_lut4_0_mode[0]})); - -endmodule -// - - diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_io_mode_io_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_io_mode_io_.v deleted file mode 100644 index ae105cb..0000000 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_io_mode_io_.v +++ /dev/null @@ -1,78 +0,0 @@ -// -// -// -// -// -// -// -// -`timescale 1ns / 1ps - -// -// -module logical_tile_io_mode_io_(prog_clk, - gfpga_pad_EMBEDDED_IO_SOC_IN, - gfpga_pad_EMBEDDED_IO_SOC_OUT, - gfpga_pad_EMBEDDED_IO_SOC_DIR, - io_outpad, - ccff_head, - io_inpad, - ccff_tail); -// -input [0:0] prog_clk; -// -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN; -// -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT; -// -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR; -// -input [0:0] io_outpad; -// -input [0:0] ccff_head; -// -output [0:0] io_inpad; -// -output [0:0] ccff_tail; - -// -wire [0:0] io_outpad; -wire [0:0] io_inpad; -// - - -// -// - - -wire [0:0] direct_interc_1_out; -wire [0:0] logical_tile_io_mode_physical__iopad_0_iopad_inpad; - -// -// -// -// - - logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( - .prog_clk(prog_clk[0]), - .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[0]), - .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[0]), - .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[0]), - .iopad_outpad(direct_interc_1_out[0]), - .ccff_head(ccff_head[0]), - .iopad_inpad(logical_tile_io_mode_physical__iopad_0_iopad_inpad[0]), - .ccff_tail(ccff_tail[0])); - - direct_interc direct_interc_0_ ( - .in(logical_tile_io_mode_physical__iopad_0_iopad_inpad[0]), - .out(io_inpad[0])); - - direct_interc direct_interc_1_ ( - .in(io_outpad[0]), - .out(direct_interc_1_out[0])); - -endmodule -// - - -// diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_io_mode_physical__iopad.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_io_mode_physical__iopad.v deleted file mode 100644 index 2a2d521..0000000 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/logical_tile_io_mode_physical__iopad.v +++ /dev/null @@ -1,71 +0,0 @@ -// -// -// -// -// -// -// -// -`timescale 1ns / 1ps - -// -module logical_tile_io_mode_physical__iopad(prog_clk, - gfpga_pad_EMBEDDED_IO_SOC_IN, - gfpga_pad_EMBEDDED_IO_SOC_OUT, - gfpga_pad_EMBEDDED_IO_SOC_DIR, - iopad_outpad, - ccff_head, - iopad_inpad, - ccff_tail); -// -input [0:0] prog_clk; -// -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN; -// -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT; -// -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR; -// -input [0:0] iopad_outpad; -// -input [0:0] ccff_head; -// -output [0:0] iopad_inpad; -// -output [0:0] ccff_tail; - -// -wire [0:0] iopad_outpad; -wire [0:0] iopad_inpad; -// - - -// -// - - -wire [0:0] EMBEDDED_IO_0_en; - -// -// -// -// - - EMBEDDED_IO EMBEDDED_IO_0_ ( - .SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[0]), - .SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[0]), - .SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[0]), - .FPGA_OUT(iopad_outpad[0]), - .FPGA_DIR(EMBEDDED_IO_0_en[0]), - .FPGA_IN(iopad_inpad[0])); - - EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( - .prog_clk(prog_clk[0]), - .ccff_head(ccff_head[0]), - .ccff_tail(ccff_tail[0]), - .mem_out(EMBEDDED_IO_0_en[0])); - -endmodule -// - - diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cbx_1__0_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cbx_1__0_.v deleted file mode 100644 index be730ed..0000000 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cbx_1__0_.v +++ /dev/null @@ -1,321 +0,0 @@ - - -module cbx_1__0_ -( prog_clk, chanx_left_in, chanx_right_in, ccff_head, chanx_left_out, chanx_right_out, bottom_grid_pin_0_, bottom_grid_pin_2_, bottom_grid_pin_4_, bottom_grid_pin_6_, bottom_grid_pin_8_, bottom_grid_pin_10_, ccff_tail, gfpga_pad_EMBEDDED_IO_SOC_IN, gfpga_pad_EMBEDDED_IO_SOC_OUT, gfpga_pad_EMBEDDED_IO_SOC_DIR, top_width_0_height_0__pin_0_, top_width_0_height_0__pin_2_, top_width_0_height_0__pin_4_, top_width_0_height_0__pin_6_, top_width_0_height_0__pin_8_, top_width_0_height_0__pin_10_, top_width_0_height_0__pin_1_upper, top_width_0_height_0__pin_1_lower, top_width_0_height_0__pin_3_upper, top_width_0_height_0__pin_3_lower, top_width_0_height_0__pin_5_upper, top_width_0_height_0__pin_5_lower, top_width_0_height_0__pin_7_upper, top_width_0_height_0__pin_7_lower, top_width_0_height_0__pin_9_upper, top_width_0_height_0__pin_9_lower, top_width_0_height_0__pin_11_upper, top_width_0_height_0__pin_11_lower, SC_IN_TOP, SC_IN_BOT, SC_OUT_TOP, SC_OUT_BOT ); - input [0:0] prog_clk; - input [0:19] chanx_left_in; - input [0:19] chanx_right_in; - input [0:0] ccff_head; - output [0:19] chanx_left_out; - output [0:19] chanx_right_out; - output [0:0] bottom_grid_pin_0_; - output [0:0] bottom_grid_pin_2_; - output [0:0] bottom_grid_pin_4_; - output [0:0] bottom_grid_pin_6_; - output [0:0] bottom_grid_pin_8_; - output [0:0] bottom_grid_pin_10_; - output [0:0] ccff_tail; - input [0:5] gfpga_pad_EMBEDDED_IO_SOC_IN; - output [0:5] gfpga_pad_EMBEDDED_IO_SOC_OUT; - output [0:5] gfpga_pad_EMBEDDED_IO_SOC_DIR; - input [0:0] top_width_0_height_0__pin_0_; - input [0:0] top_width_0_height_0__pin_2_; - input [0:0] top_width_0_height_0__pin_4_; - input [0:0] top_width_0_height_0__pin_6_; - input [0:0] top_width_0_height_0__pin_8_; - input [0:0] top_width_0_height_0__pin_10_; - output [0:0] top_width_0_height_0__pin_1_upper; - output [0:0] top_width_0_height_0__pin_1_lower; - output [0:0] top_width_0_height_0__pin_3_upper; - output [0:0] top_width_0_height_0__pin_3_lower; - output [0:0] top_width_0_height_0__pin_5_upper; - output [0:0] top_width_0_height_0__pin_5_lower; - output [0:0] top_width_0_height_0__pin_7_upper; - output [0:0] top_width_0_height_0__pin_7_lower; - output [0:0] top_width_0_height_0__pin_9_upper; - output [0:0] top_width_0_height_0__pin_9_lower; - output [0:0] top_width_0_height_0__pin_11_upper; - output [0:0] top_width_0_height_0__pin_11_lower; - input SC_IN_TOP; - input SC_IN_BOT; - output SC_OUT_TOP; - output SC_OUT_BOT; - - wire [0:3] mux_top_ipin_0_undriven_sram_inv; - wire [0:3] mux_top_ipin_1_undriven_sram_inv; - wire [0:3] mux_top_ipin_2_undriven_sram_inv; - wire [0:3] mux_top_ipin_3_undriven_sram_inv; - wire [0:3] mux_top_ipin_4_undriven_sram_inv; - wire [0:3] mux_top_ipin_5_undriven_sram_inv; - wire [0:3] mux_tree_tapbuf_size10_0_sram; - wire [0:3] mux_tree_tapbuf_size10_1_sram; - wire [0:3] mux_tree_tapbuf_size10_2_sram; - wire [0:3] mux_tree_tapbuf_size10_3_sram; - wire [0:3] mux_tree_tapbuf_size10_4_sram; - wire [0:3] mux_tree_tapbuf_size10_5_sram; - wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail; - wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail; - wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail; - wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail; - wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail; - wire ccff_tail_mid; - wire [0:0] logical_tile_io_mode_io__0_ccff_tail; - wire [0:0] logical_tile_io_mode_io__1_ccff_tail; - wire [0:0] logical_tile_io_mode_io__2_ccff_tail; - wire [0:0] logical_tile_io_mode_io__3_ccff_tail; - wire [0:0] logical_tile_io_mode_io__4_ccff_tail; - assign chanx_right_out[0] = chanx_left_in[0]; - assign chanx_right_out[1] = chanx_left_in[1]; - assign chanx_right_out[2] = chanx_left_in[2]; - assign chanx_right_out[3] = chanx_left_in[3]; - assign chanx_right_out[4] = chanx_left_in[4]; - assign chanx_right_out[5] = chanx_left_in[5]; - assign chanx_right_out[6] = chanx_left_in[6]; - assign chanx_right_out[7] = chanx_left_in[7]; - assign chanx_right_out[8] = chanx_left_in[8]; - assign chanx_right_out[9] = chanx_left_in[9]; - assign chanx_right_out[10] = chanx_left_in[10]; - assign chanx_right_out[11] = chanx_left_in[11]; - assign chanx_right_out[12] = chanx_left_in[12]; - assign chanx_right_out[13] = chanx_left_in[13]; - assign chanx_right_out[14] = chanx_left_in[14]; - assign chanx_right_out[15] = chanx_left_in[15]; - assign chanx_right_out[16] = chanx_left_in[16]; - assign chanx_right_out[17] = chanx_left_in[17]; - assign chanx_right_out[18] = chanx_left_in[18]; - assign chanx_right_out[19] = chanx_left_in[19]; - assign chanx_left_out[0] = chanx_right_in[0]; - assign chanx_left_out[1] = chanx_right_in[1]; - assign chanx_left_out[2] = chanx_right_in[2]; - assign chanx_left_out[3] = chanx_right_in[3]; - assign chanx_left_out[4] = chanx_right_in[4]; - assign chanx_left_out[5] = chanx_right_in[5]; - assign chanx_left_out[6] = chanx_right_in[6]; - assign chanx_left_out[7] = chanx_right_in[7]; - assign chanx_left_out[8] = chanx_right_in[8]; - assign chanx_left_out[9] = chanx_right_in[9]; - assign chanx_left_out[10] = chanx_right_in[10]; - assign chanx_left_out[11] = chanx_right_in[11]; - assign chanx_left_out[12] = chanx_right_in[12]; - assign chanx_left_out[13] = chanx_right_in[13]; - assign chanx_left_out[14] = chanx_right_in[14]; - assign chanx_left_out[15] = chanx_right_in[15]; - assign chanx_left_out[16] = chanx_right_in[16]; - assign chanx_left_out[17] = chanx_right_in[17]; - assign chanx_left_out[18] = chanx_right_in[18]; - assign chanx_left_out[19] = chanx_right_in[19]; - assign top_width_0_height_0__pin_1_lower[0] = top_width_0_height_0__pin_1_upper[0]; - assign top_width_0_height_0__pin_3_lower[0] = top_width_0_height_0__pin_3_upper[0]; - assign top_width_0_height_0__pin_5_lower[0] = top_width_0_height_0__pin_5_upper[0]; - assign top_width_0_height_0__pin_7_lower[0] = top_width_0_height_0__pin_7_upper[0]; - assign top_width_0_height_0__pin_9_lower[0] = top_width_0_height_0__pin_9_upper[0]; - assign top_width_0_height_0__pin_11_lower[0] = top_width_0_height_0__pin_11_upper[0]; - assign SC_IN_TOP = SC_IN_BOT; - assign SC_OUT_TOP = SC_OUT_BOT; - - mux_tree_tapbuf_size10 - mux_top_ipin_0 - ( - .in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10], chanx_left_in[16], chanx_right_in[16] }), - .sram(mux_tree_tapbuf_size10_0_sram[0:3]), - .sram_inv(mux_top_ipin_0_undriven_sram_inv[0:3]), - .out(bottom_grid_pin_0_[0]) - ); - - - mux_tree_tapbuf_size10 - mux_top_ipin_1 - ( - .in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[5], chanx_right_in[5], chanx_left_in[11], chanx_right_in[11], chanx_left_in[17], chanx_right_in[17] }), - .sram(mux_tree_tapbuf_size10_1_sram[0:3]), - .sram_inv(mux_top_ipin_1_undriven_sram_inv[0:3]), - .out(bottom_grid_pin_2_[0]) - ); - - - mux_tree_tapbuf_size10 - mux_top_ipin_2 - ( - .in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12], chanx_left_in[18], chanx_right_in[18] }), - .sram(mux_tree_tapbuf_size10_2_sram[0:3]), - .sram_inv(mux_top_ipin_2_undriven_sram_inv[0:3]), - .out(bottom_grid_pin_4_[0]) - ); - - - mux_tree_tapbuf_size10 - mux_top_ipin_3 - ( - .in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[7], chanx_right_in[7], chanx_left_in[13], chanx_right_in[13], chanx_left_in[19], chanx_right_in[19] }), - .sram(mux_tree_tapbuf_size10_3_sram[0:3]), - .sram_inv(mux_top_ipin_3_undriven_sram_inv[0:3]), - .out(bottom_grid_pin_6_[0]) - ); - - - mux_tree_tapbuf_size10 - mux_top_ipin_4 - ( - .in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[4], chanx_right_in[4], chanx_left_in[8], chanx_right_in[8], chanx_left_in[14], chanx_right_in[14] }), - .sram(mux_tree_tapbuf_size10_4_sram[0:3]), - .sram_inv(mux_top_ipin_4_undriven_sram_inv[0:3]), - .out(bottom_grid_pin_8_[0]) - ); - - - mux_tree_tapbuf_size10 - mux_top_ipin_5 - ( - .in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[5], chanx_right_in[5], chanx_left_in[9], chanx_right_in[9], chanx_left_in[15], chanx_right_in[15] }), - .sram(mux_tree_tapbuf_size10_5_sram[0:3]), - .sram_inv(mux_top_ipin_5_undriven_sram_inv[0:3]), - .out(bottom_grid_pin_10_[0]) - ); - - - mux_tree_tapbuf_size10_mem - mem_top_ipin_0 - ( - .prog_clk(prog_clk[0]), - .ccff_head(ccff_head[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_0_sram[0:3]) - ); - - - mux_tree_tapbuf_size10_mem - mem_top_ipin_1 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_1_sram[0:3]) - ); - - - mux_tree_tapbuf_size10_mem - mem_top_ipin_2 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_2_sram[0:3]) - ); - - - mux_tree_tapbuf_size10_mem - mem_top_ipin_3 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_3_sram[0:3]) - ); - - - mux_tree_tapbuf_size10_mem - mem_top_ipin_4 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_4_sram[0:3]) - ); - - - mux_tree_tapbuf_size10_mem - mem_top_ipin_5 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]), - .ccff_tail(ccff_tail_mid), - .mem_out(mux_tree_tapbuf_size10_5_sram[0:3]) - ); - - - logical_tile_io_mode_io_ - logical_tile_io_mode_io__0 - ( - .prog_clk(prog_clk[0]), - .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[0]), - .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[0]), - .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[0]), - .io_outpad(top_width_0_height_0__pin_0_[0]), - .ccff_head(ccff_tail_mid), - .io_inpad(top_width_0_height_0__pin_1_upper[0]), - .ccff_tail(logical_tile_io_mode_io__0_ccff_tail[0]) - ); - - - logical_tile_io_mode_io_ - logical_tile_io_mode_io__1 - ( - .prog_clk(prog_clk[0]), - .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[1]), - .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[1]), - .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[1]), - .io_outpad(top_width_0_height_0__pin_2_[0]), - .ccff_head(logical_tile_io_mode_io__0_ccff_tail[0]), - .io_inpad(top_width_0_height_0__pin_3_upper[0]), - .ccff_tail(logical_tile_io_mode_io__1_ccff_tail[0]) - ); - - - logical_tile_io_mode_io_ - logical_tile_io_mode_io__2 - ( - .prog_clk(prog_clk[0]), - .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[2]), - .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[2]), - .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[2]), - .io_outpad(top_width_0_height_0__pin_4_[0]), - .ccff_head(logical_tile_io_mode_io__1_ccff_tail[0]), - .io_inpad(top_width_0_height_0__pin_5_upper[0]), - .ccff_tail(logical_tile_io_mode_io__2_ccff_tail[0]) - ); - - - logical_tile_io_mode_io_ - logical_tile_io_mode_io__3 - ( - .prog_clk(prog_clk[0]), - .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[3]), - .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[3]), - .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[3]), - .io_outpad(top_width_0_height_0__pin_6_[0]), - .ccff_head(logical_tile_io_mode_io__2_ccff_tail[0]), - .io_inpad(top_width_0_height_0__pin_7_upper[0]), - .ccff_tail(logical_tile_io_mode_io__3_ccff_tail[0]) - ); - - - logical_tile_io_mode_io_ - logical_tile_io_mode_io__4 - ( - .prog_clk(prog_clk[0]), - .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[4]), - .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[4]), - .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[4]), - .io_outpad(top_width_0_height_0__pin_8_[0]), - .ccff_head(logical_tile_io_mode_io__3_ccff_tail[0]), - .io_inpad(top_width_0_height_0__pin_9_upper[0]), - .ccff_tail(logical_tile_io_mode_io__4_ccff_tail[0]) - ); - - - logical_tile_io_mode_io_ - logical_tile_io_mode_io__5 - ( - .prog_clk(prog_clk[0]), - .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[5]), - .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[5]), - .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[5]), - .io_outpad(top_width_0_height_0__pin_10_[0]), - .ccff_head(logical_tile_io_mode_io__4_ccff_tail[0]), - .io_inpad(top_width_0_height_0__pin_11_upper[0]), - .ccff_tail(ccff_tail[0]) - ); - - -endmodule - diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cbx_1__1_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cbx_1__1_.v deleted file mode 100644 index 31c9a6e..0000000 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cbx_1__1_.v +++ /dev/null @@ -1,444 +0,0 @@ - - -module cbx_1__1_ -( prog_clk, chanx_left_in, chanx_right_in, ccff_head, chanx_left_out, chanx_right_out, bottom_grid_pin_0_, bottom_grid_pin_1_, bottom_grid_pin_2_, bottom_grid_pin_3_, bottom_grid_pin_4_, bottom_grid_pin_5_, bottom_grid_pin_6_, bottom_grid_pin_7_, bottom_grid_pin_8_, bottom_grid_pin_9_, bottom_grid_pin_10_, bottom_grid_pin_11_, bottom_grid_pin_12_, bottom_grid_pin_13_, bottom_grid_pin_14_, bottom_grid_pin_15_, ccff_tail, SC_IN_TOP, SC_IN_BOT, SC_OUT_TOP, SC_OUT_BOT ); - input [0:0] prog_clk; - input [0:19] chanx_left_in; - input [0:19] chanx_right_in; - input [0:0] ccff_head; - output [0:19] chanx_left_out; - output [0:19] chanx_right_out; - output [0:0] bottom_grid_pin_0_; - output [0:0] bottom_grid_pin_1_; - output [0:0] bottom_grid_pin_2_; - output [0:0] bottom_grid_pin_3_; - output [0:0] bottom_grid_pin_4_; - output [0:0] bottom_grid_pin_5_; - output [0:0] bottom_grid_pin_6_; - output [0:0] bottom_grid_pin_7_; - output [0:0] bottom_grid_pin_8_; - output [0:0] bottom_grid_pin_9_; - output [0:0] bottom_grid_pin_10_; - output [0:0] bottom_grid_pin_11_; - output [0:0] bottom_grid_pin_12_; - output [0:0] bottom_grid_pin_13_; - output [0:0] bottom_grid_pin_14_; - output [0:0] bottom_grid_pin_15_; - output [0:0] ccff_tail; - input SC_IN_TOP; - input SC_IN_BOT; - output SC_OUT_TOP; - output SC_OUT_BOT; - - wire [0:3] mux_top_ipin_0_undriven_sram_inv; - wire [0:3] mux_top_ipin_10_undriven_sram_inv; - wire [0:3] mux_top_ipin_11_undriven_sram_inv; - wire [0:3] mux_top_ipin_12_undriven_sram_inv; - wire [0:3] mux_top_ipin_13_undriven_sram_inv; - wire [0:3] mux_top_ipin_14_undriven_sram_inv; - wire [0:3] mux_top_ipin_15_undriven_sram_inv; - wire [0:3] mux_top_ipin_1_undriven_sram_inv; - wire [0:3] mux_top_ipin_2_undriven_sram_inv; - wire [0:3] mux_top_ipin_3_undriven_sram_inv; - wire [0:3] mux_top_ipin_4_undriven_sram_inv; - wire [0:3] mux_top_ipin_5_undriven_sram_inv; - wire [0:3] mux_top_ipin_6_undriven_sram_inv; - wire [0:3] mux_top_ipin_7_undriven_sram_inv; - wire [0:3] mux_top_ipin_8_undriven_sram_inv; - wire [0:3] mux_top_ipin_9_undriven_sram_inv; - wire [0:3] mux_tree_tapbuf_size10_0_sram; - wire [0:3] mux_tree_tapbuf_size10_1_sram; - wire [0:3] mux_tree_tapbuf_size10_2_sram; - wire [0:3] mux_tree_tapbuf_size10_3_sram; - wire [0:3] mux_tree_tapbuf_size10_4_sram; - wire [0:3] mux_tree_tapbuf_size10_5_sram; - wire [0:3] mux_tree_tapbuf_size10_6_sram; - wire [0:3] mux_tree_tapbuf_size10_7_sram; - wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail; - wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail; - wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail; - wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail; - wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail; - wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail; - wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail; - wire [0:3] mux_tree_tapbuf_size8_0_sram; - wire [0:3] mux_tree_tapbuf_size8_1_sram; - wire [0:3] mux_tree_tapbuf_size8_2_sram; - wire [0:3] mux_tree_tapbuf_size8_3_sram; - wire [0:3] mux_tree_tapbuf_size8_4_sram; - wire [0:3] mux_tree_tapbuf_size8_5_sram; - wire [0:3] mux_tree_tapbuf_size8_6_sram; - wire [0:3] mux_tree_tapbuf_size8_7_sram; - wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail; - wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail; - wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail; - wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail; - wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail; - wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail; - wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail; - wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail; - assign chanx_right_out[0] = chanx_left_in[0]; - assign chanx_right_out[1] = chanx_left_in[1]; - assign chanx_right_out[2] = chanx_left_in[2]; - assign chanx_right_out[3] = chanx_left_in[3]; - assign chanx_right_out[4] = chanx_left_in[4]; - assign chanx_right_out[5] = chanx_left_in[5]; - assign chanx_right_out[6] = chanx_left_in[6]; - assign chanx_right_out[7] = chanx_left_in[7]; - assign chanx_right_out[8] = chanx_left_in[8]; - assign chanx_right_out[9] = chanx_left_in[9]; - assign chanx_right_out[10] = chanx_left_in[10]; - assign chanx_right_out[11] = chanx_left_in[11]; - assign chanx_right_out[12] = chanx_left_in[12]; - assign chanx_right_out[13] = chanx_left_in[13]; - assign chanx_right_out[14] = chanx_left_in[14]; - assign chanx_right_out[15] = chanx_left_in[15]; - assign chanx_right_out[16] = chanx_left_in[16]; - assign chanx_right_out[17] = chanx_left_in[17]; - assign chanx_right_out[18] = chanx_left_in[18]; - assign chanx_right_out[19] = chanx_left_in[19]; - assign chanx_left_out[0] = chanx_right_in[0]; - assign chanx_left_out[1] = chanx_right_in[1]; - assign chanx_left_out[2] = chanx_right_in[2]; - assign chanx_left_out[3] = chanx_right_in[3]; - assign chanx_left_out[4] = chanx_right_in[4]; - assign chanx_left_out[5] = chanx_right_in[5]; - assign chanx_left_out[6] = chanx_right_in[6]; - assign chanx_left_out[7] = chanx_right_in[7]; - assign chanx_left_out[8] = chanx_right_in[8]; - assign chanx_left_out[9] = chanx_right_in[9]; - assign chanx_left_out[10] = chanx_right_in[10]; - assign chanx_left_out[11] = chanx_right_in[11]; - assign chanx_left_out[12] = chanx_right_in[12]; - assign chanx_left_out[13] = chanx_right_in[13]; - assign chanx_left_out[14] = chanx_right_in[14]; - assign chanx_left_out[15] = chanx_right_in[15]; - assign chanx_left_out[16] = chanx_right_in[16]; - assign chanx_left_out[17] = chanx_right_in[17]; - assign chanx_left_out[18] = chanx_right_in[18]; - assign chanx_left_out[19] = chanx_right_in[19]; - assign SC_IN_TOP = SC_IN_BOT; - assign SC_OUT_TOP = SC_OUT_BOT; - - mux_tree_tapbuf_size10 - mux_top_ipin_0 - ( - .in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10], chanx_left_in[16], chanx_right_in[16] }), - .sram(mux_tree_tapbuf_size10_0_sram[0:3]), - .sram_inv(mux_top_ipin_0_undriven_sram_inv[0:3]), - .out(bottom_grid_pin_0_[0]) - ); - - - mux_tree_tapbuf_size10 - mux_top_ipin_3 - ( - .in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[7], chanx_right_in[7], chanx_left_in[13], chanx_right_in[13], chanx_left_in[19], chanx_right_in[19] }), - .sram(mux_tree_tapbuf_size10_1_sram[0:3]), - .sram_inv(mux_top_ipin_3_undriven_sram_inv[0:3]), - .out(bottom_grid_pin_3_[0]) - ); - - - mux_tree_tapbuf_size10 - mux_top_ipin_4 - ( - .in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[4], chanx_right_in[4], chanx_left_in[8], chanx_right_in[8], chanx_left_in[14], chanx_right_in[14] }), - .sram(mux_tree_tapbuf_size10_2_sram[0:3]), - .sram_inv(mux_top_ipin_4_undriven_sram_inv[0:3]), - .out(bottom_grid_pin_4_[0]) - ); - - - mux_tree_tapbuf_size10 - mux_top_ipin_7 - ( - .in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[7], chanx_right_in[7], chanx_left_in[11], chanx_right_in[11], chanx_left_in[17], chanx_right_in[17] }), - .sram(mux_tree_tapbuf_size10_3_sram[0:3]), - .sram_inv(mux_top_ipin_7_undriven_sram_inv[0:3]), - .out(bottom_grid_pin_7_[0]) - ); - - - mux_tree_tapbuf_size10 - mux_top_ipin_8 - ( - .in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[8], chanx_right_in[8], chanx_left_in[12], chanx_right_in[12], chanx_left_in[18], chanx_right_in[18] }), - .sram(mux_tree_tapbuf_size10_4_sram[0:3]), - .sram_inv(mux_top_ipin_8_undriven_sram_inv[0:3]), - .out(bottom_grid_pin_8_[0]) - ); - - - mux_tree_tapbuf_size10 - mux_top_ipin_11 - ( - .in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[5], chanx_right_in[5], chanx_left_in[11], chanx_right_in[11], chanx_left_in[15], chanx_right_in[15] }), - .sram(mux_tree_tapbuf_size10_5_sram[0:3]), - .sram_inv(mux_top_ipin_11_undriven_sram_inv[0:3]), - .out(bottom_grid_pin_11_[0]) - ); - - - mux_tree_tapbuf_size10 - mux_top_ipin_12 - ( - .in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12], chanx_left_in[16], chanx_right_in[16] }), - .sram(mux_tree_tapbuf_size10_6_sram[0:3]), - .sram_inv(mux_top_ipin_12_undriven_sram_inv[0:3]), - .out(bottom_grid_pin_12_[0]) - ); - - - mux_tree_tapbuf_size10 - mux_top_ipin_15 - ( - .in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9], chanx_left_in[15], chanx_right_in[15], chanx_left_in[19], chanx_right_in[19] }), - .sram(mux_tree_tapbuf_size10_7_sram[0:3]), - .sram_inv(mux_top_ipin_15_undriven_sram_inv[0:3]), - .out(bottom_grid_pin_15_[0]) - ); - - - mux_tree_tapbuf_size10_mem - mem_top_ipin_0 - ( - .prog_clk(prog_clk[0]), - .ccff_head(ccff_head[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_0_sram[0:3]) - ); - - - mux_tree_tapbuf_size10_mem - mem_top_ipin_3 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_1_sram[0:3]) - ); - - - mux_tree_tapbuf_size10_mem - mem_top_ipin_4 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_2_sram[0:3]) - ); - - - mux_tree_tapbuf_size10_mem - mem_top_ipin_7 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_3_sram[0:3]) - ); - - - mux_tree_tapbuf_size10_mem - mem_top_ipin_8 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_4_sram[0:3]) - ); - - - mux_tree_tapbuf_size10_mem - mem_top_ipin_11 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_5_sram[0:3]) - ); - - - mux_tree_tapbuf_size10_mem - mem_top_ipin_12 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_6_sram[0:3]) - ); - - - mux_tree_tapbuf_size10_mem - mem_top_ipin_15 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_7_ccff_tail[0]), - .ccff_tail(ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_7_sram[0:3]) - ); - - - mux_tree_tapbuf_size8 - mux_top_ipin_1 - ( - .in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[5], chanx_right_in[5], chanx_left_in[13], chanx_right_in[13] }), - .sram(mux_tree_tapbuf_size8_0_sram[0:3]), - .sram_inv(mux_top_ipin_1_undriven_sram_inv[0:3]), - .out(bottom_grid_pin_1_[0]) - ); - - - mux_tree_tapbuf_size8 - mux_top_ipin_2 - ( - .in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[14], chanx_right_in[14] }), - .sram(mux_tree_tapbuf_size8_1_sram[0:3]), - .sram_inv(mux_top_ipin_2_undriven_sram_inv[0:3]), - .out(bottom_grid_pin_2_[0]) - ); - - - mux_tree_tapbuf_size8 - mux_top_ipin_5 - ( - .in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9], chanx_left_in[17], chanx_right_in[17] }), - .sram(mux_tree_tapbuf_size8_2_sram[0:3]), - .sram_inv(mux_top_ipin_5_undriven_sram_inv[0:3]), - .out(bottom_grid_pin_5_[0]) - ); - - - mux_tree_tapbuf_size8 - mux_top_ipin_6 - ( - .in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[10], chanx_right_in[10], chanx_left_in[18], chanx_right_in[18] }), - .sram(mux_tree_tapbuf_size8_3_sram[0:3]), - .sram_inv(mux_top_ipin_6_undriven_sram_inv[0:3]), - .out(bottom_grid_pin_6_[0]) - ); - - - mux_tree_tapbuf_size8 - mux_top_ipin_9 - ( - .in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[5], chanx_right_in[5], chanx_left_in[13], chanx_right_in[13] }), - .sram(mux_tree_tapbuf_size8_4_sram[0:3]), - .sram_inv(mux_top_ipin_9_undriven_sram_inv[0:3]), - .out(bottom_grid_pin_9_[0]) - ); - - - mux_tree_tapbuf_size8 - mux_top_ipin_10 - ( - .in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[14], chanx_right_in[14] }), - .sram(mux_tree_tapbuf_size8_5_sram[0:3]), - .sram_inv(mux_top_ipin_10_undriven_sram_inv[0:3]), - .out(bottom_grid_pin_10_[0]) - ); - - - mux_tree_tapbuf_size8 - mux_top_ipin_13 - ( - .in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9], chanx_left_in[17], chanx_right_in[17] }), - .sram(mux_tree_tapbuf_size8_6_sram[0:3]), - .sram_inv(mux_top_ipin_13_undriven_sram_inv[0:3]), - .out(bottom_grid_pin_13_[0]) - ); - - - mux_tree_tapbuf_size8 - mux_top_ipin_14 - ( - .in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[10], chanx_right_in[10], chanx_left_in[18], chanx_right_in[18] }), - .sram(mux_tree_tapbuf_size8_7_sram[0:3]), - .sram_inv(mux_top_ipin_14_undriven_sram_inv[0:3]), - .out(bottom_grid_pin_14_[0]) - ); - - - mux_tree_tapbuf_size8_mem - mem_top_ipin_1 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_0_sram[0:3]) - ); - - - mux_tree_tapbuf_size8_mem - mem_top_ipin_2 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_1_sram[0:3]) - ); - - - mux_tree_tapbuf_size8_mem - mem_top_ipin_5 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_2_sram[0:3]) - ); - - - mux_tree_tapbuf_size8_mem - mem_top_ipin_6 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_3_sram[0:3]) - ); - - - mux_tree_tapbuf_size8_mem - mem_top_ipin_9 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_4_sram[0:3]) - ); - - - mux_tree_tapbuf_size8_mem - mem_top_ipin_10 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_5_sram[0:3]) - ); - - - mux_tree_tapbuf_size8_mem - mem_top_ipin_13 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_6_sram[0:3]) - ); - - - mux_tree_tapbuf_size8_mem - mem_top_ipin_14 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_7_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_7_sram[0:3]) - ); - - -endmodule - diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cbx_1__2_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cbx_1__2_.v deleted file mode 100644 index 959cf8c..0000000 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cbx_1__2_.v +++ /dev/null @@ -1,490 +0,0 @@ - - -module cbx_1__2_ -( prog_clk, chanx_left_in, chanx_right_in, ccff_head, chanx_left_out, chanx_right_out, top_grid_pin_0_, bottom_grid_pin_0_, bottom_grid_pin_1_, bottom_grid_pin_2_, bottom_grid_pin_3_, bottom_grid_pin_4_, bottom_grid_pin_5_, bottom_grid_pin_6_, bottom_grid_pin_7_, bottom_grid_pin_8_, bottom_grid_pin_9_, bottom_grid_pin_10_, bottom_grid_pin_11_, bottom_grid_pin_12_, bottom_grid_pin_13_, bottom_grid_pin_14_, bottom_grid_pin_15_, ccff_tail, gfpga_pad_EMBEDDED_IO_SOC_IN, gfpga_pad_EMBEDDED_IO_SOC_OUT, gfpga_pad_EMBEDDED_IO_SOC_DIR, bottom_width_0_height_0__pin_0_, bottom_width_0_height_0__pin_1_upper, bottom_width_0_height_0__pin_1_lower, SC_IN_TOP, SC_IN_BOT, SC_OUT_TOP, SC_OUT_BOT ); - input [0:0] prog_clk; - input [0:19] chanx_left_in; - input [0:19] chanx_right_in; - input [0:0] ccff_head; - output [0:19] chanx_left_out; - output [0:19] chanx_right_out; - output [0:0] top_grid_pin_0_; - output [0:0] bottom_grid_pin_0_; - output [0:0] bottom_grid_pin_1_; - output [0:0] bottom_grid_pin_2_; - output [0:0] bottom_grid_pin_3_; - output [0:0] bottom_grid_pin_4_; - output [0:0] bottom_grid_pin_5_; - output [0:0] bottom_grid_pin_6_; - output [0:0] bottom_grid_pin_7_; - output [0:0] bottom_grid_pin_8_; - output [0:0] bottom_grid_pin_9_; - output [0:0] bottom_grid_pin_10_; - output [0:0] bottom_grid_pin_11_; - output [0:0] bottom_grid_pin_12_; - output [0:0] bottom_grid_pin_13_; - output [0:0] bottom_grid_pin_14_; - output [0:0] bottom_grid_pin_15_; - output [0:0] ccff_tail; - input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN; - output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT; - output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR; - input [0:0] bottom_width_0_height_0__pin_0_; - output [0:0] bottom_width_0_height_0__pin_1_upper; - output [0:0] bottom_width_0_height_0__pin_1_lower; - input SC_IN_TOP; - input SC_IN_BOT; - output SC_OUT_TOP; - output SC_OUT_BOT; - - wire [0:3] mux_bottom_ipin_0_undriven_sram_inv; - wire [0:3] mux_top_ipin_0_undriven_sram_inv; - wire [0:3] mux_top_ipin_10_undriven_sram_inv; - wire [0:3] mux_top_ipin_11_undriven_sram_inv; - wire [0:3] mux_top_ipin_12_undriven_sram_inv; - wire [0:3] mux_top_ipin_13_undriven_sram_inv; - wire [0:3] mux_top_ipin_14_undriven_sram_inv; - wire [0:3] mux_top_ipin_15_undriven_sram_inv; - wire [0:3] mux_top_ipin_1_undriven_sram_inv; - wire [0:3] mux_top_ipin_2_undriven_sram_inv; - wire [0:3] mux_top_ipin_3_undriven_sram_inv; - wire [0:3] mux_top_ipin_4_undriven_sram_inv; - wire [0:3] mux_top_ipin_5_undriven_sram_inv; - wire [0:3] mux_top_ipin_6_undriven_sram_inv; - wire [0:3] mux_top_ipin_7_undriven_sram_inv; - wire [0:3] mux_top_ipin_8_undriven_sram_inv; - wire [0:3] mux_top_ipin_9_undriven_sram_inv; - wire [0:3] mux_tree_tapbuf_size10_0_sram; - wire [0:3] mux_tree_tapbuf_size10_1_sram; - wire [0:3] mux_tree_tapbuf_size10_2_sram; - wire [0:3] mux_tree_tapbuf_size10_3_sram; - wire [0:3] mux_tree_tapbuf_size10_4_sram; - wire [0:3] mux_tree_tapbuf_size10_5_sram; - wire [0:3] mux_tree_tapbuf_size10_6_sram; - wire [0:3] mux_tree_tapbuf_size10_7_sram; - wire [0:3] mux_tree_tapbuf_size10_8_sram; - wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail; - wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail; - wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail; - wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail; - wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail; - wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail; - wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail; - wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail; - wire [0:3] mux_tree_tapbuf_size8_0_sram; - wire [0:3] mux_tree_tapbuf_size8_1_sram; - wire [0:3] mux_tree_tapbuf_size8_2_sram; - wire [0:3] mux_tree_tapbuf_size8_3_sram; - wire [0:3] mux_tree_tapbuf_size8_4_sram; - wire [0:3] mux_tree_tapbuf_size8_5_sram; - wire [0:3] mux_tree_tapbuf_size8_6_sram; - wire [0:3] mux_tree_tapbuf_size8_7_sram; - wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail; - wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail; - wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail; - wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail; - wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail; - wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail; - wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail; - wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail; - wire ccff_tail_mid; - assign chanx_right_out[0] = chanx_left_in[0]; - assign chanx_right_out[1] = chanx_left_in[1]; - assign chanx_right_out[2] = chanx_left_in[2]; - assign chanx_right_out[3] = chanx_left_in[3]; - assign chanx_right_out[4] = chanx_left_in[4]; - assign chanx_right_out[5] = chanx_left_in[5]; - assign chanx_right_out[6] = chanx_left_in[6]; - assign chanx_right_out[7] = chanx_left_in[7]; - assign chanx_right_out[8] = chanx_left_in[8]; - assign chanx_right_out[9] = chanx_left_in[9]; - assign chanx_right_out[10] = chanx_left_in[10]; - assign chanx_right_out[11] = chanx_left_in[11]; - assign chanx_right_out[12] = chanx_left_in[12]; - assign chanx_right_out[13] = chanx_left_in[13]; - assign chanx_right_out[14] = chanx_left_in[14]; - assign chanx_right_out[15] = chanx_left_in[15]; - assign chanx_right_out[16] = chanx_left_in[16]; - assign chanx_right_out[17] = chanx_left_in[17]; - assign chanx_right_out[18] = chanx_left_in[18]; - assign chanx_right_out[19] = chanx_left_in[19]; - assign chanx_left_out[0] = chanx_right_in[0]; - assign chanx_left_out[1] = chanx_right_in[1]; - assign chanx_left_out[2] = chanx_right_in[2]; - assign chanx_left_out[3] = chanx_right_in[3]; - assign chanx_left_out[4] = chanx_right_in[4]; - assign chanx_left_out[5] = chanx_right_in[5]; - assign chanx_left_out[6] = chanx_right_in[6]; - assign chanx_left_out[7] = chanx_right_in[7]; - assign chanx_left_out[8] = chanx_right_in[8]; - assign chanx_left_out[9] = chanx_right_in[9]; - assign chanx_left_out[10] = chanx_right_in[10]; - assign chanx_left_out[11] = chanx_right_in[11]; - assign chanx_left_out[12] = chanx_right_in[12]; - assign chanx_left_out[13] = chanx_right_in[13]; - assign chanx_left_out[14] = chanx_right_in[14]; - assign chanx_left_out[15] = chanx_right_in[15]; - assign chanx_left_out[16] = chanx_right_in[16]; - assign chanx_left_out[17] = chanx_right_in[17]; - assign chanx_left_out[18] = chanx_right_in[18]; - assign chanx_left_out[19] = chanx_right_in[19]; - assign bottom_width_0_height_0__pin_1_lower[0] = bottom_width_0_height_0__pin_1_upper[0]; - assign SC_IN_TOP = SC_IN_BOT; - assign SC_OUT_TOP = SC_OUT_BOT; - - mux_tree_tapbuf_size10 - mux_bottom_ipin_0 - ( - .in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10], chanx_left_in[16], chanx_right_in[16] }), - .sram(mux_tree_tapbuf_size10_0_sram[0:3]), - .sram_inv(mux_bottom_ipin_0_undriven_sram_inv[0:3]), - .out(top_grid_pin_0_[0]) - ); - - - mux_tree_tapbuf_size10 - mux_top_ipin_0 - ( - .in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[5], chanx_right_in[5], chanx_left_in[11], chanx_right_in[11], chanx_left_in[17], chanx_right_in[17] }), - .sram(mux_tree_tapbuf_size10_1_sram[0:3]), - .sram_inv(mux_top_ipin_0_undriven_sram_inv[0:3]), - .out(bottom_grid_pin_0_[0]) - ); - - - mux_tree_tapbuf_size10 - mux_top_ipin_3 - ( - .in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[4], chanx_right_in[4], chanx_left_in[8], chanx_right_in[8], chanx_left_in[14], chanx_right_in[14] }), - .sram(mux_tree_tapbuf_size10_2_sram[0:3]), - .sram_inv(mux_top_ipin_3_undriven_sram_inv[0:3]), - .out(bottom_grid_pin_3_[0]) - ); - - - mux_tree_tapbuf_size10 - mux_top_ipin_4 - ( - .in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[5], chanx_right_in[5], chanx_left_in[9], chanx_right_in[9], chanx_left_in[15], chanx_right_in[15] }), - .sram(mux_tree_tapbuf_size10_3_sram[0:3]), - .sram_inv(mux_top_ipin_4_undriven_sram_inv[0:3]), - .out(bottom_grid_pin_4_[0]) - ); - - - mux_tree_tapbuf_size10 - mux_top_ipin_7 - ( - .in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[8], chanx_right_in[8], chanx_left_in[12], chanx_right_in[12], chanx_left_in[18], chanx_right_in[18] }), - .sram(mux_tree_tapbuf_size10_4_sram[0:3]), - .sram_inv(mux_top_ipin_7_undriven_sram_inv[0:3]), - .out(bottom_grid_pin_7_[0]) - ); - - - mux_tree_tapbuf_size10 - mux_top_ipin_8 - ( - .in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9], chanx_left_in[13], chanx_right_in[13], chanx_left_in[19], chanx_right_in[19] }), - .sram(mux_tree_tapbuf_size10_5_sram[0:3]), - .sram_inv(mux_top_ipin_8_undriven_sram_inv[0:3]), - .out(bottom_grid_pin_8_[0]) - ); - - - mux_tree_tapbuf_size10 - mux_top_ipin_11 - ( - .in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12], chanx_left_in[16], chanx_right_in[16] }), - .sram(mux_tree_tapbuf_size10_6_sram[0:3]), - .sram_inv(mux_top_ipin_11_undriven_sram_inv[0:3]), - .out(bottom_grid_pin_11_[0]) - ); - - - mux_tree_tapbuf_size10 - mux_top_ipin_12 - ( - .in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[7], chanx_right_in[7], chanx_left_in[13], chanx_right_in[13], chanx_left_in[17], chanx_right_in[17] }), - .sram(mux_tree_tapbuf_size10_7_sram[0:3]), - .sram_inv(mux_top_ipin_12_undriven_sram_inv[0:3]), - .out(bottom_grid_pin_12_[0]) - ); - - - mux_tree_tapbuf_size10 - mux_top_ipin_15 - ( - .in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10], chanx_left_in[16], chanx_right_in[16] }), - .sram(mux_tree_tapbuf_size10_8_sram[0:3]), - .sram_inv(mux_top_ipin_15_undriven_sram_inv[0:3]), - .out(bottom_grid_pin_15_[0]) - ); - - - mux_tree_tapbuf_size10_mem - mem_bottom_ipin_0 - ( - .prog_clk(prog_clk[0]), - .ccff_head(ccff_head[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_0_sram[0:3]) - ); - - - mux_tree_tapbuf_size10_mem - mem_top_ipin_0 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_1_sram[0:3]) - ); - - - mux_tree_tapbuf_size10_mem - mem_top_ipin_3 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_2_sram[0:3]) - ); - - - mux_tree_tapbuf_size10_mem - mem_top_ipin_4 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_3_sram[0:3]) - ); - - - mux_tree_tapbuf_size10_mem - mem_top_ipin_7 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_4_sram[0:3]) - ); - - - mux_tree_tapbuf_size10_mem - mem_top_ipin_8 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_5_sram[0:3]) - ); - - - mux_tree_tapbuf_size10_mem - mem_top_ipin_11 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_6_sram[0:3]) - ); - - - mux_tree_tapbuf_size10_mem - mem_top_ipin_12 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_7_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_7_sram[0:3]) - ); - - - mux_tree_tapbuf_size10_mem - mem_top_ipin_15 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_7_ccff_tail[0]), - .ccff_tail(ccff_tail_mid), - .mem_out(mux_tree_tapbuf_size10_8_sram[0:3]) - ); - - - mux_tree_tapbuf_size8 - mux_top_ipin_1 - ( - .in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[14], chanx_right_in[14] }), - .sram(mux_tree_tapbuf_size8_0_sram[0:3]), - .sram_inv(mux_top_ipin_1_undriven_sram_inv[0:3]), - .out(bottom_grid_pin_1_[0]) - ); - - - mux_tree_tapbuf_size8 - mux_top_ipin_2 - ( - .in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[7], chanx_right_in[7], chanx_left_in[15], chanx_right_in[15] }), - .sram(mux_tree_tapbuf_size8_1_sram[0:3]), - .sram_inv(mux_top_ipin_2_undriven_sram_inv[0:3]), - .out(bottom_grid_pin_2_[0]) - ); - - - mux_tree_tapbuf_size8 - mux_top_ipin_5 - ( - .in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[10], chanx_right_in[10], chanx_left_in[18], chanx_right_in[18] }), - .sram(mux_tree_tapbuf_size8_2_sram[0:3]), - .sram_inv(mux_top_ipin_5_undriven_sram_inv[0:3]), - .out(bottom_grid_pin_5_[0]) - ); - - - mux_tree_tapbuf_size8 - mux_top_ipin_6 - ( - .in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[11], chanx_right_in[11], chanx_left_in[19], chanx_right_in[19] }), - .sram(mux_tree_tapbuf_size8_3_sram[0:3]), - .sram_inv(mux_top_ipin_6_undriven_sram_inv[0:3]), - .out(bottom_grid_pin_6_[0]) - ); - - - mux_tree_tapbuf_size8 - mux_top_ipin_9 - ( - .in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[6], chanx_right_in[6], chanx_left_in[14], chanx_right_in[14] }), - .sram(mux_tree_tapbuf_size8_4_sram[0:3]), - .sram_inv(mux_top_ipin_9_undriven_sram_inv[0:3]), - .out(bottom_grid_pin_9_[0]) - ); - - - mux_tree_tapbuf_size8 - mux_top_ipin_10 - ( - .in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[7], chanx_right_in[7], chanx_left_in[15], chanx_right_in[15] }), - .sram(mux_tree_tapbuf_size8_5_sram[0:3]), - .sram_inv(mux_top_ipin_10_undriven_sram_inv[0:3]), - .out(bottom_grid_pin_10_[0]) - ); - - - mux_tree_tapbuf_size8 - mux_top_ipin_13 - ( - .in({ chanx_left_in[0], chanx_right_in[0], chanx_left_in[2], chanx_right_in[2], chanx_left_in[10], chanx_right_in[10], chanx_left_in[18], chanx_right_in[18] }), - .sram(mux_tree_tapbuf_size8_6_sram[0:3]), - .sram_inv(mux_top_ipin_13_undriven_sram_inv[0:3]), - .out(bottom_grid_pin_13_[0]) - ); - - - mux_tree_tapbuf_size8 - mux_top_ipin_14 - ( - .in({ chanx_left_in[1], chanx_right_in[1], chanx_left_in[3], chanx_right_in[3], chanx_left_in[11], chanx_right_in[11], chanx_left_in[19], chanx_right_in[19] }), - .sram(mux_tree_tapbuf_size8_7_sram[0:3]), - .sram_inv(mux_top_ipin_14_undriven_sram_inv[0:3]), - .out(bottom_grid_pin_14_[0]) - ); - - - mux_tree_tapbuf_size8_mem - mem_top_ipin_1 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_0_sram[0:3]) - ); - - - mux_tree_tapbuf_size8_mem - mem_top_ipin_2 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_1_sram[0:3]) - ); - - - mux_tree_tapbuf_size8_mem - mem_top_ipin_5 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_2_sram[0:3]) - ); - - - mux_tree_tapbuf_size8_mem - mem_top_ipin_6 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_3_sram[0:3]) - ); - - - mux_tree_tapbuf_size8_mem - mem_top_ipin_9 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_4_sram[0:3]) - ); - - - mux_tree_tapbuf_size8_mem - mem_top_ipin_10 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_5_sram[0:3]) - ); - - - mux_tree_tapbuf_size8_mem - mem_top_ipin_13 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_7_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_6_sram[0:3]) - ); - - - mux_tree_tapbuf_size8_mem - mem_top_ipin_14 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_7_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_7_sram[0:3]) - ); - - - logical_tile_io_mode_io_ - logical_tile_io_mode_io__0 - ( - .prog_clk(prog_clk[0]), - .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[0]), - .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[0]), - .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[0]), - .io_outpad(bottom_width_0_height_0__pin_0_[0]), - .ccff_head(ccff_tail_mid), - .io_inpad(bottom_width_0_height_0__pin_1_upper[0]), - .ccff_tail(ccff_tail[0]) - ); - - -endmodule - diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cby_0__1_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cby_0__1_.v deleted file mode 100644 index 914fb20..0000000 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cby_0__1_.v +++ /dev/null @@ -1,100 +0,0 @@ - - -module cby_0__1_ -( prog_clk, chany_bottom_in, chany_top_in, ccff_head, chany_bottom_out, chany_top_out, left_grid_pin_0_, ccff_tail, gfpga_pad_EMBEDDED_IO_SOC_IN, gfpga_pad_EMBEDDED_IO_SOC_OUT, gfpga_pad_EMBEDDED_IO_SOC_DIR, right_width_0_height_0__pin_0_, right_width_0_height_0__pin_1_upper, right_width_0_height_0__pin_1_lower ); - input [0:0] prog_clk; - input [0:19] chany_bottom_in; - input [0:19] chany_top_in; - input [0:0] ccff_head; - output [0:19] chany_bottom_out; - output [0:19] chany_top_out; - output [0:0] left_grid_pin_0_; - output [0:0] ccff_tail; - input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN; - output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT; - output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR; - input [0:0] right_width_0_height_0__pin_0_; - output [0:0] right_width_0_height_0__pin_1_upper; - output [0:0] right_width_0_height_0__pin_1_lower; - - wire [0:3] mux_right_ipin_0_undriven_sram_inv; - wire [0:3] mux_tree_tapbuf_size10_0_sram; - wire ccff_tail_mid; - assign chany_top_out[0] = chany_bottom_in[0]; - assign chany_top_out[1] = chany_bottom_in[1]; - assign chany_top_out[2] = chany_bottom_in[2]; - assign chany_top_out[3] = chany_bottom_in[3]; - assign chany_top_out[4] = chany_bottom_in[4]; - assign chany_top_out[5] = chany_bottom_in[5]; - assign chany_top_out[6] = chany_bottom_in[6]; - assign chany_top_out[7] = chany_bottom_in[7]; - assign chany_top_out[8] = chany_bottom_in[8]; - assign chany_top_out[9] = chany_bottom_in[9]; - assign chany_top_out[10] = chany_bottom_in[10]; - assign chany_top_out[11] = chany_bottom_in[11]; - assign chany_top_out[12] = chany_bottom_in[12]; - assign chany_top_out[13] = chany_bottom_in[13]; - assign chany_top_out[14] = chany_bottom_in[14]; - assign chany_top_out[15] = chany_bottom_in[15]; - assign chany_top_out[16] = chany_bottom_in[16]; - assign chany_top_out[17] = chany_bottom_in[17]; - assign chany_top_out[18] = chany_bottom_in[18]; - assign chany_top_out[19] = chany_bottom_in[19]; - assign chany_bottom_out[0] = chany_top_in[0]; - assign chany_bottom_out[1] = chany_top_in[1]; - assign chany_bottom_out[2] = chany_top_in[2]; - assign chany_bottom_out[3] = chany_top_in[3]; - assign chany_bottom_out[4] = chany_top_in[4]; - assign chany_bottom_out[5] = chany_top_in[5]; - assign chany_bottom_out[6] = chany_top_in[6]; - assign chany_bottom_out[7] = chany_top_in[7]; - assign chany_bottom_out[8] = chany_top_in[8]; - assign chany_bottom_out[9] = chany_top_in[9]; - assign chany_bottom_out[10] = chany_top_in[10]; - assign chany_bottom_out[11] = chany_top_in[11]; - assign chany_bottom_out[12] = chany_top_in[12]; - assign chany_bottom_out[13] = chany_top_in[13]; - assign chany_bottom_out[14] = chany_top_in[14]; - assign chany_bottom_out[15] = chany_top_in[15]; - assign chany_bottom_out[16] = chany_top_in[16]; - assign chany_bottom_out[17] = chany_top_in[17]; - assign chany_bottom_out[18] = chany_top_in[18]; - assign chany_bottom_out[19] = chany_top_in[19]; - assign right_width_0_height_0__pin_1_lower[0] = right_width_0_height_0__pin_1_upper[0]; - - mux_tree_tapbuf_size10 - mux_right_ipin_0 - ( - .in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[16], chany_top_in[16] }), - .sram(mux_tree_tapbuf_size10_0_sram[0:3]), - .sram_inv(mux_right_ipin_0_undriven_sram_inv[0:3]), - .out(left_grid_pin_0_[0]) - ); - - - mux_tree_tapbuf_size10_mem - mem_right_ipin_0 - ( - .prog_clk(prog_clk[0]), - .ccff_head(ccff_head[0]), - .ccff_tail(ccff_tail_mid), - .mem_out(mux_tree_tapbuf_size10_0_sram[0:3]) - ); - - - logical_tile_io_mode_io_ - logical_tile_io_mode_io__0 - ( - .prog_clk(prog_clk[0]), - .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[0]), - .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[0]), - .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[0]), - .io_outpad(right_width_0_height_0__pin_0_[0]), - .ccff_head(ccff_tail_mid), - .io_inpad(right_width_0_height_0__pin_1_upper[0]), - .ccff_tail(ccff_tail[0]) - ); - - -endmodule - diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cby_1__1_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cby_1__1_.v deleted file mode 100644 index 8f85e08..0000000 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cby_1__1_.v +++ /dev/null @@ -1,438 +0,0 @@ - - -module cby_1__1_ -( prog_clk, chany_bottom_in, chany_top_in, ccff_head, chany_bottom_out, chany_top_out, left_grid_pin_16_, left_grid_pin_17_, left_grid_pin_18_, left_grid_pin_19_, left_grid_pin_20_, left_grid_pin_21_, left_grid_pin_22_, left_grid_pin_23_, left_grid_pin_24_, left_grid_pin_25_, left_grid_pin_26_, left_grid_pin_27_, left_grid_pin_28_, left_grid_pin_29_, left_grid_pin_30_, left_grid_pin_31_, ccff_tail ); - input [0:0] prog_clk; - input [0:19] chany_bottom_in; - input [0:19] chany_top_in; - input [0:0] ccff_head; - output [0:19] chany_bottom_out; - output [0:19] chany_top_out; - output [0:0] left_grid_pin_16_; - output [0:0] left_grid_pin_17_; - output [0:0] left_grid_pin_18_; - output [0:0] left_grid_pin_19_; - output [0:0] left_grid_pin_20_; - output [0:0] left_grid_pin_21_; - output [0:0] left_grid_pin_22_; - output [0:0] left_grid_pin_23_; - output [0:0] left_grid_pin_24_; - output [0:0] left_grid_pin_25_; - output [0:0] left_grid_pin_26_; - output [0:0] left_grid_pin_27_; - output [0:0] left_grid_pin_28_; - output [0:0] left_grid_pin_29_; - output [0:0] left_grid_pin_30_; - output [0:0] left_grid_pin_31_; - output [0:0] ccff_tail; - - wire [0:3] mux_right_ipin_0_undriven_sram_inv; - wire [0:3] mux_right_ipin_10_undriven_sram_inv; - wire [0:3] mux_right_ipin_11_undriven_sram_inv; - wire [0:3] mux_right_ipin_12_undriven_sram_inv; - wire [0:3] mux_right_ipin_13_undriven_sram_inv; - wire [0:3] mux_right_ipin_14_undriven_sram_inv; - wire [0:3] mux_right_ipin_15_undriven_sram_inv; - wire [0:3] mux_right_ipin_1_undriven_sram_inv; - wire [0:3] mux_right_ipin_2_undriven_sram_inv; - wire [0:3] mux_right_ipin_3_undriven_sram_inv; - wire [0:3] mux_right_ipin_4_undriven_sram_inv; - wire [0:3] mux_right_ipin_5_undriven_sram_inv; - wire [0:3] mux_right_ipin_6_undriven_sram_inv; - wire [0:3] mux_right_ipin_7_undriven_sram_inv; - wire [0:3] mux_right_ipin_8_undriven_sram_inv; - wire [0:3] mux_right_ipin_9_undriven_sram_inv; - wire [0:3] mux_tree_tapbuf_size10_0_sram; - wire [0:3] mux_tree_tapbuf_size10_1_sram; - wire [0:3] mux_tree_tapbuf_size10_2_sram; - wire [0:3] mux_tree_tapbuf_size10_3_sram; - wire [0:3] mux_tree_tapbuf_size10_4_sram; - wire [0:3] mux_tree_tapbuf_size10_5_sram; - wire [0:3] mux_tree_tapbuf_size10_6_sram; - wire [0:3] mux_tree_tapbuf_size10_7_sram; - wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail; - wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail; - wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail; - wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail; - wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail; - wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail; - wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail; - wire [0:3] mux_tree_tapbuf_size8_0_sram; - wire [0:3] mux_tree_tapbuf_size8_1_sram; - wire [0:3] mux_tree_tapbuf_size8_2_sram; - wire [0:3] mux_tree_tapbuf_size8_3_sram; - wire [0:3] mux_tree_tapbuf_size8_4_sram; - wire [0:3] mux_tree_tapbuf_size8_5_sram; - wire [0:3] mux_tree_tapbuf_size8_6_sram; - wire [0:3] mux_tree_tapbuf_size8_7_sram; - wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail; - wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail; - wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail; - wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail; - wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail; - wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail; - wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail; - wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail; - assign chany_top_out[0] = chany_bottom_in[0]; - assign chany_top_out[1] = chany_bottom_in[1]; - assign chany_top_out[2] = chany_bottom_in[2]; - assign chany_top_out[3] = chany_bottom_in[3]; - assign chany_top_out[4] = chany_bottom_in[4]; - assign chany_top_out[5] = chany_bottom_in[5]; - assign chany_top_out[6] = chany_bottom_in[6]; - assign chany_top_out[7] = chany_bottom_in[7]; - assign chany_top_out[8] = chany_bottom_in[8]; - assign chany_top_out[9] = chany_bottom_in[9]; - assign chany_top_out[10] = chany_bottom_in[10]; - assign chany_top_out[11] = chany_bottom_in[11]; - assign chany_top_out[12] = chany_bottom_in[12]; - assign chany_top_out[13] = chany_bottom_in[13]; - assign chany_top_out[14] = chany_bottom_in[14]; - assign chany_top_out[15] = chany_bottom_in[15]; - assign chany_top_out[16] = chany_bottom_in[16]; - assign chany_top_out[17] = chany_bottom_in[17]; - assign chany_top_out[18] = chany_bottom_in[18]; - assign chany_top_out[19] = chany_bottom_in[19]; - assign chany_bottom_out[0] = chany_top_in[0]; - assign chany_bottom_out[1] = chany_top_in[1]; - assign chany_bottom_out[2] = chany_top_in[2]; - assign chany_bottom_out[3] = chany_top_in[3]; - assign chany_bottom_out[4] = chany_top_in[4]; - assign chany_bottom_out[5] = chany_top_in[5]; - assign chany_bottom_out[6] = chany_top_in[6]; - assign chany_bottom_out[7] = chany_top_in[7]; - assign chany_bottom_out[8] = chany_top_in[8]; - assign chany_bottom_out[9] = chany_top_in[9]; - assign chany_bottom_out[10] = chany_top_in[10]; - assign chany_bottom_out[11] = chany_top_in[11]; - assign chany_bottom_out[12] = chany_top_in[12]; - assign chany_bottom_out[13] = chany_top_in[13]; - assign chany_bottom_out[14] = chany_top_in[14]; - assign chany_bottom_out[15] = chany_top_in[15]; - assign chany_bottom_out[16] = chany_top_in[16]; - assign chany_bottom_out[17] = chany_top_in[17]; - assign chany_bottom_out[18] = chany_top_in[18]; - assign chany_bottom_out[19] = chany_top_in[19]; - - mux_tree_tapbuf_size10 - mux_right_ipin_0 - ( - .in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[16], chany_top_in[16] }), - .sram(mux_tree_tapbuf_size10_0_sram[0:3]), - .sram_inv(mux_right_ipin_0_undriven_sram_inv[0:3]), - .out(left_grid_pin_16_[0]) - ); - - - mux_tree_tapbuf_size10 - mux_right_ipin_3 - ( - .in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[13], chany_top_in[13], chany_bottom_in[19], chany_top_in[19] }), - .sram(mux_tree_tapbuf_size10_1_sram[0:3]), - .sram_inv(mux_right_ipin_3_undriven_sram_inv[0:3]), - .out(left_grid_pin_19_[0]) - ); - - - mux_tree_tapbuf_size10 - mux_right_ipin_4 - ( - .in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[14], chany_top_in[14] }), - .sram(mux_tree_tapbuf_size10_2_sram[0:3]), - .sram_inv(mux_right_ipin_4_undriven_sram_inv[0:3]), - .out(left_grid_pin_20_[0]) - ); - - - mux_tree_tapbuf_size10 - mux_right_ipin_7 - ( - .in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[17], chany_top_in[17] }), - .sram(mux_tree_tapbuf_size10_3_sram[0:3]), - .sram_inv(mux_right_ipin_7_undriven_sram_inv[0:3]), - .out(left_grid_pin_23_[0]) - ); - - - mux_tree_tapbuf_size10 - mux_right_ipin_8 - ( - .in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[18], chany_top_in[18] }), - .sram(mux_tree_tapbuf_size10_4_sram[0:3]), - .sram_inv(mux_right_ipin_8_undriven_sram_inv[0:3]), - .out(left_grid_pin_24_[0]) - ); - - - mux_tree_tapbuf_size10 - mux_right_ipin_11 - ( - .in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[15], chany_top_in[15] }), - .sram(mux_tree_tapbuf_size10_5_sram[0:3]), - .sram_inv(mux_right_ipin_11_undriven_sram_inv[0:3]), - .out(left_grid_pin_27_[0]) - ); - - - mux_tree_tapbuf_size10 - mux_right_ipin_12 - ( - .in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[16], chany_top_in[16] }), - .sram(mux_tree_tapbuf_size10_6_sram[0:3]), - .sram_inv(mux_right_ipin_12_undriven_sram_inv[0:3]), - .out(left_grid_pin_28_[0]) - ); - - - mux_tree_tapbuf_size10 - mux_right_ipin_15 - ( - .in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[15], chany_top_in[15], chany_bottom_in[19], chany_top_in[19] }), - .sram(mux_tree_tapbuf_size10_7_sram[0:3]), - .sram_inv(mux_right_ipin_15_undriven_sram_inv[0:3]), - .out(left_grid_pin_31_[0]) - ); - - - mux_tree_tapbuf_size10_mem - mem_right_ipin_0 - ( - .prog_clk(prog_clk[0]), - .ccff_head(ccff_head[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_0_sram[0:3]) - ); - - - mux_tree_tapbuf_size10_mem - mem_right_ipin_3 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_1_sram[0:3]) - ); - - - mux_tree_tapbuf_size10_mem - mem_right_ipin_4 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_2_sram[0:3]) - ); - - - mux_tree_tapbuf_size10_mem - mem_right_ipin_7 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_3_sram[0:3]) - ); - - - mux_tree_tapbuf_size10_mem - mem_right_ipin_8 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_4_sram[0:3]) - ); - - - mux_tree_tapbuf_size10_mem - mem_right_ipin_11 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_5_sram[0:3]) - ); - - - mux_tree_tapbuf_size10_mem - mem_right_ipin_12 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_6_sram[0:3]) - ); - - - mux_tree_tapbuf_size10_mem - mem_right_ipin_15 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_7_ccff_tail[0]), - .ccff_tail(ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_7_sram[0:3]) - ); - - - mux_tree_tapbuf_size8 - mux_right_ipin_1 - ( - .in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[13], chany_top_in[13] }), - .sram(mux_tree_tapbuf_size8_0_sram[0:3]), - .sram_inv(mux_right_ipin_1_undriven_sram_inv[0:3]), - .out(left_grid_pin_17_[0]) - ); - - - mux_tree_tapbuf_size8 - mux_right_ipin_2 - ( - .in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[14], chany_top_in[14] }), - .sram(mux_tree_tapbuf_size8_1_sram[0:3]), - .sram_inv(mux_right_ipin_2_undriven_sram_inv[0:3]), - .out(left_grid_pin_18_[0]) - ); - - - mux_tree_tapbuf_size8 - mux_right_ipin_5 - ( - .in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[17], chany_top_in[17] }), - .sram(mux_tree_tapbuf_size8_2_sram[0:3]), - .sram_inv(mux_right_ipin_5_undriven_sram_inv[0:3]), - .out(left_grid_pin_21_[0]) - ); - - - mux_tree_tapbuf_size8 - mux_right_ipin_6 - ( - .in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[18], chany_top_in[18] }), - .sram(mux_tree_tapbuf_size8_3_sram[0:3]), - .sram_inv(mux_right_ipin_6_undriven_sram_inv[0:3]), - .out(left_grid_pin_22_[0]) - ); - - - mux_tree_tapbuf_size8 - mux_right_ipin_9 - ( - .in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[13], chany_top_in[13] }), - .sram(mux_tree_tapbuf_size8_4_sram[0:3]), - .sram_inv(mux_right_ipin_9_undriven_sram_inv[0:3]), - .out(left_grid_pin_25_[0]) - ); - - - mux_tree_tapbuf_size8 - mux_right_ipin_10 - ( - .in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[14], chany_top_in[14] }), - .sram(mux_tree_tapbuf_size8_5_sram[0:3]), - .sram_inv(mux_right_ipin_10_undriven_sram_inv[0:3]), - .out(left_grid_pin_26_[0]) - ); - - - mux_tree_tapbuf_size8 - mux_right_ipin_13 - ( - .in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[17], chany_top_in[17] }), - .sram(mux_tree_tapbuf_size8_6_sram[0:3]), - .sram_inv(mux_right_ipin_13_undriven_sram_inv[0:3]), - .out(left_grid_pin_29_[0]) - ); - - - mux_tree_tapbuf_size8 - mux_right_ipin_14 - ( - .in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[18], chany_top_in[18] }), - .sram(mux_tree_tapbuf_size8_7_sram[0:3]), - .sram_inv(mux_right_ipin_14_undriven_sram_inv[0:3]), - .out(left_grid_pin_30_[0]) - ); - - - mux_tree_tapbuf_size8_mem - mem_right_ipin_1 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_0_sram[0:3]) - ); - - - mux_tree_tapbuf_size8_mem - mem_right_ipin_2 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_1_sram[0:3]) - ); - - - mux_tree_tapbuf_size8_mem - mem_right_ipin_5 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_2_sram[0:3]) - ); - - - mux_tree_tapbuf_size8_mem - mem_right_ipin_6 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_3_sram[0:3]) - ); - - - mux_tree_tapbuf_size8_mem - mem_right_ipin_9 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_4_sram[0:3]) - ); - - - mux_tree_tapbuf_size8_mem - mem_right_ipin_10 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_5_sram[0:3]) - ); - - - mux_tree_tapbuf_size8_mem - mem_right_ipin_13 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_6_sram[0:3]) - ); - - - mux_tree_tapbuf_size8_mem - mem_right_ipin_14 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_7_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_7_sram[0:3]) - ); - - -endmodule - diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cby_2__1_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cby_2__1_.v deleted file mode 100644 index 594a219..0000000 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cby_2__1_.v +++ /dev/null @@ -1,484 +0,0 @@ - - -module cby_2__1_ -( prog_clk, chany_bottom_in, chany_top_in, ccff_head, chany_bottom_out, chany_top_out, right_grid_pin_0_, left_grid_pin_16_, left_grid_pin_17_, left_grid_pin_18_, left_grid_pin_19_, left_grid_pin_20_, left_grid_pin_21_, left_grid_pin_22_, left_grid_pin_23_, left_grid_pin_24_, left_grid_pin_25_, left_grid_pin_26_, left_grid_pin_27_, left_grid_pin_28_, left_grid_pin_29_, left_grid_pin_30_, left_grid_pin_31_, ccff_tail, gfpga_pad_EMBEDDED_IO_SOC_IN, gfpga_pad_EMBEDDED_IO_SOC_OUT, gfpga_pad_EMBEDDED_IO_SOC_DIR, left_width_0_height_0__pin_0_, left_width_0_height_0__pin_1_upper, left_width_0_height_0__pin_1_lower ); - input [0:0] prog_clk; - input [0:19] chany_bottom_in; - input [0:19] chany_top_in; - input [0:0] ccff_head; - output [0:19] chany_bottom_out; - output [0:19] chany_top_out; - output [0:0] right_grid_pin_0_; - output [0:0] left_grid_pin_16_; - output [0:0] left_grid_pin_17_; - output [0:0] left_grid_pin_18_; - output [0:0] left_grid_pin_19_; - output [0:0] left_grid_pin_20_; - output [0:0] left_grid_pin_21_; - output [0:0] left_grid_pin_22_; - output [0:0] left_grid_pin_23_; - output [0:0] left_grid_pin_24_; - output [0:0] left_grid_pin_25_; - output [0:0] left_grid_pin_26_; - output [0:0] left_grid_pin_27_; - output [0:0] left_grid_pin_28_; - output [0:0] left_grid_pin_29_; - output [0:0] left_grid_pin_30_; - output [0:0] left_grid_pin_31_; - output [0:0] ccff_tail; - input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN; - output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT; - output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR; - input [0:0] left_width_0_height_0__pin_0_; - output [0:0] left_width_0_height_0__pin_1_upper; - output [0:0] left_width_0_height_0__pin_1_lower; - - wire [0:3] mux_left_ipin_0_undriven_sram_inv; - wire [0:3] mux_right_ipin_0_undriven_sram_inv; - wire [0:3] mux_right_ipin_10_undriven_sram_inv; - wire [0:3] mux_right_ipin_11_undriven_sram_inv; - wire [0:3] mux_right_ipin_12_undriven_sram_inv; - wire [0:3] mux_right_ipin_13_undriven_sram_inv; - wire [0:3] mux_right_ipin_14_undriven_sram_inv; - wire [0:3] mux_right_ipin_15_undriven_sram_inv; - wire [0:3] mux_right_ipin_1_undriven_sram_inv; - wire [0:3] mux_right_ipin_2_undriven_sram_inv; - wire [0:3] mux_right_ipin_3_undriven_sram_inv; - wire [0:3] mux_right_ipin_4_undriven_sram_inv; - wire [0:3] mux_right_ipin_5_undriven_sram_inv; - wire [0:3] mux_right_ipin_6_undriven_sram_inv; - wire [0:3] mux_right_ipin_7_undriven_sram_inv; - wire [0:3] mux_right_ipin_8_undriven_sram_inv; - wire [0:3] mux_right_ipin_9_undriven_sram_inv; - wire [0:3] mux_tree_tapbuf_size10_0_sram; - wire [0:3] mux_tree_tapbuf_size10_1_sram; - wire [0:3] mux_tree_tapbuf_size10_2_sram; - wire [0:3] mux_tree_tapbuf_size10_3_sram; - wire [0:3] mux_tree_tapbuf_size10_4_sram; - wire [0:3] mux_tree_tapbuf_size10_5_sram; - wire [0:3] mux_tree_tapbuf_size10_6_sram; - wire [0:3] mux_tree_tapbuf_size10_7_sram; - wire [0:3] mux_tree_tapbuf_size10_8_sram; - wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail; - wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail; - wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail; - wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail; - wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail; - wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail; - wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail; - wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail; - wire [0:3] mux_tree_tapbuf_size8_0_sram; - wire [0:3] mux_tree_tapbuf_size8_1_sram; - wire [0:3] mux_tree_tapbuf_size8_2_sram; - wire [0:3] mux_tree_tapbuf_size8_3_sram; - wire [0:3] mux_tree_tapbuf_size8_4_sram; - wire [0:3] mux_tree_tapbuf_size8_5_sram; - wire [0:3] mux_tree_tapbuf_size8_6_sram; - wire [0:3] mux_tree_tapbuf_size8_7_sram; - wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail; - wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail; - wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail; - wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail; - wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail; - wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail; - wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail; - wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail; - wire ccff_tail_mid; - assign chany_top_out[0] = chany_bottom_in[0]; - assign chany_top_out[1] = chany_bottom_in[1]; - assign chany_top_out[2] = chany_bottom_in[2]; - assign chany_top_out[3] = chany_bottom_in[3]; - assign chany_top_out[4] = chany_bottom_in[4]; - assign chany_top_out[5] = chany_bottom_in[5]; - assign chany_top_out[6] = chany_bottom_in[6]; - assign chany_top_out[7] = chany_bottom_in[7]; - assign chany_top_out[8] = chany_bottom_in[8]; - assign chany_top_out[9] = chany_bottom_in[9]; - assign chany_top_out[10] = chany_bottom_in[10]; - assign chany_top_out[11] = chany_bottom_in[11]; - assign chany_top_out[12] = chany_bottom_in[12]; - assign chany_top_out[13] = chany_bottom_in[13]; - assign chany_top_out[14] = chany_bottom_in[14]; - assign chany_top_out[15] = chany_bottom_in[15]; - assign chany_top_out[16] = chany_bottom_in[16]; - assign chany_top_out[17] = chany_bottom_in[17]; - assign chany_top_out[18] = chany_bottom_in[18]; - assign chany_top_out[19] = chany_bottom_in[19]; - assign chany_bottom_out[0] = chany_top_in[0]; - assign chany_bottom_out[1] = chany_top_in[1]; - assign chany_bottom_out[2] = chany_top_in[2]; - assign chany_bottom_out[3] = chany_top_in[3]; - assign chany_bottom_out[4] = chany_top_in[4]; - assign chany_bottom_out[5] = chany_top_in[5]; - assign chany_bottom_out[6] = chany_top_in[6]; - assign chany_bottom_out[7] = chany_top_in[7]; - assign chany_bottom_out[8] = chany_top_in[8]; - assign chany_bottom_out[9] = chany_top_in[9]; - assign chany_bottom_out[10] = chany_top_in[10]; - assign chany_bottom_out[11] = chany_top_in[11]; - assign chany_bottom_out[12] = chany_top_in[12]; - assign chany_bottom_out[13] = chany_top_in[13]; - assign chany_bottom_out[14] = chany_top_in[14]; - assign chany_bottom_out[15] = chany_top_in[15]; - assign chany_bottom_out[16] = chany_top_in[16]; - assign chany_bottom_out[17] = chany_top_in[17]; - assign chany_bottom_out[18] = chany_top_in[18]; - assign chany_bottom_out[19] = chany_top_in[19]; - assign left_width_0_height_0__pin_1_lower[0] = left_width_0_height_0__pin_1_upper[0]; - - mux_tree_tapbuf_size10 - mux_left_ipin_0 - ( - .in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[16], chany_top_in[16] }), - .sram(mux_tree_tapbuf_size10_0_sram[0:3]), - .sram_inv(mux_left_ipin_0_undriven_sram_inv[0:3]), - .out(right_grid_pin_0_[0]) - ); - - - mux_tree_tapbuf_size10 - mux_right_ipin_0 - ( - .in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[17], chany_top_in[17] }), - .sram(mux_tree_tapbuf_size10_1_sram[0:3]), - .sram_inv(mux_right_ipin_0_undriven_sram_inv[0:3]), - .out(left_grid_pin_16_[0]) - ); - - - mux_tree_tapbuf_size10 - mux_right_ipin_3 - ( - .in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[14], chany_top_in[14] }), - .sram(mux_tree_tapbuf_size10_2_sram[0:3]), - .sram_inv(mux_right_ipin_3_undriven_sram_inv[0:3]), - .out(left_grid_pin_19_[0]) - ); - - - mux_tree_tapbuf_size10 - mux_right_ipin_4 - ( - .in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[15], chany_top_in[15] }), - .sram(mux_tree_tapbuf_size10_3_sram[0:3]), - .sram_inv(mux_right_ipin_4_undriven_sram_inv[0:3]), - .out(left_grid_pin_20_[0]) - ); - - - mux_tree_tapbuf_size10 - mux_right_ipin_7 - ( - .in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[18], chany_top_in[18] }), - .sram(mux_tree_tapbuf_size10_4_sram[0:3]), - .sram_inv(mux_right_ipin_7_undriven_sram_inv[0:3]), - .out(left_grid_pin_23_[0]) - ); - - - mux_tree_tapbuf_size10 - mux_right_ipin_8 - ( - .in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[13], chany_top_in[13], chany_bottom_in[19], chany_top_in[19] }), - .sram(mux_tree_tapbuf_size10_5_sram[0:3]), - .sram_inv(mux_right_ipin_8_undriven_sram_inv[0:3]), - .out(left_grid_pin_24_[0]) - ); - - - mux_tree_tapbuf_size10 - mux_right_ipin_11 - ( - .in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12], chany_bottom_in[16], chany_top_in[16] }), - .sram(mux_tree_tapbuf_size10_6_sram[0:3]), - .sram_inv(mux_right_ipin_11_undriven_sram_inv[0:3]), - .out(left_grid_pin_27_[0]) - ); - - - mux_tree_tapbuf_size10 - mux_right_ipin_12 - ( - .in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[13], chany_top_in[13], chany_bottom_in[17], chany_top_in[17] }), - .sram(mux_tree_tapbuf_size10_7_sram[0:3]), - .sram_inv(mux_right_ipin_12_undriven_sram_inv[0:3]), - .out(left_grid_pin_28_[0]) - ); - - - mux_tree_tapbuf_size10 - mux_right_ipin_15 - ( - .in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[16], chany_top_in[16] }), - .sram(mux_tree_tapbuf_size10_8_sram[0:3]), - .sram_inv(mux_right_ipin_15_undriven_sram_inv[0:3]), - .out(left_grid_pin_31_[0]) - ); - - - mux_tree_tapbuf_size10_mem - mem_left_ipin_0 - ( - .prog_clk(prog_clk[0]), - .ccff_head(ccff_head[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_0_sram[0:3]) - ); - - - mux_tree_tapbuf_size10_mem - mem_right_ipin_0 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_1_sram[0:3]) - ); - - - mux_tree_tapbuf_size10_mem - mem_right_ipin_3 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_2_sram[0:3]) - ); - - - mux_tree_tapbuf_size10_mem - mem_right_ipin_4 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_3_sram[0:3]) - ); - - - mux_tree_tapbuf_size10_mem - mem_right_ipin_7 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_4_sram[0:3]) - ); - - - mux_tree_tapbuf_size10_mem - mem_right_ipin_8 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_5_sram[0:3]) - ); - - - mux_tree_tapbuf_size10_mem - mem_right_ipin_11 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_6_sram[0:3]) - ); - - - mux_tree_tapbuf_size10_mem - mem_right_ipin_12 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_7_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_7_sram[0:3]) - ); - - - mux_tree_tapbuf_size10_mem - mem_right_ipin_15 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_7_ccff_tail[0]), - .ccff_tail(ccff_tail_mid), - .mem_out(mux_tree_tapbuf_size10_8_sram[0:3]) - ); - - - mux_tree_tapbuf_size8 - mux_right_ipin_1 - ( - .in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[14], chany_top_in[14] }), - .sram(mux_tree_tapbuf_size8_0_sram[0:3]), - .sram_inv(mux_right_ipin_1_undriven_sram_inv[0:3]), - .out(left_grid_pin_17_[0]) - ); - - - mux_tree_tapbuf_size8 - mux_right_ipin_2 - ( - .in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[15], chany_top_in[15] }), - .sram(mux_tree_tapbuf_size8_1_sram[0:3]), - .sram_inv(mux_right_ipin_2_undriven_sram_inv[0:3]), - .out(left_grid_pin_18_[0]) - ); - - - mux_tree_tapbuf_size8 - mux_right_ipin_5 - ( - .in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[18], chany_top_in[18] }), - .sram(mux_tree_tapbuf_size8_2_sram[0:3]), - .sram_inv(mux_right_ipin_5_undriven_sram_inv[0:3]), - .out(left_grid_pin_21_[0]) - ); - - - mux_tree_tapbuf_size8 - mux_right_ipin_6 - ( - .in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[19], chany_top_in[19] }), - .sram(mux_tree_tapbuf_size8_3_sram[0:3]), - .sram_inv(mux_right_ipin_6_undriven_sram_inv[0:3]), - .out(left_grid_pin_22_[0]) - ); - - - mux_tree_tapbuf_size8 - mux_right_ipin_9 - ( - .in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[14], chany_top_in[14] }), - .sram(mux_tree_tapbuf_size8_4_sram[0:3]), - .sram_inv(mux_right_ipin_9_undriven_sram_inv[0:3]), - .out(left_grid_pin_25_[0]) - ); - - - mux_tree_tapbuf_size8 - mux_right_ipin_10 - ( - .in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[15], chany_top_in[15] }), - .sram(mux_tree_tapbuf_size8_5_sram[0:3]), - .sram_inv(mux_right_ipin_10_undriven_sram_inv[0:3]), - .out(left_grid_pin_26_[0]) - ); - - - mux_tree_tapbuf_size8 - mux_right_ipin_13 - ( - .in({ chany_bottom_in[0], chany_top_in[0], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[10], chany_top_in[10], chany_bottom_in[18], chany_top_in[18] }), - .sram(mux_tree_tapbuf_size8_6_sram[0:3]), - .sram_inv(mux_right_ipin_13_undriven_sram_inv[0:3]), - .out(left_grid_pin_29_[0]) - ); - - - mux_tree_tapbuf_size8 - mux_right_ipin_14 - ( - .in({ chany_bottom_in[1], chany_top_in[1], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[11], chany_top_in[11], chany_bottom_in[19], chany_top_in[19] }), - .sram(mux_tree_tapbuf_size8_7_sram[0:3]), - .sram_inv(mux_right_ipin_14_undriven_sram_inv[0:3]), - .out(left_grid_pin_30_[0]) - ); - - - mux_tree_tapbuf_size8_mem - mem_right_ipin_1 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_0_sram[0:3]) - ); - - - mux_tree_tapbuf_size8_mem - mem_right_ipin_2 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_1_sram[0:3]) - ); - - - mux_tree_tapbuf_size8_mem - mem_right_ipin_5 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_2_sram[0:3]) - ); - - - mux_tree_tapbuf_size8_mem - mem_right_ipin_6 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_3_sram[0:3]) - ); - - - mux_tree_tapbuf_size8_mem - mem_right_ipin_9 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_4_sram[0:3]) - ); - - - mux_tree_tapbuf_size8_mem - mem_right_ipin_10 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_5_sram[0:3]) - ); - - - mux_tree_tapbuf_size8_mem - mem_right_ipin_13 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_7_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_6_sram[0:3]) - ); - - - mux_tree_tapbuf_size8_mem - mem_right_ipin_14 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_7_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_7_sram[0:3]) - ); - - - logical_tile_io_mode_io_ - logical_tile_io_mode_io__0 - ( - .prog_clk(prog_clk[0]), - .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[0]), - .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[0]), - .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[0]), - .io_outpad(left_width_0_height_0__pin_0_[0]), - .ccff_head(ccff_tail_mid), - .io_inpad(left_width_0_height_0__pin_1_upper[0]), - .ccff_tail(ccff_tail[0]) - ); - - -endmodule - diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_0__0_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_0__0_.v deleted file mode 100644 index 6932ebf..0000000 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_0__0_.v +++ /dev/null @@ -1,501 +0,0 @@ - - -module sb_0__0_ -( prog_clk, chany_top_in, top_left_grid_pin_1_, chanx_right_in, right_bottom_grid_pin_1_, right_bottom_grid_pin_3_, right_bottom_grid_pin_5_, right_bottom_grid_pin_7_, right_bottom_grid_pin_9_, right_bottom_grid_pin_11_, ccff_head, chany_top_out, chanx_right_out, ccff_tail ); - input [0:0] prog_clk; - input [0:19] chany_top_in; - input [0:0] top_left_grid_pin_1_; - input [0:19] chanx_right_in; - input [0:0] right_bottom_grid_pin_1_; - input [0:0] right_bottom_grid_pin_3_; - input [0:0] right_bottom_grid_pin_5_; - input [0:0] right_bottom_grid_pin_7_; - input [0:0] right_bottom_grid_pin_9_; - input [0:0] right_bottom_grid_pin_11_; - input [0:0] ccff_head; - output [0:19] chany_top_out; - output [0:19] chanx_right_out; - output [0:0] ccff_tail; - - wire [0:2] mux_right_track_0_undriven_sram_inv; - wire [0:1] mux_right_track_10_undriven_sram_inv; - wire [0:1] mux_right_track_12_undriven_sram_inv; - wire [0:1] mux_right_track_14_undriven_sram_inv; - wire [0:1] mux_right_track_16_undriven_sram_inv; - wire [0:1] mux_right_track_18_undriven_sram_inv; - wire [0:1] mux_right_track_24_undriven_sram_inv; - wire [0:1] mux_right_track_26_undriven_sram_inv; - wire [0:1] mux_right_track_28_undriven_sram_inv; - wire [0:2] mux_right_track_2_undriven_sram_inv; - wire [0:1] mux_right_track_30_undriven_sram_inv; - wire [0:1] mux_right_track_32_undriven_sram_inv; - wire [0:1] mux_right_track_34_undriven_sram_inv; - wire [0:2] mux_right_track_4_undriven_sram_inv; - wire [0:2] mux_right_track_6_undriven_sram_inv; - wire [0:1] mux_right_track_8_undriven_sram_inv; - wire [0:1] mux_top_track_0_undriven_sram_inv; - wire [0:1] mux_top_track_24_undriven_sram_inv; - wire [0:1] mux_top_track_4_undriven_sram_inv; - wire [0:1] mux_top_track_8_undriven_sram_inv; - wire [0:1] mux_tree_tapbuf_size2_0_sram; - wire [0:1] mux_tree_tapbuf_size2_10_sram; - wire [0:1] mux_tree_tapbuf_size2_11_sram; - wire [0:1] mux_tree_tapbuf_size2_12_sram; - wire [0:1] mux_tree_tapbuf_size2_13_sram; - wire [0:1] mux_tree_tapbuf_size2_14_sram; - wire [0:1] mux_tree_tapbuf_size2_15_sram; - wire [0:1] mux_tree_tapbuf_size2_1_sram; - wire [0:1] mux_tree_tapbuf_size2_2_sram; - wire [0:1] mux_tree_tapbuf_size2_3_sram; - wire [0:1] mux_tree_tapbuf_size2_4_sram; - wire [0:1] mux_tree_tapbuf_size2_5_sram; - wire [0:1] mux_tree_tapbuf_size2_6_sram; - wire [0:1] mux_tree_tapbuf_size2_7_sram; - wire [0:1] mux_tree_tapbuf_size2_8_sram; - wire [0:1] mux_tree_tapbuf_size2_9_sram; - wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail; - wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail; - wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail; - wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail; - wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail; - wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail; - wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail; - wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail; - wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail; - wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail; - wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail; - wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail; - wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail; - wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail; - wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail; - wire [0:2] mux_tree_tapbuf_size4_0_sram; - wire [0:2] mux_tree_tapbuf_size4_1_sram; - wire [0:2] mux_tree_tapbuf_size4_2_sram; - wire [0:2] mux_tree_tapbuf_size4_3_sram; - wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail; - wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail; - wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail; - wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail; - assign chanx_right_out[10] = chany_top_in[9]; - assign chanx_right_out[11] = chany_top_in[10]; - assign chanx_right_out[18] = chany_top_in[17]; - assign chanx_right_out[19] = chany_top_in[18]; - assign chany_top_out[19] = chanx_right_in[0]; - assign chany_top_out[1] = chanx_right_in[2]; - assign chany_top_out[3] = chanx_right_in[4]; - assign chany_top_out[5] = chanx_right_in[6]; - assign chany_top_out[6] = chanx_right_in[7]; - assign chany_top_out[7] = chanx_right_in[8]; - assign chany_top_out[8] = chanx_right_in[9]; - assign chany_top_out[9] = chanx_right_in[10]; - assign chany_top_out[10] = chanx_right_in[11]; - assign chany_top_out[11] = chanx_right_in[12]; - assign chany_top_out[13] = chanx_right_in[14]; - assign chany_top_out[14] = chanx_right_in[15]; - assign chany_top_out[15] = chanx_right_in[16]; - assign chany_top_out[16] = chanx_right_in[17]; - assign chany_top_out[17] = chanx_right_in[18]; - assign chany_top_out[18] = chanx_right_in[19]; - - mux_tree_tapbuf_size2 - mux_top_track_0 - ( - .in({ top_left_grid_pin_1_[0], chanx_right_in[1] }), - .sram(mux_tree_tapbuf_size2_0_sram[0:1]), - .sram_inv(mux_top_track_0_undriven_sram_inv[0:1]), - .out(chany_top_out[0]) - ); - - - mux_tree_tapbuf_size2 - mux_top_track_4 - ( - .in({ top_left_grid_pin_1_[0], chanx_right_in[3] }), - .sram(mux_tree_tapbuf_size2_1_sram[0:1]), - .sram_inv(mux_top_track_4_undriven_sram_inv[0:1]), - .out(chany_top_out[2]) - ); - - - mux_tree_tapbuf_size2 - mux_top_track_8 - ( - .in({ top_left_grid_pin_1_[0], chanx_right_in[5] }), - .sram(mux_tree_tapbuf_size2_2_sram[0:1]), - .sram_inv(mux_top_track_8_undriven_sram_inv[0:1]), - .out(chany_top_out[4]) - ); - - - mux_tree_tapbuf_size2 - mux_top_track_24 - ( - .in({ top_left_grid_pin_1_[0], chanx_right_in[13] }), - .sram(mux_tree_tapbuf_size2_3_sram[0:1]), - .sram_inv(mux_top_track_24_undriven_sram_inv[0:1]), - .out(chany_top_out[12]) - ); - - - mux_tree_tapbuf_size2 - mux_right_track_8 - ( - .in({ chany_top_in[3], right_bottom_grid_pin_1_[0] }), - .sram(mux_tree_tapbuf_size2_4_sram[0:1]), - .sram_inv(mux_right_track_8_undriven_sram_inv[0:1]), - .out(chanx_right_out[4]) - ); - - - mux_tree_tapbuf_size2 - mux_right_track_10 - ( - .in({ chany_top_in[4], right_bottom_grid_pin_3_[0] }), - .sram(mux_tree_tapbuf_size2_5_sram[0:1]), - .sram_inv(mux_right_track_10_undriven_sram_inv[0:1]), - .out(chanx_right_out[5]) - ); - - - mux_tree_tapbuf_size2 - mux_right_track_12 - ( - .in({ chany_top_in[5], right_bottom_grid_pin_5_[0] }), - .sram(mux_tree_tapbuf_size2_6_sram[0:1]), - .sram_inv(mux_right_track_12_undriven_sram_inv[0:1]), - .out(chanx_right_out[6]) - ); - - - mux_tree_tapbuf_size2 - mux_right_track_14 - ( - .in({ chany_top_in[6], right_bottom_grid_pin_7_[0] }), - .sram(mux_tree_tapbuf_size2_7_sram[0:1]), - .sram_inv(mux_right_track_14_undriven_sram_inv[0:1]), - .out(chanx_right_out[7]) - ); - - - mux_tree_tapbuf_size2 - mux_right_track_16 - ( - .in({ chany_top_in[7], right_bottom_grid_pin_9_[0] }), - .sram(mux_tree_tapbuf_size2_8_sram[0:1]), - .sram_inv(mux_right_track_16_undriven_sram_inv[0:1]), - .out(chanx_right_out[8]) - ); - - - mux_tree_tapbuf_size2 - mux_right_track_18 - ( - .in({ chany_top_in[8], right_bottom_grid_pin_11_[0] }), - .sram(mux_tree_tapbuf_size2_9_sram[0:1]), - .sram_inv(mux_right_track_18_undriven_sram_inv[0:1]), - .out(chanx_right_out[9]) - ); - - - mux_tree_tapbuf_size2 - mux_right_track_24 - ( - .in({ chany_top_in[11], right_bottom_grid_pin_1_[0] }), - .sram(mux_tree_tapbuf_size2_10_sram[0:1]), - .sram_inv(mux_right_track_24_undriven_sram_inv[0:1]), - .out(chanx_right_out[12]) - ); - - - mux_tree_tapbuf_size2 - mux_right_track_26 - ( - .in({ chany_top_in[12], right_bottom_grid_pin_3_[0] }), - .sram(mux_tree_tapbuf_size2_11_sram[0:1]), - .sram_inv(mux_right_track_26_undriven_sram_inv[0:1]), - .out(chanx_right_out[13]) - ); - - - mux_tree_tapbuf_size2 - mux_right_track_28 - ( - .in({ chany_top_in[13], right_bottom_grid_pin_5_[0] }), - .sram(mux_tree_tapbuf_size2_12_sram[0:1]), - .sram_inv(mux_right_track_28_undriven_sram_inv[0:1]), - .out(chanx_right_out[14]) - ); - - - mux_tree_tapbuf_size2 - mux_right_track_30 - ( - .in({ chany_top_in[14], right_bottom_grid_pin_7_[0] }), - .sram(mux_tree_tapbuf_size2_13_sram[0:1]), - .sram_inv(mux_right_track_30_undriven_sram_inv[0:1]), - .out(chanx_right_out[15]) - ); - - - mux_tree_tapbuf_size2 - mux_right_track_32 - ( - .in({ chany_top_in[15], right_bottom_grid_pin_9_[0] }), - .sram(mux_tree_tapbuf_size2_14_sram[0:1]), - .sram_inv(mux_right_track_32_undriven_sram_inv[0:1]), - .out(chanx_right_out[16]) - ); - - - mux_tree_tapbuf_size2 - mux_right_track_34 - ( - .in({ chany_top_in[16], right_bottom_grid_pin_11_[0] }), - .sram(mux_tree_tapbuf_size2_15_sram[0:1]), - .sram_inv(mux_right_track_34_undriven_sram_inv[0:1]), - .out(chanx_right_out[17]) - ); - - - mux_tree_tapbuf_size2_mem - mem_top_track_0 - ( - .prog_clk(prog_clk[0]), - .ccff_head(ccff_head[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_0_sram[0:1]) - ); - - - mux_tree_tapbuf_size2_mem - mem_top_track_4 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_1_sram[0:1]) - ); - - - mux_tree_tapbuf_size2_mem - mem_top_track_8 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_2_sram[0:1]) - ); - - - mux_tree_tapbuf_size2_mem - mem_top_track_24 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_3_sram[0:1]) - ); - - - mux_tree_tapbuf_size2_mem - mem_right_track_8 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_4_sram[0:1]) - ); - - - mux_tree_tapbuf_size2_mem - mem_right_track_10 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_5_sram[0:1]) - ); - - - mux_tree_tapbuf_size2_mem - mem_right_track_12 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_6_sram[0:1]) - ); - - - mux_tree_tapbuf_size2_mem - mem_right_track_14 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_7_sram[0:1]) - ); - - - mux_tree_tapbuf_size2_mem - mem_right_track_16 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_8_sram[0:1]) - ); - - - mux_tree_tapbuf_size2_mem - mem_right_track_18 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_9_sram[0:1]) - ); - - - mux_tree_tapbuf_size2_mem - mem_right_track_24 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_10_sram[0:1]) - ); - - - mux_tree_tapbuf_size2_mem - mem_right_track_26 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_11_sram[0:1]) - ); - - - mux_tree_tapbuf_size2_mem - mem_right_track_28 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_12_sram[0:1]) - ); - - - mux_tree_tapbuf_size2_mem - mem_right_track_30 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_13_sram[0:1]) - ); - - - mux_tree_tapbuf_size2_mem - mem_right_track_32 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_14_sram[0:1]) - ); - - - mux_tree_tapbuf_size2_mem - mem_right_track_34 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail[0]), - .ccff_tail(ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_15_sram[0:1]) - ); - - - mux_tree_tapbuf_size4 - mux_right_track_0 - ( - .in({ chany_top_in[19], right_bottom_grid_pin_1_[0], right_bottom_grid_pin_5_[0], right_bottom_grid_pin_9_[0] }), - .sram(mux_tree_tapbuf_size4_0_sram[0:2]), - .sram_inv(mux_right_track_0_undriven_sram_inv[0:2]), - .out(chanx_right_out[0]) - ); - - - mux_tree_tapbuf_size4 - mux_right_track_2 - ( - .in({ chany_top_in[0], right_bottom_grid_pin_3_[0], right_bottom_grid_pin_7_[0], right_bottom_grid_pin_11_[0] }), - .sram(mux_tree_tapbuf_size4_1_sram[0:2]), - .sram_inv(mux_right_track_2_undriven_sram_inv[0:2]), - .out(chanx_right_out[1]) - ); - - - mux_tree_tapbuf_size4 - mux_right_track_4 - ( - .in({ chany_top_in[1], right_bottom_grid_pin_1_[0], right_bottom_grid_pin_5_[0], right_bottom_grid_pin_9_[0] }), - .sram(mux_tree_tapbuf_size4_2_sram[0:2]), - .sram_inv(mux_right_track_4_undriven_sram_inv[0:2]), - .out(chanx_right_out[2]) - ); - - - mux_tree_tapbuf_size4 - mux_right_track_6 - ( - .in({ chany_top_in[2], right_bottom_grid_pin_3_[0], right_bottom_grid_pin_7_[0], right_bottom_grid_pin_11_[0] }), - .sram(mux_tree_tapbuf_size4_3_sram[0:2]), - .sram_inv(mux_right_track_6_undriven_sram_inv[0:2]), - .out(chanx_right_out[3]) - ); - - - mux_tree_tapbuf_size4_mem - mem_right_track_0 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size4_0_sram[0:2]) - ); - - - mux_tree_tapbuf_size4_mem - mem_right_track_2 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size4_1_sram[0:2]) - ); - - - mux_tree_tapbuf_size4_mem - mem_right_track_4 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size4_2_sram[0:2]) - ); - - - mux_tree_tapbuf_size4_mem - mem_right_track_6 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size4_3_sram[0:2]) - ); - - -endmodule - diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_0__1_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_0__1_.v deleted file mode 100644 index 6caa8b1..0000000 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_0__1_.v +++ /dev/null @@ -1,812 +0,0 @@ - - -module sb_0__1_ -( prog_clk, chany_top_in, top_left_grid_pin_1_, chanx_right_in, right_bottom_grid_pin_34_, right_bottom_grid_pin_35_, right_bottom_grid_pin_36_, right_bottom_grid_pin_37_, right_bottom_grid_pin_38_, right_bottom_grid_pin_39_, right_bottom_grid_pin_40_, right_bottom_grid_pin_41_, chany_bottom_in, bottom_left_grid_pin_1_, ccff_head, chany_top_out, chanx_right_out, chany_bottom_out, ccff_tail ); - input [0:0] prog_clk; - input [0:19] chany_top_in; - input [0:0] top_left_grid_pin_1_; - input [0:19] chanx_right_in; - input [0:0] right_bottom_grid_pin_34_; - input [0:0] right_bottom_grid_pin_35_; - input [0:0] right_bottom_grid_pin_36_; - input [0:0] right_bottom_grid_pin_37_; - input [0:0] right_bottom_grid_pin_38_; - input [0:0] right_bottom_grid_pin_39_; - input [0:0] right_bottom_grid_pin_40_; - input [0:0] right_bottom_grid_pin_41_; - input [0:19] chany_bottom_in; - input [0:0] bottom_left_grid_pin_1_; - input [0:0] ccff_head; - output [0:19] chany_top_out; - output [0:19] chanx_right_out; - output [0:19] chany_bottom_out; - output [0:0] ccff_tail; - - wire [0:2] mux_bottom_track_17_undriven_sram_inv; - wire [0:2] mux_bottom_track_1_undriven_sram_inv; - wire [0:2] mux_bottom_track_25_undriven_sram_inv; - wire [0:1] mux_bottom_track_33_undriven_sram_inv; - wire [0:2] mux_bottom_track_3_undriven_sram_inv; - wire [0:2] mux_bottom_track_5_undriven_sram_inv; - wire [0:2] mux_bottom_track_9_undriven_sram_inv; - wire [0:2] mux_right_track_0_undriven_sram_inv; - wire [0:2] mux_right_track_10_undriven_sram_inv; - wire [0:2] mux_right_track_12_undriven_sram_inv; - wire [0:2] mux_right_track_14_undriven_sram_inv; - wire [0:1] mux_right_track_16_undriven_sram_inv; - wire [0:1] mux_right_track_18_undriven_sram_inv; - wire [0:1] mux_right_track_20_undriven_sram_inv; - wire [0:1] mux_right_track_22_undriven_sram_inv; - wire [0:2] mux_right_track_24_undriven_sram_inv; - wire [0:1] mux_right_track_26_undriven_sram_inv; - wire [0:1] mux_right_track_28_undriven_sram_inv; - wire [0:2] mux_right_track_2_undriven_sram_inv; - wire [0:1] mux_right_track_30_undriven_sram_inv; - wire [0:1] mux_right_track_32_undriven_sram_inv; - wire [0:1] mux_right_track_34_undriven_sram_inv; - wire [0:1] mux_right_track_36_undriven_sram_inv; - wire [0:2] mux_right_track_4_undriven_sram_inv; - wire [0:2] mux_right_track_6_undriven_sram_inv; - wire [0:2] mux_right_track_8_undriven_sram_inv; - wire [0:2] mux_top_track_0_undriven_sram_inv; - wire [0:2] mux_top_track_16_undriven_sram_inv; - wire [0:2] mux_top_track_24_undriven_sram_inv; - wire [0:2] mux_top_track_2_undriven_sram_inv; - wire [0:2] mux_top_track_32_undriven_sram_inv; - wire [0:2] mux_top_track_4_undriven_sram_inv; - wire [0:2] mux_top_track_8_undriven_sram_inv; - wire [0:1] mux_tree_tapbuf_size2_0_sram; - wire [0:1] mux_tree_tapbuf_size2_1_sram; - wire [0:1] mux_tree_tapbuf_size2_2_sram; - wire [0:1] mux_tree_tapbuf_size2_3_sram; - wire [0:1] mux_tree_tapbuf_size2_4_sram; - wire [0:1] mux_tree_tapbuf_size2_5_sram; - wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail; - wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail; - wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail; - wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail; - wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail; - wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail; - wire [0:1] mux_tree_tapbuf_size3_0_sram; - wire [0:1] mux_tree_tapbuf_size3_1_sram; - wire [0:1] mux_tree_tapbuf_size3_2_sram; - wire [0:1] mux_tree_tapbuf_size3_3_sram; - wire [0:1] mux_tree_tapbuf_size3_4_sram; - wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail; - wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail; - wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail; - wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail; - wire [0:2] mux_tree_tapbuf_size4_0_sram; - wire [0:2] mux_tree_tapbuf_size4_1_sram; - wire [0:2] mux_tree_tapbuf_size4_2_sram; - wire [0:2] mux_tree_tapbuf_size4_3_sram; - wire [0:2] mux_tree_tapbuf_size4_4_sram; - wire [0:2] mux_tree_tapbuf_size4_5_sram; - wire [0:2] mux_tree_tapbuf_size4_6_sram; - wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail; - wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail; - wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail; - wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail; - wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail; - wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail; - wire [0:0] mux_tree_tapbuf_size4_mem_6_ccff_tail; - wire [0:2] mux_tree_tapbuf_size5_0_sram; - wire [0:2] mux_tree_tapbuf_size5_1_sram; - wire [0:2] mux_tree_tapbuf_size5_2_sram; - wire [0:2] mux_tree_tapbuf_size5_3_sram; - wire [0:2] mux_tree_tapbuf_size5_4_sram; - wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail; - wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail; - wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail; - wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail; - wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail; - wire [0:2] mux_tree_tapbuf_size6_0_sram; - wire [0:2] mux_tree_tapbuf_size6_1_sram; - wire [0:2] mux_tree_tapbuf_size6_2_sram; - wire [0:2] mux_tree_tapbuf_size6_3_sram; - wire [0:2] mux_tree_tapbuf_size6_4_sram; - wire [0:2] mux_tree_tapbuf_size6_5_sram; - wire [0:2] mux_tree_tapbuf_size6_6_sram; - wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail; - wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail; - wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail; - wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail; - wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail; - wire [0:0] mux_tree_tapbuf_size6_mem_5_ccff_tail; - wire [0:0] mux_tree_tapbuf_size6_mem_6_ccff_tail; - wire [0:2] mux_tree_tapbuf_size7_0_sram; - wire [0:2] mux_tree_tapbuf_size7_1_sram; - wire [0:2] mux_tree_tapbuf_size7_2_sram; - wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail; - wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail; - wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail; - assign chany_bottom_out[3] = chany_top_in[2]; - assign chany_bottom_out[5] = chany_top_in[4]; - assign chany_bottom_out[6] = chany_top_in[5]; - assign chany_bottom_out[7] = chany_top_in[6]; - assign chany_bottom_out[9] = chany_top_in[8]; - assign chany_bottom_out[10] = chany_top_in[9]; - assign chany_bottom_out[11] = chany_top_in[10]; - assign chany_bottom_out[13] = chany_top_in[12]; - assign chany_bottom_out[14] = chany_top_in[13]; - assign chany_bottom_out[15] = chany_top_in[14]; - assign chany_bottom_out[17] = chany_top_in[16]; - assign chany_bottom_out[18] = chany_top_in[17]; - assign chany_bottom_out[19] = chany_top_in[18]; - assign chanx_right_out[19] = right_bottom_grid_pin_41_[0]; - assign chany_top_out[3] = chany_bottom_in[2]; - assign chany_top_out[5] = chany_bottom_in[4]; - assign chany_top_out[6] = chany_bottom_in[5]; - assign chany_top_out[7] = chany_bottom_in[6]; - assign chany_top_out[9] = chany_bottom_in[8]; - assign chany_top_out[10] = chany_bottom_in[9]; - assign chany_top_out[11] = chany_bottom_in[10]; - assign chany_top_out[13] = chany_bottom_in[12]; - assign chany_top_out[14] = chany_bottom_in[13]; - assign chany_top_out[15] = chany_bottom_in[14]; - assign chany_top_out[17] = chany_bottom_in[16]; - assign chany_top_out[18] = chany_bottom_in[17]; - assign chany_top_out[19] = chany_bottom_in[18]; - - mux_tree_tapbuf_size6 - mux_top_track_0 - ( - .in({ top_left_grid_pin_1_[0], chanx_right_in[1], chanx_right_in[8], chanx_right_in[15], chany_bottom_in[2], chany_bottom_in[12] }), - .sram(mux_tree_tapbuf_size6_0_sram[0:2]), - .sram_inv(mux_top_track_0_undriven_sram_inv[0:2]), - .out(chany_top_out[0]) - ); - - - mux_tree_tapbuf_size6 - mux_top_track_4 - ( - .in({ top_left_grid_pin_1_[0], chanx_right_in[3], chanx_right_in[10], chanx_right_in[17], chany_bottom_in[5], chany_bottom_in[14] }), - .sram(mux_tree_tapbuf_size6_1_sram[0:2]), - .sram_inv(mux_top_track_4_undriven_sram_inv[0:2]), - .out(chany_top_out[2]) - ); - - - mux_tree_tapbuf_size6 - mux_top_track_8 - ( - .in({ top_left_grid_pin_1_[0], chanx_right_in[4], chanx_right_in[11], chanx_right_in[18], chany_bottom_in[6], chany_bottom_in[16] }), - .sram(mux_tree_tapbuf_size6_2_sram[0:2]), - .sram_inv(mux_top_track_8_undriven_sram_inv[0:2]), - .out(chany_top_out[4]) - ); - - - mux_tree_tapbuf_size6 - mux_right_track_0 - ( - .in({ chany_top_in[2], right_bottom_grid_pin_34_[0], right_bottom_grid_pin_36_[0], right_bottom_grid_pin_38_[0], right_bottom_grid_pin_40_[0], chany_bottom_in[2] }), - .sram(mux_tree_tapbuf_size6_3_sram[0:2]), - .sram_inv(mux_right_track_0_undriven_sram_inv[0:2]), - .out(chanx_right_out[0]) - ); - - - mux_tree_tapbuf_size6 - mux_bottom_track_1 - ( - .in({ chany_top_in[2], chany_top_in[12], chanx_right_in[5], chanx_right_in[12], chanx_right_in[19], bottom_left_grid_pin_1_[0] }), - .sram(mux_tree_tapbuf_size6_4_sram[0:2]), - .sram_inv(mux_bottom_track_1_undriven_sram_inv[0:2]), - .out(chany_bottom_out[0]) - ); - - - mux_tree_tapbuf_size6 - mux_bottom_track_5 - ( - .in({ chany_top_in[5], chany_top_in[14], chanx_right_in[3], chanx_right_in[10], chanx_right_in[17], bottom_left_grid_pin_1_[0] }), - .sram(mux_tree_tapbuf_size6_5_sram[0:2]), - .sram_inv(mux_bottom_track_5_undriven_sram_inv[0:2]), - .out(chany_bottom_out[2]) - ); - - - mux_tree_tapbuf_size6 - mux_bottom_track_9 - ( - .in({ chany_top_in[6], chany_top_in[16], chanx_right_in[2], chanx_right_in[9], chanx_right_in[16], bottom_left_grid_pin_1_[0] }), - .sram(mux_tree_tapbuf_size6_6_sram[0:2]), - .sram_inv(mux_bottom_track_9_undriven_sram_inv[0:2]), - .out(chany_bottom_out[4]) - ); - - - mux_tree_tapbuf_size6_mem - mem_top_track_0 - ( - .prog_clk(prog_clk[0]), - .ccff_head(ccff_head[0]), - .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_0_sram[0:2]) - ); - - - mux_tree_tapbuf_size6_mem - mem_top_track_4 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_1_sram[0:2]) - ); - - - mux_tree_tapbuf_size6_mem - mem_top_track_8 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_2_sram[0:2]) - ); - - - mux_tree_tapbuf_size6_mem - mem_right_track_0 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_3_sram[0:2]) - ); - - - mux_tree_tapbuf_size6_mem - mem_bottom_track_1 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size6_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_4_sram[0:2]) - ); - - - mux_tree_tapbuf_size6_mem - mem_bottom_track_5 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size6_mem_5_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_5_sram[0:2]) - ); - - - mux_tree_tapbuf_size6_mem - mem_bottom_track_9 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size6_mem_5_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size6_mem_6_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_6_sram[0:2]) - ); - - - mux_tree_tapbuf_size5 - mux_top_track_2 - ( - .in({ chanx_right_in[2], chanx_right_in[9], chanx_right_in[16], chany_bottom_in[4], chany_bottom_in[13] }), - .sram(mux_tree_tapbuf_size5_0_sram[0:2]), - .sram_inv(mux_top_track_2_undriven_sram_inv[0:2]), - .out(chany_top_out[1]) - ); - - - mux_tree_tapbuf_size5 - mux_top_track_16 - ( - .in({ chanx_right_in[5], chanx_right_in[12], chanx_right_in[19], chany_bottom_in[8], chany_bottom_in[17] }), - .sram(mux_tree_tapbuf_size5_1_sram[0:2]), - .sram_inv(mux_top_track_16_undriven_sram_inv[0:2]), - .out(chany_top_out[8]) - ); - - - mux_tree_tapbuf_size5 - mux_bottom_track_3 - ( - .in({ chany_top_in[4], chany_top_in[13], chanx_right_in[4], chanx_right_in[11], chanx_right_in[18] }), - .sram(mux_tree_tapbuf_size5_2_sram[0:2]), - .sram_inv(mux_bottom_track_3_undriven_sram_inv[0:2]), - .out(chany_bottom_out[1]) - ); - - - mux_tree_tapbuf_size5 - mux_bottom_track_17 - ( - .in({ chany_top_in[8], chany_top_in[17], chanx_right_in[1], chanx_right_in[8], chanx_right_in[15] }), - .sram(mux_tree_tapbuf_size5_3_sram[0:2]), - .sram_inv(mux_bottom_track_17_undriven_sram_inv[0:2]), - .out(chany_bottom_out[8]) - ); - - - mux_tree_tapbuf_size5 - mux_bottom_track_25 - ( - .in({ chany_top_in[9], chany_top_in[18], chanx_right_in[0], chanx_right_in[7], chanx_right_in[14] }), - .sram(mux_tree_tapbuf_size5_4_sram[0:2]), - .sram_inv(mux_bottom_track_25_undriven_sram_inv[0:2]), - .out(chany_bottom_out[12]) - ); - - - mux_tree_tapbuf_size5_mem - mem_top_track_2 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size5_0_sram[0:2]) - ); - - - mux_tree_tapbuf_size5_mem - mem_top_track_16 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size5_1_sram[0:2]) - ); - - - mux_tree_tapbuf_size5_mem - mem_bottom_track_3 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size6_mem_4_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size5_2_sram[0:2]) - ); - - - mux_tree_tapbuf_size5_mem - mem_bottom_track_17 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size6_mem_6_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size5_3_sram[0:2]) - ); - - - mux_tree_tapbuf_size5_mem - mem_bottom_track_25 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size5_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size5_4_sram[0:2]) - ); - - - mux_tree_tapbuf_size4 - mux_top_track_24 - ( - .in({ chanx_right_in[6], chanx_right_in[13], chany_bottom_in[9], chany_bottom_in[18] }), - .sram(mux_tree_tapbuf_size4_0_sram[0:2]), - .sram_inv(mux_top_track_24_undriven_sram_inv[0:2]), - .out(chany_top_out[12]) - ); - - - mux_tree_tapbuf_size4 - mux_top_track_32 - ( - .in({ chanx_right_in[0], chanx_right_in[7], chanx_right_in[14], chany_bottom_in[10] }), - .sram(mux_tree_tapbuf_size4_1_sram[0:2]), - .sram_inv(mux_top_track_32_undriven_sram_inv[0:2]), - .out(chany_top_out[16]) - ); - - - mux_tree_tapbuf_size4 - mux_right_track_8 - ( - .in({ chany_top_in[7:8], right_bottom_grid_pin_34_[0], chany_bottom_in[8] }), - .sram(mux_tree_tapbuf_size4_2_sram[0:2]), - .sram_inv(mux_right_track_8_undriven_sram_inv[0:2]), - .out(chanx_right_out[4]) - ); - - - mux_tree_tapbuf_size4 - mux_right_track_10 - ( - .in({ chany_top_in[9], chany_top_in[11], right_bottom_grid_pin_35_[0], chany_bottom_in[9] }), - .sram(mux_tree_tapbuf_size4_3_sram[0:2]), - .sram_inv(mux_right_track_10_undriven_sram_inv[0:2]), - .out(chanx_right_out[5]) - ); - - - mux_tree_tapbuf_size4 - mux_right_track_12 - ( - .in({ chany_top_in[10], chany_top_in[15], right_bottom_grid_pin_36_[0], chany_bottom_in[10] }), - .sram(mux_tree_tapbuf_size4_4_sram[0:2]), - .sram_inv(mux_right_track_12_undriven_sram_inv[0:2]), - .out(chanx_right_out[6]) - ); - - - mux_tree_tapbuf_size4 - mux_right_track_14 - ( - .in({ chany_top_in[12], chany_top_in[19], right_bottom_grid_pin_37_[0], chany_bottom_in[12] }), - .sram(mux_tree_tapbuf_size4_5_sram[0:2]), - .sram_inv(mux_right_track_14_undriven_sram_inv[0:2]), - .out(chanx_right_out[7]) - ); - - - mux_tree_tapbuf_size4 - mux_right_track_24 - ( - .in({ chany_top_in[18], right_bottom_grid_pin_34_[0], chany_bottom_in[18:19] }), - .sram(mux_tree_tapbuf_size4_6_sram[0:2]), - .sram_inv(mux_right_track_24_undriven_sram_inv[0:2]), - .out(chanx_right_out[12]) - ); - - - mux_tree_tapbuf_size4_mem - mem_top_track_24 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size4_0_sram[0:2]) - ); - - - mux_tree_tapbuf_size4_mem - mem_top_track_32 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size4_1_sram[0:2]) - ); - - - mux_tree_tapbuf_size4_mem - mem_right_track_8 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size4_2_sram[0:2]) - ); - - - mux_tree_tapbuf_size4_mem - mem_right_track_10 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size4_3_sram[0:2]) - ); - - - mux_tree_tapbuf_size4_mem - mem_right_track_12 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size4_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size4_4_sram[0:2]) - ); - - - mux_tree_tapbuf_size4_mem - mem_right_track_14 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size4_mem_4_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size4_mem_5_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size4_5_sram[0:2]) - ); - - - mux_tree_tapbuf_size4_mem - mem_right_track_24 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size4_mem_6_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size4_6_sram[0:2]) - ); - - - mux_tree_tapbuf_size7 - mux_right_track_2 - ( - .in({ chany_top_in[0], chany_top_in[4], right_bottom_grid_pin_35_[0], right_bottom_grid_pin_37_[0], right_bottom_grid_pin_39_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[4] }), - .sram(mux_tree_tapbuf_size7_0_sram[0:2]), - .sram_inv(mux_right_track_2_undriven_sram_inv[0:2]), - .out(chanx_right_out[1]) - ); - - - mux_tree_tapbuf_size7 - mux_right_track_4 - ( - .in({ chany_top_in[1], chany_top_in[5], right_bottom_grid_pin_34_[0], right_bottom_grid_pin_36_[0], right_bottom_grid_pin_38_[0], right_bottom_grid_pin_40_[0], chany_bottom_in[5] }), - .sram(mux_tree_tapbuf_size7_1_sram[0:2]), - .sram_inv(mux_right_track_4_undriven_sram_inv[0:2]), - .out(chanx_right_out[2]) - ); - - - mux_tree_tapbuf_size7 - mux_right_track_6 - ( - .in({ chany_top_in[3], chany_top_in[6], right_bottom_grid_pin_35_[0], right_bottom_grid_pin_37_[0], right_bottom_grid_pin_39_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[6] }), - .sram(mux_tree_tapbuf_size7_2_sram[0:2]), - .sram_inv(mux_right_track_6_undriven_sram_inv[0:2]), - .out(chanx_right_out[3]) - ); - - - mux_tree_tapbuf_size7_mem - mem_right_track_2 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_0_sram[0:2]) - ); - - - mux_tree_tapbuf_size7_mem - mem_right_track_4 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_1_sram[0:2]) - ); - - - mux_tree_tapbuf_size7_mem - mem_right_track_6 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_2_sram[0:2]) - ); - - - mux_tree_tapbuf_size3 - mux_right_track_16 - ( - .in({ chany_top_in[13], right_bottom_grid_pin_38_[0], chany_bottom_in[13] }), - .sram(mux_tree_tapbuf_size3_0_sram[0:1]), - .sram_inv(mux_right_track_16_undriven_sram_inv[0:1]), - .out(chanx_right_out[8]) - ); - - - mux_tree_tapbuf_size3 - mux_right_track_18 - ( - .in({ chany_top_in[14], right_bottom_grid_pin_39_[0], chany_bottom_in[14] }), - .sram(mux_tree_tapbuf_size3_1_sram[0:1]), - .sram_inv(mux_right_track_18_undriven_sram_inv[0:1]), - .out(chanx_right_out[9]) - ); - - - mux_tree_tapbuf_size3 - mux_right_track_20 - ( - .in({ chany_top_in[16], right_bottom_grid_pin_40_[0], chany_bottom_in[16] }), - .sram(mux_tree_tapbuf_size3_2_sram[0:1]), - .sram_inv(mux_right_track_20_undriven_sram_inv[0:1]), - .out(chanx_right_out[10]) - ); - - - mux_tree_tapbuf_size3 - mux_right_track_22 - ( - .in({ chany_top_in[17], right_bottom_grid_pin_41_[0], chany_bottom_in[17] }), - .sram(mux_tree_tapbuf_size3_3_sram[0:1]), - .sram_inv(mux_right_track_22_undriven_sram_inv[0:1]), - .out(chanx_right_out[11]) - ); - - - mux_tree_tapbuf_size3 - mux_bottom_track_33 - ( - .in({ chany_top_in[10], chanx_right_in[6], chanx_right_in[13] }), - .sram(mux_tree_tapbuf_size3_4_sram[0:1]), - .sram_inv(mux_bottom_track_33_undriven_sram_inv[0:1]), - .out(chany_bottom_out[16]) - ); - - - mux_tree_tapbuf_size3_mem - mem_right_track_16 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size4_mem_5_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_0_sram[0:1]) - ); - - - mux_tree_tapbuf_size3_mem - mem_right_track_18 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_1_sram[0:1]) - ); - - - mux_tree_tapbuf_size3_mem - mem_right_track_20 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_2_sram[0:1]) - ); - - - mux_tree_tapbuf_size3_mem - mem_right_track_22 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_3_sram[0:1]) - ); - - - mux_tree_tapbuf_size3_mem - mem_bottom_track_33 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size5_mem_4_ccff_tail[0]), - .ccff_tail(ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_4_sram[0:1]) - ); - - - mux_tree_tapbuf_size2 - mux_right_track_26 - ( - .in({ right_bottom_grid_pin_35_[0], chany_bottom_in[15] }), - .sram(mux_tree_tapbuf_size2_0_sram[0:1]), - .sram_inv(mux_right_track_26_undriven_sram_inv[0:1]), - .out(chanx_right_out[13]) - ); - - - mux_tree_tapbuf_size2 - mux_right_track_28 - ( - .in({ right_bottom_grid_pin_36_[0], chany_bottom_in[11] }), - .sram(mux_tree_tapbuf_size2_1_sram[0:1]), - .sram_inv(mux_right_track_28_undriven_sram_inv[0:1]), - .out(chanx_right_out[14]) - ); - - - mux_tree_tapbuf_size2 - mux_right_track_30 - ( - .in({ right_bottom_grid_pin_37_[0], chany_bottom_in[7] }), - .sram(mux_tree_tapbuf_size2_2_sram[0:1]), - .sram_inv(mux_right_track_30_undriven_sram_inv[0:1]), - .out(chanx_right_out[15]) - ); - - - mux_tree_tapbuf_size2 - mux_right_track_32 - ( - .in({ right_bottom_grid_pin_38_[0], chany_bottom_in[3] }), - .sram(mux_tree_tapbuf_size2_3_sram[0:1]), - .sram_inv(mux_right_track_32_undriven_sram_inv[0:1]), - .out(chanx_right_out[16]) - ); - - - mux_tree_tapbuf_size2 - mux_right_track_34 - ( - .in({ right_bottom_grid_pin_39_[0], chany_bottom_in[1] }), - .sram(mux_tree_tapbuf_size2_4_sram[0:1]), - .sram_inv(mux_right_track_34_undriven_sram_inv[0:1]), - .out(chanx_right_out[17]) - ); - - - mux_tree_tapbuf_size2 - mux_right_track_36 - ( - .in({ right_bottom_grid_pin_40_[0], chany_bottom_in[0] }), - .sram(mux_tree_tapbuf_size2_5_sram[0:1]), - .sram_inv(mux_right_track_36_undriven_sram_inv[0:1]), - .out(chanx_right_out[18]) - ); - - - mux_tree_tapbuf_size2_mem - mem_right_track_26 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size4_mem_6_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_0_sram[0:1]) - ); - - - mux_tree_tapbuf_size2_mem - mem_right_track_28 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_1_sram[0:1]) - ); - - - mux_tree_tapbuf_size2_mem - mem_right_track_30 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_2_sram[0:1]) - ); - - - mux_tree_tapbuf_size2_mem - mem_right_track_32 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_3_sram[0:1]) - ); - - - mux_tree_tapbuf_size2_mem - mem_right_track_34 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_4_sram[0:1]) - ); - - - mux_tree_tapbuf_size2_mem - mem_right_track_36 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_5_sram[0:1]) - ); - - -endmodule - diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_0__2_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_0__2_.v deleted file mode 100644 index d1eab74..0000000 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_0__2_.v +++ /dev/null @@ -1,598 +0,0 @@ - - -module sb_0__2_ -( prog_clk, chanx_right_in, right_top_grid_pin_1_, right_bottom_grid_pin_34_, right_bottom_grid_pin_35_, right_bottom_grid_pin_36_, right_bottom_grid_pin_37_, right_bottom_grid_pin_38_, right_bottom_grid_pin_39_, right_bottom_grid_pin_40_, right_bottom_grid_pin_41_, chany_bottom_in, bottom_left_grid_pin_1_, ccff_head, chanx_right_out, chany_bottom_out, ccff_tail, SC_IN_TOP, SC_IN_BOT, SC_OUT_TOP, SC_OUT_BOT ); - input [0:0] prog_clk; - input [0:19] chanx_right_in; - input [0:0] right_top_grid_pin_1_; - input [0:0] right_bottom_grid_pin_34_; - input [0:0] right_bottom_grid_pin_35_; - input [0:0] right_bottom_grid_pin_36_; - input [0:0] right_bottom_grid_pin_37_; - input [0:0] right_bottom_grid_pin_38_; - input [0:0] right_bottom_grid_pin_39_; - input [0:0] right_bottom_grid_pin_40_; - input [0:0] right_bottom_grid_pin_41_; - input [0:19] chany_bottom_in; - input [0:0] bottom_left_grid_pin_1_; - input [0:0] ccff_head; - output [0:19] chanx_right_out; - output [0:19] chany_bottom_out; - output [0:0] ccff_tail; - input SC_IN_TOP; - input SC_IN_BOT; - output SC_OUT_TOP; - output SC_OUT_BOT; - - wire [0:1] mux_bottom_track_1_undriven_sram_inv; - wire [0:1] mux_bottom_track_25_undriven_sram_inv; - wire [0:1] mux_bottom_track_5_undriven_sram_inv; - wire [0:1] mux_bottom_track_9_undriven_sram_inv; - wire [0:2] mux_right_track_0_undriven_sram_inv; - wire [0:1] mux_right_track_10_undriven_sram_inv; - wire [0:1] mux_right_track_12_undriven_sram_inv; - wire [0:1] mux_right_track_14_undriven_sram_inv; - wire [0:1] mux_right_track_16_undriven_sram_inv; - wire [0:1] mux_right_track_18_undriven_sram_inv; - wire [0:1] mux_right_track_20_undriven_sram_inv; - wire [0:1] mux_right_track_22_undriven_sram_inv; - wire [0:1] mux_right_track_24_undriven_sram_inv; - wire [0:1] mux_right_track_26_undriven_sram_inv; - wire [0:1] mux_right_track_28_undriven_sram_inv; - wire [0:2] mux_right_track_2_undriven_sram_inv; - wire [0:1] mux_right_track_30_undriven_sram_inv; - wire [0:1] mux_right_track_32_undriven_sram_inv; - wire [0:1] mux_right_track_34_undriven_sram_inv; - wire [0:1] mux_right_track_36_undriven_sram_inv; - wire [0:1] mux_right_track_38_undriven_sram_inv; - wire [0:2] mux_right_track_4_undriven_sram_inv; - wire [0:2] mux_right_track_6_undriven_sram_inv; - wire [0:1] mux_right_track_8_undriven_sram_inv; - wire [0:1] mux_tree_tapbuf_size2_0_sram; - wire [0:1] mux_tree_tapbuf_size2_10_sram; - wire [0:1] mux_tree_tapbuf_size2_11_sram; - wire [0:1] mux_tree_tapbuf_size2_12_sram; - wire [0:1] mux_tree_tapbuf_size2_13_sram; - wire [0:1] mux_tree_tapbuf_size2_14_sram; - wire [0:1] mux_tree_tapbuf_size2_15_sram; - wire [0:1] mux_tree_tapbuf_size2_16_sram; - wire [0:1] mux_tree_tapbuf_size2_17_sram; - wire [0:1] mux_tree_tapbuf_size2_1_sram; - wire [0:1] mux_tree_tapbuf_size2_2_sram; - wire [0:1] mux_tree_tapbuf_size2_3_sram; - wire [0:1] mux_tree_tapbuf_size2_4_sram; - wire [0:1] mux_tree_tapbuf_size2_5_sram; - wire [0:1] mux_tree_tapbuf_size2_6_sram; - wire [0:1] mux_tree_tapbuf_size2_7_sram; - wire [0:1] mux_tree_tapbuf_size2_8_sram; - wire [0:1] mux_tree_tapbuf_size2_9_sram; - wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail; - wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail; - wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail; - wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail; - wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail; - wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail; - wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail; - wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail; - wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail; - wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail; - wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail; - wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail; - wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail; - wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail; - wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail; - wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail; - wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail; - wire [0:1] mux_tree_tapbuf_size3_0_sram; - wire [0:1] mux_tree_tapbuf_size3_1_sram; - wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail; - wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail; - wire [0:2] mux_tree_tapbuf_size5_0_sram; - wire [0:2] mux_tree_tapbuf_size5_1_sram; - wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail; - wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail; - wire [0:2] mux_tree_tapbuf_size6_0_sram; - wire [0:2] mux_tree_tapbuf_size6_1_sram; - wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail; - wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail; - assign chany_bottom_out[18] = chanx_right_in[0]; - assign chany_bottom_out[17] = chanx_right_in[1]; - assign chany_bottom_out[16] = chanx_right_in[2]; - assign chany_bottom_out[15] = chanx_right_in[3]; - assign chany_bottom_out[14] = chanx_right_in[4]; - assign chany_bottom_out[13] = chanx_right_in[5]; - assign chany_bottom_out[11] = chanx_right_in[7]; - assign chany_bottom_out[10] = chanx_right_in[8]; - assign chany_bottom_out[9] = chanx_right_in[9]; - assign chany_bottom_out[8] = chanx_right_in[10]; - assign chany_bottom_out[7] = chanx_right_in[11]; - assign chany_bottom_out[6] = chanx_right_in[12]; - assign chany_bottom_out[5] = chanx_right_in[13]; - assign chany_bottom_out[3] = chanx_right_in[15]; - assign chany_bottom_out[1] = chanx_right_in[17]; - assign chany_bottom_out[19] = chanx_right_in[19]; - assign SC_IN_TOP = SC_IN_BOT; - assign SC_OUT_TOP = SC_OUT_BOT; - - mux_tree_tapbuf_size6 - mux_right_track_0 - ( - .in({ right_top_grid_pin_1_[0], right_bottom_grid_pin_35_[0], right_bottom_grid_pin_37_[0], right_bottom_grid_pin_39_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[18] }), - .sram(mux_tree_tapbuf_size6_0_sram[0:2]), - .sram_inv(mux_right_track_0_undriven_sram_inv[0:2]), - .out(chanx_right_out[0]) - ); - - - mux_tree_tapbuf_size6 - mux_right_track_4 - ( - .in({ right_top_grid_pin_1_[0], right_bottom_grid_pin_35_[0], right_bottom_grid_pin_37_[0], right_bottom_grid_pin_39_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[16] }), - .sram(mux_tree_tapbuf_size6_1_sram[0:2]), - .sram_inv(mux_right_track_4_undriven_sram_inv[0:2]), - .out(chanx_right_out[2]) - ); - - - mux_tree_tapbuf_size6_mem - mem_right_track_0 - ( - .prog_clk(prog_clk[0]), - .ccff_head(ccff_head[0]), - .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_0_sram[0:2]) - ); - - - mux_tree_tapbuf_size6_mem - mem_right_track_4 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_1_sram[0:2]) - ); - - - mux_tree_tapbuf_size5 - mux_right_track_2 - ( - .in({ right_bottom_grid_pin_34_[0], right_bottom_grid_pin_36_[0], right_bottom_grid_pin_38_[0], right_bottom_grid_pin_40_[0], chany_bottom_in[17] }), - .sram(mux_tree_tapbuf_size5_0_sram[0:2]), - .sram_inv(mux_right_track_2_undriven_sram_inv[0:2]), - .out(chanx_right_out[1]) - ); - - - mux_tree_tapbuf_size5 - mux_right_track_6 - ( - .in({ right_bottom_grid_pin_34_[0], right_bottom_grid_pin_36_[0], right_bottom_grid_pin_38_[0], right_bottom_grid_pin_40_[0], chany_bottom_in[15] }), - .sram(mux_tree_tapbuf_size5_1_sram[0:2]), - .sram_inv(mux_right_track_6_undriven_sram_inv[0:2]), - .out(chanx_right_out[3]) - ); - - - mux_tree_tapbuf_size5_mem - mem_right_track_2 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size5_0_sram[0:2]) - ); - - - mux_tree_tapbuf_size5_mem - mem_right_track_6 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size5_1_sram[0:2]) - ); - - - mux_tree_tapbuf_size3 - mux_right_track_8 - ( - .in({ right_top_grid_pin_1_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[14] }), - .sram(mux_tree_tapbuf_size3_0_sram[0:1]), - .sram_inv(mux_right_track_8_undriven_sram_inv[0:1]), - .out(chanx_right_out[4]) - ); - - - mux_tree_tapbuf_size3 - mux_right_track_24 - ( - .in({ right_top_grid_pin_1_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[6] }), - .sram(mux_tree_tapbuf_size3_1_sram[0:1]), - .sram_inv(mux_right_track_24_undriven_sram_inv[0:1]), - .out(chanx_right_out[12]) - ); - - - mux_tree_tapbuf_size3_mem - mem_right_track_8 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_0_sram[0:1]) - ); - - - mux_tree_tapbuf_size3_mem - mem_right_track_24 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_1_sram[0:1]) - ); - - - mux_tree_tapbuf_size2 - mux_right_track_10 - ( - .in({ right_bottom_grid_pin_34_[0], chany_bottom_in[13] }), - .sram(mux_tree_tapbuf_size2_0_sram[0:1]), - .sram_inv(mux_right_track_10_undriven_sram_inv[0:1]), - .out(chanx_right_out[5]) - ); - - - mux_tree_tapbuf_size2 - mux_right_track_12 - ( - .in({ right_bottom_grid_pin_35_[0], chany_bottom_in[12] }), - .sram(mux_tree_tapbuf_size2_1_sram[0:1]), - .sram_inv(mux_right_track_12_undriven_sram_inv[0:1]), - .out(chanx_right_out[6]) - ); - - - mux_tree_tapbuf_size2 - mux_right_track_14 - ( - .in({ right_bottom_grid_pin_36_[0], chany_bottom_in[11] }), - .sram(mux_tree_tapbuf_size2_2_sram[0:1]), - .sram_inv(mux_right_track_14_undriven_sram_inv[0:1]), - .out(chanx_right_out[7]) - ); - - - mux_tree_tapbuf_size2 - mux_right_track_16 - ( - .in({ right_bottom_grid_pin_37_[0], chany_bottom_in[10] }), - .sram(mux_tree_tapbuf_size2_3_sram[0:1]), - .sram_inv(mux_right_track_16_undriven_sram_inv[0:1]), - .out(chanx_right_out[8]) - ); - - - mux_tree_tapbuf_size2 - mux_right_track_18 - ( - .in({ right_bottom_grid_pin_38_[0], chany_bottom_in[9] }), - .sram(mux_tree_tapbuf_size2_4_sram[0:1]), - .sram_inv(mux_right_track_18_undriven_sram_inv[0:1]), - .out(chanx_right_out[9]) - ); - - - mux_tree_tapbuf_size2 - mux_right_track_20 - ( - .in({ right_bottom_grid_pin_39_[0], chany_bottom_in[8] }), - .sram(mux_tree_tapbuf_size2_5_sram[0:1]), - .sram_inv(mux_right_track_20_undriven_sram_inv[0:1]), - .out(chanx_right_out[10]) - ); - - - mux_tree_tapbuf_size2 - mux_right_track_22 - ( - .in({ right_bottom_grid_pin_40_[0], chany_bottom_in[7] }), - .sram(mux_tree_tapbuf_size2_6_sram[0:1]), - .sram_inv(mux_right_track_22_undriven_sram_inv[0:1]), - .out(chanx_right_out[11]) - ); - - - mux_tree_tapbuf_size2 - mux_right_track_26 - ( - .in({ right_bottom_grid_pin_34_[0], chany_bottom_in[5] }), - .sram(mux_tree_tapbuf_size2_7_sram[0:1]), - .sram_inv(mux_right_track_26_undriven_sram_inv[0:1]), - .out(chanx_right_out[13]) - ); - - - mux_tree_tapbuf_size2 - mux_right_track_28 - ( - .in({ right_bottom_grid_pin_35_[0], chany_bottom_in[4] }), - .sram(mux_tree_tapbuf_size2_8_sram[0:1]), - .sram_inv(mux_right_track_28_undriven_sram_inv[0:1]), - .out(chanx_right_out[14]) - ); - - - mux_tree_tapbuf_size2 - mux_right_track_30 - ( - .in({ right_bottom_grid_pin_36_[0], chany_bottom_in[3] }), - .sram(mux_tree_tapbuf_size2_9_sram[0:1]), - .sram_inv(mux_right_track_30_undriven_sram_inv[0:1]), - .out(chanx_right_out[15]) - ); - - - mux_tree_tapbuf_size2 - mux_right_track_32 - ( - .in({ right_bottom_grid_pin_37_[0], chany_bottom_in[2] }), - .sram(mux_tree_tapbuf_size2_10_sram[0:1]), - .sram_inv(mux_right_track_32_undriven_sram_inv[0:1]), - .out(chanx_right_out[16]) - ); - - - mux_tree_tapbuf_size2 - mux_right_track_34 - ( - .in({ right_bottom_grid_pin_38_[0], chany_bottom_in[1] }), - .sram(mux_tree_tapbuf_size2_11_sram[0:1]), - .sram_inv(mux_right_track_34_undriven_sram_inv[0:1]), - .out(chanx_right_out[17]) - ); - - - mux_tree_tapbuf_size2 - mux_right_track_36 - ( - .in({ right_bottom_grid_pin_39_[0], chany_bottom_in[0] }), - .sram(mux_tree_tapbuf_size2_12_sram[0:1]), - .sram_inv(mux_right_track_36_undriven_sram_inv[0:1]), - .out(chanx_right_out[18]) - ); - - - mux_tree_tapbuf_size2 - mux_right_track_38 - ( - .in({ right_bottom_grid_pin_40_[0], chany_bottom_in[19] }), - .sram(mux_tree_tapbuf_size2_13_sram[0:1]), - .sram_inv(mux_right_track_38_undriven_sram_inv[0:1]), - .out(chanx_right_out[19]) - ); - - - mux_tree_tapbuf_size2 - mux_bottom_track_1 - ( - .in({ chanx_right_in[18], bottom_left_grid_pin_1_[0] }), - .sram(mux_tree_tapbuf_size2_14_sram[0:1]), - .sram_inv(mux_bottom_track_1_undriven_sram_inv[0:1]), - .out(chany_bottom_out[0]) - ); - - - mux_tree_tapbuf_size2 - mux_bottom_track_5 - ( - .in({ chanx_right_in[16], bottom_left_grid_pin_1_[0] }), - .sram(mux_tree_tapbuf_size2_15_sram[0:1]), - .sram_inv(mux_bottom_track_5_undriven_sram_inv[0:1]), - .out(chany_bottom_out[2]) - ); - - - mux_tree_tapbuf_size2 - mux_bottom_track_9 - ( - .in({ chanx_right_in[14], bottom_left_grid_pin_1_[0] }), - .sram(mux_tree_tapbuf_size2_16_sram[0:1]), - .sram_inv(mux_bottom_track_9_undriven_sram_inv[0:1]), - .out(chany_bottom_out[4]) - ); - - - mux_tree_tapbuf_size2 - mux_bottom_track_25 - ( - .in({ chanx_right_in[6], bottom_left_grid_pin_1_[0] }), - .sram(mux_tree_tapbuf_size2_17_sram[0:1]), - .sram_inv(mux_bottom_track_25_undriven_sram_inv[0:1]), - .out(chany_bottom_out[12]) - ); - - - mux_tree_tapbuf_size2_mem - mem_right_track_10 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_0_sram[0:1]) - ); - - - mux_tree_tapbuf_size2_mem - mem_right_track_12 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_1_sram[0:1]) - ); - - - mux_tree_tapbuf_size2_mem - mem_right_track_14 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_2_sram[0:1]) - ); - - - mux_tree_tapbuf_size2_mem - mem_right_track_16 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_3_sram[0:1]) - ); - - - mux_tree_tapbuf_size2_mem - mem_right_track_18 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_4_sram[0:1]) - ); - - - mux_tree_tapbuf_size2_mem - mem_right_track_20 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_5_sram[0:1]) - ); - - - mux_tree_tapbuf_size2_mem - mem_right_track_22 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_6_sram[0:1]) - ); - - - mux_tree_tapbuf_size2_mem - mem_right_track_26 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_7_sram[0:1]) - ); - - - mux_tree_tapbuf_size2_mem - mem_right_track_28 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_8_sram[0:1]) - ); - - - mux_tree_tapbuf_size2_mem - mem_right_track_30 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_9_sram[0:1]) - ); - - - mux_tree_tapbuf_size2_mem - mem_right_track_32 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_10_sram[0:1]) - ); - - - mux_tree_tapbuf_size2_mem - mem_right_track_34 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_11_sram[0:1]) - ); - - - mux_tree_tapbuf_size2_mem - mem_right_track_36 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_12_sram[0:1]) - ); - - - mux_tree_tapbuf_size2_mem - mem_right_track_38 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_13_sram[0:1]) - ); - - - mux_tree_tapbuf_size2_mem - mem_bottom_track_1 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_14_sram[0:1]) - ); - - - mux_tree_tapbuf_size2_mem - mem_bottom_track_5 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_15_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_15_sram[0:1]) - ); - - - mux_tree_tapbuf_size2_mem - mem_bottom_track_9 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_15_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_16_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_16_sram[0:1]) - ); - - - mux_tree_tapbuf_size2_mem - mem_bottom_track_25 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_16_ccff_tail[0]), - .ccff_tail(ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_17_sram[0:1]) - ); - - -endmodule - diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_1__0_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_1__0_.v deleted file mode 100644 index bf4569e..0000000 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_1__0_.v +++ /dev/null @@ -1,718 +0,0 @@ - - -module sb_1__0_ -( prog_clk, chany_top_in, top_left_grid_pin_42_, top_left_grid_pin_43_, top_left_grid_pin_44_, top_left_grid_pin_45_, top_left_grid_pin_46_, top_left_grid_pin_47_, top_left_grid_pin_48_, top_left_grid_pin_49_, chanx_right_in, right_bottom_grid_pin_1_, right_bottom_grid_pin_3_, right_bottom_grid_pin_5_, right_bottom_grid_pin_7_, right_bottom_grid_pin_9_, right_bottom_grid_pin_11_, chanx_left_in, left_bottom_grid_pin_1_, left_bottom_grid_pin_3_, left_bottom_grid_pin_5_, left_bottom_grid_pin_7_, left_bottom_grid_pin_9_, left_bottom_grid_pin_11_, ccff_head, chany_top_out, chanx_right_out, chanx_left_out, ccff_tail, SC_IN_TOP, SC_IN_BOT, SC_OUT_TOP, SC_OUT_BOT ); - input [0:0] prog_clk; - input [0:19] chany_top_in; - input [0:0] top_left_grid_pin_42_; - input [0:0] top_left_grid_pin_43_; - input [0:0] top_left_grid_pin_44_; - input [0:0] top_left_grid_pin_45_; - input [0:0] top_left_grid_pin_46_; - input [0:0] top_left_grid_pin_47_; - input [0:0] top_left_grid_pin_48_; - input [0:0] top_left_grid_pin_49_; - input [0:19] chanx_right_in; - input [0:0] right_bottom_grid_pin_1_; - input [0:0] right_bottom_grid_pin_3_; - input [0:0] right_bottom_grid_pin_5_; - input [0:0] right_bottom_grid_pin_7_; - input [0:0] right_bottom_grid_pin_9_; - input [0:0] right_bottom_grid_pin_11_; - input [0:19] chanx_left_in; - input [0:0] left_bottom_grid_pin_1_; - input [0:0] left_bottom_grid_pin_3_; - input [0:0] left_bottom_grid_pin_5_; - input [0:0] left_bottom_grid_pin_7_; - input [0:0] left_bottom_grid_pin_9_; - input [0:0] left_bottom_grid_pin_11_; - input [0:0] ccff_head; - output [0:19] chany_top_out; - output [0:19] chanx_right_out; - output [0:19] chanx_left_out; - output [0:0] ccff_tail; - input SC_IN_TOP; - input SC_IN_BOT; - output SC_OUT_TOP; - output SC_OUT_BOT; - - wire [0:2] mux_left_track_17_undriven_sram_inv; - wire [0:3] mux_left_track_1_undriven_sram_inv; - wire [0:2] mux_left_track_25_undriven_sram_inv; - wire [0:2] mux_left_track_33_undriven_sram_inv; - wire [0:2] mux_left_track_3_undriven_sram_inv; - wire [0:3] mux_left_track_5_undriven_sram_inv; - wire [0:2] mux_left_track_9_undriven_sram_inv; - wire [0:2] mux_right_track_0_undriven_sram_inv; - wire [0:2] mux_right_track_16_undriven_sram_inv; - wire [0:2] mux_right_track_24_undriven_sram_inv; - wire [0:3] mux_right_track_2_undriven_sram_inv; - wire [0:2] mux_right_track_32_undriven_sram_inv; - wire [0:3] mux_right_track_4_undriven_sram_inv; - wire [0:2] mux_right_track_8_undriven_sram_inv; - wire [0:3] mux_top_track_0_undriven_sram_inv; - wire [0:2] mux_top_track_10_undriven_sram_inv; - wire [0:1] mux_top_track_12_undriven_sram_inv; - wire [0:1] mux_top_track_14_undriven_sram_inv; - wire [0:1] mux_top_track_16_undriven_sram_inv; - wire [0:1] mux_top_track_18_undriven_sram_inv; - wire [0:1] mux_top_track_20_undriven_sram_inv; - wire [0:1] mux_top_track_22_undriven_sram_inv; - wire [0:1] mux_top_track_24_undriven_sram_inv; - wire [0:2] mux_top_track_2_undriven_sram_inv; - wire [0:1] mux_top_track_38_undriven_sram_inv; - wire [0:2] mux_top_track_4_undriven_sram_inv; - wire [0:2] mux_top_track_6_undriven_sram_inv; - wire [0:2] mux_top_track_8_undriven_sram_inv; - wire [0:3] mux_tree_tapbuf_size11_0_sram; - wire [0:3] mux_tree_tapbuf_size11_1_sram; - wire [0:0] mux_tree_tapbuf_size11_mem_0_ccff_tail; - wire [0:0] mux_tree_tapbuf_size11_mem_1_ccff_tail; - wire [0:1] mux_tree_tapbuf_size2_0_sram; - wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail; - wire [0:1] mux_tree_tapbuf_size3_0_sram; - wire [0:1] mux_tree_tapbuf_size3_1_sram; - wire [0:1] mux_tree_tapbuf_size3_2_sram; - wire [0:1] mux_tree_tapbuf_size3_3_sram; - wire [0:1] mux_tree_tapbuf_size3_4_sram; - wire [0:1] mux_tree_tapbuf_size3_5_sram; - wire [0:1] mux_tree_tapbuf_size3_6_sram; - wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail; - wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail; - wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail; - wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail; - wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail; - wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail; - wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail; - wire [0:2] mux_tree_tapbuf_size4_0_sram; - wire [0:2] mux_tree_tapbuf_size4_1_sram; - wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail; - wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail; - wire [0:2] mux_tree_tapbuf_size5_0_sram; - wire [0:2] mux_tree_tapbuf_size5_1_sram; - wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail; - wire [0:2] mux_tree_tapbuf_size6_0_sram; - wire [0:2] mux_tree_tapbuf_size6_1_sram; - wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail; - wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail; - wire [0:2] mux_tree_tapbuf_size7_0_sram; - wire [0:2] mux_tree_tapbuf_size7_1_sram; - wire [0:2] mux_tree_tapbuf_size7_2_sram; - wire [0:2] mux_tree_tapbuf_size7_3_sram; - wire [0:2] mux_tree_tapbuf_size7_4_sram; - wire [0:2] mux_tree_tapbuf_size7_5_sram; - wire [0:2] mux_tree_tapbuf_size7_6_sram; - wire [0:2] mux_tree_tapbuf_size7_7_sram; - wire [0:2] mux_tree_tapbuf_size7_8_sram; - wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail; - wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail; - wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail; - wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail; - wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail; - wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail; - wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail; - wire [0:0] mux_tree_tapbuf_size7_mem_7_ccff_tail; - wire [0:0] mux_tree_tapbuf_size7_mem_8_ccff_tail; - wire [0:3] mux_tree_tapbuf_size8_0_sram; - wire [0:3] mux_tree_tapbuf_size8_1_sram; - wire [0:3] mux_tree_tapbuf_size8_2_sram; - wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail; - wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail; - wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail; - assign chany_top_out[13] = top_left_grid_pin_43_[0]; - assign chanx_left_out[3] = chanx_right_in[2]; - assign chanx_left_out[5] = chanx_right_in[4]; - assign chanx_left_out[6] = chanx_right_in[5]; - assign chanx_left_out[7] = chanx_right_in[6]; - assign chanx_left_out[9] = chanx_right_in[8]; - assign chanx_left_out[10] = chanx_right_in[9]; - assign chanx_left_out[11] = chanx_right_in[10]; - assign chanx_left_out[13] = chanx_right_in[12]; - assign chanx_left_out[14] = chanx_right_in[13]; - assign chanx_left_out[15] = chanx_right_in[14]; - assign chanx_left_out[17] = chanx_right_in[16]; - assign chanx_left_out[18] = chanx_right_in[17]; - assign chanx_left_out[19] = chanx_right_in[18]; - assign chanx_right_out[3] = chanx_left_in[2]; - assign chany_top_out[18] = chanx_left_in[3]; - assign chanx_right_out[5] = chanx_left_in[4]; - assign chanx_right_out[6] = chanx_left_in[5]; - assign chanx_right_out[7] = chanx_left_in[6]; - assign chany_top_out[17] = chanx_left_in[7]; - assign chanx_right_out[9] = chanx_left_in[8]; - assign chanx_right_out[10] = chanx_left_in[9]; - assign chanx_right_out[11] = chanx_left_in[10]; - assign chany_top_out[16] = chanx_left_in[11]; - assign chanx_right_out[13] = chanx_left_in[12]; - assign chanx_right_out[14] = chanx_left_in[13]; - assign chanx_right_out[15] = chanx_left_in[14]; - assign chany_top_out[15] = chanx_left_in[15]; - assign chanx_right_out[17] = chanx_left_in[16]; - assign chanx_right_out[18] = chanx_left_in[17]; - assign chanx_right_out[19] = chanx_left_in[18]; - assign chany_top_out[14] = chanx_left_in[19]; - assign SC_IN_TOP = SC_IN_BOT; - assign SC_OUT_TOP = SC_OUT_BOT; - - mux_tree_tapbuf_size8 - mux_top_track_0 - ( - .in({ top_left_grid_pin_42_[0], top_left_grid_pin_44_[0], top_left_grid_pin_46_[0], top_left_grid_pin_48_[0], chanx_right_in[1:2], chanx_left_in[0], chanx_left_in[2] }), - .sram(mux_tree_tapbuf_size8_0_sram[0:3]), - .sram_inv(mux_top_track_0_undriven_sram_inv[0:3]), - .out(chany_top_out[0]) - ); - - - mux_tree_tapbuf_size8 - mux_right_track_2 - ( - .in({ chany_top_in[0], chany_top_in[7], chany_top_in[14], right_bottom_grid_pin_3_[0], right_bottom_grid_pin_7_[0], right_bottom_grid_pin_11_[0], chanx_left_in[4], chanx_left_in[13] }), - .sram(mux_tree_tapbuf_size8_1_sram[0:3]), - .sram_inv(mux_right_track_2_undriven_sram_inv[0:3]), - .out(chanx_right_out[1]) - ); - - - mux_tree_tapbuf_size8 - mux_left_track_1 - ( - .in({ chany_top_in[0], chany_top_in[7], chany_top_in[14], chanx_right_in[2], chanx_right_in[12], left_bottom_grid_pin_1_[0], left_bottom_grid_pin_5_[0], left_bottom_grid_pin_9_[0] }), - .sram(mux_tree_tapbuf_size8_2_sram[0:3]), - .sram_inv(mux_left_track_1_undriven_sram_inv[0:3]), - .out(chanx_left_out[0]) - ); - - - mux_tree_tapbuf_size8_mem - mem_top_track_0 - ( - .prog_clk(prog_clk[0]), - .ccff_head(ccff_head[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_0_sram[0:3]) - ); - - - mux_tree_tapbuf_size8_mem - mem_right_track_2 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size7_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_1_sram[0:3]) - ); - - - mux_tree_tapbuf_size8_mem - mem_left_track_1 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_2_sram[0:3]) - ); - - - mux_tree_tapbuf_size7 - mux_top_track_2 - ( - .in({ top_left_grid_pin_43_[0], top_left_grid_pin_45_[0], top_left_grid_pin_47_[0], top_left_grid_pin_49_[0], chanx_right_in[3:4], chanx_left_in[4] }), - .sram(mux_tree_tapbuf_size7_0_sram[0:2]), - .sram_inv(mux_top_track_2_undriven_sram_inv[0:2]), - .out(chany_top_out[1]) - ); - - - mux_tree_tapbuf_size7 - mux_top_track_4 - ( - .in({ top_left_grid_pin_42_[0], top_left_grid_pin_44_[0], top_left_grid_pin_46_[0], top_left_grid_pin_48_[0], chanx_right_in[5], chanx_right_in[7], chanx_left_in[5] }), - .sram(mux_tree_tapbuf_size7_1_sram[0:2]), - .sram_inv(mux_top_track_4_undriven_sram_inv[0:2]), - .out(chany_top_out[2]) - ); - - - mux_tree_tapbuf_size7 - mux_top_track_6 - ( - .in({ top_left_grid_pin_43_[0], top_left_grid_pin_45_[0], top_left_grid_pin_47_[0], top_left_grid_pin_49_[0], chanx_right_in[6], chanx_right_in[11], chanx_left_in[6] }), - .sram(mux_tree_tapbuf_size7_2_sram[0:2]), - .sram_inv(mux_top_track_6_undriven_sram_inv[0:2]), - .out(chany_top_out[3]) - ); - - - mux_tree_tapbuf_size7 - mux_right_track_0 - ( - .in({ chany_top_in[6], chany_top_in[13], right_bottom_grid_pin_1_[0], right_bottom_grid_pin_5_[0], right_bottom_grid_pin_9_[0], chanx_left_in[2], chanx_left_in[12] }), - .sram(mux_tree_tapbuf_size7_3_sram[0:2]), - .sram_inv(mux_right_track_0_undriven_sram_inv[0:2]), - .out(chanx_right_out[0]) - ); - - - mux_tree_tapbuf_size7 - mux_right_track_8 - ( - .in({ chany_top_in[2], chany_top_in[9], chany_top_in[16], right_bottom_grid_pin_1_[0], right_bottom_grid_pin_9_[0], chanx_left_in[6], chanx_left_in[16] }), - .sram(mux_tree_tapbuf_size7_4_sram[0:2]), - .sram_inv(mux_right_track_8_undriven_sram_inv[0:2]), - .out(chanx_right_out[4]) - ); - - - mux_tree_tapbuf_size7 - mux_right_track_16 - ( - .in({ chany_top_in[3], chany_top_in[10], chany_top_in[17], right_bottom_grid_pin_3_[0], right_bottom_grid_pin_11_[0], chanx_left_in[8], chanx_left_in[17] }), - .sram(mux_tree_tapbuf_size7_5_sram[0:2]), - .sram_inv(mux_right_track_16_undriven_sram_inv[0:2]), - .out(chanx_right_out[8]) - ); - - - mux_tree_tapbuf_size7 - mux_left_track_3 - ( - .in({ chany_top_in[6], chany_top_in[13], chanx_right_in[4], chanx_right_in[13], left_bottom_grid_pin_3_[0], left_bottom_grid_pin_7_[0], left_bottom_grid_pin_11_[0] }), - .sram(mux_tree_tapbuf_size7_6_sram[0:2]), - .sram_inv(mux_left_track_3_undriven_sram_inv[0:2]), - .out(chanx_left_out[1]) - ); - - - mux_tree_tapbuf_size7 - mux_left_track_9 - ( - .in({ chany_top_in[4], chany_top_in[11], chany_top_in[18], chanx_right_in[6], chanx_right_in[16], left_bottom_grid_pin_1_[0], left_bottom_grid_pin_9_[0] }), - .sram(mux_tree_tapbuf_size7_7_sram[0:2]), - .sram_inv(mux_left_track_9_undriven_sram_inv[0:2]), - .out(chanx_left_out[4]) - ); - - - mux_tree_tapbuf_size7 - mux_left_track_17 - ( - .in({ chany_top_in[3], chany_top_in[10], chany_top_in[17], chanx_right_in[8], chanx_right_in[17], left_bottom_grid_pin_3_[0], left_bottom_grid_pin_11_[0] }), - .sram(mux_tree_tapbuf_size7_8_sram[0:2]), - .sram_inv(mux_left_track_17_undriven_sram_inv[0:2]), - .out(chanx_left_out[8]) - ); - - - mux_tree_tapbuf_size7_mem - mem_top_track_2 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_0_sram[0:2]) - ); - - - mux_tree_tapbuf_size7_mem - mem_top_track_4 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_1_sram[0:2]) - ); - - - mux_tree_tapbuf_size7_mem - mem_top_track_6 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_2_sram[0:2]) - ); - - - mux_tree_tapbuf_size7_mem - mem_right_track_0 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size7_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_3_sram[0:2]) - ); - - - mux_tree_tapbuf_size7_mem - mem_right_track_8 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size11_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size7_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_4_sram[0:2]) - ); - - - mux_tree_tapbuf_size7_mem - mem_right_track_16 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size7_mem_4_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size7_mem_5_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_5_sram[0:2]) - ); - - - mux_tree_tapbuf_size7_mem - mem_left_track_3 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size7_mem_6_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_6_sram[0:2]) - ); - - - mux_tree_tapbuf_size7_mem - mem_left_track_9 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size11_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size7_mem_7_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_7_sram[0:2]) - ); - - - mux_tree_tapbuf_size7_mem - mem_left_track_17 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size7_mem_7_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size7_mem_8_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_8_sram[0:2]) - ); - - - mux_tree_tapbuf_size4 - mux_top_track_8 - ( - .in({ top_left_grid_pin_42_[0], chanx_right_in[8], chanx_right_in[15], chanx_left_in[8] }), - .sram(mux_tree_tapbuf_size4_0_sram[0:2]), - .sram_inv(mux_top_track_8_undriven_sram_inv[0:2]), - .out(chany_top_out[4]) - ); - - - mux_tree_tapbuf_size4 - mux_top_track_10 - ( - .in({ top_left_grid_pin_43_[0], chanx_right_in[9], chanx_right_in[19], chanx_left_in[9] }), - .sram(mux_tree_tapbuf_size4_1_sram[0:2]), - .sram_inv(mux_top_track_10_undriven_sram_inv[0:2]), - .out(chany_top_out[5]) - ); - - - mux_tree_tapbuf_size4_mem - mem_top_track_8 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size4_0_sram[0:2]) - ); - - - mux_tree_tapbuf_size4_mem - mem_top_track_10 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size4_1_sram[0:2]) - ); - - - mux_tree_tapbuf_size3 - mux_top_track_12 - ( - .in({ top_left_grid_pin_44_[0], chanx_right_in[10], chanx_left_in[10] }), - .sram(mux_tree_tapbuf_size3_0_sram[0:1]), - .sram_inv(mux_top_track_12_undriven_sram_inv[0:1]), - .out(chany_top_out[6]) - ); - - - mux_tree_tapbuf_size3 - mux_top_track_14 - ( - .in({ top_left_grid_pin_45_[0], chanx_right_in[12], chanx_left_in[12] }), - .sram(mux_tree_tapbuf_size3_1_sram[0:1]), - .sram_inv(mux_top_track_14_undriven_sram_inv[0:1]), - .out(chany_top_out[7]) - ); - - - mux_tree_tapbuf_size3 - mux_top_track_16 - ( - .in({ top_left_grid_pin_46_[0], chanx_right_in[13], chanx_left_in[13] }), - .sram(mux_tree_tapbuf_size3_2_sram[0:1]), - .sram_inv(mux_top_track_16_undriven_sram_inv[0:1]), - .out(chany_top_out[8]) - ); - - - mux_tree_tapbuf_size3 - mux_top_track_18 - ( - .in({ top_left_grid_pin_47_[0], chanx_right_in[14], chanx_left_in[14] }), - .sram(mux_tree_tapbuf_size3_3_sram[0:1]), - .sram_inv(mux_top_track_18_undriven_sram_inv[0:1]), - .out(chany_top_out[9]) - ); - - - mux_tree_tapbuf_size3 - mux_top_track_20 - ( - .in({ top_left_grid_pin_48_[0], chanx_right_in[16], chanx_left_in[16] }), - .sram(mux_tree_tapbuf_size3_4_sram[0:1]), - .sram_inv(mux_top_track_20_undriven_sram_inv[0:1]), - .out(chany_top_out[10]) - ); - - - mux_tree_tapbuf_size3 - mux_top_track_22 - ( - .in({ top_left_grid_pin_49_[0], chanx_right_in[17], chanx_left_in[17] }), - .sram(mux_tree_tapbuf_size3_5_sram[0:1]), - .sram_inv(mux_top_track_22_undriven_sram_inv[0:1]), - .out(chany_top_out[11]) - ); - - - mux_tree_tapbuf_size3 - mux_top_track_24 - ( - .in({ top_left_grid_pin_42_[0], chanx_right_in[18], chanx_left_in[18] }), - .sram(mux_tree_tapbuf_size3_6_sram[0:1]), - .sram_inv(mux_top_track_24_undriven_sram_inv[0:1]), - .out(chany_top_out[12]) - ); - - - mux_tree_tapbuf_size3_mem - mem_top_track_12 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_0_sram[0:1]) - ); - - - mux_tree_tapbuf_size3_mem - mem_top_track_14 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_1_sram[0:1]) - ); - - - mux_tree_tapbuf_size3_mem - mem_top_track_16 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_2_sram[0:1]) - ); - - - mux_tree_tapbuf_size3_mem - mem_top_track_18 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_3_sram[0:1]) - ); - - - mux_tree_tapbuf_size3_mem - mem_top_track_20 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_4_sram[0:1]) - ); - - - mux_tree_tapbuf_size3_mem - mem_top_track_22 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_5_sram[0:1]) - ); - - - mux_tree_tapbuf_size3_mem - mem_top_track_24 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_6_sram[0:1]) - ); - - - mux_tree_tapbuf_size2 - mux_top_track_38 - ( - .in({ chanx_right_in[0], chanx_left_in[1] }), - .sram(mux_tree_tapbuf_size2_0_sram[0:1]), - .sram_inv(mux_top_track_38_undriven_sram_inv[0:1]), - .out(chany_top_out[19]) - ); - - - mux_tree_tapbuf_size2_mem - mem_top_track_38 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_0_sram[0:1]) - ); - - - mux_tree_tapbuf_size11 - mux_right_track_4 - ( - .in({ chany_top_in[1], chany_top_in[8], chany_top_in[15], right_bottom_grid_pin_1_[0], right_bottom_grid_pin_3_[0], right_bottom_grid_pin_5_[0], right_bottom_grid_pin_7_[0], right_bottom_grid_pin_9_[0], right_bottom_grid_pin_11_[0], chanx_left_in[5], chanx_left_in[14] }), - .sram(mux_tree_tapbuf_size11_0_sram[0:3]), - .sram_inv(mux_right_track_4_undriven_sram_inv[0:3]), - .out(chanx_right_out[2]) - ); - - - mux_tree_tapbuf_size11 - mux_left_track_5 - ( - .in({ chany_top_in[5], chany_top_in[12], chany_top_in[19], chanx_right_in[5], chanx_right_in[14], left_bottom_grid_pin_1_[0], left_bottom_grid_pin_3_[0], left_bottom_grid_pin_5_[0], left_bottom_grid_pin_7_[0], left_bottom_grid_pin_9_[0], left_bottom_grid_pin_11_[0] }), - .sram(mux_tree_tapbuf_size11_1_sram[0:3]), - .sram_inv(mux_left_track_5_undriven_sram_inv[0:3]), - .out(chanx_left_out[2]) - ); - - - mux_tree_tapbuf_size11_mem - mem_right_track_4 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size11_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size11_0_sram[0:3]) - ); - - - mux_tree_tapbuf_size11_mem - mem_left_track_5 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size7_mem_6_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size11_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size11_1_sram[0:3]) - ); - - - mux_tree_tapbuf_size6 - mux_right_track_24 - ( - .in({ chany_top_in[4], chany_top_in[11], chany_top_in[18], right_bottom_grid_pin_5_[0], chanx_left_in[9], chanx_left_in[18] }), - .sram(mux_tree_tapbuf_size6_0_sram[0:2]), - .sram_inv(mux_right_track_24_undriven_sram_inv[0:2]), - .out(chanx_right_out[12]) - ); - - - mux_tree_tapbuf_size6 - mux_left_track_25 - ( - .in({ chany_top_in[2], chany_top_in[9], chany_top_in[16], chanx_right_in[9], chanx_right_in[18], left_bottom_grid_pin_5_[0] }), - .sram(mux_tree_tapbuf_size6_1_sram[0:2]), - .sram_inv(mux_left_track_25_undriven_sram_inv[0:2]), - .out(chanx_left_out[12]) - ); - - - mux_tree_tapbuf_size6_mem - mem_right_track_24 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size7_mem_5_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_0_sram[0:2]) - ); - - - mux_tree_tapbuf_size6_mem - mem_left_track_25 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size7_mem_8_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_1_sram[0:2]) - ); - - - mux_tree_tapbuf_size5 - mux_right_track_32 - ( - .in({ chany_top_in[5], chany_top_in[12], chany_top_in[19], right_bottom_grid_pin_7_[0], chanx_left_in[10] }), - .sram(mux_tree_tapbuf_size5_0_sram[0:2]), - .sram_inv(mux_right_track_32_undriven_sram_inv[0:2]), - .out(chanx_right_out[16]) - ); - - - mux_tree_tapbuf_size5 - mux_left_track_33 - ( - .in({ chany_top_in[1], chany_top_in[8], chany_top_in[15], chanx_right_in[10], left_bottom_grid_pin_7_[0] }), - .sram(mux_tree_tapbuf_size5_1_sram[0:2]), - .sram_inv(mux_left_track_33_undriven_sram_inv[0:2]), - .out(chanx_left_out[16]) - ); - - - mux_tree_tapbuf_size5_mem - mem_right_track_32 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size5_0_sram[0:2]) - ); - - - mux_tree_tapbuf_size5_mem - mem_left_track_33 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]), - .ccff_tail(ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size5_1_sram[0:2]) - ); - - -endmodule - diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_1__1_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_1__1_.v deleted file mode 100644 index 48df5f7..0000000 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_1__1_.v +++ /dev/null @@ -1,746 +0,0 @@ - - -module sb_1__1_ -( prog_clk, chany_top_in, top_left_grid_pin_42_, top_left_grid_pin_43_, top_left_grid_pin_44_, top_left_grid_pin_45_, top_left_grid_pin_46_, top_left_grid_pin_47_, top_left_grid_pin_48_, top_left_grid_pin_49_, chanx_right_in, right_bottom_grid_pin_34_, right_bottom_grid_pin_35_, right_bottom_grid_pin_36_, right_bottom_grid_pin_37_, right_bottom_grid_pin_38_, right_bottom_grid_pin_39_, right_bottom_grid_pin_40_, right_bottom_grid_pin_41_, chany_bottom_in, bottom_left_grid_pin_42_, bottom_left_grid_pin_43_, bottom_left_grid_pin_44_, bottom_left_grid_pin_45_, bottom_left_grid_pin_46_, bottom_left_grid_pin_47_, bottom_left_grid_pin_48_, bottom_left_grid_pin_49_, chanx_left_in, left_bottom_grid_pin_34_, left_bottom_grid_pin_35_, left_bottom_grid_pin_36_, left_bottom_grid_pin_37_, left_bottom_grid_pin_38_, left_bottom_grid_pin_39_, left_bottom_grid_pin_40_, left_bottom_grid_pin_41_, ccff_head, chany_top_out, chanx_right_out, chany_bottom_out, chanx_left_out, ccff_tail ); - input [0:0] prog_clk; - input [0:19] chany_top_in; - input [0:0] top_left_grid_pin_42_; - input [0:0] top_left_grid_pin_43_; - input [0:0] top_left_grid_pin_44_; - input [0:0] top_left_grid_pin_45_; - input [0:0] top_left_grid_pin_46_; - input [0:0] top_left_grid_pin_47_; - input [0:0] top_left_grid_pin_48_; - input [0:0] top_left_grid_pin_49_; - input [0:19] chanx_right_in; - input [0:0] right_bottom_grid_pin_34_; - input [0:0] right_bottom_grid_pin_35_; - input [0:0] right_bottom_grid_pin_36_; - input [0:0] right_bottom_grid_pin_37_; - input [0:0] right_bottom_grid_pin_38_; - input [0:0] right_bottom_grid_pin_39_; - input [0:0] right_bottom_grid_pin_40_; - input [0:0] right_bottom_grid_pin_41_; - input [0:19] chany_bottom_in; - input [0:0] bottom_left_grid_pin_42_; - input [0:0] bottom_left_grid_pin_43_; - input [0:0] bottom_left_grid_pin_44_; - input [0:0] bottom_left_grid_pin_45_; - input [0:0] bottom_left_grid_pin_46_; - input [0:0] bottom_left_grid_pin_47_; - input [0:0] bottom_left_grid_pin_48_; - input [0:0] bottom_left_grid_pin_49_; - input [0:19] chanx_left_in; - input [0:0] left_bottom_grid_pin_34_; - input [0:0] left_bottom_grid_pin_35_; - input [0:0] left_bottom_grid_pin_36_; - input [0:0] left_bottom_grid_pin_37_; - input [0:0] left_bottom_grid_pin_38_; - input [0:0] left_bottom_grid_pin_39_; - input [0:0] left_bottom_grid_pin_40_; - input [0:0] left_bottom_grid_pin_41_; - input [0:0] ccff_head; - output [0:19] chany_top_out; - output [0:19] chanx_right_out; - output [0:19] chany_bottom_out; - output [0:19] chanx_left_out; - output [0:0] ccff_tail; - - wire [0:3] mux_bottom_track_17_undriven_sram_inv; - wire [0:3] mux_bottom_track_1_undriven_sram_inv; - wire [0:3] mux_bottom_track_25_undriven_sram_inv; - wire [0:2] mux_bottom_track_33_undriven_sram_inv; - wire [0:3] mux_bottom_track_3_undriven_sram_inv; - wire [0:4] mux_bottom_track_5_undriven_sram_inv; - wire [0:3] mux_bottom_track_9_undriven_sram_inv; - wire [0:3] mux_left_track_17_undriven_sram_inv; - wire [0:3] mux_left_track_1_undriven_sram_inv; - wire [0:3] mux_left_track_25_undriven_sram_inv; - wire [0:2] mux_left_track_33_undriven_sram_inv; - wire [0:3] mux_left_track_3_undriven_sram_inv; - wire [0:4] mux_left_track_5_undriven_sram_inv; - wire [0:3] mux_left_track_9_undriven_sram_inv; - wire [0:3] mux_right_track_0_undriven_sram_inv; - wire [0:3] mux_right_track_16_undriven_sram_inv; - wire [0:3] mux_right_track_24_undriven_sram_inv; - wire [0:3] mux_right_track_2_undriven_sram_inv; - wire [0:2] mux_right_track_32_undriven_sram_inv; - wire [0:4] mux_right_track_4_undriven_sram_inv; - wire [0:3] mux_right_track_8_undriven_sram_inv; - wire [0:3] mux_top_track_0_undriven_sram_inv; - wire [0:3] mux_top_track_16_undriven_sram_inv; - wire [0:3] mux_top_track_24_undriven_sram_inv; - wire [0:3] mux_top_track_2_undriven_sram_inv; - wire [0:2] mux_top_track_32_undriven_sram_inv; - wire [0:4] mux_top_track_4_undriven_sram_inv; - wire [0:3] mux_top_track_8_undriven_sram_inv; - wire [0:3] mux_tree_tapbuf_size10_0_sram; - wire [0:3] mux_tree_tapbuf_size10_10_sram; - wire [0:3] mux_tree_tapbuf_size10_11_sram; - wire [0:3] mux_tree_tapbuf_size10_1_sram; - wire [0:3] mux_tree_tapbuf_size10_2_sram; - wire [0:3] mux_tree_tapbuf_size10_3_sram; - wire [0:3] mux_tree_tapbuf_size10_4_sram; - wire [0:3] mux_tree_tapbuf_size10_5_sram; - wire [0:3] mux_tree_tapbuf_size10_6_sram; - wire [0:3] mux_tree_tapbuf_size10_7_sram; - wire [0:3] mux_tree_tapbuf_size10_8_sram; - wire [0:3] mux_tree_tapbuf_size10_9_sram; - wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail; - wire [0:0] mux_tree_tapbuf_size10_mem_10_ccff_tail; - wire [0:0] mux_tree_tapbuf_size10_mem_11_ccff_tail; - wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail; - wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail; - wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail; - wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail; - wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail; - wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail; - wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail; - wire [0:0] mux_tree_tapbuf_size10_mem_8_ccff_tail; - wire [0:0] mux_tree_tapbuf_size10_mem_9_ccff_tail; - wire [0:3] mux_tree_tapbuf_size12_0_sram; - wire [0:3] mux_tree_tapbuf_size12_1_sram; - wire [0:3] mux_tree_tapbuf_size12_2_sram; - wire [0:3] mux_tree_tapbuf_size12_3_sram; - wire [0:3] mux_tree_tapbuf_size12_4_sram; - wire [0:3] mux_tree_tapbuf_size12_5_sram; - wire [0:3] mux_tree_tapbuf_size12_6_sram; - wire [0:3] mux_tree_tapbuf_size12_7_sram; - wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail; - wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail; - wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail; - wire [0:0] mux_tree_tapbuf_size12_mem_3_ccff_tail; - wire [0:0] mux_tree_tapbuf_size12_mem_4_ccff_tail; - wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail; - wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail; - wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail; - wire [0:4] mux_tree_tapbuf_size16_0_sram; - wire [0:4] mux_tree_tapbuf_size16_1_sram; - wire [0:4] mux_tree_tapbuf_size16_2_sram; - wire [0:4] mux_tree_tapbuf_size16_3_sram; - wire [0:0] mux_tree_tapbuf_size16_mem_0_ccff_tail; - wire [0:0] mux_tree_tapbuf_size16_mem_1_ccff_tail; - wire [0:0] mux_tree_tapbuf_size16_mem_2_ccff_tail; - wire [0:0] mux_tree_tapbuf_size16_mem_3_ccff_tail; - wire [0:2] mux_tree_tapbuf_size7_0_sram; - wire [0:2] mux_tree_tapbuf_size7_1_sram; - wire [0:2] mux_tree_tapbuf_size7_2_sram; - wire [0:2] mux_tree_tapbuf_size7_3_sram; - wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail; - wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail; - wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail; - assign chany_bottom_out[3] = chany_top_in[2]; - assign chany_bottom_out[5] = chany_top_in[4]; - assign chany_bottom_out[6] = chany_top_in[5]; - assign chany_bottom_out[7] = chany_top_in[6]; - assign chany_bottom_out[9] = chany_top_in[8]; - assign chany_bottom_out[10] = chany_top_in[9]; - assign chany_bottom_out[11] = chany_top_in[10]; - assign chany_bottom_out[13] = chany_top_in[12]; - assign chany_bottom_out[14] = chany_top_in[13]; - assign chany_bottom_out[15] = chany_top_in[14]; - assign chany_bottom_out[17] = chany_top_in[16]; - assign chany_bottom_out[18] = chany_top_in[17]; - assign chany_bottom_out[19] = chany_top_in[18]; - assign chanx_left_out[3] = chanx_right_in[2]; - assign chanx_left_out[5] = chanx_right_in[4]; - assign chanx_left_out[6] = chanx_right_in[5]; - assign chanx_left_out[7] = chanx_right_in[6]; - assign chanx_left_out[9] = chanx_right_in[8]; - assign chanx_left_out[10] = chanx_right_in[9]; - assign chanx_left_out[11] = chanx_right_in[10]; - assign chanx_left_out[13] = chanx_right_in[12]; - assign chanx_left_out[14] = chanx_right_in[13]; - assign chanx_left_out[15] = chanx_right_in[14]; - assign chanx_left_out[17] = chanx_right_in[16]; - assign chanx_left_out[18] = chanx_right_in[17]; - assign chanx_left_out[19] = chanx_right_in[18]; - assign chany_top_out[3] = chany_bottom_in[2]; - assign chany_top_out[5] = chany_bottom_in[4]; - assign chany_top_out[6] = chany_bottom_in[5]; - assign chany_top_out[7] = chany_bottom_in[6]; - assign chany_top_out[9] = chany_bottom_in[8]; - assign chany_top_out[10] = chany_bottom_in[9]; - assign chany_top_out[11] = chany_bottom_in[10]; - assign chany_top_out[13] = chany_bottom_in[12]; - assign chany_top_out[14] = chany_bottom_in[13]; - assign chany_top_out[15] = chany_bottom_in[14]; - assign chany_top_out[17] = chany_bottom_in[16]; - assign chany_top_out[18] = chany_bottom_in[17]; - assign chany_top_out[19] = chany_bottom_in[18]; - assign chanx_right_out[3] = chanx_left_in[2]; - assign chanx_right_out[5] = chanx_left_in[4]; - assign chanx_right_out[6] = chanx_left_in[5]; - assign chanx_right_out[7] = chanx_left_in[6]; - assign chanx_right_out[9] = chanx_left_in[8]; - assign chanx_right_out[10] = chanx_left_in[9]; - assign chanx_right_out[11] = chanx_left_in[10]; - assign chanx_right_out[13] = chanx_left_in[12]; - assign chanx_right_out[14] = chanx_left_in[13]; - assign chanx_right_out[15] = chanx_left_in[14]; - assign chanx_right_out[17] = chanx_left_in[16]; - assign chanx_right_out[18] = chanx_left_in[17]; - assign chanx_right_out[19] = chanx_left_in[18]; - - mux_tree_tapbuf_size12 - mux_top_track_0 - ( - .in({ top_left_grid_pin_42_[0], top_left_grid_pin_44_[0], top_left_grid_pin_46_[0], top_left_grid_pin_48_[0], chanx_right_in[1:2], chanx_right_in[12], chany_bottom_in[2], chany_bottom_in[12], chanx_left_in[0], chanx_left_in[2], chanx_left_in[12] }), - .sram(mux_tree_tapbuf_size12_0_sram[0:3]), - .sram_inv(mux_top_track_0_undriven_sram_inv[0:3]), - .out(chany_top_out[0]) - ); - - - mux_tree_tapbuf_size12 - mux_top_track_2 - ( - .in({ top_left_grid_pin_43_[0], top_left_grid_pin_45_[0], top_left_grid_pin_47_[0], top_left_grid_pin_49_[0], chanx_right_in[3:4], chanx_right_in[13], chany_bottom_in[4], chany_bottom_in[13], chanx_left_in[4], chanx_left_in[13], chanx_left_in[19] }), - .sram(mux_tree_tapbuf_size12_1_sram[0:3]), - .sram_inv(mux_top_track_2_undriven_sram_inv[0:3]), - .out(chany_top_out[1]) - ); - - - mux_tree_tapbuf_size12 - mux_right_track_0 - ( - .in({ chany_top_in[2], chany_top_in[12], chany_top_in[19], right_bottom_grid_pin_34_[0], right_bottom_grid_pin_36_[0], right_bottom_grid_pin_38_[0], right_bottom_grid_pin_40_[0], chany_bottom_in[2], chany_bottom_in[12], chany_bottom_in[15], chanx_left_in[2], chanx_left_in[12] }), - .sram(mux_tree_tapbuf_size12_2_sram[0:3]), - .sram_inv(mux_right_track_0_undriven_sram_inv[0:3]), - .out(chanx_right_out[0]) - ); - - - mux_tree_tapbuf_size12 - mux_right_track_2 - ( - .in({ chany_top_in[0], chany_top_in[4], chany_top_in[13], right_bottom_grid_pin_35_[0], right_bottom_grid_pin_37_[0], right_bottom_grid_pin_39_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[4], chany_bottom_in[11], chany_bottom_in[13], chanx_left_in[4], chanx_left_in[13] }), - .sram(mux_tree_tapbuf_size12_3_sram[0:3]), - .sram_inv(mux_right_track_2_undriven_sram_inv[0:3]), - .out(chanx_right_out[1]) - ); - - - mux_tree_tapbuf_size12 - mux_bottom_track_1 - ( - .in({ chany_top_in[2], chany_top_in[12], chanx_right_in[2], chanx_right_in[12], chanx_right_in[15], bottom_left_grid_pin_42_[0], bottom_left_grid_pin_44_[0], bottom_left_grid_pin_46_[0], bottom_left_grid_pin_48_[0], chanx_left_in[1:2], chanx_left_in[12] }), - .sram(mux_tree_tapbuf_size12_4_sram[0:3]), - .sram_inv(mux_bottom_track_1_undriven_sram_inv[0:3]), - .out(chany_bottom_out[0]) - ); - - - mux_tree_tapbuf_size12 - mux_bottom_track_3 - ( - .in({ chany_top_in[4], chany_top_in[13], chanx_right_in[4], chanx_right_in[11], chanx_right_in[13], bottom_left_grid_pin_43_[0], bottom_left_grid_pin_45_[0], bottom_left_grid_pin_47_[0], bottom_left_grid_pin_49_[0], chanx_left_in[3:4], chanx_left_in[13] }), - .sram(mux_tree_tapbuf_size12_5_sram[0:3]), - .sram_inv(mux_bottom_track_3_undriven_sram_inv[0:3]), - .out(chany_bottom_out[1]) - ); - - - mux_tree_tapbuf_size12 - mux_left_track_1 - ( - .in({ chany_top_in[0], chany_top_in[2], chany_top_in[12], chanx_right_in[2], chanx_right_in[12], chany_bottom_in[2], chany_bottom_in[12], chany_bottom_in[19], left_bottom_grid_pin_34_[0], left_bottom_grid_pin_36_[0], left_bottom_grid_pin_38_[0], left_bottom_grid_pin_40_[0] }), - .sram(mux_tree_tapbuf_size12_6_sram[0:3]), - .sram_inv(mux_left_track_1_undriven_sram_inv[0:3]), - .out(chanx_left_out[0]) - ); - - - mux_tree_tapbuf_size12 - mux_left_track_3 - ( - .in({ chany_top_in[4], chany_top_in[13], chany_top_in[19], chanx_right_in[4], chanx_right_in[13], chany_bottom_in[0], chany_bottom_in[4], chany_bottom_in[13], left_bottom_grid_pin_35_[0], left_bottom_grid_pin_37_[0], left_bottom_grid_pin_39_[0], left_bottom_grid_pin_41_[0] }), - .sram(mux_tree_tapbuf_size12_7_sram[0:3]), - .sram_inv(mux_left_track_3_undriven_sram_inv[0:3]), - .out(chanx_left_out[1]) - ); - - - mux_tree_tapbuf_size12_mem - mem_top_track_0 - ( - .prog_clk(prog_clk[0]), - .ccff_head(ccff_head[0]), - .ccff_tail(mux_tree_tapbuf_size12_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size12_0_sram[0:3]) - ); - - - mux_tree_tapbuf_size12_mem - mem_top_track_2 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size12_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size12_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size12_1_sram[0:3]) - ); - - - mux_tree_tapbuf_size12_mem - mem_right_track_0 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size12_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size12_2_sram[0:3]) - ); - - - mux_tree_tapbuf_size12_mem - mem_right_track_2 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size12_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size12_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size12_3_sram[0:3]) - ); - - - mux_tree_tapbuf_size12_mem - mem_bottom_track_1 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size12_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size12_4_sram[0:3]) - ); - - - mux_tree_tapbuf_size12_mem - mem_bottom_track_3 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size12_mem_4_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size12_mem_5_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size12_5_sram[0:3]) - ); - - - mux_tree_tapbuf_size12_mem - mem_left_track_1 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size12_mem_6_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size12_6_sram[0:3]) - ); - - - mux_tree_tapbuf_size12_mem - mem_left_track_3 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size12_mem_6_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size12_mem_7_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size12_7_sram[0:3]) - ); - - - mux_tree_tapbuf_size16 - mux_top_track_4 - ( - .in({ top_left_grid_pin_42_[0], top_left_grid_pin_43_[0], top_left_grid_pin_44_[0], top_left_grid_pin_45_[0], top_left_grid_pin_46_[0], top_left_grid_pin_47_[0], top_left_grid_pin_48_[0], top_left_grid_pin_49_[0], chanx_right_in[5], chanx_right_in[7], chanx_right_in[14], chany_bottom_in[5], chany_bottom_in[14], chanx_left_in[5], chanx_left_in[14:15] }), - .sram(mux_tree_tapbuf_size16_0_sram[0:4]), - .sram_inv(mux_top_track_4_undriven_sram_inv[0:4]), - .out(chany_top_out[2]) - ); - - - mux_tree_tapbuf_size16 - mux_right_track_4 - ( - .in({ chany_top_in[1], chany_top_in[5], chany_top_in[14], right_bottom_grid_pin_34_[0], right_bottom_grid_pin_35_[0], right_bottom_grid_pin_36_[0], right_bottom_grid_pin_37_[0], right_bottom_grid_pin_38_[0], right_bottom_grid_pin_39_[0], right_bottom_grid_pin_40_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[5], chany_bottom_in[7], chany_bottom_in[14], chanx_left_in[5], chanx_left_in[14] }), - .sram(mux_tree_tapbuf_size16_1_sram[0:4]), - .sram_inv(mux_right_track_4_undriven_sram_inv[0:4]), - .out(chanx_right_out[2]) - ); - - - mux_tree_tapbuf_size16 - mux_bottom_track_5 - ( - .in({ chany_top_in[5], chany_top_in[14], chanx_right_in[5], chanx_right_in[7], chanx_right_in[14], bottom_left_grid_pin_42_[0], bottom_left_grid_pin_43_[0], bottom_left_grid_pin_44_[0], bottom_left_grid_pin_45_[0], bottom_left_grid_pin_46_[0], bottom_left_grid_pin_47_[0], bottom_left_grid_pin_48_[0], bottom_left_grid_pin_49_[0], chanx_left_in[5], chanx_left_in[7], chanx_left_in[14] }), - .sram(mux_tree_tapbuf_size16_2_sram[0:4]), - .sram_inv(mux_bottom_track_5_undriven_sram_inv[0:4]), - .out(chany_bottom_out[2]) - ); - - - mux_tree_tapbuf_size16 - mux_left_track_5 - ( - .in({ chany_top_in[5], chany_top_in[14:15], chanx_right_in[5], chanx_right_in[14], chany_bottom_in[1], chany_bottom_in[5], chany_bottom_in[14], left_bottom_grid_pin_34_[0], left_bottom_grid_pin_35_[0], left_bottom_grid_pin_36_[0], left_bottom_grid_pin_37_[0], left_bottom_grid_pin_38_[0], left_bottom_grid_pin_39_[0], left_bottom_grid_pin_40_[0], left_bottom_grid_pin_41_[0] }), - .sram(mux_tree_tapbuf_size16_3_sram[0:4]), - .sram_inv(mux_left_track_5_undriven_sram_inv[0:4]), - .out(chanx_left_out[2]) - ); - - - mux_tree_tapbuf_size16_mem - mem_top_track_4 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size12_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size16_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size16_0_sram[0:4]) - ); - - - mux_tree_tapbuf_size16_mem - mem_right_track_4 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size12_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size16_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size16_1_sram[0:4]) - ); - - - mux_tree_tapbuf_size16_mem - mem_bottom_track_5 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size12_mem_5_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size16_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size16_2_sram[0:4]) - ); - - - mux_tree_tapbuf_size16_mem - mem_left_track_5 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size12_mem_7_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size16_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size16_3_sram[0:4]) - ); - - - mux_tree_tapbuf_size10 - mux_top_track_8 - ( - .in({ top_left_grid_pin_42_[0], top_left_grid_pin_46_[0], chanx_right_in[6], chanx_right_in[11], chanx_right_in[16], chany_bottom_in[6], chany_bottom_in[16], chanx_left_in[6], chanx_left_in[11], chanx_left_in[16] }), - .sram(mux_tree_tapbuf_size10_0_sram[0:3]), - .sram_inv(mux_top_track_8_undriven_sram_inv[0:3]), - .out(chany_top_out[4]) - ); - - - mux_tree_tapbuf_size10 - mux_top_track_16 - ( - .in({ top_left_grid_pin_43_[0], top_left_grid_pin_47_[0], chanx_right_in[8], chanx_right_in[15], chanx_right_in[17], chany_bottom_in[8], chany_bottom_in[17], chanx_left_in[7:8], chanx_left_in[17] }), - .sram(mux_tree_tapbuf_size10_1_sram[0:3]), - .sram_inv(mux_top_track_16_undriven_sram_inv[0:3]), - .out(chany_top_out[8]) - ); - - - mux_tree_tapbuf_size10 - mux_top_track_24 - ( - .in({ top_left_grid_pin_44_[0], top_left_grid_pin_48_[0], chanx_right_in[9], chanx_right_in[18:19], chany_bottom_in[9], chany_bottom_in[18], chanx_left_in[3], chanx_left_in[9], chanx_left_in[18] }), - .sram(mux_tree_tapbuf_size10_2_sram[0:3]), - .sram_inv(mux_top_track_24_undriven_sram_inv[0:3]), - .out(chany_top_out[12]) - ); - - - mux_tree_tapbuf_size10 - mux_right_track_8 - ( - .in({ chany_top_in[3], chany_top_in[6], chany_top_in[16], right_bottom_grid_pin_34_[0], right_bottom_grid_pin_38_[0], chany_bottom_in[3], chany_bottom_in[6], chany_bottom_in[16], chanx_left_in[6], chanx_left_in[16] }), - .sram(mux_tree_tapbuf_size10_3_sram[0:3]), - .sram_inv(mux_right_track_8_undriven_sram_inv[0:3]), - .out(chanx_right_out[4]) - ); - - - mux_tree_tapbuf_size10 - mux_right_track_16 - ( - .in({ chany_top_in[7:8], chany_top_in[17], right_bottom_grid_pin_35_[0], right_bottom_grid_pin_39_[0], chany_bottom_in[1], chany_bottom_in[8], chany_bottom_in[17], chanx_left_in[8], chanx_left_in[17] }), - .sram(mux_tree_tapbuf_size10_4_sram[0:3]), - .sram_inv(mux_right_track_16_undriven_sram_inv[0:3]), - .out(chanx_right_out[8]) - ); - - - mux_tree_tapbuf_size10 - mux_right_track_24 - ( - .in({ chany_top_in[9], chany_top_in[11], chany_top_in[18], right_bottom_grid_pin_36_[0], right_bottom_grid_pin_40_[0], chany_bottom_in[0], chany_bottom_in[9], chany_bottom_in[18], chanx_left_in[9], chanx_left_in[18] }), - .sram(mux_tree_tapbuf_size10_5_sram[0:3]), - .sram_inv(mux_right_track_24_undriven_sram_inv[0:3]), - .out(chanx_right_out[12]) - ); - - - mux_tree_tapbuf_size10 - mux_bottom_track_9 - ( - .in({ chany_top_in[6], chany_top_in[16], chanx_right_in[3], chanx_right_in[6], chanx_right_in[16], bottom_left_grid_pin_42_[0], bottom_left_grid_pin_46_[0], chanx_left_in[6], chanx_left_in[11], chanx_left_in[16] }), - .sram(mux_tree_tapbuf_size10_6_sram[0:3]), - .sram_inv(mux_bottom_track_9_undriven_sram_inv[0:3]), - .out(chany_bottom_out[4]) - ); - - - mux_tree_tapbuf_size10 - mux_bottom_track_17 - ( - .in({ chany_top_in[8], chany_top_in[17], chanx_right_in[1], chanx_right_in[8], chanx_right_in[17], bottom_left_grid_pin_43_[0], bottom_left_grid_pin_47_[0], chanx_left_in[8], chanx_left_in[15], chanx_left_in[17] }), - .sram(mux_tree_tapbuf_size10_7_sram[0:3]), - .sram_inv(mux_bottom_track_17_undriven_sram_inv[0:3]), - .out(chany_bottom_out[8]) - ); - - - mux_tree_tapbuf_size10 - mux_bottom_track_25 - ( - .in({ chany_top_in[9], chany_top_in[18], chanx_right_in[0], chanx_right_in[9], chanx_right_in[18], bottom_left_grid_pin_44_[0], bottom_left_grid_pin_48_[0], chanx_left_in[9], chanx_left_in[18:19] }), - .sram(mux_tree_tapbuf_size10_8_sram[0:3]), - .sram_inv(mux_bottom_track_25_undriven_sram_inv[0:3]), - .out(chany_bottom_out[12]) - ); - - - mux_tree_tapbuf_size10 - mux_left_track_9 - ( - .in({ chany_top_in[6], chany_top_in[11], chany_top_in[16], chanx_right_in[6], chanx_right_in[16], chany_bottom_in[3], chany_bottom_in[6], chany_bottom_in[16], left_bottom_grid_pin_34_[0], left_bottom_grid_pin_38_[0] }), - .sram(mux_tree_tapbuf_size10_9_sram[0:3]), - .sram_inv(mux_left_track_9_undriven_sram_inv[0:3]), - .out(chanx_left_out[4]) - ); - - - mux_tree_tapbuf_size10 - mux_left_track_17 - ( - .in({ chany_top_in[7:8], chany_top_in[17], chanx_right_in[8], chanx_right_in[17], chany_bottom_in[7:8], chany_bottom_in[17], left_bottom_grid_pin_35_[0], left_bottom_grid_pin_39_[0] }), - .sram(mux_tree_tapbuf_size10_10_sram[0:3]), - .sram_inv(mux_left_track_17_undriven_sram_inv[0:3]), - .out(chanx_left_out[8]) - ); - - - mux_tree_tapbuf_size10 - mux_left_track_25 - ( - .in({ chany_top_in[3], chany_top_in[9], chany_top_in[18], chanx_right_in[9], chanx_right_in[18], chany_bottom_in[9], chany_bottom_in[11], chany_bottom_in[18], left_bottom_grid_pin_36_[0], left_bottom_grid_pin_40_[0] }), - .sram(mux_tree_tapbuf_size10_11_sram[0:3]), - .sram_inv(mux_left_track_25_undriven_sram_inv[0:3]), - .out(chanx_left_out[12]) - ); - - - mux_tree_tapbuf_size10_mem - mem_top_track_8 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size16_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_0_sram[0:3]) - ); - - - mux_tree_tapbuf_size10_mem - mem_top_track_16 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_1_sram[0:3]) - ); - - - mux_tree_tapbuf_size10_mem - mem_top_track_24 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_2_sram[0:3]) - ); - - - mux_tree_tapbuf_size10_mem - mem_right_track_8 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size16_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_3_sram[0:3]) - ); - - - mux_tree_tapbuf_size10_mem - mem_right_track_16 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_4_sram[0:3]) - ); - - - mux_tree_tapbuf_size10_mem - mem_right_track_24 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_5_sram[0:3]) - ); - - - mux_tree_tapbuf_size10_mem - mem_bottom_track_9 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size16_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_6_sram[0:3]) - ); - - - mux_tree_tapbuf_size10_mem - mem_bottom_track_17 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_7_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_7_sram[0:3]) - ); - - - mux_tree_tapbuf_size10_mem - mem_bottom_track_25 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_7_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_8_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_8_sram[0:3]) - ); - - - mux_tree_tapbuf_size10_mem - mem_left_track_9 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size16_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_9_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_9_sram[0:3]) - ); - - - mux_tree_tapbuf_size10_mem - mem_left_track_17 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_9_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_10_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_10_sram[0:3]) - ); - - - mux_tree_tapbuf_size10_mem - mem_left_track_25 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_10_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_11_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_11_sram[0:3]) - ); - - - mux_tree_tapbuf_size7 - mux_top_track_32 - ( - .in({ top_left_grid_pin_45_[0], top_left_grid_pin_49_[0], chanx_right_in[0], chanx_right_in[10], chany_bottom_in[10], chanx_left_in[1], chanx_left_in[10] }), - .sram(mux_tree_tapbuf_size7_0_sram[0:2]), - .sram_inv(mux_top_track_32_undriven_sram_inv[0:2]), - .out(chany_top_out[16]) - ); - - - mux_tree_tapbuf_size7 - mux_right_track_32 - ( - .in({ chany_top_in[10], chany_top_in[15], right_bottom_grid_pin_37_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[10], chany_bottom_in[19], chanx_left_in[10] }), - .sram(mux_tree_tapbuf_size7_1_sram[0:2]), - .sram_inv(mux_right_track_32_undriven_sram_inv[0:2]), - .out(chanx_right_out[16]) - ); - - - mux_tree_tapbuf_size7 - mux_bottom_track_33 - ( - .in({ chany_top_in[10], chanx_right_in[10], chanx_right_in[19], bottom_left_grid_pin_45_[0], bottom_left_grid_pin_49_[0], chanx_left_in[0], chanx_left_in[10] }), - .sram(mux_tree_tapbuf_size7_2_sram[0:2]), - .sram_inv(mux_bottom_track_33_undriven_sram_inv[0:2]), - .out(chany_bottom_out[16]) - ); - - - mux_tree_tapbuf_size7 - mux_left_track_33 - ( - .in({ chany_top_in[1], chany_top_in[10], chanx_right_in[10], chany_bottom_in[10], chany_bottom_in[15], left_bottom_grid_pin_37_[0], left_bottom_grid_pin_41_[0] }), - .sram(mux_tree_tapbuf_size7_3_sram[0:2]), - .sram_inv(mux_left_track_33_undriven_sram_inv[0:2]), - .out(chanx_left_out[16]) - ); - - - mux_tree_tapbuf_size7_mem - mem_top_track_32 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_0_sram[0:2]) - ); - - - mux_tree_tapbuf_size7_mem - mem_right_track_32 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_1_sram[0:2]) - ); - - - mux_tree_tapbuf_size7_mem - mem_bottom_track_33 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_8_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_2_sram[0:2]) - ); - - - mux_tree_tapbuf_size7_mem - mem_left_track_33 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_11_ccff_tail[0]), - .ccff_tail(ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_3_sram[0:2]) - ); - - -endmodule - diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_1__2_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_1__2_.v deleted file mode 100644 index 0b691df..0000000 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_1__2_.v +++ /dev/null @@ -1,724 +0,0 @@ - - -module sb_1__2_ -( prog_clk, chanx_right_in, right_top_grid_pin_1_, right_bottom_grid_pin_34_, right_bottom_grid_pin_35_, right_bottom_grid_pin_36_, right_bottom_grid_pin_37_, right_bottom_grid_pin_38_, right_bottom_grid_pin_39_, right_bottom_grid_pin_40_, right_bottom_grid_pin_41_, chany_bottom_in, bottom_left_grid_pin_42_, bottom_left_grid_pin_43_, bottom_left_grid_pin_44_, bottom_left_grid_pin_45_, bottom_left_grid_pin_46_, bottom_left_grid_pin_47_, bottom_left_grid_pin_48_, bottom_left_grid_pin_49_, chanx_left_in, left_top_grid_pin_1_, left_bottom_grid_pin_34_, left_bottom_grid_pin_35_, left_bottom_grid_pin_36_, left_bottom_grid_pin_37_, left_bottom_grid_pin_38_, left_bottom_grid_pin_39_, left_bottom_grid_pin_40_, left_bottom_grid_pin_41_, ccff_head, chanx_right_out, chany_bottom_out, chanx_left_out, ccff_tail, SC_IN_TOP, SC_IN_BOT, SC_OUT_TOP, SC_OUT_BOT ); - input [0:0] prog_clk; - input [0:19] chanx_right_in; - input [0:0] right_top_grid_pin_1_; - input [0:0] right_bottom_grid_pin_34_; - input [0:0] right_bottom_grid_pin_35_; - input [0:0] right_bottom_grid_pin_36_; - input [0:0] right_bottom_grid_pin_37_; - input [0:0] right_bottom_grid_pin_38_; - input [0:0] right_bottom_grid_pin_39_; - input [0:0] right_bottom_grid_pin_40_; - input [0:0] right_bottom_grid_pin_41_; - input [0:19] chany_bottom_in; - input [0:0] bottom_left_grid_pin_42_; - input [0:0] bottom_left_grid_pin_43_; - input [0:0] bottom_left_grid_pin_44_; - input [0:0] bottom_left_grid_pin_45_; - input [0:0] bottom_left_grid_pin_46_; - input [0:0] bottom_left_grid_pin_47_; - input [0:0] bottom_left_grid_pin_48_; - input [0:0] bottom_left_grid_pin_49_; - input [0:19] chanx_left_in; - input [0:0] left_top_grid_pin_1_; - input [0:0] left_bottom_grid_pin_34_; - input [0:0] left_bottom_grid_pin_35_; - input [0:0] left_bottom_grid_pin_36_; - input [0:0] left_bottom_grid_pin_37_; - input [0:0] left_bottom_grid_pin_38_; - input [0:0] left_bottom_grid_pin_39_; - input [0:0] left_bottom_grid_pin_40_; - input [0:0] left_bottom_grid_pin_41_; - input [0:0] ccff_head; - output [0:19] chanx_right_out; - output [0:19] chany_bottom_out; - output [0:19] chanx_left_out; - output [0:0] ccff_tail; - input SC_IN_TOP; - input SC_IN_BOT; - output SC_OUT_TOP; - output SC_OUT_BOT; - - wire [0:2] mux_bottom_track_11_undriven_sram_inv; - wire [0:1] mux_bottom_track_13_undriven_sram_inv; - wire [0:1] mux_bottom_track_15_undriven_sram_inv; - wire [0:1] mux_bottom_track_17_undriven_sram_inv; - wire [0:1] mux_bottom_track_19_undriven_sram_inv; - wire [0:2] mux_bottom_track_1_undriven_sram_inv; - wire [0:1] mux_bottom_track_21_undriven_sram_inv; - wire [0:1] mux_bottom_track_23_undriven_sram_inv; - wire [0:2] mux_bottom_track_25_undriven_sram_inv; - wire [0:1] mux_bottom_track_27_undriven_sram_inv; - wire [0:2] mux_bottom_track_3_undriven_sram_inv; - wire [0:2] mux_bottom_track_5_undriven_sram_inv; - wire [0:2] mux_bottom_track_7_undriven_sram_inv; - wire [0:2] mux_bottom_track_9_undriven_sram_inv; - wire [0:2] mux_left_track_17_undriven_sram_inv; - wire [0:3] mux_left_track_1_undriven_sram_inv; - wire [0:2] mux_left_track_25_undriven_sram_inv; - wire [0:2] mux_left_track_33_undriven_sram_inv; - wire [0:3] mux_left_track_3_undriven_sram_inv; - wire [0:3] mux_left_track_5_undriven_sram_inv; - wire [0:3] mux_left_track_9_undriven_sram_inv; - wire [0:3] mux_right_track_0_undriven_sram_inv; - wire [0:2] mux_right_track_16_undriven_sram_inv; - wire [0:2] mux_right_track_24_undriven_sram_inv; - wire [0:3] mux_right_track_2_undriven_sram_inv; - wire [0:2] mux_right_track_32_undriven_sram_inv; - wire [0:3] mux_right_track_4_undriven_sram_inv; - wire [0:3] mux_right_track_8_undriven_sram_inv; - wire [0:3] mux_tree_tapbuf_size10_0_sram; - wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail; - wire [0:3] mux_tree_tapbuf_size14_0_sram; - wire [0:3] mux_tree_tapbuf_size14_1_sram; - wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail; - wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail; - wire [0:1] mux_tree_tapbuf_size2_0_sram; - wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail; - wire [0:1] mux_tree_tapbuf_size3_0_sram; - wire [0:1] mux_tree_tapbuf_size3_1_sram; - wire [0:1] mux_tree_tapbuf_size3_2_sram; - wire [0:1] mux_tree_tapbuf_size3_3_sram; - wire [0:1] mux_tree_tapbuf_size3_4_sram; - wire [0:1] mux_tree_tapbuf_size3_5_sram; - wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail; - wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail; - wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail; - wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail; - wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail; - wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail; - wire [0:2] mux_tree_tapbuf_size4_0_sram; - wire [0:2] mux_tree_tapbuf_size4_1_sram; - wire [0:2] mux_tree_tapbuf_size4_2_sram; - wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail; - wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail; - wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail; - wire [0:2] mux_tree_tapbuf_size5_0_sram; - wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail; - wire [0:2] mux_tree_tapbuf_size6_0_sram; - wire [0:2] mux_tree_tapbuf_size7_0_sram; - wire [0:2] mux_tree_tapbuf_size7_1_sram; - wire [0:2] mux_tree_tapbuf_size7_2_sram; - wire [0:2] mux_tree_tapbuf_size7_3_sram; - wire [0:2] mux_tree_tapbuf_size7_4_sram; - wire [0:2] mux_tree_tapbuf_size7_5_sram; - wire [0:2] mux_tree_tapbuf_size7_6_sram; - wire [0:2] mux_tree_tapbuf_size7_7_sram; - wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail; - wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail; - wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail; - wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail; - wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail; - wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail; - wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail; - wire [0:0] mux_tree_tapbuf_size7_mem_7_ccff_tail; - wire [0:3] mux_tree_tapbuf_size8_0_sram; - wire [0:3] mux_tree_tapbuf_size8_1_sram; - wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail; - wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail; - wire [0:3] mux_tree_tapbuf_size9_0_sram; - wire [0:3] mux_tree_tapbuf_size9_1_sram; - wire [0:3] mux_tree_tapbuf_size9_2_sram; - wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail; - wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail; - wire [0:0] mux_tree_tapbuf_size9_mem_2_ccff_tail; - assign chany_bottom_out[18] = chanx_right_in[0]; - assign chany_bottom_out[17] = chanx_right_in[1]; - assign chanx_left_out[3] = chanx_right_in[2]; - assign chany_bottom_out[16] = chanx_right_in[3]; - assign chanx_left_out[5] = chanx_right_in[4]; - assign chanx_left_out[6] = chanx_right_in[5]; - assign chanx_left_out[7] = chanx_right_in[6]; - assign chany_bottom_out[15] = chanx_right_in[7]; - assign chanx_left_out[9] = chanx_right_in[8]; - assign chanx_left_out[10] = chanx_right_in[9]; - assign chanx_left_out[11] = chanx_right_in[10]; - assign chany_bottom_out[14] = chanx_right_in[11]; - assign chanx_left_out[13] = chanx_right_in[12]; - assign chanx_left_out[14] = chanx_right_in[13]; - assign chanx_left_out[15] = chanx_right_in[14]; - assign chanx_left_out[17] = chanx_right_in[16]; - assign chanx_left_out[18] = chanx_right_in[17]; - assign chanx_left_out[19] = chanx_right_in[18]; - assign chany_bottom_out[19] = chanx_left_in[0]; - assign chanx_right_out[3] = chanx_left_in[2]; - assign chanx_right_out[5] = chanx_left_in[4]; - assign chanx_right_out[6] = chanx_left_in[5]; - assign chanx_right_out[7] = chanx_left_in[6]; - assign chanx_right_out[9] = chanx_left_in[8]; - assign chanx_right_out[10] = chanx_left_in[9]; - assign chanx_right_out[11] = chanx_left_in[10]; - assign chanx_right_out[13] = chanx_left_in[12]; - assign chanx_right_out[14] = chanx_left_in[13]; - assign chanx_right_out[15] = chanx_left_in[14]; - assign chanx_right_out[17] = chanx_left_in[16]; - assign chanx_right_out[18] = chanx_left_in[17]; - assign chanx_right_out[19] = chanx_left_in[18]; - assign SC_IN_TOP = SC_IN_BOT; - assign SC_OUT_TOP = SC_OUT_BOT; - - mux_tree_tapbuf_size10 - mux_right_track_0 - ( - .in({ right_top_grid_pin_1_[0], right_bottom_grid_pin_35_[0], right_bottom_grid_pin_37_[0], right_bottom_grid_pin_39_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[5], chany_bottom_in[12], chany_bottom_in[19], chanx_left_in[2], chanx_left_in[12] }), - .sram(mux_tree_tapbuf_size10_0_sram[0:3]), - .sram_inv(mux_right_track_0_undriven_sram_inv[0:3]), - .out(chanx_right_out[0]) - ); - - - mux_tree_tapbuf_size10_mem - mem_right_track_0 - ( - .prog_clk(prog_clk[0]), - .ccff_head(ccff_head[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_0_sram[0:3]) - ); - - - mux_tree_tapbuf_size9 - mux_right_track_2 - ( - .in({ right_bottom_grid_pin_34_[0], right_bottom_grid_pin_36_[0], right_bottom_grid_pin_38_[0], right_bottom_grid_pin_40_[0], chany_bottom_in[4], chany_bottom_in[11], chany_bottom_in[18], chanx_left_in[4], chanx_left_in[13] }), - .sram(mux_tree_tapbuf_size9_0_sram[0:3]), - .sram_inv(mux_right_track_2_undriven_sram_inv[0:3]), - .out(chanx_right_out[1]) - ); - - - mux_tree_tapbuf_size9 - mux_left_track_1 - ( - .in({ chanx_right_in[2], chanx_right_in[12], chany_bottom_in[6], chany_bottom_in[13], left_top_grid_pin_1_[0], left_bottom_grid_pin_35_[0], left_bottom_grid_pin_37_[0], left_bottom_grid_pin_39_[0], left_bottom_grid_pin_41_[0] }), - .sram(mux_tree_tapbuf_size9_1_sram[0:3]), - .sram_inv(mux_left_track_1_undriven_sram_inv[0:3]), - .out(chanx_left_out[0]) - ); - - - mux_tree_tapbuf_size9 - mux_left_track_3 - ( - .in({ chanx_right_in[4], chanx_right_in[13], chany_bottom_in[0], chany_bottom_in[7], chany_bottom_in[14], left_bottom_grid_pin_34_[0], left_bottom_grid_pin_36_[0], left_bottom_grid_pin_38_[0], left_bottom_grid_pin_40_[0] }), - .sram(mux_tree_tapbuf_size9_2_sram[0:3]), - .sram_inv(mux_left_track_3_undriven_sram_inv[0:3]), - .out(chanx_left_out[1]) - ); - - - mux_tree_tapbuf_size9_mem - mem_right_track_2 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size9_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size9_0_sram[0:3]) - ); - - - mux_tree_tapbuf_size9_mem - mem_left_track_1 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size9_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size9_1_sram[0:3]) - ); - - - mux_tree_tapbuf_size9_mem - mem_left_track_3 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size9_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size9_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size9_2_sram[0:3]) - ); - - - mux_tree_tapbuf_size14 - mux_right_track_4 - ( - .in({ right_top_grid_pin_1_[0], right_bottom_grid_pin_34_[0], right_bottom_grid_pin_35_[0], right_bottom_grid_pin_36_[0], right_bottom_grid_pin_37_[0], right_bottom_grid_pin_38_[0], right_bottom_grid_pin_39_[0], right_bottom_grid_pin_40_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[3], chany_bottom_in[10], chany_bottom_in[17], chanx_left_in[5], chanx_left_in[14] }), - .sram(mux_tree_tapbuf_size14_0_sram[0:3]), - .sram_inv(mux_right_track_4_undriven_sram_inv[0:3]), - .out(chanx_right_out[2]) - ); - - - mux_tree_tapbuf_size14 - mux_left_track_5 - ( - .in({ chanx_right_in[5], chanx_right_in[14], chany_bottom_in[1], chany_bottom_in[8], chany_bottom_in[15], left_top_grid_pin_1_[0], left_bottom_grid_pin_34_[0], left_bottom_grid_pin_35_[0], left_bottom_grid_pin_36_[0], left_bottom_grid_pin_37_[0], left_bottom_grid_pin_38_[0], left_bottom_grid_pin_39_[0], left_bottom_grid_pin_40_[0], left_bottom_grid_pin_41_[0] }), - .sram(mux_tree_tapbuf_size14_1_sram[0:3]), - .sram_inv(mux_left_track_5_undriven_sram_inv[0:3]), - .out(chanx_left_out[2]) - ); - - - mux_tree_tapbuf_size14_mem - mem_right_track_4 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size9_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size14_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size14_0_sram[0:3]) - ); - - - mux_tree_tapbuf_size14_mem - mem_left_track_5 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size9_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size14_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size14_1_sram[0:3]) - ); - - - mux_tree_tapbuf_size8 - mux_right_track_8 - ( - .in({ right_top_grid_pin_1_[0], right_bottom_grid_pin_37_[0], right_bottom_grid_pin_41_[0], chany_bottom_in[2], chany_bottom_in[9], chany_bottom_in[16], chanx_left_in[6], chanx_left_in[16] }), - .sram(mux_tree_tapbuf_size8_0_sram[0:3]), - .sram_inv(mux_right_track_8_undriven_sram_inv[0:3]), - .out(chanx_right_out[4]) - ); - - - mux_tree_tapbuf_size8 - mux_left_track_9 - ( - .in({ chanx_right_in[6], chanx_right_in[16], chany_bottom_in[2], chany_bottom_in[9], chany_bottom_in[16], left_top_grid_pin_1_[0], left_bottom_grid_pin_37_[0], left_bottom_grid_pin_41_[0] }), - .sram(mux_tree_tapbuf_size8_1_sram[0:3]), - .sram_inv(mux_left_track_9_undriven_sram_inv[0:3]), - .out(chanx_left_out[4]) - ); - - - mux_tree_tapbuf_size8_mem - mem_right_track_8 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size14_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_0_sram[0:3]) - ); - - - mux_tree_tapbuf_size8_mem - mem_left_track_9 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size14_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_1_sram[0:3]) - ); - - - mux_tree_tapbuf_size7 - mux_right_track_16 - ( - .in({ right_bottom_grid_pin_34_[0], right_bottom_grid_pin_38_[0], chany_bottom_in[1], chany_bottom_in[8], chany_bottom_in[15], chanx_left_in[8], chanx_left_in[17] }), - .sram(mux_tree_tapbuf_size7_0_sram[0:2]), - .sram_inv(mux_right_track_16_undriven_sram_inv[0:2]), - .out(chanx_right_out[8]) - ); - - - mux_tree_tapbuf_size7 - mux_right_track_24 - ( - .in({ right_bottom_grid_pin_35_[0], right_bottom_grid_pin_39_[0], chany_bottom_in[0], chany_bottom_in[7], chany_bottom_in[14], chanx_left_in[9], chanx_left_in[18] }), - .sram(mux_tree_tapbuf_size7_1_sram[0:2]), - .sram_inv(mux_right_track_24_undriven_sram_inv[0:2]), - .out(chanx_right_out[12]) - ); - - - mux_tree_tapbuf_size7 - mux_bottom_track_1 - ( - .in({ chanx_right_in[2], bottom_left_grid_pin_42_[0], bottom_left_grid_pin_44_[0], bottom_left_grid_pin_46_[0], bottom_left_grid_pin_48_[0], chanx_left_in[1:2] }), - .sram(mux_tree_tapbuf_size7_2_sram[0:2]), - .sram_inv(mux_bottom_track_1_undriven_sram_inv[0:2]), - .out(chany_bottom_out[0]) - ); - - - mux_tree_tapbuf_size7 - mux_bottom_track_3 - ( - .in({ chanx_right_in[4], bottom_left_grid_pin_43_[0], bottom_left_grid_pin_45_[0], bottom_left_grid_pin_47_[0], bottom_left_grid_pin_49_[0], chanx_left_in[3:4] }), - .sram(mux_tree_tapbuf_size7_3_sram[0:2]), - .sram_inv(mux_bottom_track_3_undriven_sram_inv[0:2]), - .out(chany_bottom_out[1]) - ); - - - mux_tree_tapbuf_size7 - mux_bottom_track_5 - ( - .in({ chanx_right_in[5], bottom_left_grid_pin_42_[0], bottom_left_grid_pin_44_[0], bottom_left_grid_pin_46_[0], bottom_left_grid_pin_48_[0], chanx_left_in[5], chanx_left_in[7] }), - .sram(mux_tree_tapbuf_size7_4_sram[0:2]), - .sram_inv(mux_bottom_track_5_undriven_sram_inv[0:2]), - .out(chany_bottom_out[2]) - ); - - - mux_tree_tapbuf_size7 - mux_bottom_track_7 - ( - .in({ chanx_right_in[6], bottom_left_grid_pin_43_[0], bottom_left_grid_pin_45_[0], bottom_left_grid_pin_47_[0], bottom_left_grid_pin_49_[0], chanx_left_in[6], chanx_left_in[11] }), - .sram(mux_tree_tapbuf_size7_5_sram[0:2]), - .sram_inv(mux_bottom_track_7_undriven_sram_inv[0:2]), - .out(chany_bottom_out[3]) - ); - - - mux_tree_tapbuf_size7 - mux_left_track_17 - ( - .in({ chanx_right_in[8], chanx_right_in[17], chany_bottom_in[3], chany_bottom_in[10], chany_bottom_in[17], left_bottom_grid_pin_34_[0], left_bottom_grid_pin_38_[0] }), - .sram(mux_tree_tapbuf_size7_6_sram[0:2]), - .sram_inv(mux_left_track_17_undriven_sram_inv[0:2]), - .out(chanx_left_out[8]) - ); - - - mux_tree_tapbuf_size7 - mux_left_track_25 - ( - .in({ chanx_right_in[9], chanx_right_in[18], chany_bottom_in[4], chany_bottom_in[11], chany_bottom_in[18], left_bottom_grid_pin_35_[0], left_bottom_grid_pin_39_[0] }), - .sram(mux_tree_tapbuf_size7_7_sram[0:2]), - .sram_inv(mux_left_track_25_undriven_sram_inv[0:2]), - .out(chanx_left_out[12]) - ); - - - mux_tree_tapbuf_size7_mem - mem_right_track_16 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_0_sram[0:2]) - ); - - - mux_tree_tapbuf_size7_mem - mem_right_track_24 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_1_sram[0:2]) - ); - - - mux_tree_tapbuf_size7_mem - mem_bottom_track_1 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_2_sram[0:2]) - ); - - - mux_tree_tapbuf_size7_mem - mem_bottom_track_3 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size7_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_3_sram[0:2]) - ); - - - mux_tree_tapbuf_size7_mem - mem_bottom_track_5 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size7_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size7_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_4_sram[0:2]) - ); - - - mux_tree_tapbuf_size7_mem - mem_bottom_track_7 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size7_mem_4_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size7_mem_5_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_5_sram[0:2]) - ); - - - mux_tree_tapbuf_size7_mem - mem_left_track_17 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size7_mem_6_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_6_sram[0:2]) - ); - - - mux_tree_tapbuf_size7_mem - mem_left_track_25 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size7_mem_6_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size7_mem_7_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_7_sram[0:2]) - ); - - - mux_tree_tapbuf_size5 - mux_right_track_32 - ( - .in({ right_bottom_grid_pin_36_[0], right_bottom_grid_pin_40_[0], chany_bottom_in[6], chany_bottom_in[13], chanx_left_in[10] }), - .sram(mux_tree_tapbuf_size5_0_sram[0:2]), - .sram_inv(mux_right_track_32_undriven_sram_inv[0:2]), - .out(chanx_right_out[16]) - ); - - - mux_tree_tapbuf_size5_mem - mem_right_track_32 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size5_0_sram[0:2]) - ); - - - mux_tree_tapbuf_size4 - mux_bottom_track_9 - ( - .in({ chanx_right_in[8], bottom_left_grid_pin_42_[0], chanx_left_in[8], chanx_left_in[15] }), - .sram(mux_tree_tapbuf_size4_0_sram[0:2]), - .sram_inv(mux_bottom_track_9_undriven_sram_inv[0:2]), - .out(chany_bottom_out[4]) - ); - - - mux_tree_tapbuf_size4 - mux_bottom_track_11 - ( - .in({ chanx_right_in[9], bottom_left_grid_pin_43_[0], chanx_left_in[9], chanx_left_in[19] }), - .sram(mux_tree_tapbuf_size4_1_sram[0:2]), - .sram_inv(mux_bottom_track_11_undriven_sram_inv[0:2]), - .out(chany_bottom_out[5]) - ); - - - mux_tree_tapbuf_size4 - mux_bottom_track_25 - ( - .in({ chanx_right_in[18:19], bottom_left_grid_pin_42_[0], chanx_left_in[18] }), - .sram(mux_tree_tapbuf_size4_2_sram[0:2]), - .sram_inv(mux_bottom_track_25_undriven_sram_inv[0:2]), - .out(chany_bottom_out[12]) - ); - - - mux_tree_tapbuf_size4_mem - mem_bottom_track_9 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size7_mem_5_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size4_0_sram[0:2]) - ); - - - mux_tree_tapbuf_size4_mem - mem_bottom_track_11 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size4_1_sram[0:2]) - ); - - - mux_tree_tapbuf_size4_mem - mem_bottom_track_25 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size4_2_sram[0:2]) - ); - - - mux_tree_tapbuf_size3 - mux_bottom_track_13 - ( - .in({ chanx_right_in[10], bottom_left_grid_pin_44_[0], chanx_left_in[10] }), - .sram(mux_tree_tapbuf_size3_0_sram[0:1]), - .sram_inv(mux_bottom_track_13_undriven_sram_inv[0:1]), - .out(chany_bottom_out[6]) - ); - - - mux_tree_tapbuf_size3 - mux_bottom_track_15 - ( - .in({ chanx_right_in[12], bottom_left_grid_pin_45_[0], chanx_left_in[12] }), - .sram(mux_tree_tapbuf_size3_1_sram[0:1]), - .sram_inv(mux_bottom_track_15_undriven_sram_inv[0:1]), - .out(chany_bottom_out[7]) - ); - - - mux_tree_tapbuf_size3 - mux_bottom_track_17 - ( - .in({ chanx_right_in[13], bottom_left_grid_pin_46_[0], chanx_left_in[13] }), - .sram(mux_tree_tapbuf_size3_2_sram[0:1]), - .sram_inv(mux_bottom_track_17_undriven_sram_inv[0:1]), - .out(chany_bottom_out[8]) - ); - - - mux_tree_tapbuf_size3 - mux_bottom_track_19 - ( - .in({ chanx_right_in[14], bottom_left_grid_pin_47_[0], chanx_left_in[14] }), - .sram(mux_tree_tapbuf_size3_3_sram[0:1]), - .sram_inv(mux_bottom_track_19_undriven_sram_inv[0:1]), - .out(chany_bottom_out[9]) - ); - - - mux_tree_tapbuf_size3 - mux_bottom_track_21 - ( - .in({ chanx_right_in[16], bottom_left_grid_pin_48_[0], chanx_left_in[16] }), - .sram(mux_tree_tapbuf_size3_4_sram[0:1]), - .sram_inv(mux_bottom_track_21_undriven_sram_inv[0:1]), - .out(chany_bottom_out[10]) - ); - - - mux_tree_tapbuf_size3 - mux_bottom_track_23 - ( - .in({ chanx_right_in[17], bottom_left_grid_pin_49_[0], chanx_left_in[17] }), - .sram(mux_tree_tapbuf_size3_5_sram[0:1]), - .sram_inv(mux_bottom_track_23_undriven_sram_inv[0:1]), - .out(chany_bottom_out[11]) - ); - - - mux_tree_tapbuf_size3_mem - mem_bottom_track_13 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_0_sram[0:1]) - ); - - - mux_tree_tapbuf_size3_mem - mem_bottom_track_15 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_1_sram[0:1]) - ); - - - mux_tree_tapbuf_size3_mem - mem_bottom_track_17 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_2_sram[0:1]) - ); - - - mux_tree_tapbuf_size3_mem - mem_bottom_track_19 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_3_sram[0:1]) - ); - - - mux_tree_tapbuf_size3_mem - mem_bottom_track_21 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_4_sram[0:1]) - ); - - - mux_tree_tapbuf_size3_mem - mem_bottom_track_23 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_5_sram[0:1]) - ); - - - mux_tree_tapbuf_size2 - mux_bottom_track_27 - ( - .in({ chanx_right_in[15], bottom_left_grid_pin_43_[0] }), - .sram(mux_tree_tapbuf_size2_0_sram[0:1]), - .sram_inv(mux_bottom_track_27_undriven_sram_inv[0:1]), - .out(chany_bottom_out[13]) - ); - - - mux_tree_tapbuf_size2_mem - mem_bottom_track_27 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_0_sram[0:1]) - ); - - - mux_tree_tapbuf_size6 - mux_left_track_33 - ( - .in({ chanx_right_in[10], chany_bottom_in[5], chany_bottom_in[12], chany_bottom_in[19], left_bottom_grid_pin_36_[0], left_bottom_grid_pin_40_[0] }), - .sram(mux_tree_tapbuf_size6_0_sram[0:2]), - .sram_inv(mux_left_track_33_undriven_sram_inv[0:2]), - .out(chanx_left_out[16]) - ); - - - mux_tree_tapbuf_size6_mem - mem_left_track_33 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size7_mem_7_ccff_tail[0]), - .ccff_tail(ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_0_sram[0:2]) - ); - - -endmodule - diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_2__0_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_2__0_.v deleted file mode 100644 index c8a7319..0000000 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_2__0_.v +++ /dev/null @@ -1,729 +0,0 @@ - - -module sb_2__0_ -( prog_clk, chany_top_in, top_left_grid_pin_42_, top_left_grid_pin_43_, top_left_grid_pin_44_, top_left_grid_pin_45_, top_left_grid_pin_46_, top_left_grid_pin_47_, top_left_grid_pin_48_, top_left_grid_pin_49_, top_right_grid_pin_1_, chanx_left_in, left_bottom_grid_pin_1_, left_bottom_grid_pin_3_, left_bottom_grid_pin_5_, left_bottom_grid_pin_7_, left_bottom_grid_pin_9_, left_bottom_grid_pin_11_, ccff_head, chany_top_out, chanx_left_out, ccff_tail ); - input [0:0] prog_clk; - input [0:19] chany_top_in; - input [0:0] top_left_grid_pin_42_; - input [0:0] top_left_grid_pin_43_; - input [0:0] top_left_grid_pin_44_; - input [0:0] top_left_grid_pin_45_; - input [0:0] top_left_grid_pin_46_; - input [0:0] top_left_grid_pin_47_; - input [0:0] top_left_grid_pin_48_; - input [0:0] top_left_grid_pin_49_; - input [0:0] top_right_grid_pin_1_; - input [0:19] chanx_left_in; - input [0:0] left_bottom_grid_pin_1_; - input [0:0] left_bottom_grid_pin_3_; - input [0:0] left_bottom_grid_pin_5_; - input [0:0] left_bottom_grid_pin_7_; - input [0:0] left_bottom_grid_pin_9_; - input [0:0] left_bottom_grid_pin_11_; - input [0:0] ccff_head; - output [0:19] chany_top_out; - output [0:19] chanx_left_out; - output [0:0] ccff_tail; - - wire [0:1] mux_left_track_11_undriven_sram_inv; - wire [0:1] mux_left_track_13_undriven_sram_inv; - wire [0:1] mux_left_track_15_undriven_sram_inv; - wire [0:1] mux_left_track_17_undriven_sram_inv; - wire [0:1] mux_left_track_19_undriven_sram_inv; - wire [0:2] mux_left_track_1_undriven_sram_inv; - wire [0:1] mux_left_track_25_undriven_sram_inv; - wire [0:1] mux_left_track_27_undriven_sram_inv; - wire [0:1] mux_left_track_29_undriven_sram_inv; - wire [0:1] mux_left_track_31_undriven_sram_inv; - wire [0:1] mux_left_track_33_undriven_sram_inv; - wire [0:1] mux_left_track_35_undriven_sram_inv; - wire [0:2] mux_left_track_3_undriven_sram_inv; - wire [0:2] mux_left_track_5_undriven_sram_inv; - wire [0:2] mux_left_track_7_undriven_sram_inv; - wire [0:1] mux_left_track_9_undriven_sram_inv; - wire [0:2] mux_top_track_0_undriven_sram_inv; - wire [0:1] mux_top_track_10_undriven_sram_inv; - wire [0:1] mux_top_track_12_undriven_sram_inv; - wire [0:1] mux_top_track_14_undriven_sram_inv; - wire [0:1] mux_top_track_16_undriven_sram_inv; - wire [0:1] mux_top_track_18_undriven_sram_inv; - wire [0:1] mux_top_track_20_undriven_sram_inv; - wire [0:1] mux_top_track_22_undriven_sram_inv; - wire [0:1] mux_top_track_24_undriven_sram_inv; - wire [0:1] mux_top_track_26_undriven_sram_inv; - wire [0:2] mux_top_track_2_undriven_sram_inv; - wire [0:2] mux_top_track_4_undriven_sram_inv; - wire [0:2] mux_top_track_6_undriven_sram_inv; - wire [0:1] mux_top_track_8_undriven_sram_inv; - wire [0:1] mux_tree_tapbuf_size2_0_sram; - wire [0:1] mux_tree_tapbuf_size2_10_sram; - wire [0:1] mux_tree_tapbuf_size2_11_sram; - wire [0:1] mux_tree_tapbuf_size2_12_sram; - wire [0:1] mux_tree_tapbuf_size2_13_sram; - wire [0:1] mux_tree_tapbuf_size2_14_sram; - wire [0:1] mux_tree_tapbuf_size2_15_sram; - wire [0:1] mux_tree_tapbuf_size2_16_sram; - wire [0:1] mux_tree_tapbuf_size2_17_sram; - wire [0:1] mux_tree_tapbuf_size2_18_sram; - wire [0:1] mux_tree_tapbuf_size2_19_sram; - wire [0:1] mux_tree_tapbuf_size2_1_sram; - wire [0:1] mux_tree_tapbuf_size2_2_sram; - wire [0:1] mux_tree_tapbuf_size2_3_sram; - wire [0:1] mux_tree_tapbuf_size2_4_sram; - wire [0:1] mux_tree_tapbuf_size2_5_sram; - wire [0:1] mux_tree_tapbuf_size2_6_sram; - wire [0:1] mux_tree_tapbuf_size2_7_sram; - wire [0:1] mux_tree_tapbuf_size2_8_sram; - wire [0:1] mux_tree_tapbuf_size2_9_sram; - wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail; - wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail; - wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail; - wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail; - wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail; - wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail; - wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail; - wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail; - wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail; - wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail; - wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail; - wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail; - wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail; - wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail; - wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail; - wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail; - wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail; - wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail; - wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail; - wire [0:1] mux_tree_tapbuf_size3_0_sram; - wire [0:1] mux_tree_tapbuf_size3_1_sram; - wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail; - wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail; - wire [0:2] mux_tree_tapbuf_size4_0_sram; - wire [0:2] mux_tree_tapbuf_size4_1_sram; - wire [0:2] mux_tree_tapbuf_size4_2_sram; - wire [0:2] mux_tree_tapbuf_size4_3_sram; - wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail; - wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail; - wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail; - wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail; - wire [0:2] mux_tree_tapbuf_size5_0_sram; - wire [0:2] mux_tree_tapbuf_size5_1_sram; - wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail; - wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail; - wire [0:2] mux_tree_tapbuf_size6_0_sram; - wire [0:2] mux_tree_tapbuf_size6_1_sram; - wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail; - wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail; - assign chanx_left_out[19] = chany_top_in[1]; - assign chanx_left_out[18] = chany_top_in[2]; - assign chanx_left_out[11] = chany_top_in[9]; - assign chanx_left_out[10] = chany_top_in[10]; - assign chany_top_out[19] = chanx_left_in[1]; - assign chany_top_out[18] = chanx_left_in[2]; - assign chany_top_out[17] = chanx_left_in[3]; - assign chany_top_out[16] = chanx_left_in[4]; - assign chany_top_out[15] = chanx_left_in[5]; - assign chany_top_out[14] = chanx_left_in[6]; - - mux_tree_tapbuf_size6 - mux_top_track_0 - ( - .in({ top_left_grid_pin_42_[0], top_left_grid_pin_44_[0], top_left_grid_pin_46_[0], top_left_grid_pin_48_[0], top_right_grid_pin_1_[0], chanx_left_in[0] }), - .sram(mux_tree_tapbuf_size6_0_sram[0:2]), - .sram_inv(mux_top_track_0_undriven_sram_inv[0:2]), - .out(chany_top_out[0]) - ); - - - mux_tree_tapbuf_size6 - mux_top_track_4 - ( - .in({ top_left_grid_pin_42_[0], top_left_grid_pin_44_[0], top_left_grid_pin_46_[0], top_left_grid_pin_48_[0], top_right_grid_pin_1_[0], chanx_left_in[18] }), - .sram(mux_tree_tapbuf_size6_1_sram[0:2]), - .sram_inv(mux_top_track_4_undriven_sram_inv[0:2]), - .out(chany_top_out[2]) - ); - - - mux_tree_tapbuf_size6_mem - mem_top_track_0 - ( - .prog_clk(prog_clk[0]), - .ccff_head(ccff_head[0]), - .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_0_sram[0:2]) - ); - - - mux_tree_tapbuf_size6_mem - mem_top_track_4 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_1_sram[0:2]) - ); - - - mux_tree_tapbuf_size5 - mux_top_track_2 - ( - .in({ top_left_grid_pin_43_[0], top_left_grid_pin_45_[0], top_left_grid_pin_47_[0], top_left_grid_pin_49_[0], chanx_left_in[19] }), - .sram(mux_tree_tapbuf_size5_0_sram[0:2]), - .sram_inv(mux_top_track_2_undriven_sram_inv[0:2]), - .out(chany_top_out[1]) - ); - - - mux_tree_tapbuf_size5 - mux_top_track_6 - ( - .in({ top_left_grid_pin_43_[0], top_left_grid_pin_45_[0], top_left_grid_pin_47_[0], top_left_grid_pin_49_[0], chanx_left_in[17] }), - .sram(mux_tree_tapbuf_size5_1_sram[0:2]), - .sram_inv(mux_top_track_6_undriven_sram_inv[0:2]), - .out(chany_top_out[3]) - ); - - - mux_tree_tapbuf_size5_mem - mem_top_track_2 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size5_0_sram[0:2]) - ); - - - mux_tree_tapbuf_size5_mem - mem_top_track_6 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size5_1_sram[0:2]) - ); - - - mux_tree_tapbuf_size3 - mux_top_track_8 - ( - .in({ top_left_grid_pin_42_[0], top_right_grid_pin_1_[0], chanx_left_in[16] }), - .sram(mux_tree_tapbuf_size3_0_sram[0:1]), - .sram_inv(mux_top_track_8_undriven_sram_inv[0:1]), - .out(chany_top_out[4]) - ); - - - mux_tree_tapbuf_size3 - mux_top_track_24 - ( - .in({ top_left_grid_pin_42_[0], top_right_grid_pin_1_[0], chanx_left_in[8] }), - .sram(mux_tree_tapbuf_size3_1_sram[0:1]), - .sram_inv(mux_top_track_24_undriven_sram_inv[0:1]), - .out(chany_top_out[12]) - ); - - - mux_tree_tapbuf_size3_mem - mem_top_track_8 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_0_sram[0:1]) - ); - - - mux_tree_tapbuf_size3_mem - mem_top_track_24 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_1_sram[0:1]) - ); - - - mux_tree_tapbuf_size2 - mux_top_track_10 - ( - .in({ top_left_grid_pin_43_[0], chanx_left_in[15] }), - .sram(mux_tree_tapbuf_size2_0_sram[0:1]), - .sram_inv(mux_top_track_10_undriven_sram_inv[0:1]), - .out(chany_top_out[5]) - ); - - - mux_tree_tapbuf_size2 - mux_top_track_12 - ( - .in({ top_left_grid_pin_44_[0], chanx_left_in[14] }), - .sram(mux_tree_tapbuf_size2_1_sram[0:1]), - .sram_inv(mux_top_track_12_undriven_sram_inv[0:1]), - .out(chany_top_out[6]) - ); - - - mux_tree_tapbuf_size2 - mux_top_track_14 - ( - .in({ top_left_grid_pin_45_[0], chanx_left_in[13] }), - .sram(mux_tree_tapbuf_size2_2_sram[0:1]), - .sram_inv(mux_top_track_14_undriven_sram_inv[0:1]), - .out(chany_top_out[7]) - ); - - - mux_tree_tapbuf_size2 - mux_top_track_16 - ( - .in({ top_left_grid_pin_46_[0], chanx_left_in[12] }), - .sram(mux_tree_tapbuf_size2_3_sram[0:1]), - .sram_inv(mux_top_track_16_undriven_sram_inv[0:1]), - .out(chany_top_out[8]) - ); - - - mux_tree_tapbuf_size2 - mux_top_track_18 - ( - .in({ top_left_grid_pin_47_[0], chanx_left_in[11] }), - .sram(mux_tree_tapbuf_size2_4_sram[0:1]), - .sram_inv(mux_top_track_18_undriven_sram_inv[0:1]), - .out(chany_top_out[9]) - ); - - - mux_tree_tapbuf_size2 - mux_top_track_20 - ( - .in({ top_left_grid_pin_48_[0], chanx_left_in[10] }), - .sram(mux_tree_tapbuf_size2_5_sram[0:1]), - .sram_inv(mux_top_track_20_undriven_sram_inv[0:1]), - .out(chany_top_out[10]) - ); - - - mux_tree_tapbuf_size2 - mux_top_track_22 - ( - .in({ top_left_grid_pin_49_[0], chanx_left_in[9] }), - .sram(mux_tree_tapbuf_size2_6_sram[0:1]), - .sram_inv(mux_top_track_22_undriven_sram_inv[0:1]), - .out(chany_top_out[11]) - ); - - - mux_tree_tapbuf_size2 - mux_top_track_26 - ( - .in({ top_left_grid_pin_43_[0], chanx_left_in[7] }), - .sram(mux_tree_tapbuf_size2_7_sram[0:1]), - .sram_inv(mux_top_track_26_undriven_sram_inv[0:1]), - .out(chany_top_out[13]) - ); - - - mux_tree_tapbuf_size2 - mux_left_track_9 - ( - .in({ chany_top_in[16], left_bottom_grid_pin_1_[0] }), - .sram(mux_tree_tapbuf_size2_8_sram[0:1]), - .sram_inv(mux_left_track_9_undriven_sram_inv[0:1]), - .out(chanx_left_out[4]) - ); - - - mux_tree_tapbuf_size2 - mux_left_track_11 - ( - .in({ chany_top_in[15], left_bottom_grid_pin_3_[0] }), - .sram(mux_tree_tapbuf_size2_9_sram[0:1]), - .sram_inv(mux_left_track_11_undriven_sram_inv[0:1]), - .out(chanx_left_out[5]) - ); - - - mux_tree_tapbuf_size2 - mux_left_track_13 - ( - .in({ chany_top_in[14], left_bottom_grid_pin_5_[0] }), - .sram(mux_tree_tapbuf_size2_10_sram[0:1]), - .sram_inv(mux_left_track_13_undriven_sram_inv[0:1]), - .out(chanx_left_out[6]) - ); - - - mux_tree_tapbuf_size2 - mux_left_track_15 - ( - .in({ chany_top_in[13], left_bottom_grid_pin_7_[0] }), - .sram(mux_tree_tapbuf_size2_11_sram[0:1]), - .sram_inv(mux_left_track_15_undriven_sram_inv[0:1]), - .out(chanx_left_out[7]) - ); - - - mux_tree_tapbuf_size2 - mux_left_track_17 - ( - .in({ chany_top_in[12], left_bottom_grid_pin_9_[0] }), - .sram(mux_tree_tapbuf_size2_12_sram[0:1]), - .sram_inv(mux_left_track_17_undriven_sram_inv[0:1]), - .out(chanx_left_out[8]) - ); - - - mux_tree_tapbuf_size2 - mux_left_track_19 - ( - .in({ chany_top_in[11], left_bottom_grid_pin_11_[0] }), - .sram(mux_tree_tapbuf_size2_13_sram[0:1]), - .sram_inv(mux_left_track_19_undriven_sram_inv[0:1]), - .out(chanx_left_out[9]) - ); - - - mux_tree_tapbuf_size2 - mux_left_track_25 - ( - .in({ chany_top_in[8], left_bottom_grid_pin_1_[0] }), - .sram(mux_tree_tapbuf_size2_14_sram[0:1]), - .sram_inv(mux_left_track_25_undriven_sram_inv[0:1]), - .out(chanx_left_out[12]) - ); - - - mux_tree_tapbuf_size2 - mux_left_track_27 - ( - .in({ chany_top_in[7], left_bottom_grid_pin_3_[0] }), - .sram(mux_tree_tapbuf_size2_15_sram[0:1]), - .sram_inv(mux_left_track_27_undriven_sram_inv[0:1]), - .out(chanx_left_out[13]) - ); - - - mux_tree_tapbuf_size2 - mux_left_track_29 - ( - .in({ chany_top_in[6], left_bottom_grid_pin_5_[0] }), - .sram(mux_tree_tapbuf_size2_16_sram[0:1]), - .sram_inv(mux_left_track_29_undriven_sram_inv[0:1]), - .out(chanx_left_out[14]) - ); - - - mux_tree_tapbuf_size2 - mux_left_track_31 - ( - .in({ chany_top_in[5], left_bottom_grid_pin_7_[0] }), - .sram(mux_tree_tapbuf_size2_17_sram[0:1]), - .sram_inv(mux_left_track_31_undriven_sram_inv[0:1]), - .out(chanx_left_out[15]) - ); - - - mux_tree_tapbuf_size2 - mux_left_track_33 - ( - .in({ chany_top_in[4], left_bottom_grid_pin_9_[0] }), - .sram(mux_tree_tapbuf_size2_18_sram[0:1]), - .sram_inv(mux_left_track_33_undriven_sram_inv[0:1]), - .out(chanx_left_out[16]) - ); - - - mux_tree_tapbuf_size2 - mux_left_track_35 - ( - .in({ chany_top_in[3], left_bottom_grid_pin_11_[0] }), - .sram(mux_tree_tapbuf_size2_19_sram[0:1]), - .sram_inv(mux_left_track_35_undriven_sram_inv[0:1]), - .out(chanx_left_out[17]) - ); - - - mux_tree_tapbuf_size2_mem - mem_top_track_10 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_0_sram[0:1]) - ); - - - mux_tree_tapbuf_size2_mem - mem_top_track_12 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_1_sram[0:1]) - ); - - - mux_tree_tapbuf_size2_mem - mem_top_track_14 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_2_sram[0:1]) - ); - - - mux_tree_tapbuf_size2_mem - mem_top_track_16 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_3_sram[0:1]) - ); - - - mux_tree_tapbuf_size2_mem - mem_top_track_18 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_4_sram[0:1]) - ); - - - mux_tree_tapbuf_size2_mem - mem_top_track_20 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_5_sram[0:1]) - ); - - - mux_tree_tapbuf_size2_mem - mem_top_track_22 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_6_sram[0:1]) - ); - - - mux_tree_tapbuf_size2_mem - mem_top_track_26 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_7_sram[0:1]) - ); - - - mux_tree_tapbuf_size2_mem - mem_left_track_9 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_8_sram[0:1]) - ); - - - mux_tree_tapbuf_size2_mem - mem_left_track_11 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_9_sram[0:1]) - ); - - - mux_tree_tapbuf_size2_mem - mem_left_track_13 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_10_sram[0:1]) - ); - - - mux_tree_tapbuf_size2_mem - mem_left_track_15 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_11_sram[0:1]) - ); - - - mux_tree_tapbuf_size2_mem - mem_left_track_17 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_12_sram[0:1]) - ); - - - mux_tree_tapbuf_size2_mem - mem_left_track_19 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_13_sram[0:1]) - ); - - - mux_tree_tapbuf_size2_mem - mem_left_track_25 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_14_sram[0:1]) - ); - - - mux_tree_tapbuf_size2_mem - mem_left_track_27 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_15_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_15_sram[0:1]) - ); - - - mux_tree_tapbuf_size2_mem - mem_left_track_29 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_15_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_16_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_16_sram[0:1]) - ); - - - mux_tree_tapbuf_size2_mem - mem_left_track_31 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_16_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_17_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_17_sram[0:1]) - ); - - - mux_tree_tapbuf_size2_mem - mem_left_track_33 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_17_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_18_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_18_sram[0:1]) - ); - - - mux_tree_tapbuf_size2_mem - mem_left_track_35 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_18_ccff_tail[0]), - .ccff_tail(ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_19_sram[0:1]) - ); - - - mux_tree_tapbuf_size4 - mux_left_track_1 - ( - .in({ chany_top_in[0], left_bottom_grid_pin_1_[0], left_bottom_grid_pin_5_[0], left_bottom_grid_pin_9_[0] }), - .sram(mux_tree_tapbuf_size4_0_sram[0:2]), - .sram_inv(mux_left_track_1_undriven_sram_inv[0:2]), - .out(chanx_left_out[0]) - ); - - - mux_tree_tapbuf_size4 - mux_left_track_3 - ( - .in({ chany_top_in[19], left_bottom_grid_pin_3_[0], left_bottom_grid_pin_7_[0], left_bottom_grid_pin_11_[0] }), - .sram(mux_tree_tapbuf_size4_1_sram[0:2]), - .sram_inv(mux_left_track_3_undriven_sram_inv[0:2]), - .out(chanx_left_out[1]) - ); - - - mux_tree_tapbuf_size4 - mux_left_track_5 - ( - .in({ chany_top_in[18], left_bottom_grid_pin_1_[0], left_bottom_grid_pin_5_[0], left_bottom_grid_pin_9_[0] }), - .sram(mux_tree_tapbuf_size4_2_sram[0:2]), - .sram_inv(mux_left_track_5_undriven_sram_inv[0:2]), - .out(chanx_left_out[2]) - ); - - - mux_tree_tapbuf_size4 - mux_left_track_7 - ( - .in({ chany_top_in[17], left_bottom_grid_pin_3_[0], left_bottom_grid_pin_7_[0], left_bottom_grid_pin_11_[0] }), - .sram(mux_tree_tapbuf_size4_3_sram[0:2]), - .sram_inv(mux_left_track_7_undriven_sram_inv[0:2]), - .out(chanx_left_out[3]) - ); - - - mux_tree_tapbuf_size4_mem - mem_left_track_1 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size4_0_sram[0:2]) - ); - - - mux_tree_tapbuf_size4_mem - mem_left_track_3 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size4_1_sram[0:2]) - ); - - - mux_tree_tapbuf_size4_mem - mem_left_track_5 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size4_2_sram[0:2]) - ); - - - mux_tree_tapbuf_size4_mem - mem_left_track_7 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size4_3_sram[0:2]) - ); - - -endmodule - diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_2__1_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_2__1_.v deleted file mode 100644 index 2052030..0000000 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_2__1_.v +++ /dev/null @@ -1,828 +0,0 @@ - - -module sb_2__1_ -( prog_clk, chany_top_in, top_left_grid_pin_42_, top_left_grid_pin_43_, top_left_grid_pin_44_, top_left_grid_pin_45_, top_left_grid_pin_46_, top_left_grid_pin_47_, top_left_grid_pin_48_, top_left_grid_pin_49_, top_right_grid_pin_1_, chany_bottom_in, bottom_right_grid_pin_1_, bottom_left_grid_pin_42_, bottom_left_grid_pin_43_, bottom_left_grid_pin_44_, bottom_left_grid_pin_45_, bottom_left_grid_pin_46_, bottom_left_grid_pin_47_, bottom_left_grid_pin_48_, bottom_left_grid_pin_49_, chanx_left_in, left_bottom_grid_pin_34_, left_bottom_grid_pin_35_, left_bottom_grid_pin_36_, left_bottom_grid_pin_37_, left_bottom_grid_pin_38_, left_bottom_grid_pin_39_, left_bottom_grid_pin_40_, left_bottom_grid_pin_41_, ccff_head, chany_top_out, chany_bottom_out, chanx_left_out, ccff_tail ); - input [0:0] prog_clk; - input [0:19] chany_top_in; - input [0:0] top_left_grid_pin_42_; - input [0:0] top_left_grid_pin_43_; - input [0:0] top_left_grid_pin_44_; - input [0:0] top_left_grid_pin_45_; - input [0:0] top_left_grid_pin_46_; - input [0:0] top_left_grid_pin_47_; - input [0:0] top_left_grid_pin_48_; - input [0:0] top_left_grid_pin_49_; - input [0:0] top_right_grid_pin_1_; - input [0:19] chany_bottom_in; - input [0:0] bottom_right_grid_pin_1_; - input [0:0] bottom_left_grid_pin_42_; - input [0:0] bottom_left_grid_pin_43_; - input [0:0] bottom_left_grid_pin_44_; - input [0:0] bottom_left_grid_pin_45_; - input [0:0] bottom_left_grid_pin_46_; - input [0:0] bottom_left_grid_pin_47_; - input [0:0] bottom_left_grid_pin_48_; - input [0:0] bottom_left_grid_pin_49_; - input [0:19] chanx_left_in; - input [0:0] left_bottom_grid_pin_34_; - input [0:0] left_bottom_grid_pin_35_; - input [0:0] left_bottom_grid_pin_36_; - input [0:0] left_bottom_grid_pin_37_; - input [0:0] left_bottom_grid_pin_38_; - input [0:0] left_bottom_grid_pin_39_; - input [0:0] left_bottom_grid_pin_40_; - input [0:0] left_bottom_grid_pin_41_; - input [0:0] ccff_head; - output [0:19] chany_top_out; - output [0:19] chany_bottom_out; - output [0:19] chanx_left_out; - output [0:0] ccff_tail; - - wire [0:2] mux_bottom_track_17_undriven_sram_inv; - wire [0:3] mux_bottom_track_1_undriven_sram_inv; - wire [0:2] mux_bottom_track_25_undriven_sram_inv; - wire [0:2] mux_bottom_track_33_undriven_sram_inv; - wire [0:3] mux_bottom_track_3_undriven_sram_inv; - wire [0:3] mux_bottom_track_5_undriven_sram_inv; - wire [0:3] mux_bottom_track_9_undriven_sram_inv; - wire [0:2] mux_left_track_11_undriven_sram_inv; - wire [0:2] mux_left_track_13_undriven_sram_inv; - wire [0:2] mux_left_track_15_undriven_sram_inv; - wire [0:1] mux_left_track_17_undriven_sram_inv; - wire [0:1] mux_left_track_19_undriven_sram_inv; - wire [0:2] mux_left_track_1_undriven_sram_inv; - wire [0:1] mux_left_track_21_undriven_sram_inv; - wire [0:1] mux_left_track_23_undriven_sram_inv; - wire [0:1] mux_left_track_25_undriven_sram_inv; - wire [0:1] mux_left_track_29_undriven_sram_inv; - wire [0:1] mux_left_track_31_undriven_sram_inv; - wire [0:1] mux_left_track_33_undriven_sram_inv; - wire [0:1] mux_left_track_35_undriven_sram_inv; - wire [0:1] mux_left_track_37_undriven_sram_inv; - wire [0:1] mux_left_track_39_undriven_sram_inv; - wire [0:2] mux_left_track_3_undriven_sram_inv; - wire [0:2] mux_left_track_5_undriven_sram_inv; - wire [0:2] mux_left_track_7_undriven_sram_inv; - wire [0:2] mux_left_track_9_undriven_sram_inv; - wire [0:3] mux_top_track_0_undriven_sram_inv; - wire [0:2] mux_top_track_16_undriven_sram_inv; - wire [0:2] mux_top_track_24_undriven_sram_inv; - wire [0:3] mux_top_track_2_undriven_sram_inv; - wire [0:2] mux_top_track_32_undriven_sram_inv; - wire [0:3] mux_top_track_4_undriven_sram_inv; - wire [0:3] mux_top_track_8_undriven_sram_inv; - wire [0:3] mux_tree_tapbuf_size10_0_sram; - wire [0:3] mux_tree_tapbuf_size10_1_sram; - wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail; - wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail; - wire [0:3] mux_tree_tapbuf_size14_0_sram; - wire [0:3] mux_tree_tapbuf_size14_1_sram; - wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail; - wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail; - wire [0:1] mux_tree_tapbuf_size2_0_sram; - wire [0:1] mux_tree_tapbuf_size2_1_sram; - wire [0:1] mux_tree_tapbuf_size2_2_sram; - wire [0:1] mux_tree_tapbuf_size2_3_sram; - wire [0:1] mux_tree_tapbuf_size2_4_sram; - wire [0:1] mux_tree_tapbuf_size2_5_sram; - wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail; - wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail; - wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail; - wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail; - wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail; - wire [0:1] mux_tree_tapbuf_size3_0_sram; - wire [0:1] mux_tree_tapbuf_size3_1_sram; - wire [0:1] mux_tree_tapbuf_size3_2_sram; - wire [0:1] mux_tree_tapbuf_size3_3_sram; - wire [0:1] mux_tree_tapbuf_size3_4_sram; - wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail; - wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail; - wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail; - wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail; - wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail; - wire [0:2] mux_tree_tapbuf_size4_0_sram; - wire [0:2] mux_tree_tapbuf_size4_1_sram; - wire [0:2] mux_tree_tapbuf_size4_2_sram; - wire [0:2] mux_tree_tapbuf_size4_3_sram; - wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail; - wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail; - wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail; - wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail; - wire [0:2] mux_tree_tapbuf_size6_0_sram; - wire [0:2] mux_tree_tapbuf_size6_1_sram; - wire [0:2] mux_tree_tapbuf_size6_2_sram; - wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail; - wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail; - wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail; - wire [0:2] mux_tree_tapbuf_size7_0_sram; - wire [0:2] mux_tree_tapbuf_size7_1_sram; - wire [0:2] mux_tree_tapbuf_size7_2_sram; - wire [0:2] mux_tree_tapbuf_size7_3_sram; - wire [0:2] mux_tree_tapbuf_size7_4_sram; - wire [0:2] mux_tree_tapbuf_size7_5_sram; - wire [0:2] mux_tree_tapbuf_size7_6_sram; - wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail; - wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail; - wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail; - wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail; - wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail; - wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail; - wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail; - wire [0:3] mux_tree_tapbuf_size8_0_sram; - wire [0:3] mux_tree_tapbuf_size8_1_sram; - wire [0:3] mux_tree_tapbuf_size8_2_sram; - wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail; - wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail; - wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail; - wire [0:3] mux_tree_tapbuf_size9_0_sram; - wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail; - assign chany_bottom_out[3] = chany_top_in[2]; - assign chany_bottom_out[5] = chany_top_in[4]; - assign chany_bottom_out[6] = chany_top_in[5]; - assign chany_bottom_out[7] = chany_top_in[6]; - assign chany_bottom_out[9] = chany_top_in[8]; - assign chany_bottom_out[10] = chany_top_in[9]; - assign chany_bottom_out[11] = chany_top_in[10]; - assign chany_bottom_out[13] = chany_top_in[12]; - assign chany_bottom_out[14] = chany_top_in[13]; - assign chany_bottom_out[15] = chany_top_in[14]; - assign chany_bottom_out[17] = chany_top_in[16]; - assign chany_bottom_out[18] = chany_top_in[17]; - assign chany_bottom_out[19] = chany_top_in[18]; - assign chany_top_out[3] = chany_bottom_in[2]; - assign chany_top_out[5] = chany_bottom_in[4]; - assign chany_top_out[6] = chany_bottom_in[5]; - assign chany_top_out[7] = chany_bottom_in[6]; - assign chany_top_out[9] = chany_bottom_in[8]; - assign chany_top_out[10] = chany_bottom_in[9]; - assign chany_top_out[11] = chany_bottom_in[10]; - assign chany_top_out[13] = chany_bottom_in[12]; - assign chany_top_out[14] = chany_bottom_in[13]; - assign chany_top_out[15] = chany_bottom_in[14]; - assign chany_top_out[17] = chany_bottom_in[16]; - assign chany_top_out[18] = chany_bottom_in[17]; - assign chany_top_out[19] = chany_bottom_in[18]; - assign chanx_left_out[13] = left_bottom_grid_pin_35_[0]; - - mux_tree_tapbuf_size10 - mux_top_track_0 - ( - .in({ top_left_grid_pin_42_[0], top_left_grid_pin_44_[0], top_left_grid_pin_46_[0], top_left_grid_pin_48_[0], top_right_grid_pin_1_[0], chany_bottom_in[2], chany_bottom_in[12], chanx_left_in[0], chanx_left_in[7], chanx_left_in[14] }), - .sram(mux_tree_tapbuf_size10_0_sram[0:3]), - .sram_inv(mux_top_track_0_undriven_sram_inv[0:3]), - .out(chany_top_out[0]) - ); - - - mux_tree_tapbuf_size10 - mux_bottom_track_1 - ( - .in({ chany_top_in[2], chany_top_in[12], bottom_right_grid_pin_1_[0], bottom_left_grid_pin_43_[0], bottom_left_grid_pin_45_[0], bottom_left_grid_pin_47_[0], bottom_left_grid_pin_49_[0], chanx_left_in[1], chanx_left_in[8], chanx_left_in[15] }), - .sram(mux_tree_tapbuf_size10_1_sram[0:3]), - .sram_inv(mux_bottom_track_1_undriven_sram_inv[0:3]), - .out(chany_bottom_out[0]) - ); - - - mux_tree_tapbuf_size10_mem - mem_top_track_0 - ( - .prog_clk(prog_clk[0]), - .ccff_head(ccff_head[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_0_sram[0:3]) - ); - - - mux_tree_tapbuf_size10_mem - mem_bottom_track_1 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size10_1_sram[0:3]) - ); - - - mux_tree_tapbuf_size8 - mux_top_track_2 - ( - .in({ top_left_grid_pin_43_[0], top_left_grid_pin_45_[0], top_left_grid_pin_47_[0], top_left_grid_pin_49_[0], chany_bottom_in[4], chany_bottom_in[13], chanx_left_in[6], chanx_left_in[13] }), - .sram(mux_tree_tapbuf_size8_0_sram[0:3]), - .sram_inv(mux_top_track_2_undriven_sram_inv[0:3]), - .out(chany_top_out[1]) - ); - - - mux_tree_tapbuf_size8 - mux_top_track_8 - ( - .in({ top_left_grid_pin_42_[0], top_left_grid_pin_46_[0], top_right_grid_pin_1_[0], chany_bottom_in[6], chany_bottom_in[16], chanx_left_in[4], chanx_left_in[11], chanx_left_in[18] }), - .sram(mux_tree_tapbuf_size8_1_sram[0:3]), - .sram_inv(mux_top_track_8_undriven_sram_inv[0:3]), - .out(chany_top_out[4]) - ); - - - mux_tree_tapbuf_size8 - mux_bottom_track_9 - ( - .in({ chany_top_in[6], chany_top_in[16], bottom_right_grid_pin_1_[0], bottom_left_grid_pin_45_[0], bottom_left_grid_pin_49_[0], chanx_left_in[4], chanx_left_in[11], chanx_left_in[18] }), - .sram(mux_tree_tapbuf_size8_2_sram[0:3]), - .sram_inv(mux_bottom_track_9_undriven_sram_inv[0:3]), - .out(chany_bottom_out[4]) - ); - - - mux_tree_tapbuf_size8_mem - mem_top_track_2 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_0_sram[0:3]) - ); - - - mux_tree_tapbuf_size8_mem - mem_top_track_8 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size14_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_1_sram[0:3]) - ); - - - mux_tree_tapbuf_size8_mem - mem_bottom_track_9 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size14_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size8_2_sram[0:3]) - ); - - - mux_tree_tapbuf_size14 - mux_top_track_4 - ( - .in({ top_left_grid_pin_42_[0], top_left_grid_pin_43_[0], top_left_grid_pin_44_[0], top_left_grid_pin_45_[0], top_left_grid_pin_46_[0], top_left_grid_pin_47_[0], top_left_grid_pin_48_[0], top_left_grid_pin_49_[0], top_right_grid_pin_1_[0], chany_bottom_in[5], chany_bottom_in[14], chanx_left_in[5], chanx_left_in[12], chanx_left_in[19] }), - .sram(mux_tree_tapbuf_size14_0_sram[0:3]), - .sram_inv(mux_top_track_4_undriven_sram_inv[0:3]), - .out(chany_top_out[2]) - ); - - - mux_tree_tapbuf_size14 - mux_bottom_track_5 - ( - .in({ chany_top_in[5], chany_top_in[14], bottom_right_grid_pin_1_[0], bottom_left_grid_pin_42_[0], bottom_left_grid_pin_43_[0], bottom_left_grid_pin_44_[0], bottom_left_grid_pin_45_[0], bottom_left_grid_pin_46_[0], bottom_left_grid_pin_47_[0], bottom_left_grid_pin_48_[0], bottom_left_grid_pin_49_[0], chanx_left_in[3], chanx_left_in[10], chanx_left_in[17] }), - .sram(mux_tree_tapbuf_size14_1_sram[0:3]), - .sram_inv(mux_bottom_track_5_undriven_sram_inv[0:3]), - .out(chany_bottom_out[2]) - ); - - - mux_tree_tapbuf_size14_mem - mem_top_track_4 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size14_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size14_0_sram[0:3]) - ); - - - mux_tree_tapbuf_size14_mem - mem_bottom_track_5 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size9_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size14_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size14_1_sram[0:3]) - ); - - - mux_tree_tapbuf_size7 - mux_top_track_16 - ( - .in({ top_left_grid_pin_43_[0], top_left_grid_pin_47_[0], chany_bottom_in[8], chany_bottom_in[17], chanx_left_in[3], chanx_left_in[10], chanx_left_in[17] }), - .sram(mux_tree_tapbuf_size7_0_sram[0:2]), - .sram_inv(mux_top_track_16_undriven_sram_inv[0:2]), - .out(chany_top_out[8]) - ); - - - mux_tree_tapbuf_size7 - mux_top_track_24 - ( - .in({ top_left_grid_pin_44_[0], top_left_grid_pin_48_[0], chany_bottom_in[9], chany_bottom_in[18], chanx_left_in[2], chanx_left_in[9], chanx_left_in[16] }), - .sram(mux_tree_tapbuf_size7_1_sram[0:2]), - .sram_inv(mux_top_track_24_undriven_sram_inv[0:2]), - .out(chany_top_out[12]) - ); - - - mux_tree_tapbuf_size7 - mux_bottom_track_17 - ( - .in({ chany_top_in[8], chany_top_in[17], bottom_left_grid_pin_42_[0], bottom_left_grid_pin_46_[0], chanx_left_in[5], chanx_left_in[12], chanx_left_in[19] }), - .sram(mux_tree_tapbuf_size7_2_sram[0:2]), - .sram_inv(mux_bottom_track_17_undriven_sram_inv[0:2]), - .out(chany_bottom_out[8]) - ); - - - mux_tree_tapbuf_size7 - mux_left_track_1 - ( - .in({ chany_top_in[0], chany_top_in[2], chany_bottom_in[2], left_bottom_grid_pin_34_[0], left_bottom_grid_pin_36_[0], left_bottom_grid_pin_38_[0], left_bottom_grid_pin_40_[0] }), - .sram(mux_tree_tapbuf_size7_3_sram[0:2]), - .sram_inv(mux_left_track_1_undriven_sram_inv[0:2]), - .out(chanx_left_out[0]) - ); - - - mux_tree_tapbuf_size7 - mux_left_track_3 - ( - .in({ chany_top_in[4], chany_bottom_in[0], chany_bottom_in[4], left_bottom_grid_pin_35_[0], left_bottom_grid_pin_37_[0], left_bottom_grid_pin_39_[0], left_bottom_grid_pin_41_[0] }), - .sram(mux_tree_tapbuf_size7_4_sram[0:2]), - .sram_inv(mux_left_track_3_undriven_sram_inv[0:2]), - .out(chanx_left_out[1]) - ); - - - mux_tree_tapbuf_size7 - mux_left_track_5 - ( - .in({ chany_top_in[5], chany_bottom_in[1], chany_bottom_in[5], left_bottom_grid_pin_34_[0], left_bottom_grid_pin_36_[0], left_bottom_grid_pin_38_[0], left_bottom_grid_pin_40_[0] }), - .sram(mux_tree_tapbuf_size7_5_sram[0:2]), - .sram_inv(mux_left_track_5_undriven_sram_inv[0:2]), - .out(chanx_left_out[2]) - ); - - - mux_tree_tapbuf_size7 - mux_left_track_7 - ( - .in({ chany_top_in[6], chany_bottom_in[3], chany_bottom_in[6], left_bottom_grid_pin_35_[0], left_bottom_grid_pin_37_[0], left_bottom_grid_pin_39_[0], left_bottom_grid_pin_41_[0] }), - .sram(mux_tree_tapbuf_size7_6_sram[0:2]), - .sram_inv(mux_left_track_7_undriven_sram_inv[0:2]), - .out(chanx_left_out[3]) - ); - - - mux_tree_tapbuf_size7_mem - mem_top_track_16 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_0_sram[0:2]) - ); - - - mux_tree_tapbuf_size7_mem - mem_top_track_24 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size7_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_1_sram[0:2]) - ); - - - mux_tree_tapbuf_size7_mem - mem_bottom_track_17 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_2_sram[0:2]) - ); - - - mux_tree_tapbuf_size7_mem - mem_left_track_1 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size7_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_3_sram[0:2]) - ); - - - mux_tree_tapbuf_size7_mem - mem_left_track_3 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size7_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size7_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_4_sram[0:2]) - ); - - - mux_tree_tapbuf_size7_mem - mem_left_track_5 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size7_mem_4_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size7_mem_5_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_5_sram[0:2]) - ); - - - mux_tree_tapbuf_size7_mem - mem_left_track_7 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size7_mem_5_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size7_mem_6_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size7_6_sram[0:2]) - ); - - - mux_tree_tapbuf_size6 - mux_top_track_32 - ( - .in({ top_left_grid_pin_45_[0], top_left_grid_pin_49_[0], chany_bottom_in[10], chanx_left_in[1], chanx_left_in[8], chanx_left_in[15] }), - .sram(mux_tree_tapbuf_size6_0_sram[0:2]), - .sram_inv(mux_top_track_32_undriven_sram_inv[0:2]), - .out(chany_top_out[16]) - ); - - - mux_tree_tapbuf_size6 - mux_bottom_track_25 - ( - .in({ chany_top_in[9], chany_top_in[18], bottom_left_grid_pin_43_[0], bottom_left_grid_pin_47_[0], chanx_left_in[6], chanx_left_in[13] }), - .sram(mux_tree_tapbuf_size6_1_sram[0:2]), - .sram_inv(mux_bottom_track_25_undriven_sram_inv[0:2]), - .out(chany_bottom_out[12]) - ); - - - mux_tree_tapbuf_size6 - mux_bottom_track_33 - ( - .in({ chany_top_in[10], bottom_left_grid_pin_44_[0], bottom_left_grid_pin_48_[0], chanx_left_in[0], chanx_left_in[7], chanx_left_in[14] }), - .sram(mux_tree_tapbuf_size6_2_sram[0:2]), - .sram_inv(mux_bottom_track_33_undriven_sram_inv[0:2]), - .out(chany_bottom_out[16]) - ); - - - mux_tree_tapbuf_size6_mem - mem_top_track_32 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size7_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_0_sram[0:2]) - ); - - - mux_tree_tapbuf_size6_mem - mem_bottom_track_25 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size7_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_1_sram[0:2]) - ); - - - mux_tree_tapbuf_size6_mem - mem_bottom_track_33 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_2_sram[0:2]) - ); - - - mux_tree_tapbuf_size9 - mux_bottom_track_3 - ( - .in({ chany_top_in[4], chany_top_in[13], bottom_left_grid_pin_42_[0], bottom_left_grid_pin_44_[0], bottom_left_grid_pin_46_[0], bottom_left_grid_pin_48_[0], chanx_left_in[2], chanx_left_in[9], chanx_left_in[16] }), - .sram(mux_tree_tapbuf_size9_0_sram[0:3]), - .sram_inv(mux_bottom_track_3_undriven_sram_inv[0:3]), - .out(chany_bottom_out[1]) - ); - - - mux_tree_tapbuf_size9_mem - mem_bottom_track_3 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size9_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size9_0_sram[0:3]) - ); - - - mux_tree_tapbuf_size4 - mux_left_track_9 - ( - .in({ chany_top_in[8], chany_bottom_in[7:8], left_bottom_grid_pin_34_[0] }), - .sram(mux_tree_tapbuf_size4_0_sram[0:2]), - .sram_inv(mux_left_track_9_undriven_sram_inv[0:2]), - .out(chanx_left_out[4]) - ); - - - mux_tree_tapbuf_size4 - mux_left_track_11 - ( - .in({ chany_top_in[9], chany_bottom_in[9], chany_bottom_in[11], left_bottom_grid_pin_35_[0] }), - .sram(mux_tree_tapbuf_size4_1_sram[0:2]), - .sram_inv(mux_left_track_11_undriven_sram_inv[0:2]), - .out(chanx_left_out[5]) - ); - - - mux_tree_tapbuf_size4 - mux_left_track_13 - ( - .in({ chany_top_in[10], chany_bottom_in[10], chany_bottom_in[15], left_bottom_grid_pin_36_[0] }), - .sram(mux_tree_tapbuf_size4_2_sram[0:2]), - .sram_inv(mux_left_track_13_undriven_sram_inv[0:2]), - .out(chanx_left_out[6]) - ); - - - mux_tree_tapbuf_size4 - mux_left_track_15 - ( - .in({ chany_top_in[12], chany_bottom_in[12], chany_bottom_in[19], left_bottom_grid_pin_37_[0] }), - .sram(mux_tree_tapbuf_size4_3_sram[0:2]), - .sram_inv(mux_left_track_15_undriven_sram_inv[0:2]), - .out(chanx_left_out[7]) - ); - - - mux_tree_tapbuf_size4_mem - mem_left_track_9 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size7_mem_6_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size4_0_sram[0:2]) - ); - - - mux_tree_tapbuf_size4_mem - mem_left_track_11 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size4_1_sram[0:2]) - ); - - - mux_tree_tapbuf_size4_mem - mem_left_track_13 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size4_2_sram[0:2]) - ); - - - mux_tree_tapbuf_size4_mem - mem_left_track_15 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size4_3_sram[0:2]) - ); - - - mux_tree_tapbuf_size3 - mux_left_track_17 - ( - .in({ chany_top_in[13], chany_bottom_in[13], left_bottom_grid_pin_38_[0] }), - .sram(mux_tree_tapbuf_size3_0_sram[0:1]), - .sram_inv(mux_left_track_17_undriven_sram_inv[0:1]), - .out(chanx_left_out[8]) - ); - - - mux_tree_tapbuf_size3 - mux_left_track_19 - ( - .in({ chany_top_in[14], chany_bottom_in[14], left_bottom_grid_pin_39_[0] }), - .sram(mux_tree_tapbuf_size3_1_sram[0:1]), - .sram_inv(mux_left_track_19_undriven_sram_inv[0:1]), - .out(chanx_left_out[9]) - ); - - - mux_tree_tapbuf_size3 - mux_left_track_21 - ( - .in({ chany_top_in[16], chany_bottom_in[16], left_bottom_grid_pin_40_[0] }), - .sram(mux_tree_tapbuf_size3_2_sram[0:1]), - .sram_inv(mux_left_track_21_undriven_sram_inv[0:1]), - .out(chanx_left_out[10]) - ); - - - mux_tree_tapbuf_size3 - mux_left_track_23 - ( - .in({ chany_top_in[17], chany_bottom_in[17], left_bottom_grid_pin_41_[0] }), - .sram(mux_tree_tapbuf_size3_3_sram[0:1]), - .sram_inv(mux_left_track_23_undriven_sram_inv[0:1]), - .out(chanx_left_out[11]) - ); - - - mux_tree_tapbuf_size3 - mux_left_track_25 - ( - .in({ chany_top_in[18], chany_bottom_in[18], left_bottom_grid_pin_34_[0] }), - .sram(mux_tree_tapbuf_size3_4_sram[0:1]), - .sram_inv(mux_left_track_25_undriven_sram_inv[0:1]), - .out(chanx_left_out[12]) - ); - - - mux_tree_tapbuf_size3_mem - mem_left_track_17 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_0_sram[0:1]) - ); - - - mux_tree_tapbuf_size3_mem - mem_left_track_19 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_1_sram[0:1]) - ); - - - mux_tree_tapbuf_size3_mem - mem_left_track_21 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_2_sram[0:1]) - ); - - - mux_tree_tapbuf_size3_mem - mem_left_track_23 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_3_sram[0:1]) - ); - - - mux_tree_tapbuf_size3_mem - mem_left_track_25 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_4_sram[0:1]) - ); - - - mux_tree_tapbuf_size2 - mux_left_track_29 - ( - .in({ chany_top_in[19], left_bottom_grid_pin_36_[0] }), - .sram(mux_tree_tapbuf_size2_0_sram[0:1]), - .sram_inv(mux_left_track_29_undriven_sram_inv[0:1]), - .out(chanx_left_out[14]) - ); - - - mux_tree_tapbuf_size2 - mux_left_track_31 - ( - .in({ chany_top_in[15], left_bottom_grid_pin_37_[0] }), - .sram(mux_tree_tapbuf_size2_1_sram[0:1]), - .sram_inv(mux_left_track_31_undriven_sram_inv[0:1]), - .out(chanx_left_out[15]) - ); - - - mux_tree_tapbuf_size2 - mux_left_track_33 - ( - .in({ chany_top_in[11], left_bottom_grid_pin_38_[0] }), - .sram(mux_tree_tapbuf_size2_2_sram[0:1]), - .sram_inv(mux_left_track_33_undriven_sram_inv[0:1]), - .out(chanx_left_out[16]) - ); - - - mux_tree_tapbuf_size2 - mux_left_track_35 - ( - .in({ chany_top_in[7], left_bottom_grid_pin_39_[0] }), - .sram(mux_tree_tapbuf_size2_3_sram[0:1]), - .sram_inv(mux_left_track_35_undriven_sram_inv[0:1]), - .out(chanx_left_out[17]) - ); - - - mux_tree_tapbuf_size2 - mux_left_track_37 - ( - .in({ chany_top_in[3], left_bottom_grid_pin_40_[0] }), - .sram(mux_tree_tapbuf_size2_4_sram[0:1]), - .sram_inv(mux_left_track_37_undriven_sram_inv[0:1]), - .out(chanx_left_out[18]) - ); - - - mux_tree_tapbuf_size2 - mux_left_track_39 - ( - .in({ chany_top_in[1], left_bottom_grid_pin_41_[0] }), - .sram(mux_tree_tapbuf_size2_5_sram[0:1]), - .sram_inv(mux_left_track_39_undriven_sram_inv[0:1]), - .out(chanx_left_out[19]) - ); - - - mux_tree_tapbuf_size2_mem - mem_left_track_29 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_0_sram[0:1]) - ); - - - mux_tree_tapbuf_size2_mem - mem_left_track_31 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_1_sram[0:1]) - ); - - - mux_tree_tapbuf_size2_mem - mem_left_track_33 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_2_sram[0:1]) - ); - - - mux_tree_tapbuf_size2_mem - mem_left_track_35 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_3_sram[0:1]) - ); - - - mux_tree_tapbuf_size2_mem - mem_left_track_37 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_4_sram[0:1]) - ); - - - mux_tree_tapbuf_size2_mem - mem_left_track_39 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]), - .ccff_tail(ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_5_sram[0:1]) - ); - - -endmodule - diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_2__2_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_2__2_.v deleted file mode 100644 index 3c0b2d6..0000000 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_2__2_.v +++ /dev/null @@ -1,848 +0,0 @@ - - -module sb_2__2_ -( prog_clk, chany_bottom_in, bottom_right_grid_pin_1_, bottom_left_grid_pin_42_, bottom_left_grid_pin_43_, bottom_left_grid_pin_44_, bottom_left_grid_pin_45_, bottom_left_grid_pin_46_, bottom_left_grid_pin_47_, bottom_left_grid_pin_48_, bottom_left_grid_pin_49_, chanx_left_in, left_top_grid_pin_1_, left_bottom_grid_pin_34_, left_bottom_grid_pin_35_, left_bottom_grid_pin_36_, left_bottom_grid_pin_37_, left_bottom_grid_pin_38_, left_bottom_grid_pin_39_, left_bottom_grid_pin_40_, left_bottom_grid_pin_41_, ccff_head, chany_bottom_out, chanx_left_out, ccff_tail, SC_IN_TOP, SC_IN_BOT, SC_OUT_TOP, SC_OUT_BOT ); - input [0:0] prog_clk; - input [0:19] chany_bottom_in; - input [0:0] bottom_right_grid_pin_1_; - input [0:0] bottom_left_grid_pin_42_; - input [0:0] bottom_left_grid_pin_43_; - input [0:0] bottom_left_grid_pin_44_; - input [0:0] bottom_left_grid_pin_45_; - input [0:0] bottom_left_grid_pin_46_; - input [0:0] bottom_left_grid_pin_47_; - input [0:0] bottom_left_grid_pin_48_; - input [0:0] bottom_left_grid_pin_49_; - input [0:19] chanx_left_in; - input [0:0] left_top_grid_pin_1_; - input [0:0] left_bottom_grid_pin_34_; - input [0:0] left_bottom_grid_pin_35_; - input [0:0] left_bottom_grid_pin_36_; - input [0:0] left_bottom_grid_pin_37_; - input [0:0] left_bottom_grid_pin_38_; - input [0:0] left_bottom_grid_pin_39_; - input [0:0] left_bottom_grid_pin_40_; - input [0:0] left_bottom_grid_pin_41_; - input [0:0] ccff_head; - output [0:19] chany_bottom_out; - output [0:19] chanx_left_out; - output [0:0] ccff_tail; - input SC_IN_TOP; - input SC_IN_BOT; - output SC_OUT_TOP; - output SC_OUT_BOT; - - wire [0:1] mux_bottom_track_11_undriven_sram_inv; - wire [0:1] mux_bottom_track_13_undriven_sram_inv; - wire [0:1] mux_bottom_track_15_undriven_sram_inv; - wire [0:1] mux_bottom_track_17_undriven_sram_inv; - wire [0:1] mux_bottom_track_19_undriven_sram_inv; - wire [0:2] mux_bottom_track_1_undriven_sram_inv; - wire [0:1] mux_bottom_track_21_undriven_sram_inv; - wire [0:1] mux_bottom_track_23_undriven_sram_inv; - wire [0:1] mux_bottom_track_25_undriven_sram_inv; - wire [0:1] mux_bottom_track_27_undriven_sram_inv; - wire [0:1] mux_bottom_track_29_undriven_sram_inv; - wire [0:2] mux_bottom_track_3_undriven_sram_inv; - wire [0:2] mux_bottom_track_5_undriven_sram_inv; - wire [0:2] mux_bottom_track_7_undriven_sram_inv; - wire [0:1] mux_bottom_track_9_undriven_sram_inv; - wire [0:1] mux_left_track_11_undriven_sram_inv; - wire [0:1] mux_left_track_13_undriven_sram_inv; - wire [0:1] mux_left_track_15_undriven_sram_inv; - wire [0:1] mux_left_track_17_undriven_sram_inv; - wire [0:1] mux_left_track_19_undriven_sram_inv; - wire [0:2] mux_left_track_1_undriven_sram_inv; - wire [0:1] mux_left_track_21_undriven_sram_inv; - wire [0:1] mux_left_track_23_undriven_sram_inv; - wire [0:1] mux_left_track_25_undriven_sram_inv; - wire [0:1] mux_left_track_27_undriven_sram_inv; - wire [0:1] mux_left_track_29_undriven_sram_inv; - wire [0:1] mux_left_track_31_undriven_sram_inv; - wire [0:1] mux_left_track_33_undriven_sram_inv; - wire [0:1] mux_left_track_35_undriven_sram_inv; - wire [0:1] mux_left_track_37_undriven_sram_inv; - wire [0:1] mux_left_track_39_undriven_sram_inv; - wire [0:2] mux_left_track_3_undriven_sram_inv; - wire [0:2] mux_left_track_5_undriven_sram_inv; - wire [0:2] mux_left_track_7_undriven_sram_inv; - wire [0:1] mux_left_track_9_undriven_sram_inv; - wire [0:1] mux_tree_tapbuf_size2_0_sram; - wire [0:1] mux_tree_tapbuf_size2_10_sram; - wire [0:1] mux_tree_tapbuf_size2_11_sram; - wire [0:1] mux_tree_tapbuf_size2_12_sram; - wire [0:1] mux_tree_tapbuf_size2_13_sram; - wire [0:1] mux_tree_tapbuf_size2_14_sram; - wire [0:1] mux_tree_tapbuf_size2_15_sram; - wire [0:1] mux_tree_tapbuf_size2_16_sram; - wire [0:1] mux_tree_tapbuf_size2_17_sram; - wire [0:1] mux_tree_tapbuf_size2_18_sram; - wire [0:1] mux_tree_tapbuf_size2_19_sram; - wire [0:1] mux_tree_tapbuf_size2_1_sram; - wire [0:1] mux_tree_tapbuf_size2_20_sram; - wire [0:1] mux_tree_tapbuf_size2_21_sram; - wire [0:1] mux_tree_tapbuf_size2_22_sram; - wire [0:1] mux_tree_tapbuf_size2_23_sram; - wire [0:1] mux_tree_tapbuf_size2_2_sram; - wire [0:1] mux_tree_tapbuf_size2_3_sram; - wire [0:1] mux_tree_tapbuf_size2_4_sram; - wire [0:1] mux_tree_tapbuf_size2_5_sram; - wire [0:1] mux_tree_tapbuf_size2_6_sram; - wire [0:1] mux_tree_tapbuf_size2_7_sram; - wire [0:1] mux_tree_tapbuf_size2_8_sram; - wire [0:1] mux_tree_tapbuf_size2_9_sram; - wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail; - wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail; - wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail; - wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail; - wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail; - wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail; - wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail; - wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail; - wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail; - wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail; - wire [0:0] mux_tree_tapbuf_size2_mem_19_ccff_tail; - wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail; - wire [0:0] mux_tree_tapbuf_size2_mem_20_ccff_tail; - wire [0:0] mux_tree_tapbuf_size2_mem_21_ccff_tail; - wire [0:0] mux_tree_tapbuf_size2_mem_22_ccff_tail; - wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail; - wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail; - wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail; - wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail; - wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail; - wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail; - wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail; - wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail; - wire [0:1] mux_tree_tapbuf_size3_0_sram; - wire [0:1] mux_tree_tapbuf_size3_1_sram; - wire [0:1] mux_tree_tapbuf_size3_2_sram; - wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail; - wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail; - wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail; - wire [0:2] mux_tree_tapbuf_size5_0_sram; - wire [0:2] mux_tree_tapbuf_size5_1_sram; - wire [0:2] mux_tree_tapbuf_size5_2_sram; - wire [0:2] mux_tree_tapbuf_size5_3_sram; - wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail; - wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail; - wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail; - wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail; - wire [0:2] mux_tree_tapbuf_size6_0_sram; - wire [0:2] mux_tree_tapbuf_size6_1_sram; - wire [0:2] mux_tree_tapbuf_size6_2_sram; - wire [0:2] mux_tree_tapbuf_size6_3_sram; - wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail; - wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail; - wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail; - wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail; - assign chany_bottom_out[19] = chanx_left_in[0]; - assign chany_bottom_out[15] = chanx_left_in[16]; - assign chany_bottom_out[16] = chanx_left_in[17]; - assign chany_bottom_out[17] = chanx_left_in[18]; - assign chany_bottom_out[18] = chanx_left_in[19]; - assign SC_IN_TOP = SC_IN_BOT; - assign SC_OUT_TOP = SC_OUT_BOT; - - mux_tree_tapbuf_size6 - mux_bottom_track_1 - ( - .in({ bottom_right_grid_pin_1_[0], bottom_left_grid_pin_43_[0], bottom_left_grid_pin_45_[0], bottom_left_grid_pin_47_[0], bottom_left_grid_pin_49_[0], chanx_left_in[1] }), - .sram(mux_tree_tapbuf_size6_0_sram[0:2]), - .sram_inv(mux_bottom_track_1_undriven_sram_inv[0:2]), - .out(chany_bottom_out[0]) - ); - - - mux_tree_tapbuf_size6 - mux_bottom_track_5 - ( - .in({ bottom_right_grid_pin_1_[0], bottom_left_grid_pin_43_[0], bottom_left_grid_pin_45_[0], bottom_left_grid_pin_47_[0], bottom_left_grid_pin_49_[0], chanx_left_in[3] }), - .sram(mux_tree_tapbuf_size6_1_sram[0:2]), - .sram_inv(mux_bottom_track_5_undriven_sram_inv[0:2]), - .out(chany_bottom_out[2]) - ); - - - mux_tree_tapbuf_size6 - mux_left_track_1 - ( - .in({ chany_bottom_in[19], left_top_grid_pin_1_[0], left_bottom_grid_pin_35_[0], left_bottom_grid_pin_37_[0], left_bottom_grid_pin_39_[0], left_bottom_grid_pin_41_[0] }), - .sram(mux_tree_tapbuf_size6_2_sram[0:2]), - .sram_inv(mux_left_track_1_undriven_sram_inv[0:2]), - .out(chanx_left_out[0]) - ); - - - mux_tree_tapbuf_size6 - mux_left_track_5 - ( - .in({ chany_bottom_in[1], left_top_grid_pin_1_[0], left_bottom_grid_pin_35_[0], left_bottom_grid_pin_37_[0], left_bottom_grid_pin_39_[0], left_bottom_grid_pin_41_[0] }), - .sram(mux_tree_tapbuf_size6_3_sram[0:2]), - .sram_inv(mux_left_track_5_undriven_sram_inv[0:2]), - .out(chanx_left_out[2]) - ); - - - mux_tree_tapbuf_size6_mem - mem_bottom_track_1 - ( - .prog_clk(prog_clk[0]), - .ccff_head(ccff_head[0]), - .ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_0_sram[0:2]) - ); - - - mux_tree_tapbuf_size6_mem - mem_bottom_track_5 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_1_sram[0:2]) - ); - - - mux_tree_tapbuf_size6_mem - mem_left_track_1 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_2_sram[0:2]) - ); - - - mux_tree_tapbuf_size6_mem - mem_left_track_5 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size5_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size6_3_sram[0:2]) - ); - - - mux_tree_tapbuf_size5 - mux_bottom_track_3 - ( - .in({ bottom_left_grid_pin_42_[0], bottom_left_grid_pin_44_[0], bottom_left_grid_pin_46_[0], bottom_left_grid_pin_48_[0], chanx_left_in[2] }), - .sram(mux_tree_tapbuf_size5_0_sram[0:2]), - .sram_inv(mux_bottom_track_3_undriven_sram_inv[0:2]), - .out(chany_bottom_out[1]) - ); - - - mux_tree_tapbuf_size5 - mux_bottom_track_7 - ( - .in({ bottom_left_grid_pin_42_[0], bottom_left_grid_pin_44_[0], bottom_left_grid_pin_46_[0], bottom_left_grid_pin_48_[0], chanx_left_in[4] }), - .sram(mux_tree_tapbuf_size5_1_sram[0:2]), - .sram_inv(mux_bottom_track_7_undriven_sram_inv[0:2]), - .out(chany_bottom_out[3]) - ); - - - mux_tree_tapbuf_size5 - mux_left_track_3 - ( - .in({ chany_bottom_in[0], left_bottom_grid_pin_34_[0], left_bottom_grid_pin_36_[0], left_bottom_grid_pin_38_[0], left_bottom_grid_pin_40_[0] }), - .sram(mux_tree_tapbuf_size5_2_sram[0:2]), - .sram_inv(mux_left_track_3_undriven_sram_inv[0:2]), - .out(chanx_left_out[1]) - ); - - - mux_tree_tapbuf_size5 - mux_left_track_7 - ( - .in({ chany_bottom_in[2], left_bottom_grid_pin_34_[0], left_bottom_grid_pin_36_[0], left_bottom_grid_pin_38_[0], left_bottom_grid_pin_40_[0] }), - .sram(mux_tree_tapbuf_size5_3_sram[0:2]), - .sram_inv(mux_left_track_7_undriven_sram_inv[0:2]), - .out(chanx_left_out[3]) - ); - - - mux_tree_tapbuf_size5_mem - mem_bottom_track_3 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size5_0_sram[0:2]) - ); - - - mux_tree_tapbuf_size5_mem - mem_bottom_track_7 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size5_1_sram[0:2]) - ); - - - mux_tree_tapbuf_size5_mem - mem_left_track_3 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size5_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size5_2_sram[0:2]) - ); - - - mux_tree_tapbuf_size5_mem - mem_left_track_7 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size5_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size5_3_sram[0:2]) - ); - - - mux_tree_tapbuf_size2 - mux_bottom_track_9 - ( - .in({ bottom_right_grid_pin_1_[0], chanx_left_in[5] }), - .sram(mux_tree_tapbuf_size2_0_sram[0:1]), - .sram_inv(mux_bottom_track_9_undriven_sram_inv[0:1]), - .out(chany_bottom_out[4]) - ); - - - mux_tree_tapbuf_size2 - mux_bottom_track_11 - ( - .in({ bottom_left_grid_pin_42_[0], chanx_left_in[6] }), - .sram(mux_tree_tapbuf_size2_1_sram[0:1]), - .sram_inv(mux_bottom_track_11_undriven_sram_inv[0:1]), - .out(chany_bottom_out[5]) - ); - - - mux_tree_tapbuf_size2 - mux_bottom_track_13 - ( - .in({ bottom_left_grid_pin_43_[0], chanx_left_in[7] }), - .sram(mux_tree_tapbuf_size2_2_sram[0:1]), - .sram_inv(mux_bottom_track_13_undriven_sram_inv[0:1]), - .out(chany_bottom_out[6]) - ); - - - mux_tree_tapbuf_size2 - mux_bottom_track_15 - ( - .in({ bottom_left_grid_pin_44_[0], chanx_left_in[8] }), - .sram(mux_tree_tapbuf_size2_3_sram[0:1]), - .sram_inv(mux_bottom_track_15_undriven_sram_inv[0:1]), - .out(chany_bottom_out[7]) - ); - - - mux_tree_tapbuf_size2 - mux_bottom_track_17 - ( - .in({ bottom_left_grid_pin_45_[0], chanx_left_in[9] }), - .sram(mux_tree_tapbuf_size2_4_sram[0:1]), - .sram_inv(mux_bottom_track_17_undriven_sram_inv[0:1]), - .out(chany_bottom_out[8]) - ); - - - mux_tree_tapbuf_size2 - mux_bottom_track_19 - ( - .in({ bottom_left_grid_pin_46_[0], chanx_left_in[10] }), - .sram(mux_tree_tapbuf_size2_5_sram[0:1]), - .sram_inv(mux_bottom_track_19_undriven_sram_inv[0:1]), - .out(chany_bottom_out[9]) - ); - - - mux_tree_tapbuf_size2 - mux_bottom_track_21 - ( - .in({ bottom_left_grid_pin_47_[0], chanx_left_in[11] }), - .sram(mux_tree_tapbuf_size2_6_sram[0:1]), - .sram_inv(mux_bottom_track_21_undriven_sram_inv[0:1]), - .out(chany_bottom_out[10]) - ); - - - mux_tree_tapbuf_size2 - mux_bottom_track_23 - ( - .in({ bottom_left_grid_pin_48_[0], chanx_left_in[12] }), - .sram(mux_tree_tapbuf_size2_7_sram[0:1]), - .sram_inv(mux_bottom_track_23_undriven_sram_inv[0:1]), - .out(chany_bottom_out[11]) - ); - - - mux_tree_tapbuf_size2 - mux_bottom_track_27 - ( - .in({ bottom_left_grid_pin_42_[0], chanx_left_in[14] }), - .sram(mux_tree_tapbuf_size2_8_sram[0:1]), - .sram_inv(mux_bottom_track_27_undriven_sram_inv[0:1]), - .out(chany_bottom_out[13]) - ); - - - mux_tree_tapbuf_size2 - mux_bottom_track_29 - ( - .in({ bottom_left_grid_pin_43_[0], chanx_left_in[15] }), - .sram(mux_tree_tapbuf_size2_9_sram[0:1]), - .sram_inv(mux_bottom_track_29_undriven_sram_inv[0:1]), - .out(chany_bottom_out[14]) - ); - - - mux_tree_tapbuf_size2 - mux_left_track_11 - ( - .in({ chany_bottom_in[4], left_bottom_grid_pin_34_[0] }), - .sram(mux_tree_tapbuf_size2_10_sram[0:1]), - .sram_inv(mux_left_track_11_undriven_sram_inv[0:1]), - .out(chanx_left_out[5]) - ); - - - mux_tree_tapbuf_size2 - mux_left_track_13 - ( - .in({ chany_bottom_in[5], left_bottom_grid_pin_35_[0] }), - .sram(mux_tree_tapbuf_size2_11_sram[0:1]), - .sram_inv(mux_left_track_13_undriven_sram_inv[0:1]), - .out(chanx_left_out[6]) - ); - - - mux_tree_tapbuf_size2 - mux_left_track_15 - ( - .in({ chany_bottom_in[6], left_bottom_grid_pin_36_[0] }), - .sram(mux_tree_tapbuf_size2_12_sram[0:1]), - .sram_inv(mux_left_track_15_undriven_sram_inv[0:1]), - .out(chanx_left_out[7]) - ); - - - mux_tree_tapbuf_size2 - mux_left_track_17 - ( - .in({ chany_bottom_in[7], left_bottom_grid_pin_37_[0] }), - .sram(mux_tree_tapbuf_size2_13_sram[0:1]), - .sram_inv(mux_left_track_17_undriven_sram_inv[0:1]), - .out(chanx_left_out[8]) - ); - - - mux_tree_tapbuf_size2 - mux_left_track_19 - ( - .in({ chany_bottom_in[8], left_bottom_grid_pin_38_[0] }), - .sram(mux_tree_tapbuf_size2_14_sram[0:1]), - .sram_inv(mux_left_track_19_undriven_sram_inv[0:1]), - .out(chanx_left_out[9]) - ); - - - mux_tree_tapbuf_size2 - mux_left_track_21 - ( - .in({ chany_bottom_in[9], left_bottom_grid_pin_39_[0] }), - .sram(mux_tree_tapbuf_size2_15_sram[0:1]), - .sram_inv(mux_left_track_21_undriven_sram_inv[0:1]), - .out(chanx_left_out[10]) - ); - - - mux_tree_tapbuf_size2 - mux_left_track_23 - ( - .in({ chany_bottom_in[10], left_bottom_grid_pin_40_[0] }), - .sram(mux_tree_tapbuf_size2_16_sram[0:1]), - .sram_inv(mux_left_track_23_undriven_sram_inv[0:1]), - .out(chanx_left_out[11]) - ); - - - mux_tree_tapbuf_size2 - mux_left_track_27 - ( - .in({ chany_bottom_in[12], left_bottom_grid_pin_34_[0] }), - .sram(mux_tree_tapbuf_size2_17_sram[0:1]), - .sram_inv(mux_left_track_27_undriven_sram_inv[0:1]), - .out(chanx_left_out[13]) - ); - - - mux_tree_tapbuf_size2 - mux_left_track_29 - ( - .in({ chany_bottom_in[13], left_bottom_grid_pin_35_[0] }), - .sram(mux_tree_tapbuf_size2_18_sram[0:1]), - .sram_inv(mux_left_track_29_undriven_sram_inv[0:1]), - .out(chanx_left_out[14]) - ); - - - mux_tree_tapbuf_size2 - mux_left_track_31 - ( - .in({ chany_bottom_in[14], left_bottom_grid_pin_36_[0] }), - .sram(mux_tree_tapbuf_size2_19_sram[0:1]), - .sram_inv(mux_left_track_31_undriven_sram_inv[0:1]), - .out(chanx_left_out[15]) - ); - - - mux_tree_tapbuf_size2 - mux_left_track_33 - ( - .in({ chany_bottom_in[15], left_bottom_grid_pin_37_[0] }), - .sram(mux_tree_tapbuf_size2_20_sram[0:1]), - .sram_inv(mux_left_track_33_undriven_sram_inv[0:1]), - .out(chanx_left_out[16]) - ); - - - mux_tree_tapbuf_size2 - mux_left_track_35 - ( - .in({ chany_bottom_in[16], left_bottom_grid_pin_38_[0] }), - .sram(mux_tree_tapbuf_size2_21_sram[0:1]), - .sram_inv(mux_left_track_35_undriven_sram_inv[0:1]), - .out(chanx_left_out[17]) - ); - - - mux_tree_tapbuf_size2 - mux_left_track_37 - ( - .in({ chany_bottom_in[17], left_bottom_grid_pin_39_[0] }), - .sram(mux_tree_tapbuf_size2_22_sram[0:1]), - .sram_inv(mux_left_track_37_undriven_sram_inv[0:1]), - .out(chanx_left_out[18]) - ); - - - mux_tree_tapbuf_size2 - mux_left_track_39 - ( - .in({ chany_bottom_in[18], left_bottom_grid_pin_40_[0] }), - .sram(mux_tree_tapbuf_size2_23_sram[0:1]), - .sram_inv(mux_left_track_39_undriven_sram_inv[0:1]), - .out(chanx_left_out[19]) - ); - - - mux_tree_tapbuf_size2_mem - mem_bottom_track_9 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size5_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_0_sram[0:1]) - ); - - - mux_tree_tapbuf_size2_mem - mem_bottom_track_11 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_1_sram[0:1]) - ); - - - mux_tree_tapbuf_size2_mem - mem_bottom_track_13 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_2_sram[0:1]) - ); - - - mux_tree_tapbuf_size2_mem - mem_bottom_track_15 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_3_sram[0:1]) - ); - - - mux_tree_tapbuf_size2_mem - mem_bottom_track_17 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_4_sram[0:1]) - ); - - - mux_tree_tapbuf_size2_mem - mem_bottom_track_19 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_5_sram[0:1]) - ); - - - mux_tree_tapbuf_size2_mem - mem_bottom_track_21 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_6_sram[0:1]) - ); - - - mux_tree_tapbuf_size2_mem - mem_bottom_track_23 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_7_sram[0:1]) - ); - - - mux_tree_tapbuf_size2_mem - mem_bottom_track_27 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_8_sram[0:1]) - ); - - - mux_tree_tapbuf_size2_mem - mem_bottom_track_29 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_9_sram[0:1]) - ); - - - mux_tree_tapbuf_size2_mem - mem_left_track_11 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_10_sram[0:1]) - ); - - - mux_tree_tapbuf_size2_mem - mem_left_track_13 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_11_sram[0:1]) - ); - - - mux_tree_tapbuf_size2_mem - mem_left_track_15 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_12_sram[0:1]) - ); - - - mux_tree_tapbuf_size2_mem - mem_left_track_17 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_13_sram[0:1]) - ); - - - mux_tree_tapbuf_size2_mem - mem_left_track_19 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_14_sram[0:1]) - ); - - - mux_tree_tapbuf_size2_mem - mem_left_track_21 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_15_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_15_sram[0:1]) - ); - - - mux_tree_tapbuf_size2_mem - mem_left_track_23 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_15_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_16_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_16_sram[0:1]) - ); - - - mux_tree_tapbuf_size2_mem - mem_left_track_27 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_17_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_17_sram[0:1]) - ); - - - mux_tree_tapbuf_size2_mem - mem_left_track_29 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_17_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_18_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_18_sram[0:1]) - ); - - - mux_tree_tapbuf_size2_mem - mem_left_track_31 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_18_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_19_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_19_sram[0:1]) - ); - - - mux_tree_tapbuf_size2_mem - mem_left_track_33 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_19_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_20_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_20_sram[0:1]) - ); - - - mux_tree_tapbuf_size2_mem - mem_left_track_35 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_20_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_21_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_21_sram[0:1]) - ); - - - mux_tree_tapbuf_size2_mem - mem_left_track_37 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_21_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size2_mem_22_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_22_sram[0:1]) - ); - - - mux_tree_tapbuf_size2_mem - mem_left_track_39 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_22_ccff_tail[0]), - .ccff_tail(ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size2_23_sram[0:1]) - ); - - - mux_tree_tapbuf_size3 - mux_bottom_track_25 - ( - .in({ bottom_right_grid_pin_1_[0], bottom_left_grid_pin_49_[0], chanx_left_in[13] }), - .sram(mux_tree_tapbuf_size3_0_sram[0:1]), - .sram_inv(mux_bottom_track_25_undriven_sram_inv[0:1]), - .out(chany_bottom_out[12]) - ); - - - mux_tree_tapbuf_size3 - mux_left_track_9 - ( - .in({ chany_bottom_in[3], left_top_grid_pin_1_[0], left_bottom_grid_pin_41_[0] }), - .sram(mux_tree_tapbuf_size3_1_sram[0:1]), - .sram_inv(mux_left_track_9_undriven_sram_inv[0:1]), - .out(chanx_left_out[4]) - ); - - - mux_tree_tapbuf_size3 - mux_left_track_25 - ( - .in({ chany_bottom_in[11], left_top_grid_pin_1_[0], left_bottom_grid_pin_41_[0] }), - .sram(mux_tree_tapbuf_size3_2_sram[0:1]), - .sram_inv(mux_left_track_25_undriven_sram_inv[0:1]), - .out(chanx_left_out[12]) - ); - - - mux_tree_tapbuf_size3_mem - mem_bottom_track_25 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_0_sram[0:1]) - ); - - - mux_tree_tapbuf_size3_mem - mem_left_track_9 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size5_mem_3_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_1_sram[0:1]) - ); - - - mux_tree_tapbuf_size3_mem - mem_left_track_25 - ( - .prog_clk(prog_clk[0]), - .ccff_head(mux_tree_tapbuf_size2_mem_16_ccff_tail[0]), - .ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail[0]), - .mem_out(mux_tree_tapbuf_size3_2_sram[0:1]) - ); - - -endmodule - diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/arch_encoder.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/arch_encoder.v deleted file mode 100644 index f234114..0000000 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/arch_encoder.v +++ /dev/null @@ -1,10 +0,0 @@ -// -// -// -// -// -// -// -// -`timescale 1ns / 1ps - diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/digital_io_hd.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/digital_io_hd.v deleted file mode 100644 index 0dcc04f..0000000 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/digital_io_hd.v +++ /dev/null @@ -1,63 +0,0 @@ -`timescale 1ns/1ps - -module GPIO (A, IE, OE, Y, in, out, mem_out); - output A; - output IE; - output OE; - output Y; - input in; - output out; - input mem_out; - - assign A = in; - assign out = Y; - assign IE = mem_out; - sky130_fd_sc_hd__inv_1 ie_oe_inv ( - .A (mem_out), - .Y (OE) ); -endmodule - - -// -// -// -// -module EMBEDDED_IO ( - input SOC_IN, // - output SOC_OUT, // - output SOC_DIR, // - output FPGA_IN, // - input FPGA_OUT, // - input FPGA_DIR // -); - - assign FPGA_IN = SOC_IN; - assign SOC_OUT = FPGA_OUT; - assign SOC_DIR = FPGA_DIR; -endmodule - -// -// -// -module GPIN ( - inout A, // - output Y // -); - // - sky130_fd_sc_hd__buf_4 in_buf ( - .A (A), - .X (Y) ); -endmodule - -// -// -// -module GPOUT ( - inout Y, // - input A // -); - // - sky130_fd_sc_hd__buf_4 in_buf ( - .A (A), - .X (Y) ); -endmodule diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/inv_buf_passgate.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/inv_buf_passgate.v deleted file mode 100644 index faa32c6..0000000 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/inv_buf_passgate.v +++ /dev/null @@ -1,42 +0,0 @@ -// -// -// -// -// -// -// -// -`timescale 1ns / 1ps - -// -module const0(const0); -// -output [0:0] const0; - -// -// - - -// -// - - assign const0[0] = 1'b0; -endmodule -// - -// -module const1(const1); -// -output [0:0] const1; - -// -// - - -// -// - - assign const1[0] = 1'b1; -endmodule -// - diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/local_encoder.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/local_encoder.v deleted file mode 100644 index f234114..0000000 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/local_encoder.v +++ /dev/null @@ -1,10 +0,0 @@ -// -// -// -// -// -// -// -// -`timescale 1ns / 1ps - diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/luts.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/luts.v deleted file mode 100644 index ff797ff..0000000 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/luts.v +++ /dev/null @@ -1,107 +0,0 @@ -// -// -// -// -// -// -// -// -`timescale 1ns / 1ps - -// -module frac_lut4(in, - sram, - sram_inv, - mode, - mode_inv, - lut3_out, - lut4_out); -// -input [0:3] in; -// -input [0:15] sram; -// -input [0:15] sram_inv; -// -input [0:0] mode; -// -input [0:0] mode_inv; -// -output [0:1] lut3_out; -// -output [0:0] lut4_out; - -// -wire [0:3] in; -wire [0:1] lut3_out; -wire [0:0] lut4_out; -// - - -// -// - - -wire [0:0] sky130_fd_sc_hd__buf_2_0_X; -wire [0:0] sky130_fd_sc_hd__buf_2_1_X; -wire [0:0] sky130_fd_sc_hd__buf_2_2_X; -wire [0:0] sky130_fd_sc_hd__buf_2_3_X; -wire [0:0] sky130_fd_sc_hd__inv_1_0_Y; -wire [0:0] sky130_fd_sc_hd__inv_1_1_Y; -wire [0:0] sky130_fd_sc_hd__inv_1_2_Y; -wire [0:0] sky130_fd_sc_hd__inv_1_3_Y; -wire [0:0] sky130_fd_sc_hd__or2_1_0_X; - -// -// -// -// - - sky130_fd_sc_hd__or2_1 sky130_fd_sc_hd__or2_1_0_ ( - .A(mode[0]), - .B(in[3]), - .X(sky130_fd_sc_hd__or2_1_0_X[0])); - - sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( - .A(in[0]), - .Y(sky130_fd_sc_hd__inv_1_0_Y[0])); - - sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( - .A(in[1]), - .Y(sky130_fd_sc_hd__inv_1_1_Y[0])); - - sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( - .A(in[2]), - .Y(sky130_fd_sc_hd__inv_1_2_Y[0])); - - sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( - .A(sky130_fd_sc_hd__or2_1_0_X[0]), - .Y(sky130_fd_sc_hd__inv_1_3_Y[0])); - - sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ ( - .A(in[0]), - .X(sky130_fd_sc_hd__buf_2_0_X[0])); - - sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ ( - .A(in[1]), - .X(sky130_fd_sc_hd__buf_2_1_X[0])); - - sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_2_ ( - .A(in[2]), - .X(sky130_fd_sc_hd__buf_2_2_X[0])); - - sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ ( - .A(sky130_fd_sc_hd__or2_1_0_X[0]), - .X(sky130_fd_sc_hd__buf_2_3_X[0])); - - frac_lut4_mux frac_lut4_mux_0_ ( - .in(sram[0:15]), - .sram({sky130_fd_sc_hd__buf_2_0_X[0], sky130_fd_sc_hd__buf_2_1_X[0], sky130_fd_sc_hd__buf_2_2_X[0], sky130_fd_sc_hd__buf_2_3_X[0]}), - .sram_inv({sky130_fd_sc_hd__inv_1_0_Y[0], sky130_fd_sc_hd__inv_1_1_Y[0], sky130_fd_sc_hd__inv_1_2_Y[0], sky130_fd_sc_hd__inv_1_3_Y[0]}), - .lut3_out(lut3_out[0:1]), - .lut4_out(lut4_out[0])); - -endmodule -// - - diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/memories.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/memories.v deleted file mode 100644 index 3febf86..0000000 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/memories.v +++ /dev/null @@ -1,879 +0,0 @@ -// -// -// -// -// -// -// -// -`timescale 1ns / 1ps - -// -module mux_tree_tapbuf_size10_mem(prog_clk, - ccff_head, - ccff_tail, - mem_out); -// -input [0:0] prog_clk; -// -input [0:0] ccff_head; -// -output [0:0] ccff_tail; -// -output [0:3] mem_out; - -// -// - - -// -// - - - -// -// -// - assign ccff_tail[0] = mem_out[3]; -// - - sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( - .CLK(prog_clk[0]), - .D(ccff_head[0]), - .Q(mem_out[0])); - - sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( - .CLK(prog_clk[0]), - .D(mem_out[0]), - .Q(mem_out[1])); - - sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( - .CLK(prog_clk[0]), - .D(mem_out[1]), - .Q(mem_out[2])); - - sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( - .CLK(prog_clk[0]), - .D(mem_out[2]), - .Q(mem_out[3])); - -endmodule -// - - - -// -module mux_tree_tapbuf_size8_mem(prog_clk, - ccff_head, - ccff_tail, - mem_out); -// -input [0:0] prog_clk; -// -input [0:0] ccff_head; -// -output [0:0] ccff_tail; -// -output [0:3] mem_out; - -// -// - - -// -// - - - -// -// -// - assign ccff_tail[0] = mem_out[3]; -// - - sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( - .CLK(prog_clk[0]), - .D(ccff_head[0]), - .Q(mem_out[0])); - - sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( - .CLK(prog_clk[0]), - .D(mem_out[0]), - .Q(mem_out[1])); - - sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( - .CLK(prog_clk[0]), - .D(mem_out[1]), - .Q(mem_out[2])); - - sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( - .CLK(prog_clk[0]), - .D(mem_out[2]), - .Q(mem_out[3])); - -endmodule -// - - - -// -module mux_tree_tapbuf_size4_mem(prog_clk, - ccff_head, - ccff_tail, - mem_out); -// -input [0:0] prog_clk; -// -input [0:0] ccff_head; -// -output [0:0] ccff_tail; -// -output [0:2] mem_out; - -// -// - - -// -// - - - -// -// -// - assign ccff_tail[0] = mem_out[2]; -// - - sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( - .CLK(prog_clk[0]), - .D(ccff_head[0]), - .Q(mem_out[0])); - - sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( - .CLK(prog_clk[0]), - .D(mem_out[0]), - .Q(mem_out[1])); - - sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( - .CLK(prog_clk[0]), - .D(mem_out[1]), - .Q(mem_out[2])); - -endmodule -// - - - -// -module mux_tree_tapbuf_size7_mem(prog_clk, - ccff_head, - ccff_tail, - mem_out); -// -input [0:0] prog_clk; -// -input [0:0] ccff_head; -// -output [0:0] ccff_tail; -// -output [0:2] mem_out; - -// -// - - -// -// - - - -// -// -// - assign ccff_tail[0] = mem_out[2]; -// - - sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( - .CLK(prog_clk[0]), - .D(ccff_head[0]), - .Q(mem_out[0])); - - sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( - .CLK(prog_clk[0]), - .D(mem_out[0]), - .Q(mem_out[1])); - - sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( - .CLK(prog_clk[0]), - .D(mem_out[1]), - .Q(mem_out[2])); - -endmodule -// - - - -// -module mux_tree_tapbuf_size11_mem(prog_clk, - ccff_head, - ccff_tail, - mem_out); -// -input [0:0] prog_clk; -// -input [0:0] ccff_head; -// -output [0:0] ccff_tail; -// -output [0:3] mem_out; - -// -// - - -// -// - - - -// -// -// - assign ccff_tail[0] = mem_out[3]; -// - - sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( - .CLK(prog_clk[0]), - .D(ccff_head[0]), - .Q(mem_out[0])); - - sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( - .CLK(prog_clk[0]), - .D(mem_out[0]), - .Q(mem_out[1])); - - sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( - .CLK(prog_clk[0]), - .D(mem_out[1]), - .Q(mem_out[2])); - - sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( - .CLK(prog_clk[0]), - .D(mem_out[2]), - .Q(mem_out[3])); - -endmodule -// - - - -// -module mux_tree_tapbuf_size2_mem(prog_clk, - ccff_head, - ccff_tail, - mem_out); -// -input [0:0] prog_clk; -// -input [0:0] ccff_head; -// -output [0:0] ccff_tail; -// -output [0:1] mem_out; - -// -// - - -// -// - - - -// -// -// - assign ccff_tail[0] = mem_out[1]; -// - - sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( - .CLK(prog_clk[0]), - .D(ccff_head[0]), - .Q(mem_out[0])); - - sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( - .CLK(prog_clk[0]), - .D(mem_out[0]), - .Q(mem_out[1])); - -endmodule -// - - - -// -module mux_tree_tapbuf_size6_mem(prog_clk, - ccff_head, - ccff_tail, - mem_out); -// -input [0:0] prog_clk; -// -input [0:0] ccff_head; -// -output [0:0] ccff_tail; -// -output [0:2] mem_out; - -// -// - - -// -// - - - -// -// -// - assign ccff_tail[0] = mem_out[2]; -// - - sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( - .CLK(prog_clk[0]), - .D(ccff_head[0]), - .Q(mem_out[0])); - - sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( - .CLK(prog_clk[0]), - .D(mem_out[0]), - .Q(mem_out[1])); - - sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( - .CLK(prog_clk[0]), - .D(mem_out[1]), - .Q(mem_out[2])); - -endmodule -// - - - -// -module mux_tree_tapbuf_size5_mem(prog_clk, - ccff_head, - ccff_tail, - mem_out); -// -input [0:0] prog_clk; -// -input [0:0] ccff_head; -// -output [0:0] ccff_tail; -// -output [0:2] mem_out; - -// -// - - -// -// - - - -// -// -// - assign ccff_tail[0] = mem_out[2]; -// - - sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( - .CLK(prog_clk[0]), - .D(ccff_head[0]), - .Q(mem_out[0])); - - sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( - .CLK(prog_clk[0]), - .D(mem_out[0]), - .Q(mem_out[1])); - - sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( - .CLK(prog_clk[0]), - .D(mem_out[1]), - .Q(mem_out[2])); - -endmodule -// - - - -// -module mux_tree_tapbuf_size12_mem(prog_clk, - ccff_head, - ccff_tail, - mem_out); -// -input [0:0] prog_clk; -// -input [0:0] ccff_head; -// -output [0:0] ccff_tail; -// -output [0:3] mem_out; - -// -// - - -// -// - - - -// -// -// - assign ccff_tail[0] = mem_out[3]; -// - - sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( - .CLK(prog_clk[0]), - .D(ccff_head[0]), - .Q(mem_out[0])); - - sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( - .CLK(prog_clk[0]), - .D(mem_out[0]), - .Q(mem_out[1])); - - sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( - .CLK(prog_clk[0]), - .D(mem_out[1]), - .Q(mem_out[2])); - - sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( - .CLK(prog_clk[0]), - .D(mem_out[2]), - .Q(mem_out[3])); - -endmodule -// - - - -// -module mux_tree_tapbuf_size16_mem(prog_clk, - ccff_head, - ccff_tail, - mem_out); -// -input [0:0] prog_clk; -// -input [0:0] ccff_head; -// -output [0:0] ccff_tail; -// -output [0:4] mem_out; - -// -// - - -// -// - - - -// -// -// - assign ccff_tail[0] = mem_out[4]; -// - - sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( - .CLK(prog_clk[0]), - .D(ccff_head[0]), - .Q(mem_out[0])); - - sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( - .CLK(prog_clk[0]), - .D(mem_out[0]), - .Q(mem_out[1])); - - sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( - .CLK(prog_clk[0]), - .D(mem_out[1]), - .Q(mem_out[2])); - - sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( - .CLK(prog_clk[0]), - .D(mem_out[2]), - .Q(mem_out[3])); - - sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( - .CLK(prog_clk[0]), - .D(mem_out[3]), - .Q(mem_out[4])); - -endmodule -// - - - -// -module mux_tree_tapbuf_size3_mem(prog_clk, - ccff_head, - ccff_tail, - mem_out); -// -input [0:0] prog_clk; -// -input [0:0] ccff_head; -// -output [0:0] ccff_tail; -// -output [0:1] mem_out; - -// -// - - -// -// - - - -// -// -// - assign ccff_tail[0] = mem_out[1]; -// - - sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( - .CLK(prog_clk[0]), - .D(ccff_head[0]), - .Q(mem_out[0])); - - sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( - .CLK(prog_clk[0]), - .D(mem_out[0]), - .Q(mem_out[1])); - -endmodule -// - - - -// -module mux_tree_tapbuf_size9_mem(prog_clk, - ccff_head, - ccff_tail, - mem_out); -// -input [0:0] prog_clk; -// -input [0:0] ccff_head; -// -output [0:0] ccff_tail; -// -output [0:3] mem_out; - -// -// - - -// -// - - - -// -// -// - assign ccff_tail[0] = mem_out[3]; -// - - sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( - .CLK(prog_clk[0]), - .D(ccff_head[0]), - .Q(mem_out[0])); - - sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( - .CLK(prog_clk[0]), - .D(mem_out[0]), - .Q(mem_out[1])); - - sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( - .CLK(prog_clk[0]), - .D(mem_out[1]), - .Q(mem_out[2])); - - sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( - .CLK(prog_clk[0]), - .D(mem_out[2]), - .Q(mem_out[3])); - -endmodule -// - - - -// -module mux_tree_tapbuf_size14_mem(prog_clk, - ccff_head, - ccff_tail, - mem_out); -// -input [0:0] prog_clk; -// -input [0:0] ccff_head; -// -output [0:0] ccff_tail; -// -output [0:3] mem_out; - -// -// - - -// -// - - - -// -// -// - assign ccff_tail[0] = mem_out[3]; -// - - sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( - .CLK(prog_clk[0]), - .D(ccff_head[0]), - .Q(mem_out[0])); - - sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( - .CLK(prog_clk[0]), - .D(mem_out[0]), - .Q(mem_out[1])); - - sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( - .CLK(prog_clk[0]), - .D(mem_out[1]), - .Q(mem_out[2])); - - sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( - .CLK(prog_clk[0]), - .D(mem_out[2]), - .Q(mem_out[3])); - -endmodule -// - - - -// -module mux_tree_size2_mem(prog_clk, - ccff_head, - ccff_tail, - mem_out); -// -input [0:0] prog_clk; -// -input [0:0] ccff_head; -// -output [0:0] ccff_tail; -// -output [0:1] mem_out; - -// -// - - -// -// - - - -// -// -// - assign ccff_tail[0] = mem_out[1]; -// - - sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( - .CLK(prog_clk[0]), - .D(ccff_head[0]), - .Q(mem_out[0])); - - sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( - .CLK(prog_clk[0]), - .D(mem_out[0]), - .Q(mem_out[1])); - -endmodule -// - - - -// -module frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem(prog_clk, - ccff_head, - ccff_tail, - mem_out); -// -input [0:0] prog_clk; -// -input [0:0] ccff_head; -// -output [0:0] ccff_tail; -// -output [0:16] mem_out; - -// -// - - -// -// - - - -// -// -// - assign ccff_tail[0] = mem_out[16]; -// - - sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( - .CLK(prog_clk[0]), - .D(ccff_head[0]), - .Q(mem_out[0])); - - sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( - .CLK(prog_clk[0]), - .D(mem_out[0]), - .Q(mem_out[1])); - - sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( - .CLK(prog_clk[0]), - .D(mem_out[1]), - .Q(mem_out[2])); - - sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( - .CLK(prog_clk[0]), - .D(mem_out[2]), - .Q(mem_out[3])); - - sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( - .CLK(prog_clk[0]), - .D(mem_out[3]), - .Q(mem_out[4])); - - sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_5_ ( - .CLK(prog_clk[0]), - .D(mem_out[4]), - .Q(mem_out[5])); - - sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_6_ ( - .CLK(prog_clk[0]), - .D(mem_out[5]), - .Q(mem_out[6])); - - sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_7_ ( - .CLK(prog_clk[0]), - .D(mem_out[6]), - .Q(mem_out[7])); - - sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_8_ ( - .CLK(prog_clk[0]), - .D(mem_out[7]), - .Q(mem_out[8])); - - sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_9_ ( - .CLK(prog_clk[0]), - .D(mem_out[8]), - .Q(mem_out[9])); - - sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_10_ ( - .CLK(prog_clk[0]), - .D(mem_out[9]), - .Q(mem_out[10])); - - sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_11_ ( - .CLK(prog_clk[0]), - .D(mem_out[10]), - .Q(mem_out[11])); - - sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_12_ ( - .CLK(prog_clk[0]), - .D(mem_out[11]), - .Q(mem_out[12])); - - sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_13_ ( - .CLK(prog_clk[0]), - .D(mem_out[12]), - .Q(mem_out[13])); - - sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_14_ ( - .CLK(prog_clk[0]), - .D(mem_out[13]), - .Q(mem_out[14])); - - sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_15_ ( - .CLK(prog_clk[0]), - .D(mem_out[14]), - .Q(mem_out[15])); - - sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_16_ ( - .CLK(prog_clk[0]), - .D(mem_out[15]), - .Q(mem_out[16])); - -endmodule -// - - - -// -module EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem(prog_clk, - ccff_head, - ccff_tail, - mem_out); -// -input [0:0] prog_clk; -// -input [0:0] ccff_head; -// -output [0:0] ccff_tail; -// -output [0:0] mem_out; - -// -// - - -// -// - - - -// -// -// - assign ccff_tail[0] = mem_out[0]; -// - - sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( - .CLK(prog_clk[0]), - .D(ccff_head[0]), - .Q(mem_out[0])); - -endmodule -// - - - diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/muxes.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/muxes.v deleted file mode 100644 index 9d0204a..0000000 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/muxes.v +++ /dev/null @@ -1,1515 +0,0 @@ -// -// -// -// -// -// -// -// -`timescale 1ns / 1ps - -// -module mux_tree_tapbuf_size10(in, - sram, - sram_inv, - out); -// -input [0:9] in; -// -input [0:3] sram; -// -input [0:3] sram_inv; -// -output [0:0] out; - -// -// - - -// -// - - -wire [0:0] const1_0_const1; -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X; - -// -// -// -// - - const1 const1_0_ ( - .const1(const1_0_const1[0])); - - sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A(sky130_fd_sc_hd__mux2_1_9_X[0]), - .X(out[0])); - - sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( - .A1(in[0]), - .A0(in[1]), - .S(sram[0]), - .X(sky130_fd_sc_hd__mux2_1_0_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( - .A1(in[2]), - .A0(in[3]), - .S(sram[0]), - .X(sky130_fd_sc_hd__mux2_1_1_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( - .A1(in[4]), - .A0(in[5]), - .S(sram[0]), - .X(sky130_fd_sc_hd__mux2_1_2_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A1(sky130_fd_sc_hd__mux2_1_0_X[0]), - .A0(sky130_fd_sc_hd__mux2_1_1_X[0]), - .S(sram[1]), - .X(sky130_fd_sc_hd__mux2_1_3_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A1(sky130_fd_sc_hd__mux2_1_2_X[0]), - .A0(in[6]), - .S(sram[1]), - .X(sky130_fd_sc_hd__mux2_1_4_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( - .A1(in[7]), - .A0(in[8]), - .S(sram[1]), - .X(sky130_fd_sc_hd__mux2_1_5_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( - .A1(in[9]), - .A0(const1_0_const1[0]), - .S(sram[1]), - .X(sky130_fd_sc_hd__mux2_1_6_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A1(sky130_fd_sc_hd__mux2_1_3_X[0]), - .A0(sky130_fd_sc_hd__mux2_1_4_X[0]), - .S(sram[2]), - .X(sky130_fd_sc_hd__mux2_1_7_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A1(sky130_fd_sc_hd__mux2_1_5_X[0]), - .A0(sky130_fd_sc_hd__mux2_1_6_X[0]), - .S(sram[2]), - .X(sky130_fd_sc_hd__mux2_1_8_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A1(sky130_fd_sc_hd__mux2_1_7_X[0]), - .A0(sky130_fd_sc_hd__mux2_1_8_X[0]), - .S(sram[3]), - .X(sky130_fd_sc_hd__mux2_1_9_X[0])); - -endmodule -// - - - -// -module mux_tree_tapbuf_size8(in, - sram, - sram_inv, - out); -// -input [0:7] in; -// -input [0:3] sram; -// -input [0:3] sram_inv; -// -output [0:0] out; - -// -// - - -// -// - - -wire [0:0] const1_0_const1; -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X; - -// -// -// -// - - const1 const1_0_ ( - .const1(const1_0_const1[0])); - - sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A(sky130_fd_sc_hd__mux2_1_7_X[0]), - .X(out[0])); - - sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( - .A1(in[0]), - .A0(in[1]), - .S(sram[0]), - .X(sky130_fd_sc_hd__mux2_1_0_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A1(sky130_fd_sc_hd__mux2_1_0_X[0]), - .A0(in[2]), - .S(sram[1]), - .X(sky130_fd_sc_hd__mux2_1_1_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A1(in[3]), - .A0(in[4]), - .S(sram[1]), - .X(sky130_fd_sc_hd__mux2_1_2_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( - .A1(in[5]), - .A0(in[6]), - .S(sram[1]), - .X(sky130_fd_sc_hd__mux2_1_3_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( - .A1(in[7]), - .A0(const1_0_const1[0]), - .S(sram[1]), - .X(sky130_fd_sc_hd__mux2_1_4_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A1(sky130_fd_sc_hd__mux2_1_1_X[0]), - .A0(sky130_fd_sc_hd__mux2_1_2_X[0]), - .S(sram[2]), - .X(sky130_fd_sc_hd__mux2_1_5_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A1(sky130_fd_sc_hd__mux2_1_3_X[0]), - .A0(sky130_fd_sc_hd__mux2_1_4_X[0]), - .S(sram[2]), - .X(sky130_fd_sc_hd__mux2_1_6_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A1(sky130_fd_sc_hd__mux2_1_5_X[0]), - .A0(sky130_fd_sc_hd__mux2_1_6_X[0]), - .S(sram[3]), - .X(sky130_fd_sc_hd__mux2_1_7_X[0])); - -endmodule -// - - - -// -module mux_tree_tapbuf_size4(in, - sram, - sram_inv, - out); -// -input [0:3] in; -// -input [0:2] sram; -// -input [0:2] sram_inv; -// -output [0:0] out; - -// -// - - -// -// - - -wire [0:0] const1_0_const1; -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X; - -// -// -// -// - - const1 const1_0_ ( - .const1(const1_0_const1[0])); - - sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A(sky130_fd_sc_hd__mux2_1_3_X[0]), - .X(out[0])); - - sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( - .A1(in[0]), - .A0(in[1]), - .S(sram[0]), - .X(sky130_fd_sc_hd__mux2_1_0_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A1(sky130_fd_sc_hd__mux2_1_0_X[0]), - .A0(in[2]), - .S(sram[1]), - .X(sky130_fd_sc_hd__mux2_1_1_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A1(in[3]), - .A0(const1_0_const1[0]), - .S(sram[1]), - .X(sky130_fd_sc_hd__mux2_1_2_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A1(sky130_fd_sc_hd__mux2_1_1_X[0]), - .A0(sky130_fd_sc_hd__mux2_1_2_X[0]), - .S(sram[2]), - .X(sky130_fd_sc_hd__mux2_1_3_X[0])); - -endmodule -// - - - -// -module mux_tree_tapbuf_size7(in, - sram, - sram_inv, - out); -// -input [0:6] in; -// -input [0:2] sram; -// -input [0:2] sram_inv; -// -output [0:0] out; - -// -// - - -// -// - - -wire [0:0] const1_0_const1; -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X; - -// -// -// -// - - const1 const1_0_ ( - .const1(const1_0_const1[0])); - - sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A(sky130_fd_sc_hd__mux2_1_6_X[0]), - .X(out[0])); - - sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( - .A1(in[0]), - .A0(in[1]), - .S(sram[0]), - .X(sky130_fd_sc_hd__mux2_1_0_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( - .A1(in[2]), - .A0(in[3]), - .S(sram[0]), - .X(sky130_fd_sc_hd__mux2_1_1_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( - .A1(in[4]), - .A0(in[5]), - .S(sram[0]), - .X(sky130_fd_sc_hd__mux2_1_2_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( - .A1(in[6]), - .A0(const1_0_const1[0]), - .S(sram[0]), - .X(sky130_fd_sc_hd__mux2_1_3_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A1(sky130_fd_sc_hd__mux2_1_0_X[0]), - .A0(sky130_fd_sc_hd__mux2_1_1_X[0]), - .S(sram[1]), - .X(sky130_fd_sc_hd__mux2_1_4_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A1(sky130_fd_sc_hd__mux2_1_2_X[0]), - .A0(sky130_fd_sc_hd__mux2_1_3_X[0]), - .S(sram[1]), - .X(sky130_fd_sc_hd__mux2_1_5_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A1(sky130_fd_sc_hd__mux2_1_4_X[0]), - .A0(sky130_fd_sc_hd__mux2_1_5_X[0]), - .S(sram[2]), - .X(sky130_fd_sc_hd__mux2_1_6_X[0])); - -endmodule -// - - - -// -module mux_tree_tapbuf_size11(in, - sram, - sram_inv, - out); -// -input [0:10] in; -// -input [0:3] sram; -// -input [0:3] sram_inv; -// -output [0:0] out; - -// -// - - -// -// - - -wire [0:0] const1_0_const1; -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X; - -// -// -// -// - - const1 const1_0_ ( - .const1(const1_0_const1[0])); - - sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A(sky130_fd_sc_hd__mux2_1_10_X[0]), - .X(out[0])); - - sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( - .A1(in[0]), - .A0(in[1]), - .S(sram[0]), - .X(sky130_fd_sc_hd__mux2_1_0_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( - .A1(in[2]), - .A0(in[3]), - .S(sram[0]), - .X(sky130_fd_sc_hd__mux2_1_1_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( - .A1(in[4]), - .A0(in[5]), - .S(sram[0]), - .X(sky130_fd_sc_hd__mux2_1_2_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( - .A1(in[6]), - .A0(in[7]), - .S(sram[0]), - .X(sky130_fd_sc_hd__mux2_1_3_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A1(sky130_fd_sc_hd__mux2_1_0_X[0]), - .A0(sky130_fd_sc_hd__mux2_1_1_X[0]), - .S(sram[1]), - .X(sky130_fd_sc_hd__mux2_1_4_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A1(sky130_fd_sc_hd__mux2_1_2_X[0]), - .A0(sky130_fd_sc_hd__mux2_1_3_X[0]), - .S(sram[1]), - .X(sky130_fd_sc_hd__mux2_1_5_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( - .A1(in[8]), - .A0(in[9]), - .S(sram[1]), - .X(sky130_fd_sc_hd__mux2_1_6_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( - .A1(in[10]), - .A0(const1_0_const1[0]), - .S(sram[1]), - .X(sky130_fd_sc_hd__mux2_1_7_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A1(sky130_fd_sc_hd__mux2_1_4_X[0]), - .A0(sky130_fd_sc_hd__mux2_1_5_X[0]), - .S(sram[2]), - .X(sky130_fd_sc_hd__mux2_1_8_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A1(sky130_fd_sc_hd__mux2_1_6_X[0]), - .A0(sky130_fd_sc_hd__mux2_1_7_X[0]), - .S(sram[2]), - .X(sky130_fd_sc_hd__mux2_1_9_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A1(sky130_fd_sc_hd__mux2_1_8_X[0]), - .A0(sky130_fd_sc_hd__mux2_1_9_X[0]), - .S(sram[3]), - .X(sky130_fd_sc_hd__mux2_1_10_X[0])); - -endmodule -// - - - -// -module mux_tree_tapbuf_size2(in, - sram, - sram_inv, - out); -// -input [0:1] in; -// -input [0:1] sram; -// -input [0:1] sram_inv; -// -output [0:0] out; - -// -// - - -// -// - - -wire [0:0] const1_0_const1; -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X; - -// -// -// -// - - const1 const1_0_ ( - .const1(const1_0_const1[0])); - - sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A(sky130_fd_sc_hd__mux2_1_1_X[0]), - .X(out[0])); - - sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( - .A1(in[0]), - .A0(in[1]), - .S(sram[0]), - .X(sky130_fd_sc_hd__mux2_1_0_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A1(sky130_fd_sc_hd__mux2_1_0_X[0]), - .A0(const1_0_const1[0]), - .S(sram[1]), - .X(sky130_fd_sc_hd__mux2_1_1_X[0])); - -endmodule -// - - - -// -module mux_tree_tapbuf_size6(in, - sram, - sram_inv, - out); -// -input [0:5] in; -// -input [0:2] sram; -// -input [0:2] sram_inv; -// -output [0:0] out; - -// -// - - -// -// - - -wire [0:0] const1_0_const1; -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X; - -// -// -// -// - - const1 const1_0_ ( - .const1(const1_0_const1[0])); - - sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A(sky130_fd_sc_hd__mux2_1_5_X[0]), - .X(out[0])); - - sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( - .A1(in[0]), - .A0(in[1]), - .S(sram[0]), - .X(sky130_fd_sc_hd__mux2_1_0_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( - .A1(in[2]), - .A0(in[3]), - .S(sram[0]), - .X(sky130_fd_sc_hd__mux2_1_1_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( - .A1(in[4]), - .A0(in[5]), - .S(sram[0]), - .X(sky130_fd_sc_hd__mux2_1_2_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A1(sky130_fd_sc_hd__mux2_1_0_X[0]), - .A0(sky130_fd_sc_hd__mux2_1_1_X[0]), - .S(sram[1]), - .X(sky130_fd_sc_hd__mux2_1_3_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A1(sky130_fd_sc_hd__mux2_1_2_X[0]), - .A0(const1_0_const1[0]), - .S(sram[1]), - .X(sky130_fd_sc_hd__mux2_1_4_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A1(sky130_fd_sc_hd__mux2_1_3_X[0]), - .A0(sky130_fd_sc_hd__mux2_1_4_X[0]), - .S(sram[2]), - .X(sky130_fd_sc_hd__mux2_1_5_X[0])); - -endmodule -// - - - -// -module mux_tree_tapbuf_size5(in, - sram, - sram_inv, - out); -// -input [0:4] in; -// -input [0:2] sram; -// -input [0:2] sram_inv; -// -output [0:0] out; - -// -// - - -// -// - - -wire [0:0] const1_0_const1; -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X; - -// -// -// -// - - const1 const1_0_ ( - .const1(const1_0_const1[0])); - - sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A(sky130_fd_sc_hd__mux2_1_4_X[0]), - .X(out[0])); - - sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( - .A1(in[0]), - .A0(in[1]), - .S(sram[0]), - .X(sky130_fd_sc_hd__mux2_1_0_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( - .A1(in[2]), - .A0(in[3]), - .S(sram[0]), - .X(sky130_fd_sc_hd__mux2_1_1_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A1(sky130_fd_sc_hd__mux2_1_0_X[0]), - .A0(sky130_fd_sc_hd__mux2_1_1_X[0]), - .S(sram[1]), - .X(sky130_fd_sc_hd__mux2_1_2_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A1(in[4]), - .A0(const1_0_const1[0]), - .S(sram[1]), - .X(sky130_fd_sc_hd__mux2_1_3_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A1(sky130_fd_sc_hd__mux2_1_2_X[0]), - .A0(sky130_fd_sc_hd__mux2_1_3_X[0]), - .S(sram[2]), - .X(sky130_fd_sc_hd__mux2_1_4_X[0])); - -endmodule -// - - - -// -module mux_tree_tapbuf_size12(in, - sram, - sram_inv, - out); -// -input [0:11] in; -// -input [0:3] sram; -// -input [0:3] sram_inv; -// -output [0:0] out; - -// -// - - -// -// - - -wire [0:0] const1_0_const1; -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X; - -// -// -// -// - - const1 const1_0_ ( - .const1(const1_0_const1[0])); - - sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A(sky130_fd_sc_hd__mux2_1_11_X[0]), - .X(out[0])); - - sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( - .A1(in[0]), - .A0(in[1]), - .S(sram[0]), - .X(sky130_fd_sc_hd__mux2_1_0_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( - .A1(in[2]), - .A0(in[3]), - .S(sram[0]), - .X(sky130_fd_sc_hd__mux2_1_1_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( - .A1(in[4]), - .A0(in[5]), - .S(sram[0]), - .X(sky130_fd_sc_hd__mux2_1_2_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( - .A1(in[6]), - .A0(in[7]), - .S(sram[0]), - .X(sky130_fd_sc_hd__mux2_1_3_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( - .A1(in[8]), - .A0(in[9]), - .S(sram[0]), - .X(sky130_fd_sc_hd__mux2_1_4_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A1(sky130_fd_sc_hd__mux2_1_0_X[0]), - .A0(sky130_fd_sc_hd__mux2_1_1_X[0]), - .S(sram[1]), - .X(sky130_fd_sc_hd__mux2_1_5_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A1(sky130_fd_sc_hd__mux2_1_2_X[0]), - .A0(sky130_fd_sc_hd__mux2_1_3_X[0]), - .S(sram[1]), - .X(sky130_fd_sc_hd__mux2_1_6_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( - .A1(sky130_fd_sc_hd__mux2_1_4_X[0]), - .A0(in[10]), - .S(sram[1]), - .X(sky130_fd_sc_hd__mux2_1_7_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( - .A1(in[11]), - .A0(const1_0_const1[0]), - .S(sram[1]), - .X(sky130_fd_sc_hd__mux2_1_8_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A1(sky130_fd_sc_hd__mux2_1_5_X[0]), - .A0(sky130_fd_sc_hd__mux2_1_6_X[0]), - .S(sram[2]), - .X(sky130_fd_sc_hd__mux2_1_9_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A1(sky130_fd_sc_hd__mux2_1_7_X[0]), - .A0(sky130_fd_sc_hd__mux2_1_8_X[0]), - .S(sram[2]), - .X(sky130_fd_sc_hd__mux2_1_10_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A1(sky130_fd_sc_hd__mux2_1_9_X[0]), - .A0(sky130_fd_sc_hd__mux2_1_10_X[0]), - .S(sram[3]), - .X(sky130_fd_sc_hd__mux2_1_11_X[0])); - -endmodule -// - - - -// -module mux_tree_tapbuf_size16(in, - sram, - sram_inv, - out); -// -input [0:15] in; -// -input [0:4] sram; -// -input [0:4] sram_inv; -// -output [0:0] out; - -// -// - - -// -// - - -wire [0:0] const1_0_const1; -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_14_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_15_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X; - -// -// -// -// - - const1 const1_0_ ( - .const1(const1_0_const1[0])); - - sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A(sky130_fd_sc_hd__mux2_1_15_X[0]), - .X(out[0])); - - sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( - .A1(in[0]), - .A0(in[1]), - .S(sram[0]), - .X(sky130_fd_sc_hd__mux2_1_0_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A1(sky130_fd_sc_hd__mux2_1_0_X[0]), - .A0(in[2]), - .S(sram[1]), - .X(sky130_fd_sc_hd__mux2_1_1_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A1(in[3]), - .A0(in[4]), - .S(sram[1]), - .X(sky130_fd_sc_hd__mux2_1_2_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( - .A1(in[5]), - .A0(in[6]), - .S(sram[1]), - .X(sky130_fd_sc_hd__mux2_1_3_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( - .A1(in[7]), - .A0(in[8]), - .S(sram[1]), - .X(sky130_fd_sc_hd__mux2_1_4_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( - .A1(in[9]), - .A0(in[10]), - .S(sram[1]), - .X(sky130_fd_sc_hd__mux2_1_5_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( - .A1(in[11]), - .A0(in[12]), - .S(sram[1]), - .X(sky130_fd_sc_hd__mux2_1_6_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( - .A1(in[13]), - .A0(in[14]), - .S(sram[1]), - .X(sky130_fd_sc_hd__mux2_1_7_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( - .A1(in[15]), - .A0(const1_0_const1[0]), - .S(sram[1]), - .X(sky130_fd_sc_hd__mux2_1_8_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A1(sky130_fd_sc_hd__mux2_1_1_X[0]), - .A0(sky130_fd_sc_hd__mux2_1_2_X[0]), - .S(sram[2]), - .X(sky130_fd_sc_hd__mux2_1_9_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A1(sky130_fd_sc_hd__mux2_1_3_X[0]), - .A0(sky130_fd_sc_hd__mux2_1_4_X[0]), - .S(sram[2]), - .X(sky130_fd_sc_hd__mux2_1_10_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( - .A1(sky130_fd_sc_hd__mux2_1_5_X[0]), - .A0(sky130_fd_sc_hd__mux2_1_6_X[0]), - .S(sram[2]), - .X(sky130_fd_sc_hd__mux2_1_11_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( - .A1(sky130_fd_sc_hd__mux2_1_7_X[0]), - .A0(sky130_fd_sc_hd__mux2_1_8_X[0]), - .S(sram[2]), - .X(sky130_fd_sc_hd__mux2_1_12_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A1(sky130_fd_sc_hd__mux2_1_9_X[0]), - .A0(sky130_fd_sc_hd__mux2_1_10_X[0]), - .S(sram[3]), - .X(sky130_fd_sc_hd__mux2_1_13_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( - .A1(sky130_fd_sc_hd__mux2_1_11_X[0]), - .A0(sky130_fd_sc_hd__mux2_1_12_X[0]), - .S(sram[3]), - .X(sky130_fd_sc_hd__mux2_1_14_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( - .A1(sky130_fd_sc_hd__mux2_1_13_X[0]), - .A0(sky130_fd_sc_hd__mux2_1_14_X[0]), - .S(sram[4]), - .X(sky130_fd_sc_hd__mux2_1_15_X[0])); - -endmodule -// - - - -// -module mux_tree_tapbuf_size3(in, - sram, - sram_inv, - out); -// -input [0:2] in; -// -input [0:1] sram; -// -input [0:1] sram_inv; -// -output [0:0] out; - -// -// - - -// -// - - -wire [0:0] const1_0_const1; -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X; - -// -// -// -// - - const1 const1_0_ ( - .const1(const1_0_const1[0])); - - sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A(sky130_fd_sc_hd__mux2_1_2_X[0]), - .X(out[0])); - - sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( - .A1(in[0]), - .A0(in[1]), - .S(sram[0]), - .X(sky130_fd_sc_hd__mux2_1_0_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( - .A1(in[2]), - .A0(const1_0_const1[0]), - .S(sram[0]), - .X(sky130_fd_sc_hd__mux2_1_1_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A1(sky130_fd_sc_hd__mux2_1_0_X[0]), - .A0(sky130_fd_sc_hd__mux2_1_1_X[0]), - .S(sram[1]), - .X(sky130_fd_sc_hd__mux2_1_2_X[0])); - -endmodule -// - - - -// -module mux_tree_tapbuf_size9(in, - sram, - sram_inv, - out); -// -input [0:8] in; -// -input [0:3] sram; -// -input [0:3] sram_inv; -// -output [0:0] out; - -// -// - - -// -// - - -wire [0:0] const1_0_const1; -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X; - -// -// -// -// - - const1 const1_0_ ( - .const1(const1_0_const1[0])); - - sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A(sky130_fd_sc_hd__mux2_1_8_X[0]), - .X(out[0])); - - sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( - .A1(in[0]), - .A0(in[1]), - .S(sram[0]), - .X(sky130_fd_sc_hd__mux2_1_0_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( - .A1(in[2]), - .A0(in[3]), - .S(sram[0]), - .X(sky130_fd_sc_hd__mux2_1_1_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A1(sky130_fd_sc_hd__mux2_1_0_X[0]), - .A0(sky130_fd_sc_hd__mux2_1_1_X[0]), - .S(sram[1]), - .X(sky130_fd_sc_hd__mux2_1_2_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A1(in[4]), - .A0(in[5]), - .S(sram[1]), - .X(sky130_fd_sc_hd__mux2_1_3_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( - .A1(in[6]), - .A0(in[7]), - .S(sram[1]), - .X(sky130_fd_sc_hd__mux2_1_4_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( - .A1(in[8]), - .A0(const1_0_const1[0]), - .S(sram[1]), - .X(sky130_fd_sc_hd__mux2_1_5_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A1(sky130_fd_sc_hd__mux2_1_2_X[0]), - .A0(sky130_fd_sc_hd__mux2_1_3_X[0]), - .S(sram[2]), - .X(sky130_fd_sc_hd__mux2_1_6_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A1(sky130_fd_sc_hd__mux2_1_4_X[0]), - .A0(sky130_fd_sc_hd__mux2_1_5_X[0]), - .S(sram[2]), - .X(sky130_fd_sc_hd__mux2_1_7_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A1(sky130_fd_sc_hd__mux2_1_6_X[0]), - .A0(sky130_fd_sc_hd__mux2_1_7_X[0]), - .S(sram[3]), - .X(sky130_fd_sc_hd__mux2_1_8_X[0])); - -endmodule -// - - - -// -module mux_tree_tapbuf_size14(in, - sram, - sram_inv, - out); -// -input [0:13] in; -// -input [0:3] sram; -// -input [0:3] sram_inv; -// -output [0:0] out; - -// -// - - -// -// - - -wire [0:0] const1_0_const1; -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X; - -// -// -// -// - - const1 const1_0_ ( - .const1(const1_0_const1[0])); - - sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A(sky130_fd_sc_hd__mux2_1_13_X[0]), - .X(out[0])); - - sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( - .A1(in[0]), - .A0(in[1]), - .S(sram[0]), - .X(sky130_fd_sc_hd__mux2_1_0_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( - .A1(in[2]), - .A0(in[3]), - .S(sram[0]), - .X(sky130_fd_sc_hd__mux2_1_1_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( - .A1(in[4]), - .A0(in[5]), - .S(sram[0]), - .X(sky130_fd_sc_hd__mux2_1_2_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( - .A1(in[6]), - .A0(in[7]), - .S(sram[0]), - .X(sky130_fd_sc_hd__mux2_1_3_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( - .A1(in[8]), - .A0(in[9]), - .S(sram[0]), - .X(sky130_fd_sc_hd__mux2_1_4_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( - .A1(in[10]), - .A0(in[11]), - .S(sram[0]), - .X(sky130_fd_sc_hd__mux2_1_5_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( - .A1(in[12]), - .A0(in[13]), - .S(sram[0]), - .X(sky130_fd_sc_hd__mux2_1_6_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A1(sky130_fd_sc_hd__mux2_1_0_X[0]), - .A0(sky130_fd_sc_hd__mux2_1_1_X[0]), - .S(sram[1]), - .X(sky130_fd_sc_hd__mux2_1_7_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A1(sky130_fd_sc_hd__mux2_1_2_X[0]), - .A0(sky130_fd_sc_hd__mux2_1_3_X[0]), - .S(sram[1]), - .X(sky130_fd_sc_hd__mux2_1_8_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( - .A1(sky130_fd_sc_hd__mux2_1_4_X[0]), - .A0(sky130_fd_sc_hd__mux2_1_5_X[0]), - .S(sram[1]), - .X(sky130_fd_sc_hd__mux2_1_9_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( - .A1(sky130_fd_sc_hd__mux2_1_6_X[0]), - .A0(const1_0_const1[0]), - .S(sram[1]), - .X(sky130_fd_sc_hd__mux2_1_10_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A1(sky130_fd_sc_hd__mux2_1_7_X[0]), - .A0(sky130_fd_sc_hd__mux2_1_8_X[0]), - .S(sram[2]), - .X(sky130_fd_sc_hd__mux2_1_11_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A1(sky130_fd_sc_hd__mux2_1_9_X[0]), - .A0(sky130_fd_sc_hd__mux2_1_10_X[0]), - .S(sram[2]), - .X(sky130_fd_sc_hd__mux2_1_12_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A1(sky130_fd_sc_hd__mux2_1_11_X[0]), - .A0(sky130_fd_sc_hd__mux2_1_12_X[0]), - .S(sram[3]), - .X(sky130_fd_sc_hd__mux2_1_13_X[0])); - -endmodule -// - - - -// -module mux_tree_size2(in, - sram, - sram_inv, - out); -// -input [0:1] in; -// -input [0:1] sram; -// -input [0:1] sram_inv; -// -output [0:0] out; - -// -// - - -// -// - - -wire [0:0] const1_0_const1; -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X; - -// -// -// -// - - const1 const1_0_ ( - .const1(const1_0_const1[0])); - - sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( - .A1(in[0]), - .A0(in[1]), - .S(sram[0]), - .X(sky130_fd_sc_hd__mux2_1_0_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A1(sky130_fd_sc_hd__mux2_1_0_X[0]), - .A0(const1_0_const1[0]), - .S(sram[1]), - .X(out[0])); - -endmodule -// - - - -// -module frac_lut4_mux(in, - sram, - sram_inv, - lut3_out, - lut4_out); -// -input [0:15] in; -// -input [0:3] sram; -// -input [0:3] sram_inv; -// -output [0:1] lut3_out; -// -output [0:0] lut4_out; - -// -// - - -// -// - - -wire [0:0] sky130_fd_sc_hd__buf_2_3_X; -wire [0:0] sky130_fd_sc_hd__buf_2_4_X; -wire [0:0] sky130_fd_sc_hd__buf_2_5_X; -wire [0:0] sky130_fd_sc_hd__buf_2_6_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_14_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X; - -// -// -// -// - - sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ ( - .A(sky130_fd_sc_hd__mux2_1_12_X[0]), - .X(lut3_out[0])); - - sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ ( - .A(sky130_fd_sc_hd__mux2_1_13_X[0]), - .X(lut3_out[1])); - - sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_2_ ( - .A(sky130_fd_sc_hd__mux2_1_14_X[0]), - .X(lut4_out[0])); - - sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ ( - .A(sky130_fd_sc_hd__mux2_1_8_X[0]), - .X(sky130_fd_sc_hd__buf_2_3_X[0])); - - sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_4_ ( - .A(sky130_fd_sc_hd__mux2_1_9_X[0]), - .X(sky130_fd_sc_hd__buf_2_4_X[0])); - - sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_5_ ( - .A(sky130_fd_sc_hd__mux2_1_10_X[0]), - .X(sky130_fd_sc_hd__buf_2_5_X[0])); - - sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_6_ ( - .A(sky130_fd_sc_hd__mux2_1_11_X[0]), - .X(sky130_fd_sc_hd__buf_2_6_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( - .A1(in[0]), - .A0(in[1]), - .S(sram[0]), - .X(sky130_fd_sc_hd__mux2_1_0_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( - .A1(in[2]), - .A0(in[3]), - .S(sram[0]), - .X(sky130_fd_sc_hd__mux2_1_1_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( - .A1(in[4]), - .A0(in[5]), - .S(sram[0]), - .X(sky130_fd_sc_hd__mux2_1_2_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( - .A1(in[6]), - .A0(in[7]), - .S(sram[0]), - .X(sky130_fd_sc_hd__mux2_1_3_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( - .A1(in[8]), - .A0(in[9]), - .S(sram[0]), - .X(sky130_fd_sc_hd__mux2_1_4_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( - .A1(in[10]), - .A0(in[11]), - .S(sram[0]), - .X(sky130_fd_sc_hd__mux2_1_5_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( - .A1(in[12]), - .A0(in[13]), - .S(sram[0]), - .X(sky130_fd_sc_hd__mux2_1_6_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( - .A1(in[14]), - .A0(in[15]), - .S(sram[0]), - .X(sky130_fd_sc_hd__mux2_1_7_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A1(sky130_fd_sc_hd__mux2_1_0_X[0]), - .A0(sky130_fd_sc_hd__mux2_1_1_X[0]), - .S(sram[1]), - .X(sky130_fd_sc_hd__mux2_1_8_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A1(sky130_fd_sc_hd__mux2_1_2_X[0]), - .A0(sky130_fd_sc_hd__mux2_1_3_X[0]), - .S(sram[1]), - .X(sky130_fd_sc_hd__mux2_1_9_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( - .A1(sky130_fd_sc_hd__mux2_1_4_X[0]), - .A0(sky130_fd_sc_hd__mux2_1_5_X[0]), - .S(sram[1]), - .X(sky130_fd_sc_hd__mux2_1_10_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( - .A1(sky130_fd_sc_hd__mux2_1_6_X[0]), - .A0(sky130_fd_sc_hd__mux2_1_7_X[0]), - .S(sram[1]), - .X(sky130_fd_sc_hd__mux2_1_11_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A1(sky130_fd_sc_hd__buf_2_3_X[0]), - .A0(sky130_fd_sc_hd__buf_2_4_X[0]), - .S(sram[2]), - .X(sky130_fd_sc_hd__mux2_1_12_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A1(sky130_fd_sc_hd__buf_2_5_X[0]), - .A0(sky130_fd_sc_hd__buf_2_6_X[0]), - .S(sram[2]), - .X(sky130_fd_sc_hd__mux2_1_13_X[0])); - - sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A1(sky130_fd_sc_hd__mux2_1_12_X[0]), - .A0(sky130_fd_sc_hd__mux2_1_13_X[0]), - .S(sram[3]), - .X(sky130_fd_sc_hd__mux2_1_14_X[0])); - -endmodule -// - - - diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/wires.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/wires.v deleted file mode 100644 index 8bbc5d8..0000000 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/wires.v +++ /dev/null @@ -1,34 +0,0 @@ -// -// -// -// -// -// -// -// -`timescale 1ns / 1ps - -// -// -module direct_interc(in, - out); -// -input [0:0] in; -// -output [0:0] out; - -// -// - - -// -// - -wire [0:0] in; -wire [0:0] out; - assign out[0] = in[0]; -endmodule -// - - -// diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/top_include_netlists.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/top_include_netlists.v deleted file mode 100644 index 50c918d..0000000 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/top_include_netlists.v +++ /dev/null @@ -1,31 +0,0 @@ -// -// -// -// -// -// -// -// -`timescale 1ns / 1ps - -// -`include "./SRC/define_simulation.v" - -// -`include "./SRC/fabric_netlists.v" - -`ifdef AUTOCHECKED_SIMULATION - `include "top_output_verilog.v" -`endif - -`ifdef ENABLE_FORMAL_VERIFICATION - `include "./SRC/top_top_formal_verification.v" - `ifdef FORMAL_SIMULATION - `include "./SRC/top_formal_random_top_tb.v" - `endif -`endif - -`ifdef AUTOCHECKED_SIMULATION - `include "./SRC/top_autocheck_top_tb.v" -`endif - diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/top_top_formal_verification.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/top_top_formal_verification.v deleted file mode 100644 index 28aecd5..0000000 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/top_top_formal_verification.v +++ /dev/null @@ -1,1267 +0,0 @@ -// -// -// -// -// -// -// -// -`timescale 1ns / 1ps - -module top_top_formal_verification ( -input [0:0] a_fm, -input [0:0] b_fm, -output [0:0] out:c_fm); - -// -wire [0:0] prog_clk; -wire [0:0] Test_en; -wire [0:0] clk; -wire [0:17] gfpga_pad_EMBEDDED_IO_SOC_IN; -wire [0:17] gfpga_pad_EMBEDDED_IO_SOC_OUT; -wire [0:17] gfpga_pad_EMBEDDED_IO_SOC_DIR; -wire [0:0] ccff_head; -wire [0:0] ccff_tail; - -// - fpga_top U0_formal_verification ( - .prog_clk(prog_clk[0]), - .Test_en(Test_en[0]), - .clk(clk[0]), - .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[0:17]), - .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[0:17]), - .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[0:17]), - .ccff_head(ccff_head[0]), - .ccff_tail(ccff_tail[0])); - -// - assign prog_clk[0] = 1'b0; - assign Test_en[0] = 1'b0; -// - -// -// - assign gfpga_pad_EMBEDDED_IO_SOC_IN[16] = a_fm[0]; - -// - assign gfpga_pad_EMBEDDED_IO_SOC_IN[6] = b_fm[0]; - -// - assign out:c_fm[0] = gfpga_pad_EMBEDDED_IO_SOC_OUT[9]; - -// - assign gfpga_pad_EMBEDDED_IO_SOC_IN[0] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[1] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[2] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[3] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[4] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[5] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[7] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[8] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[9] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[10] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[11] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[12] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[13] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[14] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[15] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_IN[17] = 1'b0; - - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[0] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[1] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[2] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[3] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[4] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[5] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[6] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[7] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[8] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[10] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[11] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[12] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[13] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[14] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[15] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[16] = 1'b0; - assign gfpga_pad_EMBEDDED_IO_SOC_OUT[17] = 1'b0; - -// -`ifdef ICARUS_SIMULATOR -// - assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0:16] = {17{1'b0}}; - assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0:16] = {17{1'b0}}; - assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0:16] = {17{1'b0}}; - assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0:16] = {17{1'b0}}; - assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0:16] = {17{1'b0}}; - assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0:16] = {17{1'b0}}; - assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0:16] = {17{1'b0}}; - assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0:16] = 17'b00000000110000001; - assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = 2'b01; - assign U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0:16] = {17{1'b0}}; - assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0:16] = {17{1'b0}}; - assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0:16] = {17{1'b0}}; - assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0:16] = {17{1'b0}}; - assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0:16] = {17{1'b0}}; - assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0:16] = {17{1'b0}}; - assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0:16] = {17{1'b0}}; - assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0:16] = {17{1'b0}}; - assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0:16] = {17{1'b0}}; - assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0:16] = {17{1'b0}}; - assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0:16] = {17{1'b0}}; - assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0:16] = {17{1'b0}}; - assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0:16] = {17{1'b0}}; - assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0:16] = {17{1'b0}}; - assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0:16] = {17{1'b0}}; - assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0:16] = {17{1'b0}}; - assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_2__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0:16] = {17{1'b0}}; - assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0:16] = {17{1'b0}}; - assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0:16] = {17{1'b0}}; - assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0:16] = {17{1'b0}}; - assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0:16] = {17{1'b0}}; - assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0:16] = {17{1'b0}}; - assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0:16] = {17{1'b0}}; - assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0:16] = {17{1'b0}}; - assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.grid_io_top_top_1__3_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0] = 1'b1; - assign U0_formal_verification.grid_io_top_top_2__3_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0] = 1'b1; - assign U0_formal_verification.grid_io_right_right_3__1_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0] = 1'b1; - assign U0_formal_verification.grid_io_right_right_3__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0] = 1'b1; - assign U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0] = 1'b1; - assign U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0] = 1'b1; - assign U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0] = 1'b1; - assign U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0] = 1'b1; - assign U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0] = 1'b1; - assign U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0] = 1'b0; - assign U0_formal_verification.grid_io_bottom_bottom_2__0_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0] = 1'b1; - assign U0_formal_verification.grid_io_bottom_bottom_2__0_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0] = 1'b1; - assign U0_formal_verification.grid_io_bottom_bottom_2__0_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0] = 1'b1; - assign U0_formal_verification.grid_io_bottom_bottom_2__0_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0] = 1'b1; - assign U0_formal_verification.grid_io_bottom_bottom_2__0_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0] = 1'b1; - assign U0_formal_verification.grid_io_bottom_bottom_2__0_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0] = 1'b1; - assign U0_formal_verification.grid_io_left_left_0__1_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0] = 1'b1; - assign U0_formal_verification.grid_io_left_left_0__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0] = 1'b1; - assign U0_formal_verification.sb_0__0_.mem_top_track_0.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_0__0_.mem_top_track_4.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_0__0_.mem_top_track_8.mem_out[0:1] = {2{1'b1}}; - assign U0_formal_verification.sb_0__0_.mem_top_track_24.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_0__0_.mem_right_track_0.mem_out[0:2] = 3'b001; - assign U0_formal_verification.sb_0__0_.mem_right_track_2.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_0__0_.mem_right_track_4.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_0__0_.mem_right_track_6.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_0__0_.mem_right_track_8.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_0__0_.mem_right_track_10.mem_out[0:1] = {2{1'b1}}; - assign U0_formal_verification.sb_0__0_.mem_right_track_12.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_0__0_.mem_right_track_14.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_0__0_.mem_right_track_16.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_0__0_.mem_right_track_18.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_0__0_.mem_right_track_24.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_0__0_.mem_right_track_26.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_0__0_.mem_right_track_28.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_0__0_.mem_right_track_30.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_0__0_.mem_right_track_32.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_0__0_.mem_right_track_34.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_0__1_.mem_top_track_0.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_0__1_.mem_top_track_2.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_0__1_.mem_top_track_4.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_0__1_.mem_top_track_8.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_0__1_.mem_top_track_16.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_0__1_.mem_top_track_24.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_0__1_.mem_top_track_32.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_0__1_.mem_right_track_0.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_0__1_.mem_right_track_2.mem_out[0:2] = 3'b100; - assign U0_formal_verification.sb_0__1_.mem_right_track_4.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_0__1_.mem_right_track_6.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_0__1_.mem_right_track_8.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_0__1_.mem_right_track_10.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_0__1_.mem_right_track_12.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_0__1_.mem_right_track_14.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_0__1_.mem_right_track_16.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_0__1_.mem_right_track_18.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_0__1_.mem_right_track_20.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_0__1_.mem_right_track_22.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_0__1_.mem_right_track_24.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_0__1_.mem_right_track_26.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_0__1_.mem_right_track_28.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_0__1_.mem_right_track_30.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_0__1_.mem_right_track_32.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_0__1_.mem_right_track_34.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_0__1_.mem_right_track_36.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_0__1_.mem_bottom_track_1.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_0__1_.mem_bottom_track_3.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_0__1_.mem_bottom_track_5.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_0__1_.mem_bottom_track_9.mem_out[0:2] = 3'b110; - assign U0_formal_verification.sb_0__1_.mem_bottom_track_17.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_0__1_.mem_bottom_track_25.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_0__1_.mem_bottom_track_33.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_0__2_.mem_right_track_0.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_0__2_.mem_right_track_2.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_0__2_.mem_right_track_4.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_0__2_.mem_right_track_6.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_0__2_.mem_right_track_8.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_0__2_.mem_right_track_10.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_0__2_.mem_right_track_12.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_0__2_.mem_right_track_14.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_0__2_.mem_right_track_16.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_0__2_.mem_right_track_18.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_0__2_.mem_right_track_20.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_0__2_.mem_right_track_22.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_0__2_.mem_right_track_24.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_0__2_.mem_right_track_26.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_0__2_.mem_right_track_28.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_0__2_.mem_right_track_30.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_0__2_.mem_right_track_32.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_0__2_.mem_right_track_34.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_0__2_.mem_right_track_36.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_0__2_.mem_right_track_38.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_0__2_.mem_bottom_track_1.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_0__2_.mem_bottom_track_5.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_0__2_.mem_bottom_track_9.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_0__2_.mem_bottom_track_25.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_1__0_.mem_top_track_0.mem_out[0:3] = 4'b0010; - assign U0_formal_verification.sb_1__0_.mem_top_track_2.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_1__0_.mem_top_track_4.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_1__0_.mem_top_track_6.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_1__0_.mem_top_track_8.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_1__0_.mem_top_track_10.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_1__0_.mem_top_track_12.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_1__0_.mem_top_track_14.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_1__0_.mem_top_track_16.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_1__0_.mem_top_track_18.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_1__0_.mem_top_track_20.mem_out[0:1] = {2{1'b1}}; - assign U0_formal_verification.sb_1__0_.mem_top_track_22.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_1__0_.mem_top_track_24.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_1__0_.mem_top_track_38.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_1__0_.mem_right_track_0.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_1__0_.mem_right_track_2.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.sb_1__0_.mem_right_track_4.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.sb_1__0_.mem_right_track_8.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_1__0_.mem_right_track_16.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_1__0_.mem_right_track_24.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_1__0_.mem_right_track_32.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_1__0_.mem_left_track_1.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.sb_1__0_.mem_left_track_3.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_1__0_.mem_left_track_5.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.sb_1__0_.mem_left_track_9.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_1__0_.mem_left_track_17.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_1__0_.mem_left_track_25.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_1__0_.mem_left_track_33.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_1__1_.mem_top_track_0.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.sb_1__1_.mem_top_track_2.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.sb_1__1_.mem_top_track_4.mem_out[0:4] = {5{1'b0}}; - assign U0_formal_verification.sb_1__1_.mem_top_track_8.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.sb_1__1_.mem_top_track_16.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.sb_1__1_.mem_top_track_24.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.sb_1__1_.mem_top_track_32.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_1__1_.mem_right_track_0.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.sb_1__1_.mem_right_track_2.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.sb_1__1_.mem_right_track_4.mem_out[0:4] = {5{1'b0}}; - assign U0_formal_verification.sb_1__1_.mem_right_track_8.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.sb_1__1_.mem_right_track_16.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.sb_1__1_.mem_right_track_24.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.sb_1__1_.mem_right_track_32.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_1__1_.mem_bottom_track_1.mem_out[0:3] = 4'b0110; - assign U0_formal_verification.sb_1__1_.mem_bottom_track_3.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.sb_1__1_.mem_bottom_track_5.mem_out[0:4] = {5{1'b0}}; - assign U0_formal_verification.sb_1__1_.mem_bottom_track_9.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.sb_1__1_.mem_bottom_track_17.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.sb_1__1_.mem_bottom_track_25.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.sb_1__1_.mem_bottom_track_33.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_1__1_.mem_left_track_1.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.sb_1__1_.mem_left_track_3.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.sb_1__1_.mem_left_track_5.mem_out[0:4] = {5{1'b0}}; - assign U0_formal_verification.sb_1__1_.mem_left_track_9.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.sb_1__1_.mem_left_track_17.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.sb_1__1_.mem_left_track_25.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.sb_1__1_.mem_left_track_33.mem_out[0:2] = 3'b001; - assign U0_formal_verification.sb_1__2_.mem_right_track_0.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.sb_1__2_.mem_right_track_2.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.sb_1__2_.mem_right_track_4.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.sb_1__2_.mem_right_track_8.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.sb_1__2_.mem_right_track_16.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_1__2_.mem_right_track_24.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_1__2_.mem_right_track_32.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_1__2_.mem_bottom_track_1.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_1__2_.mem_bottom_track_3.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_1__2_.mem_bottom_track_5.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_1__2_.mem_bottom_track_7.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_1__2_.mem_bottom_track_9.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_1__2_.mem_bottom_track_11.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_1__2_.mem_bottom_track_13.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_1__2_.mem_bottom_track_15.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_1__2_.mem_bottom_track_17.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_1__2_.mem_bottom_track_19.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_1__2_.mem_bottom_track_21.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_1__2_.mem_bottom_track_23.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_1__2_.mem_bottom_track_25.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_1__2_.mem_bottom_track_27.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_1__2_.mem_left_track_1.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.sb_1__2_.mem_left_track_3.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.sb_1__2_.mem_left_track_5.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.sb_1__2_.mem_left_track_9.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.sb_1__2_.mem_left_track_17.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_1__2_.mem_left_track_25.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_1__2_.mem_left_track_33.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_2__0_.mem_top_track_0.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_2__0_.mem_top_track_2.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_2__0_.mem_top_track_4.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_2__0_.mem_top_track_6.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_2__0_.mem_top_track_8.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__0_.mem_top_track_10.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__0_.mem_top_track_12.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__0_.mem_top_track_14.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__0_.mem_top_track_16.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__0_.mem_top_track_18.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__0_.mem_top_track_20.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__0_.mem_top_track_22.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__0_.mem_top_track_24.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__0_.mem_top_track_26.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__0_.mem_left_track_1.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_2__0_.mem_left_track_3.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_2__0_.mem_left_track_5.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_2__0_.mem_left_track_7.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_2__0_.mem_left_track_9.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__0_.mem_left_track_11.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__0_.mem_left_track_13.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__0_.mem_left_track_15.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__0_.mem_left_track_17.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__0_.mem_left_track_19.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__0_.mem_left_track_25.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__0_.mem_left_track_27.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__0_.mem_left_track_29.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__0_.mem_left_track_31.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__0_.mem_left_track_33.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__0_.mem_left_track_35.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__1_.mem_top_track_0.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.sb_2__1_.mem_top_track_2.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.sb_2__1_.mem_top_track_4.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.sb_2__1_.mem_top_track_8.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.sb_2__1_.mem_top_track_16.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_2__1_.mem_top_track_24.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_2__1_.mem_top_track_32.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_2__1_.mem_bottom_track_1.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.sb_2__1_.mem_bottom_track_3.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.sb_2__1_.mem_bottom_track_5.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.sb_2__1_.mem_bottom_track_9.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.sb_2__1_.mem_bottom_track_17.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_2__1_.mem_bottom_track_25.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_2__1_.mem_bottom_track_33.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_2__1_.mem_left_track_1.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_2__1_.mem_left_track_3.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_2__1_.mem_left_track_5.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_2__1_.mem_left_track_7.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_2__1_.mem_left_track_9.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_2__1_.mem_left_track_11.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_2__1_.mem_left_track_13.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_2__1_.mem_left_track_15.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_2__1_.mem_left_track_17.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__1_.mem_left_track_19.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__1_.mem_left_track_21.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__1_.mem_left_track_23.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__1_.mem_left_track_25.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__1_.mem_left_track_29.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__1_.mem_left_track_31.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__1_.mem_left_track_33.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__1_.mem_left_track_35.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__1_.mem_left_track_37.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__1_.mem_left_track_39.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__2_.mem_bottom_track_1.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_2__2_.mem_bottom_track_3.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_2__2_.mem_bottom_track_5.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_2__2_.mem_bottom_track_7.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_2__2_.mem_bottom_track_9.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__2_.mem_bottom_track_11.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__2_.mem_bottom_track_13.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__2_.mem_bottom_track_15.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__2_.mem_bottom_track_17.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__2_.mem_bottom_track_19.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__2_.mem_bottom_track_21.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__2_.mem_bottom_track_23.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__2_.mem_bottom_track_25.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__2_.mem_bottom_track_27.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__2_.mem_bottom_track_29.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__2_.mem_left_track_1.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_2__2_.mem_left_track_3.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_2__2_.mem_left_track_5.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_2__2_.mem_left_track_7.mem_out[0:2] = {3{1'b0}}; - assign U0_formal_verification.sb_2__2_.mem_left_track_9.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__2_.mem_left_track_11.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__2_.mem_left_track_13.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__2_.mem_left_track_15.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__2_.mem_left_track_17.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__2_.mem_left_track_19.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__2_.mem_left_track_21.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__2_.mem_left_track_23.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__2_.mem_left_track_25.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__2_.mem_left_track_27.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__2_.mem_left_track_29.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__2_.mem_left_track_31.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__2_.mem_left_track_33.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__2_.mem_left_track_35.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__2_.mem_left_track_37.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.sb_2__2_.mem_left_track_39.mem_out[0:1] = {2{1'b0}}; - assign U0_formal_verification.cbx_1__0_.mem_top_ipin_0.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__0_.mem_top_ipin_1.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__0_.mem_top_ipin_2.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__0_.mem_top_ipin_3.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__0_.mem_top_ipin_4.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__0_.mem_top_ipin_5.mem_out[0:3] = 4'b1101; - assign U0_formal_verification.cbx_1__1_.mem_top_ipin_0.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__1_.mem_top_ipin_1.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__1_.mem_top_ipin_2.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__1_.mem_top_ipin_3.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__1_.mem_top_ipin_4.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__1_.mem_top_ipin_5.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__1_.mem_top_ipin_6.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__1_.mem_top_ipin_7.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__1_.mem_top_ipin_8.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__1_.mem_top_ipin_9.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__1_.mem_top_ipin_10.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__1_.mem_top_ipin_11.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__1_.mem_top_ipin_12.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__1_.mem_top_ipin_13.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__1_.mem_top_ipin_14.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__1_.mem_top_ipin_15.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__2_.mem_bottom_ipin_0.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__2_.mem_top_ipin_0.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__2_.mem_top_ipin_1.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__2_.mem_top_ipin_2.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__2_.mem_top_ipin_3.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__2_.mem_top_ipin_4.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__2_.mem_top_ipin_5.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__2_.mem_top_ipin_6.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__2_.mem_top_ipin_7.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__2_.mem_top_ipin_8.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__2_.mem_top_ipin_9.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__2_.mem_top_ipin_10.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__2_.mem_top_ipin_11.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__2_.mem_top_ipin_12.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__2_.mem_top_ipin_13.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__2_.mem_top_ipin_14.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_1__2_.mem_top_ipin_15.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__0_.mem_top_ipin_0.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__0_.mem_top_ipin_1.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__0_.mem_top_ipin_2.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__0_.mem_top_ipin_3.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__0_.mem_top_ipin_4.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__0_.mem_top_ipin_5.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__1_.mem_top_ipin_0.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__1_.mem_top_ipin_1.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__1_.mem_top_ipin_2.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__1_.mem_top_ipin_3.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__1_.mem_top_ipin_4.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__1_.mem_top_ipin_5.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__1_.mem_top_ipin_6.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__1_.mem_top_ipin_7.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__1_.mem_top_ipin_8.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__1_.mem_top_ipin_9.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__1_.mem_top_ipin_10.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__1_.mem_top_ipin_11.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__1_.mem_top_ipin_12.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__1_.mem_top_ipin_13.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__1_.mem_top_ipin_14.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__1_.mem_top_ipin_15.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__2_.mem_bottom_ipin_0.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__2_.mem_top_ipin_0.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__2_.mem_top_ipin_1.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__2_.mem_top_ipin_2.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__2_.mem_top_ipin_3.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__2_.mem_top_ipin_4.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__2_.mem_top_ipin_5.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__2_.mem_top_ipin_6.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__2_.mem_top_ipin_7.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__2_.mem_top_ipin_8.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__2_.mem_top_ipin_9.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__2_.mem_top_ipin_10.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__2_.mem_top_ipin_11.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__2_.mem_top_ipin_12.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__2_.mem_top_ipin_13.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__2_.mem_top_ipin_14.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cbx_2__2_.mem_top_ipin_15.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cby_0__1_.mem_right_ipin_0.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cby_0__2_.mem_right_ipin_0.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cby_1__1_.mem_right_ipin_0.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cby_1__1_.mem_right_ipin_1.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cby_1__1_.mem_right_ipin_2.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cby_1__1_.mem_right_ipin_3.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cby_1__1_.mem_right_ipin_4.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cby_1__1_.mem_right_ipin_5.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cby_1__1_.mem_right_ipin_6.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cby_1__1_.mem_right_ipin_7.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cby_1__1_.mem_right_ipin_8.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cby_1__1_.mem_right_ipin_9.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cby_1__1_.mem_right_ipin_10.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cby_1__1_.mem_right_ipin_11.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cby_1__1_.mem_right_ipin_12.mem_out[0:3] = {4{1'b1}}; - assign U0_formal_verification.cby_1__1_.mem_right_ipin_13.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cby_1__1_.mem_right_ipin_14.mem_out[0:3] = 4'b0111; - assign U0_formal_verification.cby_1__1_.mem_right_ipin_15.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cby_1__2_.mem_right_ipin_0.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cby_1__2_.mem_right_ipin_1.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cby_1__2_.mem_right_ipin_2.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cby_1__2_.mem_right_ipin_3.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cby_1__2_.mem_right_ipin_4.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cby_1__2_.mem_right_ipin_5.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cby_1__2_.mem_right_ipin_6.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cby_1__2_.mem_right_ipin_7.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cby_1__2_.mem_right_ipin_8.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cby_1__2_.mem_right_ipin_9.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cby_1__2_.mem_right_ipin_10.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cby_1__2_.mem_right_ipin_11.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cby_1__2_.mem_right_ipin_12.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cby_1__2_.mem_right_ipin_13.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cby_1__2_.mem_right_ipin_14.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cby_1__2_.mem_right_ipin_15.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cby_2__1_.mem_left_ipin_0.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cby_2__1_.mem_right_ipin_0.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cby_2__1_.mem_right_ipin_1.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cby_2__1_.mem_right_ipin_2.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cby_2__1_.mem_right_ipin_3.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cby_2__1_.mem_right_ipin_4.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cby_2__1_.mem_right_ipin_5.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cby_2__1_.mem_right_ipin_6.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cby_2__1_.mem_right_ipin_7.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cby_2__1_.mem_right_ipin_8.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cby_2__1_.mem_right_ipin_9.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cby_2__1_.mem_right_ipin_10.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cby_2__1_.mem_right_ipin_11.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cby_2__1_.mem_right_ipin_12.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cby_2__1_.mem_right_ipin_13.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cby_2__1_.mem_right_ipin_14.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cby_2__1_.mem_right_ipin_15.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cby_2__2_.mem_left_ipin_0.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cby_2__2_.mem_right_ipin_0.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cby_2__2_.mem_right_ipin_1.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cby_2__2_.mem_right_ipin_2.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cby_2__2_.mem_right_ipin_3.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cby_2__2_.mem_right_ipin_4.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cby_2__2_.mem_right_ipin_5.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cby_2__2_.mem_right_ipin_6.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cby_2__2_.mem_right_ipin_7.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cby_2__2_.mem_right_ipin_8.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cby_2__2_.mem_right_ipin_9.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cby_2__2_.mem_right_ipin_10.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cby_2__2_.mem_right_ipin_11.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cby_2__2_.mem_right_ipin_12.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cby_2__2_.mem_right_ipin_13.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cby_2__2_.mem_right_ipin_14.mem_out[0:3] = {4{1'b0}}; - assign U0_formal_verification.cby_2__2_.mem_right_ipin_15.mem_out[0:3] = {4{1'b0}}; -// -`else -// -initial begin - $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0:16], {17{1'b0}}); - $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0:16], {17{1'b0}}); - $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_1.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0:16], {17{1'b0}}); - $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_2.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0:16], {17{1'b0}}); - $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_3.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0:16], {17{1'b0}}); - $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_4.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0:16], {17{1'b0}}); - $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_5.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0:16], {17{1'b0}}); - $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_6.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0.frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0:16], 17'b00000000110000001); - $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1], {2{1'b0}}); - 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$deposit(U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0.mem_frac_logic_out_0.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_0.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.grid_clb_1__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_0.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1], {2{1'b0}}); - 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$deposit(U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_fabric_out_1.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.grid_clb_2__2_.logical_tile_clb_mode_clb__0.logical_tile_clb_mode_default__fle_7.logical_tile_clb_mode_default__fle_mode_physical__fabric_0.mem_ff_0_D_0.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.grid_io_top_top_1__3_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0], 1'b1); - $deposit(U0_formal_verification.grid_io_top_top_2__3_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0], 1'b1); - $deposit(U0_formal_verification.grid_io_right_right_3__1_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0], 1'b1); - $deposit(U0_formal_verification.grid_io_right_right_3__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0], 1'b1); - $deposit(U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0], 1'b1); - $deposit(U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0], 1'b1); - $deposit(U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0], 1'b1); - $deposit(U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0], 1'b1); - $deposit(U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0], 1'b1); - $deposit(U0_formal_verification.grid_io_bottom_bottom_1__0_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0], 1'b0); - $deposit(U0_formal_verification.grid_io_bottom_bottom_2__0_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0], 1'b1); - $deposit(U0_formal_verification.grid_io_bottom_bottom_2__0_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0], 1'b1); - $deposit(U0_formal_verification.grid_io_bottom_bottom_2__0_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0], 1'b1); - $deposit(U0_formal_verification.grid_io_bottom_bottom_2__0_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0], 1'b1); - $deposit(U0_formal_verification.grid_io_bottom_bottom_2__0_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0], 1'b1); - $deposit(U0_formal_verification.grid_io_bottom_bottom_2__0_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0], 1'b1); - $deposit(U0_formal_verification.grid_io_left_left_0__1_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0], 1'b1); - $deposit(U0_formal_verification.grid_io_left_left_0__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem.mem_out[0], 1'b1); - $deposit(U0_formal_verification.sb_0__0_.mem_top_track_0.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__0_.mem_top_track_4.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__0_.mem_top_track_8.mem_out[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.sb_0__0_.mem_top_track_24.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__0_.mem_right_track_0.mem_out[0:2], 3'b001); - $deposit(U0_formal_verification.sb_0__0_.mem_right_track_2.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_0__0_.mem_right_track_4.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_0__0_.mem_right_track_6.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_0__0_.mem_right_track_8.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__0_.mem_right_track_10.mem_out[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.sb_0__0_.mem_right_track_12.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__0_.mem_right_track_14.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__0_.mem_right_track_16.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__0_.mem_right_track_18.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__0_.mem_right_track_24.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__0_.mem_right_track_26.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__0_.mem_right_track_28.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__0_.mem_right_track_30.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__0_.mem_right_track_32.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__0_.mem_right_track_34.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__1_.mem_top_track_0.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_0__1_.mem_top_track_2.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_0__1_.mem_top_track_4.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_0__1_.mem_top_track_8.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_0__1_.mem_top_track_16.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_0__1_.mem_top_track_24.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_0__1_.mem_top_track_32.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_0__1_.mem_right_track_0.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_0__1_.mem_right_track_2.mem_out[0:2], 3'b100); - $deposit(U0_formal_verification.sb_0__1_.mem_right_track_4.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_0__1_.mem_right_track_6.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_0__1_.mem_right_track_8.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_0__1_.mem_right_track_10.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_0__1_.mem_right_track_12.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_0__1_.mem_right_track_14.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_0__1_.mem_right_track_16.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__1_.mem_right_track_18.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__1_.mem_right_track_20.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__1_.mem_right_track_22.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__1_.mem_right_track_24.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_0__1_.mem_right_track_26.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__1_.mem_right_track_28.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__1_.mem_right_track_30.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__1_.mem_right_track_32.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__1_.mem_right_track_34.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__1_.mem_right_track_36.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__1_.mem_bottom_track_1.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_0__1_.mem_bottom_track_3.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_0__1_.mem_bottom_track_5.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_0__1_.mem_bottom_track_9.mem_out[0:2], 3'b110); - $deposit(U0_formal_verification.sb_0__1_.mem_bottom_track_17.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_0__1_.mem_bottom_track_25.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_0__1_.mem_bottom_track_33.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__2_.mem_right_track_0.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_0__2_.mem_right_track_2.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_0__2_.mem_right_track_4.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_0__2_.mem_right_track_6.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_0__2_.mem_right_track_8.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__2_.mem_right_track_10.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__2_.mem_right_track_12.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__2_.mem_right_track_14.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__2_.mem_right_track_16.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__2_.mem_right_track_18.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__2_.mem_right_track_20.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__2_.mem_right_track_22.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__2_.mem_right_track_24.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__2_.mem_right_track_26.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__2_.mem_right_track_28.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__2_.mem_right_track_30.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__2_.mem_right_track_32.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__2_.mem_right_track_34.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__2_.mem_right_track_36.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__2_.mem_right_track_38.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__2_.mem_bottom_track_1.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__2_.mem_bottom_track_5.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__2_.mem_bottom_track_9.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_0__2_.mem_bottom_track_25.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_1__0_.mem_top_track_0.mem_out[0:3], 4'b0010); - $deposit(U0_formal_verification.sb_1__0_.mem_top_track_2.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_1__0_.mem_top_track_4.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_1__0_.mem_top_track_6.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_1__0_.mem_top_track_8.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_1__0_.mem_top_track_10.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_1__0_.mem_top_track_12.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_1__0_.mem_top_track_14.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_1__0_.mem_top_track_16.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_1__0_.mem_top_track_18.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_1__0_.mem_top_track_20.mem_out[0:1], {2{1'b1}}); - $deposit(U0_formal_verification.sb_1__0_.mem_top_track_22.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_1__0_.mem_top_track_24.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_1__0_.mem_top_track_38.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_1__0_.mem_right_track_0.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_1__0_.mem_right_track_2.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.sb_1__0_.mem_right_track_4.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.sb_1__0_.mem_right_track_8.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_1__0_.mem_right_track_16.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_1__0_.mem_right_track_24.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_1__0_.mem_right_track_32.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_1__0_.mem_left_track_1.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.sb_1__0_.mem_left_track_3.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_1__0_.mem_left_track_5.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.sb_1__0_.mem_left_track_9.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_1__0_.mem_left_track_17.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_1__0_.mem_left_track_25.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_1__0_.mem_left_track_33.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_1__1_.mem_top_track_0.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.sb_1__1_.mem_top_track_2.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.sb_1__1_.mem_top_track_4.mem_out[0:4], {5{1'b0}}); - $deposit(U0_formal_verification.sb_1__1_.mem_top_track_8.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.sb_1__1_.mem_top_track_16.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.sb_1__1_.mem_top_track_24.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.sb_1__1_.mem_top_track_32.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_1__1_.mem_right_track_0.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.sb_1__1_.mem_right_track_2.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.sb_1__1_.mem_right_track_4.mem_out[0:4], {5{1'b0}}); - $deposit(U0_formal_verification.sb_1__1_.mem_right_track_8.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.sb_1__1_.mem_right_track_16.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.sb_1__1_.mem_right_track_24.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.sb_1__1_.mem_right_track_32.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_1__1_.mem_bottom_track_1.mem_out[0:3], 4'b0110); - $deposit(U0_formal_verification.sb_1__1_.mem_bottom_track_3.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.sb_1__1_.mem_bottom_track_5.mem_out[0:4], {5{1'b0}}); - $deposit(U0_formal_verification.sb_1__1_.mem_bottom_track_9.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.sb_1__1_.mem_bottom_track_17.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.sb_1__1_.mem_bottom_track_25.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.sb_1__1_.mem_bottom_track_33.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_1__1_.mem_left_track_1.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.sb_1__1_.mem_left_track_3.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.sb_1__1_.mem_left_track_5.mem_out[0:4], {5{1'b0}}); - $deposit(U0_formal_verification.sb_1__1_.mem_left_track_9.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.sb_1__1_.mem_left_track_17.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.sb_1__1_.mem_left_track_25.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.sb_1__1_.mem_left_track_33.mem_out[0:2], 3'b001); - $deposit(U0_formal_verification.sb_1__2_.mem_right_track_0.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.sb_1__2_.mem_right_track_2.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.sb_1__2_.mem_right_track_4.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.sb_1__2_.mem_right_track_8.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.sb_1__2_.mem_right_track_16.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_1__2_.mem_right_track_24.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_1__2_.mem_right_track_32.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_1.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_3.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_5.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_7.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_9.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_11.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_13.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_15.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_17.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_19.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_21.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_23.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_25.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_1__2_.mem_bottom_track_27.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_1__2_.mem_left_track_1.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.sb_1__2_.mem_left_track_3.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.sb_1__2_.mem_left_track_5.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.sb_1__2_.mem_left_track_9.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.sb_1__2_.mem_left_track_17.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_1__2_.mem_left_track_25.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_1__2_.mem_left_track_33.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_2__0_.mem_top_track_0.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_2__0_.mem_top_track_2.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_2__0_.mem_top_track_4.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_2__0_.mem_top_track_6.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_2__0_.mem_top_track_8.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__0_.mem_top_track_10.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__0_.mem_top_track_12.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__0_.mem_top_track_14.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__0_.mem_top_track_16.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__0_.mem_top_track_18.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__0_.mem_top_track_20.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__0_.mem_top_track_22.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__0_.mem_top_track_24.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__0_.mem_top_track_26.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__0_.mem_left_track_1.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_2__0_.mem_left_track_3.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_2__0_.mem_left_track_5.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_2__0_.mem_left_track_7.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_2__0_.mem_left_track_9.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__0_.mem_left_track_11.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__0_.mem_left_track_13.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__0_.mem_left_track_15.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__0_.mem_left_track_17.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__0_.mem_left_track_19.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__0_.mem_left_track_25.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__0_.mem_left_track_27.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__0_.mem_left_track_29.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__0_.mem_left_track_31.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__0_.mem_left_track_33.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__0_.mem_left_track_35.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__1_.mem_top_track_0.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.sb_2__1_.mem_top_track_2.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.sb_2__1_.mem_top_track_4.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.sb_2__1_.mem_top_track_8.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.sb_2__1_.mem_top_track_16.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_2__1_.mem_top_track_24.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_2__1_.mem_top_track_32.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_2__1_.mem_bottom_track_1.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.sb_2__1_.mem_bottom_track_3.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.sb_2__1_.mem_bottom_track_5.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.sb_2__1_.mem_bottom_track_9.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.sb_2__1_.mem_bottom_track_17.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_2__1_.mem_bottom_track_25.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_2__1_.mem_bottom_track_33.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_2__1_.mem_left_track_1.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_2__1_.mem_left_track_3.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_2__1_.mem_left_track_5.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_2__1_.mem_left_track_7.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_2__1_.mem_left_track_9.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_2__1_.mem_left_track_11.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_2__1_.mem_left_track_13.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_2__1_.mem_left_track_15.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_2__1_.mem_left_track_17.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__1_.mem_left_track_19.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__1_.mem_left_track_21.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__1_.mem_left_track_23.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__1_.mem_left_track_25.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__1_.mem_left_track_29.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__1_.mem_left_track_31.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__1_.mem_left_track_33.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__1_.mem_left_track_35.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__1_.mem_left_track_37.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__1_.mem_left_track_39.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_1.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_3.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_5.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_7.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_9.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_11.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_13.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_15.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_17.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_19.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_21.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_23.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_25.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_27.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__2_.mem_bottom_track_29.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__2_.mem_left_track_1.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_2__2_.mem_left_track_3.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_2__2_.mem_left_track_5.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_2__2_.mem_left_track_7.mem_out[0:2], {3{1'b0}}); - $deposit(U0_formal_verification.sb_2__2_.mem_left_track_9.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__2_.mem_left_track_11.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__2_.mem_left_track_13.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__2_.mem_left_track_15.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__2_.mem_left_track_17.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__2_.mem_left_track_19.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__2_.mem_left_track_21.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__2_.mem_left_track_23.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__2_.mem_left_track_25.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__2_.mem_left_track_27.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__2_.mem_left_track_29.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__2_.mem_left_track_31.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__2_.mem_left_track_33.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__2_.mem_left_track_35.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__2_.mem_left_track_37.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.sb_2__2_.mem_left_track_39.mem_out[0:1], {2{1'b0}}); - $deposit(U0_formal_verification.cbx_1__0_.mem_top_ipin_0.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__0_.mem_top_ipin_1.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__0_.mem_top_ipin_2.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__0_.mem_top_ipin_3.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__0_.mem_top_ipin_4.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__0_.mem_top_ipin_5.mem_out[0:3], 4'b1101); - $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_0.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_1.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_2.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_3.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_4.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_5.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_6.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_7.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_8.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_9.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_10.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_11.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_12.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_13.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_14.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__1_.mem_top_ipin_15.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__2_.mem_bottom_ipin_0.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_0.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_1.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_2.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_3.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_4.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_5.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_6.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_7.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_8.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_9.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_10.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_11.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_12.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_13.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_14.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_1__2_.mem_top_ipin_15.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__0_.mem_top_ipin_0.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__0_.mem_top_ipin_1.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__0_.mem_top_ipin_2.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__0_.mem_top_ipin_3.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__0_.mem_top_ipin_4.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__0_.mem_top_ipin_5.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_0.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_1.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_2.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_3.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_4.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_5.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_6.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_7.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_8.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_9.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_10.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_11.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_12.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_13.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_14.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__1_.mem_top_ipin_15.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__2_.mem_bottom_ipin_0.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_0.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_1.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_2.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_3.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_4.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_5.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_6.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_7.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_8.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_9.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_10.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_11.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_12.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_13.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_14.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cbx_2__2_.mem_top_ipin_15.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_0__1_.mem_right_ipin_0.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_0__2_.mem_right_ipin_0.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_0.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_1.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_2.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_3.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_4.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_5.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_6.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_7.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_8.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_9.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_10.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_11.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_12.mem_out[0:3], {4{1'b1}}); - $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_13.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_14.mem_out[0:3], 4'b0111); - $deposit(U0_formal_verification.cby_1__1_.mem_right_ipin_15.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_1__2_.mem_right_ipin_0.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_1__2_.mem_right_ipin_1.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_1__2_.mem_right_ipin_2.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_1__2_.mem_right_ipin_3.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_1__2_.mem_right_ipin_4.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_1__2_.mem_right_ipin_5.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_1__2_.mem_right_ipin_6.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_1__2_.mem_right_ipin_7.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_1__2_.mem_right_ipin_8.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_1__2_.mem_right_ipin_9.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_1__2_.mem_right_ipin_10.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_1__2_.mem_right_ipin_11.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_1__2_.mem_right_ipin_12.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_1__2_.mem_right_ipin_13.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_1__2_.mem_right_ipin_14.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_1__2_.mem_right_ipin_15.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_2__1_.mem_left_ipin_0.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_2__1_.mem_right_ipin_0.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_2__1_.mem_right_ipin_1.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_2__1_.mem_right_ipin_2.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_2__1_.mem_right_ipin_3.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_2__1_.mem_right_ipin_4.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_2__1_.mem_right_ipin_5.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_2__1_.mem_right_ipin_6.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_2__1_.mem_right_ipin_7.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_2__1_.mem_right_ipin_8.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_2__1_.mem_right_ipin_9.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_2__1_.mem_right_ipin_10.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_2__1_.mem_right_ipin_11.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_2__1_.mem_right_ipin_12.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_2__1_.mem_right_ipin_13.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_2__1_.mem_right_ipin_14.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_2__1_.mem_right_ipin_15.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_2__2_.mem_left_ipin_0.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_2__2_.mem_right_ipin_0.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_2__2_.mem_right_ipin_1.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_2__2_.mem_right_ipin_2.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_2__2_.mem_right_ipin_3.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_2__2_.mem_right_ipin_4.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_2__2_.mem_right_ipin_5.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_2__2_.mem_right_ipin_6.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_2__2_.mem_right_ipin_7.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_2__2_.mem_right_ipin_8.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_2__2_.mem_right_ipin_9.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_2__2_.mem_right_ipin_10.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_2__2_.mem_right_ipin_11.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_2__2_.mem_right_ipin_12.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_2__2_.mem_right_ipin_13.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_2__2_.mem_right_ipin_14.mem_out[0:3], {4{1'b0}}); - $deposit(U0_formal_verification.cby_2__2_.mem_right_ipin_15.mem_out[0:3], {4{1'b0}}); -end -// -`endif -// -endmodule -// - diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/TESTBENCH/top/fabric_bitstream.bit b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/TESTBENCH/top/fabric_bitstream.bit deleted file mode 100644 index cd6e31f..0000000 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/TESTBENCH/top/fabric_bitstream.bit +++ /dev/null @@ -1 +0,0 @@ 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diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/TESTBENCH/top/fabric_bitstream.xml b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/TESTBENCH/top/fabric_bitstream.xml deleted file mode 100644 index 6b3467f..0000000 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/TESTBENCH/top/fabric_bitstream.xml +++ /dev/null @@ -1,4221 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 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- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 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- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 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- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/openfpgashell.log b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/openfpgashell.log deleted file mode 100644 index c8e7269..0000000 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/openfpgashell.log +++ /dev/null @@ -1,892 +0,0 @@ -/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga/openfpga -f top_run.openfpga -Reading script file top_run.openfpga... - - ___ _____ ____ ____ _ - / _ \ _ __ ___ _ __ | ___| _ \ / ___| / \ - | | | | '_ \ / _ \ '_ \| |_ | |_) | | _ / _ \ - | |_| | |_) | __/ | | | _| | __/| |_| |/ ___ \ - \___/| .__/ \___|_| |_|_| |_| \____/_/ \_\ - |_| - - OpenFPGA: An Open-source FPGA IP Generator - Versatile Place and Route (VPR) - FPGA-Verilog - FPGA-SPICE - FPGA-SDC - FPGA-Bitstream - - This is a free software under the MIT License - - Copyright (c) 2018 LNIS - The University of Utah - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. - - - -Command line to execute: vpr /research/ece/lnis/USERS/DARPA_ERI/GF14nm_chip_2019/ICC2_Methodology_Flow/GANESH/FROG_PnR/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/run001/vpr_arch/top/MIN_ROUTE_CHAN_WIDTH/arch/vpr_arch.xml top.blif --clock_modeling route --device 2x2 --route_chan_width 40 --absorb_buffer_luts off -VPR FPGA Placement and Routing. -Version: 0.0.0+520e54d7 -Revision: 520e54d7 -Compiled: 2020-11-09T18:01:05 -Compiler: GNU 8.4.0 on Linux-3.10.0-1062.9.1.el7.x86_64 x86_64 -Build Info: release VTR_ASSERT_LEVEL=2 - -University of Toronto -verilogtorouting.org -vtr-users@googlegroups.com -This is free open source code under MIT license. - -VPR was run with the following command-line: -vpr /research/ece/lnis/USERS/DARPA_ERI/GF14nm_chip_2019/ICC2_Methodology_Flow/GANESH/FROG_PnR/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/run001/vpr_arch/top/MIN_ROUTE_CHAN_WIDTH/arch/vpr_arch.xml top.blif --clock_modeling route --device 2x2 --route_chan_width 40 --absorb_buffer_luts off - - -Architecture file: /research/ece/lnis/USERS/DARPA_ERI/GF14nm_chip_2019/ICC2_Methodology_Flow/GANESH/FROG_PnR/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/run001/vpr_arch/top/MIN_ROUTE_CHAN_WIDTH/arch/vpr_arch.xml -Circuit name: top - -# Loading Architecture Description -Warning 1: Model 'io' input port 'outpad' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) -Warning 2: Model 'io' output port 'inpad' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output) -Warning 3: Model 'frac_lut4' input port 'in' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input) -Warning 4: Model 'frac_lut4' output port 'lut4_out' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output) -Warning 5: Model 'frac_lut4' output port 'lut3_out' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output) -# Loading Architecture Description took 0.01 seconds (max_rss 9.0 MiB, delta_rss +0.6 MiB) -# Building complex block graph -Warning 6: [LINE 586] false logically-equivalent pin clb[0].I0[1]. -Warning 7: [LINE 586] false logically-equivalent pin clb[0].I0[2]. -Warning 8: [LINE 592] false logically-equivalent pin clb[0].I1[1]. -Warning 9: [LINE 592] false logically-equivalent pin clb[0].I1[2]. -Warning 10: [LINE 598] false logically-equivalent pin clb[0].I2[1]. -Warning 11: [LINE 598] false logically-equivalent pin clb[0].I2[2]. -Warning 12: [LINE 604] false logically-equivalent pin clb[0].I3[1]. -Warning 13: [LINE 604] false logically-equivalent pin clb[0].I3[2]. -Warning 14: [LINE 610] false logically-equivalent pin clb[0].I4[1]. -Warning 15: [LINE 610] false logically-equivalent pin clb[0].I4[2]. -Warning 16: [LINE 616] false logically-equivalent pin clb[0].I5[1]. -Warning 17: [LINE 616] false logically-equivalent pin clb[0].I5[2]. -Warning 18: [LINE 622] false logically-equivalent pin clb[0].I6[1]. -Warning 19: [LINE 622] false logically-equivalent pin clb[0].I6[2]. -Warning 20: [LINE 628] false logically-equivalent pin clb[0].I7[1]. -Warning 21: [LINE 628] false logically-equivalent pin clb[0].I7[2]. -# Building complex block graph took 0.01 seconds (max_rss 9.5 MiB, delta_rss +0.5 MiB) -# Load circuit -# Load circuit took 0.00 seconds (max_rss 9.9 MiB, delta_rss +0.4 MiB) -# Clean circuit -Inferred 0 additional primitive pins as constant generators since they have no combinationally connected inputs -Inferred 0 additional primitive pins as constant generators due to constant inputs -Swept input(s) : 0 -Swept output(s) : 0 (0 dangling, 0 constant) -Swept net(s) : 0 -Swept block(s) : 0 -Constant Pins Marked: 0 -# Clean circuit took 0.00 seconds (max_rss 9.9 MiB, delta_rss +0.0 MiB) -# Compress circuit -# Compress circuit took 0.00 seconds (max_rss 9.9 MiB, delta_rss +0.0 MiB) -# Verify circuit -# Verify circuit took 0.00 seconds (max_rss 9.9 MiB, delta_rss +0.0 MiB) -Circuit Statistics: - Blocks: 4 - .input : 2 - .output: 1 - 4-LUT : 1 - Nets : 3 - Avg Fanout: 1.0 - Max Fanout: 1.0 - Min Fanout: 1.0 - Netlist Clocks: 0 -# Build Timing Graph - Timing Graph Nodes: 6 - Timing Graph Edges: 5 - Timing Graph Levels: 4 -# Build Timing Graph took 0.00 seconds (max_rss 9.9 MiB, delta_rss +0.0 MiB) -Netlist contains 0 clocks -# Load Timing Constraints - -SDC file 'top.sdc' not found -Setting default timing constraints: - * constrain all primay inputs and primary outputs on a virtual external clock 'virtual_io_clock' - * optimize virtual clock to run as fast as possible -Timing constraints created 1 clocks - Constrained Clock 'virtual_io_clock' (Virtual Clock) - -# Load Timing Constraints took 0.00 seconds (max_rss 9.9 MiB, delta_rss +0.0 MiB) -Timing analysis: ON -Circuit netlist file: top.net -Circuit placement file: top.place -Circuit routing file: top.route -Circuit SDC file: top.sdc - -Packer: ENABLED -Placer: ENABLED -Router: ENABLED -Analysis: ENABLED - -NetlistOpts.abosrb_buffer_luts : false -NetlistOpts.sweep_dangling_primary_ios : true -NetlistOpts.sweep_dangling_nets : true -NetlistOpts.sweep_dangling_blocks : true -NetlistOpts.sweep_constant_primary_outputs: false - -PackerOpts.allow_unrelated_clustering: auto -PackerOpts.alpha_clustering: 0.750000 -PackerOpts.beta_clustering: 0.900000 -PackerOpts.cluster_seed_type: BLEND2 -PackerOpts.connection_driven: true -PackerOpts.global_clocks: true -PackerOpts.hill_climbing_flag: false -PackerOpts.inter_cluster_net_delay: 1.000000 -PackerOpts.timing_driven: true -PackerOpts.target_external_pin_util: auto -PlacerOpts.place_freq: PLACE_ONCE -PlacerOpts.place_algorithm: PATH_TIMING_DRIVEN_PLACE -PlacerOpts.pad_loc_type: FREE -PlacerOpts.place_cost_exp: 1.000000 -PlacerOpts.place_chan_width: 40 -PlacerOpts.inner_loop_recompute_divider: 0 -PlacerOpts.recompute_crit_iter: 1 -PlacerOpts.timing_tradeoff: 0.500000 -PlacerOpts.td_place_exp_first: 1.000000 -PlacerOpts.td_place_exp_last: 8.000000 -PlaceOpts.seed: 1 -AnnealSched.type: AUTO_SCHED -AnnealSched.inner_num: 1.000000 - -RouterOpts.route_type: DETAILED -RouterOpts.router_algorithm: TIMING_DRIVEN -RouterOpts.base_cost_type: DELAY_NORMALIZED_LENGTH -RouterOpts.fixed_channel_width: 40 -RouterOpts.trim_empty_chan: false -RouterOpts.trim_obs_chan: false -RouterOpts.acc_fac: 1.000000 -RouterOpts.bb_factor: 3 -RouterOpts.bend_cost: 0.000000 -RouterOpts.first_iter_pres_fac: 0.000000 -RouterOpts.initial_pres_fac: 0.500000 -RouterOpts.pres_fac_mult: 1.300000 -RouterOpts.max_router_iterations: 50 -RouterOpts.min_incremental_reroute_fanout: 16 -RouterOpts.astar_fac: 1.200000 -RouterOpts.criticality_exp: 1.000000 -RouterOpts.max_criticality: 0.990000 -RouterOpts.routing_failure_predictor = SAFE -RouterOpts.routing_budgets_algorithm = DISABLE - -AnalysisOpts.gen_post_synthesis_netlist: false - -RoutingArch.directionality: UNI_DIRECTIONAL -RoutingArch.switch_block_type: WILTON -RoutingArch.Fs: 3 - -# Packing -Warning 22: Ambiguous block type specification at grid location (0,0). Existing block type 'io_bottom' at (0,0) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply. -Warning 23: Ambiguous block type specification at grid location (0,3). Existing block type 'io_top' at (0,3) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply. -Warning 24: Ambiguous block type specification at grid location (3,0). Existing block type 'io_bottom' at (3,0) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply. -Warning 25: Ambiguous block type specification at grid location (3,3). Existing block type 'io_top' at (3,3) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply. -Begin packing 'top.blif'. - -After removing unused inputs... - total blocks: 4, total nets: 3, total inputs: 2, total outputs: 1 -Begin prepacking. -Finish prepacking. -Using inter-cluster delay: 1.33777e-09 -Packing with pin utilization targets: io_top:1,1 io_right:1,1 io_bottom:1,1 io_left:1,1 clb:0.8,1 -Packing with high fanout thresholds: io_top:128 io_right:128 io_bottom:128 io_left:128 clb:32 -Warning 26: Ambiguous block type specification at grid location (0,0). Existing block type 'io_bottom' at (0,0) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply. -Warning 27: Ambiguous block type specification at grid location (0,3). Existing block type 'io_top' at (0,3) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply. -Warning 28: Ambiguous block type specification at grid location (3,0). Existing block type 'io_bottom' at (3,0) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply. -Warning 29: Ambiguous block type specification at grid location (3,3). Existing block type 'io_top' at (3,3) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply. -Not enough resources expand FPGA size to (4 x 4) -Complex block 0: 'c' (clb) . -Complex block 1: 'out:c' (io) . -Complex block 2: 'a' (io) . -Complex block 3: 'b' (io) . - -Pb types usage... - inpad : 2 - outpad : 1 - fle : 1 - clb : 1 - lut3inter : 1 - ble3 : 1 - io : 3 - lut3 : 1 - lut : 1 - - -Logic Element (fle) detailed count: - Total number of Logic Elements used : 1 - LEs used for logic and registers : 0 - LEs used for logic only : 1 - LEs used for registers only : 0 - - EMPTY: # blocks: 0, average # input + clock pins used: 0, average # output pins used: 0 - io: # blocks: 3, average # input + clock pins used: 0.333333, average # output pins used: 0.666667 - clb: # blocks: 1, average # input + clock pins used: 2, average # output pins used: 1 -Absorbed logical nets 0 out of 3 nets, 3 nets not absorbed. -Warning 30: Ambiguous block type specification at grid location (0,0). Existing block type 'io_bottom' at (0,0) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply. -Warning 31: Ambiguous block type specification at grid location (0,3). Existing block type 'io_top' at (0,3) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply. -Warning 32: Ambiguous block type specification at grid location (3,0). Existing block type 'io_bottom' at (3,0) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply. -Warning 33: Ambiguous block type specification at grid location (3,3). Existing block type 'io_top' at (3,3) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply. -FPGA sized to 4 x 4 (2x2) -Device Utilization: 0.25 (target 1.00) - Block Utilization: 0.17 Type: io - Block Utilization: 0.25 Type: clb - - -Netlist conversion complete. - -# Packing took 0.01 seconds (max_rss 10.6 MiB, delta_rss +0.7 MiB) -# Load Packing -Begin loading packed FPGA netlist file. -Netlist generated from file 'top.net'. -Detected 0 constant generators (to see names run with higher pack verbosity) -Finished loading packed FPGA netlist file (took 0.01 seconds). -Warning 34: Treated 0 constant nets as global which will not be routed (to see net names increase packer verbosity). -# Load Packing took 0.01 seconds (max_rss 10.6 MiB, delta_rss +0.1 MiB) -Warning 35: Netlist contains 0 global net to non-global architecture pin connections - -Netlist num_nets: 3 -Netlist num_blocks: 4 -Netlist EMPTY blocks: 0. -Netlist io blocks: 3. -Netlist clb blocks: 1. -Netlist inputs pins: 2 -Netlist output pins: 1 - -# Create Device -## Build Device Grid -Warning 36: Ambiguous block type specification at grid location (0,0). Existing block type 'io_bottom' at (0,0) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply. -Warning 37: Ambiguous block type specification at grid location (0,3). Existing block type 'io_top' at (0,3) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply. -Warning 38: Ambiguous block type specification at grid location (3,0). Existing block type 'io_bottom' at (3,0) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply. -Warning 39: Ambiguous block type specification at grid location (3,3). Existing block type 'io_top' at (3,3) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply. -FPGA sized to 4 x 4: 16 grid tiles (2x2) - -Resource usage... - Netlist - 3 blocks of type: io - Architecture - 2 blocks of type: io_top - 2 blocks of type: io_right - 12 blocks of type: io_bottom - 2 blocks of type: io_left - Netlist - 1 blocks of type: clb - Architecture - 4 blocks of type: clb - -Device Utilization: 0.25 (target 1.00) - Physical Tile io_top: - Block Utilization: 1.50 Logical Block: io - Physical Tile io_right: - Block Utilization: 1.50 Logical Block: io - Physical Tile io_bottom: - Block Utilization: 0.25 Logical Block: io - Physical Tile io_left: - Block Utilization: 1.50 Logical Block: io - Physical Tile clb: - Block Utilization: 0.25 Logical Block: clb - -## Build Device Grid took 0.00 seconds (max_rss 10.7 MiB, delta_rss +0.0 MiB) -## Build tileable routing resource graph -X-direction routing channel width is 40 -Y-direction routing channel width is 40 -Warning 40: in check_rr_node: RR node: 105 type: OPIN location: (1,1) pin: 50 pin_name: clb.regout[0] capacity: 1 has no out-going edges. -Warning 41: in check_rr_node: RR node: 106 type: OPIN location: (1,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. -Warning 42: in check_rr_node: RR node: 195 type: OPIN location: (2,1) pin: 50 pin_name: clb.regout[0] capacity: 1 has no out-going edges. -Warning 43: in check_rr_node: RR node: 196 type: OPIN location: (2,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. -## Build tileable routing resource graph took 0.01 seconds (max_rss 11.2 MiB, delta_rss +0.5 MiB) - RR Graph Nodes: 756 - RR Graph Edges: 2930 -# Create Device took 0.01 seconds (max_rss 11.2 MiB, delta_rss +0.5 MiB) - -# Placement -## Computing placement delta delay look-up -### Build routing resource graph -Warning 44: in check_rr_node: RR node: 119 type: OPIN location: (1,1) pin: 50 pin_name: clb.regout[0] capacity: 1 has no out-going edges. -Warning 45: in check_rr_node: RR node: 120 type: OPIN location: (1,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. -Warning 46: in check_rr_node: RR node: 327 type: OPIN location: (2,1) pin: 50 pin_name: clb.regout[0] capacity: 1 has no out-going edges. -Warning 47: in check_rr_node: RR node: 328 type: OPIN location: (2,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. -### Build routing resource graph took 0.00 seconds (max_rss 11.2 MiB, delta_rss +0.0 MiB) - RR Graph Nodes: 756 - RR Graph Edges: 2428 -### Computing delta delays -### Computing delta delays took 0.00 seconds (max_rss 11.5 MiB, delta_rss +0.0 MiB) -## Computing placement delta delay look-up took 0.00 seconds (max_rss 11.5 MiB, delta_rss +0.3 MiB) - -There are 3 point to point connections in this circuit. - - -BB estimate of min-dist (placement) wire length: 10 - -Completed placement consistency check successfully. -Initial placement cost: 1 bb_cost: 0.25 td_cost: 6.04709e-10 -Initial placement estimated Critical Path Delay (CPD): 0.80931 ns -Initial placement estimated setup Total Negative Slack (sTNS): -0.80931 ns -Initial placement estimated setup Worst Negative Slack (sWNS): -0.80931 ns - -Initial placement estimated setup slack histogram: -[ -8.1e-10: -8.1e-10) 1 (100.0%) |************************************************** -[ -8.1e-10: -8.1e-10) 0 ( 0.0%) | -[ -8.1e-10: -8.1e-10) 0 ( 0.0%) | -[ -8.1e-10: -8.1e-10) 0 ( 0.0%) | -[ -8.1e-10: -8.1e-10) 0 ( 0.0%) | -[ -8.1e-10: -8.1e-10) 0 ( 0.0%) | -[ -8.1e-10: -8.1e-10) 0 ( 0.0%) | -[ -8.1e-10: -8.1e-10) 0 ( 0.0%) | -[ -8.1e-10: -8.1e-10) 0 ( 0.0%) | -[ -8.1e-10: -8.1e-10) 0 ( 0.0%) | -Placement contains 0 placement macros involving 0 blocks (average macro size -nan) - -------- ------- ---------- ---------- ------- ---------- -------- ------- ------- ------ -------- --------- ------ - T Av Cost Av BB Cost Av TD Cost CPD sTNS sWNS Ac Rate Std Dev R lim Crit Exp Tot Moves Alpha -------- ------- ---------- ---------- ------- ---------- -------- ------- ------- ------ -------- --------- ------ -9.2e-01 0.857 0.21 4.9164e-10 0.693 -0.693 -0.693 0.667 0.0425 3.0 1.00 6 0.950 -8.8e-01 1.031 0.22 5.2788e-10 0.693 -0.693 -0.693 1.000 0.1248 3.0 1.00 12 0.500 -4.4e-01 0.977 0.20 4.5978e-10 0.693 -0.693 -0.693 1.000 0.0478 3.0 1.00 18 0.500 -2.2e-01 1.296 0.24 6.1181e-10 0.577 -0.577 -0.577 0.833 0.1114 3.0 1.00 24 0.900 -2.0e-01 0.807 0.21 5.1793e-10 0.809 -0.809 -0.809 0.833 0.1585 3.0 1.00 30 0.900 -1.8e-01 1.284 0.23 4.5908e-10 0.577 -0.577 -0.577 1.000 0.1344 3.0 1.00 36 0.500 -8.9e-02 0.981 0.23 4.8318e-10 0.635 -0.635 -0.635 1.000 0.0703 3.0 1.00 42 0.500 -4.4e-02 0.906 0.23 4.617e-10 0.693 -0.693 -0.693 0.833 0.0159 3.0 1.00 48 0.900 -4.0e-02 0.915 0.20 4.3008e-10 0.693 -0.693 -0.693 1.000 0.0692 3.0 1.00 54 0.500 -2.0e-02 1.000 0.18 3.9141e-10 0.577 -0.577 -0.577 0.333 0.0000 3.0 1.00 60 0.950 -1.9e-02 1.000 0.18 3.9141e-10 0.577 -0.577 -0.577 0.167 0.0000 2.7 2.12 66 0.950 -1.8e-02 0.982 0.17 3.9141e-10 0.577 -0.577 -0.577 0.667 0.0357 1.9 4.68 72 0.950 -1.7e-02 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.167 0.0000 2.4 3.14 78 0.950 -1.6e-02 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.167 0.0000 1.7 5.42 84 0.950 -1.5e-02 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.500 0.0000 1.3 7.08 90 0.950 -1.5e-02 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.500 0.0000 1.3 6.82 96 0.950 -1.4e-02 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.333 0.0000 1.4 6.54 102 0.950 -1.3e-02 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.333 0.0000 1.3 7.07 108 0.950 -1.3e-02 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.500 0.0000 1.1 7.54 114 0.950 -1.2e-02 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.000 0.0000 1.2 7.30 120 0.950 -1.1e-02 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.000 0.0000 1.0 8.00 126 0.800 -9.1e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.500 0.0000 1.0 8.00 132 0.950 -8.6e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.500 0.0000 1.1 7.79 138 0.950 -8.2e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.333 0.0000 1.1 7.57 144 0.950 -7.8e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.167 0.0000 1.0 7.99 150 0.950 -7.4e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.500 0.0000 1.0 8.00 156 0.950 -7.0e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.667 0.0000 1.1 7.79 162 0.950 -6.7e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.833 0.0000 1.3 6.95 168 0.900 -6.0e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.000 0.0000 1.8 5.16 174 0.950 -5.7e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.167 0.0000 1.0 7.95 180 0.950 -5.4e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.333 0.0000 1.0 8.00 186 0.950 -5.1e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.500 0.0000 1.0 8.00 192 0.950 -4.9e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.167 0.0000 1.1 7.79 198 0.950 -4.6e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.167 0.0000 1.0 8.00 204 0.950 -4.4e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.500 0.0000 1.0 8.00 210 0.950 -4.2e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.500 0.0000 1.1 7.79 216 0.950 -4.0e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.333 0.0000 1.1 7.57 222 0.950 -3.8e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.333 0.0000 1.0 7.99 228 0.950 -3.6e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.167 0.0000 1.0 8.00 234 0.950 -3.4e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.167 0.0000 1.0 8.00 240 0.950 -3.2e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.500 0.0000 1.0 8.00 246 0.950 -3.1e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.333 0.0000 1.1 7.79 252 0.950 -2.9e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.000 0.0000 1.0 8.00 258 0.800 -2.3e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.167 0.0000 1.0 8.00 264 0.950 -2.2e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.167 0.0000 1.0 8.00 270 0.950 -2.1e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.000 0.0000 1.0 8.00 276 0.800 -1.7e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.167 0.0000 1.0 8.00 282 0.950 -1.7e-03 1.000 0.15 3.9141e-10 0.577 -0.577 -0.577 0.167 0.0000 1.0 8.00 288 0.000 - -BB estimate of min-dist (placement) wire length: 6 - -Completed placement consistency check successfully. - -Swaps called: 292 - -Placement estimated critical path delay: 0.57731 ns -Placement estimated setup Total Negative Slack (sTNS): -0.57731 ns -Placement estimated setup Worst Negative Slack (sWNS): -0.57731 ns - -Placement estimated setup slack histogram: -[ -5.8e-10: -5.8e-10) 1 (100.0%) |************************************************** -[ -5.8e-10: -5.8e-10) 0 ( 0.0%) | -[ -5.8e-10: -5.8e-10) 0 ( 0.0%) | -[ -5.8e-10: -5.8e-10) 0 ( 0.0%) | -[ -5.8e-10: -5.8e-10) 0 ( 0.0%) | -[ -5.8e-10: -5.8e-10) 0 ( 0.0%) | -[ -5.8e-10: -5.8e-10) 0 ( 0.0%) | -[ -5.8e-10: -5.8e-10) 0 ( 0.0%) | -[ -5.8e-10: -5.8e-10) 0 ( 0.0%) | -[ -5.8e-10: -5.8e-10) 0 ( 0.0%) | - -Placement cost: 1, bb_cost: 0.15, td_cost: 3.9141e-10, - -Placement resource usage: - io implemented as io_bottom: 2 - io implemented as io_left : 1 - clb implemented as clb : 1 - -Placement number of temperatures: 48 -Placement total # of swap attempts: 292 - Swaps accepted: 125 (42.8 %) - Swaps rejected: 167 (57.2 %) - Swaps aborted : 0 ( 0.0 %) - -Aborted Move Reasons: -# Placement took 0.01 seconds (max_rss 11.7 MiB, delta_rss +0.5 MiB) - -# Routing -## Build tileable routing resource graph -X-direction routing channel width is 40 -Y-direction routing channel width is 40 -Warning 48: in check_rr_node: RR node: 105 type: OPIN location: (1,1) pin: 50 pin_name: clb.regout[0] capacity: 1 has no out-going edges. -Warning 49: in check_rr_node: RR node: 106 type: OPIN location: (1,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. -Warning 50: in check_rr_node: RR node: 195 type: OPIN location: (2,1) pin: 50 pin_name: clb.regout[0] capacity: 1 has no out-going edges. -Warning 51: in check_rr_node: RR node: 196 type: OPIN location: (2,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. -## Build tileable routing resource graph took 0.01 seconds (max_rss 11.7 MiB, delta_rss +0.0 MiB) - RR Graph Nodes: 756 - RR Graph Edges: 2930 -Confirming router algorithm: TIMING_DRIVEN. ----- ------ ------- ---- ------- ------- ------- ----------------- --------------- -------- ---------- ---------- ---------- ---------- -------- -Iter Time pres BBs Heap Re-Rtd Re-Rtd Overused RR Nodes Wirelength CPD sTNS sWNS hTNS hWNS Est Succ - (sec) fac Updt push Nets Conns (ns) (ns) (ns) (ns) (ns) Iter ----- ------ ------- ---- ------- ------- ------- ----------------- --------------- -------- ---------- ---------- ---------- ---------- -------- - 1 0.0 0.0 0 203 3 3 1 ( 0.132%) 12 ( 2.5%) 0.867 -0.8673 -0.867 0.000 0.000 N/A - 2 0.0 0.5 0 86 1 1 0 ( 0.000%) 12 ( 2.5%) 0.867 -0.8673 -0.867 0.000 0.000 N/A -Restoring best routing -Critical path: 0.86731 ns -Successfully routed after 2 routing iterations. -Router Stats: total_nets_routed: 4 total_connections_routed: 4 total_heap_pushes: 289 total_heap_pops: 187 -# Routing took 0.01 seconds (max_rss 11.9 MiB, delta_rss +0.2 MiB) - -Checking to ensure routing is legal... -Completed routing consistency check successfully. - -Serial number (magic cookie) for the routing is: -18854 -Circuit successfully routed with a channel width factor of 40. - -Average number of bends per net: 2.00000 Maximum # of bends: 3 - -Number of global nets: 0 -Number of routed nets (nonglobal): 3 -Wire length results (in units of 1 clb segments)... - Total wirelength: 12, average net length: 4.00000 - Maximum net length: 6 - -Wire length results in terms of physical segments... - Total wiring segments used: 9, average wire segments per net: 3.00000 - Maximum segments used by a net: 4 - Total local nets with reserved CLB opins: 0 - -Routing channel utilization histogram: -[ 1: inf) 0 ( 0.0%) | -[ 0.9: 1) 0 ( 0.0%) | -[ 0.8: 0.9) 0 ( 0.0%) | -[ 0.7: 0.8) 0 ( 0.0%) | -[ 0.5: 0.6) 0 ( 0.0%) | -[ 0.4: 0.5) 0 ( 0.0%) | -[ 0.3: 0.4) 0 ( 0.0%) | -[ 0.2: 0.3) 0 ( 0.0%) | -[ 0.1: 0.2) 0 ( 0.0%) | -[ 0: 0.1) 18 (100.0%) |************************************************ -Maximum routing channel utilization: 0.05 at (1,0) - -X - Directed channels: j max occ ave occ capacity - ---- ------- ------- -------- - 0 2 0.750 40 - 1 2 0.500 40 - 2 0 0.000 40 -Y - Directed channels: i max occ ave occ capacity - ---- ------- ------- -------- - 0 2 0.750 40 - 1 3 1.000 40 - 2 0 0.000 40 - -Total tracks in x-direction: 120, in y-direction: 120 - -Logic area (in minimum width transistor areas, excludes I/Os and empty grid tiles)... - Total logic block area (Warning, need to add pitch of routing to blocks with height > 3): 215576 - Total used logic block area: 53894 - -Routing area (in minimum width transistor areas)... - Total routing area: 23072.6, per logic tile: 1442.04 - -Segment usage by type (index): type utilization - ---- ----------- - 0 0.0833 - 1 0 - 2 0.0208 - -Segment usage by length: length utilization - ------ ----------- - 1 0.0833 - 2 0 - 4 0.0208 - - -Hold Worst Negative Slack (hWNS): 0 ns -Hold Total Negative Slack (hTNS): 0 ns - -Hold slack histogram: -[ 7.3e-10: 7.3e-10) 1 (100.0%) |************************************************** -[ 7.3e-10: 7.3e-10) 0 ( 0.0%) | -[ 7.3e-10: 7.3e-10) 0 ( 0.0%) | -[ 7.3e-10: 7.3e-10) 0 ( 0.0%) | -[ 7.3e-10: 7.3e-10) 0 ( 0.0%) | -[ 7.3e-10: 7.3e-10) 0 ( 0.0%) | -[ 7.3e-10: 7.3e-10) 0 ( 0.0%) | -[ 7.3e-10: 7.3e-10) 0 ( 0.0%) | -[ 7.3e-10: 7.3e-10) 0 ( 0.0%) | -[ 7.3e-10: 7.3e-10) 0 ( 0.0%) | - -Final critical path: 0.86731 ns, Fmax: 1152.99 MHz -Setup Worst Negative Slack (sWNS): -0.86731 ns -Setup Total Negative Slack (sTNS): -0.86731 ns - -Setup slack histogram: -[ -8.7e-10: -8.7e-10) 1 (100.0%) |************************************************** -[ -8.7e-10: -8.7e-10) 0 ( 0.0%) | -[ -8.7e-10: -8.7e-10) 0 ( 0.0%) | -[ -8.7e-10: -8.7e-10) 0 ( 0.0%) | -[ -8.7e-10: -8.7e-10) 0 ( 0.0%) | -[ -8.7e-10: -8.7e-10) 0 ( 0.0%) | -[ -8.7e-10: -8.7e-10) 0 ( 0.0%) | -[ -8.7e-10: -8.7e-10) 0 ( 0.0%) | -[ -8.7e-10: -8.7e-10) 0 ( 0.0%) | -[ -8.7e-10: -8.7e-10) 0 ( 0.0%) | - -Timing analysis took 0.000405567 seconds (0.000363868 STA, 4.1699e-05 slack) (54 full updates: 51 setup, 0 hold, 3 combined). -VPR suceeded -The entire flow of VPR took 0.09 seconds (max_rss 11.9 MiB) - -Command line to execute: read_openfpga_arch -f /research/ece/lnis/USERS/DARPA_ERI/GF14nm_chip_2019/ICC2_Methodology_Flow/GANESH/FROG_PnR/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/run001/vpr_arch/top/MIN_ROUTE_CHAN_WIDTH/arch/openfpga_arch.xml - -Confirm selected options when call command 'read_openfpga_arch': ---file, -f: /research/ece/lnis/USERS/DARPA_ERI/GF14nm_chip_2019/ICC2_Methodology_Flow/GANESH/FROG_PnR/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/run001/vpr_arch/top/MIN_ROUTE_CHAN_WIDTH/arch/openfpga_arch.xml -Reading XML architecture '/research/ece/lnis/USERS/DARPA_ERI/GF14nm_chip_2019/ICC2_Methodology_Flow/GANESH/FROG_PnR/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/run001/vpr_arch/top/MIN_ROUTE_CHAN_WIDTH/arch/openfpga_arch.xml'... -Read OpenFPGA architecture -Warning 52: Automatically set circuit model 'frac_lut4' to be default in its type. -Warning 53: Automatically set circuit model 'sky130_fd_sc_hd__sdfxtp_1' to be default in its type. -Warning 54: Automatically set circuit model 'sky130_fd_sc_hd__dfxtp_1' to be default in its type. -Use the default configurable memory model 'sky130_fd_sc_hd__dfxtp_1' for circuit model 'mux_tree' port 'sram') -Use the default configurable memory model 'sky130_fd_sc_hd__dfxtp_1' for circuit model 'mux_tree_tapbuf' port 'sram') -Use the default configurable memory model 'sky130_fd_sc_hd__dfxtp_1' for circuit model 'frac_lut4' port 'sram') -Read OpenFPGA architecture took 0.00 seconds (max_rss 12.0 MiB, delta_rss +0.1 MiB) -Check circuit library -Checking circuit library passed. -Check circuit library took 0.00 seconds (max_rss 12.3 MiB, delta_rss +0.0 MiB) -Found 0 errors when checking configurable memory circuit models! - -Command line to execute: read_openfpga_simulation_setting -f /research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml - -Confirm selected options when call command 'read_openfpga_simulation_setting': ---file, -f: /research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -Reading XML simulation setting '/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml'... -Read OpenFPGA simulation settings -Read OpenFPGA simulation settings took 0.00 seconds (max_rss 12.3 MiB, delta_rss +0.0 MiB) - -Command line to execute: link_openfpga_arch --activity_file top_ace_out.act --sort_gsb_chan_node_in_edges - -Confirm selected options when call command 'link_openfpga_arch': ---activity_file: top_ace_out.act ---sort_gsb_chan_node_in_edges: on ---verbose: off -Link OpenFPGA architecture to VPR architecture - -Building annotation for physical modes in pb_type...Done -Check physical mode annotation for pb_types passed. - -Building annotation about physical types for pb_type interconnection...Done - -Building annotation between operating and physical pb_types...Done -Check physical pb_type annotation for pb_types passed. - -Building annotation between physical pb_types and circuit models...Done -Check physical pb_type annotation for circuit model passed. - -Building annotation between physical pb_types and mode selection bits...Done -Check pb_type annotation for mode selection bits passed. -Assigning unique indices for primitive pb_graph nodes...Done -Binding operating pb_graph nodes/pins to physical pb_graph nodes/pins...Done -Check pb_graph annotation for physical nodes and pins passed. -Binded 4 routing resource graph switches to circuit models -Binded 3 routing segments to circuit models -Binded 2 direct connections to circuit models -Annotating rr_node with routed nets...Done with 15 nodes mapping -Annotating previous nodes for rr_node...Warning 55: Override the previous node '139' by previous node '137' for node '84' with in routing context annotation! -Done with 18 nodes mapping -# Build General Switch Block(GSB) annotation on top of routing resource graph -[11%] Backannotated GSB[0][0] -[22%] Backannotated GSB[0][1] -[33%] Backannotated GSB[0][2] -[44%] Backannotated GSB[1][0] -[55%] Backannotated GSB[1][1] -[66%] Backannotated GSB[1][2] -[77%] Backannotated GSB[2][0] -[88%] Backannotated GSB[2][1] -[100%] Backannotated GSB[2][2] -Backannotated 9 General Switch Blocks (GSBs). -# Build General Switch Block(GSB) annotation on top of routing resource graph took 0.00 seconds (max_rss 12.3 MiB, delta_rss +0.0 MiB) -# Sort incoming edges for each routing track output node of General Switch Block(GSB) -[11%] Sorted edges for GSB[0][0] -[22%] Sorted edges for GSB[0][1] -[33%] Sorted edges for GSB[0][2] -[44%] Sorted edges for GSB[1][0] -[55%] Sorted edges for GSB[1][1] -[66%] Sorted edges for GSB[1][2] -[77%] Sorted edges for GSB[2][0] -[88%] Sorted edges for GSB[2][1] -[100%] Sorted edges for GSB[2][2] -Sorted edges for 9 General Switch Blocks (GSBs). -# Sort incoming edges for each routing track output node of General Switch Block(GSB) took 0.00 seconds (max_rss 12.3 MiB, delta_rss +0.0 MiB) -# Build a library of physical multiplexers -Built a multiplexer library of 15 physical multiplexers. -Maximum multiplexer size is 17. -# Build a library of physical multiplexers took 0.00 seconds (max_rss 12.5 MiB, delta_rss +0.3 MiB) -# Build the annotation about direct connection between tiles -Built 6 tile-to-tile direct connections -# Build the annotation about direct connection between tiles took 0.00 seconds (max_rss 12.5 MiB, delta_rss +0.0 MiB) -Building annotation for mapped blocks on grid locations...Done -User specified the operating clock frequency to use VPR results -Use VPR critical path delay 1.04077e-18 [ns] with a 20 [%] slack in OpenFPGA. -Will apply operating clock frequency 960.825 [MHz] to simulations -User specified the number of operating clock cycles to be inferred from signal activities -Average net density: 0.42 -Median net density: 0.00 -Average net density after weighting: 0.42 -Will apply 2 operating clock cycles to simulations -Link OpenFPGA architecture to VPR architecture took 0.00 seconds (max_rss 12.6 MiB, delta_rss +0.3 MiB) - -Command line to execute: build_fabric --compress_routing --duplicate_grid_pin --load_fabric_key /research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_task/arch/fabric_key.xml - -Confirm selected options when call command 'build_fabric': ---frame_view: off ---compress_routing: on ---duplicate_grid_pin: on ---load_fabric_key: /research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_task/arch/fabric_key.xml ---write_fabric_key: off ---generate_random_fabric_key: off ---verbose: off -Identify unique General Switch Blocks (GSBs) -Detected 9 unique general switch blocks from a total of 9 (compression rate=0.00%) -Identify unique General Switch Blocks (GSBs) took 0.00 seconds (max_rss 12.6 MiB, delta_rss +0.0 MiB) - -Read Fabric Key -Read Fabric Key took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB) - -Build fabric module graph -# Build constant generator modules -# Build constant generator modules took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB) -# Build user-defined modules -# Build user-defined modules took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB) -# Build essential (inverter/buffer/logic gate) modules -# Build essential (inverter/buffer/logic gate) modules took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB) -# Build local encoder (for multiplexers) modules -# Build local encoder (for multiplexers) modules took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB) -# Building multiplexer modules -# Building multiplexer modules took 0.00 seconds (max_rss 12.9 MiB, delta_rss +0.3 MiB) -# Build Look-Up Table (LUT) modules -# Build Look-Up Table (LUT) modules took 0.00 seconds (max_rss 13.2 MiB, delta_rss +0.3 MiB) -# Build wire modules -# Build wire modules took 0.00 seconds (max_rss 13.2 MiB, delta_rss +0.0 MiB) -# Build memory modules -# Build memory modules took 0.00 seconds (max_rss 13.2 MiB, delta_rss +0.0 MiB) -# Build grid modules -Building logical tiles...Done -Building physical tiles...Done -# Build grid modules took 0.00 seconds (max_rss 13.7 MiB, delta_rss +0.5 MiB) -# Build unique routing modules... -# Build unique routing modules... took 0.02 seconds (max_rss 15.8 MiB, delta_rss +2.1 MiB) -# Build FPGA fabric module -## Add grid instances to top module -## Add grid instances to top module took 0.00 seconds (max_rss 15.8 MiB, delta_rss +0.0 MiB) -## Add switch block instances to top module -## Add switch block instances to top module took 0.00 seconds (max_rss 15.8 MiB, delta_rss +0.0 MiB) -## Add connection block instances to top module -## Add connection block instances to top module took 0.00 seconds (max_rss 15.8 MiB, delta_rss +0.0 MiB) -## Add connection block instances to top module -## Add connection block instances to top module took 0.00 seconds (max_rss 16.0 MiB, delta_rss +0.3 MiB) -## Add module nets between grids and GSBs -## Add module nets between grids and GSBs took 0.01 seconds (max_rss 16.5 MiB, delta_rss +0.5 MiB) -## Add module nets for inter-tile connections -## Add module nets for inter-tile connections took 0.00 seconds (max_rss 16.5 MiB, delta_rss +0.0 MiB) -## Add module nets for configuration buses -## Add module nets for configuration buses took 0.00 seconds (max_rss 16.8 MiB, delta_rss +0.3 MiB) -# Build FPGA fabric module took 0.01 seconds (max_rss 16.8 MiB, delta_rss +1.0 MiB) -Build fabric module graph took 0.03 seconds (max_rss 16.8 MiB, delta_rss +4.1 MiB) -Create I/O location mapping for top module -Create I/O location mapping for top module took 0.00 seconds (max_rss 16.8 MiB, delta_rss +0.0 MiB) - -Command line to execute: repack - -Confirm selected options when call command 'repack': ---verbose: off -Build routing resource graph for the physical implementation of logical tile -Build routing resource graph for the physical implementation of logical tile took 0.00 seconds (max_rss 17.0 MiB, delta_rss +0.3 MiB) -Repack clustered blocks to physical implementation of logical tile -Repack clustered block 'c'...Done -Repack clustered block 'out:c'...Done -Repack clustered block 'a'...Done -Repack clustered block 'b'...Done -Repack clustered blocks to physical implementation of logical tile took 0.00 seconds (max_rss 17.0 MiB, delta_rss +0.0 MiB) -Build truth tables for physical LUTs -Build truth tables for physical LUTs took 0.00 seconds (max_rss 17.0 MiB, delta_rss +0.0 MiB) - -Command line to execute: build_architecture_bitstream --write_file fabric_indepenent_bitstream.xml - -Confirm selected options when call command 'build_architecture_bitstream': ---write_file: fabric_indepenent_bitstream.xml ---read_file: off ---verbose: off - -Build fabric-independent bitstream for implementation 'top' - -Generating bitstream for Switch blocks...Done -Generating bitstream for X-direction Connection blocks ...Done -Generating bitstream for Y-direction Connection blocks ...Done - -Build fabric-independent bitstream for implementation 'top' - took 0.01 seconds (max_rss 17.0 MiB, delta_rss +0.0 MiB) -Warning 56: Directory path is empty and nothing will be created. -Write 2106 architecture independent bitstream into XML file 'fabric_indepenent_bitstream.xml' -Write 2106 architecture independent bitstream into XML file 'fabric_indepenent_bitstream.xml' took 0.03 seconds (max_rss 17.3 MiB, delta_rss +0.3 MiB) - -Command line to execute: build_fabric_bitstream - -Confirm selected options when call command 'build_fabric_bitstream': ---verbose: off - -Build fabric dependent bitstream - - -Build fabric dependent bitstream - took 0.00 seconds (max_rss 17.3 MiB, delta_rss +0.0 MiB) - -Command line to execute: write_fabric_bitstream --format plain_text --file fabric_bitstream.bit - -Confirm selected options when call command 'write_fabric_bitstream': ---file, -f: fabric_bitstream.bit ---format: plain_text ---verbose: off -Warning 57: Directory path is empty and nothing will be created. -Write 2106 fabric bitstream into plain text file 'fabric_bitstream.bit' -Write 2106 fabric bitstream into plain text file 'fabric_bitstream.bit' took 0.00 seconds (max_rss 17.3 MiB, delta_rss +0.0 MiB) - -Command line to execute: write_fabric_bitstream --format xml --file fabric_bitstream.xml - -Confirm selected options when call command 'write_fabric_bitstream': ---file, -f: fabric_bitstream.xml ---format: xml ---verbose: off -Warning 58: Directory path is empty and nothing will be created. -Write 2106 fabric bitstream into xml file 'fabric_bitstream.xml' -Write 2106 fabric bitstream into xml file 'fabric_bitstream.xml' took 0.01 seconds (max_rss 17.3 MiB, delta_rss +0.0 MiB) - -Command line to execute: write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --verbose - -Confirm selected options when call command 'write_fabric_verilog': ---file, -f: ./SRC ---explicit_port_mapping: on ---include_timing: on ---include_signal_init: on ---support_icarus_simulator: on ---print_user_defined_template: off ---verbose: on -Write Verilog netlists for FPGA fabric - -Succeed to create directory './SRC' -Succeed to create directory './SRC/sub_module' -Succeed to create directory './SRC/lb' -Succeed to create directory './SRC/routing' -Generating Verilog netlist './SRC/sub_module/inv_buf_passgate.v' for essential gates...Done -Writing Verilog netlist for configuration decoders './SRC/sub_module/arch_encoder.v'...Done -Writing Verilog netlist for local decoders for multiplexers './SRC/sub_module/local_encoder.v'...Done -Writing Verilog netlist for Multiplexers './SRC/sub_module/muxes.v' ...Done -Writing Verilog netlist for LUTs './SRC/sub_module/luts.v'...Done -Writing Verilog netlist for wires './SRC/sub_module/wires.v'...Done -Writing Verilog netlist for memories './SRC/sub_module/memories.v' ...Done - -Writing logical tiles... -Writing Verilog netlists for logic tile 'io' ... -Writing Verilog netlist './SRC/lb/logical_tile_io_mode_physical__iopad.v' for primitive pb_type 'iopad' ... -Writing Verilog codes of logical tile primitive block 'logical_tile_io_mode_physical__iopad'...Done -Writing Verilog netlist './SRC/lb/logical_tile_io_mode_io_.v' for pb_type 'io' ... -Writing Verilog codes of pb_type 'logical_tile_io_mode_io_'...Done -Done - -Writing Verilog netlists for logic tile 'clb' ... -Writing Verilog netlist './SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4.v' for primitive pb_type 'frac_lut4' ... -Writing Verilog codes of logical tile primitive block 'logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4'...Done -Writing Verilog netlist './SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.v' for pb_type 'frac_logic' ... -Writing Verilog codes of pb_type 'logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic'...Done -Writing Verilog netlist './SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v' for primitive pb_type 'ff' ... -Writing Verilog codes of logical tile primitive block 'logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff'...Done -Writing Verilog netlist './SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v' for pb_type 'fabric' ... -Writing Verilog codes of pb_type 'logical_tile_clb_mode_default__fle_mode_physical__fabric'...Done -Writing Verilog netlist './SRC/lb/logical_tile_clb_mode_default__fle.v' for pb_type 'fle' ... -Writing Verilog codes of pb_type 'logical_tile_clb_mode_default__fle'...Done -Writing Verilog netlist './SRC/lb/logical_tile_clb_mode_clb_.v' for pb_type 'clb' ... -Writing Verilog codes of pb_type 'logical_tile_clb_mode_clb_'...Done -Done - -Writing logical tiles...Done - -Building physical tiles... -Writing Verilog Netlist './SRC/lb/grid_io_top_top.v' for physical tile 'io_top' at top side ...Done -Writing Verilog Netlist './SRC/lb/grid_io_right_right.v' for physical tile 'io_right' at right side ...Done -Writing Verilog Netlist './SRC/lb/grid_io_bottom_bottom.v' for physical tile 'io_bottom' at bottom side ...Done -Writing Verilog Netlist './SRC/lb/grid_io_left_left.v' for physical tile 'io_left' at left side ...Done -Writing Verilog Netlist './SRC/lb/grid_clb.v' for physical_tile 'clb'...Done -Building physical tiles...Done - -Writing Verilog netlist for top-level module of FPGA fabric './SRC/fpga_top.v'...Done -Written 73 Verilog modules in total -Write Verilog netlists for FPGA fabric - took 0.19 seconds (max_rss 17.7 MiB, delta_rss +0.4 MiB) - -Command line to execute: write_verilog_testbench --file ./SRC --reference_benchmark_file_path top_output_verilog.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping - -Confirm selected options when call command 'write_verilog_testbench': ---file, -f: ./SRC ---fabric_netlist_file_path: off ---reference_benchmark_file_path: top_output_verilog.v ---print_top_testbench: on ---fast_configuration: off ---print_formal_verification_top_netlist: off ---print_preconfig_top_testbench: on ---print_simulation_ini: ./SimulationDeck/simulation_deck.ini ---explicit_port_mapping: on ---verbose: off -Warning 59: Forcely enable to print top-level Verilog netlist in formal verification purpose as print pre-configured top-level Verilog testbench is enabled -Write Verilog testbenches for FPGA fabric - -Warning 60: Directory './SRC' already exists. Will overwrite contents -# Write pre-configured FPGA top-level Verilog netlist for design 'top' -# Write pre-configured FPGA top-level Verilog netlist for design 'top' took 0.01 seconds (max_rss 17.7 MiB, delta_rss +0.0 MiB) -# Write configuration-skip testbench for FPGA top-level Verilog netlist implemented by 'top' -# Write configuration-skip testbench for FPGA top-level Verilog netlist implemented by 'top' took 0.00 seconds (max_rss 17.7 MiB, delta_rss +0.0 MiB) -# Write autocheck testbench for FPGA top-level Verilog netlist for 'top' -Will use 2107 configuration clock cycles to top testbench -# Write autocheck testbench for FPGA top-level Verilog netlist for 'top' took 0.01 seconds (max_rss 17.8 MiB, delta_rss +0.1 MiB) -Succeed to create directory './SimulationDeck' -# Write exchangeable file containing simulation information './SimulationDeck/simulation_deck.ini' -# Write exchangeable file containing simulation information './SimulationDeck/simulation_deck.ini' took 0.00 seconds (max_rss 17.8 MiB, delta_rss +0.0 MiB) -Write Verilog testbenches for FPGA fabric - took 0.03 seconds (max_rss 17.8 MiB, delta_rss +0.1 MiB) - -Command line to execute: exit - -Confirm selected options when call command 'exit': - -Finish execution with 0 errors - -The entire OpenFPGA flow took 0.25 seconds - -Thank you for using OpenFPGA! diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/proj_const.tcl b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/proj_const.tcl deleted file mode 100644 index 7fba78d..0000000 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/proj_const.tcl +++ /dev/null @@ -1,13 +0,0 @@ -set DIE_HEIGHT 700 -set DIE_WIDTH 700 -set DESIGN_NAME fpga_core -set TASK_NAME FPGA22_HIER_SKY_task -set VERILOG_PROJ_DIR FPGA22_HIER_SKY_Verilog -set FPGA_ROW 2 -set FPGA_COL 2 -set INIT_DESIGN_INPUT DP_RM_NDM -set TECHNOLOGY skywater -set DP_BLOCK_REFS [list sb_0__0_ sb_0__1_ sb_0__2_ sb_1__0_ sb_1__1_ sb_1__2_ sb_2__0_ sb_2__1_ sb_2__2_ cbx_1__0_ cbx_1__1_ cbx_1__2_ cby_0__1_ cby_1__1_ cby_2__1_ grid_clb]; -set DP_FLOW "hier"; -set DESIGN_STYLE "hier"; -set STANDARD_CELLS sc_hd; diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/arch/fabric_key.xml b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/arch/fabric_key.xml deleted file mode 100644 index 47f4507..0000000 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/arch/fabric_key.xml +++ /dev/null @@ -1,38 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/arch/openfpga_arch.xml b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/arch/openfpga_arch.xml deleted file mode 100644 index 1d3208c..0000000 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/arch/openfpga_arch.xml +++ /dev/null @@ -1,248 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - - - - - 10e-12 5e-12 - - - 10e-12 5e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/arch/vpr_arch.xml b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/arch/vpr_arch.xml deleted file mode 100644 index 62a7869..0000000 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/arch/vpr_arch.xml +++ /dev/null @@ -1,670 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - io_top.outpad io_top.inpad - - - - - - - - - - - - io_right.outpad io_right.inpad - - - - - - - - - - - - io_bottom.outpad io_bottom.inpad - - - - - - - - - - - - io_left.outpad io_left.inpad - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - clb.clk - clb.regin clb.sc_in clb.O[7:0] clb.I0 clb.I0i clb.I1 clb.I1i clb.I2 clb.I2i clb.I3 clb.I3i - clb.O[15:8] clb.I4 clb.I4i clb.I5 clb.I5i clb.I6 clb.I6i clb.I7 clb.I7i - clb.regout clb.sc_out - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 - 1 - - - - 1 1 1 - 1 1 - - - - 1 1 1 1 1 - 1 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 235e-12 - 235e-12 - 235e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 261e-12 - 261e-12 - 261e-12 - 261e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/config/task.conf b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/config/task.conf deleted file mode 100644 index e372ec2..0000000 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/config/task.conf +++ /dev/null @@ -1,37 +0,0 @@ - # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# Configuration file for running experiments -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs -# Each job execute fpga_flow script on combination of architecture & benchmark -# timeout_each_job is timeout for each job -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = - -[GENERAL] -run_engine=openfpga_shell -power_analysis = false -spice_output=false -verilog_output=true -timeout_each_job = 20*60 -fpga_flow=vpr_blif - -[OpenFPGA_SHELL] -openfpga_shell_template=${PATH:TASK_DIR}/generate_fabric.openfpga -openfpga_arch_file=${PATH:TASK_DIR}/arch/openfpga_arch.xml -openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -external_fabric_key_file=${PATH:TASK_DIR}/arch/fabric_key.xml -openfpga_vpr_device_layout=2x2 -openfpga_vpr_route_chan_width=40 - -[ARCHITECTURES] -arch0=${PATH:TASK_DIR}/arch/vpr_arch.xml - -[BENCHMARKS] -bench0=${PATH:TASK_DIR}/micro_benchmark/and.blif - -[SYNTHESIS_PARAM] -bench0_top = top -bench0_act = ${PATH:TASK_DIR}/micro_benchmark/and.act -bench0_verilog = ${PATH:TASK_DIR}/micro_benchmark/and.v - -[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] -vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/config/task_generation.conf b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/config/task_generation.conf deleted file mode 100644 index e372ec2..0000000 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/config/task_generation.conf +++ /dev/null @@ -1,37 +0,0 @@ - # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# Configuration file for running experiments -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs -# Each job execute fpga_flow script on combination of architecture & benchmark -# timeout_each_job is timeout for each job -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = - -[GENERAL] -run_engine=openfpga_shell -power_analysis = false -spice_output=false -verilog_output=true -timeout_each_job = 20*60 -fpga_flow=vpr_blif - -[OpenFPGA_SHELL] -openfpga_shell_template=${PATH:TASK_DIR}/generate_fabric.openfpga -openfpga_arch_file=${PATH:TASK_DIR}/arch/openfpga_arch.xml -openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -external_fabric_key_file=${PATH:TASK_DIR}/arch/fabric_key.xml -openfpga_vpr_device_layout=2x2 -openfpga_vpr_route_chan_width=40 - -[ARCHITECTURES] -arch0=${PATH:TASK_DIR}/arch/vpr_arch.xml - -[BENCHMARKS] -bench0=${PATH:TASK_DIR}/micro_benchmark/and.blif - -[SYNTHESIS_PARAM] -bench0_top = top -bench0_act = ${PATH:TASK_DIR}/micro_benchmark/and.act -bench0_verilog = ${PATH:TASK_DIR}/micro_benchmark/and.v - -[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] -vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/config/task_simulation.conf b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/config/task_simulation.conf deleted file mode 100644 index 0f65eca..0000000 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/config/task_simulation.conf +++ /dev/null @@ -1,33 +0,0 @@ -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# Configuration file for running experiments -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs -# Each job execute fpga_flow script on combination of architecture & benchmark -# timeout_each_job is timeout for each job -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = - -[GENERAL] -run_engine=openfpga_shell -power_analysis = false -spice_output=false -verilog_output=true -timeout_each_job = 20*60 -fpga_flow=vpr_blif -openfpga_shell_template=${PATH:TASK_DIR}/openfpga_flow/tasks/FPGA22_MODULAR_task/generate_testbench.openfpga -openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/arch/openfpga_arch.xml -openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -external_fabric_key_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/arch/fabric_key.xml - -[ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/arch/vpr_arch.xml - -[BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/micro_benchmark/and.blif - -[SYNTHESIS_PARAM] -bench0_top = top -bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/micro_benchmark/and.act -bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/micro_benchmark/and.v - -[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] -vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/expand_sdc.py b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/expand_sdc.py deleted file mode 100644 index 75f4ab1..0000000 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/expand_sdc.py +++ /dev/null @@ -1,71 +0,0 @@ -import yaml -import argparse -import pprint as pp -import glob -import os - - -def formatter(prog): return argparse.HelpFormatter(prog, max_help_position=60) - - -parser = argparse.ArgumentParser(formatter_class=formatter) - -# Mandatory arguments -parser.add_argument('--hierfile', type=str, default="design.hier") -parser.add_argument('--shellscript_name', type=str, default="sdc_expand.sh") -parser.add_argument('--in_dir', type=str, default="./sdc/") -parser.add_argument('--out_dir', type=str, default="./sdc/expanded") -parser.add_argument('--extract_format', type=str, default="tcl") -parser.add_argument('--compress', type=bool, default=False) -args = parser.parse_args() - -print(f"In_dir = {args.in_dir}") -print(f"Out_dir = {args.out_dir}") -if args.extract_format == "sdc": - with open(args.hierfile) as f: - with open(args.shellscript_name, 'w') as fp: - designHier = yaml.load(f, Loader=yaml.FullLoader) - for eachHier in designHier: - for eachMod, instanceList in eachHier.items(): - fp.write(f"mkdir -p {eachMod}\n") - for eachInst in instanceList: - eachInst = eachInst.replace("/", "_") - st = (f"sed \"s/{eachMod}/{eachInst}/g\" {args.in_dir}/{eachMod}.sdc " + - f"> {args.out_dir}/{eachInst}/{eachInst}.sdc\n") - fp.write(st) - if args.compress: - fp.write(f"tar -zcvf {args.out_dir}/{eachMod}.tar.gz " - f"{args.out_dir}/{eachInst}/") -elif args.extract_format == "tcl": - files = glob.glob(os.path.join(args.in_dir, 'grid*.txt')) - filename = files[0] - print(f"Reading {filename}") - with open(filename) as f: - with open(args.shellscript_name, 'w') as fp: - designHier = yaml.load(f, Loader=yaml.FullLoader)[:5] - for eachModule in designHier: - ForLoopStruct = [] - while True: - instList = eachModule[list(eachModule.keys())[0]] - iterAgain = all([isinstance(ele, str) for ele in instList]) - if (iterAgain): - # print(list(eachModule.keys())[0]) - # print(f">> leaf Instance {instList}") - ForLoopStruct.append({ - list(eachModule.keys())[0]: - instList - }) - break - else: - ForLoopStruct.append({ - list(eachModule.keys())[0]: - [list(ee.keys())[0] for ee in instList] - }) - # print(list(eachModule.keys())[0]) - # print([list(ee.keys())[0] for ee in instList]) - eachModule = instList[0] - del ForLoopStruct[1::2] - print("= = "*10) - print("ForLoop Struct") - pp.pprint(ForLoopStruct) - print("= = "*10) diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/generate_fabric.openfpga b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/generate_fabric.openfpga deleted file mode 100644 index 2c8e5b5..0000000 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/generate_fabric.openfpga +++ /dev/null @@ -1,46 +0,0 @@ -# This script is designed to generate fabric Verilog netlists -# with a fixed device layout -# It will only output netlists to be used by backend tools, -# i.e., Synopsys ICC2, including -# - Verilog netlists -# - fabric hierarchy description for ICC2's hierarchical flow -# - Timing/Design constraints -# -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --absorb_buffer_luts off - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} - -# Read OpenFPGA simulation settings -read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} - -# Annotate the OpenFPGA architecture to VPR data base -# to debug use --verbose options -link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --compress_routing --duplicate_grid_pin --load_fabric_key ${EXTERNAL_FABRIC_KEY_FILE} - -# Repack the netlist to physical pbs -# This must be done before bitstream generator and testbench generation -# Strongly recommend it is done after all the fix-up have been applied -repack - -build_architecture_bitstream --write_file fabric_indepenent_bitstream.xml - -build_fabric_bitstream -write_fabric_bitstream --format plain_text --file fabric_bitstream.bit -write_fabric_bitstream --format xml --file fabric_bitstream.xml - -# Write the Verilog netlist for FPGA fabric -# - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --verbose - -write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping -# Finish and exit OpenFPGA -exit - -# Note : -# To run verification at the end of the flow maintain source in ./SRC directory \ No newline at end of file diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/generate_testbench.openfpga b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/generate_testbench.openfpga deleted file mode 100644 index 124dbcd..0000000 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/generate_testbench.openfpga +++ /dev/null @@ -1,70 +0,0 @@ -# Run VPR for the 'and' design -#--write_rr_graph example_rr_graph.xml -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --route_chan_width 200 - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} - -# Read OpenFPGA simulation settings -read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} - -# Annotate the OpenFPGA architecture to VPR data base -# to debug use --verbose options -link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges - -# Check and correct any naming conflicts in the BLIF netlist -check_netlist_naming_conflict --fix --report ./netlist_renaming.xml - -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - -# Apply fix-up to Look-Up Table truth tables based on packing results -lut_truth_table_fixup - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --compress_routing --duplicate_grid_pin --load_fabric_key ${EXTERNAL_FABRIC_KEY_FILE} - -# Write the fabric hierarchy of module graph to a file -# This is used by hierarchical PnR flows -write_fabric_hierarchy --file ./fabric_hierarchy.txt - -# Repack the netlist to physical pbs -# This must be done before bitstream generator and testbench generation -# Strongly recommend it is done after all the fix-up have been applied -repack #--verbose - -# Build the bitstream -# - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --write_file fabric_indepenent_bitstream.xml - -build_fabric_bitstream - -# Build fabric-dependent bitstream -build_fabric_bitstream -write_fabric_bitstream --format plain_text --file fabric_bitstream.bit -write_fabric_bitstream --format xml --file fabric_bitstream.xml -# Write the Verilog testbench for FPGA fabric -# - We suggest the use of same output directory as fabric Verilog netlists -# - Must specify the reference benchmark file if you want to output any testbenches -# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA -# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase -# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --file ./SDC - -# Write SDC to disable timing for configure ports -write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file ./SDC_analysis - -# Finish and exit OpenFPGA -exit - -# Note : -# To run verification at the end of the flow maintain source in ./SRC directory \ No newline at end of file diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/micro_benchmark/and.act b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/micro_benchmark/and.act deleted file mode 100644 index 0f77bc6..0000000 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/micro_benchmark/and.act +++ /dev/null @@ -1,3 +0,0 @@ -a 0.5 0.5 -b 0.5 0.5 -c 0.25 0.25 diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/micro_benchmark/and.blif b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/micro_benchmark/and.blif deleted file mode 100644 index 67d9787..0000000 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/micro_benchmark/and.blif +++ /dev/null @@ -1,8 +0,0 @@ -.model top -.inputs a b -.outputs c - -.names a b c -11 1 - -.end diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/micro_benchmark/and.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/micro_benchmark/and.v deleted file mode 100644 index 876f1c6..0000000 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/micro_benchmark/and.v +++ /dev/null @@ -1,14 +0,0 @@ -`timescale 1ns / 1ps - -module top( - a, - b, - c); - -input wire a; -input wire b; -output wire c; - -assign c = a & b; - -endmodule diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/sc_verilog/digital_io_hd.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/sc_verilog/digital_io_hd.v deleted file mode 100644 index 0dcc04f..0000000 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/sc_verilog/digital_io_hd.v +++ /dev/null @@ -1,63 +0,0 @@ -`timescale 1ns/1ps - -module GPIO (A, IE, OE, Y, in, out, mem_out); - output A; - output IE; - output OE; - output Y; - input in; - output out; - input mem_out; - - assign A = in; - assign out = Y; - assign IE = mem_out; - sky130_fd_sc_hd__inv_1 ie_oe_inv ( - .A (mem_out), - .Y (OE) ); -endmodule - - -// -// -// -// -module EMBEDDED_IO ( - input SOC_IN, // - output SOC_OUT, // - output SOC_DIR, // - output FPGA_IN, // - input FPGA_OUT, // - input FPGA_DIR // -); - - assign FPGA_IN = SOC_IN; - assign SOC_OUT = FPGA_OUT; - assign SOC_DIR = FPGA_DIR; -endmodule - -// -// -// -module GPIN ( - inout A, // - output Y // -); - // - sky130_fd_sc_hd__buf_4 in_buf ( - .A (A), - .X (Y) ); -endmodule - -// -// -// -module GPOUT ( - inout Y, // - input A // -); - // - sky130_fd_sc_hd__buf_4 in_buf ( - .A (A), - .X (Y) ); -endmodule diff --git a/FPGA22_HIER_SKY_PNR/README.md b/FPGA22_HIER_SKY_PNR/README.md deleted file mode 100644 index f1baa09..0000000 --- a/FPGA22_HIER_SKY_PNR/README.md +++ /dev/null @@ -1,32 +0,0 @@ -FPGA22_HIER_SKY_PNR -==================== - -2x2 FPGA designed using hierarchical flow and `SKY130_FD_SC_HD`. - -Updates -------------------- -- Merged `grid_io` modules with connection blocks -- Pre-routed scan chain signals -- Created `carry_chain` feedthrough between `grid_clb` modules -- **Prerouting global signals (`Test_en`)** -- **Prerouting clock signals** -- **Enabled Feed through generation for clock** - -Directory Structure -------------------- -- **FPGA22_HIER_SKY_task** :- OpenFPGA task directory and all related files -- **FPGA22_HIER_SKY_Verilog** :- Verilog-netlist used for this design -- **modules** :- Final files of each module (lef,def,spef,v,gds) -- **fpga_core** :- Final files of fpga_core (eFPGA design) -- **fpga_top** :- Reserved for design with GPIOs or caravel - -Checks ---------- -- .tech file DRC - Clean -- Timing SignOff - Clean - -Pending ---------- -- DRC SignOff -- LVS SignOff -- PostPnR functional simulation diff --git a/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/ConfigFlipFLop.png b/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/ConfigFlipFLop.png deleted file mode 100644 index 410b7dc..0000000 Binary files a/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/ConfigFlipFLop.png and /dev/null differ diff --git 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a/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/power_contacts.png b/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/power_contacts.png deleted file mode 100644 index ce2f53a..0000000 Binary files a/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/power_contacts.png and /dev/null differ diff --git a/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/utilization.png b/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/utilization.png deleted file mode 100644 index e370106..0000000 Binary files a/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/utilization.png and /dev/null differ diff --git a/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.fm.v b/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.fm.v deleted file mode 100644 index eec69c9..0000000 --- a/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.fm.v +++ /dev/null @@ -1,36286 +0,0 @@ -// -// -// -// -// -// -module direct_interc ( in , out ) ; -input [0:0] in ; -output [0:0] out ; -endmodule - - -module direct_interc_4 ( in , out ) ; -input [0:0] in ; -output [0:0] out ; -endmodule - - -module direct_interc_3 ( in , out ) ; -input [0:0] in ; -output [0:0] out ; -endmodule - - -module direct_interc_2 ( in , out ) ; -input [0:0] in ; -output [0:0] out ; - -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__2 ( .A ( in[0] ) , .X ( out[0] ) ) ; -endmodule - - -module direct_interc_1 ( in , out ) ; -input [0:0] in ; -output [0:0] out ; - -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__1 ( .A ( in[0] ) , .X ( out[0] ) ) ; -endmodule - - -module direct_interc_0 ( in , out ) ; -input [0:0] in ; -output [0:0] out ; - -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__0 ( .A ( in[0] ) , .X ( out[0] ) ) ; -endmodule - - -module cby_2__1__direct_interc ( in , out ) ; -input [0:0] in ; -output [0:0] out ; - -assign out[0] = in[0] ; -endmodule - - -module cby_2__1__direct_interc_0 ( in , out ) ; -input [0:0] in ; -output [0:0] out ; -endmodule - - -module cby_2__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( prog_clk , - ccff_head , ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:0] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_20__60 ( .A ( mem_out[0] ) , - .X ( net_net_80 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_80 ( .A ( net_net_80 ) , - .X ( net_net_79 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_101 ( .A ( net_net_79 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_2__1__EMBEDDED_IO ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , - FPGA_OUT , FPGA_DIR , p_abuf0 ) ; -input SOC_IN ; -output SOC_OUT ; -output SOC_DIR ; -output FPGA_IN ; -input FPGA_OUT ; -input FPGA_DIR ; -output p_abuf0 ; - -assign SOC_OUT = FPGA_OUT ; - -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__58 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 FTB_19__59 ( .A ( FPGA_DIR ) , - .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_62 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; -endmodule - - -module cby_2__1__logical_tile_io_mode_physical__iopad ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] iopad_outpad ; -input [0:0] ccff_head ; -output [0:0] iopad_inpad ; -output [0:0] ccff_tail ; -output p_abuf0 ; - -wire [0:0] EMBEDDED_IO_0_en ; - -cby_2__1__EMBEDDED_IO EMBEDDED_IO_0_ ( - .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , - .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , - .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , - .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; -cby_2__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) ) ; -endmodule - - -module cby_2__1__logical_tile_io_mode_io_ ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , - ccff_tail , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] io_outpad ; -input [0:0] ccff_head ; -output [0:0] io_inpad ; -output [0:0] ccff_tail ; -output p_abuf0 ; - -cby_2__1__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , - .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , - .p_abuf0 ( p_abuf0 ) ) ; -cby_2__1__direct_interc_0 direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; -cby_2__1__direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( io_outpad ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__57 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__56 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__55 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__54 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__53 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__52 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__51 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__50 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_2__1__const1 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -cby_2__1__const1 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cby_2__1__const1_15 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -cby_2__1__const1_15 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cby_2__1__const1_14 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -cby_2__1__const1_14 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_4 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; -endmodule - - -module cby_2__1__const1_13 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -cby_2__1__const1_13 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cby_2__1__const1_12 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -cby_2__1__const1_12 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cby_2__1__const1_11 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -cby_2__1__const1_11 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cby_2__1__const1_10 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -cby_2__1__const1_10 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cby_2__1__const1_9 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -cby_2__1__const1_9 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__49 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__48 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__47 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__46 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__45 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__44 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__43 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__42 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__41 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_2__1__const1_8 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -cby_2__1__const1_8 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cby_2__1__const1_7 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -cby_2__1__const1_7 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cby_2__1__const1_6 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -cby_2__1__const1_6 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cby_2__1__const1_5 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -cby_2__1__const1_5 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cby_2__1__const1_4 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -cby_2__1__const1_4 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cby_2__1__const1_3 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -cby_2__1__const1_3 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cby_2__1__const1_2 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -cby_2__1__const1_2 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cby_2__1__const1_1 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -cby_2__1__const1_1 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cby_2__1__const1_0 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -cby_2__1__const1_0 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cby_2__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , - chany_bottom_out , chany_top_out , right_grid_pin_0_ , left_grid_pin_16_ , - left_grid_pin_17_ , left_grid_pin_18_ , left_grid_pin_19_ , - left_grid_pin_20_ , left_grid_pin_21_ , left_grid_pin_22_ , - left_grid_pin_23_ , left_grid_pin_24_ , left_grid_pin_25_ , - left_grid_pin_26_ , left_grid_pin_27_ , left_grid_pin_28_ , - left_grid_pin_29_ , left_grid_pin_30_ , left_grid_pin_31_ , ccff_tail , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , left_width_0_height_0__pin_0_ , - left_width_0_height_0__pin_1_upper , left_width_0_height_0__pin_1_lower ) ; -input [0:0] prog_clk ; -input [0:19] chany_bottom_in ; -input [0:19] chany_top_in ; -input [0:0] ccff_head ; -output [0:19] chany_bottom_out ; -output [0:19] chany_top_out ; -output [0:0] right_grid_pin_0_ ; -output [0:0] left_grid_pin_16_ ; -output [0:0] left_grid_pin_17_ ; -output [0:0] left_grid_pin_18_ ; -output [0:0] left_grid_pin_19_ ; -output [0:0] left_grid_pin_20_ ; -output [0:0] left_grid_pin_21_ ; -output [0:0] left_grid_pin_22_ ; -output [0:0] left_grid_pin_23_ ; -output [0:0] left_grid_pin_24_ ; -output [0:0] left_grid_pin_25_ ; -output [0:0] left_grid_pin_26_ ; -output [0:0] left_grid_pin_27_ ; -output [0:0] left_grid_pin_28_ ; -output [0:0] left_grid_pin_29_ ; -output [0:0] left_grid_pin_30_ ; -output [0:0] left_grid_pin_31_ ; -output [0:0] ccff_tail ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] left_width_0_height_0__pin_0_ ; -output [0:0] left_width_0_height_0__pin_1_upper ; -output [0:0] left_width_0_height_0__pin_1_lower ; - -wire ropt_net_114 ; -wire [0:3] mux_left_ipin_0_undriven_sram_inv ; -wire [0:3] mux_right_ipin_0_undriven_sram_inv ; -wire [0:3] mux_right_ipin_10_undriven_sram_inv ; -wire [0:3] mux_right_ipin_11_undriven_sram_inv ; -wire [0:3] mux_right_ipin_12_undriven_sram_inv ; -wire [0:3] mux_right_ipin_13_undriven_sram_inv ; -wire [0:3] mux_right_ipin_14_undriven_sram_inv ; -wire [0:3] mux_right_ipin_15_undriven_sram_inv ; -wire [0:3] mux_right_ipin_1_undriven_sram_inv ; -wire [0:3] mux_right_ipin_2_undriven_sram_inv ; -wire [0:3] mux_right_ipin_3_undriven_sram_inv ; -wire [0:3] mux_right_ipin_4_undriven_sram_inv ; -wire [0:3] mux_right_ipin_5_undriven_sram_inv ; -wire [0:3] mux_right_ipin_6_undriven_sram_inv ; -wire [0:3] mux_right_ipin_7_undriven_sram_inv ; -wire [0:3] mux_right_ipin_8_undriven_sram_inv ; -wire [0:3] mux_right_ipin_9_undriven_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:3] mux_tree_tapbuf_size10_2_sram ; -wire [0:3] mux_tree_tapbuf_size10_3_sram ; -wire [0:3] mux_tree_tapbuf_size10_4_sram ; -wire [0:3] mux_tree_tapbuf_size10_5_sram ; -wire [0:3] mux_tree_tapbuf_size10_6_sram ; -wire [0:3] mux_tree_tapbuf_size10_7_sram ; -wire [0:3] mux_tree_tapbuf_size10_8_sram ; -wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:3] mux_tree_tapbuf_size8_2_sram ; -wire [0:3] mux_tree_tapbuf_size8_3_sram ; -wire [0:3] mux_tree_tapbuf_size8_4_sram ; -wire [0:3] mux_tree_tapbuf_size8_5_sram ; -wire [0:3] mux_tree_tapbuf_size8_6_sram ; -wire [0:3] mux_tree_tapbuf_size8_7_sram ; -wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ; - -cby_2__1__mux_tree_tapbuf_size10_0 mux_left_ipin_0 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , - chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , - chany_top_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_left_ipin_0_undriven_sram_inv ) , - .out ( right_grid_pin_0_ ) , .p0 ( optlc_net_111 ) ) ; -cby_2__1__mux_tree_tapbuf_size10_1 mux_right_ipin_0 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , - chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[17] , - chany_top_in[17] } ) , - .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_right_ipin_0_undriven_sram_inv ) , - .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_110 ) ) ; -cby_2__1__mux_tree_tapbuf_size10_5 mux_right_ipin_3 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , - chany_bottom_in[8] , chany_top_in[8] , chany_bottom_in[14] , - chany_top_in[14] } ) , - .sram ( mux_tree_tapbuf_size10_2_sram ) , - .sram_inv ( mux_right_ipin_3_undriven_sram_inv ) , - .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_109 ) ) ; -cby_2__1__mux_tree_tapbuf_size10_6 mux_right_ipin_4 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , - chany_bottom_in[9] , chany_top_in[9] , chany_bottom_in[15] , - chany_top_in[15] } ) , - .sram ( mux_tree_tapbuf_size10_3_sram ) , - .sram_inv ( mux_right_ipin_4_undriven_sram_inv ) , - .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_108 ) ) ; -cby_2__1__mux_tree_tapbuf_size10_7 mux_right_ipin_7 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[8] , chany_top_in[8] , - chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[18] , - chany_top_in[18] } ) , - .sram ( mux_tree_tapbuf_size10_4_sram ) , - .sram_inv ( mux_right_ipin_7_undriven_sram_inv ) , - .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_109 ) ) ; -cby_2__1__mux_tree_tapbuf_size10 mux_right_ipin_8 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , - chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[19] , - chany_top_in[19] } ) , - .sram ( mux_tree_tapbuf_size10_5_sram ) , - .sram_inv ( mux_right_ipin_8_undriven_sram_inv ) , - .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_108 ) ) ; -cby_2__1__mux_tree_tapbuf_size10_2 mux_right_ipin_11 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , - chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[16] , - chany_top_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_6_sram ) , - .sram_inv ( mux_right_ipin_11_undriven_sram_inv ) , - .out ( left_grid_pin_27_ ) , .p0 ( optlc_net_109 ) ) ; -cby_2__1__mux_tree_tapbuf_size10_3 mux_right_ipin_12 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , - chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[17] , - chany_top_in[17] } ) , - .sram ( mux_tree_tapbuf_size10_7_sram ) , - .sram_inv ( mux_right_ipin_12_undriven_sram_inv ) , - .out ( left_grid_pin_28_ ) , .p0 ( optlc_net_108 ) ) ; -cby_2__1__mux_tree_tapbuf_size10_4 mux_right_ipin_15 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , - chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , - chany_top_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_8_sram ) , - .sram_inv ( mux_right_ipin_15_undriven_sram_inv ) , - .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_111 ) ) ; -cby_2__1__mux_tree_tapbuf_size10_mem_0 mem_left_ipin_0 ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; -cby_2__1__mux_tree_tapbuf_size10_mem_1 mem_right_ipin_0 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ; -cby_2__1__mux_tree_tapbuf_size10_mem_5 mem_right_ipin_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ; -cby_2__1__mux_tree_tapbuf_size10_mem_6 mem_right_ipin_4 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ; -cby_2__1__mux_tree_tapbuf_size10_mem_7 mem_right_ipin_7 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ; -cby_2__1__mux_tree_tapbuf_size10_mem mem_right_ipin_8 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ; -cby_2__1__mux_tree_tapbuf_size10_mem_2 mem_right_ipin_11 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ; -cby_2__1__mux_tree_tapbuf_size10_mem_3 mem_right_ipin_12 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ; -cby_2__1__mux_tree_tapbuf_size10_mem_4 mem_right_ipin_15 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , - .mem_out ( mux_tree_tapbuf_size10_8_sram ) ) ; -cby_2__1__mux_tree_tapbuf_size8_0 mux_right_ipin_1 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , - chany_bottom_in[14] , chany_top_in[14] } ) , - .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_right_ipin_1_undriven_sram_inv ) , - .out ( left_grid_pin_17_ ) , .p0 ( optlc_net_111 ) ) ; -cby_2__1__mux_tree_tapbuf_size8_4 mux_right_ipin_2 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , - chany_bottom_in[15] , chany_top_in[15] } ) , - .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_right_ipin_2_undriven_sram_inv ) , - .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_108 ) ) ; -cby_2__1__mux_tree_tapbuf_size8_5 mux_right_ipin_5 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , - chany_bottom_in[18] , chany_top_in[18] } ) , - .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_right_ipin_5_undriven_sram_inv ) , - .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_111 ) ) ; -cby_2__1__mux_tree_tapbuf_size8_6 mux_right_ipin_6 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[11] , chany_top_in[11] , - chany_bottom_in[19] , chany_top_in[19] } ) , - .sram ( mux_tree_tapbuf_size8_3_sram ) , - .sram_inv ( mux_right_ipin_6_undriven_sram_inv ) , - .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_110 ) ) ; -cby_2__1__mux_tree_tapbuf_size8 mux_right_ipin_9 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , - chany_bottom_in[14] , chany_top_in[14] } ) , - .sram ( mux_tree_tapbuf_size8_4_sram ) , - .sram_inv ( mux_right_ipin_9_undriven_sram_inv ) , - .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_111 ) ) ; -cby_2__1__mux_tree_tapbuf_size8_1 mux_right_ipin_10 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , - chany_bottom_in[15] , chany_top_in[15] } ) , - .sram ( mux_tree_tapbuf_size8_5_sram ) , - .sram_inv ( mux_right_ipin_10_undriven_sram_inv ) , - .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_108 ) ) ; -cby_2__1__mux_tree_tapbuf_size8_2 mux_right_ipin_13 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , - chany_bottom_in[18] , chany_top_in[18] } ) , - .sram ( mux_tree_tapbuf_size8_6_sram ) , - .sram_inv ( mux_right_ipin_13_undriven_sram_inv ) , - .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_111 ) ) ; -cby_2__1__mux_tree_tapbuf_size8_3 mux_right_ipin_14 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[11] , chany_top_in[11] , - chany_bottom_in[19] , chany_top_in[19] } ) , - .sram ( mux_tree_tapbuf_size8_7_sram ) , - .sram_inv ( mux_right_ipin_14_undriven_sram_inv ) , - .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_110 ) ) ; -cby_2__1__mux_tree_tapbuf_size8_mem_0 mem_right_ipin_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ; -cby_2__1__mux_tree_tapbuf_size8_mem_4 mem_right_ipin_2 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ; -cby_2__1__mux_tree_tapbuf_size8_mem_5 mem_right_ipin_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ; -cby_2__1__mux_tree_tapbuf_size8_mem_6 mem_right_ipin_6 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_3_sram ) ) ; -cby_2__1__mux_tree_tapbuf_size8_mem mem_right_ipin_9 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_4_sram ) ) ; -cby_2__1__mux_tree_tapbuf_size8_mem_1 mem_right_ipin_10 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_5_sram ) ) ; -cby_2__1__mux_tree_tapbuf_size8_mem_2 mem_right_ipin_13 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_6_sram ) ) ; -cby_2__1__mux_tree_tapbuf_size8_mem_3 mem_right_ipin_14 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_7_sram ) ) ; -cby_2__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , - .io_outpad ( left_width_0_height_0__pin_0_ ) , - .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_8_ } ) , - .ccff_tail ( ccff_tail ) , .p_abuf0 ( ropt_net_114 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_bottom_in[0] ) , - .X ( ropt_net_115 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chany_bottom_in[1] ) , - .X ( chany_top_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_bottom_in[2] ) , - .X ( chany_top_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_bottom_in[3] ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chany_bottom_in[4] ) , - .X ( chany_top_out[4] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_108 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_bottom_in[6] ) , - .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_109 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chany_bottom_in[8] ) , - .X ( chany_top_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_691 ( .A ( ropt_net_114 ) , - .X ( left_width_0_height_0__pin_1_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_689 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_116 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__11 ( .A ( chany_bottom_in[11] ) , - .X ( aps_rename_3_ ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__12 ( .A ( chany_bottom_in[12] ) , - .X ( aps_rename_4_ ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chany_bottom_in[13] ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__14 ( .A ( chany_bottom_in[14] ) , - .X ( aps_rename_5_ ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__15 ( .A ( chany_bottom_in[15] ) , - .X ( aps_rename_6_ ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chany_bottom_in[16] ) , - .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_692 ( .A ( ropt_net_115 ) , - .X ( chany_top_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chany_bottom_in[18] ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_110 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chany_top_in[0] ) , - .X ( chany_bottom_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chany_top_in[1] ) , - .X ( chany_bottom_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chany_top_in[2] ) , - .X ( chany_bottom_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chany_top_in[3] ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_111 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chany_top_in[5] ) , - .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_690 ( - .A ( chany_bottom_in[17] ) , .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chany_top_in[7] ) , - .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_693 ( .A ( ropt_net_116 ) , - .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chany_top_in[9] ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_694 ( .A ( ropt_net_117 ) , - .X ( left_width_0_height_0__pin_1_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_32__31 ( .A ( chany_top_in[11] ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_36__35 ( .A ( chany_top_in[15] ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_37__36 ( .A ( chany_top_in[16] ) , - .X ( chany_bottom_out[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_39__38 ( .A ( chany_top_in[18] ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_41__40 ( .A ( aps_rename_8_ ) , - .X ( aps_rename_9_ ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_66 ( .A ( chany_bottom_in[5] ) , - .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_67 ( .A ( chany_bottom_in[7] ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_74 ( .A ( chany_top_in[8] ) , - .X ( chany_bottom_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_77 ( .A ( chany_top_in[17] ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_78 ( .A ( aps_rename_9_ ) , - .X ( ropt_net_117 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_82 ( .A ( chany_bottom_in[19] ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_83 ( .A ( chany_top_in[10] ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_85 ( .A ( aps_rename_3_ ) , - .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_86 ( .A ( aps_rename_4_ ) , - .X ( chany_top_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_87 ( .A ( aps_rename_5_ ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_88 ( .A ( aps_rename_6_ ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_90 ( .A ( chany_top_in[12] ) , - .X ( chany_bottom_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_94 ( .A ( chany_top_in[4] ) , - .X ( chany_bottom_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_95 ( .A ( chany_top_in[6] ) , - .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_96 ( .A ( chany_top_in[14] ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_97 ( .A ( chany_top_in[19] ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_98 ( .A ( chany_bottom_in[10] ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_99 ( .A ( chany_top_in[13] ) , - .X ( chany_bottom_out[13] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__55 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__54 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__53 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__52 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__51 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__50 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__49 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__48 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_1__1__const1 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -cby_1__1__const1 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; -endmodule - - -module cby_1__1__const1_14 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -cby_1__1__const1_14 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cby_1__1__const1_13 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -cby_1__1__const1_13 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; -endmodule - - -module cby_1__1__const1_12 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -cby_1__1__const1_12 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cby_1__1__const1_11 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -cby_1__1__const1_11 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cby_1__1__const1_10 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -cby_1__1__const1_10 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cby_1__1__const1_9 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -cby_1__1__const1_9 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cby_1__1__const1_8 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -cby_1__1__const1_8 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_8__47 ( .A ( mem_out[3] ) , - .X ( net_net_72 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_96 ( .A ( net_net_72 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__46 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__45 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__44 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__43 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__42 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__41 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__40 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_1__1__const1_7 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -cby_1__1__const1_7 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cby_1__1__const1_6 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -cby_1__1__const1_6 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cby_1__1__const1_5 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -cby_1__1__const1_5 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cby_1__1__const1_4 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -cby_1__1__const1_4 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cby_1__1__const1_3 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -cby_1__1__const1_3 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cby_1__1__const1_2 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -cby_1__1__const1_2 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cby_1__1__const1_1 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -cby_1__1__const1_1 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cby_1__1__const1_0 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -cby_1__1__const1_0 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cby_1__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , - chany_bottom_out , chany_top_out , left_grid_pin_16_ , left_grid_pin_17_ , - left_grid_pin_18_ , left_grid_pin_19_ , left_grid_pin_20_ , - left_grid_pin_21_ , left_grid_pin_22_ , left_grid_pin_23_ , - left_grid_pin_24_ , left_grid_pin_25_ , left_grid_pin_26_ , - left_grid_pin_27_ , left_grid_pin_28_ , left_grid_pin_29_ , - left_grid_pin_30_ , left_grid_pin_31_ , ccff_tail , prog_clk__FEEDTHRU_1 , - prog_clk__FEEDTHRU_2 ) ; -input [0:0] prog_clk ; -input [0:19] chany_bottom_in ; -input [0:19] chany_top_in ; -input [0:0] ccff_head ; -output [0:19] chany_bottom_out ; -output [0:19] chany_top_out ; -output [0:0] left_grid_pin_16_ ; -output [0:0] left_grid_pin_17_ ; -output [0:0] left_grid_pin_18_ ; -output [0:0] left_grid_pin_19_ ; -output [0:0] left_grid_pin_20_ ; -output [0:0] left_grid_pin_21_ ; -output [0:0] left_grid_pin_22_ ; -output [0:0] left_grid_pin_23_ ; -output [0:0] left_grid_pin_24_ ; -output [0:0] left_grid_pin_25_ ; -output [0:0] left_grid_pin_26_ ; -output [0:0] left_grid_pin_27_ ; -output [0:0] left_grid_pin_28_ ; -output [0:0] left_grid_pin_29_ ; -output [0:0] left_grid_pin_30_ ; -output [0:0] left_grid_pin_31_ ; -output [0:0] ccff_tail ; -output [0:0] prog_clk__FEEDTHRU_1 ; -output [0:0] prog_clk__FEEDTHRU_2 ; - -wire [0:3] mux_right_ipin_0_undriven_sram_inv ; -wire [0:3] mux_right_ipin_10_undriven_sram_inv ; -wire [0:3] mux_right_ipin_11_undriven_sram_inv ; -wire [0:3] mux_right_ipin_12_undriven_sram_inv ; -wire [0:3] mux_right_ipin_13_undriven_sram_inv ; -wire [0:3] mux_right_ipin_14_undriven_sram_inv ; -wire [0:3] mux_right_ipin_15_undriven_sram_inv ; -wire [0:3] mux_right_ipin_1_undriven_sram_inv ; -wire [0:3] mux_right_ipin_2_undriven_sram_inv ; -wire [0:3] mux_right_ipin_3_undriven_sram_inv ; -wire [0:3] mux_right_ipin_4_undriven_sram_inv ; -wire [0:3] mux_right_ipin_5_undriven_sram_inv ; -wire [0:3] mux_right_ipin_6_undriven_sram_inv ; -wire [0:3] mux_right_ipin_7_undriven_sram_inv ; -wire [0:3] mux_right_ipin_8_undriven_sram_inv ; -wire [0:3] mux_right_ipin_9_undriven_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:3] mux_tree_tapbuf_size10_2_sram ; -wire [0:3] mux_tree_tapbuf_size10_3_sram ; -wire [0:3] mux_tree_tapbuf_size10_4_sram ; -wire [0:3] mux_tree_tapbuf_size10_5_sram ; -wire [0:3] mux_tree_tapbuf_size10_6_sram ; -wire [0:3] mux_tree_tapbuf_size10_7_sram ; -wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:3] mux_tree_tapbuf_size8_2_sram ; -wire [0:3] mux_tree_tapbuf_size8_3_sram ; -wire [0:3] mux_tree_tapbuf_size8_4_sram ; -wire [0:3] mux_tree_tapbuf_size8_5_sram ; -wire [0:3] mux_tree_tapbuf_size8_6_sram ; -wire [0:3] mux_tree_tapbuf_size8_7_sram ; -wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ; - -cby_1__1__mux_tree_tapbuf_size10_0 mux_right_ipin_0 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , - chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , - chany_top_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_right_ipin_0_undriven_sram_inv ) , - .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_103 ) ) ; -cby_1__1__mux_tree_tapbuf_size10_4 mux_right_ipin_3 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , - chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[19] , - chany_top_in[19] } ) , - .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_right_ipin_3_undriven_sram_inv ) , - .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_105 ) ) ; -cby_1__1__mux_tree_tapbuf_size10_5 mux_right_ipin_4 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , - chany_bottom_in[8] , chany_top_in[8] , chany_bottom_in[14] , - chany_top_in[14] } ) , - .sram ( mux_tree_tapbuf_size10_2_sram ) , - .sram_inv ( mux_right_ipin_4_undriven_sram_inv ) , - .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_103 ) ) ; -cby_1__1__mux_tree_tapbuf_size10_6 mux_right_ipin_7 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , - chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[17] , - chany_top_in[17] } ) , - .sram ( mux_tree_tapbuf_size10_3_sram ) , - .sram_inv ( mux_right_ipin_7_undriven_sram_inv ) , - .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_104 ) ) ; -cby_1__1__mux_tree_tapbuf_size10 mux_right_ipin_8 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[8] , chany_top_in[8] , - chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[18] , - chany_top_in[18] } ) , - .sram ( mux_tree_tapbuf_size10_4_sram ) , - .sram_inv ( mux_right_ipin_8_undriven_sram_inv ) , - .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_106 ) ) ; -cby_1__1__mux_tree_tapbuf_size10_1 mux_right_ipin_11 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , - chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[15] , - chany_top_in[15] } ) , - .sram ( mux_tree_tapbuf_size10_5_sram ) , - .sram_inv ( mux_right_ipin_11_undriven_sram_inv ) , - .out ( left_grid_pin_27_ ) , .p0 ( optlc_net_106 ) ) ; -cby_1__1__mux_tree_tapbuf_size10_2 mux_right_ipin_12 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , - chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[16] , - chany_top_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_6_sram ) , - .sram_inv ( mux_right_ipin_12_undriven_sram_inv ) , - .out ( left_grid_pin_28_ ) , .p0 ( optlc_net_106 ) ) ; -cby_1__1__mux_tree_tapbuf_size10_3 mux_right_ipin_15 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , - chany_bottom_in[15] , chany_top_in[15] , chany_bottom_in[19] , - chany_top_in[19] } ) , - .sram ( mux_tree_tapbuf_size10_7_sram ) , - .sram_inv ( mux_right_ipin_15_undriven_sram_inv ) , - .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_104 ) ) ; -cby_1__1__mux_tree_tapbuf_size10_mem_0 mem_right_ipin_0 ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; -cby_1__1__mux_tree_tapbuf_size10_mem_4 mem_right_ipin_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ; -cby_1__1__mux_tree_tapbuf_size10_mem_5 mem_right_ipin_4 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ; -cby_1__1__mux_tree_tapbuf_size10_mem_6 mem_right_ipin_7 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ; -cby_1__1__mux_tree_tapbuf_size10_mem mem_right_ipin_8 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ; -cby_1__1__mux_tree_tapbuf_size10_mem_1 mem_right_ipin_11 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ; -cby_1__1__mux_tree_tapbuf_size10_mem_2 mem_right_ipin_12 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ; -cby_1__1__mux_tree_tapbuf_size10_mem_3 mem_right_ipin_15 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .ccff_tail ( { ropt_net_120 } ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ; -cby_1__1__mux_tree_tapbuf_size8_0 mux_right_ipin_1 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , - chany_bottom_in[13] , chany_top_in[13] } ) , - .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_right_ipin_1_undriven_sram_inv ) , - .out ( left_grid_pin_17_ ) , .p0 ( optlc_net_105 ) ) ; -cby_1__1__mux_tree_tapbuf_size8_4 mux_right_ipin_2 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , - chany_bottom_in[14] , chany_top_in[14] } ) , - .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_right_ipin_2_undriven_sram_inv ) , - .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_103 ) ) ; -cby_1__1__mux_tree_tapbuf_size8_5 mux_right_ipin_5 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , - chany_bottom_in[17] , chany_top_in[17] } ) , - .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_right_ipin_5_undriven_sram_inv ) , - .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_105 ) ) ; -cby_1__1__mux_tree_tapbuf_size8_6 mux_right_ipin_6 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , - chany_bottom_in[18] , chany_top_in[18] } ) , - .sram ( mux_tree_tapbuf_size8_3_sram ) , - .sram_inv ( mux_right_ipin_6_undriven_sram_inv ) , - .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_103 ) ) ; -cby_1__1__mux_tree_tapbuf_size8 mux_right_ipin_9 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , - chany_bottom_in[13] , chany_top_in[13] } ) , - .sram ( mux_tree_tapbuf_size8_4_sram ) , - .sram_inv ( mux_right_ipin_9_undriven_sram_inv ) , - .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_105 ) ) ; -cby_1__1__mux_tree_tapbuf_size8_1 mux_right_ipin_10 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , - chany_bottom_in[14] , chany_top_in[14] } ) , - .sram ( mux_tree_tapbuf_size8_5_sram ) , - .sram_inv ( mux_right_ipin_10_undriven_sram_inv ) , - .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_103 ) ) ; -cby_1__1__mux_tree_tapbuf_size8_2 mux_right_ipin_13 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , - chany_bottom_in[17] , chany_top_in[17] } ) , - .sram ( mux_tree_tapbuf_size8_6_sram ) , - .sram_inv ( mux_right_ipin_13_undriven_sram_inv ) , - .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_105 ) ) ; -cby_1__1__mux_tree_tapbuf_size8_3 mux_right_ipin_14 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , - chany_bottom_in[18] , chany_top_in[18] } ) , - .sram ( mux_tree_tapbuf_size8_7_sram ) , - .sram_inv ( mux_right_ipin_14_undriven_sram_inv ) , - .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_106 ) ) ; -cby_1__1__mux_tree_tapbuf_size8_mem_0 mem_right_ipin_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ; -cby_1__1__mux_tree_tapbuf_size8_mem_4 mem_right_ipin_2 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ; -cby_1__1__mux_tree_tapbuf_size8_mem_5 mem_right_ipin_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ; -cby_1__1__mux_tree_tapbuf_size8_mem_6 mem_right_ipin_6 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_3_sram ) ) ; -cby_1__1__mux_tree_tapbuf_size8_mem mem_right_ipin_9 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_4_sram ) ) ; -cby_1__1__mux_tree_tapbuf_size8_mem_1 mem_right_ipin_10 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_5_sram ) ) ; -cby_1__1__mux_tree_tapbuf_size8_mem_2 mem_right_ipin_13 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_6_sram ) ) ; -cby_1__1__mux_tree_tapbuf_size8_mem_3 mem_right_ipin_14 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_7_sram ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_bottom_in[0] ) , - .X ( chany_top_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chany_bottom_in[1] ) , - .X ( chany_top_out[1] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_103 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_bottom_in[3] ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_104 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_757 ( .A ( ropt_net_125 ) , - .X ( chany_bottom_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_bottom_in[6] ) , - .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_758 ( .A ( ropt_net_126 ) , - .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chany_bottom_in[8] ) , - .X ( ropt_net_118 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chany_bottom_in[9] ) , - .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chany_bottom_in[10] ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_105 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chany_bottom_in[12] ) , - .X ( chany_top_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chany_bottom_in[13] ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_106 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_127 ) , - .X ( chany_bottom_out[4] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__16 ( .A ( chany_bottom_in[16] ) , - .X ( ropt_net_119 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_760 ( .A ( ropt_net_128 ) , - .X ( chany_bottom_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chany_bottom_in[18] ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_20__19 ( .A ( chany_bottom_in[19] ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chany_top_in[0] ) , - .X ( chany_bottom_out[0] ) ) ; -sky130_fd_sc_hd__buf_2 \prog_clk[0]_bip372 ( .A ( prog_clk[0] ) , - .X ( ctsbuf_net_1107 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( chany_top_in[11] ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chany_top_in[3] ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__24 ( .A ( chany_top_in[4] ) , - .X ( ropt_net_124 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_116 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chany_top_in[6] ) , - .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chany_top_in[7] ) , - .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_29__28 ( .A ( chany_top_in[8] ) , - .X ( chany_bottom_out[8] ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_325697 ( .A ( ctsbuf_net_1107 ) , - .X ( prog_clk__FEEDTHRU_2[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_31__30 ( .A ( chany_top_in[10] ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( ropt_net_129 ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_326698 ( .A ( ctsbuf_net_1107 ) , - .X ( prog_clk__FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_110 ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_728 ( - .A ( chany_bottom_in[17] ) , .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_729 ( .A ( chany_bottom_in[4] ) , - .X ( chany_top_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_730 ( .A ( chany_bottom_in[5] ) , - .X ( ropt_net_126 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_130 ) , - .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_39__38 ( .A ( chany_top_in[18] ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( .A ( chany_top_in[17] ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_59 ( .A ( chany_bottom_in[2] ) , - .X ( chany_top_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_766 ( .A ( ropt_net_131 ) , - .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_768 ( .A ( ropt_net_132 ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_63 ( .A ( chany_bottom_in[14] ) , - .X ( ropt_net_117 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( - .A ( chany_bottom_in[11] ) , .X ( ropt_net_130 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_116 ) , - .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_68 ( .A ( chany_top_in[13] ) , - .X ( BUF_net_68 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( .A ( chany_top_in[15] ) , - .X ( BUF_net_69 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_70 ( .A ( chany_top_in[16] ) , - .X ( chany_bottom_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_117 ) , - .X ( ropt_net_129 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_75 ( .A ( chany_bottom_in[7] ) , - .X ( ropt_net_110 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_76 ( .A ( chany_bottom_in[15] ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( ropt_net_118 ) , - .X ( chany_top_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_119 ) , - .X ( ropt_net_131 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_120 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_121 ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( chany_top_in[2] ) , - .X ( chany_bottom_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_87 ( .A ( chany_top_in[9] ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_88 ( .A ( chany_top_in[14] ) , - .X ( ropt_net_121 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_93 ( .A ( BUF_net_68 ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_94 ( .A ( BUF_net_69 ) , - .X ( ropt_net_132 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_95 ( .A ( chany_top_in[19] ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( chany_top_in[12] ) , - .X ( ropt_net_125 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( chany_top_in[1] ) , - .X ( ropt_net_128 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_124 ) , - .X ( ropt_net_127 ) ) ; -endmodule - - -module cby_0__1__direct_interc ( in , out ) ; -input [0:0] in ; -output [0:0] out ; - -assign out[0] = in[0] ; -endmodule - - -module cby_0__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( prog_clk , - ccff_head , ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:0] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__44 ( .A ( mem_out[0] ) , - .X ( net_net_86 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_163 ( .A ( net_net_86 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_0__1__EMBEDDED_IO ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , - FPGA_OUT , FPGA_DIR , p_abuf0 , p_abuf1 ) ; -input SOC_IN ; -output SOC_OUT ; -output SOC_DIR ; -output FPGA_IN ; -input FPGA_OUT ; -input FPGA_DIR ; -output p_abuf0 ; -output p_abuf1 ; - -wire aps_rename_2_ ; - -assign SOC_OUT = FPGA_OUT ; - -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__42 ( .A ( SOC_IN ) , .X ( p_abuf1 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__43 ( .A ( FPGA_DIR ) , - .X ( aps_rename_2_ ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_45 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_46 ( .A ( p_abuf1 ) , - .X ( BUF_net_46 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_128 ( .A ( BUF_net_46 ) , - .X ( p_abuf0 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_162 ( .A ( aps_rename_2_ ) , - .X ( SOC_DIR ) ) ; -endmodule - - -module cby_0__1__logical_tile_io_mode_physical__iopad ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , p_abuf0 , p_abuf1 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] iopad_outpad ; -input [0:0] ccff_head ; -output [0:0] iopad_inpad ; -output [0:0] ccff_tail ; -output p_abuf0 ; -output p_abuf1 ; - -wire [0:0] EMBEDDED_IO_0_en ; - -cby_0__1__EMBEDDED_IO EMBEDDED_IO_0_ ( - .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , - .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , - .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , - .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , - .p_abuf1 ( p_abuf1 ) ) ; -cby_0__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) ) ; -endmodule - - -module cby_0__1__logical_tile_io_mode_io_ ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , - ccff_tail , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] io_outpad ; -input [0:0] ccff_head ; -output [0:0] io_inpad ; -output [0:0] ccff_tail ; -output p_abuf0 ; - -cby_0__1__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , - .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , - .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; -cby_0__1__direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( { p_abuf1 } ) ) ; -cby_0__1__direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( io_outpad ) ) ; -endmodule - - -module cby_0__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__41 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_0__1__const1 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cby_0__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -cby_0__1__const1 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cby_0__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , - chany_bottom_out , chany_top_out , left_grid_pin_0_ , ccff_tail , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , right_width_0_height_0__pin_0_ , - right_width_0_height_0__pin_1_upper , - right_width_0_height_0__pin_1_lower ) ; -input [0:0] prog_clk ; -input [0:19] chany_bottom_in ; -input [0:19] chany_top_in ; -input [0:0] ccff_head ; -output [0:19] chany_bottom_out ; -output [0:19] chany_top_out ; -output [0:0] left_grid_pin_0_ ; -output [0:0] ccff_tail ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] right_width_0_height_0__pin_0_ ; -output [0:0] right_width_0_height_0__pin_1_upper ; -output [0:0] right_width_0_height_0__pin_1_lower ; - -wire ropt_net_168 ; -wire [0:3] mux_right_ipin_0_undriven_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_0_sram ; - -cby_0__1__mux_tree_tapbuf_size10 mux_right_ipin_0 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , - chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , - chany_top_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_right_ipin_0_undriven_sram_inv ) , - .out ( left_grid_pin_0_ ) , .p0 ( optlc_net_164 ) ) ; -cby_0__1__mux_tree_tapbuf_size10_mem mem_right_ipin_0 ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( { ccff_tail_mid } ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; -cby_0__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_178 } ) , - .io_outpad ( right_width_0_height_0__pin_0_ ) , - .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_8_ } ) , - .ccff_tail ( { ropt_net_170 } ) , - .p_abuf0 ( ropt_net_168 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_165 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_164 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_165 ) , - .X ( ropt_net_210 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_745 ( - .A ( chany_bottom_in[10] ) , .X ( ropt_net_233 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_167 ) , - .X ( right_width_0_height_0__pin_1_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( ropt_net_168 ) , - .X ( right_width_0_height_0__pin_1_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_169 ) , - .X ( ropt_net_211 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_749 ( .A ( ropt_net_170 ) , - .X ( ropt_net_223 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_171 ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_751 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_226 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_786 ( .A ( ropt_net_205 ) , - .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_206 ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_752 ( .A ( chany_bottom_in[1] ) , - .X ( ropt_net_235 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_753 ( - .A ( chany_bottom_in[14] ) , .X ( ropt_net_231 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_754 ( .A ( chany_bottom_in[7] ) , - .X ( ropt_net_230 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_755 ( - .A ( chany_bottom_in[16] ) , .X ( ropt_net_228 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_756 ( .A ( chany_top_in[13] ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_757 ( .A ( ropt_net_178 ) , - .X ( ropt_net_224 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_758 ( - .A ( chany_bottom_in[18] ) , .X ( ropt_net_234 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_759 ( .A ( chany_top_in[18] ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_760 ( .A ( chany_top_in[9] ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chany_top_in[0] ) , - .X ( chany_bottom_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( .A ( chany_bottom_in[5] ) , - .X ( ropt_net_227 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( chany_top_in[7] ) , - .X ( ropt_net_225 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_184 ) , - .X ( ropt_net_212 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_764 ( .A ( chany_top_in[6] ) , - .X ( ropt_net_229 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_186 ) , - .X ( ropt_net_205 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_187 ) , - .X ( ropt_net_214 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_232 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_207 ) , - .X ( chany_bottom_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_189 ) , - .X ( ropt_net_215 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_31__30 ( .A ( chany_top_in[10] ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( ropt_net_208 ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( ropt_net_209 ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_190 ) , - .X ( ropt_net_209 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_191 ) , - .X ( ropt_net_220 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_192 ) , - .X ( ropt_net_213 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_37__36 ( .A ( chany_top_in[16] ) , - .X ( ropt_net_202 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_193 ) , - .X ( ropt_net_208 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_194 ) , - .X ( ropt_net_217 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_195 ) , - .X ( ropt_net_206 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_196 ) , - .X ( ropt_net_218 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_47 ( .A ( chany_bottom_in[0] ) , - .X ( ropt_net_189 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( ropt_net_210 ) , - .X ( chany_bottom_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_197 ) , - .X ( ropt_net_216 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_198 ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_51 ( .A ( chany_bottom_in[4] ) , - .X ( ropt_net_191 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( ropt_net_211 ) , - .X ( chany_bottom_out[12] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_53 ( .A ( chany_bottom_in[6] ) , - .X ( ropt_net_192 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_212 ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( ropt_net_213 ) , - .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_795 ( .A ( ropt_net_214 ) , - .X ( chany_top_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( ropt_net_215 ) , - .X ( chany_top_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_58 ( .A ( chany_bottom_in[11] ) , - .X ( ropt_net_186 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_59 ( .A ( chany_bottom_in[12] ) , - .X ( ropt_net_187 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_60 ( .A ( chany_bottom_in[13] ) , - .X ( ropt_net_196 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_216 ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_62 ( .A ( chany_bottom_in[15] ) , - .X ( ropt_net_184 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_800 ( .A ( ropt_net_217 ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_199 ) , - .X ( ropt_net_219 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_218 ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_200 ) , - .X ( chany_bottom_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_201 ) , - .X ( ropt_net_222 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_68 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_203 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_69 ( .A ( chany_top_in[3] ) , - .X ( ropt_net_201 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_802 ( .A ( ropt_net_219 ) , - .X ( chany_top_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_202 ) , - .X ( chany_bottom_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_803 ( .A ( ropt_net_220 ) , - .X ( chany_top_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_804 ( .A ( ropt_net_221 ) , - .X ( chany_bottom_out[8] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_74 ( .A ( chany_top_in[8] ) , - .X ( BUF_net_74 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_203 ) , - .X ( ropt_net_207 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( ropt_net_222 ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_223 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_224 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_79 ( .A ( chany_top_in[14] ) , - .X ( ropt_net_190 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_80 ( .A ( chany_top_in[15] ) , - .X ( ropt_net_194 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_81 ( .A ( chany_top_in[17] ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_817 ( .A ( ropt_net_225 ) , - .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_226 ) , - .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_227 ) , - .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_228 ) , - .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_229 ) , - .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_230 ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_231 ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( ropt_net_232 ) , - .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_826 ( .A ( ropt_net_233 ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_827 ( .A ( ropt_net_234 ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_235 ) , - .X ( chany_top_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_96 ( .A ( chany_bottom_in[8] ) , - .X ( BUF_net_96 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_108 ( .A ( chany_top_in[1] ) , - .X ( ropt_net_200 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_121 ( .A ( chany_top_in[19] ) , - .X ( ropt_net_198 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_122 ( .A ( aps_rename_8_ ) , - .X ( ropt_net_167 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_125 ( .A ( BUF_net_74 ) , - .X ( ropt_net_221 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_126 ( .A ( chany_top_in[11] ) , - .X ( ropt_net_171 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_127 ( .A ( chany_top_in[12] ) , - .X ( ropt_net_169 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_131 ( .A ( chany_bottom_in[2] ) , - .X ( ropt_net_199 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_132 ( .A ( chany_bottom_in[3] ) , - .X ( ropt_net_195 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_137 ( .A ( BUF_net_96 ) , - .X ( chany_top_out[8] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_144 ( .A ( chany_bottom_in[17] ) , - .X ( ropt_net_193 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_146 ( .A ( chany_bottom_in[19] ) , - .X ( ropt_net_197 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_150 ( .A ( chany_top_in[4] ) , - .X ( ropt_net_165 ) ) ; -endmodule - - -module cbx_1__2__direct_interc ( in , out ) ; -input [0:0] in ; -output [0:0] out ; - -assign out[0] = in[0] ; -endmodule - - -module cbx_1__2__direct_interc_0 ( in , out ) ; -input [0:0] in ; -output [0:0] out ; -endmodule - - -module cbx_1__2__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( prog_clk , - ccff_head , ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:0] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_20__61 ( .A ( mem_out[0] ) , - .X ( net_net_76 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_76 ( .A ( net_net_76 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__2__EMBEDDED_IO ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , - FPGA_OUT , FPGA_DIR , p_abuf0 ) ; -input SOC_IN ; -output SOC_OUT ; -output SOC_DIR ; -output FPGA_IN ; -input FPGA_OUT ; -input FPGA_DIR ; -output p_abuf0 ; - -wire aps_rename_1_ ; - -assign SOC_OUT = FPGA_OUT ; - -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__59 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__60 ( .A ( FPGA_DIR ) , - .X ( aps_rename_1_ ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_75 ( .A ( aps_rename_1_ ) , - .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_63 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; -endmodule - - -module cbx_1__2__logical_tile_io_mode_physical__iopad ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] iopad_outpad ; -input [0:0] ccff_head ; -output [0:0] iopad_inpad ; -output [0:0] ccff_tail ; -output p_abuf0 ; - -wire [0:0] EMBEDDED_IO_0_en ; - -cbx_1__2__EMBEDDED_IO EMBEDDED_IO_0_ ( - .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , - .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , - .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , - .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__2__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) ) ; -endmodule - - -module cbx_1__2__logical_tile_io_mode_io_ ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , - ccff_tail , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] io_outpad ; -input [0:0] ccff_head ; -output [0:0] io_inpad ; -output [0:0] ccff_tail ; -output p_abuf0 ; - -cbx_1__2__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , - .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , - .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__2__direct_interc_0 direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; -cbx_1__2__direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( io_outpad ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__58 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__57 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__56 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__55 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__54 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__53 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__52 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__51 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__2__const1 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -cbx_1__2__const1 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cbx_1__2__const1_15 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -cbx_1__2__const1_15 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cbx_1__2__const1_14 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -cbx_1__2__const1_14 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cbx_1__2__const1_13 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -cbx_1__2__const1_13 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cbx_1__2__const1_12 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -cbx_1__2__const1_12 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cbx_1__2__const1_11 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -cbx_1__2__const1_11 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cbx_1__2__const1_10 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -cbx_1__2__const1_10 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cbx_1__2__const1_9 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -cbx_1__2__const1_9 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__50 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__49 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__48 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__47 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__46 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__45 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__44 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__43 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__42 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__2__const1_8 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -cbx_1__2__const1_8 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cbx_1__2__const1_7 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -cbx_1__2__const1_7 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cbx_1__2__const1_6 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -cbx_1__2__const1_6 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cbx_1__2__const1_5 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -cbx_1__2__const1_5 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cbx_1__2__const1_4 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -cbx_1__2__const1_4 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cbx_1__2__const1_3 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -cbx_1__2__const1_3 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cbx_1__2__const1_2 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -cbx_1__2__const1_2 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_64 ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module cbx_1__2__const1_1 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -cbx_1__2__const1_1 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cbx_1__2__const1_0 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -cbx_1__2__const1_0 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cbx_1__2_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , - chanx_left_out , chanx_right_out , top_grid_pin_0_ , bottom_grid_pin_0_ , - bottom_grid_pin_1_ , bottom_grid_pin_2_ , bottom_grid_pin_3_ , - bottom_grid_pin_4_ , bottom_grid_pin_5_ , bottom_grid_pin_6_ , - bottom_grid_pin_7_ , bottom_grid_pin_8_ , bottom_grid_pin_9_ , - bottom_grid_pin_10_ , bottom_grid_pin_11_ , bottom_grid_pin_12_ , - bottom_grid_pin_13_ , bottom_grid_pin_14_ , bottom_grid_pin_15_ , - ccff_tail , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , bottom_width_0_height_0__pin_0_ , - bottom_width_0_height_0__pin_1_upper , - bottom_width_0_height_0__pin_1_lower , SC_IN_TOP , SC_IN_BOT , - SC_OUT_TOP , SC_OUT_BOT , prog_clk__FEEDTHRU_1 , prog_clk__FEEDTHRU_2 ) ; -input [0:0] prog_clk ; -input [0:19] chanx_left_in ; -input [0:19] chanx_right_in ; -input [0:0] ccff_head ; -output [0:19] chanx_left_out ; -output [0:19] chanx_right_out ; -output [0:0] top_grid_pin_0_ ; -output [0:0] bottom_grid_pin_0_ ; -output [0:0] bottom_grid_pin_1_ ; -output [0:0] bottom_grid_pin_2_ ; -output [0:0] bottom_grid_pin_3_ ; -output [0:0] bottom_grid_pin_4_ ; -output [0:0] bottom_grid_pin_5_ ; -output [0:0] bottom_grid_pin_6_ ; -output [0:0] bottom_grid_pin_7_ ; -output [0:0] bottom_grid_pin_8_ ; -output [0:0] bottom_grid_pin_9_ ; -output [0:0] bottom_grid_pin_10_ ; -output [0:0] bottom_grid_pin_11_ ; -output [0:0] bottom_grid_pin_12_ ; -output [0:0] bottom_grid_pin_13_ ; -output [0:0] bottom_grid_pin_14_ ; -output [0:0] bottom_grid_pin_15_ ; -output [0:0] ccff_tail ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] bottom_width_0_height_0__pin_0_ ; -output [0:0] bottom_width_0_height_0__pin_1_upper ; -output [0:0] bottom_width_0_height_0__pin_1_lower ; -input SC_IN_TOP ; -input SC_IN_BOT ; -output SC_OUT_TOP ; -output SC_OUT_BOT ; -output [0:0] prog_clk__FEEDTHRU_1 ; -output [0:0] prog_clk__FEEDTHRU_2 ; - -wire ropt_net_112 ; -wire [0:3] mux_bottom_ipin_0_undriven_sram_inv ; -wire [0:3] mux_top_ipin_0_undriven_sram_inv ; -wire [0:3] mux_top_ipin_10_undriven_sram_inv ; -wire [0:3] mux_top_ipin_11_undriven_sram_inv ; -wire [0:3] mux_top_ipin_12_undriven_sram_inv ; -wire [0:3] mux_top_ipin_13_undriven_sram_inv ; -wire [0:3] mux_top_ipin_14_undriven_sram_inv ; -wire [0:3] mux_top_ipin_15_undriven_sram_inv ; -wire [0:3] mux_top_ipin_1_undriven_sram_inv ; -wire [0:3] mux_top_ipin_2_undriven_sram_inv ; -wire [0:3] mux_top_ipin_3_undriven_sram_inv ; -wire [0:3] mux_top_ipin_4_undriven_sram_inv ; -wire [0:3] mux_top_ipin_5_undriven_sram_inv ; -wire [0:3] mux_top_ipin_6_undriven_sram_inv ; -wire [0:3] mux_top_ipin_7_undriven_sram_inv ; -wire [0:3] mux_top_ipin_8_undriven_sram_inv ; -wire [0:3] mux_top_ipin_9_undriven_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:3] mux_tree_tapbuf_size10_2_sram ; -wire [0:3] mux_tree_tapbuf_size10_3_sram ; -wire [0:3] mux_tree_tapbuf_size10_4_sram ; -wire [0:3] mux_tree_tapbuf_size10_5_sram ; -wire [0:3] mux_tree_tapbuf_size10_6_sram ; -wire [0:3] mux_tree_tapbuf_size10_7_sram ; -wire [0:3] mux_tree_tapbuf_size10_8_sram ; -wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:3] mux_tree_tapbuf_size8_2_sram ; -wire [0:3] mux_tree_tapbuf_size8_3_sram ; -wire [0:3] mux_tree_tapbuf_size8_4_sram ; -wire [0:3] mux_tree_tapbuf_size8_5_sram ; -wire [0:3] mux_tree_tapbuf_size8_6_sram ; -wire [0:3] mux_tree_tapbuf_size8_7_sram ; -wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ; - -assign SC_IN_TOP = SC_IN_BOT ; - -cbx_1__2__mux_tree_tapbuf_size10_0 mux_bottom_ipin_0 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , - chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , - chanx_right_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_bottom_ipin_0_undriven_sram_inv ) , - .out ( top_grid_pin_0_ ) , .p0 ( optlc_net_108 ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_1 mux_top_ipin_0 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , - chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , - chanx_right_in[17] } ) , - .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_top_ipin_0_undriven_sram_inv ) , - .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_108 ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_5 mux_top_ipin_3 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , - chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[14] , - chanx_right_in[14] } ) , - .sram ( mux_tree_tapbuf_size10_2_sram ) , - .sram_inv ( mux_top_ipin_3_undriven_sram_inv ) , - .out ( { ropt_net_117 } ) , - .p0 ( optlc_net_107 ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_6 mux_top_ipin_4 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , - chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[15] , - chanx_right_in[15] } ) , - .sram ( mux_tree_tapbuf_size10_3_sram ) , - .sram_inv ( mux_top_ipin_4_undriven_sram_inv ) , - .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_108 ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_7 mux_top_ipin_7 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[8] , chanx_right_in[8] , - chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , - chanx_right_in[18] } ) , - .sram ( mux_tree_tapbuf_size10_4_sram ) , - .sram_inv ( mux_top_ipin_7_undriven_sram_inv ) , - .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_107 ) ) ; -cbx_1__2__mux_tree_tapbuf_size10 mux_top_ipin_8 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , - chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , - chanx_right_in[19] } ) , - .sram ( mux_tree_tapbuf_size10_5_sram ) , - .sram_inv ( mux_top_ipin_8_undriven_sram_inv ) , - .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_106 ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_2 mux_top_ipin_11 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , - chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[16] , - chanx_right_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_6_sram ) , - .sram_inv ( mux_top_ipin_11_undriven_sram_inv ) , - .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_106 ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_3 mux_top_ipin_12 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , - chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[17] , - chanx_right_in[17] } ) , - .sram ( mux_tree_tapbuf_size10_7_sram ) , - .sram_inv ( mux_top_ipin_12_undriven_sram_inv ) , - .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_108 ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_4 mux_top_ipin_15 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , - chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , - chanx_right_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_8_sram ) , - .sram_inv ( mux_top_ipin_15_undriven_sram_inv ) , - .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_108 ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_mem_0 mem_bottom_ipin_0 ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_0 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_mem_5 mem_top_ipin_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_mem_6 mem_top_ipin_4 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_mem_7 mem_top_ipin_7 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_mem mem_top_ipin_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_11 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_12 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_15 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , - .mem_out ( mux_tree_tapbuf_size10_8_sram ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_0 mux_top_ipin_1 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , - chanx_left_in[14] , chanx_right_in[14] } ) , - .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_top_ipin_1_undriven_sram_inv ) , - .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_109 ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_4 mux_top_ipin_2 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , - chanx_left_in[15] , chanx_right_in[15] } ) , - .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_top_ipin_2_undriven_sram_inv ) , - .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_106 ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_5 mux_top_ipin_5 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , - chanx_left_in[18] , chanx_right_in[18] } ) , - .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_top_ipin_5_undriven_sram_inv ) , - .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_107 ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_6 mux_top_ipin_6 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , - chanx_left_in[19] , chanx_right_in[19] } ) , - .sram ( mux_tree_tapbuf_size8_3_sram ) , - .sram_inv ( mux_top_ipin_6_undriven_sram_inv ) , - .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_107 ) ) ; -cbx_1__2__mux_tree_tapbuf_size8 mux_top_ipin_9 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , - chanx_left_in[14] , chanx_right_in[14] } ) , - .sram ( mux_tree_tapbuf_size8_4_sram ) , - .sram_inv ( mux_top_ipin_9_undriven_sram_inv ) , - .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_109 ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_1 mux_top_ipin_10 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , - chanx_left_in[15] , chanx_right_in[15] } ) , - .sram ( mux_tree_tapbuf_size8_5_sram ) , - .sram_inv ( mux_top_ipin_10_undriven_sram_inv ) , - .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_106 ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_2 mux_top_ipin_13 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , - chanx_left_in[18] , chanx_right_in[18] } ) , - .sram ( mux_tree_tapbuf_size8_6_sram ) , - .sram_inv ( mux_top_ipin_13_undriven_sram_inv ) , - .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_107 ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_3 mux_top_ipin_14 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , - chanx_left_in[19] , chanx_right_in[19] } ) , - .sram ( mux_tree_tapbuf_size8_7_sram ) , - .sram_inv ( mux_top_ipin_14_undriven_sram_inv ) , - .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_106 ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_mem_0 mem_top_ipin_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_mem_4 mem_top_ipin_2 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_mem_5 mem_top_ipin_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_mem_6 mem_top_ipin_6 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_3_sram ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_mem mem_top_ipin_9 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_4_sram ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_mem_1 mem_top_ipin_10 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_5_sram ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_mem_2 mem_top_ipin_13 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_6_sram ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_mem_3 mem_top_ipin_14 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_7_sram ) ) ; -cbx_1__2__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_114 } ) , - .io_outpad ( bottom_width_0_height_0__pin_0_ ) , - .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_3_ } ) , - .ccff_tail ( ccff_tail ) , .p_abuf0 ( ropt_net_112 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_106 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chanx_left_in[1] ) , - .X ( chanx_right_out[1] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_107 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chanx_left_in[4] ) , - .X ( chanx_right_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chanx_left_in[5] ) , - .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chanx_left_in[6] ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chanx_left_in[7] ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_108 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chanx_left_in[9] ) , - .X ( ropt_net_130 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_109 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_12__11 ( .A ( chanx_left_in[11] ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chanx_left_in[12] ) , - .X ( chanx_right_out[12] ) ) ; -sky130_fd_sc_hd__buf_2 \prog_clk[0]_bip377 ( .A ( prog_clk[0] ) , - .X ( ctsbuf_net_2111 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chanx_left_in[14] ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_112 ) , - .X ( ropt_net_137 ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_330707 ( .A ( ctsbuf_net_2111 ) , - .X ( prog_clk__FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chanx_left_in[17] ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_132 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_20__19 ( .A ( chanx_left_in[19] ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_right_in[0] ) , - .X ( ropt_net_131 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , - .X ( ropt_net_134 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chanx_right_in[2] ) , - .X ( ropt_net_147 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chanx_right_in[3] ) , - .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__24 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_129 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chanx_right_in[5] ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_331708 ( .A ( ctsbuf_net_2111 ) , - .X ( prog_clk__FEEDTHRU_2[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chanx_right_in[7] ) , - .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( .A ( chanx_right_in[6] ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_114 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( ropt_net_115 ) , - .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_138 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_33__32 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_127 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_117 ) , - .X ( ropt_net_141 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_137 ) , - .X ( bottom_width_0_height_0__pin_1_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_741 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_146 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_37__36 ( .A ( chanx_right_in[16] ) , - .X ( chanx_left_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_119 ) , - .X ( chanx_right_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_39__38 ( .A ( chanx_right_in[18] ) , - .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_40__39 ( .A ( chanx_right_in[19] ) , - .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_41__40 ( .A ( aps_rename_3_ ) , - .X ( ropt_net_121 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_42__41 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_115 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_66 ( .A ( chanx_left_in[0] ) , - .X ( chanx_right_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_744 ( .A ( chanx_right_in[14] ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_138 ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( ropt_net_139 ) , - .X ( chanx_left_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_121 ) , - .X ( ropt_net_142 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_780 ( .A ( ropt_net_140 ) , - .X ( chanx_left_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_785 ( .A ( ropt_net_141 ) , - .X ( bottom_grid_pin_3_[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_786 ( .A ( ropt_net_142 ) , - .X ( bottom_width_0_height_0__pin_1_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_143 ) , - .X ( chanx_left_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_139 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_79 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_119 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_750 ( .A ( chanx_left_in[13] ) , - .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_124 ) , - .X ( ropt_net_145 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_752 ( .A ( chanx_left_in[16] ) , - .X ( chanx_right_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( ropt_net_144 ) , - .X ( chanx_right_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_753 ( .A ( chanx_left_in[10] ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_88 ( .A ( chanx_left_in[15] ) , - .X ( ropt_net_124 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( ropt_net_145 ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_90 ( .A ( chanx_right_in[9] ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_146 ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_92 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_133 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_93 ( .A ( chanx_right_in[13] ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_94 ( .A ( chanx_right_in[15] ) , - .X ( ropt_net_135 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_96 ( .A ( chanx_left_in[2] ) , - .X ( ropt_net_128 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_754 ( .A ( ropt_net_127 ) , - .X ( chanx_left_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_147 ) , - .X ( chanx_left_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_128 ) , - .X ( ropt_net_144 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_129 ) , - .X ( ropt_net_143 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_130 ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_131 ) , - .X ( chanx_left_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_132 ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_133 ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_134 ) , - .X ( ropt_net_140 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_135 ) , - .X ( chanx_left_out[15] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__56 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__55 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__54 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__53 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__52 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__51 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__50 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__49 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__1__const1 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -cbx_1__1__const1 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cbx_1__1__const1_14 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -cbx_1__1__const1_14 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cbx_1__1__const1_13 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -cbx_1__1__const1_13 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cbx_1__1__const1_12 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -cbx_1__1__const1_12 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cbx_1__1__const1_11 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -cbx_1__1__const1_11 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cbx_1__1__const1_10 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -cbx_1__1__const1_10 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cbx_1__1__const1_9 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -cbx_1__1__const1_9 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cbx_1__1__const1_8 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -cbx_1__1__const1_8 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__48 ( .A ( mem_out[3] ) , - .X ( net_net_72 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_90 ( .A ( net_net_72 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__47 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__46 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__45 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__44 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__43 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__42 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__41 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__1__const1_7 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -cbx_1__1__const1_7 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cbx_1__1__const1_6 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -cbx_1__1__const1_6 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cbx_1__1__const1_5 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -cbx_1__1__const1_5 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cbx_1__1__const1_4 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -cbx_1__1__const1_4 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cbx_1__1__const1_3 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -cbx_1__1__const1_3 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cbx_1__1__const1_2 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -cbx_1__1__const1_2 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cbx_1__1__const1_1 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -cbx_1__1__const1_1 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cbx_1__1__const1_0 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -cbx_1__1__const1_0 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cbx_1__1_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , - chanx_left_out , chanx_right_out , bottom_grid_pin_0_ , - bottom_grid_pin_1_ , bottom_grid_pin_2_ , bottom_grid_pin_3_ , - bottom_grid_pin_4_ , bottom_grid_pin_5_ , bottom_grid_pin_6_ , - bottom_grid_pin_7_ , bottom_grid_pin_8_ , bottom_grid_pin_9_ , - bottom_grid_pin_10_ , bottom_grid_pin_11_ , bottom_grid_pin_12_ , - bottom_grid_pin_13_ , bottom_grid_pin_14_ , bottom_grid_pin_15_ , - ccff_tail , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , SC_OUT_BOT , - prog_clk__FEEDTHRU_1 ) ; -input [0:0] prog_clk ; -input [0:19] chanx_left_in ; -input [0:19] chanx_right_in ; -input [0:0] ccff_head ; -output [0:19] chanx_left_out ; -output [0:19] chanx_right_out ; -output [0:0] bottom_grid_pin_0_ ; -output [0:0] bottom_grid_pin_1_ ; -output [0:0] bottom_grid_pin_2_ ; -output [0:0] bottom_grid_pin_3_ ; -output [0:0] bottom_grid_pin_4_ ; -output [0:0] bottom_grid_pin_5_ ; -output [0:0] bottom_grid_pin_6_ ; -output [0:0] bottom_grid_pin_7_ ; -output [0:0] bottom_grid_pin_8_ ; -output [0:0] bottom_grid_pin_9_ ; -output [0:0] bottom_grid_pin_10_ ; -output [0:0] bottom_grid_pin_11_ ; -output [0:0] bottom_grid_pin_12_ ; -output [0:0] bottom_grid_pin_13_ ; -output [0:0] bottom_grid_pin_14_ ; -output [0:0] bottom_grid_pin_15_ ; -output [0:0] ccff_tail ; -input SC_IN_TOP ; -input SC_IN_BOT ; -output SC_OUT_TOP ; -output SC_OUT_BOT ; -output [0:0] prog_clk__FEEDTHRU_1 ; - -wire [0:3] mux_top_ipin_0_undriven_sram_inv ; -wire [0:3] mux_top_ipin_10_undriven_sram_inv ; -wire [0:3] mux_top_ipin_11_undriven_sram_inv ; -wire [0:3] mux_top_ipin_12_undriven_sram_inv ; -wire [0:3] mux_top_ipin_13_undriven_sram_inv ; -wire [0:3] mux_top_ipin_14_undriven_sram_inv ; -wire [0:3] mux_top_ipin_15_undriven_sram_inv ; -wire [0:3] mux_top_ipin_1_undriven_sram_inv ; -wire [0:3] mux_top_ipin_2_undriven_sram_inv ; -wire [0:3] mux_top_ipin_3_undriven_sram_inv ; -wire [0:3] mux_top_ipin_4_undriven_sram_inv ; -wire [0:3] mux_top_ipin_5_undriven_sram_inv ; -wire [0:3] mux_top_ipin_6_undriven_sram_inv ; -wire [0:3] mux_top_ipin_7_undriven_sram_inv ; -wire [0:3] mux_top_ipin_8_undriven_sram_inv ; -wire [0:3] mux_top_ipin_9_undriven_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:3] mux_tree_tapbuf_size10_2_sram ; -wire [0:3] mux_tree_tapbuf_size10_3_sram ; -wire [0:3] mux_tree_tapbuf_size10_4_sram ; -wire [0:3] mux_tree_tapbuf_size10_5_sram ; -wire [0:3] mux_tree_tapbuf_size10_6_sram ; -wire [0:3] mux_tree_tapbuf_size10_7_sram ; -wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:3] mux_tree_tapbuf_size8_2_sram ; -wire [0:3] mux_tree_tapbuf_size8_3_sram ; -wire [0:3] mux_tree_tapbuf_size8_4_sram ; -wire [0:3] mux_tree_tapbuf_size8_5_sram ; -wire [0:3] mux_tree_tapbuf_size8_6_sram ; -wire [0:3] mux_tree_tapbuf_size8_7_sram ; -wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ; - -assign SC_IN_TOP = SC_IN_BOT ; - -cbx_1__1__mux_tree_tapbuf_size10_0 mux_top_ipin_0 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , - chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , - chanx_right_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_top_ipin_0_undriven_sram_inv ) , - .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_104 ) ) ; -cbx_1__1__mux_tree_tapbuf_size10_4 mux_top_ipin_3 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , - chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , - chanx_right_in[19] } ) , - .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_top_ipin_3_undriven_sram_inv ) , - .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_105 ) ) ; -cbx_1__1__mux_tree_tapbuf_size10_5 mux_top_ipin_4 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , - chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[14] , - chanx_right_in[14] } ) , - .sram ( mux_tree_tapbuf_size10_2_sram ) , - .sram_inv ( mux_top_ipin_4_undriven_sram_inv ) , - .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_102 ) ) ; -cbx_1__1__mux_tree_tapbuf_size10_6 mux_top_ipin_7 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , - chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , - chanx_right_in[17] } ) , - .sram ( mux_tree_tapbuf_size10_3_sram ) , - .sram_inv ( mux_top_ipin_7_undriven_sram_inv ) , - .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_104 ) ) ; -cbx_1__1__mux_tree_tapbuf_size10 mux_top_ipin_8 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[8] , chanx_right_in[8] , - chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , - chanx_right_in[18] } ) , - .sram ( mux_tree_tapbuf_size10_4_sram ) , - .sram_inv ( mux_top_ipin_8_undriven_sram_inv ) , - .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_103 ) ) ; -cbx_1__1__mux_tree_tapbuf_size10_1 mux_top_ipin_11 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , - chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[15] , - chanx_right_in[15] } ) , - .sram ( mux_tree_tapbuf_size10_5_sram ) , - .sram_inv ( mux_top_ipin_11_undriven_sram_inv ) , - .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_105 ) ) ; -cbx_1__1__mux_tree_tapbuf_size10_2 mux_top_ipin_12 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , - chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[16] , - chanx_right_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_6_sram ) , - .sram_inv ( mux_top_ipin_12_undriven_sram_inv ) , - .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_103 ) ) ; -cbx_1__1__mux_tree_tapbuf_size10_3 mux_top_ipin_15 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , - chanx_left_in[15] , chanx_right_in[15] , chanx_left_in[19] , - chanx_right_in[19] } ) , - .sram ( mux_tree_tapbuf_size10_7_sram ) , - .sram_inv ( mux_top_ipin_15_undriven_sram_inv ) , - .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_105 ) ) ; -cbx_1__1__mux_tree_tapbuf_size10_mem_0 mem_top_ipin_0 ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; -cbx_1__1__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ; -cbx_1__1__mux_tree_tapbuf_size10_mem_5 mem_top_ipin_4 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ; -cbx_1__1__mux_tree_tapbuf_size10_mem_6 mem_top_ipin_7 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ; -cbx_1__1__mux_tree_tapbuf_size10_mem mem_top_ipin_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ; -cbx_1__1__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_11 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ; -cbx_1__1__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_12 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ; -cbx_1__1__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_15 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .ccff_tail ( { ropt_net_124 } ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_0 mux_top_ipin_1 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , - chanx_left_in[13] , chanx_right_in[13] } ) , - .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_top_ipin_1_undriven_sram_inv ) , - .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_105 ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_4 mux_top_ipin_2 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , - chanx_left_in[14] , chanx_right_in[14] } ) , - .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_top_ipin_2_undriven_sram_inv ) , - .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_102 ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_5 mux_top_ipin_5 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , - chanx_left_in[17] , chanx_right_in[17] } ) , - .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_top_ipin_5_undriven_sram_inv ) , - .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_104 ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_6 mux_top_ipin_6 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , - chanx_left_in[18] , chanx_right_in[18] } ) , - .sram ( mux_tree_tapbuf_size8_3_sram ) , - .sram_inv ( mux_top_ipin_6_undriven_sram_inv ) , - .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_103 ) ) ; -cbx_1__1__mux_tree_tapbuf_size8 mux_top_ipin_9 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , - chanx_left_in[13] , chanx_right_in[13] } ) , - .sram ( mux_tree_tapbuf_size8_4_sram ) , - .sram_inv ( mux_top_ipin_9_undriven_sram_inv ) , - .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_103 ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_1 mux_top_ipin_10 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , - chanx_left_in[14] , chanx_right_in[14] } ) , - .sram ( mux_tree_tapbuf_size8_5_sram ) , - .sram_inv ( mux_top_ipin_10_undriven_sram_inv ) , - .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_102 ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_2 mux_top_ipin_13 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , - chanx_left_in[17] , chanx_right_in[17] } ) , - .sram ( mux_tree_tapbuf_size8_6_sram ) , - .sram_inv ( mux_top_ipin_13_undriven_sram_inv ) , - .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_104 ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_3 mux_top_ipin_14 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , - chanx_left_in[18] , chanx_right_in[18] } ) , - .sram ( mux_tree_tapbuf_size8_7_sram ) , - .sram_inv ( mux_top_ipin_14_undriven_sram_inv ) , - .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_103 ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_mem_0 mem_top_ipin_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_mem_4 mem_top_ipin_2 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_mem_5 mem_top_ipin_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_mem_6 mem_top_ipin_6 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_3_sram ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_mem mem_top_ipin_9 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_4_sram ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_mem_1 mem_top_ipin_10 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_5_sram ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_mem_2 mem_top_ipin_13 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_6_sram ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_mem_3 mem_top_ipin_14 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_7_sram ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chanx_left_in[0] ) , - .X ( chanx_right_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_134 ) , - .X ( chanx_left_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chanx_left_in[2] ) , - .X ( chanx_right_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__4 ( .A ( chanx_left_in[4] ) , - .X ( ropt_net_128 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_102 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_103 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__7 ( .A ( chanx_left_in[7] ) , - .X ( ropt_net_130 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_104 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_105 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chanx_left_in[10] ) , - .X ( ropt_net_133 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( ropt_net_135 ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__clkbuf_1 \prog_clk[0]_bip373 ( .A ( prog_clk[0] ) , - .X ( ctsbuf_net_1106 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( chanx_right_in[4] ) , - .X ( chanx_left_out[4] ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_326699 ( .A ( ctsbuf_net_1106 ) , - .X ( prog_clk__FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_136 ) , - .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( ropt_net_108 ) , - .X ( ropt_net_146 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chanx_left_in[17] ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_137 ) , - .X ( chanx_left_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_138 ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_right_in[0] ) , - .X ( chanx_left_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , - .X ( ropt_net_123 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chanx_right_in[2] ) , - .X ( chanx_left_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chanx_right_in[3] ) , - .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_728 ( .A ( chanx_left_in[13] ) , - .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chanx_right_in[5] ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_148 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chanx_right_in[7] ) , - .X ( ropt_net_145 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_110 ) , - .X ( ropt_net_141 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chanx_right_in[9] ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( chanx_right_in[15] ) , - .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_32__31 ( .A ( chanx_right_in[11] ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_134 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_126 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_35__34 ( .A ( chanx_right_in[14] ) , - .X ( ropt_net_132 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( chanx_left_in[9] ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_37__36 ( .A ( chanx_right_in[16] ) , - .X ( ropt_net_129 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_38__37 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_121 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_39__38 ( .A ( chanx_right_in[18] ) , - .X ( ropt_net_125 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( chanx_left_in[5] ) , - .X ( ropt_net_149 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_41__40 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_108 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_770 ( .A ( ropt_net_139 ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_59 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_131 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( chanx_left_in[18] ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_772 ( .A ( ropt_net_140 ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_774 ( .A ( ropt_net_141 ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_63 ( .A ( chanx_left_in[14] ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_64 ( .A ( chanx_left_in[15] ) , - .X ( ropt_net_110 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_116 ) , - .X ( ropt_net_135 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( .A ( ropt_net_142 ) , - .X ( chanx_right_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( ropt_net_143 ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_777 ( .A ( ropt_net_144 ) , - .X ( chanx_left_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( chanx_left_in[11] ) , - .X ( ropt_net_139 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_70 ( .A ( chanx_right_in[19] ) , - .X ( ropt_net_127 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( chanx_left_in[8] ) , - .X ( chanx_right_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( chanx_left_in[16] ) , - .X ( ropt_net_147 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_739 ( .A ( chanx_left_in[1] ) , - .X ( chanx_right_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_121 ) , - .X ( ropt_net_138 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( .A ( chanx_right_in[12] ) , - .X ( chanx_left_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_145 ) , - .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_79 ( .A ( chanx_left_in[19] ) , - .X ( ropt_net_116 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_123 ) , - .X ( ropt_net_137 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_124 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_125 ) , - .X ( ropt_net_136 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( chanx_left_in[12] ) , - .X ( chanx_right_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_146 ) , - .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_88 ( .A ( chanx_right_in[10] ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_147 ) , - .X ( chanx_right_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_148 ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_149 ) , - .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_126 ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( .A ( ropt_net_127 ) , - .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_128 ) , - .X ( ropt_net_142 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_129 ) , - .X ( ropt_net_144 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_130 ) , - .X ( ropt_net_143 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_131 ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_132 ) , - .X ( ropt_net_140 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_133 ) , - .X ( chanx_right_out[10] ) ) ; -endmodule - - -module cbx_1__0__direct_interc_3 ( in , out ) ; -input [0:0] in ; -output [0:0] out ; -endmodule - - -module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( prog_clk , - ccff_head , ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:0] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_24__70 ( .A ( mem_out[0] ) , - .X ( net_net_108 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_163 ( .A ( net_net_108 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__0__EMBEDDED_IO ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , - FPGA_OUT , FPGA_DIR , p_abuf0 ) ; -input SOC_IN ; -output SOC_OUT ; -output SOC_DIR ; -output FPGA_IN ; -input FPGA_OUT ; -input FPGA_DIR ; -output p_abuf0 ; - -assign SOC_OUT = FPGA_OUT ; - -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__68 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 FTB_23__69 ( .A ( FPGA_DIR ) , - .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_82 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; -endmodule - - -module cbx_1__0__logical_tile_io_mode_physical__iopad ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] iopad_outpad ; -input [0:0] ccff_head ; -output [0:0] iopad_inpad ; -output [0:0] ccff_tail ; -output p_abuf0 ; - -wire [0:0] EMBEDDED_IO_0_en ; - -cbx_1__0__EMBEDDED_IO EMBEDDED_IO_0_ ( - .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , - .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , - .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , - .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) ) ; -endmodule - - -module cbx_1__0__logical_tile_io_mode_io_ ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , - ccff_tail , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] io_outpad ; -input [0:0] ccff_head ; -output [0:0] io_inpad ; -output [0:0] ccff_tail ; -output p_abuf0 ; - -cbx_1__0__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , - .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , - .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__0__direct_interc_3 direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; -cbx_1__0__direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( io_outpad ) ) ; -endmodule - - -module cbx_1__0__direct_interc_2 ( in , out ) ; -input [0:0] in ; -output [0:0] out ; -endmodule - - -module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_4 ( prog_clk , - ccff_head , ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:0] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__67 ( .A ( mem_out[0] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__0__EMBEDDED_IO_4 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , - FPGA_OUT , FPGA_DIR , p_abuf0 ) ; -input SOC_IN ; -output SOC_OUT ; -output SOC_DIR ; -output FPGA_IN ; -input FPGA_OUT ; -input FPGA_DIR ; -output p_abuf0 ; - -assign SOC_OUT = FPGA_OUT ; - -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__65 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 FTB_20__66 ( .A ( FPGA_DIR ) , - .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_150 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; -endmodule - - -module cbx_1__0__logical_tile_io_mode_physical__iopad_4 ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] iopad_outpad ; -input [0:0] ccff_head ; -output [0:0] iopad_inpad ; -output [0:0] ccff_tail ; -output p_abuf0 ; - -wire [0:0] EMBEDDED_IO_0_en ; - -cbx_1__0__EMBEDDED_IO_4 EMBEDDED_IO_0_ ( - .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , - .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , - .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , - .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_4 EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) ) ; -endmodule - - -module cbx_1__0__logical_tile_io_mode_io__4 ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , - ccff_tail , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] io_outpad ; -input [0:0] ccff_head ; -output [0:0] io_inpad ; -output [0:0] ccff_tail ; -output p_abuf0 ; - -cbx_1__0__logical_tile_io_mode_physical__iopad_4 logical_tile_io_mode_physical__iopad_0 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , - .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , - .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__0__direct_interc_2 direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; -cbx_1__0__direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( io_outpad ) ) ; -endmodule - - -module cbx_1__0__direct_interc_1 ( in , out ) ; -input [0:0] in ; -output [0:0] out ; -endmodule - - -module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_3 ( prog_clk , - ccff_head , ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:0] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__64 ( .A ( mem_out[0] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__0__EMBEDDED_IO_3 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , - FPGA_OUT , FPGA_DIR , p_abuf0 ) ; -input SOC_IN ; -output SOC_OUT ; -output SOC_DIR ; -output FPGA_IN ; -input FPGA_OUT ; -input FPGA_DIR ; -output p_abuf0 ; - -wire aps_rename_3_ ; - -assign SOC_OUT = FPGA_OUT ; - -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__62 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__63 ( .A ( FPGA_DIR ) , - .X ( aps_rename_3_ ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_78 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_162 ( .A ( aps_rename_3_ ) , - .X ( SOC_DIR ) ) ; -endmodule - - -module cbx_1__0__logical_tile_io_mode_physical__iopad_3 ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] iopad_outpad ; -input [0:0] ccff_head ; -output [0:0] iopad_inpad ; -output [0:0] ccff_tail ; -output p_abuf0 ; - -wire [0:0] EMBEDDED_IO_0_en ; - -cbx_1__0__EMBEDDED_IO_3 EMBEDDED_IO_0_ ( - .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , - .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , - .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , - .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_3 EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) ) ; -endmodule - - -module cbx_1__0__logical_tile_io_mode_io__3 ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , - ccff_tail , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] io_outpad ; -input [0:0] ccff_head ; -output [0:0] io_inpad ; -output [0:0] ccff_tail ; -output p_abuf0 ; - -cbx_1__0__logical_tile_io_mode_physical__iopad_3 logical_tile_io_mode_physical__iopad_0 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , - .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , - .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__0__direct_interc_1 direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; -cbx_1__0__direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( io_outpad ) ) ; -endmodule - - -module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_2 ( prog_clk , - ccff_head , ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:0] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__61 ( .A ( mem_out[0] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__0__EMBEDDED_IO_2 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , - FPGA_OUT , FPGA_DIR , p_abuf0 , p_abuf1 ) ; -input SOC_IN ; -output SOC_OUT ; -output SOC_DIR ; -output FPGA_IN ; -input FPGA_OUT ; -input FPGA_DIR ; -output p_abuf0 ; -output p_abuf1 ; - -assign SOC_OUT = FPGA_OUT ; - -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__59 ( .A ( SOC_IN ) , .X ( p_abuf1 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__60 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_75 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_76 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; -endmodule - - -module cbx_1__0__logical_tile_io_mode_physical__iopad_2 ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , p_abuf0 , p_abuf1 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] iopad_outpad ; -input [0:0] ccff_head ; -output [0:0] iopad_inpad ; -output [0:0] ccff_tail ; -output p_abuf0 ; -output p_abuf1 ; - -wire [0:0] EMBEDDED_IO_0_en ; - -cbx_1__0__EMBEDDED_IO_2 EMBEDDED_IO_0_ ( - .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , - .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , - .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , - .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , - .p_abuf1 ( p_abuf1 ) ) ; -cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_2 EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) ) ; -endmodule - - -module cbx_1__0__logical_tile_io_mode_io__2 ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , - ccff_tail , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] io_outpad ; -input [0:0] ccff_head ; -output [0:0] io_inpad ; -output [0:0] ccff_tail ; -output p_abuf0 ; - -cbx_1__0__logical_tile_io_mode_physical__iopad_2 logical_tile_io_mode_physical__iopad_0 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , - .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , - .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; -cbx_1__0__direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( { p_abuf1 } ) ) ; -cbx_1__0__direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( io_outpad ) ) ; -endmodule - - -module cbx_1__0__direct_interc_0 ( in , out ) ; -input [0:0] in ; -output [0:0] out ; -endmodule - - -module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_1 ( prog_clk , - ccff_head , ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:0] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__58 ( .A ( mem_out[0] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__0__EMBEDDED_IO_1 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , - FPGA_OUT , FPGA_DIR , p_abuf0 ) ; -input SOC_IN ; -output SOC_OUT ; -output SOC_DIR ; -output FPGA_IN ; -input FPGA_OUT ; -input FPGA_DIR ; -output p_abuf0 ; - -assign SOC_OUT = FPGA_OUT ; - -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__56 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__57 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_141 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; -endmodule - - -module cbx_1__0__logical_tile_io_mode_physical__iopad_1 ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] iopad_outpad ; -input [0:0] ccff_head ; -output [0:0] iopad_inpad ; -output [0:0] ccff_tail ; -output p_abuf0 ; - -wire [0:0] EMBEDDED_IO_0_en ; - -cbx_1__0__EMBEDDED_IO_1 EMBEDDED_IO_0_ ( - .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , - .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , - .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , - .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_1 EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) ) ; -endmodule - - -module cbx_1__0__logical_tile_io_mode_io__1 ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , - ccff_tail , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] io_outpad ; -input [0:0] ccff_head ; -output [0:0] io_inpad ; -output [0:0] ccff_tail ; -output p_abuf0 ; - -cbx_1__0__logical_tile_io_mode_physical__iopad_1 logical_tile_io_mode_physical__iopad_0 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , - .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , - .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__0__direct_interc_0 direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; -cbx_1__0__direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( io_outpad ) ) ; -endmodule - - -module cbx_1__0__direct_interc ( in , out ) ; -input [0:0] in ; -output [0:0] out ; - -assign out[0] = in[0] ; -endmodule - - -module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_0 ( prog_clk , - ccff_head , ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:0] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__55 ( .A ( mem_out[0] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__0__EMBEDDED_IO_0 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , - FPGA_OUT , FPGA_DIR , p_abuf0 , p_abuf1 ) ; -input SOC_IN ; -output SOC_OUT ; -output SOC_DIR ; -output FPGA_IN ; -input FPGA_OUT ; -input FPGA_DIR ; -output p_abuf0 ; -output p_abuf1 ; - -assign SOC_OUT = FPGA_OUT ; - -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__53 ( .A ( SOC_IN ) , .X ( p_abuf1 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__54 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_71 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_146 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; -endmodule - - -module cbx_1__0__logical_tile_io_mode_physical__iopad_0 ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , p_abuf0 , p_abuf1 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] iopad_outpad ; -input [0:0] ccff_head ; -output [0:0] iopad_inpad ; -output [0:0] ccff_tail ; -output p_abuf0 ; -output p_abuf1 ; - -wire [0:0] EMBEDDED_IO_0_en ; - -cbx_1__0__EMBEDDED_IO_0 EMBEDDED_IO_0_ ( - .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , - .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , - .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , - .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , - .p_abuf1 ( p_abuf1 ) ) ; -cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_0 EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) ) ; -endmodule - - -module cbx_1__0__logical_tile_io_mode_io__0 ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , - ccff_tail , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] io_outpad ; -input [0:0] ccff_head ; -output [0:0] io_inpad ; -output [0:0] ccff_tail ; -output p_abuf0 ; - -cbx_1__0__logical_tile_io_mode_physical__iopad_0 logical_tile_io_mode_physical__iopad_0 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , - .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , - .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; -cbx_1__0__direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( { p_abuf1 } ) ) ; -cbx_1__0__direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( io_outpad ) ) ; -endmodule - - -module cbx_1__0__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__52 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__0__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__51 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__0__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__50 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__0__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__49 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__0__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__48 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__0__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__47 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__0__const1 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cbx_1__0__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; - -cbx_1__0__const1 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; -endmodule - - -module cbx_1__0__const1_4 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cbx_1__0__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -cbx_1__0__const1_4 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cbx_1__0__const1_3 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cbx_1__0__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -cbx_1__0__const1_3 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cbx_1__0__const1_2 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cbx_1__0__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -cbx_1__0__const1_2 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cbx_1__0__const1_1 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cbx_1__0__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; - -cbx_1__0__const1_1 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; -endmodule - - -module cbx_1__0__const1_0 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cbx_1__0__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -cbx_1__0__const1_0 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cbx_1__0_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , - chanx_left_out , chanx_right_out , bottom_grid_pin_0_ , - bottom_grid_pin_2_ , bottom_grid_pin_4_ , bottom_grid_pin_6_ , - bottom_grid_pin_8_ , bottom_grid_pin_10_ , ccff_tail , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , top_width_0_height_0__pin_0_ , - top_width_0_height_0__pin_2_ , top_width_0_height_0__pin_4_ , - top_width_0_height_0__pin_6_ , top_width_0_height_0__pin_8_ , - top_width_0_height_0__pin_10_ , top_width_0_height_0__pin_1_upper , - top_width_0_height_0__pin_1_lower , top_width_0_height_0__pin_3_upper , - top_width_0_height_0__pin_3_lower , top_width_0_height_0__pin_5_upper , - top_width_0_height_0__pin_5_lower , top_width_0_height_0__pin_7_upper , - top_width_0_height_0__pin_7_lower , top_width_0_height_0__pin_9_upper , - top_width_0_height_0__pin_9_lower , top_width_0_height_0__pin_11_upper , - top_width_0_height_0__pin_11_lower , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , - SC_OUT_BOT , prog_clk__FEEDTHRU_1 ) ; -input [0:0] prog_clk ; -input [0:19] chanx_left_in ; -input [0:19] chanx_right_in ; -input [0:0] ccff_head ; -output [0:19] chanx_left_out ; -output [0:19] chanx_right_out ; -output [0:0] bottom_grid_pin_0_ ; -output [0:0] bottom_grid_pin_2_ ; -output [0:0] bottom_grid_pin_4_ ; -output [0:0] bottom_grid_pin_6_ ; -output [0:0] bottom_grid_pin_8_ ; -output [0:0] bottom_grid_pin_10_ ; -output [0:0] ccff_tail ; -input [0:5] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:5] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:5] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] top_width_0_height_0__pin_0_ ; -input [0:0] top_width_0_height_0__pin_2_ ; -input [0:0] top_width_0_height_0__pin_4_ ; -input [0:0] top_width_0_height_0__pin_6_ ; -input [0:0] top_width_0_height_0__pin_8_ ; -input [0:0] top_width_0_height_0__pin_10_ ; -output [0:0] top_width_0_height_0__pin_1_upper ; -output [0:0] top_width_0_height_0__pin_1_lower ; -output [0:0] top_width_0_height_0__pin_3_upper ; -output [0:0] top_width_0_height_0__pin_3_lower ; -output [0:0] top_width_0_height_0__pin_5_upper ; -output [0:0] top_width_0_height_0__pin_5_lower ; -output [0:0] top_width_0_height_0__pin_7_upper ; -output [0:0] top_width_0_height_0__pin_7_lower ; -output [0:0] top_width_0_height_0__pin_9_upper ; -output [0:0] top_width_0_height_0__pin_9_lower ; -output [0:0] top_width_0_height_0__pin_11_upper ; -output [0:0] top_width_0_height_0__pin_11_lower ; -input SC_IN_TOP ; -input SC_IN_BOT ; -output SC_OUT_TOP ; -output SC_OUT_BOT ; -output [0:0] prog_clk__FEEDTHRU_1 ; - -wire ropt_net_191 ; -wire ropt_net_197 ; -wire ropt_net_179 ; -wire ropt_net_177 ; -wire ropt_net_190 ; -wire ropt_net_178 ; -wire [0:3] mux_top_ipin_0_undriven_sram_inv ; -wire [0:3] mux_top_ipin_1_undriven_sram_inv ; -wire [0:3] mux_top_ipin_2_undriven_sram_inv ; -wire [0:3] mux_top_ipin_3_undriven_sram_inv ; -wire [0:3] mux_top_ipin_4_undriven_sram_inv ; -wire [0:3] mux_top_ipin_5_undriven_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:3] mux_tree_tapbuf_size10_2_sram ; -wire [0:3] mux_tree_tapbuf_size10_3_sram ; -wire [0:3] mux_tree_tapbuf_size10_4_sram ; -wire [0:3] mux_tree_tapbuf_size10_5_sram ; -wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; -wire [0:0] logical_tile_io_mode_io__0_ccff_tail ; -wire [0:0] logical_tile_io_mode_io__1_ccff_tail ; -wire [0:0] logical_tile_io_mode_io__2_ccff_tail ; -wire [0:0] logical_tile_io_mode_io__3_ccff_tail ; -wire [0:0] logical_tile_io_mode_io__4_ccff_tail ; - -assign SC_IN_TOP = SC_IN_BOT ; - -cbx_1__0__mux_tree_tapbuf_size10_0 mux_top_ipin_0 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , - chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , - chanx_right_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_top_ipin_0_undriven_sram_inv ) , - .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_174 ) ) ; -cbx_1__0__mux_tree_tapbuf_size10_1 mux_top_ipin_1 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , - chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , - chanx_right_in[17] } ) , - .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_top_ipin_1_undriven_sram_inv ) , - .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_173 ) ) ; -cbx_1__0__mux_tree_tapbuf_size10_2 mux_top_ipin_2 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , - chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , - chanx_right_in[18] } ) , - .sram ( mux_tree_tapbuf_size10_2_sram ) , - .sram_inv ( mux_top_ipin_2_undriven_sram_inv ) , - .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_173 ) ) ; -cbx_1__0__mux_tree_tapbuf_size10_3 mux_top_ipin_3 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , - chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , - chanx_right_in[19] } ) , - .sram ( mux_tree_tapbuf_size10_3_sram ) , - .sram_inv ( mux_top_ipin_3_undriven_sram_inv ) , - .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_173 ) ) ; -cbx_1__0__mux_tree_tapbuf_size10_4 mux_top_ipin_4 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , - chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[14] , - chanx_right_in[14] } ) , - .sram ( mux_tree_tapbuf_size10_4_sram ) , - .sram_inv ( mux_top_ipin_4_undriven_sram_inv ) , - .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_174 ) ) ; -cbx_1__0__mux_tree_tapbuf_size10 mux_top_ipin_5 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , - chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[15] , - chanx_right_in[15] } ) , - .sram ( mux_tree_tapbuf_size10_5_sram ) , - .sram_inv ( mux_top_ipin_5_undriven_sram_inv ) , - .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_174 ) ) ; -cbx_1__0__mux_tree_tapbuf_size10_mem_0 mem_top_ipin_0 ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; -cbx_1__0__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ; -cbx_1__0__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_2 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ; -cbx_1__0__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ; -cbx_1__0__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_4 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ; -cbx_1__0__mux_tree_tapbuf_size10_mem mem_top_ipin_5 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , - .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ; -cbx_1__0__logical_tile_io_mode_io__0 logical_tile_io_mode_io__0 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_196 } ) , - .io_outpad ( top_width_0_height_0__pin_0_ ) , - .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_8_ } ) , - .ccff_tail ( logical_tile_io_mode_io__0_ccff_tail ) , - .p_abuf0 ( ropt_net_191 ) ) ; -cbx_1__0__logical_tile_io_mode_io__1 logical_tile_io_mode_io__1 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[1] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[1] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_200 } ) , - .io_outpad ( top_width_0_height_0__pin_2_ ) , - .ccff_head ( logical_tile_io_mode_io__0_ccff_tail ) , - .io_inpad ( { aps_rename_10_ } ) , - .ccff_tail ( logical_tile_io_mode_io__1_ccff_tail ) , - .p_abuf0 ( ropt_net_197 ) ) ; -cbx_1__0__logical_tile_io_mode_io__2 logical_tile_io_mode_io__2 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[2] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[2] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_198 } ) , - .io_outpad ( top_width_0_height_0__pin_4_ ) , - .ccff_head ( logical_tile_io_mode_io__1_ccff_tail ) , - .io_inpad ( { aps_rename_12_ } ) , - .ccff_tail ( logical_tile_io_mode_io__2_ccff_tail ) , - .p_abuf0 ( ropt_net_179 ) ) ; -cbx_1__0__logical_tile_io_mode_io__3 logical_tile_io_mode_io__3 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[3] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[3] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_193 } ) , - .io_outpad ( top_width_0_height_0__pin_6_ ) , - .ccff_head ( logical_tile_io_mode_io__2_ccff_tail ) , - .io_inpad ( { aps_rename_13_ } ) , - .ccff_tail ( logical_tile_io_mode_io__3_ccff_tail ) , - .p_abuf0 ( ropt_net_177 ) ) ; -cbx_1__0__logical_tile_io_mode_io__4 logical_tile_io_mode_io__4 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[4] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[4] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_201 } ) , - .io_outpad ( top_width_0_height_0__pin_8_ ) , - .ccff_head ( logical_tile_io_mode_io__3_ccff_tail ) , - .io_inpad ( { aps_rename_14_ } ) , - .ccff_tail ( logical_tile_io_mode_io__4_ccff_tail ) , - .p_abuf0 ( ropt_net_190 ) ) ; -cbx_1__0__logical_tile_io_mode_io_ logical_tile_io_mode_io__5 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[5] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[5] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[5] ) , - .io_outpad ( top_width_0_height_0__pin_10_ ) , - .ccff_head ( logical_tile_io_mode_io__4_ccff_tail ) , - .io_inpad ( { aps_rename_15_ } ) , - .ccff_tail ( { ropt_net_212 } ) , - .p_abuf0 ( ropt_net_178 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_166 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_173 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_168 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_174 ) ) ; -sky130_fd_sc_hd__clkbuf_1 \prog_clk[0]_bip435 ( .A ( prog_clk[0] ) , - .X ( ctsbuf_net_1176 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , - .X ( ropt_net_207 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_177 ) , - .X ( ropt_net_243 ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_326761 ( .A ( ctsbuf_net_1176 ) , - .X ( prog_clk__FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_849 ( .A ( ropt_net_239 ) , - .X ( chanx_left_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_178 ) , - .X ( ropt_net_247 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_266 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chanx_left_in[9] ) , - .X ( ropt_net_208 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_179 ) , - .X ( ropt_net_249 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( ropt_net_180 ) , - .X ( ropt_net_245 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_792 ( .A ( ropt_net_181 ) , - .X ( top_width_0_height_0__pin_11_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( ropt_net_182 ) , - .X ( ropt_net_270 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_244 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__15 ( .A ( chanx_left_in[15] ) , - .X ( ropt_net_222 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_184 ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( chanx_right_in[5] ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_233 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( chanx_right_in[7] ) , - .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_187 ) , - .X ( top_width_0_height_0__pin_3_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , - .X ( ropt_net_219 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_850 ( .A ( ropt_net_240 ) , - .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_188 ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_246 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_190 ) , - .X ( ropt_net_250 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_224 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_191 ) , - .X ( top_width_0_height_0__pin_1_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_192 ) , - .X ( ropt_net_240 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__29 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_221 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__30 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_223 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_851 ( .A ( ropt_net_241 ) , - .X ( chanx_left_out[12] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__32 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_216 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_193 ) , - .X ( ropt_net_262 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_194 ) , - .X ( top_width_0_height_0__pin_1_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_36__35 ( .A ( chanx_right_in[15] ) , - .X ( ropt_net_226 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_37__36 ( .A ( chanx_right_in[16] ) , - .X ( ropt_net_229 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( ropt_net_195 ) , - .X ( ropt_net_264 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_39__38 ( .A ( chanx_right_in[18] ) , - .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_852 ( .A ( ropt_net_242 ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_41__40 ( .A ( aps_rename_8_ ) , - .X ( aps_rename_9_ ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_853 ( .A ( ropt_net_243 ) , - .X ( top_width_0_height_0__pin_7_upper[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_43__42 ( .A ( aps_rename_12_ ) , - .X ( ropt_net_182 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_196 ) , - .X ( ropt_net_254 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_197 ) , - .X ( top_width_0_height_0__pin_3_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_46__45 ( .A ( aps_rename_15_ ) , - .X ( ropt_net_181 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_47__46 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_180 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_85 ( .A ( chanx_left_in[0] ) , - .X ( ropt_net_209 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_86 ( .A ( chanx_left_in[1] ) , - .X ( ropt_net_225 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_87 ( .A ( chanx_left_in[4] ) , - .X ( ropt_net_214 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_88 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_184 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_809 ( .A ( ropt_net_198 ) , - .X ( ropt_net_268 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_90 ( .A ( chanx_left_in[11] ) , - .X ( ropt_net_227 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_810 ( .A ( ropt_net_199 ) , - .X ( ropt_net_265 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_92 ( .A ( chanx_left_in[16] ) , - .X ( ropt_net_213 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_93 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_210 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_94 ( .A ( chanx_right_in[3] ) , - .X ( ropt_net_220 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_854 ( .A ( ropt_net_244 ) , - .X ( chanx_left_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_857 ( .A ( ropt_net_245 ) , - .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_858 ( .A ( ropt_net_246 ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_811 ( .A ( ropt_net_200 ) , - .X ( ropt_net_267 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_860 ( .A ( ropt_net_247 ) , - .X ( top_width_0_height_0__pin_11_upper[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_100 ( .A ( chanx_right_in[14] ) , - .X ( ropt_net_231 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_862 ( .A ( ropt_net_248 ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_812 ( .A ( ropt_net_201 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_103 ( .A ( aps_rename_9_ ) , - .X ( ropt_net_194 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_104 ( .A ( aps_rename_10_ ) , - .X ( ropt_net_187 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_864 ( .A ( ropt_net_249 ) , - .X ( top_width_0_height_0__pin_5_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_865 ( .A ( ropt_net_250 ) , - .X ( top_width_0_height_0__pin_9_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( chanx_right_in[2] ) , - .X ( chanx_left_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_814 ( .A ( chanx_left_in[5] ) , - .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_815 ( .A ( chanx_left_in[7] ) , - .X ( ropt_net_269 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_205 ) , - .X ( ropt_net_256 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_817 ( .A ( chanx_right_in[13] ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_207 ) , - .X ( ropt_net_248 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_208 ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_209 ) , - .X ( ropt_net_260 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_210 ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_211 ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_212 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_213 ) , - .X ( chanx_right_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_131 ( .A ( chanx_left_in[2] ) , - .X ( ropt_net_228 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_866 ( .A ( ropt_net_251 ) , - .X ( chanx_left_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_133 ( .A ( chanx_left_in[10] ) , - .X ( ropt_net_211 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_134 ( .A ( chanx_left_in[12] ) , - .X ( ropt_net_205 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_135 ( .A ( chanx_left_in[13] ) , - .X ( ropt_net_217 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_136 ( .A ( chanx_left_in[19] ) , - .X ( ropt_net_215 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_137 ( .A ( chanx_right_in[0] ) , - .X ( ropt_net_232 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_138 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_218 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( ropt_net_214 ) , - .X ( ropt_net_259 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_144 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_188 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_145 ( .A ( chanx_right_in[19] ) , - .X ( ropt_net_192 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_826 ( .A ( ropt_net_215 ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_867 ( .A ( ropt_net_252 ) , - .X ( chanx_left_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_154 ( .A ( chanx_left_in[14] ) , - .X ( ropt_net_230 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_827 ( .A ( ropt_net_216 ) , - .X ( ropt_net_241 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_217 ) , - .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_829 ( .A ( ropt_net_218 ) , - .X ( ropt_net_252 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_219 ) , - .X ( ropt_net_239 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_220 ) , - .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_160 ( .A ( aps_rename_13_ ) , - .X ( ropt_net_199 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_161 ( .A ( aps_rename_14_ ) , - .X ( ropt_net_195 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_832 ( .A ( ropt_net_221 ) , - .X ( ropt_net_242 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_833 ( .A ( ropt_net_222 ) , - .X ( ropt_net_255 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_834 ( .A ( ropt_net_223 ) , - .X ( ropt_net_257 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_835 ( .A ( ropt_net_224 ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_836 ( .A ( ropt_net_225 ) , - .X ( ropt_net_258 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_838 ( .A ( ropt_net_226 ) , - .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_839 ( .A ( ropt_net_227 ) , - .X ( ropt_net_261 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_840 ( .A ( ropt_net_228 ) , - .X ( chanx_right_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_841 ( .A ( ropt_net_229 ) , - .X ( ropt_net_263 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_843 ( .A ( ropt_net_230 ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_844 ( .A ( ropt_net_231 ) , - .X ( ropt_net_253 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_845 ( .A ( ropt_net_232 ) , - .X ( ropt_net_251 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_847 ( .A ( ropt_net_233 ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_868 ( .A ( ropt_net_253 ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_871 ( .A ( ropt_net_254 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_873 ( .A ( ropt_net_255 ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_874 ( .A ( ropt_net_256 ) , - .X ( chanx_right_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_875 ( .A ( ropt_net_257 ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_876 ( .A ( ropt_net_258 ) , - .X ( chanx_right_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_877 ( .A ( ropt_net_259 ) , - .X ( chanx_right_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_878 ( .A ( ropt_net_260 ) , - .X ( chanx_right_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_879 ( .A ( ropt_net_261 ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_880 ( .A ( ropt_net_262 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_882 ( .A ( ropt_net_263 ) , - .X ( chanx_left_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_889 ( .A ( ropt_net_264 ) , - .X ( top_width_0_height_0__pin_9_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_890 ( .A ( ropt_net_265 ) , - .X ( top_width_0_height_0__pin_7_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_892 ( .A ( ropt_net_266 ) , - .X ( chanx_right_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_893 ( .A ( ropt_net_267 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_894 ( .A ( ropt_net_268 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_896 ( .A ( ropt_net_269 ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_899 ( .A ( ropt_net_270 ) , - .X ( top_width_0_height_0__pin_5_lower[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_35__40 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_34__39 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__38 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__const1 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sb_2__2__const1 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_2__2__const1_33 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sb_2__2__const1_33 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_2__2__const1_32 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sb_2__2__const1_32 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__37 ( .A ( mem_out[1] ) , - .X ( net_net_51 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_51 ( .A ( net_net_51 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_22 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__36 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_21 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__35 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_20 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__34 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_19 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__33 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_18 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__32 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_17 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__31 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__30 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__29 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__28 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__27 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__26 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__25 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__24 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__23 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__22 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__21 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__20 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__19 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__18 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__17 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__16 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__15 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__14 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__const1_31 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__2__const1_31 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__const1_30 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_22 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__2__const1_30 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__const1_29 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_21 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__2__const1_29 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__const1_28 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_20 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__2__const1_28 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__const1_27 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_19 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__2__const1_27 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__const1_26 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__2__const1_26 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__const1_25 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__2__const1_25 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__const1_24 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__2__const1_24 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__const1_23 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__2__const1_23 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__const1_22 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__2__const1_22 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__const1_21 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__2__const1_21 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__const1_20 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__2__const1_20 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__const1_19 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__2__const1_19 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__const1_18 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__2__const1_18 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__const1_17 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__2__const1_17 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__const1_16 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__2__const1_16 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__const1_15 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__2__const1_15 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__const1_14 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__2__const1_14 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__const1_13 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__2__const1_13 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__const1_12 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__2__const1_12 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__const1_11 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__2__const1_11 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__const1_10 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__2__const1_10 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__const1_9 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__2__const1_9 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__const1_8 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__2__const1_8 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__13 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size5_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__12 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size5_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__11 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__10 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__const1_7 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -sb_2__2__const1_7 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -endmodule - - -module sb_2__2__const1_6 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sb_2__2__const1_6 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_2__2__const1_5 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sb_2__2__const1_5 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_2__2__const1_4 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -sb_2__2__const1_4 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__9 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size6_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__8 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__7 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__6 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__const1_3 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sb_2__2__const1_3 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module sb_2__2__const1_2 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sb_2__2__const1_2 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module sb_2__2__const1_1 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sb_2__2__const1_1 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module sb_2__2__const1_0 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sb_2__2__const1_0 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module sb_2__2_ ( prog_clk , chany_bottom_in , bottom_right_grid_pin_1_ , - bottom_left_grid_pin_42_ , bottom_left_grid_pin_43_ , - bottom_left_grid_pin_44_ , bottom_left_grid_pin_45_ , - bottom_left_grid_pin_46_ , bottom_left_grid_pin_47_ , - bottom_left_grid_pin_48_ , bottom_left_grid_pin_49_ , chanx_left_in , - left_top_grid_pin_1_ , left_bottom_grid_pin_34_ , - left_bottom_grid_pin_35_ , left_bottom_grid_pin_36_ , - left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , - left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , - left_bottom_grid_pin_41_ , ccff_head , chany_bottom_out , chanx_left_out , - ccff_tail , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , SC_OUT_BOT ) ; -input [0:0] prog_clk ; -input [0:19] chany_bottom_in ; -input [0:0] bottom_right_grid_pin_1_ ; -input [0:0] bottom_left_grid_pin_42_ ; -input [0:0] bottom_left_grid_pin_43_ ; -input [0:0] bottom_left_grid_pin_44_ ; -input [0:0] bottom_left_grid_pin_45_ ; -input [0:0] bottom_left_grid_pin_46_ ; -input [0:0] bottom_left_grid_pin_47_ ; -input [0:0] bottom_left_grid_pin_48_ ; -input [0:0] bottom_left_grid_pin_49_ ; -input [0:19] chanx_left_in ; -input [0:0] left_top_grid_pin_1_ ; -input [0:0] left_bottom_grid_pin_34_ ; -input [0:0] left_bottom_grid_pin_35_ ; -input [0:0] left_bottom_grid_pin_36_ ; -input [0:0] left_bottom_grid_pin_37_ ; -input [0:0] left_bottom_grid_pin_38_ ; -input [0:0] left_bottom_grid_pin_39_ ; -input [0:0] left_bottom_grid_pin_40_ ; -input [0:0] left_bottom_grid_pin_41_ ; -input [0:0] ccff_head ; -output [0:19] chany_bottom_out ; -output [0:19] chanx_left_out ; -output [0:0] ccff_tail ; -input SC_IN_TOP ; -input SC_IN_BOT ; -output SC_OUT_TOP ; -output SC_OUT_BOT ; - -wire [0:1] mux_bottom_track_11_undriven_sram_inv ; -wire [0:1] mux_bottom_track_13_undriven_sram_inv ; -wire [0:1] mux_bottom_track_15_undriven_sram_inv ; -wire [0:1] mux_bottom_track_17_undriven_sram_inv ; -wire [0:1] mux_bottom_track_19_undriven_sram_inv ; -wire [0:2] mux_bottom_track_1_undriven_sram_inv ; -wire [0:1] mux_bottom_track_21_undriven_sram_inv ; -wire [0:1] mux_bottom_track_23_undriven_sram_inv ; -wire [0:1] mux_bottom_track_25_undriven_sram_inv ; -wire [0:1] mux_bottom_track_27_undriven_sram_inv ; -wire [0:1] mux_bottom_track_29_undriven_sram_inv ; -wire [0:2] mux_bottom_track_3_undriven_sram_inv ; -wire [0:2] mux_bottom_track_5_undriven_sram_inv ; -wire [0:2] mux_bottom_track_7_undriven_sram_inv ; -wire [0:1] mux_bottom_track_9_undriven_sram_inv ; -wire [0:1] mux_left_track_11_undriven_sram_inv ; -wire [0:1] mux_left_track_13_undriven_sram_inv ; -wire [0:1] mux_left_track_15_undriven_sram_inv ; -wire [0:1] mux_left_track_17_undriven_sram_inv ; -wire [0:1] mux_left_track_19_undriven_sram_inv ; -wire [0:2] mux_left_track_1_undriven_sram_inv ; -wire [0:1] mux_left_track_21_undriven_sram_inv ; -wire [0:1] mux_left_track_23_undriven_sram_inv ; -wire [0:1] mux_left_track_25_undriven_sram_inv ; -wire [0:1] mux_left_track_27_undriven_sram_inv ; -wire [0:1] mux_left_track_29_undriven_sram_inv ; -wire [0:1] mux_left_track_31_undriven_sram_inv ; -wire [0:1] mux_left_track_33_undriven_sram_inv ; -wire [0:1] mux_left_track_35_undriven_sram_inv ; -wire [0:1] mux_left_track_37_undriven_sram_inv ; -wire [0:1] mux_left_track_39_undriven_sram_inv ; -wire [0:2] mux_left_track_3_undriven_sram_inv ; -wire [0:2] mux_left_track_5_undriven_sram_inv ; -wire [0:2] mux_left_track_7_undriven_sram_inv ; -wire [0:1] mux_left_track_9_undriven_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_10_sram ; -wire [0:1] mux_tree_tapbuf_size2_11_sram ; -wire [0:1] mux_tree_tapbuf_size2_12_sram ; -wire [0:1] mux_tree_tapbuf_size2_13_sram ; -wire [0:1] mux_tree_tapbuf_size2_14_sram ; -wire [0:1] mux_tree_tapbuf_size2_15_sram ; -wire [0:1] mux_tree_tapbuf_size2_16_sram ; -wire [0:1] mux_tree_tapbuf_size2_17_sram ; -wire [0:1] mux_tree_tapbuf_size2_18_sram ; -wire [0:1] mux_tree_tapbuf_size2_19_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_20_sram ; -wire [0:1] mux_tree_tapbuf_size2_21_sram ; -wire [0:1] mux_tree_tapbuf_size2_22_sram ; -wire [0:1] mux_tree_tapbuf_size2_23_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_5_sram ; -wire [0:1] mux_tree_tapbuf_size2_6_sram ; -wire [0:1] mux_tree_tapbuf_size2_7_sram ; -wire [0:1] mux_tree_tapbuf_size2_8_sram ; -wire [0:1] mux_tree_tapbuf_size2_9_sram ; -wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_19_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_20_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_21_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_22_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; -wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:1] mux_tree_tapbuf_size3_2_sram ; -wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size5_0_sram ; -wire [0:2] mux_tree_tapbuf_size5_1_sram ; -wire [0:2] mux_tree_tapbuf_size5_2_sram ; -wire [0:2] mux_tree_tapbuf_size5_3_sram ; -wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size6_1_sram ; -wire [0:2] mux_tree_tapbuf_size6_2_sram ; -wire [0:2] mux_tree_tapbuf_size6_3_sram ; -wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ; - -assign SC_IN_TOP = SC_IN_BOT ; - -sb_2__2__mux_tree_tapbuf_size6_0 mux_bottom_track_1 ( - .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_43_[0] , - bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , - bottom_left_grid_pin_49_[0] , chanx_left_in[1] } ) , - .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_bottom_track_1_undriven_sram_inv ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_82 ) ) ; -sb_2__2__mux_tree_tapbuf_size6_1 mux_bottom_track_5 ( - .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_43_[0] , - bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , - bottom_left_grid_pin_49_[0] , chanx_left_in[3] } ) , - .sram ( mux_tree_tapbuf_size6_1_sram ) , - .sram_inv ( mux_bottom_track_5_undriven_sram_inv ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_84 ) ) ; -sb_2__2__mux_tree_tapbuf_size6_2 mux_left_track_1 ( - .in ( { chany_bottom_in[19] , left_top_grid_pin_1_[0] , - left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , - left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , - .sram ( mux_tree_tapbuf_size6_2_sram ) , - .sram_inv ( mux_left_track_1_undriven_sram_inv ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_83 ) ) ; -sb_2__2__mux_tree_tapbuf_size6 mux_left_track_5 ( - .in ( { chany_bottom_in[1] , left_top_grid_pin_1_[0] , - left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , - left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , - .sram ( mux_tree_tapbuf_size6_3_sram ) , - .sram_inv ( mux_left_track_5_undriven_sram_inv ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_83 ) ) ; -sb_2__2__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_1 ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size6_mem_1 mem_bottom_track_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size6_mem_2 mem_left_track_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_2_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size6_mem mem_left_track_5 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_3_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size5_0 mux_bottom_track_3 ( - .in ( { bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , - bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , - chanx_left_in[2] } ) , - .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_bottom_track_3_undriven_sram_inv ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_82 ) ) ; -sb_2__2__mux_tree_tapbuf_size5_1 mux_bottom_track_7 ( - .in ( { bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , - bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , - chanx_left_in[4] } ) , - .sram ( mux_tree_tapbuf_size5_1_sram ) , - .sram_inv ( mux_bottom_track_7_undriven_sram_inv ) , - .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_84 ) ) ; -sb_2__2__mux_tree_tapbuf_size5_2 mux_left_track_3 ( - .in ( { chany_bottom_in[0] , left_bottom_grid_pin_34_[0] , - left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , - left_bottom_grid_pin_40_[0] } ) , - .sram ( mux_tree_tapbuf_size5_2_sram ) , - .sram_inv ( mux_left_track_3_undriven_sram_inv ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_82 ) ) ; -sb_2__2__mux_tree_tapbuf_size5 mux_left_track_7 ( - .in ( { chany_bottom_in[2] , left_bottom_grid_pin_34_[0] , - left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , - left_bottom_grid_pin_40_[0] } ) , - .sram ( mux_tree_tapbuf_size5_3_sram ) , - .sram_inv ( mux_left_track_7_undriven_sram_inv ) , - .out ( chanx_left_out[3] ) , .p0 ( optlc_net_82 ) ) ; -sb_2__2__mux_tree_tapbuf_size5_mem_0 mem_bottom_track_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size5_mem_1 mem_bottom_track_7 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size5_mem_2 mem_left_track_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_2_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size5_mem mem_left_track_7 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_3_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_9 mux_bottom_track_9 ( - .in ( { bottom_right_grid_pin_1_[0] , chanx_left_in[5] } ) , - .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_bottom_track_9_undriven_sram_inv ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_84 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_0 mux_bottom_track_11 ( - .in ( { bottom_left_grid_pin_42_[0] , chanx_left_in[6] } ) , - .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_bottom_track_11_undriven_sram_inv ) , - .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_84 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_1 mux_bottom_track_13 ( - .in ( { bottom_left_grid_pin_43_[0] , chanx_left_in[7] } ) , - .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_bottom_track_13_undriven_sram_inv ) , - .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_81 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_2 mux_bottom_track_15 ( - .in ( { bottom_left_grid_pin_44_[0] , chanx_left_in[8] } ) , - .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_bottom_track_15_undriven_sram_inv ) , - .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_81 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_3 mux_bottom_track_17 ( - .in ( { bottom_left_grid_pin_45_[0] , chanx_left_in[9] } ) , - .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_bottom_track_17_undriven_sram_inv ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_81 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_4 mux_bottom_track_19 ( - .in ( { bottom_left_grid_pin_46_[0] , chanx_left_in[10] } ) , - .sram ( mux_tree_tapbuf_size2_5_sram ) , - .sram_inv ( mux_bottom_track_19_undriven_sram_inv ) , - .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_84 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_5 mux_bottom_track_21 ( - .in ( { bottom_left_grid_pin_47_[0] , chanx_left_in[11] } ) , - .sram ( mux_tree_tapbuf_size2_6_sram ) , - .sram_inv ( mux_bottom_track_21_undriven_sram_inv ) , - .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_81 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_6 mux_bottom_track_23 ( - .in ( { bottom_left_grid_pin_48_[0] , chanx_left_in[12] } ) , - .sram ( mux_tree_tapbuf_size2_7_sram ) , - .sram_inv ( mux_bottom_track_23_undriven_sram_inv ) , - .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_84 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_7 mux_bottom_track_27 ( - .in ( { bottom_left_grid_pin_42_[0] , chanx_left_in[14] } ) , - .sram ( mux_tree_tapbuf_size2_8_sram ) , - .sram_inv ( mux_bottom_track_27_undriven_sram_inv ) , - .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_84 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_8 mux_bottom_track_29 ( - .in ( { bottom_left_grid_pin_43_[0] , chanx_left_in[15] } ) , - .sram ( mux_tree_tapbuf_size2_9_sram ) , - .sram_inv ( mux_bottom_track_29_undriven_sram_inv ) , - .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_81 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_10 mux_left_track_11 ( - .in ( { chany_bottom_in[4] , left_bottom_grid_pin_34_[0] } ) , - .sram ( mux_tree_tapbuf_size2_10_sram ) , - .sram_inv ( mux_left_track_11_undriven_sram_inv ) , - .out ( chanx_left_out[5] ) , .p0 ( optlc_net_82 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_11 mux_left_track_13 ( - .in ( { chany_bottom_in[5] , left_bottom_grid_pin_35_[0] } ) , - .sram ( mux_tree_tapbuf_size2_11_sram ) , - .sram_inv ( mux_left_track_13_undriven_sram_inv ) , - .out ( chanx_left_out[6] ) , .p0 ( optlc_net_83 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_12 mux_left_track_15 ( - .in ( { chany_bottom_in[6] , left_bottom_grid_pin_36_[0] } ) , - .sram ( mux_tree_tapbuf_size2_12_sram ) , - .sram_inv ( mux_left_track_15_undriven_sram_inv ) , - .out ( chanx_left_out[7] ) , .p0 ( optlc_net_83 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_13 mux_left_track_17 ( - .in ( { chany_bottom_in[7] , left_bottom_grid_pin_37_[0] } ) , - .sram ( mux_tree_tapbuf_size2_13_sram ) , - .sram_inv ( mux_left_track_17_undriven_sram_inv ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_83 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_14 mux_left_track_19 ( - .in ( { chany_bottom_in[8] , left_bottom_grid_pin_38_[0] } ) , - .sram ( mux_tree_tapbuf_size2_14_sram ) , - .sram_inv ( mux_left_track_19_undriven_sram_inv ) , - .out ( chanx_left_out[9] ) , .p0 ( optlc_net_83 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_15 mux_left_track_21 ( - .in ( { chany_bottom_in[9] , left_bottom_grid_pin_39_[0] } ) , - .sram ( mux_tree_tapbuf_size2_15_sram ) , - .sram_inv ( mux_left_track_21_undriven_sram_inv ) , - .out ( chanx_left_out[10] ) , .p0 ( optlc_net_82 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_16 mux_left_track_23 ( - .in ( { chany_bottom_in[10] , left_bottom_grid_pin_40_[0] } ) , - .sram ( mux_tree_tapbuf_size2_16_sram ) , - .sram_inv ( mux_left_track_23_undriven_sram_inv ) , - .out ( chanx_left_out[11] ) , .p0 ( optlc_net_82 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_17 mux_left_track_27 ( - .in ( { chany_bottom_in[12] , left_bottom_grid_pin_34_[0] } ) , - .sram ( mux_tree_tapbuf_size2_17_sram ) , - .sram_inv ( mux_left_track_27_undriven_sram_inv ) , - .out ( chanx_left_out[13] ) , .p0 ( optlc_net_82 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_18 mux_left_track_29 ( - .in ( { chany_bottom_in[13] , left_bottom_grid_pin_35_[0] } ) , - .sram ( mux_tree_tapbuf_size2_18_sram ) , - .sram_inv ( mux_left_track_29_undriven_sram_inv ) , - .out ( chanx_left_out[14] ) , .p0 ( optlc_net_82 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_19 mux_left_track_31 ( - .in ( { chany_bottom_in[14] , left_bottom_grid_pin_36_[0] } ) , - .sram ( mux_tree_tapbuf_size2_19_sram ) , - .sram_inv ( mux_left_track_31_undriven_sram_inv ) , - .out ( chanx_left_out[15] ) , .p0 ( optlc_net_83 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_20 mux_left_track_33 ( - .in ( { chany_bottom_in[15] , left_bottom_grid_pin_37_[0] } ) , - .sram ( mux_tree_tapbuf_size2_20_sram ) , - .sram_inv ( mux_left_track_33_undriven_sram_inv ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_83 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_21 mux_left_track_35 ( - .in ( { chany_bottom_in[16] , left_bottom_grid_pin_38_[0] } ) , - .sram ( mux_tree_tapbuf_size2_21_sram ) , - .sram_inv ( mux_left_track_35_undriven_sram_inv ) , - .out ( chanx_left_out[17] ) , .p0 ( optlc_net_81 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_22 mux_left_track_37 ( - .in ( { chany_bottom_in[17] , left_bottom_grid_pin_39_[0] } ) , - .sram ( mux_tree_tapbuf_size2_22_sram ) , - .sram_inv ( mux_left_track_37_undriven_sram_inv ) , - .out ( chanx_left_out[18] ) , .p0 ( optlc_net_83 ) ) ; -sb_2__2__mux_tree_tapbuf_size2 mux_left_track_39 ( - .in ( { chany_bottom_in[18] , left_bottom_grid_pin_40_[0] } ) , - .sram ( mux_tree_tapbuf_size2_23_sram ) , - .sram_inv ( mux_left_track_39_undriven_sram_inv ) , - .out ( chanx_left_out[19] ) , .p0 ( optlc_net_82 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_9 mem_bottom_track_9 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_0 mem_bottom_track_11 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_1 mem_bottom_track_13 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_2 mem_bottom_track_15 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_3 mem_bottom_track_17 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_4 mem_bottom_track_19 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_5 mem_bottom_track_21 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_6 mem_bottom_track_23 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_7 mem_bottom_track_27 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_8 mem_bottom_track_29 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_10 mem_left_track_11 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_11 mem_left_track_13 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_11_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_12 mem_left_track_15 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_12_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_13 mem_left_track_17 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_13_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_14 mem_left_track_19 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_14_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_15 mem_left_track_21 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_15_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_16 mem_left_track_23 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_16_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_17 mem_left_track_27 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_17_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_18 mem_left_track_29 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_18_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_19 mem_left_track_31 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_19_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_20 mem_left_track_33 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_20_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_21 mem_left_track_35 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_21_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_22 mem_left_track_37 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_22_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem mem_left_track_39 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , - .ccff_tail ( { ropt_net_91 } ) , - .mem_out ( mux_tree_tapbuf_size2_23_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size3_0 mux_bottom_track_25 ( - .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_49_[0] , - chanx_left_in[13] } ) , - .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_bottom_track_25_undriven_sram_inv ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_84 ) ) ; -sb_2__2__mux_tree_tapbuf_size3 mux_left_track_9 ( - .in ( { chany_bottom_in[3] , left_top_grid_pin_1_[0] , - left_bottom_grid_pin_41_[0] } ) , - .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_left_track_9_undriven_sram_inv ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_82 ) ) ; -sb_2__2__mux_tree_tapbuf_size3_1 mux_left_track_25 ( - .in ( { chany_bottom_in[11] , left_top_grid_pin_1_[0] , - left_bottom_grid_pin_41_[0] } ) , - .sram ( mux_tree_tapbuf_size3_2_sram ) , - .sram_inv ( mux_left_track_25_undriven_sram_inv ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_82 ) ) ; -sb_2__2__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_25 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size3_mem mem_left_track_9 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size3_mem_1 mem_left_track_25 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_688 ( .A ( ropt_net_94 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_689 ( .A ( ropt_net_95 ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_690 ( .A ( ropt_net_96 ) , - .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__conb_1 optlc_72 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_81 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__4 ( .A ( chanx_left_in[19] ) , - .X ( ropt_net_92 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_6__5 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_86 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_691 ( .A ( ropt_net_97 ) , - .X ( chany_bottom_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_692 ( .A ( ropt_net_98 ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_693 ( .A ( ropt_net_99 ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_694 ( .A ( ropt_net_100 ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_74 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_82 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_76 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_83 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_78 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_84 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_681 ( .A ( ropt_net_86 ) , - .X ( ropt_net_96 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_682 ( .A ( chanx_left_in[0] ) , - .X ( ropt_net_98 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_683 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_100 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_684 ( .A ( chanx_left_in[16] ) , - .X ( ropt_net_99 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_685 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_97 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_686 ( .A ( ropt_net_91 ) , - .X ( ropt_net_94 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_687 ( .A ( ropt_net_92 ) , - .X ( ropt_net_95 ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__60 ( .A ( mem_out[1] ) , - .X ( net_net_79 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_78 ( .A ( net_net_79 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__59 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__58 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__57 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__56 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__55 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__const1 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__1__const1 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__1__const1_31 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__1__const1_31 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__1__const1_30 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__1__const1_30 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__1__const1_29 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__1__const1_29 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__1__const1_28 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__1__const1_28 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__1__const1_27 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__1__const1_27 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__54 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__53 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__52 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__51 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__50 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__const1_26 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sb_2__1__const1_26 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_2__1__const1_25 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sb_2__1__const1_25 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_2__1__const1_24 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sb_2__1__const1_24 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_2__1__const1_23 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sb_2__1__const1_23 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_2__1__const1_22 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sb_2__1__const1_22 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_67 ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__49 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__48 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__47 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__46 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__const1_21 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sb_2__1__const1_21 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -endmodule - - -module sb_2__1__const1_20 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sb_2__1__const1_20 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_65 ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( BUF_net_65 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_107 ( .A ( BUF_net_65 ) , - .X ( out[0] ) ) ; -endmodule - - -module sb_2__1__const1_19 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sb_2__1__const1_19 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -endmodule - - -module sb_2__1__const1_18 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sb_2__1__const1_18 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size9_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__45 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__const1_17 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , p0 ) ; -input [0:8] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; - -sb_2__1__const1_17 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_106 ( - .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__44 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__43 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__42 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__const1_16 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sb_2__1__const1_16 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module sb_2__1__const1_15 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sb_2__1__const1_15 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module sb_2__1__const1_14 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sb_2__1__const1_14 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__41 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__40 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__39 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__38 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__37 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__36 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__35 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__const1_13 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sb_2__1__const1_13 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_2__1__const1_12 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sb_2__1__const1_12 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_2__1__const1_11 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sb_2__1__const1_11 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_2__1__const1_10 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sb_2__1__const1_10 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_2__1__const1_9 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sb_2__1__const1_9 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_2__1__const1_8 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sb_2__1__const1_8 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_2__1__const1_7 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sb_2__1__const1_7 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size14_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__34 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size14_mem ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__33 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__const1_6 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size14_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:13] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sb_2__1__const1_6 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; -endmodule - - -module sb_2__1__const1_5 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size14 ( in , sram , sram_inv , out , p0 ) ; -input [0:13] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sb_2__1__const1_5 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__32 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__31 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__30 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__const1_4 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sb_2__1__const1_4 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module sb_2__1__const1_3 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sb_2__1__const1_3 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module sb_2__1__const1_2 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sb_2__1__const1_2 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__29 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__28 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__const1_1 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sb_2__1__const1_1 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module sb_2__1__const1_0 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sb_2__1__const1_0 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module sb_2__1_ ( prog_clk , chany_top_in , top_left_grid_pin_42_ , - top_left_grid_pin_43_ , top_left_grid_pin_44_ , top_left_grid_pin_45_ , - top_left_grid_pin_46_ , top_left_grid_pin_47_ , top_left_grid_pin_48_ , - top_left_grid_pin_49_ , top_right_grid_pin_1_ , chany_bottom_in , - bottom_right_grid_pin_1_ , bottom_left_grid_pin_42_ , - bottom_left_grid_pin_43_ , bottom_left_grid_pin_44_ , - bottom_left_grid_pin_45_ , bottom_left_grid_pin_46_ , - bottom_left_grid_pin_47_ , bottom_left_grid_pin_48_ , - bottom_left_grid_pin_49_ , chanx_left_in , left_bottom_grid_pin_34_ , - left_bottom_grid_pin_35_ , left_bottom_grid_pin_36_ , - left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , - left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , - left_bottom_grid_pin_41_ , ccff_head , chany_top_out , chany_bottom_out , - chanx_left_out , ccff_tail , Test_en__FEEDTHRU_0 , Test_en__FEEDTHRU_1 , - clk__FEEDTHRU_0 , clk__FEEDTHRU_1 ) ; -input [0:0] prog_clk ; -input [0:19] chany_top_in ; -input [0:0] top_left_grid_pin_42_ ; -input [0:0] top_left_grid_pin_43_ ; -input [0:0] top_left_grid_pin_44_ ; -input [0:0] top_left_grid_pin_45_ ; -input [0:0] top_left_grid_pin_46_ ; -input [0:0] top_left_grid_pin_47_ ; -input [0:0] top_left_grid_pin_48_ ; -input [0:0] top_left_grid_pin_49_ ; -input [0:0] top_right_grid_pin_1_ ; -input [0:19] chany_bottom_in ; -input [0:0] bottom_right_grid_pin_1_ ; -input [0:0] bottom_left_grid_pin_42_ ; -input [0:0] bottom_left_grid_pin_43_ ; -input [0:0] bottom_left_grid_pin_44_ ; -input [0:0] bottom_left_grid_pin_45_ ; -input [0:0] bottom_left_grid_pin_46_ ; -input [0:0] bottom_left_grid_pin_47_ ; -input [0:0] bottom_left_grid_pin_48_ ; -input [0:0] bottom_left_grid_pin_49_ ; -input [0:19] chanx_left_in ; -input [0:0] left_bottom_grid_pin_34_ ; -input [0:0] left_bottom_grid_pin_35_ ; -input [0:0] left_bottom_grid_pin_36_ ; -input [0:0] left_bottom_grid_pin_37_ ; -input [0:0] left_bottom_grid_pin_38_ ; -input [0:0] left_bottom_grid_pin_39_ ; -input [0:0] left_bottom_grid_pin_40_ ; -input [0:0] left_bottom_grid_pin_41_ ; -input [0:0] ccff_head ; -output [0:19] chany_top_out ; -output [0:19] chany_bottom_out ; -output [0:19] chanx_left_out ; -output [0:0] ccff_tail ; -input [0:0] Test_en__FEEDTHRU_0 ; -output [0:0] Test_en__FEEDTHRU_1 ; -input [0:0] clk__FEEDTHRU_0 ; -output [0:0] clk__FEEDTHRU_1 ; - -wire [0:2] mux_bottom_track_17_undriven_sram_inv ; -wire [0:3] mux_bottom_track_1_undriven_sram_inv ; -wire [0:2] mux_bottom_track_25_undriven_sram_inv ; -wire [0:2] mux_bottom_track_33_undriven_sram_inv ; -wire [0:3] mux_bottom_track_3_undriven_sram_inv ; -wire [0:3] mux_bottom_track_5_undriven_sram_inv ; -wire [0:3] mux_bottom_track_9_undriven_sram_inv ; -wire [0:2] mux_left_track_11_undriven_sram_inv ; -wire [0:2] mux_left_track_13_undriven_sram_inv ; -wire [0:2] mux_left_track_15_undriven_sram_inv ; -wire [0:1] mux_left_track_17_undriven_sram_inv ; -wire [0:1] mux_left_track_19_undriven_sram_inv ; -wire [0:2] mux_left_track_1_undriven_sram_inv ; -wire [0:1] mux_left_track_21_undriven_sram_inv ; -wire [0:1] mux_left_track_23_undriven_sram_inv ; -wire [0:1] mux_left_track_25_undriven_sram_inv ; -wire [0:1] mux_left_track_29_undriven_sram_inv ; -wire [0:1] mux_left_track_31_undriven_sram_inv ; -wire [0:1] mux_left_track_33_undriven_sram_inv ; -wire [0:1] mux_left_track_35_undriven_sram_inv ; -wire [0:1] mux_left_track_37_undriven_sram_inv ; -wire [0:1] mux_left_track_39_undriven_sram_inv ; -wire [0:2] mux_left_track_3_undriven_sram_inv ; -wire [0:2] mux_left_track_5_undriven_sram_inv ; -wire [0:2] mux_left_track_7_undriven_sram_inv ; -wire [0:2] mux_left_track_9_undriven_sram_inv ; -wire [0:3] mux_top_track_0_undriven_sram_inv ; -wire [0:2] mux_top_track_16_undriven_sram_inv ; -wire [0:2] mux_top_track_24_undriven_sram_inv ; -wire [0:3] mux_top_track_2_undriven_sram_inv ; -wire [0:2] mux_top_track_32_undriven_sram_inv ; -wire [0:3] mux_top_track_4_undriven_sram_inv ; -wire [0:3] mux_top_track_8_undriven_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size14_0_sram ; -wire [0:3] mux_tree_tapbuf_size14_1_sram ; -wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail ; -wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_5_sram ; -wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; -wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:1] mux_tree_tapbuf_size3_2_sram ; -wire [0:1] mux_tree_tapbuf_size3_3_sram ; -wire [0:1] mux_tree_tapbuf_size3_4_sram ; -wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size4_0_sram ; -wire [0:2] mux_tree_tapbuf_size4_1_sram ; -wire [0:2] mux_tree_tapbuf_size4_2_sram ; -wire [0:2] mux_tree_tapbuf_size4_3_sram ; -wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size6_1_sram ; -wire [0:2] mux_tree_tapbuf_size6_2_sram ; -wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size7_0_sram ; -wire [0:2] mux_tree_tapbuf_size7_1_sram ; -wire [0:2] mux_tree_tapbuf_size7_2_sram ; -wire [0:2] mux_tree_tapbuf_size7_3_sram ; -wire [0:2] mux_tree_tapbuf_size7_4_sram ; -wire [0:2] mux_tree_tapbuf_size7_5_sram ; -wire [0:2] mux_tree_tapbuf_size7_6_sram ; -wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:3] mux_tree_tapbuf_size8_2_sram ; -wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size9_0_sram ; -wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ; - -assign clk__FEEDTHRU_1[0] = clk__FEEDTHRU_0[0] ; - -sb_2__1__mux_tree_tapbuf_size10 mux_top_track_0 ( - .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , - top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , - top_right_grid_pin_1_[0] , chany_bottom_in[2] , chany_bottom_in[12] , - chanx_left_in[0] , chanx_left_in[7] , chanx_left_in[14] } ) , - .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_top_track_0_undriven_sram_inv ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_126 ) ) ; -sb_2__1__mux_tree_tapbuf_size10_0 mux_bottom_track_1 ( - .in ( { chany_top_in[2] , chany_top_in[12] , bottom_right_grid_pin_1_[0] , - bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , - bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , - chanx_left_in[1] , chanx_left_in[8] , chanx_left_in[15] } ) , - .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_bottom_track_1_undriven_sram_inv ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_126 ) ) ; -sb_2__1__mux_tree_tapbuf_size10_mem mem_top_track_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size10_mem_0 mem_bottom_track_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size8_1 mux_top_track_2 ( - .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , - top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , - chany_bottom_in[4] , chany_bottom_in[13] , chanx_left_in[6] , - chanx_left_in[13] } ) , - .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_top_track_2_undriven_sram_inv ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_127 ) ) ; -sb_2__1__mux_tree_tapbuf_size8 mux_top_track_8 ( - .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_46_[0] , - top_right_grid_pin_1_[0] , chany_bottom_in[6] , chany_bottom_in[16] , - chanx_left_in[4] , chanx_left_in[11] , chanx_left_in[18] } ) , - .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_top_track_8_undriven_sram_inv ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_127 ) ) ; -sb_2__1__mux_tree_tapbuf_size8_0 mux_bottom_track_9 ( - .in ( { chany_top_in[6] , chany_top_in[16] , bottom_right_grid_pin_1_[0] , - bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_49_[0] , - chanx_left_in[4] , chanx_left_in[11] , chanx_left_in[18] } ) , - .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_bottom_track_9_undriven_sram_inv ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_125 ) ) ; -sb_2__1__mux_tree_tapbuf_size8_mem_1 mem_top_track_2 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size8_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size8_mem_0 mem_bottom_track_9 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size14 mux_top_track_4 ( - .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_43_[0] , - top_left_grid_pin_44_[0] , top_left_grid_pin_45_[0] , - top_left_grid_pin_46_[0] , top_left_grid_pin_47_[0] , - top_left_grid_pin_48_[0] , top_left_grid_pin_49_[0] , - top_right_grid_pin_1_[0] , chany_bottom_in[5] , chany_bottom_in[14] , - chanx_left_in[5] , chanx_left_in[12] , chanx_left_in[19] } ) , - .sram ( mux_tree_tapbuf_size14_0_sram ) , - .sram_inv ( mux_top_track_4_undriven_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_127 ) ) ; -sb_2__1__mux_tree_tapbuf_size14_0 mux_bottom_track_5 ( - .in ( { chany_top_in[5] , chany_top_in[14] , bottom_right_grid_pin_1_[0] , - bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_43_[0] , - bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_45_[0] , - bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_47_[0] , - bottom_left_grid_pin_48_[0] , bottom_left_grid_pin_49_[0] , - chanx_left_in[3] , chanx_left_in[10] , chanx_left_in[17] } ) , - .sram ( mux_tree_tapbuf_size14_1_sram ) , - .sram_inv ( mux_bottom_track_5_undriven_sram_inv ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_125 ) ) ; -sb_2__1__mux_tree_tapbuf_size14_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size14_0_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size14_mem_0 mem_bottom_track_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size14_1_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size7_5 mux_top_track_16 ( - .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_47_[0] , - chany_bottom_in[8] , chany_bottom_in[17] , chanx_left_in[3] , - chanx_left_in[10] , chanx_left_in[17] } ) , - .sram ( mux_tree_tapbuf_size7_0_sram ) , - .sram_inv ( mux_top_track_16_undriven_sram_inv ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_126 ) ) ; -sb_2__1__mux_tree_tapbuf_size7 mux_top_track_24 ( - .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_48_[0] , - chany_bottom_in[9] , chany_bottom_in[18] , chanx_left_in[2] , - chanx_left_in[9] , chanx_left_in[16] } ) , - .sram ( mux_tree_tapbuf_size7_1_sram ) , - .sram_inv ( mux_top_track_24_undriven_sram_inv ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_126 ) ) ; -sb_2__1__mux_tree_tapbuf_size7_0 mux_bottom_track_17 ( - .in ( { chany_top_in[8] , chany_top_in[17] , bottom_left_grid_pin_42_[0] , - bottom_left_grid_pin_46_[0] , chanx_left_in[5] , chanx_left_in[12] , - chanx_left_in[19] } ) , - .sram ( mux_tree_tapbuf_size7_2_sram ) , - .sram_inv ( mux_bottom_track_17_undriven_sram_inv ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_126 ) ) ; -sb_2__1__mux_tree_tapbuf_size7_1 mux_left_track_1 ( - .in ( { chany_top_in[0] , chany_top_in[2] , chany_bottom_in[2] , - left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , - left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , - .sram ( mux_tree_tapbuf_size7_3_sram ) , - .sram_inv ( mux_left_track_1_undriven_sram_inv ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_128 ) ) ; -sb_2__1__mux_tree_tapbuf_size7_2 mux_left_track_3 ( - .in ( { chany_top_in[4] , chany_bottom_in[0] , chany_bottom_in[4] , - left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , - left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , - .sram ( mux_tree_tapbuf_size7_4_sram ) , - .sram_inv ( mux_left_track_3_undriven_sram_inv ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_128 ) ) ; -sb_2__1__mux_tree_tapbuf_size7_3 mux_left_track_5 ( - .in ( { chany_top_in[5] , chany_bottom_in[1] , chany_bottom_in[5] , - left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , - left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , - .sram ( mux_tree_tapbuf_size7_5_sram ) , - .sram_inv ( mux_left_track_5_undriven_sram_inv ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_128 ) ) ; -sb_2__1__mux_tree_tapbuf_size7_4 mux_left_track_7 ( - .in ( { chany_top_in[6] , chany_bottom_in[3] , chany_bottom_in[6] , - left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , - left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , - .sram ( mux_tree_tapbuf_size7_6_sram ) , - .sram_inv ( mux_left_track_7_undriven_sram_inv ) , - .out ( chanx_left_out[3] ) , .p0 ( optlc_net_128 ) ) ; -sb_2__1__mux_tree_tapbuf_size7_mem_5 mem_top_track_16 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size7_mem mem_top_track_24 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size7_mem_0 mem_bottom_track_17 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size7_mem_1 mem_left_track_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_3_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size7_mem_2 mem_left_track_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_4_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size7_mem_3 mem_left_track_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_5_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size7_mem_4 mem_left_track_7 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_6_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size6 mux_top_track_32 ( - .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_49_[0] , - chany_bottom_in[10] , chanx_left_in[1] , chanx_left_in[8] , - chanx_left_in[15] } ) , - .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_top_track_32_undriven_sram_inv ) , - .out ( chany_top_out[16] ) , .p0 ( optlc_net_126 ) ) ; -sb_2__1__mux_tree_tapbuf_size6_0 mux_bottom_track_25 ( - .in ( { chany_top_in[9] , chany_top_in[18] , bottom_left_grid_pin_43_[0] , - bottom_left_grid_pin_47_[0] , chanx_left_in[6] , chanx_left_in[13] } ) , - .sram ( mux_tree_tapbuf_size6_1_sram ) , - .sram_inv ( mux_bottom_track_25_undriven_sram_inv ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_125 ) ) ; -sb_2__1__mux_tree_tapbuf_size6_1 mux_bottom_track_33 ( - .in ( { chany_top_in[10] , bottom_left_grid_pin_44_[0] , - bottom_left_grid_pin_48_[0] , chanx_left_in[0] , chanx_left_in[7] , - chanx_left_in[14] } ) , - .sram ( mux_tree_tapbuf_size6_2_sram ) , - .sram_inv ( mux_bottom_track_33_undriven_sram_inv ) , - .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_126 ) ) ; -sb_2__1__mux_tree_tapbuf_size6_mem mem_top_track_32 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_25 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size6_mem_1 mem_bottom_track_33 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_2_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size9 mux_bottom_track_3 ( - .in ( { chany_top_in[4] , chany_top_in[13] , bottom_left_grid_pin_42_[0] , - bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , - bottom_left_grid_pin_48_[0] , chanx_left_in[2] , chanx_left_in[9] , - chanx_left_in[16] } ) , - .sram ( mux_tree_tapbuf_size9_0_sram ) , - .sram_inv ( mux_bottom_track_3_undriven_sram_inv ) , - .out ( { ropt_net_132 } ) , - .p0 ( optlc_net_125 ) ) ; -sb_2__1__mux_tree_tapbuf_size9_mem mem_bottom_track_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size9_0_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size4 mux_left_track_9 ( - .in ( { chany_top_in[8] , chany_bottom_in[7] , chany_bottom_in[8] , - left_bottom_grid_pin_34_[0] } ) , - .sram ( mux_tree_tapbuf_size4_0_sram ) , - .sram_inv ( mux_left_track_9_undriven_sram_inv ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_128 ) ) ; -sb_2__1__mux_tree_tapbuf_size4_0 mux_left_track_11 ( - .in ( { chany_top_in[9] , chany_bottom_in[9] , chany_bottom_in[11] , - left_bottom_grid_pin_35_[0] } ) , - .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_left_track_11_undriven_sram_inv ) , - .out ( chanx_left_out[5] ) , .p0 ( optlc_net_128 ) ) ; -sb_2__1__mux_tree_tapbuf_size4_1 mux_left_track_13 ( - .in ( { chany_top_in[10] , chany_bottom_in[10] , chany_bottom_in[15] , - left_bottom_grid_pin_36_[0] } ) , - .sram ( mux_tree_tapbuf_size4_2_sram ) , - .sram_inv ( mux_left_track_13_undriven_sram_inv ) , - .out ( { ropt_net_130 } ) , - .p0 ( optlc_net_125 ) ) ; -sb_2__1__mux_tree_tapbuf_size4_2 mux_left_track_15 ( - .in ( { chany_top_in[12] , chany_bottom_in[12] , chany_bottom_in[19] , - left_bottom_grid_pin_37_[0] } ) , - .sram ( mux_tree_tapbuf_size4_3_sram ) , - .sram_inv ( mux_left_track_15_undriven_sram_inv ) , - .out ( chanx_left_out[7] ) , .p0 ( optlc_net_125 ) ) ; -sb_2__1__mux_tree_tapbuf_size4_mem mem_left_track_9 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size4_mem_0 mem_left_track_11 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size4_mem_1 mem_left_track_13 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size4_mem_2 mem_left_track_15 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size3_0 mux_left_track_17 ( - .in ( { chany_top_in[13] , chany_bottom_in[13] , - left_bottom_grid_pin_38_[0] } ) , - .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_left_track_17_undriven_sram_inv ) , - .out ( { ropt_net_131 } ) , - .p0 ( optlc_net_125 ) ) ; -sb_2__1__mux_tree_tapbuf_size3_1 mux_left_track_19 ( - .in ( { chany_top_in[14] , chany_bottom_in[14] , - left_bottom_grid_pin_39_[0] } ) , - .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_left_track_19_undriven_sram_inv ) , - .out ( chanx_left_out[9] ) , .p0 ( optlc_net_127 ) ) ; -sb_2__1__mux_tree_tapbuf_size3_2 mux_left_track_21 ( - .in ( { chany_top_in[16] , chany_bottom_in[16] , - left_bottom_grid_pin_40_[0] } ) , - .sram ( mux_tree_tapbuf_size3_2_sram ) , - .sram_inv ( mux_left_track_21_undriven_sram_inv ) , - .out ( chanx_left_out[10] ) , .p0 ( optlc_net_128 ) ) ; -sb_2__1__mux_tree_tapbuf_size3_3 mux_left_track_23 ( - .in ( { chany_top_in[17] , chany_bottom_in[17] , - left_bottom_grid_pin_41_[0] } ) , - .sram ( mux_tree_tapbuf_size3_3_sram ) , - .sram_inv ( mux_left_track_23_undriven_sram_inv ) , - .out ( chanx_left_out[11] ) , .p0 ( optlc_net_127 ) ) ; -sb_2__1__mux_tree_tapbuf_size3 mux_left_track_25 ( - .in ( { chany_top_in[18] , chany_bottom_in[18] , - left_bottom_grid_pin_34_[0] } ) , - .sram ( mux_tree_tapbuf_size3_4_sram ) , - .sram_inv ( mux_left_track_25_undriven_sram_inv ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_128 ) ) ; -sb_2__1__mux_tree_tapbuf_size3_mem_0 mem_left_track_17 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size3_mem_1 mem_left_track_19 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size3_mem_2 mem_left_track_21 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size3_mem_3 mem_left_track_23 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size3_mem mem_left_track_25 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_4_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size2_0 mux_left_track_29 ( - .in ( { chany_top_in[19] , left_bottom_grid_pin_36_[0] } ) , - .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_left_track_29_undriven_sram_inv ) , - .out ( chanx_left_out[14] ) , .p0 ( optlc_net_128 ) ) ; -sb_2__1__mux_tree_tapbuf_size2_1 mux_left_track_31 ( - .in ( { chany_top_in[15] , left_bottom_grid_pin_37_[0] } ) , - .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_left_track_31_undriven_sram_inv ) , - .out ( chanx_left_out[15] ) , .p0 ( optlc_net_127 ) ) ; -sb_2__1__mux_tree_tapbuf_size2_2 mux_left_track_33 ( - .in ( { chany_top_in[11] , left_bottom_grid_pin_38_[0] } ) , - .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_left_track_33_undriven_sram_inv ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_127 ) ) ; -sb_2__1__mux_tree_tapbuf_size2_3 mux_left_track_35 ( - .in ( { chany_top_in[7] , left_bottom_grid_pin_39_[0] } ) , - .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_left_track_35_undriven_sram_inv ) , - .out ( chanx_left_out[17] ) , .p0 ( optlc_net_127 ) ) ; -sb_2__1__mux_tree_tapbuf_size2_4 mux_left_track_37 ( - .in ( { chany_top_in[3] , left_bottom_grid_pin_40_[0] } ) , - .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_left_track_37_undriven_sram_inv ) , - .out ( chanx_left_out[18] ) , .p0 ( optlc_net_127 ) ) ; -sb_2__1__mux_tree_tapbuf_size2 mux_left_track_39 ( - .in ( { chany_top_in[1] , left_bottom_grid_pin_41_[0] } ) , - .sram ( mux_tree_tapbuf_size2_5_sram ) , - .sram_inv ( mux_left_track_39_undriven_sram_inv ) , - .out ( chanx_left_out[19] ) , .p0 ( optlc_net_127 ) ) ; -sb_2__1__mux_tree_tapbuf_size2_mem_0 mem_left_track_29 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size2_mem_1 mem_left_track_31 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size2_mem_2 mem_left_track_33 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size2_mem_3 mem_left_track_35 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size2_mem_4 mem_left_track_37 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size2_mem mem_left_track_39 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .ccff_tail ( { ropt_net_134 } ) , - .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; -sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_125 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_126 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_154 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__3 ( .A ( chany_top_in[6] ) , - .X ( ropt_net_145 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_120 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_127 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chany_top_in[9] ) , - .X ( ropt_net_156 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__6 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_153 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__7 ( .A ( chany_top_in[12] ) , - .X ( ropt_net_151 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_122 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_128 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chany_top_in[14] ) , - .X ( ropt_net_150 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chany_top_in[16] ) , - .X ( ropt_net_149 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( chany_top_in[17] ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__12 ( .A ( chany_top_in[18] ) , - .X ( ropt_net_148 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chany_bottom_in[2] ) , - .X ( ropt_net_146 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__14 ( .A ( chany_bottom_in[4] ) , - .X ( ropt_net_142 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__15 ( .A ( chany_bottom_in[5] ) , - .X ( ropt_net_144 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__16 ( .A ( chany_bottom_in[6] ) , - .X ( aps_rename_1_ ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_130 ) , - .X ( ropt_net_168 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( ropt_net_131 ) , - .X ( chanx_left_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_132 ) , - .X ( ropt_net_169 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__20 ( .A ( chany_bottom_in[12] ) , - .X ( ropt_net_158 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_161 ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_23__22 ( .A ( chany_bottom_in[14] ) , - .X ( ropt_net_139 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_162 ) , - .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_25__24 ( .A ( chany_bottom_in[17] ) , - .X ( ropt_net_143 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_26__25 ( .A ( chany_bottom_in[18] ) , - .X ( ropt_net_155 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_163 ) , - .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_133 ) , - .X ( ropt_net_173 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_759 ( .A ( ropt_net_164 ) , - .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_165 ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_166 ) , - .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( ropt_net_134 ) , - .X ( ropt_net_180 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( - .A ( chany_bottom_in[16] ) , .X ( ropt_net_182 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( - .A ( chany_bottom_in[13] ) , .X ( ropt_net_181 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( chany_top_in[13] ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_167 ) , - .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_763 ( .A ( ropt_net_168 ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_77 ( - .A ( left_bottom_grid_pin_35_[0] ) , .X ( ropt_net_133 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_81 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_157 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( chany_top_in[8] ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_766 ( .A ( ropt_net_169 ) , - .X ( chany_bottom_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_139 ) , - .X ( ropt_net_161 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_140 ) , - .X ( ropt_net_164 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( chany_bottom_in[8] ) , - .X ( ropt_net_166 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( ropt_net_170 ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_98 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_183 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_99 ( .A ( chany_top_in[4] ) , - .X ( ropt_net_140 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_100 ( .A ( Test_en__FEEDTHRU_0[0] ) , - .X ( ropt_net_152 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( ropt_net_142 ) , - .X ( ropt_net_167 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_103 ( .A ( aps_rename_1_ ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_769 ( .A ( ropt_net_171 ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_143 ) , - .X ( ropt_net_177 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_144 ) , - .X ( ropt_net_176 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_145 ) , - .X ( ropt_net_163 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_742 ( .A ( ropt_net_146 ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_172 ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_113 ( .A ( chany_bottom_in[10] ) , - .X ( ropt_net_147 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_147 ) , - .X ( ropt_net_162 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_148 ) , - .X ( ropt_net_174 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_149 ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_150 ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( ropt_net_151 ) , - .X ( ropt_net_171 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_152 ) , - .X ( ropt_net_178 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( .A ( ropt_net_153 ) , - .X ( ropt_net_179 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_154 ) , - .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_155 ) , - .X ( ropt_net_175 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_156 ) , - .X ( ropt_net_165 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_157 ) , - .X ( ropt_net_170 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_158 ) , - .X ( ropt_net_172 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_771 ( .A ( ropt_net_173 ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_772 ( .A ( ropt_net_174 ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_773 ( .A ( ropt_net_175 ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_774 ( .A ( ropt_net_176 ) , - .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( ropt_net_177 ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( ropt_net_178 ) , - .X ( Test_en__FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( ropt_net_179 ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_180 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_181 ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_182 ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_183 ) , - .X ( chany_bottom_out[3] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__39 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__38 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__37 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__36 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__const1 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sb_2__0__const1 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -endmodule - - -module sb_2__0__const1_28 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sb_2__0__const1_28 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -endmodule - - -module sb_2__0__const1_27 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sb_2__0__const1_27 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -endmodule - - -module sb_2__0__const1_26 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sb_2__0__const1_26 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__35 ( .A ( mem_out[1] ) , - .X ( net_net_64 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_64 ( .A ( net_net_64 ) , - .X ( net_net_63 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_92 ( .A ( net_net_63 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__34 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__33 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__32 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__31 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__30 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__29 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__28 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__27 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__26 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__25 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__24 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__23 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_18 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__22 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_17 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__21 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__20 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__19 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__18 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__17 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__16 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__const1_25 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -sb_2__0__const1_25 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_2__0__const1_24 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__0__const1_24 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__0__const1_23 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__0__const1_23 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__0__const1_22 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__0__const1_22 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_51 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_2__0__const1_21 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -sb_2__0__const1_21 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_2__0__const1_20 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__0__const1_20 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__0__const1_19 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -sb_2__0__const1_19 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_2__0__const1_18 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -sb_2__0__const1_18 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_2__0__const1_17 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__0__const1_17 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__0__const1_16 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__0__const1_16 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__0__const1_15 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__0__const1_15 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__0__const1_14 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__0__const1_14 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__0__const1_13 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__0__const1_13 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__0__const1_12 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__0__const1_12 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__0__const1_11 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__0__const1_11 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__0__const1_10 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__0__const1_10 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__0__const1_9 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__0__const1_9 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__0__const1_8 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__0__const1_8 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__0__const1_7 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__0__const1_7 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__0__const1_6 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__0__const1_6 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__15 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__14 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__const1_5 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sb_2__0__const1_5 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_2__0__const1_4 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sb_2__0__const1_4 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__13 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__12 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__const1_3 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -sb_2__0__const1_3 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -endmodule - - -module sb_2__0__const1_2 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -sb_2__0__const1_2 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__11 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__10 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__const1_1 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sb_2__0__const1_1 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module sb_2__0__const1_0 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sb_2__0__const1_0 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module sb_2__0_ ( prog_clk , chany_top_in , top_left_grid_pin_42_ , - top_left_grid_pin_43_ , top_left_grid_pin_44_ , top_left_grid_pin_45_ , - top_left_grid_pin_46_ , top_left_grid_pin_47_ , top_left_grid_pin_48_ , - top_left_grid_pin_49_ , top_right_grid_pin_1_ , chanx_left_in , - left_bottom_grid_pin_1_ , left_bottom_grid_pin_3_ , - left_bottom_grid_pin_5_ , left_bottom_grid_pin_7_ , - left_bottom_grid_pin_9_ , left_bottom_grid_pin_11_ , ccff_head , - chany_top_out , chanx_left_out , ccff_tail ) ; -input [0:0] prog_clk ; -input [0:19] chany_top_in ; -input [0:0] top_left_grid_pin_42_ ; -input [0:0] top_left_grid_pin_43_ ; -input [0:0] top_left_grid_pin_44_ ; -input [0:0] top_left_grid_pin_45_ ; -input [0:0] top_left_grid_pin_46_ ; -input [0:0] top_left_grid_pin_47_ ; -input [0:0] top_left_grid_pin_48_ ; -input [0:0] top_left_grid_pin_49_ ; -input [0:0] top_right_grid_pin_1_ ; -input [0:19] chanx_left_in ; -input [0:0] left_bottom_grid_pin_1_ ; -input [0:0] left_bottom_grid_pin_3_ ; -input [0:0] left_bottom_grid_pin_5_ ; -input [0:0] left_bottom_grid_pin_7_ ; -input [0:0] left_bottom_grid_pin_9_ ; -input [0:0] left_bottom_grid_pin_11_ ; -input [0:0] ccff_head ; -output [0:19] chany_top_out ; -output [0:19] chanx_left_out ; -output [0:0] ccff_tail ; - -wire [0:1] mux_left_track_11_undriven_sram_inv ; -wire [0:1] mux_left_track_13_undriven_sram_inv ; -wire [0:1] mux_left_track_15_undriven_sram_inv ; -wire [0:1] mux_left_track_17_undriven_sram_inv ; -wire [0:1] mux_left_track_19_undriven_sram_inv ; -wire [0:2] mux_left_track_1_undriven_sram_inv ; -wire [0:1] mux_left_track_25_undriven_sram_inv ; -wire [0:1] mux_left_track_27_undriven_sram_inv ; -wire [0:1] mux_left_track_29_undriven_sram_inv ; -wire [0:1] mux_left_track_31_undriven_sram_inv ; -wire [0:1] mux_left_track_33_undriven_sram_inv ; -wire [0:1] mux_left_track_35_undriven_sram_inv ; -wire [0:2] mux_left_track_3_undriven_sram_inv ; -wire [0:2] mux_left_track_5_undriven_sram_inv ; -wire [0:2] mux_left_track_7_undriven_sram_inv ; -wire [0:1] mux_left_track_9_undriven_sram_inv ; -wire [0:2] mux_top_track_0_undriven_sram_inv ; -wire [0:1] mux_top_track_10_undriven_sram_inv ; -wire [0:1] mux_top_track_12_undriven_sram_inv ; -wire [0:1] mux_top_track_14_undriven_sram_inv ; -wire [0:1] mux_top_track_16_undriven_sram_inv ; -wire [0:1] mux_top_track_18_undriven_sram_inv ; -wire [0:1] mux_top_track_20_undriven_sram_inv ; -wire [0:1] mux_top_track_22_undriven_sram_inv ; -wire [0:1] mux_top_track_24_undriven_sram_inv ; -wire [0:1] mux_top_track_26_undriven_sram_inv ; -wire [0:2] mux_top_track_2_undriven_sram_inv ; -wire [0:2] mux_top_track_4_undriven_sram_inv ; -wire [0:2] mux_top_track_6_undriven_sram_inv ; -wire [0:1] mux_top_track_8_undriven_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_10_sram ; -wire [0:1] mux_tree_tapbuf_size2_11_sram ; -wire [0:1] mux_tree_tapbuf_size2_12_sram ; -wire [0:1] mux_tree_tapbuf_size2_13_sram ; -wire [0:1] mux_tree_tapbuf_size2_14_sram ; -wire [0:1] mux_tree_tapbuf_size2_15_sram ; -wire [0:1] mux_tree_tapbuf_size2_16_sram ; -wire [0:1] mux_tree_tapbuf_size2_17_sram ; -wire [0:1] mux_tree_tapbuf_size2_18_sram ; -wire [0:1] mux_tree_tapbuf_size2_19_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_5_sram ; -wire [0:1] mux_tree_tapbuf_size2_6_sram ; -wire [0:1] mux_tree_tapbuf_size2_7_sram ; -wire [0:1] mux_tree_tapbuf_size2_8_sram ; -wire [0:1] mux_tree_tapbuf_size2_9_sram ; -wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; -wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size4_0_sram ; -wire [0:2] mux_tree_tapbuf_size4_1_sram ; -wire [0:2] mux_tree_tapbuf_size4_2_sram ; -wire [0:2] mux_tree_tapbuf_size4_3_sram ; -wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size5_0_sram ; -wire [0:2] mux_tree_tapbuf_size5_1_sram ; -wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size6_1_sram ; -wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; - -sb_2__0__mux_tree_tapbuf_size6_0 mux_top_track_0 ( - .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , - top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , - top_right_grid_pin_1_[0] , chanx_left_in[0] } ) , - .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_top_track_0_undriven_sram_inv ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_120 ) ) ; -sb_2__0__mux_tree_tapbuf_size6 mux_top_track_4 ( - .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , - top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , - top_right_grid_pin_1_[0] , chanx_left_in[18] } ) , - .sram ( mux_tree_tapbuf_size6_1_sram ) , - .sram_inv ( mux_top_track_4_undriven_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_119 ) ) ; -sb_2__0__mux_tree_tapbuf_size6_mem_0 mem_top_track_0 ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size6_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size5_0 mux_top_track_2 ( - .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , - top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , - chanx_left_in[19] } ) , - .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_top_track_2_undriven_sram_inv ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_120 ) ) ; -sb_2__0__mux_tree_tapbuf_size5 mux_top_track_6 ( - .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , - top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , - chanx_left_in[17] } ) , - .sram ( mux_tree_tapbuf_size5_1_sram ) , - .sram_inv ( mux_top_track_6_undriven_sram_inv ) , - .out ( chany_top_out[3] ) , .p0 ( optlc_net_121 ) ) ; -sb_2__0__mux_tree_tapbuf_size5_mem_0 mem_top_track_2 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size5_mem mem_top_track_6 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size3 mux_top_track_8 ( - .in ( { top_left_grid_pin_42_[0] , top_right_grid_pin_1_[0] , - chanx_left_in[16] } ) , - .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_top_track_8_undriven_sram_inv ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_121 ) ) ; -sb_2__0__mux_tree_tapbuf_size3_0 mux_top_track_24 ( - .in ( { top_left_grid_pin_42_[0] , top_right_grid_pin_1_[0] , - chanx_left_in[8] } ) , - .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_top_track_24_undriven_sram_inv ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_119 ) ) ; -sb_2__0__mux_tree_tapbuf_size3_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size3_mem_0 mem_top_track_24 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size2_12 mux_top_track_10 ( - .in ( { top_left_grid_pin_43_[0] , chanx_left_in[15] } ) , - .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_top_track_10_undriven_sram_inv ) , - .out ( chany_top_out[5] ) , .p0 ( optlc_net_119 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_13 mux_top_track_12 ( - .in ( { top_left_grid_pin_44_[0] , chanx_left_in[14] } ) , - .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_top_track_12_undriven_sram_inv ) , - .out ( chany_top_out[6] ) , .p0 ( optlc_net_120 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_14 mux_top_track_14 ( - .in ( { top_left_grid_pin_45_[0] , chanx_left_in[13] } ) , - .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_top_track_14_undriven_sram_inv ) , - .out ( chany_top_out[7] ) , .p0 ( optlc_net_120 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_15 mux_top_track_16 ( - .in ( { top_left_grid_pin_46_[0] , chanx_left_in[12] } ) , - .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_top_track_16_undriven_sram_inv ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_120 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_16 mux_top_track_18 ( - .in ( { top_left_grid_pin_47_[0] , chanx_left_in[11] } ) , - .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_top_track_18_undriven_sram_inv ) , - .out ( chany_top_out[9] ) , .p0 ( optlc_net_121 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_17 mux_top_track_20 ( - .in ( { top_left_grid_pin_48_[0] , chanx_left_in[10] } ) , - .sram ( mux_tree_tapbuf_size2_5_sram ) , - .sram_inv ( mux_top_track_20_undriven_sram_inv ) , - .out ( chany_top_out[10] ) , .p0 ( optlc_net_119 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_18 mux_top_track_22 ( - .in ( { top_left_grid_pin_49_[0] , chanx_left_in[9] } ) , - .sram ( mux_tree_tapbuf_size2_6_sram ) , - .sram_inv ( mux_top_track_22_undriven_sram_inv ) , - .out ( chany_top_out[11] ) , .p0 ( optlc_net_119 ) ) ; -sb_2__0__mux_tree_tapbuf_size2 mux_top_track_26 ( - .in ( { top_left_grid_pin_43_[0] , chanx_left_in[7] } ) , - .sram ( mux_tree_tapbuf_size2_7_sram ) , - .sram_inv ( mux_top_track_26_undriven_sram_inv ) , - .out ( chany_top_out[13] ) , .p0 ( optlc_net_120 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_11 mux_left_track_9 ( - .in ( { chany_top_in[16] , left_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size2_8_sram ) , - .sram_inv ( mux_left_track_9_undriven_sram_inv ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_122 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_0 mux_left_track_11 ( - .in ( { chany_top_in[15] , left_bottom_grid_pin_3_[0] } ) , - .sram ( mux_tree_tapbuf_size2_9_sram ) , - .sram_inv ( mux_left_track_11_undriven_sram_inv ) , - .out ( chanx_left_out[5] ) , .p0 ( optlc_net_120 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_1 mux_left_track_13 ( - .in ( { chany_top_in[14] , left_bottom_grid_pin_5_[0] } ) , - .sram ( mux_tree_tapbuf_size2_10_sram ) , - .sram_inv ( mux_left_track_13_undriven_sram_inv ) , - .out ( chanx_left_out[6] ) , .p0 ( optlc_net_120 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_2 mux_left_track_15 ( - .in ( { chany_top_in[13] , left_bottom_grid_pin_7_[0] } ) , - .sram ( mux_tree_tapbuf_size2_11_sram ) , - .sram_inv ( mux_left_track_15_undriven_sram_inv ) , - .out ( chanx_left_out[7] ) , .p0 ( optlc_net_119 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_3 mux_left_track_17 ( - .in ( { chany_top_in[12] , left_bottom_grid_pin_9_[0] } ) , - .sram ( mux_tree_tapbuf_size2_12_sram ) , - .sram_inv ( mux_left_track_17_undriven_sram_inv ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_121 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_4 mux_left_track_19 ( - .in ( { chany_top_in[11] , left_bottom_grid_pin_11_[0] } ) , - .sram ( mux_tree_tapbuf_size2_13_sram ) , - .sram_inv ( mux_left_track_19_undriven_sram_inv ) , - .out ( chanx_left_out[9] ) , .p0 ( optlc_net_119 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_5 mux_left_track_25 ( - .in ( { chany_top_in[8] , left_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size2_14_sram ) , - .sram_inv ( mux_left_track_25_undriven_sram_inv ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_120 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_6 mux_left_track_27 ( - .in ( { chany_top_in[7] , left_bottom_grid_pin_3_[0] } ) , - .sram ( mux_tree_tapbuf_size2_15_sram ) , - .sram_inv ( mux_left_track_27_undriven_sram_inv ) , - .out ( chanx_left_out[13] ) , .p0 ( optlc_net_122 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_7 mux_left_track_29 ( - .in ( { chany_top_in[6] , left_bottom_grid_pin_5_[0] } ) , - .sram ( mux_tree_tapbuf_size2_16_sram ) , - .sram_inv ( mux_left_track_29_undriven_sram_inv ) , - .out ( { ropt_net_126 } ) , - .p0 ( optlc_net_119 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_8 mux_left_track_31 ( - .in ( { chany_top_in[5] , left_bottom_grid_pin_7_[0] } ) , - .sram ( mux_tree_tapbuf_size2_17_sram ) , - .sram_inv ( mux_left_track_31_undriven_sram_inv ) , - .out ( chanx_left_out[15] ) , .p0 ( optlc_net_122 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_9 mux_left_track_33 ( - .in ( { chany_top_in[4] , left_bottom_grid_pin_9_[0] } ) , - .sram ( mux_tree_tapbuf_size2_18_sram ) , - .sram_inv ( mux_left_track_33_undriven_sram_inv ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_119 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_10 mux_left_track_35 ( - .in ( { chany_top_in[3] , left_bottom_grid_pin_11_[0] } ) , - .sram ( mux_tree_tapbuf_size2_19_sram ) , - .sram_inv ( mux_left_track_35_undriven_sram_inv ) , - .out ( chanx_left_out[17] ) , .p0 ( optlc_net_121 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_12 mem_top_track_10 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_13 mem_top_track_12 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_14 mem_top_track_14 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_15 mem_top_track_16 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_16 mem_top_track_18 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_17 mem_top_track_20 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_18 mem_top_track_22 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem mem_top_track_26 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_11 mem_left_track_9 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_0 mem_left_track_11 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_1 mem_left_track_13 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_2 mem_left_track_15 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_11_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_3 mem_left_track_17 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_12_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_4 mem_left_track_19 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_13_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_5 mem_left_track_25 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_14_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_6 mem_left_track_27 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_15_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_7 mem_left_track_29 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_16_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_8 mem_left_track_31 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_17_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_9 mem_left_track_33 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_18_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_10 mem_left_track_35 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , - .ccff_tail ( { ropt_net_130 } ) , - .mem_out ( mux_tree_tapbuf_size2_19_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size4_0 mux_left_track_1 ( - .in ( { chany_top_in[0] , left_bottom_grid_pin_1_[0] , - left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] } ) , - .sram ( mux_tree_tapbuf_size4_0_sram ) , - .sram_inv ( mux_left_track_1_undriven_sram_inv ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_122 ) ) ; -sb_2__0__mux_tree_tapbuf_size4_1 mux_left_track_3 ( - .in ( { chany_top_in[19] , left_bottom_grid_pin_3_[0] , - left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] } ) , - .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_left_track_3_undriven_sram_inv ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_122 ) ) ; -sb_2__0__mux_tree_tapbuf_size4_2 mux_left_track_5 ( - .in ( { chany_top_in[18] , left_bottom_grid_pin_1_[0] , - left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] } ) , - .sram ( mux_tree_tapbuf_size4_2_sram ) , - .sram_inv ( mux_left_track_5_undriven_sram_inv ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_122 ) ) ; -sb_2__0__mux_tree_tapbuf_size4 mux_left_track_7 ( - .in ( { chany_top_in[17] , left_bottom_grid_pin_3_[0] , - left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] } ) , - .sram ( mux_tree_tapbuf_size4_3_sram ) , - .sram_inv ( mux_left_track_7_undriven_sram_inv ) , - .out ( chanx_left_out[3] ) , .p0 ( optlc_net_122 ) ) ; -sb_2__0__mux_tree_tapbuf_size4_mem_0 mem_left_track_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size4_mem_1 mem_left_track_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size4_mem_2 mem_left_track_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size4_mem mem_left_track_7 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_139 ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_708 ( .A ( ropt_net_126 ) , - .X ( ropt_net_139 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_721 ( .A ( ropt_net_140 ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_141 ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__4 ( .A ( chanx_left_in[1] ) , - .X ( ropt_net_133 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_119 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_120 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_121 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__8 ( .A ( chanx_left_in[5] ) , - .X ( ropt_net_134 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__9 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_137 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_723 ( .A ( ropt_net_142 ) , - .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_122 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( ropt_net_143 ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( ropt_net_144 ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( ropt_net_145 ) , - .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_78 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_132 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( ropt_net_146 ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_728 ( .A ( ropt_net_147 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_86 ( .A ( chanx_left_in[2] ) , - .X ( ropt_net_136 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_87 ( .A ( chanx_left_in[3] ) , - .X ( ropt_net_131 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_88 ( .A ( chanx_left_in[4] ) , - .X ( ropt_net_135 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_709 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_148 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_710 ( .A ( chany_top_in[9] ) , - .X ( ropt_net_149 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_711 ( .A ( chany_top_in[1] ) , - .X ( ropt_net_150 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_712 ( .A ( ropt_net_130 ) , - .X ( ropt_net_147 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_713 ( .A ( ropt_net_131 ) , - .X ( ropt_net_141 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_714 ( .A ( ropt_net_132 ) , - .X ( ropt_net_142 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_715 ( .A ( ropt_net_133 ) , - .X ( ropt_net_144 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_716 ( .A ( ropt_net_134 ) , - .X ( ropt_net_140 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_717 ( .A ( ropt_net_135 ) , - .X ( ropt_net_145 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_718 ( .A ( ropt_net_136 ) , - .X ( ropt_net_146 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_137 ) , - .X ( ropt_net_143 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_148 ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_730 ( .A ( ropt_net_149 ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_150 ) , - .X ( chanx_left_out[19] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_28__62 ( .A ( mem_out[2] ) , - .X ( net_net_120 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_120 ( .A ( net_net_120 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__const1 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sb_1__2__const1 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__61 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__const1_26 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_1__2__const1_26 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__60 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size3_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__59 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__58 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__57 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__56 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__55 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__const1_25 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sb_1__2__const1_25 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_1__2__const1_24 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size3_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sb_1__2__const1_24 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_1__2__const1_23 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sb_1__2__const1_23 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_1__2__const1_22 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_1__2__const1_22 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_1__2__const1_21 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_1__2__const1_21 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_1__2__const1_20 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sb_1__2__const1_20 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__54 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__53 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__52 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__const1_19 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sb_1__2__const1_19 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_1__2__const1_18 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sb_1__2__const1_18 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -endmodule - - -module sb_1__2__const1_17 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sb_1__2__const1_17 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_126 ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__51 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__const1_16 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -sb_1__2__const1_16 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__50 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__49 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__48 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__47 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__46 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__45 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__44 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__43 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__const1_15 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sb_1__2__const1_15 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_1__2__const1_14 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sb_1__2__const1_14 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_1__2__const1_13 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sb_1__2__const1_13 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_1__2__const1_12 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sb_1__2__const1_12 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_125 ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_1__2__const1_11 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sb_1__2__const1_11 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_1__2__const1_10 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sb_1__2__const1_10 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_1__2__const1_9 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sb_1__2__const1_9 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_1__2__const1_8 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sb_1__2__const1_8 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__42 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__41 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__const1_7 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sb_1__2__const1_7 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module sb_1__2__const1_6 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sb_1__2__const1_6 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size14_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__40 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size14_mem ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__39 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__const1_5 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size14_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:13] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sb_1__2__const1_5 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; -endmodule - - -module sb_1__2__const1_4 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size14 ( in , sram , sram_inv , out , p0 ) ; -input [0:13] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sb_1__2__const1_4 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size9_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__38 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size9_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__37 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size9_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__36 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__const1_3 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size9_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:8] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; - -sb_1__2__const1_3 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -endmodule - - -module sb_1__2__const1_2 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size9_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:8] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; - -sb_1__2__const1_2 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -endmodule - - -module sb_1__2__const1_1 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , p0 ) ; -input [0:8] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; - -sb_1__2__const1_1 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__35 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__const1_0 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sb_1__2__const1_0 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module sb_1__2_ ( prog_clk , chanx_right_in , right_top_grid_pin_1_ , - right_bottom_grid_pin_34_ , right_bottom_grid_pin_35_ , - right_bottom_grid_pin_36_ , right_bottom_grid_pin_37_ , - right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ , - right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ , chany_bottom_in , - bottom_left_grid_pin_42_ , bottom_left_grid_pin_43_ , - bottom_left_grid_pin_44_ , bottom_left_grid_pin_45_ , - bottom_left_grid_pin_46_ , bottom_left_grid_pin_47_ , - bottom_left_grid_pin_48_ , bottom_left_grid_pin_49_ , chanx_left_in , - left_top_grid_pin_1_ , left_bottom_grid_pin_34_ , - left_bottom_grid_pin_35_ , left_bottom_grid_pin_36_ , - left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , - left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , - left_bottom_grid_pin_41_ , ccff_head , chanx_right_out , - chany_bottom_out , chanx_left_out , ccff_tail , SC_IN_TOP , SC_IN_BOT , - SC_OUT_TOP , SC_OUT_BOT , Test_en__FEEDTHRU_0 , Test_en__FEEDTHRU_1 , - Test_en__FEEDTHRU_2 , clk__FEEDTHRU_0 , clk__FEEDTHRU_1 , - clk__FEEDTHRU_2 ) ; -input [0:0] prog_clk ; -input [0:19] chanx_right_in ; -input [0:0] right_top_grid_pin_1_ ; -input [0:0] right_bottom_grid_pin_34_ ; -input [0:0] right_bottom_grid_pin_35_ ; -input [0:0] right_bottom_grid_pin_36_ ; -input [0:0] right_bottom_grid_pin_37_ ; -input [0:0] right_bottom_grid_pin_38_ ; -input [0:0] right_bottom_grid_pin_39_ ; -input [0:0] right_bottom_grid_pin_40_ ; -input [0:0] right_bottom_grid_pin_41_ ; -input [0:19] chany_bottom_in ; -input [0:0] bottom_left_grid_pin_42_ ; -input [0:0] bottom_left_grid_pin_43_ ; -input [0:0] bottom_left_grid_pin_44_ ; -input [0:0] bottom_left_grid_pin_45_ ; -input [0:0] bottom_left_grid_pin_46_ ; -input [0:0] bottom_left_grid_pin_47_ ; -input [0:0] bottom_left_grid_pin_48_ ; -input [0:0] bottom_left_grid_pin_49_ ; -input [0:19] chanx_left_in ; -input [0:0] left_top_grid_pin_1_ ; -input [0:0] left_bottom_grid_pin_34_ ; -input [0:0] left_bottom_grid_pin_35_ ; -input [0:0] left_bottom_grid_pin_36_ ; -input [0:0] left_bottom_grid_pin_37_ ; -input [0:0] left_bottom_grid_pin_38_ ; -input [0:0] left_bottom_grid_pin_39_ ; -input [0:0] left_bottom_grid_pin_40_ ; -input [0:0] left_bottom_grid_pin_41_ ; -input [0:0] ccff_head ; -output [0:19] chanx_right_out ; -output [0:19] chany_bottom_out ; -output [0:19] chanx_left_out ; -output [0:0] ccff_tail ; -input SC_IN_TOP ; -input SC_IN_BOT ; -output SC_OUT_TOP ; -output SC_OUT_BOT ; -input [0:0] Test_en__FEEDTHRU_0 ; -output [0:0] Test_en__FEEDTHRU_1 ; -output [0:0] Test_en__FEEDTHRU_2 ; -input [0:0] clk__FEEDTHRU_0 ; -output [0:0] clk__FEEDTHRU_1 ; -output [0:0] clk__FEEDTHRU_2 ; - -wire [0:2] mux_bottom_track_11_undriven_sram_inv ; -wire [0:1] mux_bottom_track_13_undriven_sram_inv ; -wire [0:1] mux_bottom_track_15_undriven_sram_inv ; -wire [0:1] mux_bottom_track_17_undriven_sram_inv ; -wire [0:1] mux_bottom_track_19_undriven_sram_inv ; -wire [0:2] mux_bottom_track_1_undriven_sram_inv ; -wire [0:1] mux_bottom_track_21_undriven_sram_inv ; -wire [0:1] mux_bottom_track_23_undriven_sram_inv ; -wire [0:2] mux_bottom_track_25_undriven_sram_inv ; -wire [0:1] mux_bottom_track_27_undriven_sram_inv ; -wire [0:2] mux_bottom_track_3_undriven_sram_inv ; -wire [0:2] mux_bottom_track_5_undriven_sram_inv ; -wire [0:2] mux_bottom_track_7_undriven_sram_inv ; -wire [0:2] mux_bottom_track_9_undriven_sram_inv ; -wire [0:2] mux_left_track_17_undriven_sram_inv ; -wire [0:3] mux_left_track_1_undriven_sram_inv ; -wire [0:2] mux_left_track_25_undriven_sram_inv ; -wire [0:2] mux_left_track_33_undriven_sram_inv ; -wire [0:3] mux_left_track_3_undriven_sram_inv ; -wire [0:3] mux_left_track_5_undriven_sram_inv ; -wire [0:3] mux_left_track_9_undriven_sram_inv ; -wire [0:3] mux_right_track_0_undriven_sram_inv ; -wire [0:2] mux_right_track_16_undriven_sram_inv ; -wire [0:2] mux_right_track_24_undriven_sram_inv ; -wire [0:3] mux_right_track_2_undriven_sram_inv ; -wire [0:2] mux_right_track_32_undriven_sram_inv ; -wire [0:3] mux_right_track_4_undriven_sram_inv ; -wire [0:3] mux_right_track_8_undriven_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size14_0_sram ; -wire [0:3] mux_tree_tapbuf_size14_1_sram ; -wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail ; -wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; -wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:1] mux_tree_tapbuf_size3_2_sram ; -wire [0:1] mux_tree_tapbuf_size3_3_sram ; -wire [0:1] mux_tree_tapbuf_size3_4_sram ; -wire [0:1] mux_tree_tapbuf_size3_5_sram ; -wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size4_0_sram ; -wire [0:2] mux_tree_tapbuf_size4_1_sram ; -wire [0:2] mux_tree_tapbuf_size4_2_sram ; -wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size5_0_sram ; -wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size7_0_sram ; -wire [0:2] mux_tree_tapbuf_size7_1_sram ; -wire [0:2] mux_tree_tapbuf_size7_2_sram ; -wire [0:2] mux_tree_tapbuf_size7_3_sram ; -wire [0:2] mux_tree_tapbuf_size7_4_sram ; -wire [0:2] mux_tree_tapbuf_size7_5_sram ; -wire [0:2] mux_tree_tapbuf_size7_6_sram ; -wire [0:2] mux_tree_tapbuf_size7_7_sram ; -wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_7_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size9_0_sram ; -wire [0:3] mux_tree_tapbuf_size9_1_sram ; -wire [0:3] mux_tree_tapbuf_size9_2_sram ; -wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size9_mem_2_ccff_tail ; - -assign SC_IN_TOP = SC_IN_BOT ; -assign clk__FEEDTHRU_2[0] = clk__FEEDTHRU_0[0] ; -assign clk__FEEDTHRU_1[0] = clk__FEEDTHRU_2[0] ; - -sb_1__2__mux_tree_tapbuf_size10 mux_right_track_0 ( - .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] , - right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , - right_bottom_grid_pin_41_[0] , chany_bottom_in[5] , - chany_bottom_in[12] , chany_bottom_in[19] , chanx_left_in[2] , - chanx_left_in[12] } ) , - .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_right_track_0_undriven_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_157 ) ) ; -sb_1__2__mux_tree_tapbuf_size10_mem mem_right_track_0 ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size9 mux_right_track_2 ( - .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , - right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , - chany_bottom_in[4] , chany_bottom_in[11] , chany_bottom_in[18] , - chanx_left_in[4] , chanx_left_in[13] } ) , - .sram ( mux_tree_tapbuf_size9_0_sram ) , - .sram_inv ( mux_right_track_2_undriven_sram_inv ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_157 ) ) ; -sb_1__2__mux_tree_tapbuf_size9_0 mux_left_track_1 ( - .in ( { chanx_right_in[2] , chanx_right_in[12] , chany_bottom_in[6] , - chany_bottom_in[13] , left_top_grid_pin_1_[0] , - left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , - left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , - .sram ( mux_tree_tapbuf_size9_1_sram ) , - .sram_inv ( mux_left_track_1_undriven_sram_inv ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_155 ) ) ; -sb_1__2__mux_tree_tapbuf_size9_1 mux_left_track_3 ( - .in ( { chanx_right_in[4] , chanx_right_in[13] , chany_bottom_in[0] , - chany_bottom_in[7] , chany_bottom_in[14] , - left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , - left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , - .sram ( mux_tree_tapbuf_size9_2_sram ) , - .sram_inv ( mux_left_track_3_undriven_sram_inv ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_154 ) ) ; -sb_1__2__mux_tree_tapbuf_size9_mem mem_right_track_2 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size9_0_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size9_mem_0 mem_left_track_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size9_1_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size9_mem_1 mem_left_track_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size9_2_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size14 mux_right_track_4 ( - .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_34_[0] , - right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_36_[0] , - right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_38_[0] , - right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_40_[0] , - right_bottom_grid_pin_41_[0] , chany_bottom_in[3] , - chany_bottom_in[10] , chany_bottom_in[17] , chanx_left_in[5] , - chanx_left_in[14] } ) , - .sram ( mux_tree_tapbuf_size14_0_sram ) , - .sram_inv ( mux_right_track_4_undriven_sram_inv ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_157 ) ) ; -sb_1__2__mux_tree_tapbuf_size14_0 mux_left_track_5 ( - .in ( { chanx_right_in[5] , chanx_right_in[14] , chany_bottom_in[1] , - chany_bottom_in[8] , chany_bottom_in[15] , left_top_grid_pin_1_[0] , - left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_35_[0] , - left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_37_[0] , - left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_39_[0] , - left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_41_[0] } ) , - .sram ( mux_tree_tapbuf_size14_1_sram ) , - .sram_inv ( mux_left_track_5_undriven_sram_inv ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_154 ) ) ; -sb_1__2__mux_tree_tapbuf_size14_mem mem_right_track_4 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size14_0_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size14_mem_0 mem_left_track_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size14_1_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size8 mux_right_track_8 ( - .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_37_[0] , - right_bottom_grid_pin_41_[0] , chany_bottom_in[2] , - chany_bottom_in[9] , chany_bottom_in[16] , chanx_left_in[6] , - chanx_left_in[16] } ) , - .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_right_track_8_undriven_sram_inv ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_153 ) ) ; -sb_1__2__mux_tree_tapbuf_size8_0 mux_left_track_9 ( - .in ( { chanx_right_in[6] , chanx_right_in[16] , chany_bottom_in[2] , - chany_bottom_in[9] , chany_bottom_in[16] , left_top_grid_pin_1_[0] , - left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_41_[0] } ) , - .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_left_track_9_undriven_sram_inv ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_155 ) ) ; -sb_1__2__mux_tree_tapbuf_size8_mem mem_right_track_8 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size8_mem_0 mem_left_track_9 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size7_6 mux_right_track_16 ( - .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_38_[0] , - chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[15] , - chanx_left_in[8] , chanx_left_in[17] } ) , - .sram ( mux_tree_tapbuf_size7_0_sram ) , - .sram_inv ( mux_right_track_16_undriven_sram_inv ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_153 ) ) ; -sb_1__2__mux_tree_tapbuf_size7 mux_right_track_24 ( - .in ( { right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_39_[0] , - chany_bottom_in[0] , chany_bottom_in[7] , chany_bottom_in[14] , - chanx_left_in[9] , chanx_left_in[18] } ) , - .sram ( mux_tree_tapbuf_size7_1_sram ) , - .sram_inv ( mux_right_track_24_undriven_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_153 ) ) ; -sb_1__2__mux_tree_tapbuf_size7_0 mux_bottom_track_1 ( - .in ( { chanx_right_in[2] , bottom_left_grid_pin_42_[0] , - bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , - bottom_left_grid_pin_48_[0] , chanx_left_in[1] , chanx_left_in[2] } ) , - .sram ( mux_tree_tapbuf_size7_2_sram ) , - .sram_inv ( mux_bottom_track_1_undriven_sram_inv ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_155 ) ) ; -sb_1__2__mux_tree_tapbuf_size7_1 mux_bottom_track_3 ( - .in ( { chanx_right_in[4] , bottom_left_grid_pin_43_[0] , - bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , - bottom_left_grid_pin_49_[0] , chanx_left_in[3] , chanx_left_in[4] } ) , - .sram ( mux_tree_tapbuf_size7_3_sram ) , - .sram_inv ( mux_bottom_track_3_undriven_sram_inv ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_156 ) ) ; -sb_1__2__mux_tree_tapbuf_size7_2 mux_bottom_track_5 ( - .in ( { chanx_right_in[5] , bottom_left_grid_pin_42_[0] , - bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , - bottom_left_grid_pin_48_[0] , chanx_left_in[5] , chanx_left_in[7] } ) , - .sram ( mux_tree_tapbuf_size7_4_sram ) , - .sram_inv ( mux_bottom_track_5_undriven_sram_inv ) , - .out ( { ropt_net_169 } ) , - .p0 ( optlc_net_154 ) ) ; -sb_1__2__mux_tree_tapbuf_size7_3 mux_bottom_track_7 ( - .in ( { chanx_right_in[6] , bottom_left_grid_pin_43_[0] , - bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , - bottom_left_grid_pin_49_[0] , chanx_left_in[6] , chanx_left_in[11] } ) , - .sram ( mux_tree_tapbuf_size7_5_sram ) , - .sram_inv ( mux_bottom_track_7_undriven_sram_inv ) , - .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_154 ) ) ; -sb_1__2__mux_tree_tapbuf_size7_4 mux_left_track_17 ( - .in ( { chanx_right_in[8] , chanx_right_in[17] , chany_bottom_in[3] , - chany_bottom_in[10] , chany_bottom_in[17] , - left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_38_[0] } ) , - .sram ( mux_tree_tapbuf_size7_6_sram ) , - .sram_inv ( mux_left_track_17_undriven_sram_inv ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_155 ) ) ; -sb_1__2__mux_tree_tapbuf_size7_5 mux_left_track_25 ( - .in ( { chanx_right_in[9] , chanx_right_in[18] , chany_bottom_in[4] , - chany_bottom_in[11] , chany_bottom_in[18] , - left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_39_[0] } ) , - .sram ( mux_tree_tapbuf_size7_7_sram ) , - .sram_inv ( mux_left_track_25_undriven_sram_inv ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_156 ) ) ; -sb_1__2__mux_tree_tapbuf_size7_mem_6 mem_right_track_16 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size7_mem mem_right_track_24 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size7_mem_0 mem_bottom_track_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size7_mem_1 mem_bottom_track_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_3_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size7_mem_2 mem_bottom_track_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_4_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size7_mem_3 mem_bottom_track_7 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_5_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size7_mem_4 mem_left_track_17 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_6_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size7_mem_5 mem_left_track_25 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_7_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size5 mux_right_track_32 ( - .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_40_[0] , - chany_bottom_in[6] , chany_bottom_in[13] , chanx_left_in[10] } ) , - .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_right_track_32_undriven_sram_inv ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_153 ) ) ; -sb_1__2__mux_tree_tapbuf_size5_mem mem_right_track_32 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size4 mux_bottom_track_9 ( - .in ( { chanx_right_in[8] , bottom_left_grid_pin_42_[0] , - chanx_left_in[8] , chanx_left_in[15] } ) , - .sram ( mux_tree_tapbuf_size4_0_sram ) , - .sram_inv ( mux_bottom_track_9_undriven_sram_inv ) , - .out ( { ropt_net_168 } ) , - .p0 ( optlc_net_154 ) ) ; -sb_1__2__mux_tree_tapbuf_size4_0 mux_bottom_track_11 ( - .in ( { chanx_right_in[9] , bottom_left_grid_pin_43_[0] , - chanx_left_in[9] , chanx_left_in[19] } ) , - .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_bottom_track_11_undriven_sram_inv ) , - .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_154 ) ) ; -sb_1__2__mux_tree_tapbuf_size4_1 mux_bottom_track_25 ( - .in ( { chanx_right_in[18] , chanx_right_in[19] , - bottom_left_grid_pin_42_[0] , chanx_left_in[18] } ) , - .sram ( mux_tree_tapbuf_size4_2_sram ) , - .sram_inv ( mux_bottom_track_25_undriven_sram_inv ) , - .out ( { ropt_net_162 } ) , - .p0 ( optlc_net_153 ) ) ; -sb_1__2__mux_tree_tapbuf_size4_mem mem_bottom_track_9 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size4_mem_0 mem_bottom_track_11 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size4_mem_1 mem_bottom_track_25 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size3_0 mux_bottom_track_13 ( - .in ( { chanx_right_in[10] , bottom_left_grid_pin_44_[0] , - chanx_left_in[10] } ) , - .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_bottom_track_13_undriven_sram_inv ) , - .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_156 ) ) ; -sb_1__2__mux_tree_tapbuf_size3_1 mux_bottom_track_15 ( - .in ( { chanx_right_in[12] , bottom_left_grid_pin_45_[0] , - chanx_left_in[12] } ) , - .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_bottom_track_15_undriven_sram_inv ) , - .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_156 ) ) ; -sb_1__2__mux_tree_tapbuf_size3_2 mux_bottom_track_17 ( - .in ( { chanx_right_in[13] , bottom_left_grid_pin_46_[0] , - chanx_left_in[13] } ) , - .sram ( mux_tree_tapbuf_size3_2_sram ) , - .sram_inv ( mux_bottom_track_17_undriven_sram_inv ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_156 ) ) ; -sb_1__2__mux_tree_tapbuf_size3_3 mux_bottom_track_19 ( - .in ( { chanx_right_in[14] , bottom_left_grid_pin_47_[0] , - chanx_left_in[14] } ) , - .sram ( mux_tree_tapbuf_size3_3_sram ) , - .sram_inv ( mux_bottom_track_19_undriven_sram_inv ) , - .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_156 ) ) ; -sb_1__2__mux_tree_tapbuf_size3_4 mux_bottom_track_21 ( - .in ( { chanx_right_in[16] , bottom_left_grid_pin_48_[0] , - chanx_left_in[16] } ) , - .sram ( mux_tree_tapbuf_size3_4_sram ) , - .sram_inv ( mux_bottom_track_21_undriven_sram_inv ) , - .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_156 ) ) ; -sb_1__2__mux_tree_tapbuf_size3 mux_bottom_track_23 ( - .in ( { chanx_right_in[17] , bottom_left_grid_pin_49_[0] , - chanx_left_in[17] } ) , - .sram ( mux_tree_tapbuf_size3_5_sram ) , - .sram_inv ( mux_bottom_track_23_undriven_sram_inv ) , - .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_153 ) ) ; -sb_1__2__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_13 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size3_mem_1 mem_bottom_track_15 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size3_mem_2 mem_bottom_track_17 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size3_mem_3 mem_bottom_track_19 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size3_mem_4 mem_bottom_track_21 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_4_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size3_mem mem_bottom_track_23 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_5_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size2 mux_bottom_track_27 ( - .in ( { chanx_right_in[15] , bottom_left_grid_pin_43_[0] } ) , - .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_bottom_track_27_undriven_sram_inv ) , - .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_153 ) ) ; -sb_1__2__mux_tree_tapbuf_size2_mem mem_bottom_track_27 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size6 mux_left_track_33 ( - .in ( { chanx_right_in[10] , chany_bottom_in[5] , chany_bottom_in[12] , - chany_bottom_in[19] , left_bottom_grid_pin_36_[0] , - left_bottom_grid_pin_40_[0] } ) , - .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_left_track_33_undriven_sram_inv ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_154 ) ) ; -sb_1__2__mux_tree_tapbuf_size6_mem mem_left_track_33 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , - .ccff_tail ( { ropt_net_164 } ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_811 ( .A ( ropt_net_193 ) , - .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_153 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_150 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_154 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_152 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_155 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__4 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_179 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chanx_right_in[5] ) , - .X ( ropt_net_188 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__6 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_177 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_154 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_156 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_191 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_187 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_156 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , - .HI ( optlc_net_157 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( chanx_right_in[2] ) , - .X ( ropt_net_194 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_159 ) , - .X ( ropt_net_205 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( .A ( ropt_net_160 ) , - .X ( ropt_net_209 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chanx_right_in[14] ) , - .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_194 ) , - .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__16 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_184 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( chanx_right_in[18] ) , - .X ( ropt_net_211 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_162 ) , - .X ( ropt_net_204 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_163 ) , - .X ( ropt_net_197 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__20 ( .A ( chanx_left_in[4] ) , - .X ( ropt_net_189 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( ropt_net_195 ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( ropt_net_164 ) , - .X ( ropt_net_208 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_165 ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_25__24 ( .A ( chanx_left_in[9] ) , - .X ( ropt_net_182 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_26__25 ( .A ( chanx_left_in[10] ) , - .X ( ropt_net_186 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( - .A ( Test_en__FEEDTHRU_0[0] ) , .X ( ropt_net_215 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_782 ( - .A ( Test_en__FEEDTHRU_0[0] ) , .X ( ropt_net_216 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_783 ( .A ( ropt_net_168 ) , - .X ( ropt_net_210 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_784 ( .A ( ropt_net_169 ) , - .X ( ropt_net_214 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_31__30 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_180 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_785 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_213 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_160 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_196 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_814 ( .A ( ropt_net_196 ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_816 ( .A ( ropt_net_197 ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_787 ( .A ( chanx_left_in[5] ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_173 ) , - .X ( ropt_net_199 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_75 ( .A ( chanx_right_in[3] ) , - .X ( BUF_net_75 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( chanx_left_in[18] ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_818 ( .A ( ropt_net_198 ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_78 ( .A ( chanx_right_in[11] ) , - .X ( BUF_net_78 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_819 ( .A ( ropt_net_199 ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( chanx_left_in[6] ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_822 ( .A ( ropt_net_200 ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_212 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_823 ( .A ( ropt_net_201 ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_84 ( .A ( chanx_left_in[2] ) , - .X ( BUF_net_84 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_792 ( .A ( ropt_net_177 ) , - .X ( ropt_net_193 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_86 ( .A ( chanx_left_in[8] ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_178 ) , - .X ( ropt_net_202 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_179 ) , - .X ( ropt_net_198 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_180 ) , - .X ( ropt_net_201 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_90 ( .A ( chanx_left_in[16] ) , - .X ( ropt_net_183 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_181 ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_824 ( .A ( ropt_net_202 ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_826 ( .A ( ropt_net_203 ) , - .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_100 ( .A ( chanx_right_in[0] ) , - .X ( ropt_net_163 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( ropt_net_182 ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_183 ) , - .X ( ropt_net_195 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_184 ) , - .X ( ropt_net_206 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_185 ) , - .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_186 ) , - .X ( ropt_net_200 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_187 ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_188 ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_189 ) , - .X ( ropt_net_203 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_190 ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_191 ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_827 ( .A ( ropt_net_204 ) , - .X ( chany_bottom_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_828 ( .A ( ropt_net_205 ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_113 ( .A ( chanx_left_in[12] ) , - .X ( ropt_net_185 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_829 ( .A ( ropt_net_206 ) , - .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_830 ( .A ( ropt_net_207 ) , - .X ( chany_bottom_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_208 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_832 ( .A ( ropt_net_209 ) , - .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_122 ( .A ( chanx_right_in[16] ) , - .X ( ropt_net_159 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_834 ( .A ( ropt_net_210 ) , - .X ( chany_bottom_out[4] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_129 ( .A ( chanx_right_in[1] ) , - .X ( ropt_net_173 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_835 ( .A ( ropt_net_211 ) , - .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_131 ( .A ( BUF_net_75 ) , - .X ( ropt_net_207 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_132 ( .A ( chanx_right_in[7] ) , - .X ( ropt_net_190 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_836 ( .A ( ropt_net_212 ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_134 ( .A ( BUF_net_78 ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_837 ( .A ( ropt_net_213 ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_839 ( .A ( ropt_net_214 ) , - .X ( chany_bottom_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_840 ( .A ( ropt_net_215 ) , - .X ( Test_en__FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_138 ( .A ( chanx_left_in[0] ) , - .X ( ropt_net_165 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_139 ( .A ( BUF_net_84 ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_841 ( .A ( ropt_net_216 ) , - .X ( Test_en__FEEDTHRU_2[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_141 ( .A ( chanx_left_in[13] ) , - .X ( ropt_net_181 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_142 ( .A ( chanx_left_in[14] ) , - .X ( ropt_net_178 ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_28__81 ( .A ( mem_out[2] ) , - .X ( net_net_100 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_100 ( .A ( net_net_100 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__80 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__79 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__78 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__const1 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sb_1__1__const1 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_1__1__const1_26 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sb_1__1__const1_26 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_1__1__const1_25 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sb_1__1__const1_25 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_1__1__const1_24 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sb_1__1__const1_24 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__77 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__76 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__75 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__74 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__73 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__72 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__71 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__70 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_mem_8 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__69 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_mem_10 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__68 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_mem_9 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__67 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__66 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__const1_23 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sb_1__1__const1_23 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module sb_1__1__const1_22 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sb_1__1__const1_22 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module sb_1__1__const1_21 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sb_1__1__const1_21 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module sb_1__1__const1_20 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sb_1__1__const1_20 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module sb_1__1__const1_19 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sb_1__1__const1_19 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module sb_1__1__const1_18 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sb_1__1__const1_18 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module sb_1__1__const1_17 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sb_1__1__const1_17 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module sb_1__1__const1_16 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sb_1__1__const1_16 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module sb_1__1__const1_15 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_8 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sb_1__1__const1_15 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module sb_1__1__const1_14 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_10 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sb_1__1__const1_14 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module sb_1__1__const1_13 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_9 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sb_1__1__const1_13 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module sb_1__1__const1_12 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sb_1__1__const1_12 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size16_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:4] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__65 ( .A ( mem_out[4] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size16_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:4] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__64 ( .A ( mem_out[4] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size16_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:4] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__63 ( .A ( mem_out[4] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size16_mem ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:4] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__62 ( .A ( mem_out[4] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__const1_11 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size16_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:15] in ; -input [0:4] sram ; -input [0:4] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sb_1__1__const1_11 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l5_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_1__1__const1_10 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size16_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:15] in ; -input [0:4] sram ; -input [0:4] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_15_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sb_1__1__const1_10 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , - .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_83 ( - .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( BUF_net_83 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_128 ( .A ( BUF_net_83 ) , - .X ( out[0] ) ) ; -endmodule - - -module sb_1__1__const1_9 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size16_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:15] in ; -input [0:4] sram ; -input [0:4] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_15_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sb_1__1__const1_9 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , - .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) ) ; -endmodule - - -module sb_1__1__const1_8 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size16 ( in , sram , sram_inv , out , p0 ) ; -input [0:15] in ; -input [0:4] sram ; -input [0:4] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_15_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sb_1__1__const1_8 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , - .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__61 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__60 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__59 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__58 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__57 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__56 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_mem ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__55 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__54 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__const1_7 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:11] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sb_1__1__const1_7 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -endmodule - - -module sb_1__1__const1_6 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:11] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sb_1__1__const1_6 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_127 ( - .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_1__1__const1_5 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:11] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sb_1__1__const1_5 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -endmodule - - -module sb_1__1__const1_4 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:11] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sb_1__1__const1_4 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -endmodule - - -module sb_1__1__const1_3 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:11] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sb_1__1__const1_3 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -endmodule - - -module sb_1__1__const1_2 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:11] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sb_1__1__const1_2 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -endmodule - - -module sb_1__1__const1_1 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12 ( in , sram , sram_inv , out , p0 ) ; -input [0:11] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sb_1__1__const1_1 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -endmodule - - -module sb_1__1__const1_0 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:11] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sb_1__1__const1_0 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -endmodule - - -module sb_1__1_ ( prog_clk , chany_top_in , top_left_grid_pin_42_ , - top_left_grid_pin_43_ , top_left_grid_pin_44_ , top_left_grid_pin_45_ , - top_left_grid_pin_46_ , top_left_grid_pin_47_ , top_left_grid_pin_48_ , - top_left_grid_pin_49_ , chanx_right_in , right_bottom_grid_pin_34_ , - right_bottom_grid_pin_35_ , right_bottom_grid_pin_36_ , - right_bottom_grid_pin_37_ , right_bottom_grid_pin_38_ , - right_bottom_grid_pin_39_ , right_bottom_grid_pin_40_ , - right_bottom_grid_pin_41_ , chany_bottom_in , bottom_left_grid_pin_42_ , - bottom_left_grid_pin_43_ , bottom_left_grid_pin_44_ , - bottom_left_grid_pin_45_ , bottom_left_grid_pin_46_ , - bottom_left_grid_pin_47_ , bottom_left_grid_pin_48_ , - bottom_left_grid_pin_49_ , chanx_left_in , left_bottom_grid_pin_34_ , - left_bottom_grid_pin_35_ , left_bottom_grid_pin_36_ , - left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , - left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , - left_bottom_grid_pin_41_ , ccff_head , chany_top_out , chanx_right_out , - chany_bottom_out , chanx_left_out , ccff_tail , prog_clk__FEEDTHRU_1 , - Test_en__FEEDTHRU_0 , Test_en__FEEDTHRU_1 , clk__FEEDTHRU_0 , - clk__FEEDTHRU_1 , - grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 , - grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) ; -input [0:0] prog_clk ; -input [0:19] chany_top_in ; -input [0:0] top_left_grid_pin_42_ ; -input [0:0] top_left_grid_pin_43_ ; -input [0:0] top_left_grid_pin_44_ ; -input [0:0] top_left_grid_pin_45_ ; -input [0:0] top_left_grid_pin_46_ ; -input [0:0] top_left_grid_pin_47_ ; -input [0:0] top_left_grid_pin_48_ ; -input [0:0] top_left_grid_pin_49_ ; -input [0:19] chanx_right_in ; -input [0:0] right_bottom_grid_pin_34_ ; -input [0:0] right_bottom_grid_pin_35_ ; -input [0:0] right_bottom_grid_pin_36_ ; -input [0:0] right_bottom_grid_pin_37_ ; -input [0:0] right_bottom_grid_pin_38_ ; -input [0:0] right_bottom_grid_pin_39_ ; -input [0:0] right_bottom_grid_pin_40_ ; -input [0:0] right_bottom_grid_pin_41_ ; -input [0:19] chany_bottom_in ; -input [0:0] bottom_left_grid_pin_42_ ; -input [0:0] bottom_left_grid_pin_43_ ; -input [0:0] bottom_left_grid_pin_44_ ; -input [0:0] bottom_left_grid_pin_45_ ; -input [0:0] bottom_left_grid_pin_46_ ; -input [0:0] bottom_left_grid_pin_47_ ; -input [0:0] bottom_left_grid_pin_48_ ; -input [0:0] bottom_left_grid_pin_49_ ; -input [0:19] chanx_left_in ; -input [0:0] left_bottom_grid_pin_34_ ; -input [0:0] left_bottom_grid_pin_35_ ; -input [0:0] left_bottom_grid_pin_36_ ; -input [0:0] left_bottom_grid_pin_37_ ; -input [0:0] left_bottom_grid_pin_38_ ; -input [0:0] left_bottom_grid_pin_39_ ; -input [0:0] left_bottom_grid_pin_40_ ; -input [0:0] left_bottom_grid_pin_41_ ; -input [0:0] ccff_head ; -output [0:19] chany_top_out ; -output [0:19] chanx_right_out ; -output [0:19] chany_bottom_out ; -output [0:19] chanx_left_out ; -output [0:0] ccff_tail ; -output [0:0] prog_clk__FEEDTHRU_1 ; -input [0:0] Test_en__FEEDTHRU_0 ; -output [0:0] Test_en__FEEDTHRU_1 ; -input [0:0] clk__FEEDTHRU_0 ; -output [0:0] clk__FEEDTHRU_1 ; -input [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ; -output [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ; - -wire [0:3] mux_bottom_track_17_undriven_sram_inv ; -wire [0:3] mux_bottom_track_1_undriven_sram_inv ; -wire [0:3] mux_bottom_track_25_undriven_sram_inv ; -wire [0:2] mux_bottom_track_33_undriven_sram_inv ; -wire [0:3] mux_bottom_track_3_undriven_sram_inv ; -wire [0:4] mux_bottom_track_5_undriven_sram_inv ; -wire [0:3] mux_bottom_track_9_undriven_sram_inv ; -wire [0:3] mux_left_track_17_undriven_sram_inv ; -wire [0:3] mux_left_track_1_undriven_sram_inv ; -wire [0:3] mux_left_track_25_undriven_sram_inv ; -wire [0:2] mux_left_track_33_undriven_sram_inv ; -wire [0:3] mux_left_track_3_undriven_sram_inv ; -wire [0:4] mux_left_track_5_undriven_sram_inv ; -wire [0:3] mux_left_track_9_undriven_sram_inv ; -wire [0:3] mux_right_track_0_undriven_sram_inv ; -wire [0:3] mux_right_track_16_undriven_sram_inv ; -wire [0:3] mux_right_track_24_undriven_sram_inv ; -wire [0:3] mux_right_track_2_undriven_sram_inv ; -wire [0:2] mux_right_track_32_undriven_sram_inv ; -wire [0:4] mux_right_track_4_undriven_sram_inv ; -wire [0:3] mux_right_track_8_undriven_sram_inv ; -wire [0:3] mux_top_track_0_undriven_sram_inv ; -wire [0:3] mux_top_track_16_undriven_sram_inv ; -wire [0:3] mux_top_track_24_undriven_sram_inv ; -wire [0:3] mux_top_track_2_undriven_sram_inv ; -wire [0:2] mux_top_track_32_undriven_sram_inv ; -wire [0:4] mux_top_track_4_undriven_sram_inv ; -wire [0:3] mux_top_track_8_undriven_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_10_sram ; -wire [0:3] mux_tree_tapbuf_size10_11_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:3] mux_tree_tapbuf_size10_2_sram ; -wire [0:3] mux_tree_tapbuf_size10_3_sram ; -wire [0:3] mux_tree_tapbuf_size10_4_sram ; -wire [0:3] mux_tree_tapbuf_size10_5_sram ; -wire [0:3] mux_tree_tapbuf_size10_6_sram ; -wire [0:3] mux_tree_tapbuf_size10_7_sram ; -wire [0:3] mux_tree_tapbuf_size10_8_sram ; -wire [0:3] mux_tree_tapbuf_size10_9_sram ; -wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_10_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_11_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_8_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_9_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size12_0_sram ; -wire [0:3] mux_tree_tapbuf_size12_1_sram ; -wire [0:3] mux_tree_tapbuf_size12_2_sram ; -wire [0:3] mux_tree_tapbuf_size12_3_sram ; -wire [0:3] mux_tree_tapbuf_size12_4_sram ; -wire [0:3] mux_tree_tapbuf_size12_5_sram ; -wire [0:3] mux_tree_tapbuf_size12_6_sram ; -wire [0:3] mux_tree_tapbuf_size12_7_sram ; -wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size12_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size12_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail ; -wire [0:4] mux_tree_tapbuf_size16_0_sram ; -wire [0:4] mux_tree_tapbuf_size16_1_sram ; -wire [0:4] mux_tree_tapbuf_size16_2_sram ; -wire [0:4] mux_tree_tapbuf_size16_3_sram ; -wire [0:0] mux_tree_tapbuf_size16_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size16_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size16_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size16_mem_3_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size7_0_sram ; -wire [0:2] mux_tree_tapbuf_size7_1_sram ; -wire [0:2] mux_tree_tapbuf_size7_2_sram ; -wire [0:2] mux_tree_tapbuf_size7_3_sram ; -wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; - -assign clk__FEEDTHRU_1[0] = clk__FEEDTHRU_0[0] ; - -sb_1__1__mux_tree_tapbuf_size12_6 mux_top_track_0 ( - .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , - top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , - chanx_right_in[1] , chanx_right_in[2] , chanx_right_in[12] , - chany_bottom_in[2] , chany_bottom_in[12] , chanx_left_in[0] , - chanx_left_in[2] , chanx_left_in[12] } ) , - .sram ( mux_tree_tapbuf_size12_0_sram ) , - .sram_inv ( mux_top_track_0_undriven_sram_inv ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_145 ) ) ; -sb_1__1__mux_tree_tapbuf_size12 mux_top_track_2 ( - .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , - top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , - chanx_right_in[3] , chanx_right_in[4] , chanx_right_in[13] , - chany_bottom_in[4] , chany_bottom_in[13] , chanx_left_in[4] , - chanx_left_in[13] , chanx_left_in[19] } ) , - .sram ( mux_tree_tapbuf_size12_1_sram ) , - .sram_inv ( mux_top_track_2_undriven_sram_inv ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_149 ) ) ; -sb_1__1__mux_tree_tapbuf_size12_4 mux_right_track_0 ( - .in ( { chany_top_in[2] , chany_top_in[12] , chany_top_in[19] , - right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , - right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , - chany_bottom_in[2] , chany_bottom_in[12] , chany_bottom_in[15] , - chanx_left_in[2] , chanx_left_in[12] } ) , - .sram ( mux_tree_tapbuf_size12_2_sram ) , - .sram_inv ( mux_right_track_0_undriven_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_145 ) ) ; -sb_1__1__mux_tree_tapbuf_size12_5 mux_right_track_2 ( - .in ( { chany_top_in[0] , chany_top_in[4] , chany_top_in[13] , - right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , - right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] , - chany_bottom_in[4] , chany_bottom_in[11] , chany_bottom_in[13] , - chanx_left_in[4] , chanx_left_in[13] } ) , - .sram ( mux_tree_tapbuf_size12_3_sram ) , - .sram_inv ( mux_right_track_2_undriven_sram_inv ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_146 ) ) ; -sb_1__1__mux_tree_tapbuf_size12_0 mux_bottom_track_1 ( - .in ( { chany_top_in[2] , chany_top_in[12] , chanx_right_in[2] , - chanx_right_in[12] , chanx_right_in[15] , - bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , - bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , - chanx_left_in[1] , chanx_left_in[2] , chanx_left_in[12] } ) , - .sram ( mux_tree_tapbuf_size12_4_sram ) , - .sram_inv ( mux_bottom_track_1_undriven_sram_inv ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_147 ) ) ; -sb_1__1__mux_tree_tapbuf_size12_1 mux_bottom_track_3 ( - .in ( { chany_top_in[4] , chany_top_in[13] , chanx_right_in[4] , - chanx_right_in[11] , chanx_right_in[13] , - bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , - bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , - chanx_left_in[3] , chanx_left_in[4] , chanx_left_in[13] } ) , - .sram ( mux_tree_tapbuf_size12_5_sram ) , - .sram_inv ( mux_bottom_track_3_undriven_sram_inv ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_147 ) ) ; -sb_1__1__mux_tree_tapbuf_size12_2 mux_left_track_1 ( - .in ( { chany_top_in[0] , chany_top_in[2] , chany_top_in[12] , - chanx_right_in[2] , chanx_right_in[12] , chany_bottom_in[2] , - chany_bottom_in[12] , chany_bottom_in[19] , - left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , - left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , - .sram ( mux_tree_tapbuf_size12_6_sram ) , - .sram_inv ( mux_left_track_1_undriven_sram_inv ) , - .out ( { ropt_net_158 } ) , - .p0 ( optlc_net_147 ) ) ; -sb_1__1__mux_tree_tapbuf_size12_3 mux_left_track_3 ( - .in ( { chany_top_in[4] , chany_top_in[13] , chany_top_in[19] , - chanx_right_in[4] , chanx_right_in[13] , chany_bottom_in[0] , - chany_bottom_in[4] , chany_bottom_in[13] , - left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , - left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , - .sram ( mux_tree_tapbuf_size12_7_sram ) , - .sram_inv ( mux_left_track_3_undriven_sram_inv ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_148 ) ) ; -sb_1__1__mux_tree_tapbuf_size12_mem_6 mem_top_track_0 ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_0_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size12_mem mem_top_track_2 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_1_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size12_mem_4 mem_right_track_0 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_2_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size12_mem_5 mem_right_track_2 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_3_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size12_mem_0 mem_bottom_track_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_4_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size12_mem_1 mem_bottom_track_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_5_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size12_mem_2 mem_left_track_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_6_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size12_mem_3 mem_left_track_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_7_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size16 mux_top_track_4 ( - .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_43_[0] , - top_left_grid_pin_44_[0] , top_left_grid_pin_45_[0] , - top_left_grid_pin_46_[0] , top_left_grid_pin_47_[0] , - top_left_grid_pin_48_[0] , top_left_grid_pin_49_[0] , - chanx_right_in[5] , chanx_right_in[7] , chanx_right_in[14] , - chany_bottom_in[5] , chany_bottom_in[14] , chanx_left_in[5] , - chanx_left_in[14] , chanx_left_in[15] } ) , - .sram ( mux_tree_tapbuf_size16_0_sram ) , - .sram_inv ( mux_top_track_4_undriven_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_149 ) ) ; -sb_1__1__mux_tree_tapbuf_size16_2 mux_right_track_4 ( - .in ( { chany_top_in[1] , chany_top_in[5] , chany_top_in[14] , - right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_35_[0] , - right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_37_[0] , - right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_39_[0] , - right_bottom_grid_pin_40_[0] , right_bottom_grid_pin_41_[0] , - chany_bottom_in[5] , chany_bottom_in[7] , chany_bottom_in[14] , - chanx_left_in[5] , chanx_left_in[14] } ) , - .sram ( mux_tree_tapbuf_size16_1_sram ) , - .sram_inv ( mux_right_track_4_undriven_sram_inv ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_146 ) ) ; -sb_1__1__mux_tree_tapbuf_size16_0 mux_bottom_track_5 ( - .in ( { chany_top_in[5] , chany_top_in[14] , chanx_right_in[5] , - chanx_right_in[7] , chanx_right_in[14] , bottom_left_grid_pin_42_[0] , - bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_44_[0] , - bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_46_[0] , - bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_48_[0] , - bottom_left_grid_pin_49_[0] , chanx_left_in[5] , chanx_left_in[7] , - chanx_left_in[14] } ) , - .sram ( mux_tree_tapbuf_size16_2_sram ) , - .sram_inv ( mux_bottom_track_5_undriven_sram_inv ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_148 ) ) ; -sb_1__1__mux_tree_tapbuf_size16_1 mux_left_track_5 ( - .in ( { chany_top_in[5] , chany_top_in[14] , chany_top_in[15] , - chanx_right_in[5] , chanx_right_in[14] , chany_bottom_in[1] , - chany_bottom_in[5] , chany_bottom_in[14] , - left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_35_[0] , - left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_37_[0] , - left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_39_[0] , - left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_41_[0] } ) , - .sram ( mux_tree_tapbuf_size16_3_sram ) , - .sram_inv ( mux_left_track_5_undriven_sram_inv ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_148 ) ) ; -sb_1__1__mux_tree_tapbuf_size16_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size16_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size16_0_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size16_mem_2 mem_right_track_4 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size16_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size16_1_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size16_mem_0 mem_bottom_track_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size16_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size16_2_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size16_mem_1 mem_left_track_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size16_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size16_3_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size10 mux_top_track_8 ( - .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_46_[0] , - chanx_right_in[6] , chanx_right_in[11] , chanx_right_in[16] , - chany_bottom_in[6] , chany_bottom_in[16] , chanx_left_in[6] , - chanx_left_in[11] , chanx_left_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_top_track_8_undriven_sram_inv ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_145 ) ) ; -sb_1__1__mux_tree_tapbuf_size10_9 mux_top_track_16 ( - .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_47_[0] , - chanx_right_in[8] , chanx_right_in[15] , chanx_right_in[17] , - chany_bottom_in[8] , chany_bottom_in[17] , chanx_left_in[7] , - chanx_left_in[8] , chanx_left_in[17] } ) , - .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_top_track_16_undriven_sram_inv ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_148 ) ) ; -sb_1__1__mux_tree_tapbuf_size10_10 mux_top_track_24 ( - .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_48_[0] , - chanx_right_in[9] , chanx_right_in[18] , chanx_right_in[19] , - chany_bottom_in[9] , chany_bottom_in[18] , chanx_left_in[3] , - chanx_left_in[9] , chanx_left_in[18] } ) , - .sram ( mux_tree_tapbuf_size10_2_sram ) , - .sram_inv ( mux_top_track_24_undriven_sram_inv ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_145 ) ) ; -sb_1__1__mux_tree_tapbuf_size10_8 mux_right_track_8 ( - .in ( { chany_top_in[3] , chany_top_in[6] , chany_top_in[16] , - right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_38_[0] , - chany_bottom_in[3] , chany_bottom_in[6] , chany_bottom_in[16] , - chanx_left_in[6] , chanx_left_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_3_sram ) , - .sram_inv ( mux_right_track_8_undriven_sram_inv ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_146 ) ) ; -sb_1__1__mux_tree_tapbuf_size10_6 mux_right_track_16 ( - .in ( { chany_top_in[7] , chany_top_in[8] , chany_top_in[17] , - right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_39_[0] , - chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[17] , - chanx_left_in[8] , chanx_left_in[17] } ) , - .sram ( mux_tree_tapbuf_size10_4_sram ) , - .sram_inv ( mux_right_track_16_undriven_sram_inv ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_146 ) ) ; -sb_1__1__mux_tree_tapbuf_size10_7 mux_right_track_24 ( - .in ( { chany_top_in[9] , chany_top_in[11] , chany_top_in[18] , - right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_40_[0] , - chany_bottom_in[0] , chany_bottom_in[9] , chany_bottom_in[18] , - chanx_left_in[9] , chanx_left_in[18] } ) , - .sram ( mux_tree_tapbuf_size10_5_sram ) , - .sram_inv ( mux_right_track_24_undriven_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_145 ) ) ; -sb_1__1__mux_tree_tapbuf_size10_2 mux_bottom_track_9 ( - .in ( { chany_top_in[6] , chany_top_in[16] , chanx_right_in[3] , - chanx_right_in[6] , chanx_right_in[16] , bottom_left_grid_pin_42_[0] , - bottom_left_grid_pin_46_[0] , chanx_left_in[6] , chanx_left_in[11] , - chanx_left_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_6_sram ) , - .sram_inv ( mux_bottom_track_9_undriven_sram_inv ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_147 ) ) ; -sb_1__1__mux_tree_tapbuf_size10_0 mux_bottom_track_17 ( - .in ( { chany_top_in[8] , chany_top_in[17] , chanx_right_in[1] , - chanx_right_in[8] , chanx_right_in[17] , bottom_left_grid_pin_43_[0] , - bottom_left_grid_pin_47_[0] , chanx_left_in[8] , chanx_left_in[15] , - chanx_left_in[17] } ) , - .sram ( mux_tree_tapbuf_size10_7_sram ) , - .sram_inv ( mux_bottom_track_17_undriven_sram_inv ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_146 ) ) ; -sb_1__1__mux_tree_tapbuf_size10_1 mux_bottom_track_25 ( - .in ( { chany_top_in[9] , chany_top_in[18] , chanx_right_in[0] , - chanx_right_in[9] , chanx_right_in[18] , bottom_left_grid_pin_44_[0] , - bottom_left_grid_pin_48_[0] , chanx_left_in[9] , chanx_left_in[18] , - chanx_left_in[19] } ) , - .sram ( mux_tree_tapbuf_size10_8_sram ) , - .sram_inv ( mux_bottom_track_25_undriven_sram_inv ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_145 ) ) ; -sb_1__1__mux_tree_tapbuf_size10_5 mux_left_track_9 ( - .in ( { chany_top_in[6] , chany_top_in[11] , chany_top_in[16] , - chanx_right_in[6] , chanx_right_in[16] , chany_bottom_in[3] , - chany_bottom_in[6] , chany_bottom_in[16] , - left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_38_[0] } ) , - .sram ( mux_tree_tapbuf_size10_9_sram ) , - .sram_inv ( mux_left_track_9_undriven_sram_inv ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_147 ) ) ; -sb_1__1__mux_tree_tapbuf_size10_3 mux_left_track_17 ( - .in ( { chany_top_in[7] , chany_top_in[8] , chany_top_in[17] , - chanx_right_in[8] , chanx_right_in[17] , chany_bottom_in[7] , - chany_bottom_in[8] , chany_bottom_in[17] , - left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_39_[0] } ) , - .sram ( mux_tree_tapbuf_size10_10_sram ) , - .sram_inv ( mux_left_track_17_undriven_sram_inv ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_148 ) ) ; -sb_1__1__mux_tree_tapbuf_size10_4 mux_left_track_25 ( - .in ( { chany_top_in[3] , chany_top_in[9] , chany_top_in[18] , - chanx_right_in[9] , chanx_right_in[18] , chany_bottom_in[9] , - chany_bottom_in[11] , chany_bottom_in[18] , - left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_40_[0] } ) , - .sram ( mux_tree_tapbuf_size10_11_sram ) , - .sram_inv ( mux_left_track_25_undriven_sram_inv ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_147 ) ) ; -sb_1__1__mux_tree_tapbuf_size10_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size16_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size10_mem_9 mem_top_track_16 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size10_mem_10 mem_top_track_24 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size10_mem_8 mem_right_track_8 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size16_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size10_mem_6 mem_right_track_16 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size10_mem_7 mem_right_track_24 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size10_mem_2 mem_bottom_track_9 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size16_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size10_mem_0 mem_bottom_track_17 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size10_mem_1 mem_bottom_track_25 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_8_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size10_mem_5 mem_left_track_9 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size16_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_9_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_9_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size10_mem_3 mem_left_track_17 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_9_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_10_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_10_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size10_mem_4 mem_left_track_25 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_10_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_11_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size7 mux_top_track_32 ( - .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_49_[0] , - chanx_right_in[0] , chanx_right_in[10] , chany_bottom_in[10] , - chanx_left_in[1] , chanx_left_in[10] } ) , - .sram ( mux_tree_tapbuf_size7_0_sram ) , - .sram_inv ( mux_top_track_32_undriven_sram_inv ) , - .out ( chany_top_out[16] ) , .p0 ( optlc_net_145 ) ) ; -sb_1__1__mux_tree_tapbuf_size7_2 mux_right_track_32 ( - .in ( { chany_top_in[10] , chany_top_in[15] , - right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_41_[0] , - chany_bottom_in[10] , chany_bottom_in[19] , chanx_left_in[10] } ) , - .sram ( mux_tree_tapbuf_size7_1_sram ) , - .sram_inv ( mux_right_track_32_undriven_sram_inv ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_146 ) ) ; -sb_1__1__mux_tree_tapbuf_size7_0 mux_bottom_track_33 ( - .in ( { chany_top_in[10] , chanx_right_in[10] , chanx_right_in[19] , - bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_49_[0] , - chanx_left_in[0] , chanx_left_in[10] } ) , - .sram ( mux_tree_tapbuf_size7_2_sram ) , - .sram_inv ( mux_bottom_track_33_undriven_sram_inv ) , - .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_147 ) ) ; -sb_1__1__mux_tree_tapbuf_size7_1 mux_left_track_33 ( - .in ( { chany_top_in[1] , chany_top_in[10] , chanx_right_in[10] , - chany_bottom_in[10] , chany_bottom_in[15] , - left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_41_[0] } ) , - .sram ( mux_tree_tapbuf_size7_3_sram ) , - .sram_inv ( mux_left_track_33_undriven_sram_inv ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_148 ) ) ; -sb_1__1__mux_tree_tapbuf_size7_mem mem_top_track_32 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size7_mem_2 mem_right_track_32 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size7_mem_0 mem_bottom_track_33 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size7_mem_1 mem_left_track_33 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , - .ccff_tail ( { ropt_net_155 } ) , - .mem_out ( mux_tree_tapbuf_size7_3_sram ) ) ; -sky130_fd_sc_hd__conb_1 optlc_140 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_145 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_142 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_146 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__2 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_179 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_top_in[6] ) , - .X ( ropt_net_194 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chany_top_in[8] ) , - .X ( ropt_net_178 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chany_top_in[9] ) , - .X ( ropt_net_170 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_top_in[10] ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chany_top_in[12] ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__8 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_174 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chany_top_in[14] ) , - .X ( ropt_net_196 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__10 ( .A ( chany_top_in[16] ) , - .X ( ropt_net_166 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__11 ( .A ( chany_top_in[17] ) , - .X ( ropt_net_197 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__12 ( .A ( chany_top_in[18] ) , - .X ( ropt_net_189 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_855 ( .A ( ropt_net_200 ) , - .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_144 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_147 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_146 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_148 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , - .HI ( optlc_net_149 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_198 ) ) ; -sky130_fd_sc_hd__clkbuf_1 \prog_clk[0]_bip415 ( .A ( prog_clk[0] ) , - .X ( ctsbuf_net_1151 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_20__19 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_192 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_right_in[12] ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( chanx_left_in[14] ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_23__22 ( .A ( chanx_right_in[14] ) , - .X ( ropt_net_173 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chanx_right_in[16] ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_25__24 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_184 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_26__25 ( .A ( chanx_right_in[18] ) , - .X ( ropt_net_165 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chany_bottom_in[2] ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_28__27 ( .A ( chany_bottom_in[4] ) , - .X ( ropt_net_171 ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_359774 ( .A ( ctsbuf_net_1151 ) , - .X ( prog_clk__FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_802 ( .A ( chanx_left_in[5] ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_856 ( .A ( ropt_net_201 ) , - .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_32__31 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_187 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_33__32 ( .A ( chany_bottom_in[10] ) , - .X ( ropt_net_193 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_154 ) , - .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_35__34 ( .A ( chany_bottom_in[13] ) , - .X ( ropt_net_199 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_804 ( .A ( ropt_net_155 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_37__36 ( .A ( chany_bottom_in[16] ) , - .X ( ropt_net_186 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_858 ( .A ( ropt_net_202 ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_39__38 ( .A ( chany_bottom_in[18] ) , - .X ( ropt_net_182 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( - .A ( Test_en__FEEDTHRU_0[0] ) , .X ( ropt_net_225 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( chanx_right_in[4] ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_807 ( .A ( ropt_net_158 ) , - .X ( ropt_net_224 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_808 ( .A ( chanx_right_in[5] ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( chanx_right_in[2] ) , - .X ( ropt_net_201 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_810 ( .A ( chany_bottom_in[6] ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_46__45 ( .A ( chanx_left_in[10] ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_47__46 ( .A ( chanx_left_in[12] ) , - .X ( ropt_net_185 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_48__47 ( .A ( chanx_left_in[13] ) , - .X ( ropt_net_169 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_811 ( .A ( chany_bottom_in[5] ) , - .X ( ropt_net_227 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_50__49 ( .A ( chanx_left_in[16] ) , - .X ( ropt_net_181 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_51__50 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_183 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_52__51 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_172 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_860 ( .A ( ropt_net_203 ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_812 ( - .A ( chany_bottom_in[17] ) , .X ( ropt_net_226 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_85 ( .A ( chany_top_in[4] ) , - .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_861 ( .A ( ropt_net_204 ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_862 ( .A ( ropt_net_205 ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_88 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_176 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( chanx_left_in[2] ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_165 ) , - .X ( ropt_net_210 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_91 ( .A ( chany_bottom_in[8] ) , - .X ( ropt_net_154 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_863 ( .A ( ropt_net_206 ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_166 ) , - .X ( ropt_net_223 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_167 ) , - .X ( ropt_net_206 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_95 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_180 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_96 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_177 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_97 ( .A ( chanx_left_in[9] ) , - .X ( ropt_net_168 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_864 ( .A ( ropt_net_207 ) , - .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_817 ( .A ( ropt_net_168 ) , - .X ( ropt_net_220 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_169 ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_170 ) , - .X ( ropt_net_208 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_171 ) , - .X ( ropt_net_200 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_172 ) , - .X ( ropt_net_215 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_108 ( .A ( chanx_left_in[4] ) , - .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_173 ) , - .X ( ropt_net_207 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_174 ) , - .X ( ropt_net_216 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_175 ) , - .X ( ropt_net_204 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_119 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_195 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_120 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_191 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_121 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_167 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_122 ( .A ( chany_bottom_in[12] ) , - .X ( ropt_net_188 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_123 ( .A ( chany_bottom_in[14] ) , - .X ( ropt_net_175 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_865 ( .A ( ropt_net_208 ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( ropt_net_176 ) , - .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_867 ( .A ( ropt_net_209 ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_868 ( .A ( ropt_net_210 ) , - .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_826 ( .A ( ropt_net_177 ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_871 ( .A ( ropt_net_211 ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_875 ( .A ( ropt_net_212 ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_876 ( .A ( ropt_net_213 ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_827 ( .A ( ropt_net_178 ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_136 ( - .A ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] ) , - .X ( ropt_net_190 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_179 ) , - .X ( ropt_net_219 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_829 ( .A ( ropt_net_180 ) , - .X ( ropt_net_209 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_181 ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_182 ) , - .X ( ropt_net_214 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_832 ( .A ( ropt_net_183 ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_833 ( .A ( ropt_net_184 ) , - .X ( ropt_net_222 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_834 ( .A ( ropt_net_185 ) , - .X ( ropt_net_218 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_835 ( .A ( ropt_net_186 ) , - .X ( ropt_net_205 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_836 ( .A ( ropt_net_187 ) , - .X ( ropt_net_211 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_837 ( .A ( ropt_net_188 ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_838 ( .A ( ropt_net_189 ) , - .X ( ropt_net_203 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_839 ( .A ( ropt_net_190 ) , - .X ( ropt_net_221 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_840 ( .A ( ropt_net_191 ) , - .X ( ropt_net_212 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_841 ( .A ( ropt_net_192 ) , - .X ( ropt_net_213 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_842 ( .A ( ropt_net_193 ) , - .X ( ropt_net_217 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_843 ( .A ( ropt_net_194 ) , - .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_844 ( .A ( ropt_net_195 ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_845 ( .A ( ropt_net_196 ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_846 ( .A ( ropt_net_197 ) , - .X ( ropt_net_202 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_849 ( .A ( ropt_net_198 ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_851 ( .A ( ropt_net_199 ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_878 ( .A ( ropt_net_214 ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_880 ( .A ( ropt_net_215 ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_881 ( .A ( ropt_net_216 ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_882 ( .A ( ropt_net_217 ) , - .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_883 ( .A ( ropt_net_218 ) , - .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_885 ( .A ( ropt_net_219 ) , - .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_886 ( .A ( ropt_net_220 ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_887 ( .A ( ropt_net_221 ) , - .X ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_888 ( .A ( ropt_net_222 ) , - .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_890 ( .A ( ropt_net_223 ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_893 ( .A ( ropt_net_224 ) , - .X ( chanx_left_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_897 ( .A ( ropt_net_225 ) , - .X ( Test_en__FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_898 ( .A ( ropt_net_226 ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_899 ( .A ( ropt_net_227 ) , - .X ( chany_top_out[6] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__60 ( .A ( mem_out[2] ) , - .X ( net_net_84 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_84 ( .A ( net_net_84 ) , - .X ( net_net_83 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_103 ( .A ( net_net_83 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__59 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__const1 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -sb_1__0__const1 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -endmodule - - -module sb_1__0__const1_26 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -sb_1__0__const1_26 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__58 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__57 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__const1_25 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sb_1__0__const1_25 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module sb_1__0__const1_24 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sb_1__0__const1_24 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size11_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__56 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size11_mem ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__55 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__const1_23 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size11_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:10] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sb_1__0__const1_23 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[10] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -endmodule - - -module sb_1__0__const1_22 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size11 ( in , sram , sram_inv , out , p0 ) ; -input [0:10] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sb_1__0__const1_22 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[10] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__54 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__const1_21 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_1__0__const1_21 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__53 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size3_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__52 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size3_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__51 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__50 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__49 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__48 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__47 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__const1_20 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sb_1__0__const1_20 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_1__0__const1_19 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size3_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sb_1__0__const1_19 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_1__0__const1_18 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size3_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sb_1__0__const1_18 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_1__0__const1_17 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sb_1__0__const1_17 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_1__0__const1_16 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sb_1__0__const1_16 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_1__0__const1_15 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sb_1__0__const1_15 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_1__0__const1_14 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sb_1__0__const1_14 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__46 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__45 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__const1_13 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sb_1__0__const1_13 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -endmodule - - -module sb_1__0__const1_12 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sb_1__0__const1_12 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__44 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__43 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__42 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__41 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__40 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__39 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__38 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__37 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__36 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__const1_11 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sb_1__0__const1_11 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_1__0__const1_10 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sb_1__0__const1_10 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_1__0__const1_9 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sb_1__0__const1_9 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_1__0__const1_8 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sb_1__0__const1_8 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_1__0__const1_7 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sb_1__0__const1_7 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_1__0__const1_6 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sb_1__0__const1_6 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_1__0__const1_5 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sb_1__0__const1_5 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_1__0__const1_4 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_7 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sb_1__0__const1_4 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_1__0__const1_3 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sb_1__0__const1_3 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__35 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__34 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__33 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__const1_2 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sb_1__0__const1_2 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module sb_1__0__const1_1 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sb_1__0__const1_1 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module sb_1__0__const1_0 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sb_1__0__const1_0 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module sb_1__0_ ( prog_clk , chany_top_in , top_left_grid_pin_42_ , - top_left_grid_pin_43_ , top_left_grid_pin_44_ , top_left_grid_pin_45_ , - top_left_grid_pin_46_ , top_left_grid_pin_47_ , top_left_grid_pin_48_ , - top_left_grid_pin_49_ , chanx_right_in , right_bottom_grid_pin_1_ , - right_bottom_grid_pin_3_ , right_bottom_grid_pin_5_ , - right_bottom_grid_pin_7_ , right_bottom_grid_pin_9_ , - right_bottom_grid_pin_11_ , chanx_left_in , left_bottom_grid_pin_1_ , - left_bottom_grid_pin_3_ , left_bottom_grid_pin_5_ , - left_bottom_grid_pin_7_ , left_bottom_grid_pin_9_ , - left_bottom_grid_pin_11_ , ccff_head , chany_top_out , chanx_right_out , - chanx_left_out , ccff_tail , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , - SC_OUT_BOT , prog_clk__FEEDTHRU_1 , prog_clk__FEEDTHRU_2 ) ; -input [0:0] prog_clk ; -input [0:19] chany_top_in ; -input [0:0] top_left_grid_pin_42_ ; -input [0:0] top_left_grid_pin_43_ ; -input [0:0] top_left_grid_pin_44_ ; -input [0:0] top_left_grid_pin_45_ ; -input [0:0] top_left_grid_pin_46_ ; -input [0:0] top_left_grid_pin_47_ ; -input [0:0] top_left_grid_pin_48_ ; -input [0:0] top_left_grid_pin_49_ ; -input [0:19] chanx_right_in ; -input [0:0] right_bottom_grid_pin_1_ ; -input [0:0] right_bottom_grid_pin_3_ ; -input [0:0] right_bottom_grid_pin_5_ ; -input [0:0] right_bottom_grid_pin_7_ ; -input [0:0] right_bottom_grid_pin_9_ ; -input [0:0] right_bottom_grid_pin_11_ ; -input [0:19] chanx_left_in ; -input [0:0] left_bottom_grid_pin_1_ ; -input [0:0] left_bottom_grid_pin_3_ ; -input [0:0] left_bottom_grid_pin_5_ ; -input [0:0] left_bottom_grid_pin_7_ ; -input [0:0] left_bottom_grid_pin_9_ ; -input [0:0] left_bottom_grid_pin_11_ ; -input [0:0] ccff_head ; -output [0:19] chany_top_out ; -output [0:19] chanx_right_out ; -output [0:19] chanx_left_out ; -output [0:0] ccff_tail ; -input SC_IN_TOP ; -input SC_IN_BOT ; -output SC_OUT_TOP ; -output SC_OUT_BOT ; -output [0:0] prog_clk__FEEDTHRU_1 ; -output [0:0] prog_clk__FEEDTHRU_2 ; - -wire [0:2] mux_left_track_17_undriven_sram_inv ; -wire [0:3] mux_left_track_1_undriven_sram_inv ; -wire [0:2] mux_left_track_25_undriven_sram_inv ; -wire [0:2] mux_left_track_33_undriven_sram_inv ; -wire [0:2] mux_left_track_3_undriven_sram_inv ; -wire [0:3] mux_left_track_5_undriven_sram_inv ; -wire [0:2] mux_left_track_9_undriven_sram_inv ; -wire [0:2] mux_right_track_0_undriven_sram_inv ; -wire [0:2] mux_right_track_16_undriven_sram_inv ; -wire [0:2] mux_right_track_24_undriven_sram_inv ; -wire [0:3] mux_right_track_2_undriven_sram_inv ; -wire [0:2] mux_right_track_32_undriven_sram_inv ; -wire [0:3] mux_right_track_4_undriven_sram_inv ; -wire [0:2] mux_right_track_8_undriven_sram_inv ; -wire [0:3] mux_top_track_0_undriven_sram_inv ; -wire [0:2] mux_top_track_10_undriven_sram_inv ; -wire [0:1] mux_top_track_12_undriven_sram_inv ; -wire [0:1] mux_top_track_14_undriven_sram_inv ; -wire [0:1] mux_top_track_16_undriven_sram_inv ; -wire [0:1] mux_top_track_18_undriven_sram_inv ; -wire [0:1] mux_top_track_20_undriven_sram_inv ; -wire [0:1] mux_top_track_22_undriven_sram_inv ; -wire [0:1] mux_top_track_24_undriven_sram_inv ; -wire [0:2] mux_top_track_2_undriven_sram_inv ; -wire [0:1] mux_top_track_38_undriven_sram_inv ; -wire [0:2] mux_top_track_4_undriven_sram_inv ; -wire [0:2] mux_top_track_6_undriven_sram_inv ; -wire [0:2] mux_top_track_8_undriven_sram_inv ; -wire [0:3] mux_tree_tapbuf_size11_0_sram ; -wire [0:3] mux_tree_tapbuf_size11_1_sram ; -wire [0:0] mux_tree_tapbuf_size11_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size11_mem_1_ccff_tail ; -wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; -wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:1] mux_tree_tapbuf_size3_2_sram ; -wire [0:1] mux_tree_tapbuf_size3_3_sram ; -wire [0:1] mux_tree_tapbuf_size3_4_sram ; -wire [0:1] mux_tree_tapbuf_size3_5_sram ; -wire [0:1] mux_tree_tapbuf_size3_6_sram ; -wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size4_0_sram ; -wire [0:2] mux_tree_tapbuf_size4_1_sram ; -wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size5_0_sram ; -wire [0:2] mux_tree_tapbuf_size5_1_sram ; -wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size6_1_sram ; -wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size7_0_sram ; -wire [0:2] mux_tree_tapbuf_size7_1_sram ; -wire [0:2] mux_tree_tapbuf_size7_2_sram ; -wire [0:2] mux_tree_tapbuf_size7_3_sram ; -wire [0:2] mux_tree_tapbuf_size7_4_sram ; -wire [0:2] mux_tree_tapbuf_size7_5_sram ; -wire [0:2] mux_tree_tapbuf_size7_6_sram ; -wire [0:2] mux_tree_tapbuf_size7_7_sram ; -wire [0:2] mux_tree_tapbuf_size7_8_sram ; -wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_7_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_8_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:3] mux_tree_tapbuf_size8_2_sram ; -wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; - -assign SC_IN_TOP = SC_IN_BOT ; -assign prog_clk__FEEDTHRU_1[0] = prog_clk__FEEDTHRU_2[0] ; - -sb_1__0__mux_tree_tapbuf_size8 mux_top_track_0 ( - .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , - top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , - chanx_right_in[1] , chanx_right_in[2] , chanx_left_in[0] , - chanx_left_in[2] } ) , - .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_top_track_0_undriven_sram_inv ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_120 ) ) ; -sb_1__0__mux_tree_tapbuf_size8_1 mux_right_track_2 ( - .in ( { chany_top_in[0] , chany_top_in[7] , chany_top_in[14] , - right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_7_[0] , - right_bottom_grid_pin_11_[0] , chanx_left_in[4] , chanx_left_in[13] } ) , - .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_right_track_2_undriven_sram_inv ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_123 ) ) ; -sb_1__0__mux_tree_tapbuf_size8_0 mux_left_track_1 ( - .in ( { chany_top_in[0] , chany_top_in[7] , chany_top_in[14] , - chanx_right_in[2] , chanx_right_in[12] , left_bottom_grid_pin_1_[0] , - left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] } ) , - .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_left_track_1_undriven_sram_inv ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_120 ) ) ; -sb_1__0__mux_tree_tapbuf_size8_mem mem_top_track_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size8_mem_1 mem_right_track_2 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size8_mem_0 mem_left_track_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size7_6 mux_top_track_2 ( - .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , - top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , - chanx_right_in[3] , chanx_right_in[4] , chanx_left_in[4] } ) , - .sram ( mux_tree_tapbuf_size7_0_sram ) , - .sram_inv ( mux_top_track_2_undriven_sram_inv ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_121 ) ) ; -sb_1__0__mux_tree_tapbuf_size7_7 mux_top_track_4 ( - .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , - top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , - chanx_right_in[5] , chanx_right_in[7] , chanx_left_in[5] } ) , - .sram ( mux_tree_tapbuf_size7_1_sram ) , - .sram_inv ( mux_top_track_4_undriven_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_122 ) ) ; -sb_1__0__mux_tree_tapbuf_size7 mux_top_track_6 ( - .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , - top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , - chanx_right_in[6] , chanx_right_in[11] , chanx_left_in[6] } ) , - .sram ( mux_tree_tapbuf_size7_2_sram ) , - .sram_inv ( mux_top_track_6_undriven_sram_inv ) , - .out ( chany_top_out[3] ) , .p0 ( optlc_net_122 ) ) ; -sb_1__0__mux_tree_tapbuf_size7_3 mux_right_track_0 ( - .in ( { chany_top_in[6] , chany_top_in[13] , right_bottom_grid_pin_1_[0] , - right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] , - chanx_left_in[2] , chanx_left_in[12] } ) , - .sram ( mux_tree_tapbuf_size7_3_sram ) , - .sram_inv ( mux_right_track_0_undriven_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_121 ) ) ; -sb_1__0__mux_tree_tapbuf_size7_5 mux_right_track_8 ( - .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , - right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_9_[0] , - chanx_left_in[6] , chanx_left_in[16] } ) , - .sram ( mux_tree_tapbuf_size7_4_sram ) , - .sram_inv ( mux_right_track_8_undriven_sram_inv ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_124 ) ) ; -sb_1__0__mux_tree_tapbuf_size7_4 mux_right_track_16 ( - .in ( { chany_top_in[3] , chany_top_in[10] , chany_top_in[17] , - right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_11_[0] , - chanx_left_in[8] , chanx_left_in[17] } ) , - .sram ( mux_tree_tapbuf_size7_5_sram ) , - .sram_inv ( mux_right_track_16_undriven_sram_inv ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_124 ) ) ; -sb_1__0__mux_tree_tapbuf_size7_1 mux_left_track_3 ( - .in ( { chany_top_in[6] , chany_top_in[13] , chanx_right_in[4] , - chanx_right_in[13] , left_bottom_grid_pin_3_[0] , - left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] } ) , - .sram ( mux_tree_tapbuf_size7_6_sram ) , - .sram_inv ( mux_left_track_3_undriven_sram_inv ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_120 ) ) ; -sb_1__0__mux_tree_tapbuf_size7_2 mux_left_track_9 ( - .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , - chanx_right_in[6] , chanx_right_in[16] , left_bottom_grid_pin_1_[0] , - left_bottom_grid_pin_9_[0] } ) , - .sram ( mux_tree_tapbuf_size7_7_sram ) , - .sram_inv ( mux_left_track_9_undriven_sram_inv ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_120 ) ) ; -sb_1__0__mux_tree_tapbuf_size7_0 mux_left_track_17 ( - .in ( { chany_top_in[3] , chany_top_in[10] , chany_top_in[17] , - chanx_right_in[8] , chanx_right_in[17] , left_bottom_grid_pin_3_[0] , - left_bottom_grid_pin_11_[0] } ) , - .sram ( mux_tree_tapbuf_size7_8_sram ) , - .sram_inv ( mux_left_track_17_undriven_sram_inv ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_120 ) ) ; -sb_1__0__mux_tree_tapbuf_size7_mem_6 mem_top_track_2 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size7_mem_7 mem_top_track_4 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size7_mem mem_top_track_6 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size7_mem_3 mem_right_track_0 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_3_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size7_mem_5 mem_right_track_8 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size11_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_4_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size7_mem_4 mem_right_track_16 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_5_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size7_mem_1 mem_left_track_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_6_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size7_mem_2 mem_left_track_9 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size11_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_7_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size7_mem_0 mem_left_track_17 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_8_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_8_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size4 mux_top_track_8 ( - .in ( { top_left_grid_pin_42_[0] , chanx_right_in[8] , - chanx_right_in[15] , chanx_left_in[8] } ) , - .sram ( mux_tree_tapbuf_size4_0_sram ) , - .sram_inv ( mux_top_track_8_undriven_sram_inv ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_122 ) ) ; -sb_1__0__mux_tree_tapbuf_size4_0 mux_top_track_10 ( - .in ( { top_left_grid_pin_43_[0] , chanx_right_in[9] , - chanx_right_in[19] , chanx_left_in[9] } ) , - .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_top_track_10_undriven_sram_inv ) , - .out ( chany_top_out[5] ) , .p0 ( optlc_net_124 ) ) ; -sb_1__0__mux_tree_tapbuf_size4_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size4_mem_0 mem_top_track_10 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size3_0 mux_top_track_12 ( - .in ( { top_left_grid_pin_44_[0] , chanx_right_in[10] , - chanx_left_in[10] } ) , - .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_top_track_12_undriven_sram_inv ) , - .out ( chany_top_out[6] ) , .p0 ( optlc_net_121 ) ) ; -sb_1__0__mux_tree_tapbuf_size3_1 mux_top_track_14 ( - .in ( { top_left_grid_pin_45_[0] , chanx_right_in[12] , - chanx_left_in[12] } ) , - .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_top_track_14_undriven_sram_inv ) , - .out ( chany_top_out[7] ) , .p0 ( optlc_net_121 ) ) ; -sb_1__0__mux_tree_tapbuf_size3_2 mux_top_track_16 ( - .in ( { top_left_grid_pin_46_[0] , chanx_right_in[13] , - chanx_left_in[13] } ) , - .sram ( mux_tree_tapbuf_size3_2_sram ) , - .sram_inv ( mux_top_track_16_undriven_sram_inv ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_120 ) ) ; -sb_1__0__mux_tree_tapbuf_size3_3 mux_top_track_18 ( - .in ( { top_left_grid_pin_47_[0] , chanx_right_in[14] , - chanx_left_in[14] } ) , - .sram ( mux_tree_tapbuf_size3_3_sram ) , - .sram_inv ( mux_top_track_18_undriven_sram_inv ) , - .out ( chany_top_out[9] ) , .p0 ( optlc_net_121 ) ) ; -sb_1__0__mux_tree_tapbuf_size3_4 mux_top_track_20 ( - .in ( { top_left_grid_pin_48_[0] , chanx_right_in[16] , - chanx_left_in[16] } ) , - .sram ( mux_tree_tapbuf_size3_4_sram ) , - .sram_inv ( mux_top_track_20_undriven_sram_inv ) , - .out ( chany_top_out[10] ) , .p0 ( optlc_net_122 ) ) ; -sb_1__0__mux_tree_tapbuf_size3_5 mux_top_track_22 ( - .in ( { top_left_grid_pin_49_[0] , chanx_right_in[17] , - chanx_left_in[17] } ) , - .sram ( mux_tree_tapbuf_size3_5_sram ) , - .sram_inv ( mux_top_track_22_undriven_sram_inv ) , - .out ( chany_top_out[11] ) , .p0 ( optlc_net_122 ) ) ; -sb_1__0__mux_tree_tapbuf_size3 mux_top_track_24 ( - .in ( { top_left_grid_pin_42_[0] , chanx_right_in[18] , - chanx_left_in[18] } ) , - .sram ( mux_tree_tapbuf_size3_6_sram ) , - .sram_inv ( mux_top_track_24_undriven_sram_inv ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_121 ) ) ; -sb_1__0__mux_tree_tapbuf_size3_mem_0 mem_top_track_12 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size3_mem_1 mem_top_track_14 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size3_mem_2 mem_top_track_16 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size3_mem_3 mem_top_track_18 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size3_mem_4 mem_top_track_20 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_4_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size3_mem_5 mem_top_track_22 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_5_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size3_mem mem_top_track_24 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_6_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size2 mux_top_track_38 ( - .in ( { chanx_right_in[0] , chanx_left_in[1] } ) , - .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_top_track_38_undriven_sram_inv ) , - .out ( chany_top_out[19] ) , .p0 ( optlc_net_121 ) ) ; -sb_1__0__mux_tree_tapbuf_size2_mem mem_top_track_38 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size11 mux_right_track_4 ( - .in ( { chany_top_in[1] , chany_top_in[8] , chany_top_in[15] , - right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_3_[0] , - right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_7_[0] , - right_bottom_grid_pin_9_[0] , right_bottom_grid_pin_11_[0] , - chanx_left_in[5] , chanx_left_in[14] } ) , - .sram ( mux_tree_tapbuf_size11_0_sram ) , - .sram_inv ( mux_right_track_4_undriven_sram_inv ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_123 ) ) ; -sb_1__0__mux_tree_tapbuf_size11_0 mux_left_track_5 ( - .in ( { chany_top_in[5] , chany_top_in[12] , chany_top_in[19] , - chanx_right_in[5] , chanx_right_in[14] , left_bottom_grid_pin_1_[0] , - left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_5_[0] , - left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_9_[0] , - left_bottom_grid_pin_11_[0] } ) , - .sram ( mux_tree_tapbuf_size11_1_sram ) , - .sram_inv ( mux_left_track_5_undriven_sram_inv ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_120 ) ) ; -sb_1__0__mux_tree_tapbuf_size11_mem mem_right_track_4 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size11_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size11_0_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size11_mem_0 mem_left_track_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size11_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size11_1_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size6 mux_right_track_24 ( - .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , - right_bottom_grid_pin_5_[0] , chanx_left_in[9] , chanx_left_in[18] } ) , - .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_right_track_24_undriven_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_124 ) ) ; -sb_1__0__mux_tree_tapbuf_size6_0 mux_left_track_25 ( - .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , - chanx_right_in[9] , chanx_right_in[18] , left_bottom_grid_pin_5_[0] } ) , - .sram ( mux_tree_tapbuf_size6_1_sram ) , - .sram_inv ( mux_left_track_25_undriven_sram_inv ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_122 ) ) ; -sb_1__0__mux_tree_tapbuf_size6_mem mem_right_track_24 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size6_mem_0 mem_left_track_25 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_8_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size5 mux_right_track_32 ( - .in ( { chany_top_in[5] , chany_top_in[12] , chany_top_in[19] , - right_bottom_grid_pin_7_[0] , chanx_left_in[10] } ) , - .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_right_track_32_undriven_sram_inv ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_121 ) ) ; -sb_1__0__mux_tree_tapbuf_size5_0 mux_left_track_33 ( - .in ( { chany_top_in[1] , chany_top_in[8] , chany_top_in[15] , - chanx_right_in[10] , left_bottom_grid_pin_7_[0] } ) , - .sram ( mux_tree_tapbuf_size5_1_sram ) , - .sram_inv ( mux_left_track_33_undriven_sram_inv ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_120 ) ) ; -sb_1__0__mux_tree_tapbuf_size5_mem mem_right_track_32 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size5_mem_0 mem_left_track_33 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .ccff_tail ( { ropt_net_147 } ) , - .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ; -sky130_fd_sc_hd__conb_1 optlc_114 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_120 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chanx_right_in[2] ) , - .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_145 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__3 ( .A ( chanx_right_in[5] ) , - .X ( ropt_net_154 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_121 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_161 ) , - .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_122 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_121 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_123 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__8 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_158 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_162 ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__10 ( .A ( chanx_right_in[14] ) , - .X ( ropt_net_151 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_123 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , - .HI ( optlc_net_124 ) ) ; -sky130_fd_sc_hd__clkbuf_1 \prog_clk[0]_bip390 ( .A ( prog_clk[0] ) , - .X ( \prog_clk__FEEDTHRU_2[0]0 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( .A ( ropt_net_129 ) , - .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chanx_left_in[2] ) , - .X ( ropt_net_152 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_165 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( chanx_left_in[19] ) , - .X ( ropt_net_169 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chanx_left_in[5] ) , - .X ( ropt_net_150 ) ) ; -sky130_fd_sc_hd__buf_8 cts_buf_368758 ( .A ( \prog_clk__FEEDTHRU_2[0]0 ) , - .X ( prog_clk__FEEDTHRU_2[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_784 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_179 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_785 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_175 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__21 ( .A ( chanx_left_in[9] ) , - .X ( ropt_net_148 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chanx_left_in[10] ) , - .X ( ropt_net_155 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_134 ) , - .X ( ropt_net_171 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_787 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_176 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_788 ( .A ( chanx_left_in[12] ) , - .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_137 ) , - .X ( ropt_net_163 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( chanx_right_in[18] ) , - .X ( ropt_net_174 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_821 ( .A ( ropt_net_163 ) , - .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_822 ( .A ( ropt_net_164 ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( chanx_left_in[13] ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( chanx_left_in[16] ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_129 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( chanx_right_in[6] ) , - .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_178 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_823 ( .A ( ropt_net_165 ) , - .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_166 ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_825 ( .A ( ropt_net_167 ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_826 ( .A ( ropt_net_168 ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_70 ( .A ( chanx_left_in[3] ) , - .X ( ropt_net_143 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_71 ( .A ( chanx_left_in[4] ) , - .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_72 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_157 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_73 ( .A ( chanx_left_in[7] ) , - .X ( ropt_net_160 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_74 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_156 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_75 ( .A ( chanx_left_in[11] ) , - .X ( ropt_net_137 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_827 ( .A ( ropt_net_169 ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_170 ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_78 ( .A ( chanx_left_in[14] ) , - .X ( ropt_net_159 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_79 ( .A ( chanx_left_in[15] ) , - .X ( ropt_net_146 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_143 ) , - .X ( ropt_net_164 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_830 ( .A ( ropt_net_171 ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_832 ( .A ( ropt_net_172 ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_177 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( ropt_net_145 ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_146 ) , - .X ( ropt_net_167 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_147 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_148 ) , - .X ( ropt_net_172 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_149 ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_150 ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_833 ( .A ( ropt_net_173 ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_99 ( .A ( top_left_grid_pin_43_[0] ) , - .X ( ropt_net_149 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_837 ( .A ( ropt_net_174 ) , - .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_151 ) , - .X ( ropt_net_161 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_105 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_153 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_152 ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_107 ( .A ( chanx_right_in[16] ) , - .X ( ropt_net_134 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_153 ) , - .X ( ropt_net_162 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_154 ) , - .X ( ropt_net_166 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_155 ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_156 ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_157 ) , - .X ( ropt_net_173 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_810 ( .A ( ropt_net_158 ) , - .X ( ropt_net_170 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_159 ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_160 ) , - .X ( ropt_net_168 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_838 ( .A ( ropt_net_175 ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_839 ( .A ( ropt_net_176 ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_840 ( .A ( ropt_net_177 ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_841 ( .A ( ropt_net_178 ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_842 ( .A ( ropt_net_179 ) , - .X ( chanx_right_out[19] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_24__40 ( .A ( mem_out[1] ) , - .X ( net_net_64 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_89 ( .A ( net_net_64 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__39 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__38 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__37 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__36 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__35 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__34 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__33 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__32 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__31 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__30 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__29 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__28 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__27 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__26 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__25 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__24 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__23 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__const1 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_0__2__const1 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__2__const1_22 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_0__2__const1_22 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__2__const1_21 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_0__2__const1_21 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__2__const1_20 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_0__2__const1_20 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__2__const1_19 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_0__2__const1_19 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__2__const1_18 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_0__2__const1_18 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__2__const1_17 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_0__2__const1_17 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__2__const1_16 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -sb_0__2__const1_16 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_0__2__const1_15 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_0__2__const1_15 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__2__const1_14 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -sb_0__2__const1_14 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_0__2__const1_13 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_0__2__const1_13 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__2__const1_12 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_0__2__const1_12 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__2__const1_11 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_0__2__const1_11 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__2__const1_10 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_0__2__const1_10 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__2__const1_9 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_0__2__const1_9 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_43 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_0__2__const1_8 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_0__2__const1_8 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__2__const1_7 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_0__2__const1_7 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__2__const1_6 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_0__2__const1_6 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__22 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__21 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__const1_5 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sb_0__2__const1_5 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_0__2__const1_4 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sb_0__2__const1_4 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__20 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__19 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__const1_3 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -sb_0__2__const1_3 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -endmodule - - -module sb_0__2__const1_2 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -sb_0__2__const1_2 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__18 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__17 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__const1_1 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sb_0__2__const1_1 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module sb_0__2__const1_0 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sb_0__2__const1_0 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module sb_0__2_ ( prog_clk , chanx_right_in , right_top_grid_pin_1_ , - right_bottom_grid_pin_34_ , right_bottom_grid_pin_35_ , - right_bottom_grid_pin_36_ , right_bottom_grid_pin_37_ , - right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ , - right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ , chany_bottom_in , - bottom_left_grid_pin_1_ , ccff_head , chanx_right_out , chany_bottom_out , - ccff_tail , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , SC_OUT_BOT ) ; -input [0:0] prog_clk ; -input [0:19] chanx_right_in ; -input [0:0] right_top_grid_pin_1_ ; -input [0:0] right_bottom_grid_pin_34_ ; -input [0:0] right_bottom_grid_pin_35_ ; -input [0:0] right_bottom_grid_pin_36_ ; -input [0:0] right_bottom_grid_pin_37_ ; -input [0:0] right_bottom_grid_pin_38_ ; -input [0:0] right_bottom_grid_pin_39_ ; -input [0:0] right_bottom_grid_pin_40_ ; -input [0:0] right_bottom_grid_pin_41_ ; -input [0:19] chany_bottom_in ; -input [0:0] bottom_left_grid_pin_1_ ; -input [0:0] ccff_head ; -output [0:19] chanx_right_out ; -output [0:19] chany_bottom_out ; -output [0:0] ccff_tail ; -input SC_IN_TOP ; -input SC_IN_BOT ; -output SC_OUT_TOP ; -output SC_OUT_BOT ; - -wire [0:1] mux_bottom_track_1_undriven_sram_inv ; -wire [0:1] mux_bottom_track_25_undriven_sram_inv ; -wire [0:1] mux_bottom_track_5_undriven_sram_inv ; -wire [0:1] mux_bottom_track_9_undriven_sram_inv ; -wire [0:2] mux_right_track_0_undriven_sram_inv ; -wire [0:1] mux_right_track_10_undriven_sram_inv ; -wire [0:1] mux_right_track_12_undriven_sram_inv ; -wire [0:1] mux_right_track_14_undriven_sram_inv ; -wire [0:1] mux_right_track_16_undriven_sram_inv ; -wire [0:1] mux_right_track_18_undriven_sram_inv ; -wire [0:1] mux_right_track_20_undriven_sram_inv ; -wire [0:1] mux_right_track_22_undriven_sram_inv ; -wire [0:1] mux_right_track_24_undriven_sram_inv ; -wire [0:1] mux_right_track_26_undriven_sram_inv ; -wire [0:1] mux_right_track_28_undriven_sram_inv ; -wire [0:2] mux_right_track_2_undriven_sram_inv ; -wire [0:1] mux_right_track_30_undriven_sram_inv ; -wire [0:1] mux_right_track_32_undriven_sram_inv ; -wire [0:1] mux_right_track_34_undriven_sram_inv ; -wire [0:1] mux_right_track_36_undriven_sram_inv ; -wire [0:1] mux_right_track_38_undriven_sram_inv ; -wire [0:2] mux_right_track_4_undriven_sram_inv ; -wire [0:2] mux_right_track_6_undriven_sram_inv ; -wire [0:1] mux_right_track_8_undriven_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_10_sram ; -wire [0:1] mux_tree_tapbuf_size2_11_sram ; -wire [0:1] mux_tree_tapbuf_size2_12_sram ; -wire [0:1] mux_tree_tapbuf_size2_13_sram ; -wire [0:1] mux_tree_tapbuf_size2_14_sram ; -wire [0:1] mux_tree_tapbuf_size2_15_sram ; -wire [0:1] mux_tree_tapbuf_size2_16_sram ; -wire [0:1] mux_tree_tapbuf_size2_17_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_5_sram ; -wire [0:1] mux_tree_tapbuf_size2_6_sram ; -wire [0:1] mux_tree_tapbuf_size2_7_sram ; -wire [0:1] mux_tree_tapbuf_size2_8_sram ; -wire [0:1] mux_tree_tapbuf_size2_9_sram ; -wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; -wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size5_0_sram ; -wire [0:2] mux_tree_tapbuf_size5_1_sram ; -wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size6_1_sram ; -wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; - -assign SC_IN_TOP = SC_IN_BOT ; - -sb_0__2__mux_tree_tapbuf_size6_0 mux_right_track_0 ( - .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] , - right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , - right_bottom_grid_pin_41_[0] , chany_bottom_in[18] } ) , - .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_right_track_0_undriven_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_114 ) ) ; -sb_0__2__mux_tree_tapbuf_size6 mux_right_track_4 ( - .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] , - right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , - right_bottom_grid_pin_41_[0] , chany_bottom_in[16] } ) , - .sram ( mux_tree_tapbuf_size6_1_sram ) , - .sram_inv ( mux_right_track_4_undriven_sram_inv ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_115 ) ) ; -sb_0__2__mux_tree_tapbuf_size6_mem_0 mem_right_track_0 ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size6_mem mem_right_track_4 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size5_0 mux_right_track_2 ( - .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , - right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , - chany_bottom_in[17] } ) , - .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_right_track_2_undriven_sram_inv ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_116 ) ) ; -sb_0__2__mux_tree_tapbuf_size5 mux_right_track_6 ( - .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , - right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , - chany_bottom_in[15] } ) , - .sram ( mux_tree_tapbuf_size5_1_sram ) , - .sram_inv ( mux_right_track_6_undriven_sram_inv ) , - .out ( chanx_right_out[3] ) , .p0 ( optlc_net_116 ) ) ; -sb_0__2__mux_tree_tapbuf_size5_mem_0 mem_right_track_2 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size5_mem mem_right_track_6 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size3 mux_right_track_8 ( - .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_41_[0] , - chany_bottom_in[14] } ) , - .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_right_track_8_undriven_sram_inv ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_116 ) ) ; -sb_0__2__mux_tree_tapbuf_size3_0 mux_right_track_24 ( - .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_41_[0] , - chany_bottom_in[6] } ) , - .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_right_track_24_undriven_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_116 ) ) ; -sb_0__2__mux_tree_tapbuf_size3_mem mem_right_track_8 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size3_mem_0 mem_right_track_24 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size2_4 mux_right_track_10 ( - .in ( { right_bottom_grid_pin_34_[0] , chany_bottom_in[13] } ) , - .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_right_track_10_undriven_sram_inv ) , - .out ( chanx_right_out[5] ) , .p0 ( optlc_net_116 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_5 mux_right_track_12 ( - .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[12] } ) , - .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_right_track_12_undriven_sram_inv ) , - .out ( chanx_right_out[6] ) , .p0 ( optlc_net_114 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_6 mux_right_track_14 ( - .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[11] } ) , - .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_right_track_14_undriven_sram_inv ) , - .out ( chanx_right_out[7] ) , .p0 ( optlc_net_115 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_7 mux_right_track_16 ( - .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[10] } ) , - .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_right_track_16_undriven_sram_inv ) , - .out ( { ropt_net_125 } ) , - .p0 ( optlc_net_117 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_8 mux_right_track_18 ( - .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[9] } ) , - .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_right_track_18_undriven_sram_inv ) , - .out ( chanx_right_out[9] ) , .p0 ( optlc_net_117 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_9 mux_right_track_20 ( - .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[8] } ) , - .sram ( mux_tree_tapbuf_size2_5_sram ) , - .sram_inv ( mux_right_track_20_undriven_sram_inv ) , - .out ( chanx_right_out[10] ) , .p0 ( optlc_net_114 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_10 mux_right_track_22 ( - .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[7] } ) , - .sram ( mux_tree_tapbuf_size2_6_sram ) , - .sram_inv ( mux_right_track_22_undriven_sram_inv ) , - .out ( chanx_right_out[11] ) , .p0 ( optlc_net_114 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_11 mux_right_track_26 ( - .in ( { right_bottom_grid_pin_34_[0] , chany_bottom_in[5] } ) , - .sram ( mux_tree_tapbuf_size2_7_sram ) , - .sram_inv ( mux_right_track_26_undriven_sram_inv ) , - .out ( chanx_right_out[13] ) , .p0 ( optlc_net_115 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_12 mux_right_track_28 ( - .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[4] } ) , - .sram ( mux_tree_tapbuf_size2_8_sram ) , - .sram_inv ( mux_right_track_28_undriven_sram_inv ) , - .out ( { ropt_net_122 } ) , - .p0 ( optlc_net_117 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_13 mux_right_track_30 ( - .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[3] } ) , - .sram ( mux_tree_tapbuf_size2_9_sram ) , - .sram_inv ( mux_right_track_30_undriven_sram_inv ) , - .out ( chanx_right_out[15] ) , .p0 ( optlc_net_117 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_14 mux_right_track_32 ( - .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[2] } ) , - .sram ( mux_tree_tapbuf_size2_10_sram ) , - .sram_inv ( mux_right_track_32_undriven_sram_inv ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_117 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_15 mux_right_track_34 ( - .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[1] } ) , - .sram ( mux_tree_tapbuf_size2_11_sram ) , - .sram_inv ( mux_right_track_34_undriven_sram_inv ) , - .out ( chanx_right_out[17] ) , .p0 ( optlc_net_117 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_16 mux_right_track_36 ( - .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[0] } ) , - .sram ( mux_tree_tapbuf_size2_12_sram ) , - .sram_inv ( mux_right_track_36_undriven_sram_inv ) , - .out ( chanx_right_out[18] ) , .p0 ( optlc_net_114 ) ) ; -sb_0__2__mux_tree_tapbuf_size2 mux_right_track_38 ( - .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[19] } ) , - .sram ( mux_tree_tapbuf_size2_13_sram ) , - .sram_inv ( mux_right_track_38_undriven_sram_inv ) , - .out ( chanx_right_out[19] ) , .p0 ( optlc_net_114 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_0 mux_bottom_track_1 ( - .in ( { chanx_right_in[18] , bottom_left_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size2_14_sram ) , - .sram_inv ( mux_bottom_track_1_undriven_sram_inv ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_114 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_2 mux_bottom_track_5 ( - .in ( { chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size2_15_sram ) , - .sram_inv ( mux_bottom_track_5_undriven_sram_inv ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_114 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_3 mux_bottom_track_9 ( - .in ( { chanx_right_in[14] , bottom_left_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size2_16_sram ) , - .sram_inv ( mux_bottom_track_9_undriven_sram_inv ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_114 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_1 mux_bottom_track_25 ( - .in ( { chanx_right_in[6] , bottom_left_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size2_17_sram ) , - .sram_inv ( mux_bottom_track_25_undriven_sram_inv ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_116 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_4 mem_right_track_10 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_5 mem_right_track_12 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_6 mem_right_track_14 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_7 mem_right_track_16 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_8 mem_right_track_18 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_9 mem_right_track_20 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_10 mem_right_track_22 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_11 mem_right_track_26 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_12 mem_right_track_28 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_13 mem_right_track_30 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_14 mem_right_track_32 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_15 mem_right_track_34 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_11_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_16 mem_right_track_36 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_12_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem mem_right_track_38 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_13_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_0 mem_bottom_track_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_14_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_2 mem_bottom_track_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_15_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_3 mem_bottom_track_9 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_16_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_1 mem_bottom_track_25 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_17_sram ) ) ; -sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_114 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_115 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_116 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_113 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_117 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_716 ( .A ( chanx_right_in[3] ) , - .X ( ropt_net_138 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_717 ( .A ( ropt_net_120 ) , - .X ( ropt_net_145 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_718 ( .A ( chanx_right_in[12] ) , - .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_122 ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_123 ) , - .X ( ropt_net_144 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( ropt_net_136 ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_137 ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_721 ( .A ( chanx_right_in[2] ) , - .X ( chany_bottom_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_138 ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_125 ) , - .X ( ropt_net_142 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_723 ( .A ( chanx_right_in[17] ) , - .X ( chany_bottom_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_724 ( .A ( ropt_net_127 ) , - .X ( ropt_net_140 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_17__16 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_120 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( chanx_right_in[19] ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( chanx_right_in[11] ) , - .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_741 ( .A ( ropt_net_139 ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_140 ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_744 ( .A ( ropt_net_141 ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_52 ( .A ( chanx_right_in[5] ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_746 ( .A ( ropt_net_142 ) , - .X ( chanx_right_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_747 ( .A ( ropt_net_143 ) , - .X ( chany_bottom_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_748 ( .A ( ropt_net_144 ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( .A ( ropt_net_145 ) , - .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_59 ( .A ( chanx_right_in[13] ) , - .X ( BUF_net_59 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_60 ( .A ( chanx_right_in[15] ) , - .X ( BUF_net_60 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( ropt_net_130 ) , - .X ( ropt_net_136 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( .A ( ropt_net_131 ) , - .X ( ropt_net_137 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( chanx_right_in[7] ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_133 ) , - .X ( ropt_net_141 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_86 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_143 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_88 ( .A ( BUF_net_59 ) , - .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_92 ( .A ( chanx_right_in[0] ) , - .X ( ropt_net_133 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_93 ( .A ( chanx_right_in[1] ) , - .X ( ropt_net_131 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_96 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_127 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_99 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_123 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_100 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_130 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_102 ( .A ( BUF_net_60 ) , - .X ( ropt_net_139 ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__59 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__58 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__57 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__56 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__55 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__54 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__const1 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_0__1__const1 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__1__const1_31 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_0__1__const1_31 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__1__const1_30 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -sb_0__1__const1_30 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_0__1__const1_29 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_0__1__const1_29 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__1__const1_28 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_0__1__const1_28 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__1__const1_27 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_0__1__const1_27 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_127 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_27__53 ( .A ( mem_out[1] ) , - .X ( net_net_86 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_85 ( .A ( net_net_86 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__52 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__51 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__50 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__49 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__const1_26 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sb_0__1__const1_26 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_0__1__const1_25 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sb_0__1__const1_25 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_0__1__const1_24 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sb_0__1__const1_24 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_0__1__const1_23 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sb_0__1__const1_23 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_0__1__const1_22 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sb_0__1__const1_22 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__48 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__47 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__46 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__const1_21 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sb_0__1__const1_21 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_0__1__const1_20 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sb_0__1__const1_20 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_0__1__const1_19 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sb_0__1__const1_19 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size4_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__45 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__44 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__43 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__42 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size4_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__41 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__40 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size4_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__39 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__const1_18 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sb_0__1__const1_18 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -endmodule - - -module sb_0__1__const1_17 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sb_0__1__const1_17 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_126 ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_0__1__const1_16 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sb_0__1__const1_16 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -endmodule - - -module sb_0__1__const1_15 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sb_0__1__const1_15 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -endmodule - - -module sb_0__1__const1_14 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sb_0__1__const1_14 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_65 ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_0__1__const1_13 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sb_0__1__const1_13 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -endmodule - - -module sb_0__1__const1_12 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size4_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sb_0__1__const1_12 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_124 ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size5_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__38 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__37 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size5_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__36 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size5_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__35 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__34 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__const1_11 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -sb_0__1__const1_11 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -endmodule - - -module sb_0__1__const1_10 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -sb_0__1__const1_10 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -endmodule - - -module sb_0__1__const1_9 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -sb_0__1__const1_9 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -endmodule - - -module sb_0__1__const1_8 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size5_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -sb_0__1__const1_8 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -endmodule - - -module sb_0__1__const1_7 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -sb_0__1__const1_7 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_63 ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( BUF_net_63 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_123 ( .A ( BUF_net_63 ) , - .X ( out[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__33 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__32 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__31 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__30 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__29 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__28 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__27 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__const1_6 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sb_0__1__const1_6 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module sb_0__1__const1_5 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sb_0__1__const1_5 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_62 ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( BUF_net_62 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_122 ( .A ( BUF_net_62 ) , - .X ( out[0] ) ) ; -endmodule - - -module sb_0__1__const1_4 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sb_0__1__const1_4 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module sb_0__1__const1_3 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sb_0__1__const1_3 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module sb_0__1__const1_2 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -sb_0__1__const1_2 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_0__1__const1_1 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sb_0__1__const1_1 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module sb_0__1__const1_0 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sb_0__1__const1_0 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module sb_0__1_ ( prog_clk , chany_top_in , top_left_grid_pin_1_ , - chanx_right_in , right_bottom_grid_pin_34_ , right_bottom_grid_pin_35_ , - right_bottom_grid_pin_36_ , right_bottom_grid_pin_37_ , - right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ , - right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ , chany_bottom_in , - bottom_left_grid_pin_1_ , ccff_head , chany_top_out , chanx_right_out , - chany_bottom_out , ccff_tail , prog_clk__FEEDTHRU_1 ) ; -input [0:0] prog_clk ; -input [0:19] chany_top_in ; -input [0:0] top_left_grid_pin_1_ ; -input [0:19] chanx_right_in ; -input [0:0] right_bottom_grid_pin_34_ ; -input [0:0] right_bottom_grid_pin_35_ ; -input [0:0] right_bottom_grid_pin_36_ ; -input [0:0] right_bottom_grid_pin_37_ ; -input [0:0] right_bottom_grid_pin_38_ ; -input [0:0] right_bottom_grid_pin_39_ ; -input [0:0] right_bottom_grid_pin_40_ ; -input [0:0] right_bottom_grid_pin_41_ ; -input [0:19] chany_bottom_in ; -input [0:0] bottom_left_grid_pin_1_ ; -input [0:0] ccff_head ; -output [0:19] chany_top_out ; -output [0:19] chanx_right_out ; -output [0:19] chany_bottom_out ; -output [0:0] ccff_tail ; -output [0:0] prog_clk__FEEDTHRU_1 ; - -wire [0:2] mux_bottom_track_17_undriven_sram_inv ; -wire [0:2] mux_bottom_track_1_undriven_sram_inv ; -wire [0:2] mux_bottom_track_25_undriven_sram_inv ; -wire [0:1] mux_bottom_track_33_undriven_sram_inv ; -wire [0:2] mux_bottom_track_3_undriven_sram_inv ; -wire [0:2] mux_bottom_track_5_undriven_sram_inv ; -wire [0:2] mux_bottom_track_9_undriven_sram_inv ; -wire [0:2] mux_right_track_0_undriven_sram_inv ; -wire [0:2] mux_right_track_10_undriven_sram_inv ; -wire [0:2] mux_right_track_12_undriven_sram_inv ; -wire [0:2] mux_right_track_14_undriven_sram_inv ; -wire [0:1] mux_right_track_16_undriven_sram_inv ; -wire [0:1] mux_right_track_18_undriven_sram_inv ; -wire [0:1] mux_right_track_20_undriven_sram_inv ; -wire [0:1] mux_right_track_22_undriven_sram_inv ; -wire [0:2] mux_right_track_24_undriven_sram_inv ; -wire [0:1] mux_right_track_26_undriven_sram_inv ; -wire [0:1] mux_right_track_28_undriven_sram_inv ; -wire [0:2] mux_right_track_2_undriven_sram_inv ; -wire [0:1] mux_right_track_30_undriven_sram_inv ; -wire [0:1] mux_right_track_32_undriven_sram_inv ; -wire [0:1] mux_right_track_34_undriven_sram_inv ; -wire [0:1] mux_right_track_36_undriven_sram_inv ; -wire [0:2] mux_right_track_4_undriven_sram_inv ; -wire [0:2] mux_right_track_6_undriven_sram_inv ; -wire [0:2] mux_right_track_8_undriven_sram_inv ; -wire [0:2] mux_top_track_0_undriven_sram_inv ; -wire [0:2] mux_top_track_16_undriven_sram_inv ; -wire [0:2] mux_top_track_24_undriven_sram_inv ; -wire [0:2] mux_top_track_2_undriven_sram_inv ; -wire [0:2] mux_top_track_32_undriven_sram_inv ; -wire [0:2] mux_top_track_4_undriven_sram_inv ; -wire [0:2] mux_top_track_8_undriven_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_5_sram ; -wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; -wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:1] mux_tree_tapbuf_size3_2_sram ; -wire [0:1] mux_tree_tapbuf_size3_3_sram ; -wire [0:1] mux_tree_tapbuf_size3_4_sram ; -wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size4_0_sram ; -wire [0:2] mux_tree_tapbuf_size4_1_sram ; -wire [0:2] mux_tree_tapbuf_size4_2_sram ; -wire [0:2] mux_tree_tapbuf_size4_3_sram ; -wire [0:2] mux_tree_tapbuf_size4_4_sram ; -wire [0:2] mux_tree_tapbuf_size4_5_sram ; -wire [0:2] mux_tree_tapbuf_size4_6_sram ; -wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_6_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size5_0_sram ; -wire [0:2] mux_tree_tapbuf_size5_1_sram ; -wire [0:2] mux_tree_tapbuf_size5_2_sram ; -wire [0:2] mux_tree_tapbuf_size5_3_sram ; -wire [0:2] mux_tree_tapbuf_size5_4_sram ; -wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size6_1_sram ; -wire [0:2] mux_tree_tapbuf_size6_2_sram ; -wire [0:2] mux_tree_tapbuf_size6_3_sram ; -wire [0:2] mux_tree_tapbuf_size6_4_sram ; -wire [0:2] mux_tree_tapbuf_size6_5_sram ; -wire [0:2] mux_tree_tapbuf_size6_6_sram ; -wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_6_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size7_0_sram ; -wire [0:2] mux_tree_tapbuf_size7_1_sram ; -wire [0:2] mux_tree_tapbuf_size7_2_sram ; -wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; - -sb_0__1__mux_tree_tapbuf_size6_4 mux_top_track_0 ( - .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] , chanx_right_in[8] , - chanx_right_in[15] , chany_bottom_in[2] , chany_bottom_in[12] } ) , - .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_top_track_0_undriven_sram_inv ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_156 ) ) ; -sb_0__1__mux_tree_tapbuf_size6_5 mux_top_track_4 ( - .in ( { top_left_grid_pin_1_[0] , chanx_right_in[3] , chanx_right_in[10] , - chanx_right_in[17] , chany_bottom_in[5] , chany_bottom_in[14] } ) , - .sram ( mux_tree_tapbuf_size6_1_sram ) , - .sram_inv ( mux_top_track_4_undriven_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_156 ) ) ; -sb_0__1__mux_tree_tapbuf_size6 mux_top_track_8 ( - .in ( { top_left_grid_pin_1_[0] , chanx_right_in[4] , chanx_right_in[11] , - chanx_right_in[18] , chany_bottom_in[6] , chany_bottom_in[16] } ) , - .sram ( mux_tree_tapbuf_size6_2_sram ) , - .sram_inv ( mux_top_track_8_undriven_sram_inv ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_157 ) ) ; -sb_0__1__mux_tree_tapbuf_size6_3 mux_right_track_0 ( - .in ( { chany_top_in[2] , right_bottom_grid_pin_34_[0] , - right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , - right_bottom_grid_pin_40_[0] , chany_bottom_in[2] } ) , - .sram ( mux_tree_tapbuf_size6_3_sram ) , - .sram_inv ( mux_right_track_0_undriven_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_152 ) ) ; -sb_0__1__mux_tree_tapbuf_size6_0 mux_bottom_track_1 ( - .in ( { chany_top_in[2] , chany_top_in[12] , chanx_right_in[5] , - chanx_right_in[12] , chanx_right_in[19] , bottom_left_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size6_4_sram ) , - .sram_inv ( mux_bottom_track_1_undriven_sram_inv ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_155 ) ) ; -sb_0__1__mux_tree_tapbuf_size6_1 mux_bottom_track_5 ( - .in ( { chany_top_in[5] , chany_top_in[14] , chanx_right_in[3] , - chanx_right_in[10] , chanx_right_in[17] , bottom_left_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size6_5_sram ) , - .sram_inv ( mux_bottom_track_5_undriven_sram_inv ) , - .out ( { ropt_net_167 } ) , - .p0 ( optlc_net_151 ) ) ; -sb_0__1__mux_tree_tapbuf_size6_2 mux_bottom_track_9 ( - .in ( { chany_top_in[6] , chany_top_in[16] , chanx_right_in[2] , - chanx_right_in[9] , chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size6_6_sram ) , - .sram_inv ( mux_bottom_track_9_undriven_sram_inv ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_151 ) ) ; -sb_0__1__mux_tree_tapbuf_size6_mem_4 mem_top_track_0 ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size6_mem_5 mem_top_track_4 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size6_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_2_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size6_mem_3 mem_right_track_0 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_3_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_4_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size6_mem_1 mem_bottom_track_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_5_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size6_mem_2 mem_bottom_track_9 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_6_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size5 mux_top_track_2 ( - .in ( { chanx_right_in[2] , chanx_right_in[9] , chanx_right_in[16] , - chany_bottom_in[4] , chany_bottom_in[13] } ) , - .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_top_track_2_undriven_sram_inv ) , - .out ( { ropt_net_168 } ) , - .p0 ( optlc_net_156 ) ) ; -sb_0__1__mux_tree_tapbuf_size5_3 mux_top_track_16 ( - .in ( { chanx_right_in[5] , chanx_right_in[12] , chanx_right_in[19] , - chany_bottom_in[8] , chany_bottom_in[17] } ) , - .sram ( mux_tree_tapbuf_size5_1_sram ) , - .sram_inv ( mux_top_track_16_undriven_sram_inv ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_157 ) ) ; -sb_0__1__mux_tree_tapbuf_size5_2 mux_bottom_track_3 ( - .in ( { chany_top_in[4] , chany_top_in[13] , chanx_right_in[4] , - chanx_right_in[11] , chanx_right_in[18] } ) , - .sram ( mux_tree_tapbuf_size5_2_sram ) , - .sram_inv ( mux_bottom_track_3_undriven_sram_inv ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_155 ) ) ; -sb_0__1__mux_tree_tapbuf_size5_0 mux_bottom_track_17 ( - .in ( { chany_top_in[8] , chany_top_in[17] , chanx_right_in[1] , - chanx_right_in[8] , chanx_right_in[15] } ) , - .sram ( mux_tree_tapbuf_size5_3_sram ) , - .sram_inv ( mux_bottom_track_17_undriven_sram_inv ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_151 ) ) ; -sb_0__1__mux_tree_tapbuf_size5_1 mux_bottom_track_25 ( - .in ( { chany_top_in[9] , chany_top_in[18] , chanx_right_in[0] , - chanx_right_in[7] , chanx_right_in[14] } ) , - .sram ( mux_tree_tapbuf_size5_4_sram ) , - .sram_inv ( mux_bottom_track_25_undriven_sram_inv ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_154 ) ) ; -sb_0__1__mux_tree_tapbuf_size5_mem mem_top_track_2 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size5_mem_3 mem_top_track_16 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size5_mem_2 mem_bottom_track_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_2_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size5_mem_0 mem_bottom_track_17 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_3_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size5_mem_1 mem_bottom_track_25 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_4_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size4_5 mux_top_track_24 ( - .in ( { chanx_right_in[6] , chanx_right_in[13] , chany_bottom_in[9] , - chany_bottom_in[18] } ) , - .sram ( mux_tree_tapbuf_size4_0_sram ) , - .sram_inv ( mux_top_track_24_undriven_sram_inv ) , - .out ( { ropt_net_160 } ) , - .p0 ( optlc_net_153 ) ) ; -sb_0__1__mux_tree_tapbuf_size4 mux_top_track_32 ( - .in ( { chanx_right_in[0] , chanx_right_in[7] , chanx_right_in[14] , - chany_bottom_in[10] } ) , - .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_top_track_32_undriven_sram_inv ) , - .out ( chany_top_out[16] ) , .p0 ( optlc_net_153 ) ) ; -sb_0__1__mux_tree_tapbuf_size4_4 mux_right_track_8 ( - .in ( { chany_top_in[7] , chany_top_in[8] , right_bottom_grid_pin_34_[0] , - chany_bottom_in[8] } ) , - .sram ( mux_tree_tapbuf_size4_2_sram ) , - .sram_inv ( mux_right_track_8_undriven_sram_inv ) , - .out ( { ropt_net_163 } ) , - .p0 ( optlc_net_153 ) ) ; -sb_0__1__mux_tree_tapbuf_size4_0 mux_right_track_10 ( - .in ( { chany_top_in[9] , chany_top_in[11] , - right_bottom_grid_pin_35_[0] , chany_bottom_in[9] } ) , - .sram ( mux_tree_tapbuf_size4_3_sram ) , - .sram_inv ( mux_right_track_10_undriven_sram_inv ) , - .out ( chanx_right_out[5] ) , .p0 ( optlc_net_155 ) ) ; -sb_0__1__mux_tree_tapbuf_size4_1 mux_right_track_12 ( - .in ( { chany_top_in[10] , chany_top_in[15] , - right_bottom_grid_pin_36_[0] , chany_bottom_in[10] } ) , - .sram ( mux_tree_tapbuf_size4_4_sram ) , - .sram_inv ( mux_right_track_12_undriven_sram_inv ) , - .out ( chanx_right_out[6] ) , .p0 ( optlc_net_153 ) ) ; -sb_0__1__mux_tree_tapbuf_size4_2 mux_right_track_14 ( - .in ( { chany_top_in[12] , chany_top_in[19] , - right_bottom_grid_pin_37_[0] , chany_bottom_in[12] } ) , - .sram ( mux_tree_tapbuf_size4_5_sram ) , - .sram_inv ( mux_right_track_14_undriven_sram_inv ) , - .out ( { ropt_net_166 } ) , - .p0 ( optlc_net_155 ) ) ; -sb_0__1__mux_tree_tapbuf_size4_3 mux_right_track_24 ( - .in ( { chany_top_in[18] , right_bottom_grid_pin_34_[0] , - chany_bottom_in[18] , chany_bottom_in[19] } ) , - .sram ( mux_tree_tapbuf_size4_6_sram ) , - .sram_inv ( mux_right_track_24_undriven_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_154 ) ) ; -sb_0__1__mux_tree_tapbuf_size4_mem_5 mem_top_track_24 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size4_mem mem_top_track_32 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size4_mem_4 mem_right_track_8 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size4_mem_0 mem_right_track_10 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size4_mem_1 mem_right_track_12 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_4_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size4_mem_2 mem_right_track_14 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_5_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size4_mem_3 mem_right_track_24 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_6_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size7_0 mux_right_track_2 ( - .in ( { chany_top_in[0] , chany_top_in[4] , right_bottom_grid_pin_35_[0] , - right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , - right_bottom_grid_pin_41_[0] , chany_bottom_in[4] } ) , - .sram ( mux_tree_tapbuf_size7_0_sram ) , - .sram_inv ( mux_right_track_2_undriven_sram_inv ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_151 ) ) ; -sb_0__1__mux_tree_tapbuf_size7_1 mux_right_track_4 ( - .in ( { chany_top_in[1] , chany_top_in[5] , right_bottom_grid_pin_34_[0] , - right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , - right_bottom_grid_pin_40_[0] , chany_bottom_in[5] } ) , - .sram ( mux_tree_tapbuf_size7_1_sram ) , - .sram_inv ( mux_right_track_4_undriven_sram_inv ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_152 ) ) ; -sb_0__1__mux_tree_tapbuf_size7 mux_right_track_6 ( - .in ( { chany_top_in[3] , chany_top_in[6] , right_bottom_grid_pin_35_[0] , - right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , - right_bottom_grid_pin_41_[0] , chany_bottom_in[6] } ) , - .sram ( mux_tree_tapbuf_size7_2_sram ) , - .sram_inv ( mux_right_track_6_undriven_sram_inv ) , - .out ( chanx_right_out[3] ) , .p0 ( optlc_net_153 ) ) ; -sb_0__1__mux_tree_tapbuf_size7_mem_0 mem_right_track_2 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size7_mem_1 mem_right_track_4 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size7_mem mem_right_track_6 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size3_1 mux_right_track_16 ( - .in ( { chany_top_in[13] , right_bottom_grid_pin_38_[0] , - chany_bottom_in[13] } ) , - .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_right_track_16_undriven_sram_inv ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_151 ) ) ; -sb_0__1__mux_tree_tapbuf_size3_2 mux_right_track_18 ( - .in ( { chany_top_in[14] , right_bottom_grid_pin_39_[0] , - chany_bottom_in[14] } ) , - .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_right_track_18_undriven_sram_inv ) , - .out ( chanx_right_out[9] ) , .p0 ( optlc_net_152 ) ) ; -sb_0__1__mux_tree_tapbuf_size3_3 mux_right_track_20 ( - .in ( { chany_top_in[16] , right_bottom_grid_pin_40_[0] , - chany_bottom_in[16] } ) , - .sram ( mux_tree_tapbuf_size3_2_sram ) , - .sram_inv ( mux_right_track_20_undriven_sram_inv ) , - .out ( chanx_right_out[10] ) , .p0 ( optlc_net_152 ) ) ; -sb_0__1__mux_tree_tapbuf_size3 mux_right_track_22 ( - .in ( { chany_top_in[17] , right_bottom_grid_pin_41_[0] , - chany_bottom_in[17] } ) , - .sram ( mux_tree_tapbuf_size3_3_sram ) , - .sram_inv ( mux_right_track_22_undriven_sram_inv ) , - .out ( chanx_right_out[11] ) , .p0 ( optlc_net_154 ) ) ; -sb_0__1__mux_tree_tapbuf_size3_0 mux_bottom_track_33 ( - .in ( { chany_top_in[10] , chanx_right_in[6] , chanx_right_in[13] } ) , - .sram ( mux_tree_tapbuf_size3_4_sram ) , - .sram_inv ( mux_bottom_track_33_undriven_sram_inv ) , - .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_152 ) ) ; -sb_0__1__mux_tree_tapbuf_size3_mem_1 mem_right_track_16 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size3_mem_2 mem_right_track_18 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size3_mem_3 mem_right_track_20 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size3_mem mem_right_track_22 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_33 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , - .ccff_tail ( { ropt_net_179 } ) , - .mem_out ( mux_tree_tapbuf_size3_4_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size2_0 mux_right_track_26 ( - .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[15] } ) , - .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_right_track_26_undriven_sram_inv ) , - .out ( { ropt_net_173 } ) , - .p0 ( optlc_net_152 ) ) ; -sb_0__1__mux_tree_tapbuf_size2_1 mux_right_track_28 ( - .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[11] } ) , - .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_right_track_28_undriven_sram_inv ) , - .out ( chanx_right_out[14] ) , .p0 ( optlc_net_152 ) ) ; -sb_0__1__mux_tree_tapbuf_size2_2 mux_right_track_30 ( - .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[7] } ) , - .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_right_track_30_undriven_sram_inv ) , - .out ( chanx_right_out[15] ) , .p0 ( optlc_net_152 ) ) ; -sb_0__1__mux_tree_tapbuf_size2_3 mux_right_track_32 ( - .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[3] } ) , - .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_right_track_32_undriven_sram_inv ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_152 ) ) ; -sb_0__1__mux_tree_tapbuf_size2_4 mux_right_track_34 ( - .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[1] } ) , - .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_right_track_34_undriven_sram_inv ) , - .out ( chanx_right_out[17] ) , .p0 ( optlc_net_151 ) ) ; -sb_0__1__mux_tree_tapbuf_size2 mux_right_track_36 ( - .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[0] } ) , - .sram ( mux_tree_tapbuf_size2_5_sram ) , - .sram_inv ( mux_right_track_36_undriven_sram_inv ) , - .out ( chanx_right_out[18] ) , .p0 ( optlc_net_151 ) ) ; -sb_0__1__mux_tree_tapbuf_size2_mem_0 mem_right_track_26 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size2_mem_1 mem_right_track_28 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size2_mem_2 mem_right_track_30 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size2_mem_3 mem_right_track_32 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size2_mem_4 mem_right_track_34 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size2_mem mem_right_track_36 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_top_in[2] ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( ropt_net_182 ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_137 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_151 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_top_in[6] ) , - .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_141 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_152 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_144 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_153 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_top_in[10] ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_146 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_154 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , - .HI ( optlc_net_155 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chany_top_in[14] ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chany_top_in[16] ) , - .X ( ropt_net_180 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_151 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , - .HI ( optlc_net_156 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_153 ( .LO ( SYNOPSYS_UNCONNECTED_7 ) , - .HI ( optlc_net_157 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_814 ( .A ( ropt_net_183 ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__clkbuf_1 \prog_clk[0]_bip420 ( .A ( prog_clk[0] ) , - .X ( ctsbuf_net_1159 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_792 ( .A ( ropt_net_160 ) , - .X ( ropt_net_184 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chany_bottom_in[5] ) , - .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chany_bottom_in[6] ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chany_bottom_in[8] ) , - .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_184 ) , - .X ( chany_top_out[12] ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_345765 ( .A ( ctsbuf_net_1159 ) , - .X ( prog_clk__FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_816 ( .A ( ropt_net_185 ) , - .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( chany_top_in[18] ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chany_bottom_in[14] ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_25__24 ( .A ( chany_bottom_in[16] ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_817 ( .A ( ropt_net_186 ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_162 ) , - .X ( ropt_net_185 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_73 ( .A ( chany_top_in[4] ) , - .X ( BUF_net_73 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_818 ( .A ( ropt_net_187 ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_163 ) , - .X ( ropt_net_188 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_820 ( .A ( ropt_net_188 ) , - .X ( chanx_right_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_826 ( .A ( ropt_net_189 ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_827 ( .A ( ropt_net_190 ) , - .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_164 ) , - .X ( ropt_net_182 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( - .A ( right_bottom_grid_pin_41_[0] ) , .X ( ropt_net_191 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_166 ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_82 ( .A ( chany_bottom_in[10] ) , - .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_829 ( .A ( ropt_net_191 ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_192 ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_167 ) , - .X ( chany_bottom_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_168 ) , - .X ( chany_top_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_169 ) , - .X ( ropt_net_183 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_170 ) , - .X ( ropt_net_187 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_803 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_192 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_193 ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_804 ( .A ( chany_top_in[17] ) , - .X ( ropt_net_193 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( .A ( ropt_net_173 ) , - .X ( ropt_net_190 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_113 ( .A ( chany_top_in[8] ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_117 ( .A ( BUF_net_73 ) , - .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_118 ( .A ( chany_bottom_in[2] ) , - .X ( ropt_net_189 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_128 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_162 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( chany_top_in[9] ) , - .X ( ropt_net_186 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_131 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_164 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_133 ( .A ( chany_bottom_in[13] ) , - .X ( ropt_net_170 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_134 ( .A ( chany_bottom_in[18] ) , - .X ( ropt_net_169 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_807 ( .A ( chany_top_in[12] ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_808 ( - .A ( chany_bottom_in[17] ) , .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_809 ( .A ( chany_bottom_in[4] ) , - .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_810 ( - .A ( chany_bottom_in[12] ) , .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_179 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_180 ) , - .X ( chany_bottom_out[17] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__39 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__38 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__37 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__36 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__0__const1 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sb_0__0__const1 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -endmodule - - -module sb_0__0__const1_18 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sb_0__0__const1_18 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -endmodule - - -module sb_0__0__const1_17 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sb_0__0__const1_17 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -endmodule - - -module sb_0__0__const1_16 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sb_0__0__const1_16 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__35 ( .A ( mem_out[1] ) , - .X ( net_aps_35 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_62 ( .A ( net_aps_35 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__34 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__33 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__32 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__31 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__30 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__29 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__28 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__27 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__26 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__25 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__24 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__23 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__22 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__21 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__20 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__0__const1_15 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_0__0__const1_15 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__0__const1_14 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_0__0__const1_14 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__0__const1_13 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_0__0__const1_13 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__0__const1_12 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -sb_0__0__const1_12 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_0__0__const1_11 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_0__0__const1_11 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__0__const1_10 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_0__0__const1_10 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__0__const1_9 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_0__0__const1_9 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__0__const1_8 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_0__0__const1_8 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__0__const1_7 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_0__0__const1_7 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__0__const1_6 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_0__0__const1_6 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_41 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_0__0__const1_5 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_0__0__const1_5 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__0__const1_4 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_0__0__const1_4 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_40 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_0__0__const1_3 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_0__0__const1_3 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__0__const1_2 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_0__0__const1_2 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__0__const1_1 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_0__0__const1_1 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__0__const1_0 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_0__0__const1_0 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__0_ ( prog_clk , chany_top_in , top_left_grid_pin_1_ , - chanx_right_in , right_bottom_grid_pin_1_ , right_bottom_grid_pin_3_ , - right_bottom_grid_pin_5_ , right_bottom_grid_pin_7_ , - right_bottom_grid_pin_9_ , right_bottom_grid_pin_11_ , ccff_head , - chany_top_out , chanx_right_out , ccff_tail ) ; -input [0:0] prog_clk ; -input [0:19] chany_top_in ; -input [0:0] top_left_grid_pin_1_ ; -input [0:19] chanx_right_in ; -input [0:0] right_bottom_grid_pin_1_ ; -input [0:0] right_bottom_grid_pin_3_ ; -input [0:0] right_bottom_grid_pin_5_ ; -input [0:0] right_bottom_grid_pin_7_ ; -input [0:0] right_bottom_grid_pin_9_ ; -input [0:0] right_bottom_grid_pin_11_ ; -input [0:0] ccff_head ; -output [0:19] chany_top_out ; -output [0:19] chanx_right_out ; -output [0:0] ccff_tail ; - -wire [0:2] mux_right_track_0_undriven_sram_inv ; -wire [0:1] mux_right_track_10_undriven_sram_inv ; -wire [0:1] mux_right_track_12_undriven_sram_inv ; -wire [0:1] mux_right_track_14_undriven_sram_inv ; -wire [0:1] mux_right_track_16_undriven_sram_inv ; -wire [0:1] mux_right_track_18_undriven_sram_inv ; -wire [0:1] mux_right_track_24_undriven_sram_inv ; -wire [0:1] mux_right_track_26_undriven_sram_inv ; -wire [0:1] mux_right_track_28_undriven_sram_inv ; -wire [0:2] mux_right_track_2_undriven_sram_inv ; -wire [0:1] mux_right_track_30_undriven_sram_inv ; -wire [0:1] mux_right_track_32_undriven_sram_inv ; -wire [0:1] mux_right_track_34_undriven_sram_inv ; -wire [0:2] mux_right_track_4_undriven_sram_inv ; -wire [0:2] mux_right_track_6_undriven_sram_inv ; -wire [0:1] mux_right_track_8_undriven_sram_inv ; -wire [0:1] mux_top_track_0_undriven_sram_inv ; -wire [0:1] mux_top_track_24_undriven_sram_inv ; -wire [0:1] mux_top_track_4_undriven_sram_inv ; -wire [0:1] mux_top_track_8_undriven_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_10_sram ; -wire [0:1] mux_tree_tapbuf_size2_11_sram ; -wire [0:1] mux_tree_tapbuf_size2_12_sram ; -wire [0:1] mux_tree_tapbuf_size2_13_sram ; -wire [0:1] mux_tree_tapbuf_size2_14_sram ; -wire [0:1] mux_tree_tapbuf_size2_15_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_5_sram ; -wire [0:1] mux_tree_tapbuf_size2_6_sram ; -wire [0:1] mux_tree_tapbuf_size2_7_sram ; -wire [0:1] mux_tree_tapbuf_size2_8_sram ; -wire [0:1] mux_tree_tapbuf_size2_9_sram ; -wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size4_0_sram ; -wire [0:2] mux_tree_tapbuf_size4_1_sram ; -wire [0:2] mux_tree_tapbuf_size4_2_sram ; -wire [0:2] mux_tree_tapbuf_size4_3_sram ; -wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; - -sb_0__0__mux_tree_tapbuf_size2_12 mux_top_track_0 ( - .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] } ) , - .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_top_track_0_undriven_sram_inv ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_80 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_14 mux_top_track_4 ( - .in ( { top_left_grid_pin_1_[0] , chanx_right_in[3] } ) , - .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_top_track_4_undriven_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_80 ) ) ; -sb_0__0__mux_tree_tapbuf_size2 mux_top_track_8 ( - .in ( { top_left_grid_pin_1_[0] , chanx_right_in[5] } ) , - .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_top_track_8_undriven_sram_inv ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_80 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_13 mux_top_track_24 ( - .in ( { top_left_grid_pin_1_[0] , chanx_right_in[13] } ) , - .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_top_track_24_undriven_sram_inv ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_81 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_11 mux_right_track_8 ( - .in ( { chany_top_in[3] , right_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_right_track_8_undriven_sram_inv ) , - .out ( { ropt_net_83 } ) , - .p0 ( optlc_net_81 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_0 mux_right_track_10 ( - .in ( { chany_top_in[4] , right_bottom_grid_pin_3_[0] } ) , - .sram ( mux_tree_tapbuf_size2_5_sram ) , - .sram_inv ( mux_right_track_10_undriven_sram_inv ) , - .out ( chanx_right_out[5] ) , .p0 ( optlc_net_81 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_1 mux_right_track_12 ( - .in ( { chany_top_in[5] , right_bottom_grid_pin_5_[0] } ) , - .sram ( mux_tree_tapbuf_size2_6_sram ) , - .sram_inv ( mux_right_track_12_undriven_sram_inv ) , - .out ( { ropt_net_84 } ) , - .p0 ( optlc_net_78 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_2 mux_right_track_14 ( - .in ( { chany_top_in[6] , right_bottom_grid_pin_7_[0] } ) , - .sram ( mux_tree_tapbuf_size2_7_sram ) , - .sram_inv ( mux_right_track_14_undriven_sram_inv ) , - .out ( chanx_right_out[7] ) , .p0 ( optlc_net_78 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_3 mux_right_track_16 ( - .in ( { chany_top_in[7] , right_bottom_grid_pin_9_[0] } ) , - .sram ( mux_tree_tapbuf_size2_8_sram ) , - .sram_inv ( mux_right_track_16_undriven_sram_inv ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_78 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_4 mux_right_track_18 ( - .in ( { chany_top_in[8] , right_bottom_grid_pin_11_[0] } ) , - .sram ( mux_tree_tapbuf_size2_9_sram ) , - .sram_inv ( mux_right_track_18_undriven_sram_inv ) , - .out ( chanx_right_out[9] ) , .p0 ( optlc_net_81 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_5 mux_right_track_24 ( - .in ( { chany_top_in[11] , right_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size2_10_sram ) , - .sram_inv ( mux_right_track_24_undriven_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_79 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_6 mux_right_track_26 ( - .in ( { chany_top_in[12] , right_bottom_grid_pin_3_[0] } ) , - .sram ( mux_tree_tapbuf_size2_11_sram ) , - .sram_inv ( mux_right_track_26_undriven_sram_inv ) , - .out ( chanx_right_out[13] ) , .p0 ( optlc_net_79 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_7 mux_right_track_28 ( - .in ( { chany_top_in[13] , right_bottom_grid_pin_5_[0] } ) , - .sram ( mux_tree_tapbuf_size2_12_sram ) , - .sram_inv ( mux_right_track_28_undriven_sram_inv ) , - .out ( chanx_right_out[14] ) , .p0 ( optlc_net_79 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_8 mux_right_track_30 ( - .in ( { chany_top_in[14] , right_bottom_grid_pin_7_[0] } ) , - .sram ( mux_tree_tapbuf_size2_13_sram ) , - .sram_inv ( mux_right_track_30_undriven_sram_inv ) , - .out ( chanx_right_out[15] ) , .p0 ( optlc_net_78 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_9 mux_right_track_32 ( - .in ( { chany_top_in[15] , right_bottom_grid_pin_9_[0] } ) , - .sram ( mux_tree_tapbuf_size2_14_sram ) , - .sram_inv ( mux_right_track_32_undriven_sram_inv ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_78 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_10 mux_right_track_34 ( - .in ( { chany_top_in[16] , right_bottom_grid_pin_11_[0] } ) , - .sram ( mux_tree_tapbuf_size2_15_sram ) , - .sram_inv ( mux_right_track_34_undriven_sram_inv ) , - .out ( chanx_right_out[17] ) , .p0 ( optlc_net_78 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_12 mem_top_track_0 ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_14 mem_top_track_4 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_13 mem_top_track_24 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_11 mem_right_track_8 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_0 mem_right_track_10 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_1 mem_right_track_12 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_2 mem_right_track_14 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_3 mem_right_track_16 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_4 mem_right_track_18 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_5 mem_right_track_24 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_6 mem_right_track_26 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_11_sram ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_7 mem_right_track_28 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_12_sram ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_8 mem_right_track_30 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_13_sram ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_9 mem_right_track_32 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_14_sram ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_10 mem_right_track_34 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .ccff_tail ( { ropt_net_85 } ) , - .mem_out ( mux_tree_tapbuf_size2_15_sram ) ) ; -sb_0__0__mux_tree_tapbuf_size4_0 mux_right_track_0 ( - .in ( { chany_top_in[19] , right_bottom_grid_pin_1_[0] , - right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] } ) , - .sram ( mux_tree_tapbuf_size4_0_sram ) , - .sram_inv ( mux_right_track_0_undriven_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_78 ) ) ; -sb_0__0__mux_tree_tapbuf_size4_1 mux_right_track_2 ( - .in ( { chany_top_in[0] , right_bottom_grid_pin_3_[0] , - right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_11_[0] } ) , - .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_right_track_2_undriven_sram_inv ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_79 ) ) ; -sb_0__0__mux_tree_tapbuf_size4_2 mux_right_track_4 ( - .in ( { chany_top_in[1] , right_bottom_grid_pin_1_[0] , - right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] } ) , - .sram ( mux_tree_tapbuf_size4_2_sram ) , - .sram_inv ( mux_right_track_4_undriven_sram_inv ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_79 ) ) ; -sb_0__0__mux_tree_tapbuf_size4 mux_right_track_6 ( - .in ( { chany_top_in[2] , right_bottom_grid_pin_3_[0] , - right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_11_[0] } ) , - .sram ( mux_tree_tapbuf_size4_3_sram ) , - .sram_inv ( mux_right_track_6_undriven_sram_inv ) , - .out ( chanx_right_out[3] ) , .p0 ( optlc_net_79 ) ) ; -sb_0__0__mux_tree_tapbuf_size4_mem_0 mem_right_track_0 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ; -sb_0__0__mux_tree_tapbuf_size4_mem_1 mem_right_track_2 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ; -sb_0__0__mux_tree_tapbuf_size4_mem_2 mem_right_track_4 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ; -sb_0__0__mux_tree_tapbuf_size4_mem mem_right_track_6 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__0 ( .A ( chany_top_in[9] ) , - .X ( ropt_net_94 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_76 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_78 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_78 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_79 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_80 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_80 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chanx_right_in[0] ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_82 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_81 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_685 ( .A ( ropt_net_83 ) , - .X ( chanx_right_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_686 ( .A ( ropt_net_84 ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_687 ( .A ( ropt_net_85 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_688 ( .A ( chany_top_in[18] ) , - .X ( ropt_net_103 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_689 ( .A ( chanx_right_in[6] ) , - .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_690 ( .A ( chanx_right_in[15] ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_691 ( .A ( chanx_right_in[18] ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_692 ( .A ( ropt_net_90 ) , - .X ( ropt_net_99 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chanx_right_in[14] ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_693 ( .A ( ropt_net_91 ) , - .X ( ropt_net_98 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_694 ( .A ( ropt_net_92 ) , - .X ( ropt_net_100 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_695 ( .A ( ropt_net_93 ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_696 ( .A ( ropt_net_94 ) , - .X ( ropt_net_101 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_697 ( .A ( ropt_net_98 ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_46 ( .A ( chany_top_in[17] ) , - .X ( ropt_net_91 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_698 ( .A ( ropt_net_99 ) , - .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_48 ( .A ( chanx_right_in[2] ) , - .X ( chany_top_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_49 ( .A ( chanx_right_in[4] ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_699 ( .A ( ropt_net_100 ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_51 ( .A ( chanx_right_in[7] ) , - .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_52 ( .A ( chanx_right_in[8] ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_53 ( .A ( chanx_right_in[9] ) , - .X ( chany_top_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_54 ( .A ( chanx_right_in[10] ) , - .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_55 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_92 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_56 ( .A ( chanx_right_in[12] ) , - .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_700 ( .A ( ropt_net_101 ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_58 ( .A ( chanx_right_in[16] ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_59 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_90 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_701 ( .A ( ropt_net_102 ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_61 ( .A ( chanx_right_in[19] ) , - .X ( ropt_net_102 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_702 ( .A ( ropt_net_103 ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_67 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_93 ) ) ; -endmodule - - -module grid_clb_direct_interc_11 ( in , out ) ; -input [0:0] in ; -output [0:0] out ; -endmodule - - -module grid_clb_direct_interc_10 ( in , out ) ; -input [0:0] in ; -output [0:0] out ; -endmodule - - -module grid_clb_direct_interc_9 ( in , out ) ; -input [0:0] in ; -output [0:0] out ; -endmodule - - -module grid_clb_direct_interc_8 ( in , out ) ; -input [0:0] in ; -output [0:0] out ; -endmodule - - -module grid_clb_direct_interc_7 ( in , out ) ; -input [0:0] in ; -output [0:0] out ; -endmodule - - -module grid_clb_direct_interc_6 ( in , out ) ; -input [0:0] in ; -output [0:0] out ; -endmodule - - -module grid_clb_direct_interc_5 ( in , out ) ; -input [0:0] in ; -output [0:0] out ; -endmodule - - -module grid_clb_mux_tree_size2_mem_23 ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_40__57 ( .A ( mem_out[1] ) , - .X ( net_net_110 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_110 ( .A ( net_net_110 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_mem_22 ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_39__56 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_mem_21 ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_38__55 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module grid_clb_const1 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module grid_clb_mux_tree_size2_23 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -grid_clb_const1 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module grid_clb_const1_30 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module grid_clb_mux_tree_size2_22 ( in , sram , sram_inv , out , p_abuf0 , - p_abuf1 , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -output p_abuf0 ; -output p_abuf1 ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -grid_clb_const1_30 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf1 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_92 ( .A ( p_abuf1 ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_93 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; -endmodule - - -module grid_clb_const1_29 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module grid_clb_mux_tree_size2_21 ( in , sram , sram_inv , out , p_abuf0 , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -output p_abuf0 ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -grid_clb_const1_29 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_91 ( .A ( out[0] ) , .X ( p_abuf0 ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff ( - Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk , p_abuf0 , p_abuf1 , - p_abuf2 ) ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:0] ff_D ; -input [0:0] ff_DI ; -output [0:0] ff_Q ; -input [0:0] ff_clk ; -output p_abuf0 ; -output p_abuf1 ; -output p_abuf2 ; - -sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , - .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( p_abuf2 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_58 ( .A ( p_abuf2 ) , .X ( ff_Q[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_60 ( .A ( p_abuf2 ) , .X ( p_abuf1 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_130 ( .A ( p_abuf2 ) , .X ( p_abuf0 ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_14 ( - Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:0] ff_D ; -input [0:0] ff_DI ; -output [0:0] ff_Q ; -input [0:0] ff_clk ; - -sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , - .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_37__54 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module grid_clb_const1_28 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module grid_clb_mux_tree_size2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -grid_clb_const1_28 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem ( prog_clk , - ccff_head , ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:16] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_5_ ( .D ( mem_out[4] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_6_ ( .D ( mem_out[5] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_7_ ( .D ( mem_out[6] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_8_ ( .D ( mem_out[7] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_9_ ( .D ( mem_out[8] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_10_ ( .D ( mem_out[9] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_11_ ( .D ( mem_out[10] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_12_ ( .D ( mem_out[11] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_13_ ( .D ( mem_out[12] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_14_ ( .D ( mem_out[13] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_15_ ( .D ( mem_out[14] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_16_ ( .D ( mem_out[15] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_36__53 ( .A ( mem_out[16] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module grid_clb_frac_lut4_mux ( in , sram , sram_inv , lut3_out , lut4_out ) ; -input [0:15] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:1] lut3_out ; -output [0:0] lut4_out ; - -wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_4_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_5_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( - .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( - .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( - .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( - .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_5_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_6_ ( - .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__buf_2_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__buf_2_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__buf_2_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ; -endmodule - - -module grid_clb_frac_lut4 ( in , sram , sram_inv , mode , mode_inv , - lut3_out , lut4_out ) ; -input [0:3] in ; -input [0:15] sram ; -input [0:15] sram_inv ; -input [0:0] mode ; -input [0:0] mode_inv ; -output [0:1] lut3_out ; -output [0:0] lut4_out ; - -wire [0:0] sky130_fd_sc_hd__buf_2_0_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_1_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_2_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; -wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ; -wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ; -wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ; -wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ; -wire [0:0] sky130_fd_sc_hd__or2_1_0_X ; - -sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , - .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , - .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , - .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , - .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( - .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , - .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , - .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , - .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , - .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( - .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; -grid_clb_frac_lut4_mux frac_lut4_mux_0_ ( .in ( sram ) , - .sram ( { sky130_fd_sc_hd__buf_2_0_X[0] , sky130_fd_sc_hd__buf_2_1_X[0] , - sky130_fd_sc_hd__buf_2_2_X[0] , sky130_fd_sc_hd__buf_2_3_X[0] } ) , - .sram_inv ( { sky130_fd_sc_hd__inv_1_0_Y[0] , - sky130_fd_sc_hd__inv_1_1_Y[0] , sky130_fd_sc_hd__inv_1_2_Y[0] , - sky130_fd_sc_hd__inv_1_3_Y[0] } ) , - .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4 ( - prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out , - frac_lut4_lut4_out , ccff_tail ) ; -input [0:0] prog_clk ; -input [0:3] frac_lut4_in ; -input [0:0] ccff_head ; -output [0:1] frac_lut4_lut3_out ; -output [0:0] frac_lut4_lut4_out ; -output [0:0] ccff_tail ; - -wire [0:15] frac_lut4_0__undriven_sram_inv ; -wire [0:0] frac_lut4_0_mode ; -wire [0:15] frac_lut4_0_sram ; - -grid_clb_frac_lut4 frac_lut4_0_ ( .in ( frac_lut4_in ) , - .sram ( frac_lut4_0_sram ) , - .sram_inv ( frac_lut4_0__undriven_sram_inv ) , - .mode ( frac_lut4_0_mode ) , - .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , - .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) ) ; -grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , - .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , - frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] , - frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , - frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , - frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , - frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic ( - prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p0 ) ; -input [0:0] prog_clk ; -input [0:3] frac_logic_in ; -input [0:0] ccff_head ; -output [0:1] frac_logic_out ; -output [0:0] ccff_tail ; -input p0 ; - -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; -wire [0:1] mux_frac_logic_out_0_undriven_sram_inv ; -wire [0:1] mux_tree_size2_0_sram ; - -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( - .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , - .ccff_head ( ccff_head ) , - .frac_lut4_lut3_out ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] , - frac_logic_out[1] } ) , - - .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , - .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ; -grid_clb_mux_tree_size2 mux_frac_logic_out_0 ( - .in ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] - } ) , - .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_frac_logic_out_0_undriven_sram_inv ) , - .out ( frac_logic_out[0] ) , .p0 ( p0 ) ) ; -grid_clb_mux_tree_size2_mem mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) ) ; -grid_clb_direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( frac_logic_out[1] ) ) ; -grid_clb_direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( frac_logic_in[0] ) ) ; -grid_clb_direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( frac_logic_in[1] ) ) ; -grid_clb_direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( frac_logic_in[2] ) ) ; -grid_clb_direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( frac_logic_in[3] ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric ( - prog_clk , Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , - fabric_clk , ccff_head , fabric_out , fabric_regout , fabric_sc_out , - ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p_abuf3 , p_abuf5 , p_abuf6 , - p0 ) ; -input [0:0] prog_clk ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:3] fabric_in ; -input [0:0] fabric_regin ; -input [0:0] fabric_sc_in ; -input [0:0] fabric_clk ; -input [0:0] ccff_head ; -output [0:1] fabric_out ; -output [0:0] fabric_regout ; -output [0:0] fabric_sc_out ; -output [0:0] ccff_tail ; -output p_abuf0 ; -output p_abuf1 ; -output p_abuf2 ; -output p_abuf3 ; -output p_abuf5 ; -output p_abuf6 ; -input p0 ; - -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; -wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; -wire [0:1] mux_fabric_out_0_undriven_sram_inv ; -wire [0:1] mux_fabric_out_1_undriven_sram_inv ; -wire [0:1] mux_ff_0_D_0_undriven_sram_inv ; -wire [0:1] mux_tree_size2_0_sram ; -wire [0:1] mux_tree_size2_1_sram ; -wire [0:0] mux_tree_size2_2_out ; -wire [0:1] mux_tree_size2_2_sram ; -wire [0:0] mux_tree_size2_mem_0_ccff_tail ; -wire [0:0] mux_tree_size2_mem_1_ccff_tail ; - -assign p_abuf1 = p_abuf2 ; - -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( - .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , - .ccff_head ( ccff_head ) , - .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , - .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .p0 ( p0 ) ) ; -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_14 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( - .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , - .ff_DI ( fabric_sc_in ) , - .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , - .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( - .Test_en ( Test_en ) , .clk ( clk ) , - .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , - .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , - .ff_Q ( fabric_sc_out ) , - .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) , - .p_abuf0 ( fabric_regout[0] ) , .p_abuf1 ( p_abuf0 ) , - .p_abuf2 ( p_abuf2 ) ) ; -grid_clb_mux_tree_size2_21 mux_fabric_out_0 ( - .in ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] - } ) , - .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_fabric_out_0_undriven_sram_inv ) , - .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf3 ) , .p0 ( p0 ) ) ; -grid_clb_mux_tree_size2_22 mux_fabric_out_1 ( - .in ( { fabric_sc_out[0] , - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] - } ) , - .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( mux_fabric_out_1_undriven_sram_inv ) , - .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf5 ) , .p_abuf1 ( p_abuf6 ) , - .p0 ( p0 ) ) ; -grid_clb_mux_tree_size2_23 mux_ff_0_D_0 ( - .in ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , - fabric_regin[0] } ) , - .sram ( mux_tree_size2_2_sram ) , - .sram_inv ( mux_ff_0_D_0_undriven_sram_inv ) , - .out ( mux_tree_size2_2_out ) , .p0 ( p0 ) ) ; -grid_clb_mux_tree_size2_mem_21 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_size2_0_sram ) ) ; -grid_clb_mux_tree_size2_mem_22 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_size2_1_sram ) ) ; -grid_clb_mux_tree_size2_mem_23 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , - .mem_out ( mux_tree_size2_2_sram ) ) ; -grid_clb_direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( { p_abuf2 } ) ) ; -grid_clb_direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( { p_abuf2 } ) ) ; -grid_clb_direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( fabric_in[0] ) ) ; -grid_clb_direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_6 } ) , - .out ( fabric_in[1] ) ) ; -grid_clb_direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_7 } ) , - .out ( fabric_in[2] ) ) ; -grid_clb_direct_interc direct_interc_5_ ( - .in ( { SYNOPSYS_UNCONNECTED_8 } ) , - .out ( fabric_in[3] ) ) ; -grid_clb_direct_interc direct_interc_6_ ( - .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( fabric_sc_in ) ) ; -grid_clb_direct_interc direct_interc_7_ ( - .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( fabric_clk ) ) ; -grid_clb_direct_interc direct_interc_8_ ( - .in ( { SYNOPSYS_UNCONNECTED_11 } ) , - - .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) ) ; -grid_clb_direct_interc direct_interc_9_ ( - .in ( { SYNOPSYS_UNCONNECTED_12 } ) , - - .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ) ; -grid_clb_direct_interc direct_interc_10_ ( - .in ( { SYNOPSYS_UNCONNECTED_13 } ) , - .out ( fabric_clk ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle ( prog_clk , Test_en , - clk , fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , - fle_regout , fle_sc_out , ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , - p_abuf3 , p_abuf5 , p_abuf6 , p0 ) ; -input [0:0] prog_clk ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:3] fle_in ; -input [0:0] fle_regin ; -input [0:0] fle_sc_in ; -input [0:0] fle_clk ; -input [0:0] ccff_head ; -output [0:1] fle_out ; -output [0:0] fle_regout ; -output [0:0] fle_sc_out ; -output [0:0] ccff_tail ; -output p_abuf0 ; -output p_abuf1 ; -output p_abuf2 ; -output p_abuf3 ; -output p_abuf5 ; -output p_abuf6 ; -input p0 ; - -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( - .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , - .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , - .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , - .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , - .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , - .p_abuf2 ( p_abuf2 ) , .p_abuf3 ( p_abuf3 ) , .p_abuf5 ( p_abuf5 ) , - .p_abuf6 ( p_abuf6 ) , .p0 ( p0 ) ) ; -grid_clb_direct_interc_5 direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; -grid_clb_direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( { p_abuf6 } ) ) ; -grid_clb_direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( { p_abuf1 } ) ) ; -grid_clb_direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( { p_abuf2 } ) ) ; -grid_clb_direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_6 } ) , - .out ( fle_in[0] ) ) ; -grid_clb_direct_interc direct_interc_5_ ( - .in ( { SYNOPSYS_UNCONNECTED_7 } ) , - .out ( fle_in[1] ) ) ; -grid_clb_direct_interc direct_interc_6_ ( - .in ( { SYNOPSYS_UNCONNECTED_8 } ) , - .out ( fle_in[2] ) ) ; -grid_clb_direct_interc direct_interc_7_ ( - .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( fle_in[3] ) ) ; -grid_clb_direct_interc direct_interc_8_ ( - .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( fle_regin ) ) ; -grid_clb_direct_interc direct_interc_9_ ( - .in ( { SYNOPSYS_UNCONNECTED_11 } ) , - .out ( fle_sc_in ) ) ; -grid_clb_direct_interc direct_interc_10_ ( - .in ( { SYNOPSYS_UNCONNECTED_12 } ) , - .out ( fle_clk ) ) ; -endmodule - - -module grid_clb_direct_interc_4 ( in , out ) ; -input [0:0] in ; -output [0:0] out ; -endmodule - - -module grid_clb_mux_tree_size2_mem_20 ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_35__52 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_mem_19 ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_34__51 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_mem_18 ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__50 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module grid_clb_const1_27 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module grid_clb_mux_tree_size2_20 ( in , sram , sram_inv , out , p3 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p3 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -grid_clb_const1_27 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module grid_clb_const1_26 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module grid_clb_mux_tree_size2_19 ( in , sram , sram_inv , out , p_abuf0 , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -output p_abuf0 ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -grid_clb_const1_26 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_124 ( .A ( BUF_net_89 ) , - .X ( p_abuf0 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_89 ( .A ( out[0] ) , - .X ( BUF_net_89 ) ) ; -endmodule - - -module grid_clb_const1_25 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module grid_clb_mux_tree_size2_18 ( in , sram , sram_inv , out , p_abuf0 , - p_abuf1 , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -output p_abuf0 ; -output p_abuf1 ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -grid_clb_const1_25 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf1 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_86 ( .A ( p_abuf1 ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_87 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_13 ( - Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:0] ff_D ; -input [0:0] ff_DI ; -output [0:0] ff_Q ; -input [0:0] ff_clk ; - -sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , - .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_12 ( - Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:0] ff_D ; -input [0:0] ff_DI ; -output [0:0] ff_Q ; -input [0:0] ff_clk ; - -sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , - .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_mem_30 ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_32__49 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module grid_clb_const1_24 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module grid_clb_mux_tree_size2_30 ( in , sram , sram_inv , out , p3 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p3 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -grid_clb_const1_24 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_6 ( prog_clk , - ccff_head , ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:16] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_5_ ( .D ( mem_out[4] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_6_ ( .D ( mem_out[5] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_7_ ( .D ( mem_out[6] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_8_ ( .D ( mem_out[7] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_9_ ( .D ( mem_out[8] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_10_ ( .D ( mem_out[9] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_11_ ( .D ( mem_out[10] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_12_ ( .D ( mem_out[11] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_13_ ( .D ( mem_out[12] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_14_ ( .D ( mem_out[13] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_15_ ( .D ( mem_out[14] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_16_ ( .D ( mem_out[15] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__48 ( .A ( mem_out[16] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module grid_clb_frac_lut4_mux_6 ( in , sram , sram_inv , lut3_out , lut4_out ) ; -input [0:15] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:1] lut3_out ; -output [0:0] lut4_out ; - -wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_4_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_5_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( - .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( - .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( - .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( - .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_5_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_6_ ( - .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__buf_2_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__buf_2_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__buf_2_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ; -endmodule - - -module grid_clb_frac_lut4_6 ( in , sram , sram_inv , mode , mode_inv , - lut3_out , lut4_out ) ; -input [0:3] in ; -input [0:15] sram ; -input [0:15] sram_inv ; -input [0:0] mode ; -input [0:0] mode_inv ; -output [0:1] lut3_out ; -output [0:0] lut4_out ; - -wire [0:0] sky130_fd_sc_hd__buf_2_0_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_1_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_2_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; -wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ; -wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ; -wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ; -wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ; -wire [0:0] sky130_fd_sc_hd__or2_1_0_X ; - -sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , - .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , - .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , - .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , - .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( - .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , - .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , - .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , - .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , - .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( - .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; -grid_clb_frac_lut4_mux_6 frac_lut4_mux_0_ ( .in ( sram ) , - .sram ( { sky130_fd_sc_hd__buf_2_0_X[0] , sky130_fd_sc_hd__buf_2_1_X[0] , - sky130_fd_sc_hd__buf_2_2_X[0] , sky130_fd_sc_hd__buf_2_3_X[0] } ) , - .sram_inv ( { sky130_fd_sc_hd__inv_1_0_Y[0] , - sky130_fd_sc_hd__inv_1_1_Y[0] , sky130_fd_sc_hd__inv_1_2_Y[0] , - sky130_fd_sc_hd__inv_1_3_Y[0] } ) , - .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_6 ( - prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out , - frac_lut4_lut4_out , ccff_tail ) ; -input [0:0] prog_clk ; -input [0:3] frac_lut4_in ; -input [0:0] ccff_head ; -output [0:1] frac_lut4_lut3_out ; -output [0:0] frac_lut4_lut4_out ; -output [0:0] ccff_tail ; - -wire [0:15] frac_lut4_0__undriven_sram_inv ; -wire [0:0] frac_lut4_0_mode ; -wire [0:15] frac_lut4_0_sram ; - -grid_clb_frac_lut4_6 frac_lut4_0_ ( .in ( frac_lut4_in ) , - .sram ( frac_lut4_0_sram ) , - .sram_inv ( frac_lut4_0__undriven_sram_inv ) , - .mode ( frac_lut4_0_mode ) , - .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , - .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) ) ; -grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_6 frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , - .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , - frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] , - frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , - frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , - frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , - frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_6 ( - prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p3 ) ; -input [0:0] prog_clk ; -input [0:3] frac_logic_in ; -input [0:0] ccff_head ; -output [0:1] frac_logic_out ; -output [0:0] ccff_tail ; -input p3 ; - -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; -wire [0:1] mux_frac_logic_out_0_undriven_sram_inv ; -wire [0:1] mux_tree_size2_0_sram ; - -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( - .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , - .ccff_head ( ccff_head ) , - .frac_lut4_lut3_out ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] , - frac_logic_out[1] } ) , - - .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , - .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ; -grid_clb_mux_tree_size2_30 mux_frac_logic_out_0 ( - .in ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] - } ) , - .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_frac_logic_out_0_undriven_sram_inv ) , - .out ( frac_logic_out[0] ) , .p3 ( p3 ) ) ; -grid_clb_mux_tree_size2_mem_30 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) ) ; -grid_clb_direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( frac_logic_out[1] ) ) ; -grid_clb_direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( frac_logic_in[0] ) ) ; -grid_clb_direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( frac_logic_in[1] ) ) ; -grid_clb_direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( frac_logic_in[2] ) ) ; -grid_clb_direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( frac_logic_in[3] ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_6 ( - prog_clk , Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , - fabric_clk , ccff_head , fabric_out , fabric_regout , fabric_sc_out , - ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p0 , p3 ) ; -input [0:0] prog_clk ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:3] fabric_in ; -input [0:0] fabric_regin ; -input [0:0] fabric_sc_in ; -input [0:0] fabric_clk ; -input [0:0] ccff_head ; -output [0:1] fabric_out ; -output [0:0] fabric_regout ; -output [0:0] fabric_sc_out ; -output [0:0] ccff_tail ; -output p_abuf0 ; -output p_abuf1 ; -output p_abuf2 ; -input p0 ; -input p3 ; - -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; -wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; -wire [0:1] mux_fabric_out_0_undriven_sram_inv ; -wire [0:1] mux_fabric_out_1_undriven_sram_inv ; -wire [0:1] mux_ff_0_D_0_undriven_sram_inv ; -wire [0:1] mux_tree_size2_0_sram ; -wire [0:1] mux_tree_size2_1_sram ; -wire [0:0] mux_tree_size2_2_out ; -wire [0:1] mux_tree_size2_2_sram ; -wire [0:0] mux_tree_size2_mem_0_ccff_tail ; -wire [0:0] mux_tree_size2_mem_1_ccff_tail ; - -assign fabric_regout[0] = fabric_sc_out[0] ; - -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( - .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , - .ccff_head ( ccff_head ) , - .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , - .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .p3 ( p3 ) ) ; -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_12 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( - .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , - .ff_DI ( fabric_sc_in ) , - .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , - .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_13 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( - .Test_en ( Test_en ) , .clk ( clk ) , - .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , - .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , - .ff_Q ( fabric_sc_out ) , - .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; -grid_clb_mux_tree_size2_18 mux_fabric_out_0 ( - .in ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] - } ) , - .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_fabric_out_0_undriven_sram_inv ) , - .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , - .p0 ( p0 ) ) ; -grid_clb_mux_tree_size2_19 mux_fabric_out_1 ( - .in ( { fabric_sc_out[0] , - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] - } ) , - .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( mux_fabric_out_1_undriven_sram_inv ) , - .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf2 ) , .p0 ( p0 ) ) ; -grid_clb_mux_tree_size2_20 mux_ff_0_D_0 ( - .in ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , - fabric_regin[0] } ) , - .sram ( mux_tree_size2_2_sram ) , - .sram_inv ( mux_ff_0_D_0_undriven_sram_inv ) , - .out ( mux_tree_size2_2_out ) , .p3 ( p3 ) ) ; -grid_clb_mux_tree_size2_mem_18 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_size2_0_sram ) ) ; -grid_clb_mux_tree_size2_mem_19 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_size2_1_sram ) ) ; -grid_clb_mux_tree_size2_mem_20 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , - .mem_out ( mux_tree_size2_2_sram ) ) ; -grid_clb_direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fabric_sc_out ) ) ; -grid_clb_direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fabric_sc_out ) ) ; -grid_clb_direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( fabric_in[0] ) ) ; -grid_clb_direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_6 } ) , - .out ( fabric_in[1] ) ) ; -grid_clb_direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_7 } ) , - .out ( fabric_in[2] ) ) ; -grid_clb_direct_interc direct_interc_5_ ( - .in ( { SYNOPSYS_UNCONNECTED_8 } ) , - .out ( fabric_in[3] ) ) ; -grid_clb_direct_interc direct_interc_6_ ( - .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( fabric_sc_in ) ) ; -grid_clb_direct_interc direct_interc_7_ ( - .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( fabric_clk ) ) ; -grid_clb_direct_interc direct_interc_8_ ( - .in ( { SYNOPSYS_UNCONNECTED_11 } ) , - - .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) ) ; -grid_clb_direct_interc direct_interc_9_ ( - .in ( { SYNOPSYS_UNCONNECTED_12 } ) , - - .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ) ; -grid_clb_direct_interc direct_interc_10_ ( - .in ( { SYNOPSYS_UNCONNECTED_13 } ) , - .out ( fabric_clk ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_6 ( prog_clk , Test_en , - clk , fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , - fle_regout , fle_sc_out , ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p0 , - p3 ) ; -input [0:0] prog_clk ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:3] fle_in ; -input [0:0] fle_regin ; -input [0:0] fle_sc_in ; -input [0:0] fle_clk ; -input [0:0] ccff_head ; -output [0:1] fle_out ; -output [0:0] fle_regout ; -output [0:0] fle_sc_out ; -output [0:0] ccff_tail ; -output p_abuf0 ; -output p_abuf1 ; -output p_abuf2 ; -input p0 ; -input p3 ; - -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( - .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , - .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , - .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , - .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , - .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , - .p_abuf2 ( p_abuf2 ) , .p0 ( p0 ) , .p3 ( p3 ) ) ; -grid_clb_direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( { p_abuf1 } ) ) ; -grid_clb_direct_interc_4 direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( { SYNOPSYS_UNCONNECTED_3 } ) ) ; -grid_clb_direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fle_regout ) ) ; -grid_clb_direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( fle_sc_out ) ) ; -grid_clb_direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_6 } ) , - .out ( fle_in[0] ) ) ; -grid_clb_direct_interc direct_interc_5_ ( - .in ( { SYNOPSYS_UNCONNECTED_7 } ) , - .out ( fle_in[1] ) ) ; -grid_clb_direct_interc direct_interc_6_ ( - .in ( { SYNOPSYS_UNCONNECTED_8 } ) , - .out ( fle_in[2] ) ) ; -grid_clb_direct_interc direct_interc_7_ ( - .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( fle_in[3] ) ) ; -grid_clb_direct_interc direct_interc_8_ ( - .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( fle_regin ) ) ; -grid_clb_direct_interc direct_interc_9_ ( - .in ( { SYNOPSYS_UNCONNECTED_11 } ) , - .out ( fle_sc_in ) ) ; -grid_clb_direct_interc direct_interc_10_ ( - .in ( { SYNOPSYS_UNCONNECTED_12 } ) , - .out ( fle_clk ) ) ; -endmodule - - -module grid_clb_direct_interc_3 ( in , out ) ; -input [0:0] in ; -output [0:0] out ; -endmodule - - -module grid_clb_mux_tree_size2_mem_17 ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__47 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_mem_16 ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__46 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_mem_15 ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_28__45 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module grid_clb_const1_23 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module grid_clb_mux_tree_size2_17 ( in , sram , sram_inv , out , p3 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p3 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -grid_clb_const1_23 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module grid_clb_const1_22 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module grid_clb_mux_tree_size2_16 ( in , sram , sram_inv , out , p_abuf0 , - p3 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -output p_abuf0 ; -input p3 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -grid_clb_const1_22 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_123 ( .A ( out[0] ) , .X ( p_abuf0 ) ) ; -endmodule - - -module grid_clb_const1_21 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module grid_clb_mux_tree_size2_15 ( in , sram , sram_inv , out , p_abuf0 , - p_abuf1 , p3 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -output p_abuf0 ; -output p_abuf1 ; -input p3 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -grid_clb_const1_21 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf1 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_82 ( .A ( p_abuf1 ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_83 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_11 ( - Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:0] ff_D ; -input [0:0] ff_DI ; -output [0:0] ff_Q ; -input [0:0] ff_clk ; - -sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , - .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_10 ( - Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:0] ff_D ; -input [0:0] ff_DI ; -output [0:0] ff_Q ; -input [0:0] ff_clk ; - -sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , - .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_mem_29 ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_27__44 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module grid_clb_const1_20 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module grid_clb_mux_tree_size2_29 ( in , sram , sram_inv , out , p3 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p3 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -grid_clb_const1_20 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_5 ( prog_clk , - ccff_head , ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:16] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_5_ ( .D ( mem_out[4] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_6_ ( .D ( mem_out[5] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_7_ ( .D ( mem_out[6] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_8_ ( .D ( mem_out[7] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_9_ ( .D ( mem_out[8] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_10_ ( .D ( mem_out[9] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_11_ ( .D ( mem_out[10] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_12_ ( .D ( mem_out[11] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_13_ ( .D ( mem_out[12] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_14_ ( .D ( mem_out[13] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_15_ ( .D ( mem_out[14] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_16_ ( .D ( mem_out[15] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_26__43 ( .A ( mem_out[16] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module grid_clb_frac_lut4_mux_5 ( in , sram , sram_inv , lut3_out , lut4_out ) ; -input [0:15] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:1] lut3_out ; -output [0:0] lut4_out ; - -wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_4_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_5_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( - .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( - .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( - .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( - .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_5_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_6_ ( - .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__buf_2_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__buf_2_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__buf_2_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ; -endmodule - - -module grid_clb_frac_lut4_5 ( in , sram , sram_inv , mode , mode_inv , - lut3_out , lut4_out ) ; -input [0:3] in ; -input [0:15] sram ; -input [0:15] sram_inv ; -input [0:0] mode ; -input [0:0] mode_inv ; -output [0:1] lut3_out ; -output [0:0] lut4_out ; - -wire [0:0] sky130_fd_sc_hd__buf_2_0_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_1_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_2_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; -wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ; -wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ; -wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ; -wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ; -wire [0:0] sky130_fd_sc_hd__or2_1_0_X ; - -sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , - .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , - .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , - .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , - .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( - .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , - .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , - .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , - .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , - .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( - .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; -grid_clb_frac_lut4_mux_5 frac_lut4_mux_0_ ( .in ( sram ) , - .sram ( { sky130_fd_sc_hd__buf_2_0_X[0] , sky130_fd_sc_hd__buf_2_1_X[0] , - sky130_fd_sc_hd__buf_2_2_X[0] , sky130_fd_sc_hd__buf_2_3_X[0] } ) , - .sram_inv ( { sky130_fd_sc_hd__inv_1_0_Y[0] , - sky130_fd_sc_hd__inv_1_1_Y[0] , sky130_fd_sc_hd__inv_1_2_Y[0] , - sky130_fd_sc_hd__inv_1_3_Y[0] } ) , - .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_5 ( - prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out , - frac_lut4_lut4_out , ccff_tail ) ; -input [0:0] prog_clk ; -input [0:3] frac_lut4_in ; -input [0:0] ccff_head ; -output [0:1] frac_lut4_lut3_out ; -output [0:0] frac_lut4_lut4_out ; -output [0:0] ccff_tail ; - -wire [0:15] frac_lut4_0__undriven_sram_inv ; -wire [0:0] frac_lut4_0_mode ; -wire [0:15] frac_lut4_0_sram ; - -grid_clb_frac_lut4_5 frac_lut4_0_ ( .in ( frac_lut4_in ) , - .sram ( frac_lut4_0_sram ) , - .sram_inv ( frac_lut4_0__undriven_sram_inv ) , - .mode ( frac_lut4_0_mode ) , - .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , - .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) ) ; -grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_5 frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , - .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , - frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] , - frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , - frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , - frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , - frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_5 ( - prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p3 ) ; -input [0:0] prog_clk ; -input [0:3] frac_logic_in ; -input [0:0] ccff_head ; -output [0:1] frac_logic_out ; -output [0:0] ccff_tail ; -input p3 ; - -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; -wire [0:1] mux_frac_logic_out_0_undriven_sram_inv ; -wire [0:1] mux_tree_size2_0_sram ; - -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( - .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , - .ccff_head ( ccff_head ) , - .frac_lut4_lut3_out ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] , - frac_logic_out[1] } ) , - - .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , - .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ; -grid_clb_mux_tree_size2_29 mux_frac_logic_out_0 ( - .in ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] - } ) , - .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_frac_logic_out_0_undriven_sram_inv ) , - .out ( frac_logic_out[0] ) , .p3 ( p3 ) ) ; -grid_clb_mux_tree_size2_mem_29 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) ) ; -grid_clb_direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( frac_logic_out[1] ) ) ; -grid_clb_direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( frac_logic_in[0] ) ) ; -grid_clb_direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( frac_logic_in[1] ) ) ; -grid_clb_direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( frac_logic_in[2] ) ) ; -grid_clb_direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( frac_logic_in[3] ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_5 ( - prog_clk , Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , - fabric_clk , ccff_head , fabric_out , fabric_regout , fabric_sc_out , - ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p3 ) ; -input [0:0] prog_clk ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:3] fabric_in ; -input [0:0] fabric_regin ; -input [0:0] fabric_sc_in ; -input [0:0] fabric_clk ; -input [0:0] ccff_head ; -output [0:1] fabric_out ; -output [0:0] fabric_regout ; -output [0:0] fabric_sc_out ; -output [0:0] ccff_tail ; -output p_abuf0 ; -output p_abuf1 ; -output p_abuf2 ; -input p3 ; - -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; -wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; -wire [0:1] mux_fabric_out_0_undriven_sram_inv ; -wire [0:1] mux_fabric_out_1_undriven_sram_inv ; -wire [0:1] mux_ff_0_D_0_undriven_sram_inv ; -wire [0:1] mux_tree_size2_0_sram ; -wire [0:1] mux_tree_size2_1_sram ; -wire [0:0] mux_tree_size2_2_out ; -wire [0:1] mux_tree_size2_2_sram ; -wire [0:0] mux_tree_size2_mem_0_ccff_tail ; -wire [0:0] mux_tree_size2_mem_1_ccff_tail ; - -assign fabric_regout[0] = fabric_sc_out[0] ; - -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( - .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , - .ccff_head ( ccff_head ) , - .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , - .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .p3 ( p3 ) ) ; -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_10 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( - .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , - .ff_DI ( fabric_sc_in ) , - .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , - .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_11 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( - .Test_en ( Test_en ) , .clk ( clk ) , - .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , - .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , - .ff_Q ( fabric_sc_out ) , - .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; -grid_clb_mux_tree_size2_15 mux_fabric_out_0 ( - .in ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] - } ) , - .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_fabric_out_0_undriven_sram_inv ) , - .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , - .p3 ( p3 ) ) ; -grid_clb_mux_tree_size2_16 mux_fabric_out_1 ( - .in ( { fabric_sc_out[0] , - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] - } ) , - .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( mux_fabric_out_1_undriven_sram_inv ) , - .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf2 ) , .p3 ( p3 ) ) ; -grid_clb_mux_tree_size2_17 mux_ff_0_D_0 ( - .in ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , - fabric_regin[0] } ) , - .sram ( mux_tree_size2_2_sram ) , - .sram_inv ( mux_ff_0_D_0_undriven_sram_inv ) , - .out ( mux_tree_size2_2_out ) , .p3 ( p3 ) ) ; -grid_clb_mux_tree_size2_mem_15 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_size2_0_sram ) ) ; -grid_clb_mux_tree_size2_mem_16 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_size2_1_sram ) ) ; -grid_clb_mux_tree_size2_mem_17 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , - .mem_out ( mux_tree_size2_2_sram ) ) ; -grid_clb_direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fabric_sc_out ) ) ; -grid_clb_direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fabric_sc_out ) ) ; -grid_clb_direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( fabric_in[0] ) ) ; -grid_clb_direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_6 } ) , - .out ( fabric_in[1] ) ) ; -grid_clb_direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_7 } ) , - .out ( fabric_in[2] ) ) ; -grid_clb_direct_interc direct_interc_5_ ( - .in ( { SYNOPSYS_UNCONNECTED_8 } ) , - .out ( fabric_in[3] ) ) ; -grid_clb_direct_interc direct_interc_6_ ( - .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( fabric_sc_in ) ) ; -grid_clb_direct_interc direct_interc_7_ ( - .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( fabric_clk ) ) ; -grid_clb_direct_interc direct_interc_8_ ( - .in ( { SYNOPSYS_UNCONNECTED_11 } ) , - - .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) ) ; -grid_clb_direct_interc direct_interc_9_ ( - .in ( { SYNOPSYS_UNCONNECTED_12 } ) , - - .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ) ; -grid_clb_direct_interc direct_interc_10_ ( - .in ( { SYNOPSYS_UNCONNECTED_13 } ) , - .out ( fabric_clk ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_5 ( prog_clk , Test_en , - clk , fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , - fle_regout , fle_sc_out , ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p3 ) ; -input [0:0] prog_clk ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:3] fle_in ; -input [0:0] fle_regin ; -input [0:0] fle_sc_in ; -input [0:0] fle_clk ; -input [0:0] ccff_head ; -output [0:1] fle_out ; -output [0:0] fle_regout ; -output [0:0] fle_sc_out ; -output [0:0] ccff_tail ; -output p_abuf0 ; -output p_abuf1 ; -output p_abuf2 ; -input p3 ; - -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( - .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , - .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , - .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , - .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , - .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , - .p_abuf2 ( p_abuf2 ) , .p3 ( p3 ) ) ; -grid_clb_direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( { p_abuf1 } ) ) ; -grid_clb_direct_interc_3 direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( { SYNOPSYS_UNCONNECTED_3 } ) ) ; -grid_clb_direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fle_regout ) ) ; -grid_clb_direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( fle_sc_out ) ) ; -grid_clb_direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_6 } ) , - .out ( fle_in[0] ) ) ; -grid_clb_direct_interc direct_interc_5_ ( - .in ( { SYNOPSYS_UNCONNECTED_7 } ) , - .out ( fle_in[1] ) ) ; -grid_clb_direct_interc direct_interc_6_ ( - .in ( { SYNOPSYS_UNCONNECTED_8 } ) , - .out ( fle_in[2] ) ) ; -grid_clb_direct_interc direct_interc_7_ ( - .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( fle_in[3] ) ) ; -grid_clb_direct_interc direct_interc_8_ ( - .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( fle_regin ) ) ; -grid_clb_direct_interc direct_interc_9_ ( - .in ( { SYNOPSYS_UNCONNECTED_11 } ) , - .out ( fle_sc_in ) ) ; -grid_clb_direct_interc direct_interc_10_ ( - .in ( { SYNOPSYS_UNCONNECTED_12 } ) , - .out ( fle_clk ) ) ; -endmodule - - -module grid_clb_direct_interc_2 ( in , out ) ; -input [0:0] in ; -output [0:0] out ; -endmodule - - -module grid_clb_mux_tree_size2_mem_14 ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__42 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_mem_13 ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__41 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_mem_12 ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__40 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module grid_clb_const1_19 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module grid_clb_mux_tree_size2_14 ( in , sram , sram_inv , out , p2 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p2 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -grid_clb_const1_19 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module grid_clb_const1_18 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module grid_clb_mux_tree_size2_13 ( in , sram , sram_inv , out , p_abuf0 , - p_abuf1 , p3 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -output p_abuf0 ; -output p_abuf1 ; -input p3 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -grid_clb_const1_18 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf1 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_80 ( .A ( p_abuf1 ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_81 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; -endmodule - - -module grid_clb_const1_17 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module grid_clb_mux_tree_size2_12 ( in , sram , sram_inv , out , p_abuf0 , - p3 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -output p_abuf0 ; -input p3 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -grid_clb_const1_17 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_79 ( .A ( out[0] ) , .X ( p_abuf0 ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_9 ( - Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:0] ff_D ; -input [0:0] ff_DI ; -output [0:0] ff_Q ; -input [0:0] ff_clk ; - -sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , - .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_8 ( - Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:0] ff_D ; -input [0:0] ff_DI ; -output [0:0] ff_Q ; -input [0:0] ff_clk ; - -sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , - .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_mem_28 ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_22__39 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module grid_clb_const1_16 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module grid_clb_mux_tree_size2_28 ( in , sram , sram_inv , out , p2 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p2 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -grid_clb_const1_16 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_4 ( prog_clk , - ccff_head , ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:16] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_5_ ( .D ( mem_out[4] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_6_ ( .D ( mem_out[5] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_7_ ( .D ( mem_out[6] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_8_ ( .D ( mem_out[7] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_9_ ( .D ( mem_out[8] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_10_ ( .D ( mem_out[9] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_11_ ( .D ( mem_out[10] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_12_ ( .D ( mem_out[11] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_13_ ( .D ( mem_out[12] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_14_ ( .D ( mem_out[13] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_15_ ( .D ( mem_out[14] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_16_ ( .D ( mem_out[15] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__38 ( .A ( mem_out[16] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module grid_clb_frac_lut4_mux_4 ( in , sram , sram_inv , lut3_out , lut4_out ) ; -input [0:15] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:1] lut3_out ; -output [0:0] lut4_out ; - -wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_4_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_5_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( - .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( - .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( - .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( - .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_5_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_6_ ( - .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__buf_2_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__buf_2_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__buf_2_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ; -endmodule - - -module grid_clb_frac_lut4_4 ( in , sram , sram_inv , mode , mode_inv , - lut3_out , lut4_out ) ; -input [0:3] in ; -input [0:15] sram ; -input [0:15] sram_inv ; -input [0:0] mode ; -input [0:0] mode_inv ; -output [0:1] lut3_out ; -output [0:0] lut4_out ; - -wire [0:0] sky130_fd_sc_hd__buf_2_0_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_1_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_2_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; -wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ; -wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ; -wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ; -wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ; -wire [0:0] sky130_fd_sc_hd__or2_1_0_X ; - -sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , - .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , - .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , - .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , - .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( - .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , - .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , - .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , - .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , - .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( - .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; -grid_clb_frac_lut4_mux_4 frac_lut4_mux_0_ ( .in ( sram ) , - .sram ( { sky130_fd_sc_hd__buf_2_0_X[0] , sky130_fd_sc_hd__buf_2_1_X[0] , - sky130_fd_sc_hd__buf_2_2_X[0] , sky130_fd_sc_hd__buf_2_3_X[0] } ) , - .sram_inv ( { sky130_fd_sc_hd__inv_1_0_Y[0] , - sky130_fd_sc_hd__inv_1_1_Y[0] , sky130_fd_sc_hd__inv_1_2_Y[0] , - sky130_fd_sc_hd__inv_1_3_Y[0] } ) , - .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_4 ( - prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out , - frac_lut4_lut4_out , ccff_tail ) ; -input [0:0] prog_clk ; -input [0:3] frac_lut4_in ; -input [0:0] ccff_head ; -output [0:1] frac_lut4_lut3_out ; -output [0:0] frac_lut4_lut4_out ; -output [0:0] ccff_tail ; - -wire [0:15] frac_lut4_0__undriven_sram_inv ; -wire [0:0] frac_lut4_0_mode ; -wire [0:15] frac_lut4_0_sram ; - -grid_clb_frac_lut4_4 frac_lut4_0_ ( .in ( frac_lut4_in ) , - .sram ( frac_lut4_0_sram ) , - .sram_inv ( frac_lut4_0__undriven_sram_inv ) , - .mode ( frac_lut4_0_mode ) , - .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , - .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) ) ; -grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_4 frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , - .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , - frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] , - frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , - frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , - frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , - frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_4 ( - prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p2 ) ; -input [0:0] prog_clk ; -input [0:3] frac_logic_in ; -input [0:0] ccff_head ; -output [0:1] frac_logic_out ; -output [0:0] ccff_tail ; -input p2 ; - -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; -wire [0:1] mux_frac_logic_out_0_undriven_sram_inv ; -wire [0:1] mux_tree_size2_0_sram ; - -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( - .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , - .ccff_head ( ccff_head ) , - .frac_lut4_lut3_out ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] , - frac_logic_out[1] } ) , - - .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , - .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ; -grid_clb_mux_tree_size2_28 mux_frac_logic_out_0 ( - .in ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] - } ) , - .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_frac_logic_out_0_undriven_sram_inv ) , - .out ( frac_logic_out[0] ) , .p2 ( p2 ) ) ; -grid_clb_mux_tree_size2_mem_28 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) ) ; -grid_clb_direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( frac_logic_out[1] ) ) ; -grid_clb_direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( frac_logic_in[0] ) ) ; -grid_clb_direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( frac_logic_in[1] ) ) ; -grid_clb_direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( frac_logic_in[2] ) ) ; -grid_clb_direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( frac_logic_in[3] ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_4 ( - prog_clk , Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , - fabric_clk , ccff_head , fabric_out , fabric_regout , fabric_sc_out , - ccff_tail , p_abuf0 , p_abuf2 , p_abuf3 , p2 , p3 ) ; -input [0:0] prog_clk ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:3] fabric_in ; -input [0:0] fabric_regin ; -input [0:0] fabric_sc_in ; -input [0:0] fabric_clk ; -input [0:0] ccff_head ; -output [0:1] fabric_out ; -output [0:0] fabric_regout ; -output [0:0] fabric_sc_out ; -output [0:0] ccff_tail ; -output p_abuf0 ; -output p_abuf2 ; -output p_abuf3 ; -input p2 ; -input p3 ; - -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; -wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; -wire [0:1] mux_fabric_out_0_undriven_sram_inv ; -wire [0:1] mux_fabric_out_1_undriven_sram_inv ; -wire [0:1] mux_ff_0_D_0_undriven_sram_inv ; -wire [0:1] mux_tree_size2_0_sram ; -wire [0:1] mux_tree_size2_1_sram ; -wire [0:0] mux_tree_size2_2_out ; -wire [0:1] mux_tree_size2_2_sram ; -wire [0:0] mux_tree_size2_mem_0_ccff_tail ; -wire [0:0] mux_tree_size2_mem_1_ccff_tail ; - -assign fabric_regout[0] = fabric_sc_out[0] ; - -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( - .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , - .ccff_head ( ccff_head ) , - .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , - .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .p2 ( p2 ) ) ; -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_8 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( - .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , - .ff_DI ( fabric_sc_in ) , - .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , - .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_9 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( - .Test_en ( Test_en ) , .clk ( clk ) , - .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , - .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , - .ff_Q ( fabric_sc_out ) , - .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; -grid_clb_mux_tree_size2_12 mux_fabric_out_0 ( - .in ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] - } ) , - .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_fabric_out_0_undriven_sram_inv ) , - .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p3 ( p3 ) ) ; -grid_clb_mux_tree_size2_13 mux_fabric_out_1 ( - .in ( { fabric_sc_out[0] , - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] - } ) , - .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( mux_fabric_out_1_undriven_sram_inv ) , - .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf2 ) , .p_abuf1 ( p_abuf3 ) , - .p3 ( p3 ) ) ; -grid_clb_mux_tree_size2_14 mux_ff_0_D_0 ( - .in ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , - fabric_regin[0] } ) , - .sram ( mux_tree_size2_2_sram ) , - .sram_inv ( mux_ff_0_D_0_undriven_sram_inv ) , - .out ( mux_tree_size2_2_out ) , .p2 ( p2 ) ) ; -grid_clb_mux_tree_size2_mem_12 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_size2_0_sram ) ) ; -grid_clb_mux_tree_size2_mem_13 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_size2_1_sram ) ) ; -grid_clb_mux_tree_size2_mem_14 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , - .mem_out ( mux_tree_size2_2_sram ) ) ; -grid_clb_direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fabric_sc_out ) ) ; -grid_clb_direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fabric_sc_out ) ) ; -grid_clb_direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( fabric_in[0] ) ) ; -grid_clb_direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_6 } ) , - .out ( fabric_in[1] ) ) ; -grid_clb_direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_7 } ) , - .out ( fabric_in[2] ) ) ; -grid_clb_direct_interc direct_interc_5_ ( - .in ( { SYNOPSYS_UNCONNECTED_8 } ) , - .out ( fabric_in[3] ) ) ; -grid_clb_direct_interc direct_interc_6_ ( - .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( fabric_sc_in ) ) ; -grid_clb_direct_interc direct_interc_7_ ( - .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( fabric_clk ) ) ; -grid_clb_direct_interc direct_interc_8_ ( - .in ( { SYNOPSYS_UNCONNECTED_11 } ) , - - .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) ) ; -grid_clb_direct_interc direct_interc_9_ ( - .in ( { SYNOPSYS_UNCONNECTED_12 } ) , - - .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ) ; -grid_clb_direct_interc direct_interc_10_ ( - .in ( { SYNOPSYS_UNCONNECTED_13 } ) , - .out ( fabric_clk ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_4 ( prog_clk , Test_en , - clk , fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , - fle_regout , fle_sc_out , ccff_tail , p_abuf0 , p_abuf2 , p_abuf3 , p2 , - p3 ) ; -input [0:0] prog_clk ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:3] fle_in ; -input [0:0] fle_regin ; -input [0:0] fle_sc_in ; -input [0:0] fle_clk ; -input [0:0] ccff_head ; -output [0:1] fle_out ; -output [0:0] fle_regout ; -output [0:0] fle_sc_out ; -output [0:0] ccff_tail ; -output p_abuf0 ; -output p_abuf2 ; -output p_abuf3 ; -input p2 ; -input p3 ; - -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( - .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , - .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , - .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , - .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , - .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf2 ( p_abuf2 ) , - .p_abuf3 ( p_abuf3 ) , .p2 ( p2 ) , .p3 ( p3 ) ) ; -grid_clb_direct_interc_2 direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; -grid_clb_direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( { p_abuf3 } ) ) ; -grid_clb_direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fle_regout ) ) ; -grid_clb_direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( fle_sc_out ) ) ; -grid_clb_direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_6 } ) , - .out ( fle_in[0] ) ) ; -grid_clb_direct_interc direct_interc_5_ ( - .in ( { SYNOPSYS_UNCONNECTED_7 } ) , - .out ( fle_in[1] ) ) ; -grid_clb_direct_interc direct_interc_6_ ( - .in ( { SYNOPSYS_UNCONNECTED_8 } ) , - .out ( fle_in[2] ) ) ; -grid_clb_direct_interc direct_interc_7_ ( - .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( fle_in[3] ) ) ; -grid_clb_direct_interc direct_interc_8_ ( - .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( fle_regin ) ) ; -grid_clb_direct_interc direct_interc_9_ ( - .in ( { SYNOPSYS_UNCONNECTED_11 } ) , - .out ( fle_sc_in ) ) ; -grid_clb_direct_interc direct_interc_10_ ( - .in ( { SYNOPSYS_UNCONNECTED_12 } ) , - .out ( fle_clk ) ) ; -endmodule - - -module grid_clb_direct_interc_1 ( in , out ) ; -input [0:0] in ; -output [0:0] out ; -endmodule - - -module grid_clb_mux_tree_size2_mem_11 ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__37 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_mem_10 ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__36 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_mem_9 ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__35 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module grid_clb_const1_15 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module grid_clb_mux_tree_size2_11 ( in , sram , sram_inv , out , p2 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p2 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -grid_clb_const1_15 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module grid_clb_const1_14 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module grid_clb_mux_tree_size2_10 ( in , sram , sram_inv , out , p_abuf0 , - p_abuf1 , p2 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -output p_abuf0 ; -output p_abuf1 ; -input p2 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -grid_clb_const1_14 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf1 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_76 ( .A ( p_abuf1 ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_77 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; -endmodule - - -module grid_clb_const1_13 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module grid_clb_mux_tree_size2_9 ( in , sram , sram_inv , out , p_abuf0 , p2 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -output p_abuf0 ; -input p2 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -grid_clb_const1_13 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p2 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_75 ( .A ( out[0] ) , .X ( p_abuf0 ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_7 ( - Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:0] ff_D ; -input [0:0] ff_DI ; -output [0:0] ff_Q ; -input [0:0] ff_clk ; - -sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , - .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_6 ( - Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:0] ff_D ; -input [0:0] ff_DI ; -output [0:0] ff_Q ; -input [0:0] ff_clk ; - -sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , - .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_mem_27 ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__34 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module grid_clb_const1_12 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module grid_clb_mux_tree_size2_27 ( in , sram , sram_inv , out , p2 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p2 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -grid_clb_const1_12 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_3 ( prog_clk , - ccff_head , ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:16] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_5_ ( .D ( mem_out[4] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_6_ ( .D ( mem_out[5] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_7_ ( .D ( mem_out[6] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_8_ ( .D ( mem_out[7] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_9_ ( .D ( mem_out[8] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_10_ ( .D ( mem_out[9] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_11_ ( .D ( mem_out[10] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_12_ ( .D ( mem_out[11] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_13_ ( .D ( mem_out[12] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_14_ ( .D ( mem_out[13] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_15_ ( .D ( mem_out[14] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_16_ ( .D ( mem_out[15] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__33 ( .A ( mem_out[16] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module grid_clb_frac_lut4_mux_3 ( in , sram , sram_inv , lut3_out , lut4_out ) ; -input [0:15] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:1] lut3_out ; -output [0:0] lut4_out ; - -wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_4_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_5_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( - .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( - .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( - .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_5_ ( - .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_5_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_6_ ( - .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__buf_2_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__buf_2_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__buf_2_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ; -endmodule - - -module grid_clb_frac_lut4_3 ( in , sram , sram_inv , mode , mode_inv , - lut3_out , lut4_out ) ; -input [0:3] in ; -input [0:15] sram ; -input [0:15] sram_inv ; -input [0:0] mode ; -input [0:0] mode_inv ; -output [0:1] lut3_out ; -output [0:0] lut4_out ; - -wire [0:0] sky130_fd_sc_hd__buf_2_0_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_1_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_2_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; -wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ; -wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ; -wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ; -wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ; -wire [0:0] sky130_fd_sc_hd__or2_1_0_X ; - -sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , - .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , - .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , - .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , - .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( - .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , - .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , - .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , - .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , - .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( - .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; -grid_clb_frac_lut4_mux_3 frac_lut4_mux_0_ ( .in ( sram ) , - .sram ( { sky130_fd_sc_hd__buf_2_0_X[0] , sky130_fd_sc_hd__buf_2_1_X[0] , - sky130_fd_sc_hd__buf_2_2_X[0] , sky130_fd_sc_hd__buf_2_3_X[0] } ) , - .sram_inv ( { sky130_fd_sc_hd__inv_1_0_Y[0] , - sky130_fd_sc_hd__inv_1_1_Y[0] , sky130_fd_sc_hd__inv_1_2_Y[0] , - sky130_fd_sc_hd__inv_1_3_Y[0] } ) , - .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_3 ( - prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out , - frac_lut4_lut4_out , ccff_tail ) ; -input [0:0] prog_clk ; -input [0:3] frac_lut4_in ; -input [0:0] ccff_head ; -output [0:1] frac_lut4_lut3_out ; -output [0:0] frac_lut4_lut4_out ; -output [0:0] ccff_tail ; - -wire [0:15] frac_lut4_0__undriven_sram_inv ; -wire [0:0] frac_lut4_0_mode ; -wire [0:15] frac_lut4_0_sram ; - -grid_clb_frac_lut4_3 frac_lut4_0_ ( .in ( frac_lut4_in ) , - .sram ( frac_lut4_0_sram ) , - .sram_inv ( frac_lut4_0__undriven_sram_inv ) , - .mode ( frac_lut4_0_mode ) , - .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , - .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) ) ; -grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_3 frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , - .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , - frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] , - frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , - frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , - frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , - frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_3 ( - prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p2 ) ; -input [0:0] prog_clk ; -input [0:3] frac_logic_in ; -input [0:0] ccff_head ; -output [0:1] frac_logic_out ; -output [0:0] ccff_tail ; -input p2 ; - -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; -wire [0:1] mux_frac_logic_out_0_undriven_sram_inv ; -wire [0:1] mux_tree_size2_0_sram ; - -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( - .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , - .ccff_head ( ccff_head ) , - .frac_lut4_lut3_out ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] , - frac_logic_out[1] } ) , - - .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , - .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ; -grid_clb_mux_tree_size2_27 mux_frac_logic_out_0 ( - .in ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] - } ) , - .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_frac_logic_out_0_undriven_sram_inv ) , - .out ( frac_logic_out[0] ) , .p2 ( p2 ) ) ; -grid_clb_mux_tree_size2_mem_27 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) ) ; -grid_clb_direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( frac_logic_out[1] ) ) ; -grid_clb_direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( frac_logic_in[0] ) ) ; -grid_clb_direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( frac_logic_in[1] ) ) ; -grid_clb_direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( frac_logic_in[2] ) ) ; -grid_clb_direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( frac_logic_in[3] ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_3 ( - prog_clk , Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , - fabric_clk , ccff_head , fabric_out , fabric_regout , fabric_sc_out , - ccff_tail , p_abuf0 , p_abuf2 , p_abuf3 , p2 ) ; -input [0:0] prog_clk ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:3] fabric_in ; -input [0:0] fabric_regin ; -input [0:0] fabric_sc_in ; -input [0:0] fabric_clk ; -input [0:0] ccff_head ; -output [0:1] fabric_out ; -output [0:0] fabric_regout ; -output [0:0] fabric_sc_out ; -output [0:0] ccff_tail ; -output p_abuf0 ; -output p_abuf2 ; -output p_abuf3 ; -input p2 ; - -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; -wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; -wire [0:1] mux_fabric_out_0_undriven_sram_inv ; -wire [0:1] mux_fabric_out_1_undriven_sram_inv ; -wire [0:1] mux_ff_0_D_0_undriven_sram_inv ; -wire [0:1] mux_tree_size2_0_sram ; -wire [0:1] mux_tree_size2_1_sram ; -wire [0:0] mux_tree_size2_2_out ; -wire [0:1] mux_tree_size2_2_sram ; -wire [0:0] mux_tree_size2_mem_0_ccff_tail ; -wire [0:0] mux_tree_size2_mem_1_ccff_tail ; - -assign fabric_regout[0] = fabric_sc_out[0] ; - -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( - .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , - .ccff_head ( ccff_head ) , - .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , - .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .p2 ( p2 ) ) ; -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( - .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , - .ff_DI ( fabric_sc_in ) , - .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , - .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_7 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( - .Test_en ( Test_en ) , .clk ( clk ) , - .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , - .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , - .ff_Q ( fabric_sc_out ) , - .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; -grid_clb_mux_tree_size2_9 mux_fabric_out_0 ( - .in ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] - } ) , - .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_fabric_out_0_undriven_sram_inv ) , - .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p2 ( p2 ) ) ; -grid_clb_mux_tree_size2_10 mux_fabric_out_1 ( - .in ( { fabric_sc_out[0] , - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] - } ) , - .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( mux_fabric_out_1_undriven_sram_inv ) , - .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf2 ) , .p_abuf1 ( p_abuf3 ) , - .p2 ( p2 ) ) ; -grid_clb_mux_tree_size2_11 mux_ff_0_D_0 ( - .in ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , - fabric_regin[0] } ) , - .sram ( mux_tree_size2_2_sram ) , - .sram_inv ( mux_ff_0_D_0_undriven_sram_inv ) , - .out ( mux_tree_size2_2_out ) , .p2 ( p2 ) ) ; -grid_clb_mux_tree_size2_mem_9 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_size2_0_sram ) ) ; -grid_clb_mux_tree_size2_mem_10 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_size2_1_sram ) ) ; -grid_clb_mux_tree_size2_mem_11 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , - .mem_out ( mux_tree_size2_2_sram ) ) ; -grid_clb_direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fabric_sc_out ) ) ; -grid_clb_direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fabric_sc_out ) ) ; -grid_clb_direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( fabric_in[0] ) ) ; -grid_clb_direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_6 } ) , - .out ( fabric_in[1] ) ) ; -grid_clb_direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_7 } ) , - .out ( fabric_in[2] ) ) ; -grid_clb_direct_interc direct_interc_5_ ( - .in ( { SYNOPSYS_UNCONNECTED_8 } ) , - .out ( fabric_in[3] ) ) ; -grid_clb_direct_interc direct_interc_6_ ( - .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( fabric_sc_in ) ) ; -grid_clb_direct_interc direct_interc_7_ ( - .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( fabric_clk ) ) ; -grid_clb_direct_interc direct_interc_8_ ( - .in ( { SYNOPSYS_UNCONNECTED_11 } ) , - - .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) ) ; -grid_clb_direct_interc direct_interc_9_ ( - .in ( { SYNOPSYS_UNCONNECTED_12 } ) , - - .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ) ; -grid_clb_direct_interc direct_interc_10_ ( - .in ( { SYNOPSYS_UNCONNECTED_13 } ) , - .out ( fabric_clk ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_3 ( prog_clk , Test_en , - clk , fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , - fle_regout , fle_sc_out , ccff_tail , p_abuf0 , p_abuf2 , p_abuf3 , p2 ) ; -input [0:0] prog_clk ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:3] fle_in ; -input [0:0] fle_regin ; -input [0:0] fle_sc_in ; -input [0:0] fle_clk ; -input [0:0] ccff_head ; -output [0:1] fle_out ; -output [0:0] fle_regout ; -output [0:0] fle_sc_out ; -output [0:0] ccff_tail ; -output p_abuf0 ; -output p_abuf2 ; -output p_abuf3 ; -input p2 ; - -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( - .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , - .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , - .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , - .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , - .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf2 ( p_abuf2 ) , - .p_abuf3 ( p_abuf3 ) , .p2 ( p2 ) ) ; -grid_clb_direct_interc_1 direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; -grid_clb_direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( { p_abuf3 } ) ) ; -grid_clb_direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fle_regout ) ) ; -grid_clb_direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( fle_sc_out ) ) ; -grid_clb_direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_6 } ) , - .out ( fle_in[0] ) ) ; -grid_clb_direct_interc direct_interc_5_ ( - .in ( { SYNOPSYS_UNCONNECTED_7 } ) , - .out ( fle_in[1] ) ) ; -grid_clb_direct_interc direct_interc_6_ ( - .in ( { SYNOPSYS_UNCONNECTED_8 } ) , - .out ( fle_in[2] ) ) ; -grid_clb_direct_interc direct_interc_7_ ( - .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( fle_in[3] ) ) ; -grid_clb_direct_interc direct_interc_8_ ( - .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( fle_regin ) ) ; -grid_clb_direct_interc direct_interc_9_ ( - .in ( { SYNOPSYS_UNCONNECTED_11 } ) , - .out ( fle_sc_in ) ) ; -grid_clb_direct_interc direct_interc_10_ ( - .in ( { SYNOPSYS_UNCONNECTED_12 } ) , - .out ( fle_clk ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_mem_8 ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__32 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_mem_7 ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__31 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__30 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module grid_clb_const1_11 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module grid_clb_mux_tree_size2_8 ( in , sram , sram_inv , out , p2 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p2 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -grid_clb_const1_11 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module grid_clb_const1_10 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module grid_clb_mux_tree_size2_7 ( in , sram , sram_inv , out , p_abuf0 , - p_abuf1 , p2 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -output p_abuf0 ; -output p_abuf1 ; -input p2 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -grid_clb_const1_10 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf1 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_72 ( .A ( p_abuf1 ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_73 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; -endmodule - - -module grid_clb_const1_9 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module grid_clb_mux_tree_size2_6 ( in , sram , sram_inv , out , p_abuf0 , - p_abuf1 , p2 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -output p_abuf0 ; -output p_abuf1 ; -input p2 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -grid_clb_const1_9 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf1 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_70 ( .A ( p_abuf1 ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_71 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_5 ( - Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:0] ff_D ; -input [0:0] ff_DI ; -output [0:0] ff_Q ; -input [0:0] ff_clk ; - -sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , - .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_4 ( - Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:0] ff_D ; -input [0:0] ff_DI ; -output [0:0] ff_Q ; -input [0:0] ff_clk ; - -sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , - .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_mem_26 ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__29 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module grid_clb_const1_8 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module grid_clb_mux_tree_size2_26 ( in , sram , sram_inv , out , p2 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p2 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -grid_clb_const1_8 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_2 ( prog_clk , - ccff_head , ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:16] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_5_ ( .D ( mem_out[4] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_6_ ( .D ( mem_out[5] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_7_ ( .D ( mem_out[6] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_8_ ( .D ( mem_out[7] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_9_ ( .D ( mem_out[8] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_10_ ( .D ( mem_out[9] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_11_ ( .D ( mem_out[10] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_12_ ( .D ( mem_out[11] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_13_ ( .D ( mem_out[12] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_14_ ( .D ( mem_out[13] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_15_ ( .D ( mem_out[14] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_16_ ( .D ( mem_out[15] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__28 ( .A ( mem_out[16] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module grid_clb_frac_lut4_mux_2 ( in , sram , sram_inv , lut3_out , lut4_out ) ; -input [0:15] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:1] lut3_out ; -output [0:0] lut4_out ; - -wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_4_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_5_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( - .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( - .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( - .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( - .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_5_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_6_ ( - .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__buf_2_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__buf_2_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__buf_2_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ; -endmodule - - -module grid_clb_frac_lut4_2 ( in , sram , sram_inv , mode , mode_inv , - lut3_out , lut4_out ) ; -input [0:3] in ; -input [0:15] sram ; -input [0:15] sram_inv ; -input [0:0] mode ; -input [0:0] mode_inv ; -output [0:1] lut3_out ; -output [0:0] lut4_out ; - -wire [0:0] sky130_fd_sc_hd__buf_2_0_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_1_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_2_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; -wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ; -wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ; -wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ; -wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ; -wire [0:0] sky130_fd_sc_hd__or2_1_0_X ; - -sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , - .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , - .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , - .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , - .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( - .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , - .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , - .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , - .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , - .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( - .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; -grid_clb_frac_lut4_mux_2 frac_lut4_mux_0_ ( .in ( sram ) , - .sram ( { sky130_fd_sc_hd__buf_2_0_X[0] , sky130_fd_sc_hd__buf_2_1_X[0] , - sky130_fd_sc_hd__buf_2_2_X[0] , sky130_fd_sc_hd__buf_2_3_X[0] } ) , - .sram_inv ( { sky130_fd_sc_hd__inv_1_0_Y[0] , - sky130_fd_sc_hd__inv_1_1_Y[0] , sky130_fd_sc_hd__inv_1_2_Y[0] , - sky130_fd_sc_hd__inv_1_3_Y[0] } ) , - .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_2 ( - prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out , - frac_lut4_lut4_out , ccff_tail ) ; -input [0:0] prog_clk ; -input [0:3] frac_lut4_in ; -input [0:0] ccff_head ; -output [0:1] frac_lut4_lut3_out ; -output [0:0] frac_lut4_lut4_out ; -output [0:0] ccff_tail ; - -wire [0:15] frac_lut4_0__undriven_sram_inv ; -wire [0:0] frac_lut4_0_mode ; -wire [0:15] frac_lut4_0_sram ; - -grid_clb_frac_lut4_2 frac_lut4_0_ ( .in ( frac_lut4_in ) , - .sram ( frac_lut4_0_sram ) , - .sram_inv ( frac_lut4_0__undriven_sram_inv ) , - .mode ( frac_lut4_0_mode ) , - .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , - .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) ) ; -grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_2 frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , - .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , - frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] , - frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , - frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , - frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , - frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_2 ( - prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p2 ) ; -input [0:0] prog_clk ; -input [0:3] frac_logic_in ; -input [0:0] ccff_head ; -output [0:1] frac_logic_out ; -output [0:0] ccff_tail ; -input p2 ; - -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; -wire [0:1] mux_frac_logic_out_0_undriven_sram_inv ; -wire [0:1] mux_tree_size2_0_sram ; - -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( - .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , - .ccff_head ( ccff_head ) , - .frac_lut4_lut3_out ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] , - frac_logic_out[1] } ) , - - .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , - .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ; -grid_clb_mux_tree_size2_26 mux_frac_logic_out_0 ( - .in ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] - } ) , - .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_frac_logic_out_0_undriven_sram_inv ) , - .out ( frac_logic_out[0] ) , .p2 ( p2 ) ) ; -grid_clb_mux_tree_size2_mem_26 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) ) ; -grid_clb_direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( frac_logic_out[1] ) ) ; -grid_clb_direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( frac_logic_in[0] ) ) ; -grid_clb_direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( frac_logic_in[1] ) ) ; -grid_clb_direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( frac_logic_in[2] ) ) ; -grid_clb_direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( frac_logic_in[3] ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_2 ( - prog_clk , Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , - fabric_clk , ccff_head , fabric_out , fabric_regout , fabric_sc_out , - ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p_abuf3 , p2 ) ; -input [0:0] prog_clk ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:3] fabric_in ; -input [0:0] fabric_regin ; -input [0:0] fabric_sc_in ; -input [0:0] fabric_clk ; -input [0:0] ccff_head ; -output [0:1] fabric_out ; -output [0:0] fabric_regout ; -output [0:0] fabric_sc_out ; -output [0:0] ccff_tail ; -output p_abuf0 ; -output p_abuf1 ; -output p_abuf2 ; -output p_abuf3 ; -input p2 ; - -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; -wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; -wire [0:1] mux_fabric_out_0_undriven_sram_inv ; -wire [0:1] mux_fabric_out_1_undriven_sram_inv ; -wire [0:1] mux_ff_0_D_0_undriven_sram_inv ; -wire [0:1] mux_tree_size2_0_sram ; -wire [0:1] mux_tree_size2_1_sram ; -wire [0:0] mux_tree_size2_2_out ; -wire [0:1] mux_tree_size2_2_sram ; -wire [0:0] mux_tree_size2_mem_0_ccff_tail ; -wire [0:0] mux_tree_size2_mem_1_ccff_tail ; - -assign fabric_regout[0] = fabric_sc_out[0] ; - -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( - .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , - .ccff_head ( ccff_head ) , - .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , - .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .p2 ( p2 ) ) ; -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( - .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , - .ff_DI ( fabric_sc_in ) , - .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , - .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( - .Test_en ( Test_en ) , .clk ( clk ) , - .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , - .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , - .ff_Q ( fabric_sc_out ) , - .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; -grid_clb_mux_tree_size2_6 mux_fabric_out_0 ( - .in ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] - } ) , - .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_fabric_out_0_undriven_sram_inv ) , - .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , - .p2 ( p2 ) ) ; -grid_clb_mux_tree_size2_7 mux_fabric_out_1 ( - .in ( { fabric_sc_out[0] , - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] - } ) , - .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( mux_fabric_out_1_undriven_sram_inv ) , - .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf2 ) , .p_abuf1 ( p_abuf3 ) , - .p2 ( p2 ) ) ; -grid_clb_mux_tree_size2_8 mux_ff_0_D_0 ( - .in ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , - fabric_regin[0] } ) , - .sram ( mux_tree_size2_2_sram ) , - .sram_inv ( mux_ff_0_D_0_undriven_sram_inv ) , - .out ( mux_tree_size2_2_out ) , .p2 ( p2 ) ) ; -grid_clb_mux_tree_size2_mem_6 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_size2_0_sram ) ) ; -grid_clb_mux_tree_size2_mem_7 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_size2_1_sram ) ) ; -grid_clb_mux_tree_size2_mem_8 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , - .mem_out ( mux_tree_size2_2_sram ) ) ; -grid_clb_direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fabric_sc_out ) ) ; -grid_clb_direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fabric_sc_out ) ) ; -grid_clb_direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( fabric_in[0] ) ) ; -grid_clb_direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_6 } ) , - .out ( fabric_in[1] ) ) ; -grid_clb_direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_7 } ) , - .out ( fabric_in[2] ) ) ; -grid_clb_direct_interc direct_interc_5_ ( - .in ( { SYNOPSYS_UNCONNECTED_8 } ) , - .out ( fabric_in[3] ) ) ; -grid_clb_direct_interc direct_interc_6_ ( - .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( fabric_sc_in ) ) ; -grid_clb_direct_interc direct_interc_7_ ( - .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( fabric_clk ) ) ; -grid_clb_direct_interc direct_interc_8_ ( - .in ( { SYNOPSYS_UNCONNECTED_11 } ) , - - .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) ) ; -grid_clb_direct_interc direct_interc_9_ ( - .in ( { SYNOPSYS_UNCONNECTED_12 } ) , - - .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ) ; -grid_clb_direct_interc direct_interc_10_ ( - .in ( { SYNOPSYS_UNCONNECTED_13 } ) , - .out ( fabric_clk ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_2 ( prog_clk , Test_en , - clk , fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , - fle_regout , fle_sc_out , ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , - p_abuf3 , p2 ) ; -input [0:0] prog_clk ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:3] fle_in ; -input [0:0] fle_regin ; -input [0:0] fle_sc_in ; -input [0:0] fle_clk ; -input [0:0] ccff_head ; -output [0:1] fle_out ; -output [0:0] fle_regout ; -output [0:0] fle_sc_out ; -output [0:0] ccff_tail ; -output p_abuf0 ; -output p_abuf1 ; -output p_abuf2 ; -output p_abuf3 ; -input p2 ; - -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( - .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , - .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , - .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , - .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , - .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , - .p_abuf2 ( p_abuf2 ) , .p_abuf3 ( p_abuf3 ) , .p2 ( p2 ) ) ; -grid_clb_direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( { p_abuf1 } ) ) ; -grid_clb_direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( { p_abuf3 } ) ) ; -grid_clb_direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fle_regout ) ) ; -grid_clb_direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fle_sc_out ) ) ; -grid_clb_direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( fle_in[0] ) ) ; -grid_clb_direct_interc direct_interc_5_ ( - .in ( { SYNOPSYS_UNCONNECTED_6 } ) , - .out ( fle_in[1] ) ) ; -grid_clb_direct_interc direct_interc_6_ ( - .in ( { SYNOPSYS_UNCONNECTED_7 } ) , - .out ( fle_in[2] ) ) ; -grid_clb_direct_interc direct_interc_7_ ( - .in ( { SYNOPSYS_UNCONNECTED_8 } ) , - .out ( fle_in[3] ) ) ; -grid_clb_direct_interc direct_interc_8_ ( - .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( fle_regin ) ) ; -grid_clb_direct_interc direct_interc_9_ ( - .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( fle_sc_in ) ) ; -grid_clb_direct_interc direct_interc_10_ ( - .in ( { SYNOPSYS_UNCONNECTED_11 } ) , - .out ( fle_clk ) ) ; -endmodule - - -module grid_clb_direct_interc_0 ( in , out ) ; -input [0:0] in ; -output [0:0] out ; -endmodule - - -module grid_clb_mux_tree_size2_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__27 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__26 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__25 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module grid_clb_const1_7 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module grid_clb_mux_tree_size2_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -grid_clb_const1_7 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module grid_clb_const1_6 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module grid_clb_mux_tree_size2_4 ( in , sram , sram_inv , out , p_abuf0 , p1 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -output p_abuf0 ; -input p1 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -grid_clb_const1_6 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p1 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_69 ( .A ( out[0] ) , .X ( p_abuf0 ) ) ; -endmodule - - -module grid_clb_const1_5 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module grid_clb_mux_tree_size2_3 ( in , sram , sram_inv , out , p_abuf0 , - p_abuf1 , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -output p_abuf0 ; -output p_abuf1 ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -grid_clb_const1_5 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf1 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_66 ( .A ( p_abuf1 ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_67 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_3 ( - Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:0] ff_D ; -input [0:0] ff_DI ; -output [0:0] ff_Q ; -input [0:0] ff_clk ; - -sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , - .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_2 ( - Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:0] ff_D ; -input [0:0] ff_DI ; -output [0:0] ff_Q ; -input [0:0] ff_clk ; - -sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , - .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_mem_25 ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__24 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module grid_clb_const1_4 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module grid_clb_mux_tree_size2_25 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -grid_clb_const1_4 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_1 ( prog_clk , - ccff_head , ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:16] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_5_ ( .D ( mem_out[4] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_6_ ( .D ( mem_out[5] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_7_ ( .D ( mem_out[6] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_8_ ( .D ( mem_out[7] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_9_ ( .D ( mem_out[8] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_10_ ( .D ( mem_out[9] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_11_ ( .D ( mem_out[10] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_12_ ( .D ( mem_out[11] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_13_ ( .D ( mem_out[12] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_14_ ( .D ( mem_out[13] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_15_ ( .D ( mem_out[14] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_16_ ( .D ( mem_out[15] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__23 ( .A ( mem_out[16] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module grid_clb_frac_lut4_mux_1 ( in , sram , sram_inv , lut3_out , lut4_out ) ; -input [0:15] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:1] lut3_out ; -output [0:0] lut4_out ; - -wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_4_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_5_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( - .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( - .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( - .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( - .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_5_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_6_ ( - .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__buf_2_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__buf_2_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__buf_2_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ; -endmodule - - -module grid_clb_frac_lut4_1 ( in , sram , sram_inv , mode , mode_inv , - lut3_out , lut4_out ) ; -input [0:3] in ; -input [0:15] sram ; -input [0:15] sram_inv ; -input [0:0] mode ; -input [0:0] mode_inv ; -output [0:1] lut3_out ; -output [0:0] lut4_out ; - -wire [0:0] sky130_fd_sc_hd__buf_2_0_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_1_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_2_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; -wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ; -wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ; -wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ; -wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ; -wire [0:0] sky130_fd_sc_hd__or2_1_0_X ; - -sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , - .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , - .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , - .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , - .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( - .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , - .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , - .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , - .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , - .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( - .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; -grid_clb_frac_lut4_mux_1 frac_lut4_mux_0_ ( .in ( sram ) , - .sram ( { sky130_fd_sc_hd__buf_2_0_X[0] , sky130_fd_sc_hd__buf_2_1_X[0] , - sky130_fd_sc_hd__buf_2_2_X[0] , sky130_fd_sc_hd__buf_2_3_X[0] } ) , - .sram_inv ( { sky130_fd_sc_hd__inv_1_0_Y[0] , - sky130_fd_sc_hd__inv_1_1_Y[0] , sky130_fd_sc_hd__inv_1_2_Y[0] , - sky130_fd_sc_hd__inv_1_3_Y[0] } ) , - .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_1 ( - prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out , - frac_lut4_lut4_out , ccff_tail ) ; -input [0:0] prog_clk ; -input [0:3] frac_lut4_in ; -input [0:0] ccff_head ; -output [0:1] frac_lut4_lut3_out ; -output [0:0] frac_lut4_lut4_out ; -output [0:0] ccff_tail ; - -wire [0:15] frac_lut4_0__undriven_sram_inv ; -wire [0:0] frac_lut4_0_mode ; -wire [0:15] frac_lut4_0_sram ; - -grid_clb_frac_lut4_1 frac_lut4_0_ ( .in ( frac_lut4_in ) , - .sram ( frac_lut4_0_sram ) , - .sram_inv ( frac_lut4_0__undriven_sram_inv ) , - .mode ( frac_lut4_0_mode ) , - .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , - .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) ) ; -grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_1 frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , - .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , - frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] , - frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , - frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , - frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , - frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_1 ( - prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p0 ) ; -input [0:0] prog_clk ; -input [0:3] frac_logic_in ; -input [0:0] ccff_head ; -output [0:1] frac_logic_out ; -output [0:0] ccff_tail ; -input p0 ; - -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; -wire [0:1] mux_frac_logic_out_0_undriven_sram_inv ; -wire [0:1] mux_tree_size2_0_sram ; - -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( - .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , - .ccff_head ( ccff_head ) , - .frac_lut4_lut3_out ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] , - frac_logic_out[1] } ) , - - .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , - .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ; -grid_clb_mux_tree_size2_25 mux_frac_logic_out_0 ( - .in ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] - } ) , - .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_frac_logic_out_0_undriven_sram_inv ) , - .out ( frac_logic_out[0] ) , .p0 ( p0 ) ) ; -grid_clb_mux_tree_size2_mem_25 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) ) ; -grid_clb_direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( frac_logic_out[1] ) ) ; -grid_clb_direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( frac_logic_in[0] ) ) ; -grid_clb_direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( frac_logic_in[1] ) ) ; -grid_clb_direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( frac_logic_in[2] ) ) ; -grid_clb_direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( frac_logic_in[3] ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_1 ( - prog_clk , Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , - fabric_clk , ccff_head , fabric_out , fabric_regout , fabric_sc_out , - ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p0 , p1 ) ; -input [0:0] prog_clk ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:3] fabric_in ; -input [0:0] fabric_regin ; -input [0:0] fabric_sc_in ; -input [0:0] fabric_clk ; -input [0:0] ccff_head ; -output [0:1] fabric_out ; -output [0:0] fabric_regout ; -output [0:0] fabric_sc_out ; -output [0:0] ccff_tail ; -output p_abuf0 ; -output p_abuf1 ; -output p_abuf2 ; -input p0 ; -input p1 ; - -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; -wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; -wire [0:1] mux_fabric_out_0_undriven_sram_inv ; -wire [0:1] mux_fabric_out_1_undriven_sram_inv ; -wire [0:1] mux_ff_0_D_0_undriven_sram_inv ; -wire [0:1] mux_tree_size2_0_sram ; -wire [0:1] mux_tree_size2_1_sram ; -wire [0:0] mux_tree_size2_2_out ; -wire [0:1] mux_tree_size2_2_sram ; -wire [0:0] mux_tree_size2_mem_0_ccff_tail ; -wire [0:0] mux_tree_size2_mem_1_ccff_tail ; - -assign fabric_regout[0] = fabric_sc_out[0] ; - -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( - .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , - .ccff_head ( ccff_head ) , - .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , - .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .p0 ( p0 ) ) ; -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( - .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , - .ff_DI ( fabric_sc_in ) , - .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , - .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( - .Test_en ( Test_en ) , .clk ( clk ) , - .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , - .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , - .ff_Q ( fabric_sc_out ) , - .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; -grid_clb_mux_tree_size2_3 mux_fabric_out_0 ( - .in ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] - } ) , - .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_fabric_out_0_undriven_sram_inv ) , - .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , - .p0 ( p0 ) ) ; -grid_clb_mux_tree_size2_4 mux_fabric_out_1 ( - .in ( { fabric_sc_out[0] , - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] - } ) , - .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( mux_fabric_out_1_undriven_sram_inv ) , - .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf2 ) , .p1 ( p1 ) ) ; -grid_clb_mux_tree_size2_5 mux_ff_0_D_0 ( - .in ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , - fabric_regin[0] } ) , - .sram ( mux_tree_size2_2_sram ) , - .sram_inv ( mux_ff_0_D_0_undriven_sram_inv ) , - .out ( mux_tree_size2_2_out ) , .p0 ( p0 ) ) ; -grid_clb_mux_tree_size2_mem_3 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_size2_0_sram ) ) ; -grid_clb_mux_tree_size2_mem_4 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_size2_1_sram ) ) ; -grid_clb_mux_tree_size2_mem_5 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , - .mem_out ( mux_tree_size2_2_sram ) ) ; -grid_clb_direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fabric_sc_out ) ) ; -grid_clb_direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fabric_sc_out ) ) ; -grid_clb_direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( fabric_in[0] ) ) ; -grid_clb_direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_6 } ) , - .out ( fabric_in[1] ) ) ; -grid_clb_direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_7 } ) , - .out ( fabric_in[2] ) ) ; -grid_clb_direct_interc direct_interc_5_ ( - .in ( { SYNOPSYS_UNCONNECTED_8 } ) , - .out ( fabric_in[3] ) ) ; -grid_clb_direct_interc direct_interc_6_ ( - .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( fabric_sc_in ) ) ; -grid_clb_direct_interc direct_interc_7_ ( - .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( fabric_clk ) ) ; -grid_clb_direct_interc direct_interc_8_ ( - .in ( { SYNOPSYS_UNCONNECTED_11 } ) , - - .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) ) ; -grid_clb_direct_interc direct_interc_9_ ( - .in ( { SYNOPSYS_UNCONNECTED_12 } ) , - - .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ) ; -grid_clb_direct_interc direct_interc_10_ ( - .in ( { SYNOPSYS_UNCONNECTED_13 } ) , - .out ( fabric_clk ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_1 ( prog_clk , Test_en , - clk , fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , - fle_regout , fle_sc_out , ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p0 , - p1 ) ; -input [0:0] prog_clk ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:3] fle_in ; -input [0:0] fle_regin ; -input [0:0] fle_sc_in ; -input [0:0] fle_clk ; -input [0:0] ccff_head ; -output [0:1] fle_out ; -output [0:0] fle_regout ; -output [0:0] fle_sc_out ; -output [0:0] ccff_tail ; -output p_abuf0 ; -output p_abuf1 ; -output p_abuf2 ; -input p0 ; -input p1 ; - -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( - .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , - .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , - .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , - .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , - .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , - .p_abuf2 ( p_abuf2 ) , .p0 ( p0 ) , .p1 ( p1 ) ) ; -grid_clb_direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( { p_abuf1 } ) ) ; -grid_clb_direct_interc_0 direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( { SYNOPSYS_UNCONNECTED_3 } ) ) ; -grid_clb_direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fle_regout ) ) ; -grid_clb_direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( fle_sc_out ) ) ; -grid_clb_direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_6 } ) , - .out ( fle_in[0] ) ) ; -grid_clb_direct_interc direct_interc_5_ ( - .in ( { SYNOPSYS_UNCONNECTED_7 } ) , - .out ( fle_in[1] ) ) ; -grid_clb_direct_interc direct_interc_6_ ( - .in ( { SYNOPSYS_UNCONNECTED_8 } ) , - .out ( fle_in[2] ) ) ; -grid_clb_direct_interc direct_interc_7_ ( - .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( fle_in[3] ) ) ; -grid_clb_direct_interc direct_interc_8_ ( - .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( fle_regin ) ) ; -grid_clb_direct_interc direct_interc_9_ ( - .in ( { SYNOPSYS_UNCONNECTED_11 } ) , - .out ( fle_sc_in ) ) ; -grid_clb_direct_interc direct_interc_10_ ( - .in ( { SYNOPSYS_UNCONNECTED_12 } ) , - .out ( fle_clk ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__22 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__21 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__20 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module grid_clb_const1_3 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module grid_clb_mux_tree_size2_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -grid_clb_const1_3 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module grid_clb_const1_2 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module grid_clb_mux_tree_size2_1 ( in , sram , sram_inv , out , p_abuf0 , - p_abuf1 , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -output p_abuf0 ; -output p_abuf1 ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -grid_clb_const1_2 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf1 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_64 ( .A ( p_abuf1 ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_65 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; -endmodule - - -module grid_clb_const1_1 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module grid_clb_mux_tree_size2_0 ( in , sram , sram_inv , out , p_abuf0 , - p_abuf1 , p1 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -output p_abuf0 ; -output p_abuf1 ; -input p1 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -grid_clb_const1_1 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf1 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_62 ( .A ( p_abuf1 ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_63 ( .A ( p_abuf1 ) , - .X ( BUF_net_63 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_131 ( .A ( BUF_net_63 ) , - .X ( p_abuf0 ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( - Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:0] ff_D ; -input [0:0] ff_DI ; -output [0:0] ff_Q ; -input [0:0] ff_clk ; - -sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , - .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( - Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:0] ff_D ; -input [0:0] ff_DI ; -output [0:0] ff_Q ; -input [0:0] ff_clk ; - -sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , - .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) ) ; -endmodule - - -module grid_clb_direct_interc ( in , out ) ; -input [0:0] in ; -output [0:0] out ; - -assign out[0] = in[0] ; -endmodule - - -module grid_clb_mux_tree_size2_mem_24 ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__19 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module grid_clb_const1_0 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module grid_clb_mux_tree_size2_24 ( in , sram , sram_inv , out , p1 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p1 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -grid_clb_const1_0 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_0 ( prog_clk , - ccff_head , ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:16] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_5_ ( .D ( mem_out[4] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_6_ ( .D ( mem_out[5] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_7_ ( .D ( mem_out[6] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_8_ ( .D ( mem_out[7] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_9_ ( .D ( mem_out[8] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_10_ ( .D ( mem_out[9] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_11_ ( .D ( mem_out[10] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_12_ ( .D ( mem_out[11] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_13_ ( .D ( mem_out[12] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_14_ ( .D ( mem_out[13] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_15_ ( .D ( mem_out[14] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_16_ ( .D ( mem_out[15] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__18 ( .A ( mem_out[16] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module grid_clb_frac_lut4_mux_0 ( in , sram , sram_inv , lut3_out , lut4_out ) ; -input [0:15] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:1] lut3_out ; -output [0:0] lut4_out ; - -wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_4_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_5_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( - .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( - .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( - .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( - .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_5_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_6_ ( - .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__buf_2_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__buf_2_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__buf_2_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ; -endmodule - - -module grid_clb_frac_lut4_0 ( in , sram , sram_inv , mode , mode_inv , - lut3_out , lut4_out ) ; -input [0:3] in ; -input [0:15] sram ; -input [0:15] sram_inv ; -input [0:0] mode ; -input [0:0] mode_inv ; -output [0:1] lut3_out ; -output [0:0] lut4_out ; - -wire [0:0] sky130_fd_sc_hd__buf_2_0_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_1_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_2_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; -wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ; -wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ; -wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ; -wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ; -wire [0:0] sky130_fd_sc_hd__or2_1_0_X ; - -sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , - .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , - .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , - .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , - .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( - .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , - .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , - .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , - .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , - .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( - .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; -grid_clb_frac_lut4_mux_0 frac_lut4_mux_0_ ( .in ( sram ) , - .sram ( { sky130_fd_sc_hd__buf_2_0_X[0] , sky130_fd_sc_hd__buf_2_1_X[0] , - sky130_fd_sc_hd__buf_2_2_X[0] , sky130_fd_sc_hd__buf_2_3_X[0] } ) , - .sram_inv ( { sky130_fd_sc_hd__inv_1_0_Y[0] , - sky130_fd_sc_hd__inv_1_1_Y[0] , sky130_fd_sc_hd__inv_1_2_Y[0] , - sky130_fd_sc_hd__inv_1_3_Y[0] } ) , - .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( - prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out , - frac_lut4_lut4_out , ccff_tail ) ; -input [0:0] prog_clk ; -input [0:3] frac_lut4_in ; -input [0:0] ccff_head ; -output [0:1] frac_lut4_lut3_out ; -output [0:0] frac_lut4_lut4_out ; -output [0:0] ccff_tail ; - -wire [0:15] frac_lut4_0__undriven_sram_inv ; -wire [0:0] frac_lut4_0_mode ; -wire [0:15] frac_lut4_0_sram ; - -grid_clb_frac_lut4_0 frac_lut4_0_ ( .in ( frac_lut4_in ) , - .sram ( frac_lut4_0_sram ) , - .sram_inv ( frac_lut4_0__undriven_sram_inv ) , - .mode ( frac_lut4_0_mode ) , - .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , - .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) ) ; -grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_0 frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , - .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , - frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] , - frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , - frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , - frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , - frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( - prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p1 ) ; -input [0:0] prog_clk ; -input [0:3] frac_logic_in ; -input [0:0] ccff_head ; -output [0:1] frac_logic_out ; -output [0:0] ccff_tail ; -input p1 ; - -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; -wire [0:1] mux_frac_logic_out_0_undriven_sram_inv ; -wire [0:1] mux_tree_size2_0_sram ; - -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( - .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , - .ccff_head ( ccff_head ) , - .frac_lut4_lut3_out ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] , - frac_logic_out[1] } ) , - - .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , - .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ; -grid_clb_mux_tree_size2_24 mux_frac_logic_out_0 ( - .in ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] - } ) , - .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_frac_logic_out_0_undriven_sram_inv ) , - .out ( frac_logic_out[0] ) , .p1 ( p1 ) ) ; -grid_clb_mux_tree_size2_mem_24 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) ) ; -grid_clb_direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( frac_logic_out[1] ) ) ; -grid_clb_direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( frac_logic_in[0] ) ) ; -grid_clb_direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( frac_logic_in[1] ) ) ; -grid_clb_direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( frac_logic_in[2] ) ) ; -grid_clb_direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( frac_logic_in[3] ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( - prog_clk , Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , - fabric_clk , ccff_head , fabric_out , fabric_regout , fabric_sc_out , - ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p_abuf3 , p0 , p1 ) ; -input [0:0] prog_clk ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:3] fabric_in ; -input [0:0] fabric_regin ; -input [0:0] fabric_sc_in ; -input [0:0] fabric_clk ; -input [0:0] ccff_head ; -output [0:1] fabric_out ; -output [0:0] fabric_regout ; -output [0:0] fabric_sc_out ; -output [0:0] ccff_tail ; -output p_abuf0 ; -output p_abuf1 ; -output p_abuf2 ; -output p_abuf3 ; -input p0 ; -input p1 ; - -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; -wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; -wire [0:1] mux_fabric_out_0_undriven_sram_inv ; -wire [0:1] mux_fabric_out_1_undriven_sram_inv ; -wire [0:1] mux_ff_0_D_0_undriven_sram_inv ; -wire [0:1] mux_tree_size2_0_sram ; -wire [0:1] mux_tree_size2_1_sram ; -wire [0:0] mux_tree_size2_2_out ; -wire [0:1] mux_tree_size2_2_sram ; -wire [0:0] mux_tree_size2_mem_0_ccff_tail ; -wire [0:0] mux_tree_size2_mem_1_ccff_tail ; - -assign fabric_regout[0] = fabric_sc_out[0] ; - -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( - .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , - .ccff_head ( ccff_head ) , - .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , - .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .p1 ( p1 ) ) ; -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( - .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , - .ff_DI ( fabric_sc_in ) , - .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , - .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( - .Test_en ( Test_en ) , .clk ( clk ) , - .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , - .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , - .ff_Q ( fabric_sc_out ) , - .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; -grid_clb_mux_tree_size2_0 mux_fabric_out_0 ( - .in ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] - } ) , - .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_fabric_out_0_undriven_sram_inv ) , - .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , - .p1 ( p1 ) ) ; -grid_clb_mux_tree_size2_1 mux_fabric_out_1 ( - .in ( { fabric_sc_out[0] , - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] - } ) , - .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( mux_fabric_out_1_undriven_sram_inv ) , - .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf2 ) , .p_abuf1 ( p_abuf3 ) , - .p0 ( p0 ) ) ; -grid_clb_mux_tree_size2_2 mux_ff_0_D_0 ( - .in ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , - fabric_regin[0] } ) , - .sram ( mux_tree_size2_2_sram ) , - .sram_inv ( mux_ff_0_D_0_undriven_sram_inv ) , - .out ( mux_tree_size2_2_out ) , .p0 ( p0 ) ) ; -grid_clb_mux_tree_size2_mem_0 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_size2_0_sram ) ) ; -grid_clb_mux_tree_size2_mem_1 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_size2_1_sram ) ) ; -grid_clb_mux_tree_size2_mem_2 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , - .mem_out ( mux_tree_size2_2_sram ) ) ; -grid_clb_direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fabric_sc_out ) ) ; -grid_clb_direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fabric_sc_out ) ) ; -grid_clb_direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( fabric_in[0] ) ) ; -grid_clb_direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_6 } ) , - .out ( fabric_in[1] ) ) ; -grid_clb_direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_7 } ) , - .out ( fabric_in[2] ) ) ; -grid_clb_direct_interc direct_interc_5_ ( - .in ( { SYNOPSYS_UNCONNECTED_8 } ) , - .out ( fabric_in[3] ) ) ; -grid_clb_direct_interc direct_interc_6_ ( - .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( fabric_sc_in ) ) ; -grid_clb_direct_interc direct_interc_7_ ( - .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( fabric_clk ) ) ; -grid_clb_direct_interc direct_interc_8_ ( - .in ( { SYNOPSYS_UNCONNECTED_11 } ) , - - .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) ) ; -grid_clb_direct_interc direct_interc_9_ ( - .in ( { SYNOPSYS_UNCONNECTED_12 } ) , - - .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ) ; -grid_clb_direct_interc direct_interc_10_ ( - .in ( { SYNOPSYS_UNCONNECTED_13 } ) , - .out ( fabric_clk ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_0 ( prog_clk , Test_en , - clk , fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , - fle_regout , fle_sc_out , ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , - p_abuf3 , p0 , p1 ) ; -input [0:0] prog_clk ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:3] fle_in ; -input [0:0] fle_regin ; -input [0:0] fle_sc_in ; -input [0:0] fle_clk ; -input [0:0] ccff_head ; -output [0:1] fle_out ; -output [0:0] fle_regout ; -output [0:0] fle_sc_out ; -output [0:0] ccff_tail ; -output p_abuf0 ; -output p_abuf1 ; -output p_abuf2 ; -output p_abuf3 ; -input p0 ; -input p1 ; - -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( - .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , - .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , - .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , - .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , - .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , - .p_abuf2 ( p_abuf2 ) , .p_abuf3 ( p_abuf3 ) , .p0 ( p0 ) , .p1 ( p1 ) ) ; -grid_clb_direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( { p_abuf1 } ) ) ; -grid_clb_direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( { p_abuf3 } ) ) ; -grid_clb_direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fle_regout ) ) ; -grid_clb_direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fle_sc_out ) ) ; -grid_clb_direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( fle_in[0] ) ) ; -grid_clb_direct_interc direct_interc_5_ ( - .in ( { SYNOPSYS_UNCONNECTED_6 } ) , - .out ( fle_in[1] ) ) ; -grid_clb_direct_interc direct_interc_6_ ( - .in ( { SYNOPSYS_UNCONNECTED_7 } ) , - .out ( fle_in[2] ) ) ; -grid_clb_direct_interc direct_interc_7_ ( - .in ( { SYNOPSYS_UNCONNECTED_8 } ) , - .out ( fle_in[3] ) ) ; -grid_clb_direct_interc direct_interc_8_ ( - .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( fle_regin ) ) ; -grid_clb_direct_interc direct_interc_9_ ( - .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( fle_sc_in ) ) ; -grid_clb_direct_interc direct_interc_10_ ( - .in ( { SYNOPSYS_UNCONNECTED_11 } ) , - .out ( fle_clk ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_clb_ ( prog_clk , Test_en , clk , - clb_I0 , clb_I0i , clb_I1 , clb_I1i , clb_I2 , clb_I2i , clb_I3 , - clb_I3i , clb_I4 , clb_I4i , clb_I5 , clb_I5i , clb_I6 , clb_I6i , - clb_I7 , clb_I7i , clb_regin , clb_sc_in , clb_clk , ccff_head , clb_O , - clb_regout , clb_sc_out , ccff_tail , p_abuf0 , p_abuf3 , p_abuf5 , - p_abuf7 , p_abuf9 , p_abuf11 , p_abuf13 , p_abuf15 , p_abuf17 , p_abuf19 , - p_abuf21 , p_abuf23 , p_abuf25 , p_abuf27 , p_abuf29 , p_abuf31 , - p_abuf33 , p0 , p1 , p2 , p3 , p4 ) ; -input [0:0] prog_clk ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:2] clb_I0 ; -input [0:0] clb_I0i ; -input [0:2] clb_I1 ; -input [0:0] clb_I1i ; -input [0:2] clb_I2 ; -input [0:0] clb_I2i ; -input [0:2] clb_I3 ; -input [0:0] clb_I3i ; -input [0:2] clb_I4 ; -input [0:0] clb_I4i ; -input [0:2] clb_I5 ; -input [0:0] clb_I5i ; -input [0:2] clb_I6 ; -input [0:0] clb_I6i ; -input [0:2] clb_I7 ; -input [0:0] clb_I7i ; -input [0:0] clb_regin ; -input [0:0] clb_sc_in ; -input [0:0] clb_clk ; -input [0:0] ccff_head ; -output [0:15] clb_O ; -output [0:0] clb_regout ; -output [0:0] clb_sc_out ; -output [0:0] ccff_tail ; -output p_abuf0 ; -output p_abuf3 ; -output p_abuf5 ; -output p_abuf7 ; -output p_abuf9 ; -output p_abuf11 ; -output p_abuf13 ; -output p_abuf15 ; -output p_abuf17 ; -output p_abuf19 ; -output p_abuf21 ; -output p_abuf23 ; -output p_abuf25 ; -output p_abuf27 ; -output p_abuf29 ; -output p_abuf31 ; -output p_abuf33 ; -input p0 ; -input p1 ; -input p2 ; -input p3 ; -input p4 ; - -wire [0:0] logical_tile_clb_mode_default__fle_0_ccff_tail ; -wire [0:0] logical_tile_clb_mode_default__fle_0_fle_regout ; -wire [0:0] logical_tile_clb_mode_default__fle_0_fle_sc_out ; -wire [0:0] logical_tile_clb_mode_default__fle_1_ccff_tail ; -wire [0:0] logical_tile_clb_mode_default__fle_1_fle_regout ; -wire [0:0] logical_tile_clb_mode_default__fle_1_fle_sc_out ; -wire [0:0] logical_tile_clb_mode_default__fle_2_ccff_tail ; -wire [0:0] logical_tile_clb_mode_default__fle_2_fle_regout ; -wire [0:0] logical_tile_clb_mode_default__fle_2_fle_sc_out ; -wire [0:0] logical_tile_clb_mode_default__fle_3_ccff_tail ; -wire [0:0] logical_tile_clb_mode_default__fle_3_fle_regout ; -wire [0:0] logical_tile_clb_mode_default__fle_3_fle_sc_out ; -wire [0:0] logical_tile_clb_mode_default__fle_4_ccff_tail ; -wire [0:0] logical_tile_clb_mode_default__fle_4_fle_regout ; -wire [0:0] logical_tile_clb_mode_default__fle_4_fle_sc_out ; -wire [0:0] logical_tile_clb_mode_default__fle_5_ccff_tail ; -wire [0:0] logical_tile_clb_mode_default__fle_5_fle_regout ; -wire [0:0] logical_tile_clb_mode_default__fle_5_fle_sc_out ; -wire [0:0] logical_tile_clb_mode_default__fle_6_ccff_tail ; -wire [0:0] logical_tile_clb_mode_default__fle_6_fle_regout ; -wire [0:0] logical_tile_clb_mode_default__fle_6_fle_sc_out ; - -grid_clb_logical_tile_clb_mode_default__fle_0 logical_tile_clb_mode_default__fle_0 ( - .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fle_in ( { clb_I0[0] , clb_I0[1] , clb_I0[2] , clb_I0i[0] } ) , - .fle_regin ( clb_regin ) , .fle_sc_in ( clb_sc_in ) , - .fle_clk ( clb_clk ) , .ccff_head ( ccff_head ) , - .fle_out ( { clb_O[1] , clb_O[0] } ) , - .fle_regout ( logical_tile_clb_mode_default__fle_0_fle_regout ) , - .fle_sc_out ( logical_tile_clb_mode_default__fle_0_fle_sc_out ) , - .ccff_tail ( logical_tile_clb_mode_default__fle_0_ccff_tail ) , - .p_abuf0 ( p_abuf3 ) , .p_abuf1 ( p_abuf4 ) , .p_abuf2 ( p_abuf5 ) , - .p_abuf3 ( p_abuf6 ) , .p0 ( p0 ) , .p1 ( p2 ) ) ; -grid_clb_logical_tile_clb_mode_default__fle_1 logical_tile_clb_mode_default__fle_1 ( - .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fle_in ( { clb_I1[0] , clb_I1[1] , clb_I1[2] , clb_I1i[0] } ) , - .fle_regin ( logical_tile_clb_mode_default__fle_0_fle_regout ) , - .fle_sc_in ( logical_tile_clb_mode_default__fle_0_fle_sc_out ) , - .fle_clk ( clb_clk ) , - .ccff_head ( logical_tile_clb_mode_default__fle_0_ccff_tail ) , - .fle_out ( { clb_O[3] , clb_O[2] } ) , - .fle_regout ( logical_tile_clb_mode_default__fle_1_fle_regout ) , - .fle_sc_out ( logical_tile_clb_mode_default__fle_1_fle_sc_out ) , - .ccff_tail ( logical_tile_clb_mode_default__fle_1_ccff_tail ) , - .p_abuf0 ( p_abuf7 ) , .p_abuf1 ( p_abuf8 ) , .p_abuf2 ( p_abuf9 ) , - .p0 ( p0 ) , .p1 ( p2 ) ) ; -grid_clb_logical_tile_clb_mode_default__fle_2 logical_tile_clb_mode_default__fle_2 ( - .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fle_in ( { clb_I2[0] , clb_I2[1] , clb_I2[2] , clb_I2i[0] } ) , - .fle_regin ( logical_tile_clb_mode_default__fle_1_fle_regout ) , - .fle_sc_in ( logical_tile_clb_mode_default__fle_1_fle_sc_out ) , - .fle_clk ( clb_clk ) , - .ccff_head ( logical_tile_clb_mode_default__fle_1_ccff_tail ) , - .fle_out ( { clb_O[5] , clb_O[4] } ) , - .fle_regout ( logical_tile_clb_mode_default__fle_2_fle_regout ) , - .fle_sc_out ( logical_tile_clb_mode_default__fle_2_fle_sc_out ) , - .ccff_tail ( logical_tile_clb_mode_default__fle_2_ccff_tail ) , - .p_abuf0 ( p_abuf11 ) , .p_abuf1 ( p_abuf12 ) , .p_abuf2 ( p_abuf13 ) , - .p_abuf3 ( p_abuf14 ) , .p2 ( p3 ) ) ; -grid_clb_logical_tile_clb_mode_default__fle_3 logical_tile_clb_mode_default__fle_3 ( - .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fle_in ( { clb_I3[0] , clb_I3[1] , clb_I3[2] , clb_I3i[0] } ) , - .fle_regin ( logical_tile_clb_mode_default__fle_2_fle_regout ) , - .fle_sc_in ( logical_tile_clb_mode_default__fle_2_fle_sc_out ) , - .fle_clk ( clb_clk ) , - .ccff_head ( logical_tile_clb_mode_default__fle_2_ccff_tail ) , - .fle_out ( { clb_O[7] , clb_O[6] } ) , - .fle_regout ( logical_tile_clb_mode_default__fle_3_fle_regout ) , - .fle_sc_out ( logical_tile_clb_mode_default__fle_3_fle_sc_out ) , - .ccff_tail ( logical_tile_clb_mode_default__fle_3_ccff_tail ) , - .p_abuf0 ( p_abuf15 ) , .p_abuf2 ( p_abuf17 ) , .p_abuf3 ( p_abuf18 ) , - .p2 ( p3 ) ) ; -grid_clb_logical_tile_clb_mode_default__fle_4 logical_tile_clb_mode_default__fle_4 ( - .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fle_in ( { clb_I4[0] , clb_I4[1] , clb_I4[2] , clb_I4i[0] } ) , - .fle_regin ( logical_tile_clb_mode_default__fle_3_fle_regout ) , - .fle_sc_in ( logical_tile_clb_mode_default__fle_3_fle_sc_out ) , - .fle_clk ( clb_clk ) , - .ccff_head ( logical_tile_clb_mode_default__fle_3_ccff_tail ) , - .fle_out ( { clb_O[9] , clb_O[8] } ) , - .fle_regout ( logical_tile_clb_mode_default__fle_4_fle_regout ) , - .fle_sc_out ( logical_tile_clb_mode_default__fle_4_fle_sc_out ) , - .ccff_tail ( logical_tile_clb_mode_default__fle_4_ccff_tail ) , - .p_abuf0 ( p_abuf19 ) , .p_abuf2 ( p_abuf21 ) , .p_abuf3 ( p_abuf22 ) , - .p2 ( p3 ) , .p3 ( p4 ) ) ; -grid_clb_logical_tile_clb_mode_default__fle_5 logical_tile_clb_mode_default__fle_5 ( - .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fle_in ( { clb_I5[0] , clb_I5[1] , clb_I5[2] , clb_I5i[0] } ) , - .fle_regin ( logical_tile_clb_mode_default__fle_4_fle_regout ) , - .fle_sc_in ( logical_tile_clb_mode_default__fle_4_fle_sc_out ) , - .fle_clk ( clb_clk ) , - .ccff_head ( logical_tile_clb_mode_default__fle_4_ccff_tail ) , - .fle_out ( { clb_O[11] , clb_O[10] } ) , - .fle_regout ( logical_tile_clb_mode_default__fle_5_fle_regout ) , - .fle_sc_out ( logical_tile_clb_mode_default__fle_5_fle_sc_out ) , - .ccff_tail ( logical_tile_clb_mode_default__fle_5_ccff_tail ) , - .p_abuf0 ( p_abuf23 ) , .p_abuf1 ( p_abuf24 ) , .p_abuf2 ( p_abuf25 ) , - .p3 ( p4 ) ) ; -grid_clb_logical_tile_clb_mode_default__fle_6 logical_tile_clb_mode_default__fle_6 ( - .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fle_in ( { clb_I6[0] , clb_I6[1] , clb_I6[2] , clb_I6i[0] } ) , - .fle_regin ( logical_tile_clb_mode_default__fle_5_fle_regout ) , - .fle_sc_in ( logical_tile_clb_mode_default__fle_5_fle_sc_out ) , - .fle_clk ( clb_clk ) , - .ccff_head ( logical_tile_clb_mode_default__fle_5_ccff_tail ) , - .fle_out ( { clb_O[13] , clb_O[12] } ) , - .fle_regout ( logical_tile_clb_mode_default__fle_6_fle_regout ) , - .fle_sc_out ( logical_tile_clb_mode_default__fle_6_fle_sc_out ) , - .ccff_tail ( logical_tile_clb_mode_default__fle_6_ccff_tail ) , - .p_abuf0 ( p_abuf27 ) , .p_abuf1 ( p_abuf28 ) , .p_abuf2 ( p_abuf29 ) , - .p0 ( p1 ) , .p3 ( p4 ) ) ; -grid_clb_logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_7 ( - .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fle_in ( { clb_I7[0] , clb_I7[1] , clb_I7[2] , clb_I7i[0] } ) , - .fle_regin ( logical_tile_clb_mode_default__fle_6_fle_regout ) , - .fle_sc_in ( logical_tile_clb_mode_default__fle_6_fle_sc_out ) , - .fle_clk ( clb_clk ) , - .ccff_head ( logical_tile_clb_mode_default__fle_6_ccff_tail ) , - .fle_out ( { clb_O[15] , clb_O[14] } ) , - .fle_regout ( clb_regout ) , .fle_sc_out ( clb_sc_out ) , - .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , - .p_abuf2 ( p_abuf2 ) , .p_abuf3 ( p_abuf31 ) , .p_abuf5 ( p_abuf33 ) , - .p_abuf6 ( p_abuf34 ) , .p0 ( p1 ) ) ; -grid_clb_direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( { p_abuf6 } ) ) ; -grid_clb_direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( { p_abuf4 } ) ) ; -grid_clb_direct_interc_6 direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( { SYNOPSYS_UNCONNECTED_4 } ) ) ; -grid_clb_direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( { p_abuf8 } ) ) ; -grid_clb_direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_6 } ) , - .out ( { p_abuf14 } ) ) ; -grid_clb_direct_interc direct_interc_5_ ( - .in ( { SYNOPSYS_UNCONNECTED_7 } ) , - .out ( { p_abuf12 } ) ) ; -grid_clb_direct_interc direct_interc_6_ ( - .in ( { SYNOPSYS_UNCONNECTED_8 } ) , - .out ( { p_abuf18 } ) ) ; -grid_clb_direct_interc_7 direct_interc_7_ ( - .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( { SYNOPSYS_UNCONNECTED_10 } ) ) ; -grid_clb_direct_interc direct_interc_8_ ( - .in ( { SYNOPSYS_UNCONNECTED_11 } ) , - .out ( { p_abuf22 } ) ) ; -grid_clb_direct_interc_8 direct_interc_9_ ( - .in ( { SYNOPSYS_UNCONNECTED_12 } ) , - .out ( { SYNOPSYS_UNCONNECTED_13 } ) ) ; -grid_clb_direct_interc_9 direct_interc_10_ ( - .in ( { SYNOPSYS_UNCONNECTED_14 } ) , - .out ( { SYNOPSYS_UNCONNECTED_15 } ) ) ; -grid_clb_direct_interc direct_interc_11_ ( - .in ( { SYNOPSYS_UNCONNECTED_16 } ) , - .out ( { p_abuf24 } ) ) ; -grid_clb_direct_interc_10 direct_interc_12_ ( - .in ( { SYNOPSYS_UNCONNECTED_17 } ) , - .out ( { SYNOPSYS_UNCONNECTED_18 } ) ) ; -grid_clb_direct_interc direct_interc_13_ ( - .in ( { SYNOPSYS_UNCONNECTED_19 } ) , - .out ( { p_abuf28 } ) ) ; -grid_clb_direct_interc direct_interc_14_ ( - .in ( { SYNOPSYS_UNCONNECTED_20 } ) , - .out ( { p_abuf34 } ) ) ; -grid_clb_direct_interc_11 direct_interc_15_ ( - .in ( { SYNOPSYS_UNCONNECTED_21 } ) , - .out ( { SYNOPSYS_UNCONNECTED_22 } ) ) ; -grid_clb_direct_interc direct_interc_16_ ( - .in ( { SYNOPSYS_UNCONNECTED_23 } ) , - .out ( { p_abuf1 } ) ) ; -grid_clb_direct_interc direct_interc_17_ ( - .in ( { SYNOPSYS_UNCONNECTED_24 } ) , - .out ( { p_abuf2 } ) ) ; -grid_clb_direct_interc direct_interc_18_ ( - .in ( { SYNOPSYS_UNCONNECTED_25 } ) , - .out ( clb_I0[0] ) ) ; -grid_clb_direct_interc direct_interc_19_ ( - .in ( { SYNOPSYS_UNCONNECTED_26 } ) , - .out ( clb_I0[1] ) ) ; -grid_clb_direct_interc direct_interc_20_ ( - .in ( { SYNOPSYS_UNCONNECTED_27 } ) , - .out ( clb_I0[2] ) ) ; -grid_clb_direct_interc direct_interc_21_ ( - .in ( { SYNOPSYS_UNCONNECTED_28 } ) , - .out ( clb_I0i ) ) ; -grid_clb_direct_interc direct_interc_22_ ( - .in ( { SYNOPSYS_UNCONNECTED_29 } ) , - .out ( clb_regin ) ) ; -grid_clb_direct_interc direct_interc_23_ ( - .in ( { SYNOPSYS_UNCONNECTED_30 } ) , - .out ( clb_sc_in ) ) ; -grid_clb_direct_interc direct_interc_24_ ( - .in ( { SYNOPSYS_UNCONNECTED_31 } ) , - .out ( clb_clk ) ) ; -grid_clb_direct_interc direct_interc_25_ ( - .in ( { SYNOPSYS_UNCONNECTED_32 } ) , - .out ( clb_I1[0] ) ) ; -grid_clb_direct_interc direct_interc_26_ ( - .in ( { SYNOPSYS_UNCONNECTED_33 } ) , - .out ( clb_I1[1] ) ) ; -grid_clb_direct_interc direct_interc_27_ ( - .in ( { SYNOPSYS_UNCONNECTED_34 } ) , - .out ( clb_I1[2] ) ) ; -grid_clb_direct_interc direct_interc_28_ ( - .in ( { SYNOPSYS_UNCONNECTED_35 } ) , - .out ( clb_I1i ) ) ; -grid_clb_direct_interc direct_interc_29_ ( - .in ( { SYNOPSYS_UNCONNECTED_36 } ) , - .out ( logical_tile_clb_mode_default__fle_0_fle_regout ) ) ; -grid_clb_direct_interc direct_interc_30_ ( - .in ( { SYNOPSYS_UNCONNECTED_37 } ) , - .out ( logical_tile_clb_mode_default__fle_0_fle_sc_out ) ) ; -grid_clb_direct_interc direct_interc_31_ ( - .in ( { SYNOPSYS_UNCONNECTED_38 } ) , - .out ( clb_clk ) ) ; -grid_clb_direct_interc direct_interc_32_ ( - .in ( { SYNOPSYS_UNCONNECTED_39 } ) , - .out ( clb_I2[0] ) ) ; -grid_clb_direct_interc direct_interc_33_ ( - .in ( { SYNOPSYS_UNCONNECTED_40 } ) , - .out ( clb_I2[1] ) ) ; -grid_clb_direct_interc direct_interc_34_ ( - .in ( { SYNOPSYS_UNCONNECTED_41 } ) , - .out ( clb_I2[2] ) ) ; -grid_clb_direct_interc direct_interc_35_ ( - .in ( { SYNOPSYS_UNCONNECTED_42 } ) , - .out ( clb_I2i ) ) ; -grid_clb_direct_interc direct_interc_36_ ( - .in ( { SYNOPSYS_UNCONNECTED_43 } ) , - .out ( logical_tile_clb_mode_default__fle_1_fle_regout ) ) ; -grid_clb_direct_interc direct_interc_37_ ( - .in ( { SYNOPSYS_UNCONNECTED_44 } ) , - .out ( logical_tile_clb_mode_default__fle_1_fle_sc_out ) ) ; -grid_clb_direct_interc direct_interc_38_ ( - .in ( { SYNOPSYS_UNCONNECTED_45 } ) , - .out ( clb_clk ) ) ; -grid_clb_direct_interc direct_interc_39_ ( - .in ( { SYNOPSYS_UNCONNECTED_46 } ) , - .out ( clb_I3[0] ) ) ; -grid_clb_direct_interc direct_interc_40_ ( - .in ( { SYNOPSYS_UNCONNECTED_47 } ) , - .out ( clb_I3[1] ) ) ; -grid_clb_direct_interc direct_interc_41_ ( - .in ( { SYNOPSYS_UNCONNECTED_48 } ) , - .out ( clb_I3[2] ) ) ; -grid_clb_direct_interc direct_interc_42_ ( - .in ( { SYNOPSYS_UNCONNECTED_49 } ) , - .out ( clb_I3i ) ) ; -grid_clb_direct_interc direct_interc_43_ ( - .in ( { SYNOPSYS_UNCONNECTED_50 } ) , - .out ( logical_tile_clb_mode_default__fle_2_fle_regout ) ) ; -grid_clb_direct_interc direct_interc_44_ ( - .in ( { SYNOPSYS_UNCONNECTED_51 } ) , - .out ( logical_tile_clb_mode_default__fle_2_fle_sc_out ) ) ; -grid_clb_direct_interc direct_interc_45_ ( - .in ( { SYNOPSYS_UNCONNECTED_52 } ) , - .out ( clb_clk ) ) ; -grid_clb_direct_interc direct_interc_46_ ( - .in ( { SYNOPSYS_UNCONNECTED_53 } ) , - .out ( clb_I4[0] ) ) ; -grid_clb_direct_interc direct_interc_47_ ( - .in ( { SYNOPSYS_UNCONNECTED_54 } ) , - .out ( clb_I4[1] ) ) ; -grid_clb_direct_interc direct_interc_48_ ( - .in ( { SYNOPSYS_UNCONNECTED_55 } ) , - .out ( clb_I4[2] ) ) ; -grid_clb_direct_interc direct_interc_49_ ( - .in ( { SYNOPSYS_UNCONNECTED_56 } ) , - .out ( clb_I4i ) ) ; -grid_clb_direct_interc direct_interc_50_ ( - .in ( { SYNOPSYS_UNCONNECTED_57 } ) , - .out ( logical_tile_clb_mode_default__fle_3_fle_regout ) ) ; -grid_clb_direct_interc direct_interc_51_ ( - .in ( { SYNOPSYS_UNCONNECTED_58 } ) , - .out ( logical_tile_clb_mode_default__fle_3_fle_sc_out ) ) ; -grid_clb_direct_interc direct_interc_52_ ( - .in ( { SYNOPSYS_UNCONNECTED_59 } ) , - .out ( clb_clk ) ) ; -grid_clb_direct_interc direct_interc_53_ ( - .in ( { SYNOPSYS_UNCONNECTED_60 } ) , - .out ( clb_I5[0] ) ) ; -grid_clb_direct_interc direct_interc_54_ ( - .in ( { SYNOPSYS_UNCONNECTED_61 } ) , - .out ( clb_I5[1] ) ) ; -grid_clb_direct_interc direct_interc_55_ ( - .in ( { SYNOPSYS_UNCONNECTED_62 } ) , - .out ( clb_I5[2] ) ) ; -grid_clb_direct_interc direct_interc_56_ ( - .in ( { SYNOPSYS_UNCONNECTED_63 } ) , - .out ( clb_I5i ) ) ; -grid_clb_direct_interc direct_interc_57_ ( - .in ( { SYNOPSYS_UNCONNECTED_64 } ) , - .out ( logical_tile_clb_mode_default__fle_4_fle_regout ) ) ; -grid_clb_direct_interc direct_interc_58_ ( - .in ( { SYNOPSYS_UNCONNECTED_65 } ) , - .out ( logical_tile_clb_mode_default__fle_4_fle_sc_out ) ) ; -grid_clb_direct_interc direct_interc_59_ ( - .in ( { SYNOPSYS_UNCONNECTED_66 } ) , - .out ( clb_clk ) ) ; -grid_clb_direct_interc direct_interc_60_ ( - .in ( { SYNOPSYS_UNCONNECTED_67 } ) , - .out ( clb_I6[0] ) ) ; -grid_clb_direct_interc direct_interc_61_ ( - .in ( { SYNOPSYS_UNCONNECTED_68 } ) , - .out ( clb_I6[1] ) ) ; -grid_clb_direct_interc direct_interc_62_ ( - .in ( { SYNOPSYS_UNCONNECTED_69 } ) , - .out ( clb_I6[2] ) ) ; -grid_clb_direct_interc direct_interc_63_ ( - .in ( { SYNOPSYS_UNCONNECTED_70 } ) , - .out ( clb_I6i ) ) ; -grid_clb_direct_interc direct_interc_64_ ( - .in ( { SYNOPSYS_UNCONNECTED_71 } ) , - .out ( logical_tile_clb_mode_default__fle_5_fle_regout ) ) ; -grid_clb_direct_interc direct_interc_65_ ( - .in ( { SYNOPSYS_UNCONNECTED_72 } ) , - .out ( logical_tile_clb_mode_default__fle_5_fle_sc_out ) ) ; -grid_clb_direct_interc direct_interc_66_ ( - .in ( { SYNOPSYS_UNCONNECTED_73 } ) , - .out ( clb_clk ) ) ; -grid_clb_direct_interc direct_interc_67_ ( - .in ( { SYNOPSYS_UNCONNECTED_74 } ) , - .out ( clb_I7[0] ) ) ; -grid_clb_direct_interc direct_interc_68_ ( - .in ( { SYNOPSYS_UNCONNECTED_75 } ) , - .out ( clb_I7[1] ) ) ; -grid_clb_direct_interc direct_interc_69_ ( - .in ( { SYNOPSYS_UNCONNECTED_76 } ) , - .out ( clb_I7[2] ) ) ; -grid_clb_direct_interc direct_interc_70_ ( - .in ( { SYNOPSYS_UNCONNECTED_77 } ) , - .out ( clb_I7i ) ) ; -grid_clb_direct_interc direct_interc_71_ ( - .in ( { SYNOPSYS_UNCONNECTED_78 } ) , - .out ( logical_tile_clb_mode_default__fle_6_fle_regout ) ) ; -grid_clb_direct_interc direct_interc_72_ ( - .in ( { SYNOPSYS_UNCONNECTED_79 } ) , - .out ( logical_tile_clb_mode_default__fle_6_fle_sc_out ) ) ; -grid_clb_direct_interc direct_interc_73_ ( - .in ( { SYNOPSYS_UNCONNECTED_80 } ) , - .out ( clb_clk ) ) ; -endmodule - - -module grid_clb ( prog_clk , Test_en , clk , top_width_0_height_0__pin_0_ , - top_width_0_height_0__pin_1_ , top_width_0_height_0__pin_2_ , - top_width_0_height_0__pin_3_ , top_width_0_height_0__pin_4_ , - top_width_0_height_0__pin_5_ , top_width_0_height_0__pin_6_ , - top_width_0_height_0__pin_7_ , top_width_0_height_0__pin_8_ , - top_width_0_height_0__pin_9_ , top_width_0_height_0__pin_10_ , - top_width_0_height_0__pin_11_ , top_width_0_height_0__pin_12_ , - top_width_0_height_0__pin_13_ , top_width_0_height_0__pin_14_ , - top_width_0_height_0__pin_15_ , top_width_0_height_0__pin_32_ , - top_width_0_height_0__pin_33_ , right_width_0_height_0__pin_16_ , - right_width_0_height_0__pin_17_ , right_width_0_height_0__pin_18_ , - right_width_0_height_0__pin_19_ , right_width_0_height_0__pin_20_ , - right_width_0_height_0__pin_21_ , right_width_0_height_0__pin_22_ , - right_width_0_height_0__pin_23_ , right_width_0_height_0__pin_24_ , - right_width_0_height_0__pin_25_ , right_width_0_height_0__pin_26_ , - right_width_0_height_0__pin_27_ , right_width_0_height_0__pin_28_ , - right_width_0_height_0__pin_29_ , right_width_0_height_0__pin_30_ , - right_width_0_height_0__pin_31_ , left_width_0_height_0__pin_52_ , - ccff_head , top_width_0_height_0__pin_34_upper , - top_width_0_height_0__pin_34_lower , top_width_0_height_0__pin_35_upper , - top_width_0_height_0__pin_35_lower , top_width_0_height_0__pin_36_upper , - top_width_0_height_0__pin_36_lower , top_width_0_height_0__pin_37_upper , - top_width_0_height_0__pin_37_lower , top_width_0_height_0__pin_38_upper , - top_width_0_height_0__pin_38_lower , top_width_0_height_0__pin_39_upper , - top_width_0_height_0__pin_39_lower , top_width_0_height_0__pin_40_upper , - top_width_0_height_0__pin_40_lower , top_width_0_height_0__pin_41_upper , - top_width_0_height_0__pin_41_lower , - right_width_0_height_0__pin_42_upper , - right_width_0_height_0__pin_42_lower , - right_width_0_height_0__pin_43_upper , - right_width_0_height_0__pin_43_lower , - right_width_0_height_0__pin_44_upper , - right_width_0_height_0__pin_44_lower , - right_width_0_height_0__pin_45_upper , - right_width_0_height_0__pin_45_lower , - right_width_0_height_0__pin_46_upper , - right_width_0_height_0__pin_46_lower , - right_width_0_height_0__pin_47_upper , - right_width_0_height_0__pin_47_lower , - right_width_0_height_0__pin_48_upper , - right_width_0_height_0__pin_48_lower , - right_width_0_height_0__pin_49_upper , - right_width_0_height_0__pin_49_lower , bottom_width_0_height_0__pin_50_ , - bottom_width_0_height_0__pin_51_ , ccff_tail , SC_IN_TOP , SC_IN_BOT , - SC_OUT_TOP , SC_OUT_BOT , prog_clk__FEEDTHRU_1 , prog_clk__FEEDTHRU_2 , - prog_clk__FEEDTHRU_3 , prog_clk__FEEDTHRU_4 , Test_en__FEEDTHRU_1 , - clk__FEEDTHRU_1 ) ; -input [0:0] prog_clk ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:0] top_width_0_height_0__pin_0_ ; -input [0:0] top_width_0_height_0__pin_1_ ; -input [0:0] top_width_0_height_0__pin_2_ ; -input [0:0] top_width_0_height_0__pin_3_ ; -input [0:0] top_width_0_height_0__pin_4_ ; -input [0:0] top_width_0_height_0__pin_5_ ; -input [0:0] top_width_0_height_0__pin_6_ ; -input [0:0] top_width_0_height_0__pin_7_ ; -input [0:0] top_width_0_height_0__pin_8_ ; -input [0:0] top_width_0_height_0__pin_9_ ; -input [0:0] top_width_0_height_0__pin_10_ ; -input [0:0] top_width_0_height_0__pin_11_ ; -input [0:0] top_width_0_height_0__pin_12_ ; -input [0:0] top_width_0_height_0__pin_13_ ; -input [0:0] top_width_0_height_0__pin_14_ ; -input [0:0] top_width_0_height_0__pin_15_ ; -input [0:0] top_width_0_height_0__pin_32_ ; -input [0:0] top_width_0_height_0__pin_33_ ; -input [0:0] right_width_0_height_0__pin_16_ ; -input [0:0] right_width_0_height_0__pin_17_ ; -input [0:0] right_width_0_height_0__pin_18_ ; -input [0:0] right_width_0_height_0__pin_19_ ; -input [0:0] right_width_0_height_0__pin_20_ ; -input [0:0] right_width_0_height_0__pin_21_ ; -input [0:0] right_width_0_height_0__pin_22_ ; -input [0:0] right_width_0_height_0__pin_23_ ; -input [0:0] right_width_0_height_0__pin_24_ ; -input [0:0] right_width_0_height_0__pin_25_ ; -input [0:0] right_width_0_height_0__pin_26_ ; -input [0:0] right_width_0_height_0__pin_27_ ; -input [0:0] right_width_0_height_0__pin_28_ ; -input [0:0] right_width_0_height_0__pin_29_ ; -input [0:0] right_width_0_height_0__pin_30_ ; -input [0:0] right_width_0_height_0__pin_31_ ; -input [0:0] left_width_0_height_0__pin_52_ ; -input [0:0] ccff_head ; -output [0:0] top_width_0_height_0__pin_34_upper ; -output [0:0] top_width_0_height_0__pin_34_lower ; -output [0:0] top_width_0_height_0__pin_35_upper ; -output [0:0] top_width_0_height_0__pin_35_lower ; -output [0:0] top_width_0_height_0__pin_36_upper ; -output [0:0] top_width_0_height_0__pin_36_lower ; -output [0:0] top_width_0_height_0__pin_37_upper ; -output [0:0] top_width_0_height_0__pin_37_lower ; -output [0:0] top_width_0_height_0__pin_38_upper ; -output [0:0] top_width_0_height_0__pin_38_lower ; -output [0:0] top_width_0_height_0__pin_39_upper ; -output [0:0] top_width_0_height_0__pin_39_lower ; -output [0:0] top_width_0_height_0__pin_40_upper ; -output [0:0] top_width_0_height_0__pin_40_lower ; -output [0:0] top_width_0_height_0__pin_41_upper ; -output [0:0] top_width_0_height_0__pin_41_lower ; -output [0:0] right_width_0_height_0__pin_42_upper ; -output [0:0] right_width_0_height_0__pin_42_lower ; -output [0:0] right_width_0_height_0__pin_43_upper ; -output [0:0] right_width_0_height_0__pin_43_lower ; -output [0:0] right_width_0_height_0__pin_44_upper ; -output [0:0] right_width_0_height_0__pin_44_lower ; -output [0:0] right_width_0_height_0__pin_45_upper ; -output [0:0] right_width_0_height_0__pin_45_lower ; -output [0:0] right_width_0_height_0__pin_46_upper ; -output [0:0] right_width_0_height_0__pin_46_lower ; -output [0:0] right_width_0_height_0__pin_47_upper ; -output [0:0] right_width_0_height_0__pin_47_lower ; -output [0:0] right_width_0_height_0__pin_48_upper ; -output [0:0] right_width_0_height_0__pin_48_lower ; -output [0:0] right_width_0_height_0__pin_49_upper ; -output [0:0] right_width_0_height_0__pin_49_lower ; -output [0:0] bottom_width_0_height_0__pin_50_ ; -output [0:0] bottom_width_0_height_0__pin_51_ ; -output [0:0] ccff_tail ; -input SC_IN_TOP ; -input SC_IN_BOT ; -output SC_OUT_TOP ; -output SC_OUT_BOT ; -output [0:0] prog_clk__FEEDTHRU_1 ; -output [0:0] prog_clk__FEEDTHRU_2 ; -output [0:0] prog_clk__FEEDTHRU_3 ; -output [0:0] prog_clk__FEEDTHRU_4 ; -output [0:0] Test_en__FEEDTHRU_1 ; -output [0:0] clk__FEEDTHRU_1 ; - -wire ropt_net_156 ; -wire ropt_net_153 ; -wire ropt_net_151 ; -wire ropt_net_150 ; -wire ropt_net_167 ; -wire ropt_net_154 ; -wire ropt_net_168 ; -wire ropt_net_152 ; -wire ropt_net_163 ; -wire ropt_net_162 ; - -assign SC_IN_TOP = SC_IN_BOT ; -assign prog_clk__FEEDTHRU_2[0] = prog_clk__FEEDTHRU_4[0] ; -assign prog_clk__FEEDTHRU_3[0] = prog_clk__FEEDTHRU_4[0] ; - -grid_clb_logical_tile_clb_mode_clb_ logical_tile_clb_mode_clb__0 ( - .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .clb_I0 ( { top_width_0_height_0__pin_0_[0] , - top_width_0_height_0__pin_1_[0] , top_width_0_height_0__pin_2_[0] } ) , - .clb_I0i ( top_width_0_height_0__pin_3_ ) , - .clb_I1 ( { top_width_0_height_0__pin_4_[0] , - top_width_0_height_0__pin_5_[0] , top_width_0_height_0__pin_6_[0] } ) , - .clb_I1i ( top_width_0_height_0__pin_7_ ) , - .clb_I2 ( { top_width_0_height_0__pin_8_[0] , - top_width_0_height_0__pin_9_[0] , top_width_0_height_0__pin_10_[0] } ) , - .clb_I2i ( top_width_0_height_0__pin_11_ ) , - .clb_I3 ( { top_width_0_height_0__pin_12_[0] , - top_width_0_height_0__pin_13_[0] , top_width_0_height_0__pin_14_[0] } ) , - .clb_I3i ( top_width_0_height_0__pin_15_ ) , - .clb_I4 ( { right_width_0_height_0__pin_16_[0] , - right_width_0_height_0__pin_17_[0] , - right_width_0_height_0__pin_18_[0] } ) , - .clb_I4i ( right_width_0_height_0__pin_19_ ) , - .clb_I5 ( { right_width_0_height_0__pin_20_[0] , - right_width_0_height_0__pin_21_[0] , - right_width_0_height_0__pin_22_[0] } ) , - .clb_I5i ( right_width_0_height_0__pin_23_ ) , - .clb_I6 ( { right_width_0_height_0__pin_24_[0] , - right_width_0_height_0__pin_25_[0] , - right_width_0_height_0__pin_26_[0] } ) , - .clb_I6i ( right_width_0_height_0__pin_27_ ) , - .clb_I7 ( { right_width_0_height_0__pin_28_[0] , - right_width_0_height_0__pin_29_[0] , - right_width_0_height_0__pin_30_[0] } ) , - .clb_I7i ( right_width_0_height_0__pin_31_ ) , - .clb_regin ( top_width_0_height_0__pin_32_ ) , - .clb_sc_in ( { SC_IN_BOT } ) , - .clb_clk ( left_width_0_height_0__pin_52_ ) , .ccff_head ( ccff_head ) , - .clb_O ( { aps_rename_138_ , aps_rename_139_ , - top_width_0_height_0__pin_36_lower[0] , aps_rename_142_ , - aps_rename_144_ , aps_rename_145_ , aps_rename_146_ , - top_width_0_height_0__pin_41_lower[0] , aps_rename_148_ , - aps_rename_150_ , aps_rename_151_ , aps_rename_153_ , - aps_rename_154_ , aps_rename_156_ , aps_rename_157_ , - aps_rename_158_ } ) , - .clb_regout ( { ropt_net_161 } ) , - .clb_sc_out ( { aps_rename_160_ } ) , - .ccff_tail ( ccff_tail ) , .p_abuf0 ( ropt_net_162 ) , - .p_abuf3 ( top_width_0_height_0__pin_35_upper[0] ) , - .p_abuf5 ( top_width_0_height_0__pin_34_upper[0] ) , - .p_abuf7 ( ropt_net_156 ) , - .p_abuf9 ( top_width_0_height_0__pin_36_upper[0] ) , - .p_abuf11 ( ropt_net_151 ) , .p_abuf13 ( ropt_net_153 ) , - .p_abuf15 ( top_width_0_height_0__pin_41_upper[0] ) , - .p_abuf17 ( top_width_0_height_0__pin_40_upper[0] ) , - .p_abuf19 ( ropt_net_167 ) , .p_abuf21 ( ropt_net_150 ) , - .p_abuf23 ( ropt_net_168 ) , .p_abuf25 ( ropt_net_154 ) , - .p_abuf27 ( ropt_net_152 ) , - .p_abuf29 ( right_width_0_height_0__pin_46_upper[0] ) , - .p_abuf31 ( right_width_0_height_0__pin_49_upper[0] ) , - .p_abuf33 ( ropt_net_163 ) , .p0 ( optlc_net_137 ) , - .p1 ( optlc_net_138 ) , .p2 ( optlc_net_139 ) , .p3 ( optlc_net_140 ) , - .p4 ( optlc_net_141 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( Test_en[0] ) , - .X ( ropt_net_166 ) ) ; -sky130_fd_sc_hd__buf_2 \clk[0]_bip538 ( .A ( clk[0] ) , - .X ( ctsbuf_net_1142 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_989 ( .A ( ropt_net_167 ) , - .X ( right_width_0_height_0__pin_43_upper[0] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_137 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_137 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__4 ( .A ( aps_rename_142_ ) , - .X ( aps_rename_143_ ) ) ; -sky130_fd_sc_hd__conb_1 optlc_139 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_138 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_141 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_139 ) ) ; -sky130_fd_sc_hd__clkbuf_1 \prog_clk[0]_bip539 ( .A ( prog_clk[0] ) , - .X ( ctsbuf_net_6147 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_143 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_140 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_990 ( .A ( ropt_net_168 ) , - .X ( right_width_0_height_0__pin_45_upper[0] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_145 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , - .HI ( optlc_net_141 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__11 ( .A ( aps_rename_151_ ) , - .X ( aps_rename_152_ ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_955 ( .A ( ropt_net_148 ) , - .X ( top_width_0_height_0__pin_38_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__13 ( .A ( aps_rename_154_ ) , - .X ( aps_rename_155_ ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_364903 ( .A ( ctsbuf_net_1142 ) , - .X ( clk__FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_956 ( .A ( ropt_net_149 ) , - .X ( top_width_0_height_0__pin_39_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__16 ( .A ( aps_rename_158_ ) , - .X ( aps_rename_159_ ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__17 ( .A ( aps_rename_160_ ) , - .X ( ropt_net_157 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_94 ( .A ( aps_rename_138_ ) , - .X ( BUF_net_94 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_95 ( .A ( aps_rename_139_ ) , - .X ( BUF_net_95 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_957 ( .A ( ropt_net_150 ) , - .X ( right_width_0_height_0__pin_42_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_97 ( .A ( aps_rename_143_ ) , - .X ( top_width_0_height_0__pin_37_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_98 ( .A ( aps_rename_144_ ) , - .X ( ropt_net_148 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_99 ( .A ( aps_rename_145_ ) , - .X ( ropt_net_149 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_100 ( .A ( aps_rename_146_ ) , - .X ( BUF_net_100 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_958 ( .A ( ropt_net_151 ) , - .X ( top_width_0_height_0__pin_39_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_959 ( .A ( ropt_net_152 ) , - .X ( right_width_0_height_0__pin_47_upper[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_103 ( .A ( aps_rename_150_ ) , - .X ( BUF_net_103 ) ) ; -sky130_fd_sc_hd__buf_8 cts_buf_389928 ( .A ( prog_clk__FEEDTHRU_4[0] ) , - .X ( prog_clk__FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__buf_12 cts_buf_393932 ( .A ( ctsbuf_net_6147 ) , - .X ( prog_clk__FEEDTHRU_4[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_960 ( .A ( ropt_net_153 ) , - .X ( top_width_0_height_0__pin_38_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_964 ( .A ( ropt_net_154 ) , - .X ( right_width_0_height_0__pin_44_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_994 ( .A ( ropt_net_169 ) , - .X ( right_width_0_height_0__pin_49_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_965 ( .A ( aps_rename_156_ ) , - .X ( right_width_0_height_0__pin_47_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_966 ( .A ( ropt_net_156 ) , - .X ( top_width_0_height_0__pin_37_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_968 ( .A ( ropt_net_157 ) , - .X ( ropt_net_172 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_116 ( .A ( aps_rename_152_ ) , - .X ( right_width_0_height_0__pin_44_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_998 ( .A ( ropt_net_170 ) , - .X ( right_width_0_height_0__pin_48_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_118 ( .A ( aps_rename_155_ ) , - .X ( right_width_0_height_0__pin_46_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_999 ( .A ( ropt_net_171 ) , - .X ( right_width_0_height_0__pin_48_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_120 ( .A ( aps_rename_157_ ) , - .X ( ropt_net_165 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_121 ( .A ( aps_rename_159_ ) , - .X ( ropt_net_164 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_126 ( .A ( BUF_net_94 ) , - .X ( top_width_0_height_0__pin_34_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_127 ( .A ( BUF_net_95 ) , - .X ( top_width_0_height_0__pin_35_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_128 ( .A ( BUF_net_100 ) , - .X ( ropt_net_174 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_969 ( .A ( aps_rename_153_ ) , - .X ( right_width_0_height_0__pin_45_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_132 ( .A ( aps_rename_148_ ) , - .X ( ropt_net_159 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_1004 ( .A ( ropt_net_172 ) , - .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_972 ( .A ( ropt_net_159 ) , - .X ( right_width_0_height_0__pin_42_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_974 ( .A ( BUF_net_103 ) , - .X ( right_width_0_height_0__pin_43_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_978 ( .A ( ropt_net_161 ) , - .X ( ropt_net_173 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_984 ( .A ( ropt_net_162 ) , - .X ( SC_OUT_TOP ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_985 ( .A ( ropt_net_163 ) , - .X ( ropt_net_170 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_986 ( .A ( ropt_net_164 ) , - .X ( ropt_net_169 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_987 ( .A ( ropt_net_165 ) , - .X ( ropt_net_171 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_988 ( .A ( ropt_net_166 ) , - .X ( Test_en__FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_1005 ( .A ( ropt_net_173 ) , - .X ( bottom_width_0_height_0__pin_50_[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_1007 ( .A ( ropt_net_174 ) , - .X ( top_width_0_height_0__pin_40_lower[0] ) ) ; -endmodule - - -module fpga_core ( prog_clk , Test_en , clk , gfpga_pad_EMBEDDED_IO_SOC_IN , - gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , - ccff_head , ccff_tail , sc_head , sc_tail ) ; -input [0:0] prog_clk ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:17] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:17] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:17] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -input sc_head ; -output sc_tail ; - -wire [0:0] cbx_1__0__0_bottom_grid_pin_0_ ; -wire [0:0] cbx_1__0__0_bottom_grid_pin_10_ ; -wire [0:0] cbx_1__0__0_bottom_grid_pin_2_ ; -wire [0:0] cbx_1__0__0_bottom_grid_pin_4_ ; -wire [0:0] cbx_1__0__0_bottom_grid_pin_6_ ; -wire [0:0] cbx_1__0__0_bottom_grid_pin_8_ ; -wire [0:19] cbx_1__0__0_chanx_left_out ; -wire [0:19] cbx_1__0__0_chanx_right_out ; -wire [0:0] cbx_1__0__1_bottom_grid_pin_0_ ; -wire [0:0] cbx_1__0__1_bottom_grid_pin_10_ ; -wire [0:0] cbx_1__0__1_bottom_grid_pin_2_ ; -wire [0:0] cbx_1__0__1_bottom_grid_pin_4_ ; -wire [0:0] cbx_1__0__1_bottom_grid_pin_6_ ; -wire [0:0] cbx_1__0__1_bottom_grid_pin_8_ ; -wire [0:19] cbx_1__0__1_chanx_left_out ; -wire [0:19] cbx_1__0__1_chanx_right_out ; -wire [0:0] cbx_1__1__0_bottom_grid_pin_0_ ; -wire [0:0] cbx_1__1__0_bottom_grid_pin_10_ ; -wire [0:0] cbx_1__1__0_bottom_grid_pin_11_ ; -wire [0:0] cbx_1__1__0_bottom_grid_pin_12_ ; -wire [0:0] cbx_1__1__0_bottom_grid_pin_13_ ; -wire [0:0] cbx_1__1__0_bottom_grid_pin_14_ ; -wire [0:0] cbx_1__1__0_bottom_grid_pin_15_ ; -wire [0:0] cbx_1__1__0_bottom_grid_pin_1_ ; -wire [0:0] cbx_1__1__0_bottom_grid_pin_2_ ; -wire [0:0] cbx_1__1__0_bottom_grid_pin_3_ ; -wire [0:0] cbx_1__1__0_bottom_grid_pin_4_ ; -wire [0:0] cbx_1__1__0_bottom_grid_pin_5_ ; -wire [0:0] cbx_1__1__0_bottom_grid_pin_6_ ; -wire [0:0] cbx_1__1__0_bottom_grid_pin_7_ ; -wire [0:0] cbx_1__1__0_bottom_grid_pin_8_ ; -wire [0:0] cbx_1__1__0_bottom_grid_pin_9_ ; -wire [0:0] cbx_1__1__0_ccff_tail ; -wire [0:19] cbx_1__1__0_chanx_left_out ; -wire [0:19] cbx_1__1__0_chanx_right_out ; -wire [0:0] cbx_1__1__1_bottom_grid_pin_0_ ; -wire [0:0] cbx_1__1__1_bottom_grid_pin_10_ ; -wire [0:0] cbx_1__1__1_bottom_grid_pin_11_ ; -wire [0:0] cbx_1__1__1_bottom_grid_pin_12_ ; -wire [0:0] cbx_1__1__1_bottom_grid_pin_13_ ; -wire [0:0] cbx_1__1__1_bottom_grid_pin_14_ ; -wire [0:0] cbx_1__1__1_bottom_grid_pin_15_ ; -wire [0:0] cbx_1__1__1_bottom_grid_pin_1_ ; -wire [0:0] cbx_1__1__1_bottom_grid_pin_2_ ; -wire [0:0] cbx_1__1__1_bottom_grid_pin_3_ ; -wire [0:0] cbx_1__1__1_bottom_grid_pin_4_ ; -wire [0:0] cbx_1__1__1_bottom_grid_pin_5_ ; -wire [0:0] cbx_1__1__1_bottom_grid_pin_6_ ; -wire [0:0] cbx_1__1__1_bottom_grid_pin_7_ ; -wire [0:0] cbx_1__1__1_bottom_grid_pin_8_ ; -wire [0:0] cbx_1__1__1_bottom_grid_pin_9_ ; -wire [0:0] cbx_1__1__1_ccff_tail ; -wire [0:19] cbx_1__1__1_chanx_left_out ; -wire [0:19] cbx_1__1__1_chanx_right_out ; -wire [0:0] cbx_1__2__0_bottom_grid_pin_0_ ; -wire [0:0] cbx_1__2__0_bottom_grid_pin_10_ ; -wire [0:0] cbx_1__2__0_bottom_grid_pin_11_ ; -wire [0:0] cbx_1__2__0_bottom_grid_pin_12_ ; -wire [0:0] cbx_1__2__0_bottom_grid_pin_13_ ; -wire [0:0] cbx_1__2__0_bottom_grid_pin_14_ ; -wire [0:0] cbx_1__2__0_bottom_grid_pin_15_ ; -wire [0:0] cbx_1__2__0_bottom_grid_pin_1_ ; -wire [0:0] cbx_1__2__0_bottom_grid_pin_2_ ; -wire [0:0] cbx_1__2__0_bottom_grid_pin_3_ ; -wire [0:0] cbx_1__2__0_bottom_grid_pin_4_ ; -wire [0:0] cbx_1__2__0_bottom_grid_pin_5_ ; -wire [0:0] cbx_1__2__0_bottom_grid_pin_6_ ; -wire [0:0] cbx_1__2__0_bottom_grid_pin_7_ ; -wire [0:0] cbx_1__2__0_bottom_grid_pin_8_ ; -wire [0:0] cbx_1__2__0_bottom_grid_pin_9_ ; -wire [0:19] cbx_1__2__0_chanx_left_out ; -wire [0:19] cbx_1__2__0_chanx_right_out ; -wire [0:0] cbx_1__2__0_top_grid_pin_0_ ; -wire [0:0] cbx_1__2__1_bottom_grid_pin_0_ ; -wire [0:0] cbx_1__2__1_bottom_grid_pin_10_ ; -wire [0:0] cbx_1__2__1_bottom_grid_pin_11_ ; -wire [0:0] cbx_1__2__1_bottom_grid_pin_12_ ; -wire [0:0] cbx_1__2__1_bottom_grid_pin_13_ ; -wire [0:0] cbx_1__2__1_bottom_grid_pin_14_ ; -wire [0:0] cbx_1__2__1_bottom_grid_pin_15_ ; -wire [0:0] cbx_1__2__1_bottom_grid_pin_1_ ; -wire [0:0] cbx_1__2__1_bottom_grid_pin_2_ ; -wire [0:0] cbx_1__2__1_bottom_grid_pin_3_ ; -wire [0:0] cbx_1__2__1_bottom_grid_pin_4_ ; -wire [0:0] cbx_1__2__1_bottom_grid_pin_5_ ; -wire [0:0] cbx_1__2__1_bottom_grid_pin_6_ ; -wire [0:0] cbx_1__2__1_bottom_grid_pin_7_ ; -wire [0:0] cbx_1__2__1_bottom_grid_pin_8_ ; -wire [0:0] cbx_1__2__1_bottom_grid_pin_9_ ; -wire [0:19] cbx_1__2__1_chanx_left_out ; -wire [0:19] cbx_1__2__1_chanx_right_out ; -wire [0:0] cbx_1__2__1_top_grid_pin_0_ ; -wire [0:19] cby_0__1__0_chany_bottom_out ; -wire [0:19] cby_0__1__0_chany_top_out ; -wire [0:0] cby_0__1__0_left_grid_pin_0_ ; -wire [0:19] cby_0__1__1_chany_bottom_out ; -wire [0:19] cby_0__1__1_chany_top_out ; -wire [0:0] cby_0__1__1_left_grid_pin_0_ ; -wire [0:0] cby_1__1__0_ccff_tail ; -wire [0:19] cby_1__1__0_chany_bottom_out ; -wire [0:19] cby_1__1__0_chany_top_out ; -wire [0:0] cby_1__1__0_left_grid_pin_16_ ; -wire [0:0] cby_1__1__0_left_grid_pin_17_ ; -wire [0:0] cby_1__1__0_left_grid_pin_18_ ; -wire [0:0] cby_1__1__0_left_grid_pin_19_ ; -wire [0:0] cby_1__1__0_left_grid_pin_20_ ; -wire [0:0] cby_1__1__0_left_grid_pin_21_ ; -wire [0:0] cby_1__1__0_left_grid_pin_22_ ; -wire [0:0] cby_1__1__0_left_grid_pin_23_ ; -wire [0:0] cby_1__1__0_left_grid_pin_24_ ; -wire [0:0] cby_1__1__0_left_grid_pin_25_ ; -wire [0:0] cby_1__1__0_left_grid_pin_26_ ; -wire [0:0] cby_1__1__0_left_grid_pin_27_ ; -wire [0:0] cby_1__1__0_left_grid_pin_28_ ; -wire [0:0] cby_1__1__0_left_grid_pin_29_ ; -wire [0:0] cby_1__1__0_left_grid_pin_30_ ; -wire [0:0] cby_1__1__0_left_grid_pin_31_ ; -wire [0:0] cby_1__1__1_ccff_tail ; -wire [0:19] cby_1__1__1_chany_bottom_out ; -wire [0:19] cby_1__1__1_chany_top_out ; -wire [0:0] cby_1__1__1_left_grid_pin_16_ ; -wire [0:0] cby_1__1__1_left_grid_pin_17_ ; -wire [0:0] cby_1__1__1_left_grid_pin_18_ ; -wire [0:0] cby_1__1__1_left_grid_pin_19_ ; -wire [0:0] cby_1__1__1_left_grid_pin_20_ ; -wire [0:0] cby_1__1__1_left_grid_pin_21_ ; -wire [0:0] cby_1__1__1_left_grid_pin_22_ ; -wire [0:0] cby_1__1__1_left_grid_pin_23_ ; -wire [0:0] cby_1__1__1_left_grid_pin_24_ ; -wire [0:0] cby_1__1__1_left_grid_pin_25_ ; -wire [0:0] cby_1__1__1_left_grid_pin_26_ ; -wire [0:0] cby_1__1__1_left_grid_pin_27_ ; -wire [0:0] cby_1__1__1_left_grid_pin_28_ ; -wire [0:0] cby_1__1__1_left_grid_pin_29_ ; -wire [0:0] cby_1__1__1_left_grid_pin_30_ ; -wire [0:0] cby_1__1__1_left_grid_pin_31_ ; -wire [0:19] cby_2__1__0_chany_bottom_out ; -wire [0:19] cby_2__1__0_chany_top_out ; -wire [0:0] cby_2__1__0_left_grid_pin_16_ ; -wire [0:0] cby_2__1__0_left_grid_pin_17_ ; -wire [0:0] cby_2__1__0_left_grid_pin_18_ ; -wire [0:0] cby_2__1__0_left_grid_pin_19_ ; -wire [0:0] cby_2__1__0_left_grid_pin_20_ ; -wire [0:0] cby_2__1__0_left_grid_pin_21_ ; -wire [0:0] cby_2__1__0_left_grid_pin_22_ ; -wire [0:0] cby_2__1__0_left_grid_pin_23_ ; -wire [0:0] cby_2__1__0_left_grid_pin_24_ ; -wire [0:0] cby_2__1__0_left_grid_pin_25_ ; -wire [0:0] cby_2__1__0_left_grid_pin_26_ ; -wire [0:0] cby_2__1__0_left_grid_pin_27_ ; -wire [0:0] cby_2__1__0_left_grid_pin_28_ ; -wire [0:0] cby_2__1__0_left_grid_pin_29_ ; -wire [0:0] cby_2__1__0_left_grid_pin_30_ ; -wire [0:0] cby_2__1__0_left_grid_pin_31_ ; -wire [0:0] cby_2__1__0_right_grid_pin_0_ ; -wire [0:19] cby_2__1__1_chany_bottom_out ; -wire [0:19] cby_2__1__1_chany_top_out ; -wire [0:0] cby_2__1__1_left_grid_pin_16_ ; -wire [0:0] cby_2__1__1_left_grid_pin_17_ ; -wire [0:0] cby_2__1__1_left_grid_pin_18_ ; -wire [0:0] cby_2__1__1_left_grid_pin_19_ ; -wire [0:0] cby_2__1__1_left_grid_pin_20_ ; -wire [0:0] cby_2__1__1_left_grid_pin_21_ ; -wire [0:0] cby_2__1__1_left_grid_pin_22_ ; -wire [0:0] cby_2__1__1_left_grid_pin_23_ ; -wire [0:0] cby_2__1__1_left_grid_pin_24_ ; -wire [0:0] cby_2__1__1_left_grid_pin_25_ ; -wire [0:0] cby_2__1__1_left_grid_pin_26_ ; -wire [0:0] cby_2__1__1_left_grid_pin_27_ ; -wire [0:0] cby_2__1__1_left_grid_pin_28_ ; -wire [0:0] cby_2__1__1_left_grid_pin_29_ ; -wire [0:0] cby_2__1__1_left_grid_pin_30_ ; -wire [0:0] cby_2__1__1_left_grid_pin_31_ ; -wire [0:0] cby_2__1__1_right_grid_pin_0_ ; -wire [0:0] direct_interc_0_out ; -wire [0:0] direct_interc_1_out ; -wire [0:0] direct_interc_2_out ; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_50_ ; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_51_ ; -wire [0:0] grid_clb_0_ccff_tail ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_42_lower ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_42_upper ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_43_lower ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_43_upper ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_44_lower ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_44_upper ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_45_lower ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_45_upper ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_46_lower ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_46_upper ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_47_lower ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_47_upper ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_48_lower ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_48_upper ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_49_lower ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_49_upper ; -wire [0:0] grid_clb_0_top_width_0_height_0__pin_34_lower ; -wire [0:0] grid_clb_0_top_width_0_height_0__pin_34_upper ; -wire [0:0] grid_clb_0_top_width_0_height_0__pin_35_lower ; -wire [0:0] grid_clb_0_top_width_0_height_0__pin_35_upper ; -wire [0:0] grid_clb_0_top_width_0_height_0__pin_36_lower ; -wire [0:0] grid_clb_0_top_width_0_height_0__pin_36_upper ; -wire [0:0] grid_clb_0_top_width_0_height_0__pin_37_lower ; -wire [0:0] grid_clb_0_top_width_0_height_0__pin_37_upper ; -wire [0:0] grid_clb_0_top_width_0_height_0__pin_38_lower ; -wire [0:0] grid_clb_0_top_width_0_height_0__pin_38_upper ; -wire [0:0] grid_clb_0_top_width_0_height_0__pin_39_lower ; -wire [0:0] grid_clb_0_top_width_0_height_0__pin_39_upper ; -wire [0:0] grid_clb_0_top_width_0_height_0__pin_40_lower ; -wire [0:0] grid_clb_0_top_width_0_height_0__pin_40_upper ; -wire [0:0] grid_clb_0_top_width_0_height_0__pin_41_lower ; -wire [0:0] grid_clb_0_top_width_0_height_0__pin_41_upper ; -wire [0:0] grid_clb_1__1__undriven_left_width_0_height_0__pin_52_ ; -wire [0:0] grid_clb_1__2__undriven_left_width_0_height_0__pin_52_ ; -wire [0:0] grid_clb_1__2__undriven_top_width_0_height_0__pin_32_ ; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_50_ ; -wire [0:0] grid_clb_1_ccff_tail ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_42_lower ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_42_upper ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_43_lower ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_43_upper ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_44_lower ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_44_upper ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_45_lower ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_45_upper ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_46_lower ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_46_upper ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_47_lower ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_47_upper ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_48_lower ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_48_upper ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_49_lower ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_49_upper ; -wire [0:0] grid_clb_1_top_width_0_height_0__pin_34_lower ; -wire [0:0] grid_clb_1_top_width_0_height_0__pin_34_upper ; -wire [0:0] grid_clb_1_top_width_0_height_0__pin_35_lower ; -wire [0:0] grid_clb_1_top_width_0_height_0__pin_35_upper ; -wire [0:0] grid_clb_1_top_width_0_height_0__pin_36_lower ; -wire [0:0] grid_clb_1_top_width_0_height_0__pin_36_upper ; -wire [0:0] grid_clb_1_top_width_0_height_0__pin_37_lower ; -wire [0:0] grid_clb_1_top_width_0_height_0__pin_37_upper ; -wire [0:0] grid_clb_1_top_width_0_height_0__pin_38_lower ; -wire [0:0] grid_clb_1_top_width_0_height_0__pin_38_upper ; -wire [0:0] grid_clb_1_top_width_0_height_0__pin_39_lower ; -wire [0:0] grid_clb_1_top_width_0_height_0__pin_39_upper ; -wire [0:0] grid_clb_1_top_width_0_height_0__pin_40_lower ; -wire [0:0] grid_clb_1_top_width_0_height_0__pin_40_upper ; -wire [0:0] grid_clb_1_top_width_0_height_0__pin_41_lower ; -wire [0:0] grid_clb_1_top_width_0_height_0__pin_41_upper ; -wire [0:0] grid_clb_2__1__undriven_bottom_width_0_height_0__pin_50_ ; -wire [0:0] grid_clb_2__1__undriven_left_width_0_height_0__pin_52_ ; -wire [0:0] grid_clb_2__2__undriven_left_width_0_height_0__pin_52_ ; -wire [0:0] grid_clb_2_ccff_tail ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_42_lower ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_42_upper ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_43_lower ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_43_upper ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_44_lower ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_44_upper ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_45_lower ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_45_upper ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_46_lower ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_46_upper ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_47_lower ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_47_upper ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_48_lower ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_48_upper ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_49_lower ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_49_upper ; -wire [0:0] grid_clb_2_top_width_0_height_0__pin_34_lower ; -wire [0:0] grid_clb_2_top_width_0_height_0__pin_34_upper ; -wire [0:0] grid_clb_2_top_width_0_height_0__pin_35_lower ; -wire [0:0] grid_clb_2_top_width_0_height_0__pin_35_upper ; -wire [0:0] grid_clb_2_top_width_0_height_0__pin_36_lower ; -wire [0:0] grid_clb_2_top_width_0_height_0__pin_36_upper ; -wire [0:0] grid_clb_2_top_width_0_height_0__pin_37_lower ; -wire [0:0] grid_clb_2_top_width_0_height_0__pin_37_upper ; -wire [0:0] grid_clb_2_top_width_0_height_0__pin_38_lower ; -wire [0:0] grid_clb_2_top_width_0_height_0__pin_38_upper ; -wire [0:0] grid_clb_2_top_width_0_height_0__pin_39_lower ; -wire [0:0] grid_clb_2_top_width_0_height_0__pin_39_upper ; -wire [0:0] grid_clb_2_top_width_0_height_0__pin_40_lower ; -wire [0:0] grid_clb_2_top_width_0_height_0__pin_40_upper ; -wire [0:0] grid_clb_2_top_width_0_height_0__pin_41_lower ; -wire [0:0] grid_clb_2_top_width_0_height_0__pin_41_upper ; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_50_ ; -wire [0:0] grid_clb_3_ccff_tail ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_42_lower ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_42_upper ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_43_lower ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_43_upper ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_44_lower ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_44_upper ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_45_lower ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_45_upper ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_46_lower ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_46_upper ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_47_lower ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_47_upper ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_48_lower ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_48_upper ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_49_lower ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_49_upper ; -wire [0:0] grid_clb_3_top_width_0_height_0__pin_34_lower ; -wire [0:0] grid_clb_3_top_width_0_height_0__pin_34_upper ; -wire [0:0] grid_clb_3_top_width_0_height_0__pin_35_lower ; -wire [0:0] grid_clb_3_top_width_0_height_0__pin_35_upper ; -wire [0:0] grid_clb_3_top_width_0_height_0__pin_36_lower ; -wire [0:0] grid_clb_3_top_width_0_height_0__pin_36_upper ; -wire [0:0] grid_clb_3_top_width_0_height_0__pin_37_lower ; -wire [0:0] grid_clb_3_top_width_0_height_0__pin_37_upper ; -wire [0:0] grid_clb_3_top_width_0_height_0__pin_38_lower ; -wire [0:0] grid_clb_3_top_width_0_height_0__pin_38_upper ; -wire [0:0] grid_clb_3_top_width_0_height_0__pin_39_lower ; -wire [0:0] grid_clb_3_top_width_0_height_0__pin_39_upper ; -wire [0:0] grid_clb_3_top_width_0_height_0__pin_40_lower ; -wire [0:0] grid_clb_3_top_width_0_height_0__pin_40_upper ; -wire [0:0] grid_clb_3_top_width_0_height_0__pin_41_lower ; -wire [0:0] grid_clb_3_top_width_0_height_0__pin_41_upper ; -wire [0:0] grid_io_bottom_0_ccff_tail ; -wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_11_lower ; -wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_11_upper ; -wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_1_lower ; -wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_1_upper ; -wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_3_lower ; -wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_3_upper ; -wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_5_lower ; -wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_5_upper ; -wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_7_lower ; -wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_7_upper ; -wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_9_lower ; -wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_9_upper ; -wire [0:0] grid_io_bottom_1_ccff_tail ; -wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_11_lower ; -wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_11_upper ; -wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_1_lower ; -wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_1_upper ; -wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_3_lower ; -wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_3_upper ; -wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_5_lower ; -wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_5_upper ; -wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_7_lower ; -wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_7_upper ; -wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_9_lower ; -wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_9_upper ; -wire [0:0] grid_io_left_0_ccff_tail ; -wire [0:0] grid_io_left_0_right_width_0_height_0__pin_1_lower ; -wire [0:0] grid_io_left_0_right_width_0_height_0__pin_1_upper ; -wire [0:0] grid_io_left_1_ccff_tail ; -wire [0:0] grid_io_left_1_right_width_0_height_0__pin_1_lower ; -wire [0:0] grid_io_left_1_right_width_0_height_0__pin_1_upper ; -wire [0:0] grid_io_right_0_ccff_tail ; -wire [0:0] grid_io_right_0_left_width_0_height_0__pin_1_lower ; -wire [0:0] grid_io_right_0_left_width_0_height_0__pin_1_upper ; -wire [0:0] grid_io_right_1_ccff_tail ; -wire [0:0] grid_io_right_1_left_width_0_height_0__pin_1_lower ; -wire [0:0] grid_io_right_1_left_width_0_height_0__pin_1_upper ; -wire [0:0] grid_io_top_0_bottom_width_0_height_0__pin_1_lower ; -wire [0:0] grid_io_top_0_bottom_width_0_height_0__pin_1_upper ; -wire [0:0] grid_io_top_0_ccff_tail ; -wire [0:0] grid_io_top_1_bottom_width_0_height_0__pin_1_lower ; -wire [0:0] grid_io_top_1_bottom_width_0_height_0__pin_1_upper ; -wire [0:0] grid_io_top_1_ccff_tail ; -wire [0:19] sb_0__0__0_chanx_right_out ; -wire [0:19] sb_0__0__0_chany_top_out ; -wire [0:0] sb_0__1__0_ccff_tail ; -wire [0:19] sb_0__1__0_chanx_right_out ; -wire [0:19] sb_0__1__0_chany_bottom_out ; -wire [0:19] sb_0__1__0_chany_top_out ; -wire [0:0] sb_0__2__0_ccff_tail ; -wire [0:19] sb_0__2__0_chanx_right_out ; -wire [0:19] sb_0__2__0_chany_bottom_out ; -wire [0:0] sb_1__0__0_ccff_tail ; -wire [0:19] sb_1__0__0_chanx_left_out ; -wire [0:19] sb_1__0__0_chanx_right_out ; -wire [0:19] sb_1__0__0_chany_top_out ; -wire [0:0] sb_1__1__0_ccff_tail ; -wire [0:19] sb_1__1__0_chanx_left_out ; -wire [0:19] sb_1__1__0_chanx_right_out ; -wire [0:19] sb_1__1__0_chany_bottom_out ; -wire [0:19] sb_1__1__0_chany_top_out ; -wire [0:0] sb_1__2__0_ccff_tail ; -wire [0:19] sb_1__2__0_chanx_left_out ; -wire [0:19] sb_1__2__0_chanx_right_out ; -wire [0:19] sb_1__2__0_chany_bottom_out ; -wire [0:0] sb_2__0__0_ccff_tail ; -wire [0:19] sb_2__0__0_chanx_left_out ; -wire [0:19] sb_2__0__0_chany_top_out ; -wire [0:0] sb_2__1__0_ccff_tail ; -wire [0:19] sb_2__1__0_chanx_left_out ; -wire [0:19] sb_2__1__0_chany_bottom_out ; -wire [0:19] sb_2__1__0_chany_top_out ; -wire [0:0] sb_2__2__0_ccff_tail ; -wire [0:19] sb_2__2__0_chanx_left_out ; -wire [0:19] sb_2__2__0_chany_bottom_out ; -wire [0:0] prog_clk__FEEDTHRU_1 ; -wire [0:0] prog_clk__FEEDTHRU_2 ; -wire [0:0] prog_clk__FEEDTHRU_3 ; -wire [0:0] prog_clk__FEEDTHRU_4 ; -wire [0:0] prog_clk__FEEDTHRU_5 ; -wire [0:0] prog_clk__FEEDTHRU_6 ; -wire [0:0] prog_clk__FEEDTHRU_7 ; -wire [0:0] prog_clk__FEEDTHRU_8 ; -wire [0:0] prog_clk__FEEDTHRU_9 ; -wire [0:0] prog_clk__FEEDTHRU_10 ; -wire [0:0] prog_clk__FEEDTHRU_11 ; -wire [0:0] prog_clk__FEEDTHRU_12 ; -wire [0:0] prog_clk__FEEDTHRU_13 ; -wire [0:0] prog_clk__FEEDTHRU_14 ; -wire [0:0] prog_clk__FEEDTHRU_15 ; -wire [0:0] prog_clk__FEEDTHRU_16 ; -wire [0:0] prog_clk__FEEDTHRU_17 ; -wire [0:0] prog_clk__FEEDTHRU_18 ; -wire [0:0] prog_clk__FEEDTHRU_19 ; -wire [0:0] Test_en__FEEDTHRU_1 ; -wire [0:0] Test_en__FEEDTHRU_2 ; -wire [0:0] Test_en__FEEDTHRU_3 ; -wire [0:0] Test_en__FEEDTHRU_4 ; -wire [0:0] Test_en__FEEDTHRU_5 ; -wire [0:0] Test_en__FEEDTHRU_6 ; -wire [0:0] clk__FEEDTHRU_1 ; -wire [0:0] clk__FEEDTHRU_2 ; -wire [0:0] clk__FEEDTHRU_3 ; -wire [0:0] clk__FEEDTHRU_4 ; -wire [0:0] clk__FEEDTHRU_5 ; -wire [0:0] clk__FEEDTHRU_6 ; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ; -// - -grid_clb grid_clb_1__1_ ( - .prog_clk ( { ctsbuf_net_1921 } ) , - .Test_en ( Test_en__FEEDTHRU_6 ) , .clk ( clk__FEEDTHRU_6 ) , - .top_width_0_height_0__pin_0_ ( cbx_1__1__0_bottom_grid_pin_0_ ) , - .top_width_0_height_0__pin_1_ ( cbx_1__1__0_bottom_grid_pin_1_ ) , - .top_width_0_height_0__pin_2_ ( cbx_1__1__0_bottom_grid_pin_2_ ) , - .top_width_0_height_0__pin_3_ ( cbx_1__1__0_bottom_grid_pin_3_ ) , - .top_width_0_height_0__pin_4_ ( cbx_1__1__0_bottom_grid_pin_4_ ) , - .top_width_0_height_0__pin_5_ ( cbx_1__1__0_bottom_grid_pin_5_ ) , - .top_width_0_height_0__pin_6_ ( cbx_1__1__0_bottom_grid_pin_6_ ) , - .top_width_0_height_0__pin_7_ ( cbx_1__1__0_bottom_grid_pin_7_ ) , - .top_width_0_height_0__pin_8_ ( cbx_1__1__0_bottom_grid_pin_8_ ) , - .top_width_0_height_0__pin_9_ ( cbx_1__1__0_bottom_grid_pin_9_ ) , - .top_width_0_height_0__pin_10_ ( cbx_1__1__0_bottom_grid_pin_10_ ) , - .top_width_0_height_0__pin_11_ ( cbx_1__1__0_bottom_grid_pin_11_ ) , - .top_width_0_height_0__pin_12_ ( cbx_1__1__0_bottom_grid_pin_12_ ) , - .top_width_0_height_0__pin_13_ ( cbx_1__1__0_bottom_grid_pin_13_ ) , - .top_width_0_height_0__pin_14_ ( cbx_1__1__0_bottom_grid_pin_14_ ) , - .top_width_0_height_0__pin_15_ ( cbx_1__1__0_bottom_grid_pin_15_ ) , - .top_width_0_height_0__pin_32_ ( direct_interc_0_out ) , - .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1 } ) , - .right_width_0_height_0__pin_16_ ( cby_1__1__0_left_grid_pin_16_ ) , - .right_width_0_height_0__pin_17_ ( cby_1__1__0_left_grid_pin_17_ ) , - .right_width_0_height_0__pin_18_ ( cby_1__1__0_left_grid_pin_18_ ) , - .right_width_0_height_0__pin_19_ ( cby_1__1__0_left_grid_pin_19_ ) , - .right_width_0_height_0__pin_20_ ( cby_1__1__0_left_grid_pin_20_ ) , - .right_width_0_height_0__pin_21_ ( cby_1__1__0_left_grid_pin_21_ ) , - .right_width_0_height_0__pin_22_ ( cby_1__1__0_left_grid_pin_22_ ) , - .right_width_0_height_0__pin_23_ ( cby_1__1__0_left_grid_pin_23_ ) , - .right_width_0_height_0__pin_24_ ( cby_1__1__0_left_grid_pin_24_ ) , - .right_width_0_height_0__pin_25_ ( cby_1__1__0_left_grid_pin_25_ ) , - .right_width_0_height_0__pin_26_ ( cby_1__1__0_left_grid_pin_26_ ) , - .right_width_0_height_0__pin_27_ ( cby_1__1__0_left_grid_pin_27_ ) , - .right_width_0_height_0__pin_28_ ( cby_1__1__0_left_grid_pin_28_ ) , - .right_width_0_height_0__pin_29_ ( cby_1__1__0_left_grid_pin_29_ ) , - .right_width_0_height_0__pin_30_ ( cby_1__1__0_left_grid_pin_30_ ) , - .right_width_0_height_0__pin_31_ ( cby_1__1__0_left_grid_pin_31_ ) , - .left_width_0_height_0__pin_52_ ( grid_clb_1__1__undriven_left_width_0_height_0__pin_52_ ) , - .ccff_head ( grid_io_left_0_ccff_tail ) , - .top_width_0_height_0__pin_34_upper ( grid_clb_0_top_width_0_height_0__pin_34_upper ) , - .top_width_0_height_0__pin_34_lower ( grid_clb_0_top_width_0_height_0__pin_34_lower ) , - .top_width_0_height_0__pin_35_upper ( grid_clb_0_top_width_0_height_0__pin_35_upper ) , - .top_width_0_height_0__pin_35_lower ( grid_clb_0_top_width_0_height_0__pin_35_lower ) , - .top_width_0_height_0__pin_36_upper ( grid_clb_0_top_width_0_height_0__pin_36_upper ) , - .top_width_0_height_0__pin_36_lower ( grid_clb_0_top_width_0_height_0__pin_36_lower ) , - .top_width_0_height_0__pin_37_upper ( grid_clb_0_top_width_0_height_0__pin_37_upper ) , - .top_width_0_height_0__pin_37_lower ( grid_clb_0_top_width_0_height_0__pin_37_lower ) , - .top_width_0_height_0__pin_38_upper ( grid_clb_0_top_width_0_height_0__pin_38_upper ) , - .top_width_0_height_0__pin_38_lower ( grid_clb_0_top_width_0_height_0__pin_38_lower ) , - .top_width_0_height_0__pin_39_upper ( grid_clb_0_top_width_0_height_0__pin_39_upper ) , - .top_width_0_height_0__pin_39_lower ( grid_clb_0_top_width_0_height_0__pin_39_lower ) , - .top_width_0_height_0__pin_40_upper ( grid_clb_0_top_width_0_height_0__pin_40_upper ) , - .top_width_0_height_0__pin_40_lower ( grid_clb_0_top_width_0_height_0__pin_40_lower ) , - .top_width_0_height_0__pin_41_upper ( grid_clb_0_top_width_0_height_0__pin_41_upper ) , - .top_width_0_height_0__pin_41_lower ( grid_clb_0_top_width_0_height_0__pin_41_lower ) , - .right_width_0_height_0__pin_42_upper ( grid_clb_0_right_width_0_height_0__pin_42_upper ) , - .right_width_0_height_0__pin_42_lower ( grid_clb_0_right_width_0_height_0__pin_42_lower ) , - .right_width_0_height_0__pin_43_upper ( grid_clb_0_right_width_0_height_0__pin_43_upper ) , - .right_width_0_height_0__pin_43_lower ( grid_clb_0_right_width_0_height_0__pin_43_lower ) , - .right_width_0_height_0__pin_44_upper ( grid_clb_0_right_width_0_height_0__pin_44_upper ) , - .right_width_0_height_0__pin_44_lower ( grid_clb_0_right_width_0_height_0__pin_44_lower ) , - .right_width_0_height_0__pin_45_upper ( grid_clb_0_right_width_0_height_0__pin_45_upper ) , - .right_width_0_height_0__pin_45_lower ( grid_clb_0_right_width_0_height_0__pin_45_lower ) , - .right_width_0_height_0__pin_46_upper ( grid_clb_0_right_width_0_height_0__pin_46_upper ) , - .right_width_0_height_0__pin_46_lower ( grid_clb_0_right_width_0_height_0__pin_46_lower ) , - .right_width_0_height_0__pin_47_upper ( grid_clb_0_right_width_0_height_0__pin_47_upper ) , - .right_width_0_height_0__pin_47_lower ( grid_clb_0_right_width_0_height_0__pin_47_lower ) , - .right_width_0_height_0__pin_48_upper ( grid_clb_0_right_width_0_height_0__pin_48_upper ) , - .right_width_0_height_0__pin_48_lower ( grid_clb_0_right_width_0_height_0__pin_48_lower ) , - .right_width_0_height_0__pin_49_upper ( grid_clb_0_right_width_0_height_0__pin_49_upper ) , - .right_width_0_height_0__pin_49_lower ( grid_clb_0_right_width_0_height_0__pin_49_lower ) , - .bottom_width_0_height_0__pin_50_ ( grid_clb_0_bottom_width_0_height_0__pin_50_ ) , - .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_2 } ) , - .ccff_tail ( grid_clb_0_ccff_tail ) , .SC_IN_TOP ( scff_Wires_3_ ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_3 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4 ) , .SC_OUT_BOT ( scff_Wires_5_ ) , - .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_3 ) , - .prog_clk__FEEDTHRU_2 ( prog_clk__FEEDTHRU_4 ) , - .prog_clk__FEEDTHRU_3 ( { SYNOPSYS_UNCONNECTED_5 } ) , - .prog_clk__FEEDTHRU_4 ( { SYNOPSYS_UNCONNECTED_6 } ) , - .Test_en__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_7 } ) , - .clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_8 } ) ) ; -grid_clb grid_clb_1__2_ ( - .prog_clk ( { ctsbuf_net_1113 } ) , - .Test_en ( Test_en__FEEDTHRU_4 ) , .clk ( clk__FEEDTHRU_4 ) , - .top_width_0_height_0__pin_0_ ( cbx_1__2__0_bottom_grid_pin_0_ ) , - .top_width_0_height_0__pin_1_ ( cbx_1__2__0_bottom_grid_pin_1_ ) , - .top_width_0_height_0__pin_2_ ( cbx_1__2__0_bottom_grid_pin_2_ ) , - .top_width_0_height_0__pin_3_ ( cbx_1__2__0_bottom_grid_pin_3_ ) , - .top_width_0_height_0__pin_4_ ( cbx_1__2__0_bottom_grid_pin_4_ ) , - .top_width_0_height_0__pin_5_ ( cbx_1__2__0_bottom_grid_pin_5_ ) , - .top_width_0_height_0__pin_6_ ( cbx_1__2__0_bottom_grid_pin_6_ ) , - .top_width_0_height_0__pin_7_ ( cbx_1__2__0_bottom_grid_pin_7_ ) , - .top_width_0_height_0__pin_8_ ( cbx_1__2__0_bottom_grid_pin_8_ ) , - .top_width_0_height_0__pin_9_ ( cbx_1__2__0_bottom_grid_pin_9_ ) , - .top_width_0_height_0__pin_10_ ( cbx_1__2__0_bottom_grid_pin_10_ ) , - .top_width_0_height_0__pin_11_ ( cbx_1__2__0_bottom_grid_pin_11_ ) , - .top_width_0_height_0__pin_12_ ( cbx_1__2__0_bottom_grid_pin_12_ ) , - .top_width_0_height_0__pin_13_ ( cbx_1__2__0_bottom_grid_pin_13_ ) , - .top_width_0_height_0__pin_14_ ( cbx_1__2__0_bottom_grid_pin_14_ ) , - .top_width_0_height_0__pin_15_ ( cbx_1__2__0_bottom_grid_pin_15_ ) , - .top_width_0_height_0__pin_32_ ( grid_clb_1__2__undriven_top_width_0_height_0__pin_32_ ) , - .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_9 } ) , - .right_width_0_height_0__pin_16_ ( cby_1__1__1_left_grid_pin_16_ ) , - .right_width_0_height_0__pin_17_ ( cby_1__1__1_left_grid_pin_17_ ) , - .right_width_0_height_0__pin_18_ ( cby_1__1__1_left_grid_pin_18_ ) , - .right_width_0_height_0__pin_19_ ( cby_1__1__1_left_grid_pin_19_ ) , - .right_width_0_height_0__pin_20_ ( cby_1__1__1_left_grid_pin_20_ ) , - .right_width_0_height_0__pin_21_ ( cby_1__1__1_left_grid_pin_21_ ) , - .right_width_0_height_0__pin_22_ ( cby_1__1__1_left_grid_pin_22_ ) , - .right_width_0_height_0__pin_23_ ( cby_1__1__1_left_grid_pin_23_ ) , - .right_width_0_height_0__pin_24_ ( cby_1__1__1_left_grid_pin_24_ ) , - .right_width_0_height_0__pin_25_ ( cby_1__1__1_left_grid_pin_25_ ) , - .right_width_0_height_0__pin_26_ ( cby_1__1__1_left_grid_pin_26_ ) , - .right_width_0_height_0__pin_27_ ( cby_1__1__1_left_grid_pin_27_ ) , - .right_width_0_height_0__pin_28_ ( cby_1__1__1_left_grid_pin_28_ ) , - .right_width_0_height_0__pin_29_ ( cby_1__1__1_left_grid_pin_29_ ) , - .right_width_0_height_0__pin_30_ ( cby_1__1__1_left_grid_pin_30_ ) , - .right_width_0_height_0__pin_31_ ( cby_1__1__1_left_grid_pin_31_ ) , - .left_width_0_height_0__pin_52_ ( grid_clb_1__2__undriven_left_width_0_height_0__pin_52_ ) , - .ccff_head ( grid_io_left_1_ccff_tail ) , - .top_width_0_height_0__pin_34_upper ( grid_clb_1_top_width_0_height_0__pin_34_upper ) , - .top_width_0_height_0__pin_34_lower ( grid_clb_1_top_width_0_height_0__pin_34_lower ) , - .top_width_0_height_0__pin_35_upper ( grid_clb_1_top_width_0_height_0__pin_35_upper ) , - .top_width_0_height_0__pin_35_lower ( grid_clb_1_top_width_0_height_0__pin_35_lower ) , - .top_width_0_height_0__pin_36_upper ( grid_clb_1_top_width_0_height_0__pin_36_upper ) , - .top_width_0_height_0__pin_36_lower ( grid_clb_1_top_width_0_height_0__pin_36_lower ) , - .top_width_0_height_0__pin_37_upper ( grid_clb_1_top_width_0_height_0__pin_37_upper ) , - .top_width_0_height_0__pin_37_lower ( grid_clb_1_top_width_0_height_0__pin_37_lower ) , - .top_width_0_height_0__pin_38_upper ( grid_clb_1_top_width_0_height_0__pin_38_upper ) , - .top_width_0_height_0__pin_38_lower ( grid_clb_1_top_width_0_height_0__pin_38_lower ) , - .top_width_0_height_0__pin_39_upper ( grid_clb_1_top_width_0_height_0__pin_39_upper ) , - .top_width_0_height_0__pin_39_lower ( grid_clb_1_top_width_0_height_0__pin_39_lower ) , - .top_width_0_height_0__pin_40_upper ( grid_clb_1_top_width_0_height_0__pin_40_upper ) , - .top_width_0_height_0__pin_40_lower ( grid_clb_1_top_width_0_height_0__pin_40_lower ) , - .top_width_0_height_0__pin_41_upper ( grid_clb_1_top_width_0_height_0__pin_41_upper ) , - .top_width_0_height_0__pin_41_lower ( grid_clb_1_top_width_0_height_0__pin_41_lower ) , - .right_width_0_height_0__pin_42_upper ( grid_clb_1_right_width_0_height_0__pin_42_upper ) , - .right_width_0_height_0__pin_42_lower ( grid_clb_1_right_width_0_height_0__pin_42_lower ) , - .right_width_0_height_0__pin_43_upper ( grid_clb_1_right_width_0_height_0__pin_43_upper ) , - .right_width_0_height_0__pin_43_lower ( grid_clb_1_right_width_0_height_0__pin_43_lower ) , - .right_width_0_height_0__pin_44_upper ( grid_clb_1_right_width_0_height_0__pin_44_upper ) , - .right_width_0_height_0__pin_44_lower ( grid_clb_1_right_width_0_height_0__pin_44_lower ) , - .right_width_0_height_0__pin_45_upper ( grid_clb_1_right_width_0_height_0__pin_45_upper ) , - .right_width_0_height_0__pin_45_lower ( grid_clb_1_right_width_0_height_0__pin_45_lower ) , - .right_width_0_height_0__pin_46_upper ( grid_clb_1_right_width_0_height_0__pin_46_upper ) , - .right_width_0_height_0__pin_46_lower ( grid_clb_1_right_width_0_height_0__pin_46_lower ) , - .right_width_0_height_0__pin_47_upper ( grid_clb_1_right_width_0_height_0__pin_47_upper ) , - .right_width_0_height_0__pin_47_lower ( grid_clb_1_right_width_0_height_0__pin_47_lower ) , - .right_width_0_height_0__pin_48_upper ( grid_clb_1_right_width_0_height_0__pin_48_upper ) , - .right_width_0_height_0__pin_48_lower ( grid_clb_1_right_width_0_height_0__pin_48_lower ) , - .right_width_0_height_0__pin_49_upper ( grid_clb_1_right_width_0_height_0__pin_49_upper ) , - .right_width_0_height_0__pin_49_lower ( grid_clb_1_right_width_0_height_0__pin_49_lower ) , - .bottom_width_0_height_0__pin_50_ ( grid_clb_1_bottom_width_0_height_0__pin_50_ ) , - .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_10 } ) , - .ccff_tail ( grid_clb_1_ccff_tail ) , .SC_IN_TOP ( scff_Wires_1_ ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_11 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_12 ) , .SC_OUT_BOT ( scff_Wires_2_ ) , - .prog_clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_13 } ) , - .prog_clk__FEEDTHRU_2 ( { SYNOPSYS_UNCONNECTED_14 } ) , - .prog_clk__FEEDTHRU_3 ( prog_clk__FEEDTHRU_6 ) , - .prog_clk__FEEDTHRU_4 ( { SYNOPSYS_UNCONNECTED_15 } ) , - .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_5 ) , - .clk__FEEDTHRU_1 ( clk__FEEDTHRU_5 ) ) ; -grid_clb grid_clb_2__1_ ( .prog_clk ( prog_clk__FEEDTHRU_16 ) , - .Test_en ( Test_en__FEEDTHRU_3 ) , .clk ( clk__FEEDTHRU_3 ) , - .top_width_0_height_0__pin_0_ ( cbx_1__1__1_bottom_grid_pin_0_ ) , - .top_width_0_height_0__pin_1_ ( cbx_1__1__1_bottom_grid_pin_1_ ) , - .top_width_0_height_0__pin_2_ ( cbx_1__1__1_bottom_grid_pin_2_ ) , - .top_width_0_height_0__pin_3_ ( cbx_1__1__1_bottom_grid_pin_3_ ) , - .top_width_0_height_0__pin_4_ ( cbx_1__1__1_bottom_grid_pin_4_ ) , - .top_width_0_height_0__pin_5_ ( cbx_1__1__1_bottom_grid_pin_5_ ) , - .top_width_0_height_0__pin_6_ ( cbx_1__1__1_bottom_grid_pin_6_ ) , - .top_width_0_height_0__pin_7_ ( cbx_1__1__1_bottom_grid_pin_7_ ) , - .top_width_0_height_0__pin_8_ ( cbx_1__1__1_bottom_grid_pin_8_ ) , - .top_width_0_height_0__pin_9_ ( cbx_1__1__1_bottom_grid_pin_9_ ) , - .top_width_0_height_0__pin_10_ ( cbx_1__1__1_bottom_grid_pin_10_ ) , - .top_width_0_height_0__pin_11_ ( cbx_1__1__1_bottom_grid_pin_11_ ) , - .top_width_0_height_0__pin_12_ ( cbx_1__1__1_bottom_grid_pin_12_ ) , - .top_width_0_height_0__pin_13_ ( cbx_1__1__1_bottom_grid_pin_13_ ) , - .top_width_0_height_0__pin_14_ ( cbx_1__1__1_bottom_grid_pin_14_ ) , - .top_width_0_height_0__pin_15_ ( cbx_1__1__1_bottom_grid_pin_15_ ) , - .top_width_0_height_0__pin_32_ ( direct_interc_1_out ) , - .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_16 } ) , - .right_width_0_height_0__pin_16_ ( cby_2__1__0_left_grid_pin_16_ ) , - .right_width_0_height_0__pin_17_ ( cby_2__1__0_left_grid_pin_17_ ) , - .right_width_0_height_0__pin_18_ ( cby_2__1__0_left_grid_pin_18_ ) , - .right_width_0_height_0__pin_19_ ( cby_2__1__0_left_grid_pin_19_ ) , - .right_width_0_height_0__pin_20_ ( cby_2__1__0_left_grid_pin_20_ ) , - .right_width_0_height_0__pin_21_ ( cby_2__1__0_left_grid_pin_21_ ) , - .right_width_0_height_0__pin_22_ ( cby_2__1__0_left_grid_pin_22_ ) , - .right_width_0_height_0__pin_23_ ( cby_2__1__0_left_grid_pin_23_ ) , - .right_width_0_height_0__pin_24_ ( cby_2__1__0_left_grid_pin_24_ ) , - .right_width_0_height_0__pin_25_ ( cby_2__1__0_left_grid_pin_25_ ) , - .right_width_0_height_0__pin_26_ ( cby_2__1__0_left_grid_pin_26_ ) , - .right_width_0_height_0__pin_27_ ( cby_2__1__0_left_grid_pin_27_ ) , - .right_width_0_height_0__pin_28_ ( cby_2__1__0_left_grid_pin_28_ ) , - .right_width_0_height_0__pin_29_ ( cby_2__1__0_left_grid_pin_29_ ) , - .right_width_0_height_0__pin_30_ ( cby_2__1__0_left_grid_pin_30_ ) , - .right_width_0_height_0__pin_31_ ( cby_2__1__0_left_grid_pin_31_ ) , - .left_width_0_height_0__pin_52_ ( grid_clb_2__1__undriven_left_width_0_height_0__pin_52_ ) , - .ccff_head ( cby_1__1__0_ccff_tail ) , - .top_width_0_height_0__pin_34_upper ( grid_clb_2_top_width_0_height_0__pin_34_upper ) , - .top_width_0_height_0__pin_34_lower ( grid_clb_2_top_width_0_height_0__pin_34_lower ) , - .top_width_0_height_0__pin_35_upper ( grid_clb_2_top_width_0_height_0__pin_35_upper ) , - .top_width_0_height_0__pin_35_lower ( grid_clb_2_top_width_0_height_0__pin_35_lower ) , - .top_width_0_height_0__pin_36_upper ( grid_clb_2_top_width_0_height_0__pin_36_upper ) , - .top_width_0_height_0__pin_36_lower ( grid_clb_2_top_width_0_height_0__pin_36_lower ) , - .top_width_0_height_0__pin_37_upper ( grid_clb_2_top_width_0_height_0__pin_37_upper ) , - .top_width_0_height_0__pin_37_lower ( grid_clb_2_top_width_0_height_0__pin_37_lower ) , - .top_width_0_height_0__pin_38_upper ( grid_clb_2_top_width_0_height_0__pin_38_upper ) , - .top_width_0_height_0__pin_38_lower ( grid_clb_2_top_width_0_height_0__pin_38_lower ) , - .top_width_0_height_0__pin_39_upper ( grid_clb_2_top_width_0_height_0__pin_39_upper ) , - .top_width_0_height_0__pin_39_lower ( grid_clb_2_top_width_0_height_0__pin_39_lower ) , - .top_width_0_height_0__pin_40_upper ( grid_clb_2_top_width_0_height_0__pin_40_upper ) , - .top_width_0_height_0__pin_40_lower ( grid_clb_2_top_width_0_height_0__pin_40_lower ) , - .top_width_0_height_0__pin_41_upper ( grid_clb_2_top_width_0_height_0__pin_41_upper ) , - .top_width_0_height_0__pin_41_lower ( grid_clb_2_top_width_0_height_0__pin_41_lower ) , - .right_width_0_height_0__pin_42_upper ( grid_clb_2_right_width_0_height_0__pin_42_upper ) , - .right_width_0_height_0__pin_42_lower ( grid_clb_2_right_width_0_height_0__pin_42_lower ) , - .right_width_0_height_0__pin_43_upper ( grid_clb_2_right_width_0_height_0__pin_43_upper ) , - .right_width_0_height_0__pin_43_lower ( grid_clb_2_right_width_0_height_0__pin_43_lower ) , - .right_width_0_height_0__pin_44_upper ( grid_clb_2_right_width_0_height_0__pin_44_upper ) , - .right_width_0_height_0__pin_44_lower ( grid_clb_2_right_width_0_height_0__pin_44_lower ) , - .right_width_0_height_0__pin_45_upper ( grid_clb_2_right_width_0_height_0__pin_45_upper ) , - .right_width_0_height_0__pin_45_lower ( grid_clb_2_right_width_0_height_0__pin_45_lower ) , - .right_width_0_height_0__pin_46_upper ( grid_clb_2_right_width_0_height_0__pin_46_upper ) , - .right_width_0_height_0__pin_46_lower ( grid_clb_2_right_width_0_height_0__pin_46_lower ) , - .right_width_0_height_0__pin_47_upper ( grid_clb_2_right_width_0_height_0__pin_47_upper ) , - .right_width_0_height_0__pin_47_lower ( grid_clb_2_right_width_0_height_0__pin_47_lower ) , - .right_width_0_height_0__pin_48_upper ( grid_clb_2_right_width_0_height_0__pin_48_upper ) , - .right_width_0_height_0__pin_48_lower ( grid_clb_2_right_width_0_height_0__pin_48_lower ) , - .right_width_0_height_0__pin_49_upper ( grid_clb_2_right_width_0_height_0__pin_49_upper ) , - .right_width_0_height_0__pin_49_lower ( grid_clb_2_right_width_0_height_0__pin_49_lower ) , - .bottom_width_0_height_0__pin_50_ ( grid_clb_2__1__undriven_bottom_width_0_height_0__pin_50_ ) , - .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_17 } ) , - .ccff_tail ( grid_clb_2_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_18 ) , .SC_IN_BOT ( scff_Wires_8_ ) , - .SC_OUT_TOP ( scff_Wires_9_ ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_19 ) , - .prog_clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_20 } ) , - .prog_clk__FEEDTHRU_2 ( prog_clk__FEEDTHRU_17 ) , - .prog_clk__FEEDTHRU_3 ( { SYNOPSYS_UNCONNECTED_21 } ) , - .prog_clk__FEEDTHRU_4 ( prog_clk__FEEDTHRU_19 ) , - .Test_en__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_22 } ) , - .clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_23 } ) ) ; -grid_clb grid_clb_2__2_ ( - .prog_clk ( { ctsbuf_net_1315 } ) , - .Test_en ( Test_en__FEEDTHRU_1 ) , .clk ( clk__FEEDTHRU_1 ) , - .top_width_0_height_0__pin_0_ ( cbx_1__2__1_bottom_grid_pin_0_ ) , - .top_width_0_height_0__pin_1_ ( cbx_1__2__1_bottom_grid_pin_1_ ) , - .top_width_0_height_0__pin_2_ ( cbx_1__2__1_bottom_grid_pin_2_ ) , - .top_width_0_height_0__pin_3_ ( cbx_1__2__1_bottom_grid_pin_3_ ) , - .top_width_0_height_0__pin_4_ ( cbx_1__2__1_bottom_grid_pin_4_ ) , - .top_width_0_height_0__pin_5_ ( cbx_1__2__1_bottom_grid_pin_5_ ) , - .top_width_0_height_0__pin_6_ ( cbx_1__2__1_bottom_grid_pin_6_ ) , - .top_width_0_height_0__pin_7_ ( cbx_1__2__1_bottom_grid_pin_7_ ) , - .top_width_0_height_0__pin_8_ ( cbx_1__2__1_bottom_grid_pin_8_ ) , - .top_width_0_height_0__pin_9_ ( cbx_1__2__1_bottom_grid_pin_9_ ) , - .top_width_0_height_0__pin_10_ ( cbx_1__2__1_bottom_grid_pin_10_ ) , - .top_width_0_height_0__pin_11_ ( cbx_1__2__1_bottom_grid_pin_11_ ) , - .top_width_0_height_0__pin_12_ ( cbx_1__2__1_bottom_grid_pin_12_ ) , - .top_width_0_height_0__pin_13_ ( cbx_1__2__1_bottom_grid_pin_13_ ) , - .top_width_0_height_0__pin_14_ ( cbx_1__2__1_bottom_grid_pin_14_ ) , - .top_width_0_height_0__pin_15_ ( cbx_1__2__1_bottom_grid_pin_15_ ) , - .top_width_0_height_0__pin_32_ ( direct_interc_2_out ) , - .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_24 } ) , - .right_width_0_height_0__pin_16_ ( cby_2__1__1_left_grid_pin_16_ ) , - .right_width_0_height_0__pin_17_ ( cby_2__1__1_left_grid_pin_17_ ) , - .right_width_0_height_0__pin_18_ ( cby_2__1__1_left_grid_pin_18_ ) , - .right_width_0_height_0__pin_19_ ( cby_2__1__1_left_grid_pin_19_ ) , - .right_width_0_height_0__pin_20_ ( cby_2__1__1_left_grid_pin_20_ ) , - .right_width_0_height_0__pin_21_ ( cby_2__1__1_left_grid_pin_21_ ) , - .right_width_0_height_0__pin_22_ ( cby_2__1__1_left_grid_pin_22_ ) , - .right_width_0_height_0__pin_23_ ( cby_2__1__1_left_grid_pin_23_ ) , - .right_width_0_height_0__pin_24_ ( cby_2__1__1_left_grid_pin_24_ ) , - .right_width_0_height_0__pin_25_ ( cby_2__1__1_left_grid_pin_25_ ) , - .right_width_0_height_0__pin_26_ ( cby_2__1__1_left_grid_pin_26_ ) , - .right_width_0_height_0__pin_27_ ( cby_2__1__1_left_grid_pin_27_ ) , - .right_width_0_height_0__pin_28_ ( cby_2__1__1_left_grid_pin_28_ ) , - .right_width_0_height_0__pin_29_ ( cby_2__1__1_left_grid_pin_29_ ) , - .right_width_0_height_0__pin_30_ ( cby_2__1__1_left_grid_pin_30_ ) , - .right_width_0_height_0__pin_31_ ( cby_2__1__1_left_grid_pin_31_ ) , - .left_width_0_height_0__pin_52_ ( grid_clb_2__2__undriven_left_width_0_height_0__pin_52_ ) , - .ccff_head ( cby_1__1__1_ccff_tail ) , - .top_width_0_height_0__pin_34_upper ( grid_clb_3_top_width_0_height_0__pin_34_upper ) , - .top_width_0_height_0__pin_34_lower ( grid_clb_3_top_width_0_height_0__pin_34_lower ) , - .top_width_0_height_0__pin_35_upper ( grid_clb_3_top_width_0_height_0__pin_35_upper ) , - .top_width_0_height_0__pin_35_lower ( grid_clb_3_top_width_0_height_0__pin_35_lower ) , - .top_width_0_height_0__pin_36_upper ( grid_clb_3_top_width_0_height_0__pin_36_upper ) , - .top_width_0_height_0__pin_36_lower ( grid_clb_3_top_width_0_height_0__pin_36_lower ) , - .top_width_0_height_0__pin_37_upper ( grid_clb_3_top_width_0_height_0__pin_37_upper ) , - .top_width_0_height_0__pin_37_lower ( grid_clb_3_top_width_0_height_0__pin_37_lower ) , - .top_width_0_height_0__pin_38_upper ( grid_clb_3_top_width_0_height_0__pin_38_upper ) , - .top_width_0_height_0__pin_38_lower ( grid_clb_3_top_width_0_height_0__pin_38_lower ) , - .top_width_0_height_0__pin_39_upper ( grid_clb_3_top_width_0_height_0__pin_39_upper ) , - .top_width_0_height_0__pin_39_lower ( grid_clb_3_top_width_0_height_0__pin_39_lower ) , - .top_width_0_height_0__pin_40_upper ( grid_clb_3_top_width_0_height_0__pin_40_upper ) , - .top_width_0_height_0__pin_40_lower ( grid_clb_3_top_width_0_height_0__pin_40_lower ) , - .top_width_0_height_0__pin_41_upper ( grid_clb_3_top_width_0_height_0__pin_41_upper ) , - .top_width_0_height_0__pin_41_lower ( grid_clb_3_top_width_0_height_0__pin_41_lower ) , - .right_width_0_height_0__pin_42_upper ( grid_clb_3_right_width_0_height_0__pin_42_upper ) , - .right_width_0_height_0__pin_42_lower ( grid_clb_3_right_width_0_height_0__pin_42_lower ) , - .right_width_0_height_0__pin_43_upper ( grid_clb_3_right_width_0_height_0__pin_43_upper ) , - .right_width_0_height_0__pin_43_lower ( grid_clb_3_right_width_0_height_0__pin_43_lower ) , - .right_width_0_height_0__pin_44_upper ( grid_clb_3_right_width_0_height_0__pin_44_upper ) , - .right_width_0_height_0__pin_44_lower ( grid_clb_3_right_width_0_height_0__pin_44_lower ) , - .right_width_0_height_0__pin_45_upper ( grid_clb_3_right_width_0_height_0__pin_45_upper ) , - .right_width_0_height_0__pin_45_lower ( grid_clb_3_right_width_0_height_0__pin_45_lower ) , - .right_width_0_height_0__pin_46_upper ( grid_clb_3_right_width_0_height_0__pin_46_upper ) , - .right_width_0_height_0__pin_46_lower ( grid_clb_3_right_width_0_height_0__pin_46_lower ) , - .right_width_0_height_0__pin_47_upper ( grid_clb_3_right_width_0_height_0__pin_47_upper ) , - .right_width_0_height_0__pin_47_lower ( grid_clb_3_right_width_0_height_0__pin_47_lower ) , - .right_width_0_height_0__pin_48_upper ( grid_clb_3_right_width_0_height_0__pin_48_upper ) , - .right_width_0_height_0__pin_48_lower ( grid_clb_3_right_width_0_height_0__pin_48_lower ) , - .right_width_0_height_0__pin_49_upper ( grid_clb_3_right_width_0_height_0__pin_49_upper ) , - .right_width_0_height_0__pin_49_lower ( grid_clb_3_right_width_0_height_0__pin_49_lower ) , - .bottom_width_0_height_0__pin_50_ ( grid_clb_3_bottom_width_0_height_0__pin_50_ ) , - .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_25 } ) , - .ccff_tail ( grid_clb_3_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_26 ) , .SC_IN_BOT ( scff_Wires_10_ ) , - .SC_OUT_TOP ( scff_Wires_11_ ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_27 ) , - .prog_clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_28 } ) , - .prog_clk__FEEDTHRU_2 ( { SYNOPSYS_UNCONNECTED_29 } ) , - .prog_clk__FEEDTHRU_3 ( prog_clk__FEEDTHRU_13 ) , - .prog_clk__FEEDTHRU_4 ( prog_clk__FEEDTHRU_15 ) , - .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_2 ) , - .clk__FEEDTHRU_1 ( clk__FEEDTHRU_2 ) ) ; -sb_0__0_ sb_0__0_ ( - .prog_clk ( { ctsbuf_net_1719 } ) , - .chany_top_in ( cby_0__1__0_chany_bottom_out ) , - .top_left_grid_pin_1_ ( grid_io_left_0_right_width_0_height_0__pin_1_lower ) , - .chanx_right_in ( cbx_1__0__0_chanx_left_out ) , - .right_bottom_grid_pin_1_ ( grid_io_bottom_0_top_width_0_height_0__pin_1_upper ) , - .right_bottom_grid_pin_3_ ( grid_io_bottom_0_top_width_0_height_0__pin_3_upper ) , - .right_bottom_grid_pin_5_ ( grid_io_bottom_0_top_width_0_height_0__pin_5_upper ) , - .right_bottom_grid_pin_7_ ( grid_io_bottom_0_top_width_0_height_0__pin_7_upper ) , - .right_bottom_grid_pin_9_ ( grid_io_bottom_0_top_width_0_height_0__pin_9_upper ) , - .right_bottom_grid_pin_11_ ( grid_io_bottom_0_top_width_0_height_0__pin_11_upper ) , - .ccff_head ( grid_io_bottom_0_ccff_tail ) , - .chany_top_out ( sb_0__0__0_chany_top_out ) , - .chanx_right_out ( sb_0__0__0_chanx_right_out ) , - .ccff_tail ( ccff_tail ) ) ; -sb_0__1_ sb_0__1_ ( .prog_clk ( prog_clk__FEEDTHRU_4 ) , - .chany_top_in ( cby_0__1__1_chany_bottom_out ) , - .top_left_grid_pin_1_ ( grid_io_left_1_right_width_0_height_0__pin_1_lower ) , - .chanx_right_in ( cbx_1__1__0_chanx_left_out ) , - .right_bottom_grid_pin_34_ ( grid_clb_0_top_width_0_height_0__pin_34_upper ) , - .right_bottom_grid_pin_35_ ( grid_clb_0_top_width_0_height_0__pin_35_upper ) , - .right_bottom_grid_pin_36_ ( grid_clb_0_top_width_0_height_0__pin_36_upper ) , - .right_bottom_grid_pin_37_ ( grid_clb_0_top_width_0_height_0__pin_37_upper ) , - .right_bottom_grid_pin_38_ ( grid_clb_0_top_width_0_height_0__pin_38_upper ) , - .right_bottom_grid_pin_39_ ( grid_clb_0_top_width_0_height_0__pin_39_upper ) , - .right_bottom_grid_pin_40_ ( grid_clb_0_top_width_0_height_0__pin_40_upper ) , - .right_bottom_grid_pin_41_ ( grid_clb_0_top_width_0_height_0__pin_41_upper ) , - .chany_bottom_in ( cby_0__1__0_chany_top_out ) , - .bottom_left_grid_pin_1_ ( grid_io_left_0_right_width_0_height_0__pin_1_upper ) , - .ccff_head ( cbx_1__1__0_ccff_tail ) , - .chany_top_out ( sb_0__1__0_chany_top_out ) , - .chanx_right_out ( sb_0__1__0_chanx_right_out ) , - .chany_bottom_out ( sb_0__1__0_chany_bottom_out ) , - .ccff_tail ( sb_0__1__0_ccff_tail ) , - .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_5 ) ) ; -sb_0__2_ sb_0__2_ ( .prog_clk ( prog_clk__FEEDTHRU_7 ) , - .chanx_right_in ( cbx_1__2__0_chanx_left_out ) , - .right_top_grid_pin_1_ ( grid_io_top_0_bottom_width_0_height_0__pin_1_upper ) , - .right_bottom_grid_pin_34_ ( grid_clb_1_top_width_0_height_0__pin_34_upper ) , - .right_bottom_grid_pin_35_ ( grid_clb_1_top_width_0_height_0__pin_35_upper ) , - .right_bottom_grid_pin_36_ ( grid_clb_1_top_width_0_height_0__pin_36_upper ) , - .right_bottom_grid_pin_37_ ( grid_clb_1_top_width_0_height_0__pin_37_upper ) , - .right_bottom_grid_pin_38_ ( grid_clb_1_top_width_0_height_0__pin_38_upper ) , - .right_bottom_grid_pin_39_ ( grid_clb_1_top_width_0_height_0__pin_39_upper ) , - .right_bottom_grid_pin_40_ ( grid_clb_1_top_width_0_height_0__pin_40_upper ) , - .right_bottom_grid_pin_41_ ( grid_clb_1_top_width_0_height_0__pin_41_upper ) , - .chany_bottom_in ( cby_0__1__1_chany_top_out ) , - .bottom_left_grid_pin_1_ ( grid_io_left_1_right_width_0_height_0__pin_1_upper ) , - .ccff_head ( grid_io_top_0_ccff_tail ) , - .chanx_right_out ( sb_0__2__0_chanx_right_out ) , - .chany_bottom_out ( sb_0__2__0_chany_bottom_out ) , - .ccff_tail ( sb_0__2__0_ccff_tail ) , .SC_IN_TOP ( sc_head ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_30 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_31 ) , .SC_OUT_BOT ( scff_Wires_0_ ) ) ; -sb_1__0_ sb_1__0_ ( .prog_clk ( prog_clk ) , - .chany_top_in ( cby_1__1__0_chany_bottom_out ) , - .top_left_grid_pin_42_ ( grid_clb_0_right_width_0_height_0__pin_42_lower ) , - .top_left_grid_pin_43_ ( grid_clb_0_right_width_0_height_0__pin_43_lower ) , - .top_left_grid_pin_44_ ( grid_clb_0_right_width_0_height_0__pin_44_lower ) , - .top_left_grid_pin_45_ ( grid_clb_0_right_width_0_height_0__pin_45_lower ) , - .top_left_grid_pin_46_ ( grid_clb_0_right_width_0_height_0__pin_46_lower ) , - .top_left_grid_pin_47_ ( grid_clb_0_right_width_0_height_0__pin_47_lower ) , - .top_left_grid_pin_48_ ( grid_clb_0_right_width_0_height_0__pin_48_lower ) , - .top_left_grid_pin_49_ ( grid_clb_0_right_width_0_height_0__pin_49_lower ) , - .chanx_right_in ( cbx_1__0__1_chanx_left_out ) , - .right_bottom_grid_pin_1_ ( grid_io_bottom_1_top_width_0_height_0__pin_1_upper ) , - .right_bottom_grid_pin_3_ ( grid_io_bottom_1_top_width_0_height_0__pin_3_upper ) , - .right_bottom_grid_pin_5_ ( grid_io_bottom_1_top_width_0_height_0__pin_5_upper ) , - .right_bottom_grid_pin_7_ ( grid_io_bottom_1_top_width_0_height_0__pin_7_upper ) , - .right_bottom_grid_pin_9_ ( grid_io_bottom_1_top_width_0_height_0__pin_9_upper ) , - .right_bottom_grid_pin_11_ ( grid_io_bottom_1_top_width_0_height_0__pin_11_upper ) , - .chanx_left_in ( cbx_1__0__0_chanx_right_out ) , - .left_bottom_grid_pin_1_ ( grid_io_bottom_0_top_width_0_height_0__pin_1_lower ) , - .left_bottom_grid_pin_3_ ( grid_io_bottom_0_top_width_0_height_0__pin_3_lower ) , - .left_bottom_grid_pin_5_ ( grid_io_bottom_0_top_width_0_height_0__pin_5_lower ) , - .left_bottom_grid_pin_7_ ( grid_io_bottom_0_top_width_0_height_0__pin_7_lower ) , - .left_bottom_grid_pin_9_ ( grid_io_bottom_0_top_width_0_height_0__pin_9_lower ) , - .left_bottom_grid_pin_11_ ( grid_io_bottom_0_top_width_0_height_0__pin_11_lower ) , - .ccff_head ( grid_io_bottom_1_ccff_tail ) , - .chany_top_out ( sb_1__0__0_chany_top_out ) , - .chanx_right_out ( sb_1__0__0_chanx_right_out ) , - .chanx_left_out ( sb_1__0__0_chanx_left_out ) , - .ccff_tail ( sb_1__0__0_ccff_tail ) , .SC_IN_TOP ( scff_Wires_6_ ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_32 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_33 ) , .SC_OUT_BOT ( scff_Wires_7_ ) , - .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_1 ) , - .prog_clk__FEEDTHRU_2 ( prog_clk__FEEDTHRU_8 ) ) ; -sb_1__1_ sb_1__1_ ( - .prog_clk ( { ctsbuf_net_2123 } ) , - .chany_top_in ( cby_1__1__1_chany_bottom_out ) , - .top_left_grid_pin_42_ ( grid_clb_1_right_width_0_height_0__pin_42_lower ) , - .top_left_grid_pin_43_ ( grid_clb_1_right_width_0_height_0__pin_43_lower ) , - .top_left_grid_pin_44_ ( grid_clb_1_right_width_0_height_0__pin_44_lower ) , - .top_left_grid_pin_45_ ( grid_clb_1_right_width_0_height_0__pin_45_lower ) , - .top_left_grid_pin_46_ ( grid_clb_1_right_width_0_height_0__pin_46_lower ) , - .top_left_grid_pin_47_ ( grid_clb_1_right_width_0_height_0__pin_47_lower ) , - .top_left_grid_pin_48_ ( grid_clb_1_right_width_0_height_0__pin_48_lower ) , - .top_left_grid_pin_49_ ( grid_clb_1_right_width_0_height_0__pin_49_lower ) , - .chanx_right_in ( cbx_1__1__1_chanx_left_out ) , - .right_bottom_grid_pin_34_ ( grid_clb_2_top_width_0_height_0__pin_34_upper ) , - .right_bottom_grid_pin_35_ ( grid_clb_2_top_width_0_height_0__pin_35_upper ) , - .right_bottom_grid_pin_36_ ( grid_clb_2_top_width_0_height_0__pin_36_upper ) , - .right_bottom_grid_pin_37_ ( grid_clb_2_top_width_0_height_0__pin_37_upper ) , - .right_bottom_grid_pin_38_ ( grid_clb_2_top_width_0_height_0__pin_38_upper ) , - .right_bottom_grid_pin_39_ ( grid_clb_2_top_width_0_height_0__pin_39_upper ) , - .right_bottom_grid_pin_40_ ( grid_clb_2_top_width_0_height_0__pin_40_upper ) , - .right_bottom_grid_pin_41_ ( grid_clb_2_top_width_0_height_0__pin_41_upper ) , - .chany_bottom_in ( cby_1__1__0_chany_top_out ) , - .bottom_left_grid_pin_42_ ( grid_clb_0_right_width_0_height_0__pin_42_upper ) , - .bottom_left_grid_pin_43_ ( grid_clb_0_right_width_0_height_0__pin_43_upper ) , - .bottom_left_grid_pin_44_ ( grid_clb_0_right_width_0_height_0__pin_44_upper ) , - .bottom_left_grid_pin_45_ ( grid_clb_0_right_width_0_height_0__pin_45_upper ) , - .bottom_left_grid_pin_46_ ( grid_clb_0_right_width_0_height_0__pin_46_upper ) , - .bottom_left_grid_pin_47_ ( grid_clb_0_right_width_0_height_0__pin_47_upper ) , - .bottom_left_grid_pin_48_ ( grid_clb_0_right_width_0_height_0__pin_48_upper ) , - .bottom_left_grid_pin_49_ ( grid_clb_0_right_width_0_height_0__pin_49_upper ) , - .chanx_left_in ( cbx_1__1__0_chanx_right_out ) , - .left_bottom_grid_pin_34_ ( grid_clb_0_top_width_0_height_0__pin_34_lower ) , - .left_bottom_grid_pin_35_ ( grid_clb_0_top_width_0_height_0__pin_35_lower ) , - .left_bottom_grid_pin_36_ ( grid_clb_0_top_width_0_height_0__pin_36_lower ) , - .left_bottom_grid_pin_37_ ( grid_clb_0_top_width_0_height_0__pin_37_lower ) , - .left_bottom_grid_pin_38_ ( grid_clb_0_top_width_0_height_0__pin_38_lower ) , - .left_bottom_grid_pin_39_ ( grid_clb_0_top_width_0_height_0__pin_39_lower ) , - .left_bottom_grid_pin_40_ ( grid_clb_0_top_width_0_height_0__pin_40_lower ) , - .left_bottom_grid_pin_41_ ( grid_clb_0_top_width_0_height_0__pin_41_lower ) , - .ccff_head ( cbx_1__1__1_ccff_tail ) , - .chany_top_out ( sb_1__1__0_chany_top_out ) , - .chanx_right_out ( sb_1__1__0_chanx_right_out ) , - .chany_bottom_out ( sb_1__1__0_chany_bottom_out ) , - .chanx_left_out ( sb_1__1__0_chanx_left_out ) , - .ccff_tail ( sb_1__1__0_ccff_tail ) , - .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_10 ) , - .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_5 ) , - .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_6 ) , - .clk__FEEDTHRU_0 ( clk__FEEDTHRU_5 ) , - .clk__FEEDTHRU_1 ( clk__FEEDTHRU_6 ) , - .grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_0_bottom_width_0_height_0__pin_50_ ) , - .grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) ) ; -sb_1__2_ sb_1__2_ ( .prog_clk ( prog_clk__FEEDTHRU_11 ) , - .chanx_right_in ( cbx_1__2__1_chanx_left_out ) , - .right_top_grid_pin_1_ ( grid_io_top_1_bottom_width_0_height_0__pin_1_upper ) , - .right_bottom_grid_pin_34_ ( grid_clb_3_top_width_0_height_0__pin_34_upper ) , - .right_bottom_grid_pin_35_ ( grid_clb_3_top_width_0_height_0__pin_35_upper ) , - .right_bottom_grid_pin_36_ ( grid_clb_3_top_width_0_height_0__pin_36_upper ) , - .right_bottom_grid_pin_37_ ( grid_clb_3_top_width_0_height_0__pin_37_upper ) , - .right_bottom_grid_pin_38_ ( grid_clb_3_top_width_0_height_0__pin_38_upper ) , - .right_bottom_grid_pin_39_ ( grid_clb_3_top_width_0_height_0__pin_39_upper ) , - .right_bottom_grid_pin_40_ ( grid_clb_3_top_width_0_height_0__pin_40_upper ) , - .right_bottom_grid_pin_41_ ( grid_clb_3_top_width_0_height_0__pin_41_upper ) , - .chany_bottom_in ( cby_1__1__1_chany_top_out ) , - .bottom_left_grid_pin_42_ ( grid_clb_1_right_width_0_height_0__pin_42_upper ) , - .bottom_left_grid_pin_43_ ( grid_clb_1_right_width_0_height_0__pin_43_upper ) , - .bottom_left_grid_pin_44_ ( grid_clb_1_right_width_0_height_0__pin_44_upper ) , - .bottom_left_grid_pin_45_ ( grid_clb_1_right_width_0_height_0__pin_45_upper ) , - .bottom_left_grid_pin_46_ ( grid_clb_1_right_width_0_height_0__pin_46_upper ) , - .bottom_left_grid_pin_47_ ( grid_clb_1_right_width_0_height_0__pin_47_upper ) , - .bottom_left_grid_pin_48_ ( grid_clb_1_right_width_0_height_0__pin_48_upper ) , - .bottom_left_grid_pin_49_ ( grid_clb_1_right_width_0_height_0__pin_49_upper ) , - .chanx_left_in ( cbx_1__2__0_chanx_right_out ) , - .left_top_grid_pin_1_ ( grid_io_top_0_bottom_width_0_height_0__pin_1_lower ) , - .left_bottom_grid_pin_34_ ( grid_clb_1_top_width_0_height_0__pin_34_lower ) , - .left_bottom_grid_pin_35_ ( grid_clb_1_top_width_0_height_0__pin_35_lower ) , - .left_bottom_grid_pin_36_ ( grid_clb_1_top_width_0_height_0__pin_36_lower ) , - .left_bottom_grid_pin_37_ ( grid_clb_1_top_width_0_height_0__pin_37_lower ) , - .left_bottom_grid_pin_38_ ( grid_clb_1_top_width_0_height_0__pin_38_lower ) , - .left_bottom_grid_pin_39_ ( grid_clb_1_top_width_0_height_0__pin_39_lower ) , - .left_bottom_grid_pin_40_ ( grid_clb_1_top_width_0_height_0__pin_40_lower ) , - .left_bottom_grid_pin_41_ ( grid_clb_1_top_width_0_height_0__pin_41_lower ) , - .ccff_head ( grid_io_top_1_ccff_tail ) , - .chanx_right_out ( sb_1__2__0_chanx_right_out ) , - .chany_bottom_out ( sb_1__2__0_chany_bottom_out ) , - .chanx_left_out ( sb_1__2__0_chanx_left_out ) , - .ccff_tail ( sb_1__2__0_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_34 ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_35 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_36 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_37 ) , - .Test_en__FEEDTHRU_0 ( Test_en ) , - .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_4 ) , - .Test_en__FEEDTHRU_2 ( Test_en__FEEDTHRU_1 ) , .clk__FEEDTHRU_0 ( clk ) , - .clk__FEEDTHRU_1 ( clk__FEEDTHRU_4 ) , - .clk__FEEDTHRU_2 ( clk__FEEDTHRU_1 ) ) ; -sb_2__0_ sb_2__0_ ( - .prog_clk ( { ctsbuf_net_2729 } ) , - .chany_top_in ( cby_2__1__0_chany_bottom_out ) , - .top_left_grid_pin_42_ ( grid_clb_2_right_width_0_height_0__pin_42_lower ) , - .top_left_grid_pin_43_ ( grid_clb_2_right_width_0_height_0__pin_43_lower ) , - .top_left_grid_pin_44_ ( grid_clb_2_right_width_0_height_0__pin_44_lower ) , - .top_left_grid_pin_45_ ( grid_clb_2_right_width_0_height_0__pin_45_lower ) , - .top_left_grid_pin_46_ ( grid_clb_2_right_width_0_height_0__pin_46_lower ) , - .top_left_grid_pin_47_ ( grid_clb_2_right_width_0_height_0__pin_47_lower ) , - .top_left_grid_pin_48_ ( grid_clb_2_right_width_0_height_0__pin_48_lower ) , - .top_left_grid_pin_49_ ( grid_clb_2_right_width_0_height_0__pin_49_lower ) , - .top_right_grid_pin_1_ ( grid_io_right_0_left_width_0_height_0__pin_1_lower ) , - .chanx_left_in ( cbx_1__0__1_chanx_right_out ) , - .left_bottom_grid_pin_1_ ( grid_io_bottom_1_top_width_0_height_0__pin_1_lower ) , - .left_bottom_grid_pin_3_ ( grid_io_bottom_1_top_width_0_height_0__pin_3_lower ) , - .left_bottom_grid_pin_5_ ( grid_io_bottom_1_top_width_0_height_0__pin_5_lower ) , - .left_bottom_grid_pin_7_ ( grid_io_bottom_1_top_width_0_height_0__pin_7_lower ) , - .left_bottom_grid_pin_9_ ( grid_io_bottom_1_top_width_0_height_0__pin_9_lower ) , - .left_bottom_grid_pin_11_ ( grid_io_bottom_1_top_width_0_height_0__pin_11_lower ) , - .ccff_head ( grid_io_right_0_ccff_tail ) , - .chany_top_out ( sb_2__0__0_chany_top_out ) , - .chanx_left_out ( sb_2__0__0_chanx_left_out ) , - .ccff_tail ( sb_2__0__0_ccff_tail ) ) ; -sb_2__1_ sb_2__1_ ( .prog_clk ( prog_clk__FEEDTHRU_18 ) , - .chany_top_in ( cby_2__1__1_chany_bottom_out ) , - .top_left_grid_pin_42_ ( grid_clb_3_right_width_0_height_0__pin_42_lower ) , - .top_left_grid_pin_43_ ( grid_clb_3_right_width_0_height_0__pin_43_lower ) , - .top_left_grid_pin_44_ ( grid_clb_3_right_width_0_height_0__pin_44_lower ) , - .top_left_grid_pin_45_ ( grid_clb_3_right_width_0_height_0__pin_45_lower ) , - .top_left_grid_pin_46_ ( grid_clb_3_right_width_0_height_0__pin_46_lower ) , - .top_left_grid_pin_47_ ( grid_clb_3_right_width_0_height_0__pin_47_lower ) , - .top_left_grid_pin_48_ ( grid_clb_3_right_width_0_height_0__pin_48_lower ) , - .top_left_grid_pin_49_ ( grid_clb_3_right_width_0_height_0__pin_49_lower ) , - .top_right_grid_pin_1_ ( grid_io_right_1_left_width_0_height_0__pin_1_lower ) , - .chany_bottom_in ( cby_2__1__0_chany_top_out ) , - .bottom_right_grid_pin_1_ ( grid_io_right_0_left_width_0_height_0__pin_1_upper ) , - .bottom_left_grid_pin_42_ ( grid_clb_2_right_width_0_height_0__pin_42_upper ) , - .bottom_left_grid_pin_43_ ( grid_clb_2_right_width_0_height_0__pin_43_upper ) , - .bottom_left_grid_pin_44_ ( grid_clb_2_right_width_0_height_0__pin_44_upper ) , - .bottom_left_grid_pin_45_ ( grid_clb_2_right_width_0_height_0__pin_45_upper ) , - .bottom_left_grid_pin_46_ ( grid_clb_2_right_width_0_height_0__pin_46_upper ) , - .bottom_left_grid_pin_47_ ( grid_clb_2_right_width_0_height_0__pin_47_upper ) , - .bottom_left_grid_pin_48_ ( grid_clb_2_right_width_0_height_0__pin_48_upper ) , - .bottom_left_grid_pin_49_ ( grid_clb_2_right_width_0_height_0__pin_49_upper ) , - .chanx_left_in ( cbx_1__1__1_chanx_right_out ) , - .left_bottom_grid_pin_34_ ( grid_clb_2_top_width_0_height_0__pin_34_lower ) , - .left_bottom_grid_pin_35_ ( grid_clb_2_top_width_0_height_0__pin_35_lower ) , - .left_bottom_grid_pin_36_ ( grid_clb_2_top_width_0_height_0__pin_36_lower ) , - .left_bottom_grid_pin_37_ ( grid_clb_2_top_width_0_height_0__pin_37_lower ) , - .left_bottom_grid_pin_38_ ( grid_clb_2_top_width_0_height_0__pin_38_lower ) , - .left_bottom_grid_pin_39_ ( grid_clb_2_top_width_0_height_0__pin_39_lower ) , - .left_bottom_grid_pin_40_ ( grid_clb_2_top_width_0_height_0__pin_40_lower ) , - .left_bottom_grid_pin_41_ ( grid_clb_2_top_width_0_height_0__pin_41_lower ) , - .ccff_head ( grid_io_right_1_ccff_tail ) , - .chany_top_out ( sb_2__1__0_chany_top_out ) , - .chany_bottom_out ( sb_2__1__0_chany_bottom_out ) , - .chanx_left_out ( sb_2__1__0_chanx_left_out ) , - .ccff_tail ( sb_2__1__0_ccff_tail ) , - .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_2 ) , - .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_3 ) , - .clk__FEEDTHRU_0 ( clk__FEEDTHRU_2 ) , - .clk__FEEDTHRU_1 ( clk__FEEDTHRU_3 ) ) ; -sb_2__2_ sb_2__2_ ( .prog_clk ( prog_clk__FEEDTHRU_14 ) , - .chany_bottom_in ( cby_2__1__1_chany_top_out ) , - .bottom_right_grid_pin_1_ ( grid_io_right_1_left_width_0_height_0__pin_1_upper ) , - .bottom_left_grid_pin_42_ ( grid_clb_3_right_width_0_height_0__pin_42_upper ) , - .bottom_left_grid_pin_43_ ( grid_clb_3_right_width_0_height_0__pin_43_upper ) , - .bottom_left_grid_pin_44_ ( grid_clb_3_right_width_0_height_0__pin_44_upper ) , - .bottom_left_grid_pin_45_ ( grid_clb_3_right_width_0_height_0__pin_45_upper ) , - .bottom_left_grid_pin_46_ ( grid_clb_3_right_width_0_height_0__pin_46_upper ) , - .bottom_left_grid_pin_47_ ( grid_clb_3_right_width_0_height_0__pin_47_upper ) , - .bottom_left_grid_pin_48_ ( grid_clb_3_right_width_0_height_0__pin_48_upper ) , - .bottom_left_grid_pin_49_ ( grid_clb_3_right_width_0_height_0__pin_49_upper ) , - .chanx_left_in ( cbx_1__2__1_chanx_right_out ) , - .left_top_grid_pin_1_ ( grid_io_top_1_bottom_width_0_height_0__pin_1_lower ) , - .left_bottom_grid_pin_34_ ( grid_clb_3_top_width_0_height_0__pin_34_lower ) , - .left_bottom_grid_pin_35_ ( grid_clb_3_top_width_0_height_0__pin_35_lower ) , - .left_bottom_grid_pin_36_ ( grid_clb_3_top_width_0_height_0__pin_36_lower ) , - .left_bottom_grid_pin_37_ ( grid_clb_3_top_width_0_height_0__pin_37_lower ) , - .left_bottom_grid_pin_38_ ( grid_clb_3_top_width_0_height_0__pin_38_lower ) , - .left_bottom_grid_pin_39_ ( grid_clb_3_top_width_0_height_0__pin_39_lower ) , - .left_bottom_grid_pin_40_ ( grid_clb_3_top_width_0_height_0__pin_40_lower ) , - .left_bottom_grid_pin_41_ ( grid_clb_3_top_width_0_height_0__pin_41_lower ) , - .ccff_head ( ccff_head ) , - .chany_bottom_out ( sb_2__2__0_chany_bottom_out ) , - .chanx_left_out ( sb_2__2__0_chanx_left_out ) , - .ccff_tail ( sb_2__2__0_ccff_tail ) , .SC_IN_TOP ( scff_Wires_12_ ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_38 ) , .SC_OUT_TOP ( sc_tail ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_39 ) ) ; -cbx_1__0_ cbx_1__0_ ( - .prog_clk ( { ctsbuf_net_2426 } ) , - .chanx_left_in ( sb_0__0__0_chanx_right_out ) , - .chanx_right_in ( sb_1__0__0_chanx_left_out ) , - .ccff_head ( sb_1__0__0_ccff_tail ) , - .chanx_left_out ( cbx_1__0__0_chanx_left_out ) , - .chanx_right_out ( cbx_1__0__0_chanx_right_out ) , - .bottom_grid_pin_0_ ( cbx_1__0__0_bottom_grid_pin_0_ ) , - .bottom_grid_pin_2_ ( cbx_1__0__0_bottom_grid_pin_2_ ) , - .bottom_grid_pin_4_ ( cbx_1__0__0_bottom_grid_pin_4_ ) , - .bottom_grid_pin_6_ ( cbx_1__0__0_bottom_grid_pin_6_ ) , - .bottom_grid_pin_8_ ( cbx_1__0__0_bottom_grid_pin_8_ ) , - .bottom_grid_pin_10_ ( cbx_1__0__0_bottom_grid_pin_10_ ) , - .ccff_tail ( grid_io_bottom_0_ccff_tail ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[4:9] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[4:9] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[4:9] ) , - .top_width_0_height_0__pin_0_ ( cbx_1__0__0_bottom_grid_pin_0_ ) , - .top_width_0_height_0__pin_2_ ( cbx_1__0__0_bottom_grid_pin_2_ ) , - .top_width_0_height_0__pin_4_ ( cbx_1__0__0_bottom_grid_pin_4_ ) , - .top_width_0_height_0__pin_6_ ( cbx_1__0__0_bottom_grid_pin_6_ ) , - .top_width_0_height_0__pin_8_ ( cbx_1__0__0_bottom_grid_pin_8_ ) , - .top_width_0_height_0__pin_10_ ( cbx_1__0__0_bottom_grid_pin_10_ ) , - .top_width_0_height_0__pin_1_upper ( grid_io_bottom_0_top_width_0_height_0__pin_1_upper ) , - .top_width_0_height_0__pin_1_lower ( grid_io_bottom_0_top_width_0_height_0__pin_1_lower ) , - .top_width_0_height_0__pin_3_upper ( grid_io_bottom_0_top_width_0_height_0__pin_3_upper ) , - .top_width_0_height_0__pin_3_lower ( grid_io_bottom_0_top_width_0_height_0__pin_3_lower ) , - .top_width_0_height_0__pin_5_upper ( grid_io_bottom_0_top_width_0_height_0__pin_5_upper ) , - .top_width_0_height_0__pin_5_lower ( grid_io_bottom_0_top_width_0_height_0__pin_5_lower ) , - .top_width_0_height_0__pin_7_upper ( grid_io_bottom_0_top_width_0_height_0__pin_7_upper ) , - .top_width_0_height_0__pin_7_lower ( grid_io_bottom_0_top_width_0_height_0__pin_7_lower ) , - .top_width_0_height_0__pin_9_upper ( grid_io_bottom_0_top_width_0_height_0__pin_9_upper ) , - .top_width_0_height_0__pin_9_lower ( grid_io_bottom_0_top_width_0_height_0__pin_9_lower ) , - .top_width_0_height_0__pin_11_upper ( grid_io_bottom_0_top_width_0_height_0__pin_11_upper ) , - .top_width_0_height_0__pin_11_lower ( grid_io_bottom_0_top_width_0_height_0__pin_11_lower ) , - .SC_IN_TOP ( scff_Wires_5_ ) , .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_40 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_41 ) , .SC_OUT_BOT ( scff_Wires_6_ ) , - .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_2 ) ) ; -cbx_1__0_ cbx_2__0_ ( - .prog_clk ( { ctsbuf_net_2729 } ) , - .chanx_left_in ( sb_1__0__0_chanx_right_out ) , - .chanx_right_in ( sb_2__0__0_chanx_left_out ) , - .ccff_head ( sb_2__0__0_ccff_tail ) , - .chanx_left_out ( cbx_1__0__1_chanx_left_out ) , - .chanx_right_out ( cbx_1__0__1_chanx_right_out ) , - .bottom_grid_pin_0_ ( cbx_1__0__1_bottom_grid_pin_0_ ) , - .bottom_grid_pin_2_ ( cbx_1__0__1_bottom_grid_pin_2_ ) , - .bottom_grid_pin_4_ ( cbx_1__0__1_bottom_grid_pin_4_ ) , - .bottom_grid_pin_6_ ( cbx_1__0__1_bottom_grid_pin_6_ ) , - .bottom_grid_pin_8_ ( cbx_1__0__1_bottom_grid_pin_8_ ) , - .bottom_grid_pin_10_ ( cbx_1__0__1_bottom_grid_pin_10_ ) , - .ccff_tail ( grid_io_bottom_1_ccff_tail ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[10:15] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[10:15] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[10:15] ) , - .top_width_0_height_0__pin_0_ ( cbx_1__0__1_bottom_grid_pin_0_ ) , - .top_width_0_height_0__pin_2_ ( cbx_1__0__1_bottom_grid_pin_2_ ) , - .top_width_0_height_0__pin_4_ ( cbx_1__0__1_bottom_grid_pin_4_ ) , - .top_width_0_height_0__pin_6_ ( cbx_1__0__1_bottom_grid_pin_6_ ) , - .top_width_0_height_0__pin_8_ ( cbx_1__0__1_bottom_grid_pin_8_ ) , - .top_width_0_height_0__pin_10_ ( cbx_1__0__1_bottom_grid_pin_10_ ) , - .top_width_0_height_0__pin_1_upper ( grid_io_bottom_1_top_width_0_height_0__pin_1_upper ) , - .top_width_0_height_0__pin_1_lower ( grid_io_bottom_1_top_width_0_height_0__pin_1_lower ) , - .top_width_0_height_0__pin_3_upper ( grid_io_bottom_1_top_width_0_height_0__pin_3_upper ) , - .top_width_0_height_0__pin_3_lower ( grid_io_bottom_1_top_width_0_height_0__pin_3_lower ) , - .top_width_0_height_0__pin_5_upper ( grid_io_bottom_1_top_width_0_height_0__pin_5_upper ) , - .top_width_0_height_0__pin_5_lower ( grid_io_bottom_1_top_width_0_height_0__pin_5_lower ) , - .top_width_0_height_0__pin_7_upper ( grid_io_bottom_1_top_width_0_height_0__pin_7_upper ) , - .top_width_0_height_0__pin_7_lower ( grid_io_bottom_1_top_width_0_height_0__pin_7_lower ) , - .top_width_0_height_0__pin_9_upper ( grid_io_bottom_1_top_width_0_height_0__pin_9_upper ) , - .top_width_0_height_0__pin_9_lower ( grid_io_bottom_1_top_width_0_height_0__pin_9_lower ) , - .top_width_0_height_0__pin_11_upper ( grid_io_bottom_1_top_width_0_height_0__pin_11_upper ) , - .top_width_0_height_0__pin_11_lower ( grid_io_bottom_1_top_width_0_height_0__pin_11_lower ) , - .SC_IN_TOP ( scff_Wires_7_ ) , .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_42 ) , - .SC_OUT_TOP ( scff_Wires_8_ ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_43 ) , - .prog_clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_44 } ) ) ; -cbx_1__1_ cbx_1__1_ ( .prog_clk ( prog_clk__FEEDTHRU_3 ) , - .chanx_left_in ( sb_0__1__0_chanx_right_out ) , - .chanx_right_in ( sb_1__1__0_chanx_left_out ) , - .ccff_head ( sb_1__1__0_ccff_tail ) , - .chanx_left_out ( cbx_1__1__0_chanx_left_out ) , - .chanx_right_out ( cbx_1__1__0_chanx_right_out ) , - .bottom_grid_pin_0_ ( cbx_1__1__0_bottom_grid_pin_0_ ) , - .bottom_grid_pin_1_ ( cbx_1__1__0_bottom_grid_pin_1_ ) , - .bottom_grid_pin_2_ ( cbx_1__1__0_bottom_grid_pin_2_ ) , - .bottom_grid_pin_3_ ( cbx_1__1__0_bottom_grid_pin_3_ ) , - .bottom_grid_pin_4_ ( cbx_1__1__0_bottom_grid_pin_4_ ) , - .bottom_grid_pin_5_ ( cbx_1__1__0_bottom_grid_pin_5_ ) , - .bottom_grid_pin_6_ ( cbx_1__1__0_bottom_grid_pin_6_ ) , - .bottom_grid_pin_7_ ( cbx_1__1__0_bottom_grid_pin_7_ ) , - .bottom_grid_pin_8_ ( cbx_1__1__0_bottom_grid_pin_8_ ) , - .bottom_grid_pin_9_ ( cbx_1__1__0_bottom_grid_pin_9_ ) , - .bottom_grid_pin_10_ ( cbx_1__1__0_bottom_grid_pin_10_ ) , - .bottom_grid_pin_11_ ( cbx_1__1__0_bottom_grid_pin_11_ ) , - .bottom_grid_pin_12_ ( cbx_1__1__0_bottom_grid_pin_12_ ) , - .bottom_grid_pin_13_ ( cbx_1__1__0_bottom_grid_pin_13_ ) , - .bottom_grid_pin_14_ ( cbx_1__1__0_bottom_grid_pin_14_ ) , - .bottom_grid_pin_15_ ( cbx_1__1__0_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__0_ccff_tail ) , .SC_IN_TOP ( scff_Wires_2_ ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_45 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_46 ) , .SC_OUT_BOT ( scff_Wires_3_ ) , - .prog_clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_47 } ) ) ; -cbx_1__1_ cbx_2__1_ ( .prog_clk ( prog_clk__FEEDTHRU_17 ) , - .chanx_left_in ( sb_1__1__0_chanx_right_out ) , - .chanx_right_in ( sb_2__1__0_chanx_left_out ) , - .ccff_head ( sb_2__1__0_ccff_tail ) , - .chanx_left_out ( cbx_1__1__1_chanx_left_out ) , - .chanx_right_out ( cbx_1__1__1_chanx_right_out ) , - .bottom_grid_pin_0_ ( cbx_1__1__1_bottom_grid_pin_0_ ) , - .bottom_grid_pin_1_ ( cbx_1__1__1_bottom_grid_pin_1_ ) , - .bottom_grid_pin_2_ ( cbx_1__1__1_bottom_grid_pin_2_ ) , - .bottom_grid_pin_3_ ( cbx_1__1__1_bottom_grid_pin_3_ ) , - .bottom_grid_pin_4_ ( cbx_1__1__1_bottom_grid_pin_4_ ) , - .bottom_grid_pin_5_ ( cbx_1__1__1_bottom_grid_pin_5_ ) , - .bottom_grid_pin_6_ ( cbx_1__1__1_bottom_grid_pin_6_ ) , - .bottom_grid_pin_7_ ( cbx_1__1__1_bottom_grid_pin_7_ ) , - .bottom_grid_pin_8_ ( cbx_1__1__1_bottom_grid_pin_8_ ) , - .bottom_grid_pin_9_ ( cbx_1__1__1_bottom_grid_pin_9_ ) , - .bottom_grid_pin_10_ ( cbx_1__1__1_bottom_grid_pin_10_ ) , - .bottom_grid_pin_11_ ( cbx_1__1__1_bottom_grid_pin_11_ ) , - .bottom_grid_pin_12_ ( cbx_1__1__1_bottom_grid_pin_12_ ) , - .bottom_grid_pin_13_ ( cbx_1__1__1_bottom_grid_pin_13_ ) , - .bottom_grid_pin_14_ ( cbx_1__1__1_bottom_grid_pin_14_ ) , - .bottom_grid_pin_15_ ( cbx_1__1__1_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__1_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_48 ) , .SC_IN_BOT ( scff_Wires_9_ ) , - .SC_OUT_TOP ( scff_Wires_10_ ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_49 ) , - .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_18 ) ) ; -cbx_1__2_ cbx_1__2_ ( .prog_clk ( prog_clk__FEEDTHRU_6 ) , - .chanx_left_in ( sb_0__2__0_chanx_right_out ) , - .chanx_right_in ( sb_1__2__0_chanx_left_out ) , - .ccff_head ( sb_1__2__0_ccff_tail ) , - .chanx_left_out ( cbx_1__2__0_chanx_left_out ) , - .chanx_right_out ( cbx_1__2__0_chanx_right_out ) , - .top_grid_pin_0_ ( cbx_1__2__0_top_grid_pin_0_ ) , - .bottom_grid_pin_0_ ( cbx_1__2__0_bottom_grid_pin_0_ ) , - .bottom_grid_pin_1_ ( cbx_1__2__0_bottom_grid_pin_1_ ) , - .bottom_grid_pin_2_ ( cbx_1__2__0_bottom_grid_pin_2_ ) , - .bottom_grid_pin_3_ ( cbx_1__2__0_bottom_grid_pin_3_ ) , - .bottom_grid_pin_4_ ( cbx_1__2__0_bottom_grid_pin_4_ ) , - .bottom_grid_pin_5_ ( cbx_1__2__0_bottom_grid_pin_5_ ) , - .bottom_grid_pin_6_ ( cbx_1__2__0_bottom_grid_pin_6_ ) , - .bottom_grid_pin_7_ ( cbx_1__2__0_bottom_grid_pin_7_ ) , - .bottom_grid_pin_8_ ( cbx_1__2__0_bottom_grid_pin_8_ ) , - .bottom_grid_pin_9_ ( cbx_1__2__0_bottom_grid_pin_9_ ) , - .bottom_grid_pin_10_ ( cbx_1__2__0_bottom_grid_pin_10_ ) , - .bottom_grid_pin_11_ ( cbx_1__2__0_bottom_grid_pin_11_ ) , - .bottom_grid_pin_12_ ( cbx_1__2__0_bottom_grid_pin_12_ ) , - .bottom_grid_pin_13_ ( cbx_1__2__0_bottom_grid_pin_13_ ) , - .bottom_grid_pin_14_ ( cbx_1__2__0_bottom_grid_pin_14_ ) , - .bottom_grid_pin_15_ ( cbx_1__2__0_bottom_grid_pin_15_ ) , - .ccff_tail ( grid_io_top_0_ccff_tail ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , - .bottom_width_0_height_0__pin_0_ ( cbx_1__2__0_top_grid_pin_0_ ) , - .bottom_width_0_height_0__pin_1_upper ( grid_io_top_0_bottom_width_0_height_0__pin_1_upper ) , - .bottom_width_0_height_0__pin_1_lower ( grid_io_top_0_bottom_width_0_height_0__pin_1_lower ) , - .SC_IN_TOP ( scff_Wires_0_ ) , .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_50 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_51 ) , .SC_OUT_BOT ( scff_Wires_1_ ) , - .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_7 ) , - .prog_clk__FEEDTHRU_2 ( { SYNOPSYS_UNCONNECTED_52 } ) ) ; -cbx_1__2_ cbx_2__2_ ( .prog_clk ( prog_clk__FEEDTHRU_13 ) , - .chanx_left_in ( sb_1__2__0_chanx_right_out ) , - .chanx_right_in ( sb_2__2__0_chanx_left_out ) , - .ccff_head ( sb_2__2__0_ccff_tail ) , - .chanx_left_out ( cbx_1__2__1_chanx_left_out ) , - .chanx_right_out ( cbx_1__2__1_chanx_right_out ) , - .top_grid_pin_0_ ( cbx_1__2__1_top_grid_pin_0_ ) , - .bottom_grid_pin_0_ ( cbx_1__2__1_bottom_grid_pin_0_ ) , - .bottom_grid_pin_1_ ( cbx_1__2__1_bottom_grid_pin_1_ ) , - .bottom_grid_pin_2_ ( cbx_1__2__1_bottom_grid_pin_2_ ) , - .bottom_grid_pin_3_ ( cbx_1__2__1_bottom_grid_pin_3_ ) , - .bottom_grid_pin_4_ ( cbx_1__2__1_bottom_grid_pin_4_ ) , - .bottom_grid_pin_5_ ( cbx_1__2__1_bottom_grid_pin_5_ ) , - .bottom_grid_pin_6_ ( cbx_1__2__1_bottom_grid_pin_6_ ) , - .bottom_grid_pin_7_ ( cbx_1__2__1_bottom_grid_pin_7_ ) , - .bottom_grid_pin_8_ ( cbx_1__2__1_bottom_grid_pin_8_ ) , - .bottom_grid_pin_9_ ( cbx_1__2__1_bottom_grid_pin_9_ ) , - .bottom_grid_pin_10_ ( cbx_1__2__1_bottom_grid_pin_10_ ) , - .bottom_grid_pin_11_ ( cbx_1__2__1_bottom_grid_pin_11_ ) , - .bottom_grid_pin_12_ ( cbx_1__2__1_bottom_grid_pin_12_ ) , - .bottom_grid_pin_13_ ( cbx_1__2__1_bottom_grid_pin_13_ ) , - .bottom_grid_pin_14_ ( cbx_1__2__1_bottom_grid_pin_14_ ) , - .bottom_grid_pin_15_ ( cbx_1__2__1_bottom_grid_pin_15_ ) , - .ccff_tail ( grid_io_top_1_ccff_tail ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[1] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[1] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[1] ) , - .bottom_width_0_height_0__pin_0_ ( cbx_1__2__1_top_grid_pin_0_ ) , - .bottom_width_0_height_0__pin_1_upper ( grid_io_top_1_bottom_width_0_height_0__pin_1_upper ) , - .bottom_width_0_height_0__pin_1_lower ( grid_io_top_1_bottom_width_0_height_0__pin_1_lower ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_53 ) , .SC_IN_BOT ( scff_Wires_11_ ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_54 ) , .SC_OUT_BOT ( scff_Wires_12_ ) , - .prog_clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_55 } ) , - .prog_clk__FEEDTHRU_2 ( prog_clk__FEEDTHRU_14 ) ) ; -cby_0__1_ cby_0__1_ ( - .prog_clk ( { ctsbuf_net_1719 } ) , - .chany_bottom_in ( sb_0__0__0_chany_top_out ) , - .chany_top_in ( sb_0__1__0_chany_bottom_out ) , - .ccff_head ( sb_0__1__0_ccff_tail ) , - .chany_bottom_out ( cby_0__1__0_chany_bottom_out ) , - .chany_top_out ( cby_0__1__0_chany_top_out ) , - .left_grid_pin_0_ ( cby_0__1__0_left_grid_pin_0_ ) , - .ccff_tail ( grid_io_left_0_ccff_tail ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[16] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[16] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[16] ) , - .right_width_0_height_0__pin_0_ ( cby_0__1__0_left_grid_pin_0_ ) , - .right_width_0_height_0__pin_1_upper ( grid_io_left_0_right_width_0_height_0__pin_1_upper ) , - .right_width_0_height_0__pin_1_lower ( grid_io_left_0_right_width_0_height_0__pin_1_lower ) ) ; -cby_0__1_ cby_0__2_ ( .prog_clk ( prog_clk__FEEDTHRU_5 ) , - .chany_bottom_in ( sb_0__1__0_chany_top_out ) , - .chany_top_in ( sb_0__2__0_chany_bottom_out ) , - .ccff_head ( sb_0__2__0_ccff_tail ) , - .chany_bottom_out ( cby_0__1__1_chany_bottom_out ) , - .chany_top_out ( cby_0__1__1_chany_top_out ) , - .left_grid_pin_0_ ( cby_0__1__1_left_grid_pin_0_ ) , - .ccff_tail ( grid_io_left_1_ccff_tail ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[17] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[17] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[17] ) , - .right_width_0_height_0__pin_0_ ( cby_0__1__1_left_grid_pin_0_ ) , - .right_width_0_height_0__pin_1_upper ( grid_io_left_1_right_width_0_height_0__pin_1_upper ) , - .right_width_0_height_0__pin_1_lower ( grid_io_left_1_right_width_0_height_0__pin_1_lower ) ) ; -cby_1__1_ cby_1__1_ ( - .prog_clk ( { ctsbuf_net_2325 } ) , - .chany_bottom_in ( sb_1__0__0_chany_top_out ) , - .chany_top_in ( sb_1__1__0_chany_bottom_out ) , - .ccff_head ( grid_clb_0_ccff_tail ) , - .chany_bottom_out ( cby_1__1__0_chany_bottom_out ) , - .chany_top_out ( cby_1__1__0_chany_top_out ) , - .left_grid_pin_16_ ( cby_1__1__0_left_grid_pin_16_ ) , - .left_grid_pin_17_ ( cby_1__1__0_left_grid_pin_17_ ) , - .left_grid_pin_18_ ( cby_1__1__0_left_grid_pin_18_ ) , - .left_grid_pin_19_ ( cby_1__1__0_left_grid_pin_19_ ) , - .left_grid_pin_20_ ( cby_1__1__0_left_grid_pin_20_ ) , - .left_grid_pin_21_ ( cby_1__1__0_left_grid_pin_21_ ) , - .left_grid_pin_22_ ( cby_1__1__0_left_grid_pin_22_ ) , - .left_grid_pin_23_ ( cby_1__1__0_left_grid_pin_23_ ) , - .left_grid_pin_24_ ( cby_1__1__0_left_grid_pin_24_ ) , - .left_grid_pin_25_ ( cby_1__1__0_left_grid_pin_25_ ) , - .left_grid_pin_26_ ( cby_1__1__0_left_grid_pin_26_ ) , - .left_grid_pin_27_ ( cby_1__1__0_left_grid_pin_27_ ) , - .left_grid_pin_28_ ( cby_1__1__0_left_grid_pin_28_ ) , - .left_grid_pin_29_ ( cby_1__1__0_left_grid_pin_29_ ) , - .left_grid_pin_30_ ( cby_1__1__0_left_grid_pin_30_ ) , - .left_grid_pin_31_ ( cby_1__1__0_left_grid_pin_31_ ) , - .ccff_tail ( cby_1__1__0_ccff_tail ) , - .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_16 ) , - .prog_clk__FEEDTHRU_2 ( prog_clk__FEEDTHRU_9 ) ) ; -cby_1__1_ cby_1__2_ ( .prog_clk ( prog_clk__FEEDTHRU_10 ) , - .chany_bottom_in ( sb_1__1__0_chany_top_out ) , - .chany_top_in ( sb_1__2__0_chany_bottom_out ) , - .ccff_head ( grid_clb_1_ccff_tail ) , - .chany_bottom_out ( cby_1__1__1_chany_bottom_out ) , - .chany_top_out ( cby_1__1__1_chany_top_out ) , - .left_grid_pin_16_ ( cby_1__1__1_left_grid_pin_16_ ) , - .left_grid_pin_17_ ( cby_1__1__1_left_grid_pin_17_ ) , - .left_grid_pin_18_ ( cby_1__1__1_left_grid_pin_18_ ) , - .left_grid_pin_19_ ( cby_1__1__1_left_grid_pin_19_ ) , - .left_grid_pin_20_ ( cby_1__1__1_left_grid_pin_20_ ) , - .left_grid_pin_21_ ( cby_1__1__1_left_grid_pin_21_ ) , - .left_grid_pin_22_ ( cby_1__1__1_left_grid_pin_22_ ) , - .left_grid_pin_23_ ( cby_1__1__1_left_grid_pin_23_ ) , - .left_grid_pin_24_ ( cby_1__1__1_left_grid_pin_24_ ) , - .left_grid_pin_25_ ( cby_1__1__1_left_grid_pin_25_ ) , - .left_grid_pin_26_ ( cby_1__1__1_left_grid_pin_26_ ) , - .left_grid_pin_27_ ( cby_1__1__1_left_grid_pin_27_ ) , - .left_grid_pin_28_ ( cby_1__1__1_left_grid_pin_28_ ) , - .left_grid_pin_29_ ( cby_1__1__1_left_grid_pin_29_ ) , - .left_grid_pin_30_ ( cby_1__1__1_left_grid_pin_30_ ) , - .left_grid_pin_31_ ( cby_1__1__1_left_grid_pin_31_ ) , - .ccff_tail ( cby_1__1__1_ccff_tail ) , - .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_12 ) , - .prog_clk__FEEDTHRU_2 ( prog_clk__FEEDTHRU_11 ) ) ; -cby_2__1_ cby_2__1_ ( .prog_clk ( prog_clk__FEEDTHRU_19 ) , - .chany_bottom_in ( sb_2__0__0_chany_top_out ) , - .chany_top_in ( sb_2__1__0_chany_bottom_out ) , - .ccff_head ( grid_clb_2_ccff_tail ) , - .chany_bottom_out ( cby_2__1__0_chany_bottom_out ) , - .chany_top_out ( cby_2__1__0_chany_top_out ) , - .right_grid_pin_0_ ( cby_2__1__0_right_grid_pin_0_ ) , - .left_grid_pin_16_ ( cby_2__1__0_left_grid_pin_16_ ) , - .left_grid_pin_17_ ( cby_2__1__0_left_grid_pin_17_ ) , - .left_grid_pin_18_ ( cby_2__1__0_left_grid_pin_18_ ) , - .left_grid_pin_19_ ( cby_2__1__0_left_grid_pin_19_ ) , - .left_grid_pin_20_ ( cby_2__1__0_left_grid_pin_20_ ) , - .left_grid_pin_21_ ( cby_2__1__0_left_grid_pin_21_ ) , - .left_grid_pin_22_ ( cby_2__1__0_left_grid_pin_22_ ) , - .left_grid_pin_23_ ( cby_2__1__0_left_grid_pin_23_ ) , - .left_grid_pin_24_ ( cby_2__1__0_left_grid_pin_24_ ) , - .left_grid_pin_25_ ( cby_2__1__0_left_grid_pin_25_ ) , - .left_grid_pin_26_ ( cby_2__1__0_left_grid_pin_26_ ) , - .left_grid_pin_27_ ( cby_2__1__0_left_grid_pin_27_ ) , - .left_grid_pin_28_ ( cby_2__1__0_left_grid_pin_28_ ) , - .left_grid_pin_29_ ( cby_2__1__0_left_grid_pin_29_ ) , - .left_grid_pin_30_ ( cby_2__1__0_left_grid_pin_30_ ) , - .left_grid_pin_31_ ( cby_2__1__0_left_grid_pin_31_ ) , - .ccff_tail ( grid_io_right_0_ccff_tail ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[2] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[2] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[2] ) , - .left_width_0_height_0__pin_0_ ( cby_2__1__0_right_grid_pin_0_ ) , - .left_width_0_height_0__pin_1_upper ( grid_io_right_0_left_width_0_height_0__pin_1_upper ) , - .left_width_0_height_0__pin_1_lower ( grid_io_right_0_left_width_0_height_0__pin_1_lower ) ) ; -cby_2__1_ cby_2__2_ ( - .prog_clk ( { ctsbuf_net_24 } ) , - .chany_bottom_in ( sb_2__1__0_chany_top_out ) , - .chany_top_in ( sb_2__2__0_chany_bottom_out ) , - .ccff_head ( grid_clb_3_ccff_tail ) , - .chany_bottom_out ( cby_2__1__1_chany_bottom_out ) , - .chany_top_out ( cby_2__1__1_chany_top_out ) , - .right_grid_pin_0_ ( cby_2__1__1_right_grid_pin_0_ ) , - .left_grid_pin_16_ ( cby_2__1__1_left_grid_pin_16_ ) , - .left_grid_pin_17_ ( cby_2__1__1_left_grid_pin_17_ ) , - .left_grid_pin_18_ ( cby_2__1__1_left_grid_pin_18_ ) , - .left_grid_pin_19_ ( cby_2__1__1_left_grid_pin_19_ ) , - .left_grid_pin_20_ ( cby_2__1__1_left_grid_pin_20_ ) , - .left_grid_pin_21_ ( cby_2__1__1_left_grid_pin_21_ ) , - .left_grid_pin_22_ ( cby_2__1__1_left_grid_pin_22_ ) , - .left_grid_pin_23_ ( cby_2__1__1_left_grid_pin_23_ ) , - .left_grid_pin_24_ ( cby_2__1__1_left_grid_pin_24_ ) , - .left_grid_pin_25_ ( cby_2__1__1_left_grid_pin_25_ ) , - .left_grid_pin_26_ ( cby_2__1__1_left_grid_pin_26_ ) , - .left_grid_pin_27_ ( cby_2__1__1_left_grid_pin_27_ ) , - .left_grid_pin_28_ ( cby_2__1__1_left_grid_pin_28_ ) , - .left_grid_pin_29_ ( cby_2__1__1_left_grid_pin_29_ ) , - .left_grid_pin_30_ ( cby_2__1__1_left_grid_pin_30_ ) , - .left_grid_pin_31_ ( cby_2__1__1_left_grid_pin_31_ ) , - .ccff_tail ( grid_io_right_1_ccff_tail ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[3] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[3] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[3] ) , - .left_width_0_height_0__pin_0_ ( cby_2__1__1_right_grid_pin_0_ ) , - .left_width_0_height_0__pin_1_upper ( grid_io_right_1_left_width_0_height_0__pin_1_upper ) , - .left_width_0_height_0__pin_1_lower ( grid_io_right_1_left_width_0_height_0__pin_1_lower ) ) ; -direct_interc_0 direct_interc_0_ ( - .in ( grid_clb_1_bottom_width_0_height_0__pin_50_ ) , - .out ( direct_interc_0_out ) ) ; -direct_interc_1 direct_interc_1_ ( - .in ( grid_clb_3_bottom_width_0_height_0__pin_50_ ) , - .out ( direct_interc_1_out ) ) ; -direct_interc_2 direct_interc_2_ ( - .in ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) , - .out ( direct_interc_2_out ) ) ; -direct_interc_3 direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_56 } ) , - .out ( { SYNOPSYS_UNCONNECTED_57 } ) ) ; -direct_interc_4 direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_58 } ) , - .out ( { SYNOPSYS_UNCONNECTED_59 } ) ) ; -direct_interc direct_interc_5_ ( - .in ( grid_clb_0_bottom_width_0_height_0__pin_51_ ) , - .out ( { SYNOPSYS_UNCONNECTED_60 } ) ) ; -sky130_fd_sc_hd__clkinv_2 cts_inv_80028275 ( .A ( ctsbuf_net_46 ) , - .Y ( ctsbuf_net_24 ) ) ; -sky130_fd_sc_hd__inv_1 cts_inv_80108283 ( .A ( prog_clk__FEEDTHRU_15[0] ) , - .Y ( ctsbuf_net_46 ) ) ; -sky130_fd_sc_hd__inv_6 cts_inv_80408313 ( .A ( ctsbuf_net_1214 ) , - .Y ( ctsbuf_net_1113 ) ) ; -sky130_fd_sc_hd__inv_1 cts_inv_80448317 ( .A ( prog_clk__FEEDTHRU_5[0] ) , - .Y ( ctsbuf_net_1214 ) ) ; -sky130_fd_sc_hd__clkinv_16 cts_inv_80538326 ( .A ( ctsbuf_net_1416 ) , - .Y ( ctsbuf_net_1315 ) ) ; -sky130_fd_sc_hd__inv_2 cts_inv_80578330 ( .A ( prog_clk__FEEDTHRU_12[0] ) , - .Y ( ctsbuf_net_1416 ) ) ; -sky130_fd_sc_hd__clkinv_2 cts_inv_80898362 ( .A ( ctsbuf_net_1820 ) , - .Y ( ctsbuf_net_1719 ) ) ; -sky130_fd_sc_hd__inv_1 cts_inv_80938366 ( .A ( prog_clk__FEEDTHRU_2[0] ) , - .Y ( ctsbuf_net_1820 ) ) ; -sky130_fd_sc_hd__clkinv_16 cts_inv_80978370 ( .A ( ctsbuf_net_2022 ) , - .Y ( ctsbuf_net_1921 ) ) ; -sky130_fd_sc_hd__inv_2 cts_inv_81018374 ( .A ( prog_clk__FEEDTHRU_2[0] ) , - .Y ( ctsbuf_net_2022 ) ) ; -sky130_fd_sc_hd__clkinv_16 cts_inv_81108383 ( .A ( ctsbuf_net_2224 ) , - .Y ( ctsbuf_net_2123 ) ) ; -sky130_fd_sc_hd__inv_2 cts_inv_81148387 ( .A ( prog_clk__FEEDTHRU_9[0] ) , - .Y ( ctsbuf_net_2224 ) ) ; -sky130_fd_sc_hd__clkinv_8 cts_inv_81198392 ( .A ( ctsbuf_net_2527 ) , - .Y ( ctsbuf_net_2325 ) ) ; -sky130_fd_sc_hd__inv_4 cts_inv_81238396 ( .A ( ctsbuf_net_2628 ) , - .Y ( ctsbuf_net_2426 ) ) ; -sky130_fd_sc_hd__inv_2 cts_inv_81278400 ( .A ( prog_clk__FEEDTHRU_8[0] ) , - .Y ( ctsbuf_net_2527 ) ) ; -sky130_fd_sc_hd__inv_1 cts_inv_81318404 ( .A ( prog_clk__FEEDTHRU_1[0] ) , - .Y ( ctsbuf_net_2628 ) ) ; -sky130_fd_sc_hd__inv_4 cts_inv_81368409 ( .A ( ctsbuf_net_2830 ) , - .Y ( ctsbuf_net_2729 ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_81408413 ( .A ( prog_clk[0] ) , - .Y ( ctsbuf_net_2830 ) ) ; -endmodule - - diff --git a/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.gds.gz b/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.gds.gz deleted file mode 100644 index 17ab400..0000000 Binary files a/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.gds.gz and /dev/null differ diff --git a/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.lef b/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.lef deleted file mode 100644 index bc1a90d..0000000 --- a/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.lef +++ /dev/null @@ -1,352 +0,0 @@ -VERSION 5.7 ; -BUSBITCHARS "[]" ; - -UNITS - DATABASE MICRONS 1000 ; -END UNITS - -MANUFACTURINGGRID 0.005 ; - -LAYER li1 - TYPE ROUTING ; - DIRECTION VERTICAL ; - PITCH 0.46 ; - WIDTH 0.17 ; -END li1 - -LAYER mcon - TYPE CUT ; -END mcon - -LAYER met1 - TYPE ROUTING ; - DIRECTION HORIZONTAL ; - PITCH 0.34 ; - WIDTH 0.14 ; -END met1 - -LAYER via - TYPE CUT ; -END via - -LAYER met2 - TYPE ROUTING ; - DIRECTION VERTICAL ; - PITCH 0.46 ; - WIDTH 0.14 ; -END met2 - -LAYER via2 - TYPE CUT ; -END via2 - -LAYER met3 - TYPE ROUTING ; - DIRECTION HORIZONTAL ; - PITCH 0.68 ; - WIDTH 0.3 ; -END met3 - -LAYER via3 - TYPE CUT ; -END via3 - -LAYER met4 - TYPE ROUTING ; - DIRECTION VERTICAL ; - PITCH 0.92 ; - WIDTH 0.3 ; -END met4 - -LAYER via4 - TYPE CUT ; -END via4 - -LAYER met5 - TYPE ROUTING ; - DIRECTION HORIZONTAL ; - PITCH 3.4 ; - WIDTH 1.6 ; -END met5 - -LAYER nwell - TYPE MASTERSLICE ; -END nwell - -LAYER pwell - TYPE MASTERSLICE ; -END pwell - -VIA L1M1_PR - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.145 -0.115 0.145 0.115 ; -END L1M1_PR - -VIA L1M1_PR_R - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.115 -0.145 0.115 0.145 ; -END L1M1_PR_R - -VIA L1M1_PR_M - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.115 -0.145 0.115 0.145 ; -END L1M1_PR_M - -VIA L1M1_PR_MR - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.145 -0.115 0.145 0.115 ; -END L1M1_PR_MR - -VIA L1M1_PR_C - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.145 -0.145 0.145 0.145 ; -END L1M1_PR_C - -VIA M1M2_PR - LAYER met1 ; - RECT -0.16 -0.13 0.16 0.13 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.13 -0.16 0.13 0.16 ; -END M1M2_PR - -VIA M1M2_PR_Enc - LAYER met1 ; - RECT -0.16 -0.13 0.16 0.13 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.16 -0.13 0.16 0.13 ; -END M1M2_PR_Enc - -VIA M1M2_PR_R - LAYER met1 ; - RECT -0.13 -0.16 0.13 0.16 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.16 -0.13 0.16 0.13 ; -END M1M2_PR_R - -VIA M1M2_PR_R_Enc - LAYER met1 ; - RECT -0.13 -0.16 0.13 0.16 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.13 -0.16 0.13 0.16 ; -END M1M2_PR_R_Enc - -VIA M1M2_PR_M - LAYER met1 ; - RECT -0.16 -0.13 0.16 0.13 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.16 -0.13 0.16 0.13 ; -END M1M2_PR_M - -VIA M1M2_PR_M_Enc - LAYER met1 ; - RECT -0.16 -0.13 0.16 0.13 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.13 -0.16 0.13 0.16 ; -END M1M2_PR_M_Enc - -VIA M1M2_PR_MR - LAYER met1 ; - RECT -0.13 -0.16 0.13 0.16 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.13 -0.16 0.13 0.16 ; -END M1M2_PR_MR - -VIA M1M2_PR_MR_Enc - LAYER met1 ; - RECT -0.13 -0.16 0.13 0.16 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.16 -0.13 0.16 0.13 ; -END M1M2_PR_MR_Enc - -VIA M1M2_PR_C - LAYER met1 ; - RECT -0.16 -0.16 0.16 0.16 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.16 -0.16 0.16 0.16 ; -END M1M2_PR_C - -VIA M2M3_PR - LAYER met2 ; - RECT -0.14 -0.185 0.14 0.185 ; - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met3 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M2M3_PR - -VIA M2M3_PR_R - LAYER met2 ; - RECT -0.185 -0.14 0.185 0.14 ; - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met3 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M2M3_PR_R - -VIA M2M3_PR_M - LAYER met2 ; - RECT -0.14 -0.185 0.14 0.185 ; - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met3 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M2M3_PR_M - -VIA M2M3_PR_MR - LAYER met2 ; - RECT -0.185 -0.14 0.185 0.14 ; - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met3 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M2M3_PR_MR - -VIA M2M3_PR_C - LAYER met2 ; - RECT -0.185 -0.185 0.185 0.185 ; - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met3 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M2M3_PR_C - -VIA M3M4_PR - LAYER met3 ; - RECT -0.19 -0.16 0.19 0.16 ; - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR - -VIA M3M4_PR_R - LAYER met3 ; - RECT -0.16 -0.19 0.16 0.19 ; - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR_R - -VIA M3M4_PR_M - LAYER met3 ; - RECT -0.19 -0.16 0.19 0.16 ; - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR_M - -VIA M3M4_PR_MR - LAYER met3 ; - RECT -0.16 -0.19 0.16 0.19 ; - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR_MR - -VIA M3M4_PR_C - LAYER met3 ; - RECT -0.19 -0.19 0.19 0.19 ; - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR_C - -VIA M4M5_PR - LAYER met4 ; - RECT -0.59 -0.59 0.59 0.59 ; - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - LAYER met5 ; - RECT -0.71 -0.71 0.71 0.71 ; -END M4M5_PR - -VIA M4M5_PR_R - LAYER met4 ; - RECT -0.59 -0.59 0.59 0.59 ; - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - LAYER met5 ; - RECT -0.71 -0.71 0.71 0.71 ; -END M4M5_PR_R - -VIA M4M5_PR_M - LAYER met4 ; - RECT -0.59 -0.59 0.59 0.59 ; - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - LAYER met5 ; - RECT -0.71 -0.71 0.71 0.71 ; -END M4M5_PR_M - -VIA M4M5_PR_MR - LAYER met4 ; - RECT -0.59 -0.59 0.59 0.59 ; - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - LAYER met5 ; - RECT -0.71 -0.71 0.71 0.71 ; -END M4M5_PR_MR - -VIA M4M5_PR_C - LAYER met4 ; - RECT -0.59 -0.59 0.59 0.59 ; - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - LAYER met5 ; - RECT -0.71 -0.71 0.71 0.71 ; -END M4M5_PR_C - -SITE unit - CLASS CORE ; - SYMMETRY Y ; - SIZE 0.46 BY 2.72 ; -END unit - -SITE unithddbl - CLASS CORE ; - SIZE 0.46 BY 5.44 ; -END unithddbl - -END LIBRARY diff --git a/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.lvs.v b/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.lvs.v deleted file mode 100644 index ffa37f1..0000000 --- a/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.lvs.v +++ /dev/null @@ -1,125467 +0,0 @@ -// -// -// -// -// -// -module direct_interc_2 ( in , out , VDD , VSS ) ; -input [0:0] in ; -output [0:0] out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__2 ( .A ( in[0] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module direct_interc_1 ( in , out , VDD , VSS ) ; -input [0:0] in ; -output [0:0] out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__1 ( .A ( in[0] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module direct_interc_0 ( in , out , VDD , VSS ) ; -input [0:0] in ; -output [0:0] out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__0 ( .A ( in[0] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_2__1__direct_interc ( in , out ) ; -input [0:0] in ; -output [0:0] out ; - -assign out[0] = in[0] ; -endmodule - - -module cby_2__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( prog_clk , - ccff_head , ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:0] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_20__60 ( .A ( mem_out[0] ) , - .X ( net_net_80 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_80 ( .A ( net_net_80 ) , - .X ( net_net_79 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_101 ( .A ( net_net_79 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_2__1__EMBEDDED_IO ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , - FPGA_OUT , FPGA_DIR , p_abuf0 , VDD , VSS ) ; -input SOC_IN ; -output SOC_OUT ; -output SOC_DIR ; -output FPGA_IN ; -input FPGA_OUT ; -input FPGA_DIR ; -output p_abuf0 ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -assign SOC_OUT = FPGA_OUT ; - -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__58 ( .A ( SOC_IN ) , .X ( FPGA_IN ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 FTB_19__59 ( .A ( FPGA_DIR ) , - .X ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_62 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_2__1__logical_tile_io_mode_physical__iopad ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , VDD , VSS , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] iopad_outpad ; -input [0:0] ccff_head ; -output [0:0] iopad_inpad ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; -output p_abuf0 ; - -wire [0:0] EMBEDDED_IO_0_en ; -supply1 VDD ; -supply0 VSS ; - -cby_2__1__EMBEDDED_IO EMBEDDED_IO_0_ ( - .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , - .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , - .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , - .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -cby_2__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -endmodule - - -module cby_2__1__logical_tile_io_mode_io_ ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , - ccff_tail , VDD , VSS , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] io_outpad ; -input [0:0] ccff_head ; -output [0:0] io_inpad ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; -output p_abuf0 ; - -supply1 VDD ; -supply0 VSS ; - -cby_2__1__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , - .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , - .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) ) ; -cby_2__1__direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( io_outpad ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__57 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__56 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__55 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__54 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__53 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__52 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__51 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__50 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_4 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__49 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__48 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__47 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__46 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__45 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__44 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__43 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__42 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__41 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_2__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , - chany_bottom_out , chany_top_out , right_grid_pin_0_ , left_grid_pin_16_ , - left_grid_pin_17_ , left_grid_pin_18_ , left_grid_pin_19_ , - left_grid_pin_20_ , left_grid_pin_21_ , left_grid_pin_22_ , - left_grid_pin_23_ , left_grid_pin_24_ , left_grid_pin_25_ , - left_grid_pin_26_ , left_grid_pin_27_ , left_grid_pin_28_ , - left_grid_pin_29_ , left_grid_pin_30_ , left_grid_pin_31_ , ccff_tail , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , left_width_0_height_0__pin_0_ , - left_width_0_height_0__pin_1_upper , left_width_0_height_0__pin_1_lower , - VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:19] chany_bottom_in ; -input [0:19] chany_top_in ; -input [0:0] ccff_head ; -output [0:19] chany_bottom_out ; -output [0:19] chany_top_out ; -output [0:0] right_grid_pin_0_ ; -output [0:0] left_grid_pin_16_ ; -output [0:0] left_grid_pin_17_ ; -output [0:0] left_grid_pin_18_ ; -output [0:0] left_grid_pin_19_ ; -output [0:0] left_grid_pin_20_ ; -output [0:0] left_grid_pin_21_ ; -output [0:0] left_grid_pin_22_ ; -output [0:0] left_grid_pin_23_ ; -output [0:0] left_grid_pin_24_ ; -output [0:0] left_grid_pin_25_ ; -output [0:0] left_grid_pin_26_ ; -output [0:0] left_grid_pin_27_ ; -output [0:0] left_grid_pin_28_ ; -output [0:0] left_grid_pin_29_ ; -output [0:0] left_grid_pin_30_ ; -output [0:0] left_grid_pin_31_ ; -output [0:0] ccff_tail ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] left_width_0_height_0__pin_0_ ; -output [0:0] left_width_0_height_0__pin_1_upper ; -output [0:0] left_width_0_height_0__pin_1_lower ; -input VDD ; -input VSS ; - -wire ropt_net_114 ; -wire [0:3] mux_left_ipin_0_undriven_sram_inv ; -wire [0:3] mux_right_ipin_0_undriven_sram_inv ; -wire [0:3] mux_right_ipin_10_undriven_sram_inv ; -wire [0:3] mux_right_ipin_11_undriven_sram_inv ; -wire [0:3] mux_right_ipin_12_undriven_sram_inv ; -wire [0:3] mux_right_ipin_13_undriven_sram_inv ; -wire [0:3] mux_right_ipin_14_undriven_sram_inv ; -wire [0:3] mux_right_ipin_15_undriven_sram_inv ; -wire [0:3] mux_right_ipin_1_undriven_sram_inv ; -wire [0:3] mux_right_ipin_2_undriven_sram_inv ; -wire [0:3] mux_right_ipin_3_undriven_sram_inv ; -wire [0:3] mux_right_ipin_4_undriven_sram_inv ; -wire [0:3] mux_right_ipin_5_undriven_sram_inv ; -wire [0:3] mux_right_ipin_6_undriven_sram_inv ; -wire [0:3] mux_right_ipin_7_undriven_sram_inv ; -wire [0:3] mux_right_ipin_8_undriven_sram_inv ; -wire [0:3] mux_right_ipin_9_undriven_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:3] mux_tree_tapbuf_size10_2_sram ; -wire [0:3] mux_tree_tapbuf_size10_3_sram ; -wire [0:3] mux_tree_tapbuf_size10_4_sram ; -wire [0:3] mux_tree_tapbuf_size10_5_sram ; -wire [0:3] mux_tree_tapbuf_size10_6_sram ; -wire [0:3] mux_tree_tapbuf_size10_7_sram ; -wire [0:3] mux_tree_tapbuf_size10_8_sram ; -wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:3] mux_tree_tapbuf_size8_2_sram ; -wire [0:3] mux_tree_tapbuf_size8_3_sram ; -wire [0:3] mux_tree_tapbuf_size8_4_sram ; -wire [0:3] mux_tree_tapbuf_size8_5_sram ; -wire [0:3] mux_tree_tapbuf_size8_6_sram ; -wire [0:3] mux_tree_tapbuf_size8_7_sram ; -wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ; -supply1 VDD ; -supply0 VSS ; - -cby_2__1__mux_tree_tapbuf_size10_0 mux_left_ipin_0 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , - chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , - chany_top_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_left_ipin_0_undriven_sram_inv ) , - .out ( right_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_111 ) ) ; -cby_2__1__mux_tree_tapbuf_size10_1 mux_right_ipin_0 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , - chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[17] , - chany_top_in[17] } ) , - .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_right_ipin_0_undriven_sram_inv ) , - .out ( left_grid_pin_16_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_110 ) ) ; -cby_2__1__mux_tree_tapbuf_size10_5 mux_right_ipin_3 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , - chany_bottom_in[8] , chany_top_in[8] , chany_bottom_in[14] , - chany_top_in[14] } ) , - .sram ( mux_tree_tapbuf_size10_2_sram ) , - .sram_inv ( mux_right_ipin_3_undriven_sram_inv ) , - .out ( left_grid_pin_19_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_109 ) ) ; -cby_2__1__mux_tree_tapbuf_size10_6 mux_right_ipin_4 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , - chany_bottom_in[9] , chany_top_in[9] , chany_bottom_in[15] , - chany_top_in[15] } ) , - .sram ( mux_tree_tapbuf_size10_3_sram ) , - .sram_inv ( mux_right_ipin_4_undriven_sram_inv ) , - .out ( left_grid_pin_20_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_108 ) ) ; -cby_2__1__mux_tree_tapbuf_size10_7 mux_right_ipin_7 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[8] , chany_top_in[8] , - chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[18] , - chany_top_in[18] } ) , - .sram ( mux_tree_tapbuf_size10_4_sram ) , - .sram_inv ( mux_right_ipin_7_undriven_sram_inv ) , - .out ( left_grid_pin_23_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_109 ) ) ; -cby_2__1__mux_tree_tapbuf_size10 mux_right_ipin_8 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , - chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[19] , - chany_top_in[19] } ) , - .sram ( mux_tree_tapbuf_size10_5_sram ) , - .sram_inv ( mux_right_ipin_8_undriven_sram_inv ) , - .out ( left_grid_pin_24_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_108 ) ) ; -cby_2__1__mux_tree_tapbuf_size10_2 mux_right_ipin_11 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , - chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[16] , - chany_top_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_6_sram ) , - .sram_inv ( mux_right_ipin_11_undriven_sram_inv ) , - .out ( left_grid_pin_27_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_109 ) ) ; -cby_2__1__mux_tree_tapbuf_size10_3 mux_right_ipin_12 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , - chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[17] , - chany_top_in[17] } ) , - .sram ( mux_tree_tapbuf_size10_7_sram ) , - .sram_inv ( mux_right_ipin_12_undriven_sram_inv ) , - .out ( left_grid_pin_28_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_108 ) ) ; -cby_2__1__mux_tree_tapbuf_size10_4 mux_right_ipin_15 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , - chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , - chany_top_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_8_sram ) , - .sram_inv ( mux_right_ipin_15_undriven_sram_inv ) , - .out ( left_grid_pin_31_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_111 ) ) ; -cby_2__1__mux_tree_tapbuf_size10_mem_0 mem_left_ipin_0 ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cby_2__1__mux_tree_tapbuf_size10_mem_1 mem_right_ipin_0 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cby_2__1__mux_tree_tapbuf_size10_mem_5 mem_right_ipin_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cby_2__1__mux_tree_tapbuf_size10_mem_6 mem_right_ipin_4 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cby_2__1__mux_tree_tapbuf_size10_mem_7 mem_right_ipin_7 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cby_2__1__mux_tree_tapbuf_size10_mem mem_right_ipin_8 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cby_2__1__mux_tree_tapbuf_size10_mem_2 mem_right_ipin_11 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cby_2__1__mux_tree_tapbuf_size10_mem_3 mem_right_ipin_12 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cby_2__1__mux_tree_tapbuf_size10_mem_4 mem_right_ipin_15 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , - .mem_out ( mux_tree_tapbuf_size10_8_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cby_2__1__mux_tree_tapbuf_size8_0 mux_right_ipin_1 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , - chany_bottom_in[14] , chany_top_in[14] } ) , - .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_right_ipin_1_undriven_sram_inv ) , - .out ( left_grid_pin_17_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_111 ) ) ; -cby_2__1__mux_tree_tapbuf_size8_4 mux_right_ipin_2 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , - chany_bottom_in[15] , chany_top_in[15] } ) , - .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_right_ipin_2_undriven_sram_inv ) , - .out ( left_grid_pin_18_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_108 ) ) ; -cby_2__1__mux_tree_tapbuf_size8_5 mux_right_ipin_5 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , - chany_bottom_in[18] , chany_top_in[18] } ) , - .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_right_ipin_5_undriven_sram_inv ) , - .out ( left_grid_pin_21_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_111 ) ) ; -cby_2__1__mux_tree_tapbuf_size8_6 mux_right_ipin_6 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[11] , chany_top_in[11] , - chany_bottom_in[19] , chany_top_in[19] } ) , - .sram ( mux_tree_tapbuf_size8_3_sram ) , - .sram_inv ( mux_right_ipin_6_undriven_sram_inv ) , - .out ( left_grid_pin_22_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_110 ) ) ; -cby_2__1__mux_tree_tapbuf_size8 mux_right_ipin_9 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , - chany_bottom_in[14] , chany_top_in[14] } ) , - .sram ( mux_tree_tapbuf_size8_4_sram ) , - .sram_inv ( mux_right_ipin_9_undriven_sram_inv ) , - .out ( left_grid_pin_25_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_111 ) ) ; -cby_2__1__mux_tree_tapbuf_size8_1 mux_right_ipin_10 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , - chany_bottom_in[15] , chany_top_in[15] } ) , - .sram ( mux_tree_tapbuf_size8_5_sram ) , - .sram_inv ( mux_right_ipin_10_undriven_sram_inv ) , - .out ( left_grid_pin_26_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_108 ) ) ; -cby_2__1__mux_tree_tapbuf_size8_2 mux_right_ipin_13 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , - chany_bottom_in[18] , chany_top_in[18] } ) , - .sram ( mux_tree_tapbuf_size8_6_sram ) , - .sram_inv ( mux_right_ipin_13_undriven_sram_inv ) , - .out ( left_grid_pin_29_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_111 ) ) ; -cby_2__1__mux_tree_tapbuf_size8_3 mux_right_ipin_14 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[11] , chany_top_in[11] , - chany_bottom_in[19] , chany_top_in[19] } ) , - .sram ( mux_tree_tapbuf_size8_7_sram ) , - .sram_inv ( mux_right_ipin_14_undriven_sram_inv ) , - .out ( left_grid_pin_30_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_110 ) ) ; -cby_2__1__mux_tree_tapbuf_size8_mem_0 mem_right_ipin_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cby_2__1__mux_tree_tapbuf_size8_mem_4 mem_right_ipin_2 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cby_2__1__mux_tree_tapbuf_size8_mem_5 mem_right_ipin_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cby_2__1__mux_tree_tapbuf_size8_mem_6 mem_right_ipin_6 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cby_2__1__mux_tree_tapbuf_size8_mem mem_right_ipin_9 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cby_2__1__mux_tree_tapbuf_size8_mem_1 mem_right_ipin_10 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cby_2__1__mux_tree_tapbuf_size8_mem_2 mem_right_ipin_13 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cby_2__1__mux_tree_tapbuf_size8_mem_3 mem_right_ipin_14 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cby_2__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , - .io_outpad ( left_width_0_height_0__pin_0_ ) , - .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_8_ } ) , - .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf0 ( ropt_net_114 ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1668 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1669 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1670 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1671 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1672 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1673 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1674 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1675 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1676 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1677 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1678 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1679 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1680 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1681 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1682 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_bottom_in[0] ) , - .X ( ropt_net_115 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chany_bottom_in[1] ) , - .X ( chany_top_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_bottom_in[2] ) , - .X ( chany_top_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_bottom_in[3] ) , - .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chany_bottom_in[4] ) , - .X ( chany_top_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_bottom_in[6] ) , - .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chany_bottom_in[8] ) , - .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_691 ( .A ( ropt_net_114 ) , - .X ( left_width_0_height_0__pin_1_upper[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_689 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_116 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__11 ( .A ( chany_bottom_in[11] ) , - .X ( aps_rename_3_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__12 ( .A ( chany_bottom_in[12] ) , - .X ( aps_rename_4_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chany_bottom_in[13] ) , - .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__14 ( .A ( chany_bottom_in[14] ) , - .X ( aps_rename_5_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__15 ( .A ( chany_bottom_in[15] ) , - .X ( aps_rename_6_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chany_bottom_in[16] ) , - .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_692 ( .A ( ropt_net_115 ) , - .X ( chany_top_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chany_bottom_in[18] ) , - .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chany_top_in[0] ) , - .X ( chany_bottom_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chany_top_in[1] ) , - .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chany_top_in[2] ) , - .X ( chany_bottom_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chany_top_in[3] ) , - .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chany_top_in[5] ) , - .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_690 ( - .A ( chany_bottom_in[17] ) , .X ( chany_top_out[17] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chany_top_in[7] ) , - .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_693 ( .A ( ropt_net_116 ) , - .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chany_top_in[9] ) , - .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_694 ( .A ( ropt_net_117 ) , - .X ( left_width_0_height_0__pin_1_lower[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_32__31 ( .A ( chany_top_in[11] ) , - .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_36__35 ( .A ( chany_top_in[15] ) , - .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_37__36 ( .A ( chany_top_in[16] ) , - .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_39__38 ( .A ( chany_top_in[18] ) , - .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_41__40 ( .A ( aps_rename_8_ ) , - .X ( aps_rename_9_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_66 ( .A ( chany_bottom_in[5] ) , - .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_67 ( .A ( chany_bottom_in[7] ) , - .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_74 ( .A ( chany_top_in[8] ) , - .X ( chany_bottom_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_77 ( .A ( chany_top_in[17] ) , - .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_78 ( .A ( aps_rename_9_ ) , - .X ( ropt_net_117 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_82 ( .A ( chany_bottom_in[19] ) , - .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_83 ( .A ( chany_top_in[10] ) , - .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_85 ( .A ( aps_rename_3_ ) , - .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_86 ( .A ( aps_rename_4_ ) , - .X ( chany_top_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_87 ( .A ( aps_rename_5_ ) , - .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_88 ( .A ( aps_rename_6_ ) , - .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_90 ( .A ( chany_top_in[12] ) , - .X ( chany_bottom_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_94 ( .A ( chany_top_in[4] ) , - .X ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_95 ( .A ( chany_top_in[6] ) , - .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_96 ( .A ( chany_top_in[14] ) , - .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_97 ( .A ( chany_top_in[19] ) , - .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_98 ( .A ( chany_bottom_in[10] ) , - .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_99 ( .A ( chany_top_in[13] ) , - .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y0 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y0 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x36800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x552000y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x515200y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x593400y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x55200y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x101200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x119600y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x59800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x110400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x381800y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x469200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x289800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x354200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x519800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x529000y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x151800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x243800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x446200y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x506000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x515200y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x156400y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x391000y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x36800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x138000y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x547400y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x593400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x161000y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x289800y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x326600y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x188600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x207000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x432400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x510600y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x556600y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x588800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x36800y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x271400y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x506000y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x55200y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x87400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x174800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x308200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x326600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x335800y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x391000y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x547400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x556600y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x184000y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x345000y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x400200y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x55200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x64400y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x110400y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x142600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x151800y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x197800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x207000y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x542800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x142600y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x584200y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x285200y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x556600y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__55 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__54 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__53 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__52 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__51 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__50 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__49 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__48 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_8__47 ( .A ( mem_out[3] ) , - .X ( net_net_72 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_96 ( .A ( net_net_72 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__46 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__45 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__44 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__43 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__42 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__41 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__40 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_1__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , - chany_bottom_out , chany_top_out , left_grid_pin_16_ , left_grid_pin_17_ , - left_grid_pin_18_ , left_grid_pin_19_ , left_grid_pin_20_ , - left_grid_pin_21_ , left_grid_pin_22_ , left_grid_pin_23_ , - left_grid_pin_24_ , left_grid_pin_25_ , left_grid_pin_26_ , - left_grid_pin_27_ , left_grid_pin_28_ , left_grid_pin_29_ , - left_grid_pin_30_ , left_grid_pin_31_ , ccff_tail , VDD , VSS , - prog_clk__FEEDTHRU_1 , prog_clk__FEEDTHRU_2 ) ; -input [0:0] prog_clk ; -input [0:19] chany_bottom_in ; -input [0:19] chany_top_in ; -input [0:0] ccff_head ; -output [0:19] chany_bottom_out ; -output [0:19] chany_top_out ; -output [0:0] left_grid_pin_16_ ; -output [0:0] left_grid_pin_17_ ; -output [0:0] left_grid_pin_18_ ; -output [0:0] left_grid_pin_19_ ; -output [0:0] left_grid_pin_20_ ; -output [0:0] left_grid_pin_21_ ; -output [0:0] left_grid_pin_22_ ; -output [0:0] left_grid_pin_23_ ; -output [0:0] left_grid_pin_24_ ; -output [0:0] left_grid_pin_25_ ; -output [0:0] left_grid_pin_26_ ; -output [0:0] left_grid_pin_27_ ; -output [0:0] left_grid_pin_28_ ; -output [0:0] left_grid_pin_29_ ; -output [0:0] left_grid_pin_30_ ; -output [0:0] left_grid_pin_31_ ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; -output [0:0] prog_clk__FEEDTHRU_1 ; -output [0:0] prog_clk__FEEDTHRU_2 ; - -wire [0:3] mux_right_ipin_0_undriven_sram_inv ; -wire [0:3] mux_right_ipin_10_undriven_sram_inv ; -wire [0:3] mux_right_ipin_11_undriven_sram_inv ; -wire [0:3] mux_right_ipin_12_undriven_sram_inv ; -wire [0:3] mux_right_ipin_13_undriven_sram_inv ; -wire [0:3] mux_right_ipin_14_undriven_sram_inv ; -wire [0:3] mux_right_ipin_15_undriven_sram_inv ; -wire [0:3] mux_right_ipin_1_undriven_sram_inv ; -wire [0:3] mux_right_ipin_2_undriven_sram_inv ; -wire [0:3] mux_right_ipin_3_undriven_sram_inv ; -wire [0:3] mux_right_ipin_4_undriven_sram_inv ; -wire [0:3] mux_right_ipin_5_undriven_sram_inv ; -wire [0:3] mux_right_ipin_6_undriven_sram_inv ; -wire [0:3] mux_right_ipin_7_undriven_sram_inv ; -wire [0:3] mux_right_ipin_8_undriven_sram_inv ; -wire [0:3] mux_right_ipin_9_undriven_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:3] mux_tree_tapbuf_size10_2_sram ; -wire [0:3] mux_tree_tapbuf_size10_3_sram ; -wire [0:3] mux_tree_tapbuf_size10_4_sram ; -wire [0:3] mux_tree_tapbuf_size10_5_sram ; -wire [0:3] mux_tree_tapbuf_size10_6_sram ; -wire [0:3] mux_tree_tapbuf_size10_7_sram ; -wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:3] mux_tree_tapbuf_size8_2_sram ; -wire [0:3] mux_tree_tapbuf_size8_3_sram ; -wire [0:3] mux_tree_tapbuf_size8_4_sram ; -wire [0:3] mux_tree_tapbuf_size8_5_sram ; -wire [0:3] mux_tree_tapbuf_size8_6_sram ; -wire [0:3] mux_tree_tapbuf_size8_7_sram ; -wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ; -supply1 VDD ; -supply0 VSS ; - -cby_1__1__mux_tree_tapbuf_size10_0 mux_right_ipin_0 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , - chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , - chany_top_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_right_ipin_0_undriven_sram_inv ) , - .out ( left_grid_pin_16_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_103 ) ) ; -cby_1__1__mux_tree_tapbuf_size10_4 mux_right_ipin_3 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , - chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[19] , - chany_top_in[19] } ) , - .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_right_ipin_3_undriven_sram_inv ) , - .out ( left_grid_pin_19_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_105 ) ) ; -cby_1__1__mux_tree_tapbuf_size10_5 mux_right_ipin_4 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , - chany_bottom_in[8] , chany_top_in[8] , chany_bottom_in[14] , - chany_top_in[14] } ) , - .sram ( mux_tree_tapbuf_size10_2_sram ) , - .sram_inv ( mux_right_ipin_4_undriven_sram_inv ) , - .out ( left_grid_pin_20_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_103 ) ) ; -cby_1__1__mux_tree_tapbuf_size10_6 mux_right_ipin_7 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , - chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[17] , - chany_top_in[17] } ) , - .sram ( mux_tree_tapbuf_size10_3_sram ) , - .sram_inv ( mux_right_ipin_7_undriven_sram_inv ) , - .out ( left_grid_pin_23_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_104 ) ) ; -cby_1__1__mux_tree_tapbuf_size10 mux_right_ipin_8 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[8] , chany_top_in[8] , - chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[18] , - chany_top_in[18] } ) , - .sram ( mux_tree_tapbuf_size10_4_sram ) , - .sram_inv ( mux_right_ipin_8_undriven_sram_inv ) , - .out ( left_grid_pin_24_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_106 ) ) ; -cby_1__1__mux_tree_tapbuf_size10_1 mux_right_ipin_11 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , - chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[15] , - chany_top_in[15] } ) , - .sram ( mux_tree_tapbuf_size10_5_sram ) , - .sram_inv ( mux_right_ipin_11_undriven_sram_inv ) , - .out ( left_grid_pin_27_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_106 ) ) ; -cby_1__1__mux_tree_tapbuf_size10_2 mux_right_ipin_12 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , - chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[16] , - chany_top_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_6_sram ) , - .sram_inv ( mux_right_ipin_12_undriven_sram_inv ) , - .out ( left_grid_pin_28_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_106 ) ) ; -cby_1__1__mux_tree_tapbuf_size10_3 mux_right_ipin_15 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , - chany_bottom_in[15] , chany_top_in[15] , chany_bottom_in[19] , - chany_top_in[19] } ) , - .sram ( mux_tree_tapbuf_size10_7_sram ) , - .sram_inv ( mux_right_ipin_15_undriven_sram_inv ) , - .out ( left_grid_pin_31_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_104 ) ) ; -cby_1__1__mux_tree_tapbuf_size10_mem_0 mem_right_ipin_0 ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cby_1__1__mux_tree_tapbuf_size10_mem_4 mem_right_ipin_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cby_1__1__mux_tree_tapbuf_size10_mem_5 mem_right_ipin_4 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cby_1__1__mux_tree_tapbuf_size10_mem_6 mem_right_ipin_7 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cby_1__1__mux_tree_tapbuf_size10_mem mem_right_ipin_8 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cby_1__1__mux_tree_tapbuf_size10_mem_1 mem_right_ipin_11 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cby_1__1__mux_tree_tapbuf_size10_mem_2 mem_right_ipin_12 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cby_1__1__mux_tree_tapbuf_size10_mem_3 mem_right_ipin_15 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .ccff_tail ( { ropt_net_120 } ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cby_1__1__mux_tree_tapbuf_size8_0 mux_right_ipin_1 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , - chany_bottom_in[13] , chany_top_in[13] } ) , - .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_right_ipin_1_undriven_sram_inv ) , - .out ( left_grid_pin_17_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_105 ) ) ; -cby_1__1__mux_tree_tapbuf_size8_4 mux_right_ipin_2 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , - chany_bottom_in[14] , chany_top_in[14] } ) , - .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_right_ipin_2_undriven_sram_inv ) , - .out ( left_grid_pin_18_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_103 ) ) ; -cby_1__1__mux_tree_tapbuf_size8_5 mux_right_ipin_5 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , - chany_bottom_in[17] , chany_top_in[17] } ) , - .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_right_ipin_5_undriven_sram_inv ) , - .out ( left_grid_pin_21_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_105 ) ) ; -cby_1__1__mux_tree_tapbuf_size8_6 mux_right_ipin_6 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , - chany_bottom_in[18] , chany_top_in[18] } ) , - .sram ( mux_tree_tapbuf_size8_3_sram ) , - .sram_inv ( mux_right_ipin_6_undriven_sram_inv ) , - .out ( left_grid_pin_22_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_103 ) ) ; -cby_1__1__mux_tree_tapbuf_size8 mux_right_ipin_9 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , - chany_bottom_in[13] , chany_top_in[13] } ) , - .sram ( mux_tree_tapbuf_size8_4_sram ) , - .sram_inv ( mux_right_ipin_9_undriven_sram_inv ) , - .out ( left_grid_pin_25_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_105 ) ) ; -cby_1__1__mux_tree_tapbuf_size8_1 mux_right_ipin_10 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , - chany_bottom_in[14] , chany_top_in[14] } ) , - .sram ( mux_tree_tapbuf_size8_5_sram ) , - .sram_inv ( mux_right_ipin_10_undriven_sram_inv ) , - .out ( left_grid_pin_26_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_103 ) ) ; -cby_1__1__mux_tree_tapbuf_size8_2 mux_right_ipin_13 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , - chany_bottom_in[17] , chany_top_in[17] } ) , - .sram ( mux_tree_tapbuf_size8_6_sram ) , - .sram_inv ( mux_right_ipin_13_undriven_sram_inv ) , - .out ( left_grid_pin_29_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_105 ) ) ; -cby_1__1__mux_tree_tapbuf_size8_3 mux_right_ipin_14 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , - chany_bottom_in[18] , chany_top_in[18] } ) , - .sram ( mux_tree_tapbuf_size8_7_sram ) , - .sram_inv ( mux_right_ipin_14_undriven_sram_inv ) , - .out ( left_grid_pin_30_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_106 ) ) ; -cby_1__1__mux_tree_tapbuf_size8_mem_0 mem_right_ipin_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cby_1__1__mux_tree_tapbuf_size8_mem_4 mem_right_ipin_2 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cby_1__1__mux_tree_tapbuf_size8_mem_5 mem_right_ipin_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cby_1__1__mux_tree_tapbuf_size8_mem_6 mem_right_ipin_6 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cby_1__1__mux_tree_tapbuf_size8_mem mem_right_ipin_9 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cby_1__1__mux_tree_tapbuf_size8_mem_1 mem_right_ipin_10 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cby_1__1__mux_tree_tapbuf_size8_mem_2 mem_right_ipin_13 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cby_1__1__mux_tree_tapbuf_size8_mem_3 mem_right_ipin_14 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1652 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1653 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1654 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1655 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1656 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1657 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1658 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1659 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1660 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1661 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1662 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1663 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1664 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1665 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1666 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_bottom_in[0] ) , - .X ( chany_top_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chany_bottom_in[1] ) , - .X ( chany_top_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_bottom_in[3] ) , - .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_757 ( .A ( ropt_net_125 ) , - .X ( chany_bottom_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_bottom_in[6] ) , - .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_758 ( .A ( ropt_net_126 ) , - .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chany_bottom_in[8] ) , - .X ( ropt_net_118 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chany_bottom_in[9] ) , - .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chany_bottom_in[10] ) , - .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chany_bottom_in[12] ) , - .X ( chany_top_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chany_bottom_in[13] ) , - .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_127 ) , - .X ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__16 ( .A ( chany_bottom_in[16] ) , - .X ( ropt_net_119 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_760 ( .A ( ropt_net_128 ) , - .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chany_bottom_in[18] ) , - .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_20__19 ( .A ( chany_bottom_in[19] ) , - .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chany_top_in[0] ) , - .X ( chany_bottom_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_2 \prog_clk[0]_bip372 ( .A ( prog_clk[0] ) , - .X ( ctsbuf_net_1107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( chany_top_in[11] ) , - .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chany_top_in[3] ) , - .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__24 ( .A ( chany_top_in[4] ) , - .X ( ropt_net_124 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_116 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chany_top_in[6] ) , - .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chany_top_in[7] ) , - .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_29__28 ( .A ( chany_top_in[8] ) , - .X ( chany_bottom_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_325697 ( .A ( ctsbuf_net_1107 ) , - .X ( prog_clk__FEEDTHRU_2[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_31__30 ( .A ( chany_top_in[10] ) , - .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( ropt_net_129 ) , - .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_326698 ( .A ( ctsbuf_net_1107 ) , - .X ( prog_clk__FEEDTHRU_1[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_110 ) , - .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_728 ( - .A ( chany_bottom_in[17] ) , .X ( chany_top_out[17] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_729 ( .A ( chany_bottom_in[4] ) , - .X ( chany_top_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_730 ( .A ( chany_bottom_in[5] ) , - .X ( ropt_net_126 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_130 ) , - .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_39__38 ( .A ( chany_top_in[18] ) , - .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( .A ( chany_top_in[17] ) , - .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_59 ( .A ( chany_bottom_in[2] ) , - .X ( chany_top_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_766 ( .A ( ropt_net_131 ) , - .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_768 ( .A ( ropt_net_132 ) , - .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_63 ( .A ( chany_bottom_in[14] ) , - .X ( ropt_net_117 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( - .A ( chany_bottom_in[11] ) , .X ( ropt_net_130 ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_116 ) , - .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_68 ( .A ( chany_top_in[13] ) , - .X ( BUF_net_68 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( .A ( chany_top_in[15] ) , - .X ( BUF_net_69 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_70 ( .A ( chany_top_in[16] ) , - .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_117 ) , - .X ( ropt_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_75 ( .A ( chany_bottom_in[7] ) , - .X ( ropt_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_76 ( .A ( chany_bottom_in[15] ) , - .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( ropt_net_118 ) , - .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_119 ) , - .X ( ropt_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_120 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_121 ) , - .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( chany_top_in[2] ) , - .X ( chany_bottom_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_87 ( .A ( chany_top_in[9] ) , - .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_88 ( .A ( chany_top_in[14] ) , - .X ( ropt_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_93 ( .A ( BUF_net_68 ) , - .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_94 ( .A ( BUF_net_69 ) , - .X ( ropt_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_95 ( .A ( chany_top_in[19] ) , - .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( chany_top_in[12] ) , - .X ( ropt_net_125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( chany_top_in[1] ) , - .X ( ropt_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_124 ) , - .X ( ropt_net_127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y0 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y0 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x36800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x151800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x312800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x331200y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x575000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x584200y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x174800y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x225400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x211600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x230000y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x36800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x446200y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x533600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x552000y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x598000y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x450800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x501400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x510600y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x556600y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x55200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x105800y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x602600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x128800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x138000y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x368000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x386400y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x197800y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x515200y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x64400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x147200y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x193200y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x289800y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x82800y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x161000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x55200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x115000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x133400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x243800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x285200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x294400y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x469200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x547400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x556600y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x36800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x87400y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x207000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x225400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x483000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x501400y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x312800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x349600y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x552000y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x184000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x234600y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x354200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x409400y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x455400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x464600y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x542800y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x588800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x607200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x616400y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x101200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x151800y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x478400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x128800y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x174800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x225400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x243800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x294400y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x36800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x455400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x174800y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x101200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x110400y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x197800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x409400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x418600y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x105800y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x326600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x575000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x101200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x119600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_0__1__direct_interc ( in , out ) ; -input [0:0] in ; -output [0:0] out ; - -assign out[0] = in[0] ; -endmodule - - -module cby_0__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( prog_clk , - ccff_head , ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:0] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__44 ( .A ( mem_out[0] ) , - .X ( net_net_86 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_163 ( .A ( net_net_86 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_0__1__EMBEDDED_IO ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , - FPGA_OUT , FPGA_DIR , p_abuf0 , p_abuf1 , VDD , VSS ) ; -input SOC_IN ; -output SOC_OUT ; -output SOC_DIR ; -output FPGA_IN ; -input FPGA_OUT ; -input FPGA_DIR ; -output p_abuf0 ; -output p_abuf1 ; -input VDD ; -input VSS ; - -supply1 VDD ; -wire aps_rename_2_ ; -supply0 VSS ; - -assign SOC_OUT = FPGA_OUT ; - -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__42 ( .A ( SOC_IN ) , .X ( p_abuf1 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__43 ( .A ( FPGA_DIR ) , - .X ( aps_rename_2_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_45 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_46 ( .A ( p_abuf1 ) , - .X ( BUF_net_46 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_128 ( .A ( BUF_net_46 ) , - .X ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_162 ( .A ( aps_rename_2_ ) , - .X ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_0__1__logical_tile_io_mode_physical__iopad ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] iopad_outpad ; -input [0:0] ccff_head ; -output [0:0] iopad_inpad ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; -output p_abuf0 ; -output p_abuf1 ; - -wire [0:0] EMBEDDED_IO_0_en ; -supply1 VDD ; -supply0 VSS ; - -cby_0__1__EMBEDDED_IO EMBEDDED_IO_0_ ( - .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , - .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , - .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , - .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , - .p_abuf1 ( p_abuf1 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cby_0__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -endmodule - - -module cby_0__1__logical_tile_io_mode_io_ ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , - ccff_tail , VDD , VSS , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] io_outpad ; -input [0:0] ccff_head ; -output [0:0] io_inpad ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; -output p_abuf0 ; - -supply1 VDD ; -supply0 VSS ; - -cby_0__1__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , - .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , - .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; -cby_0__1__direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( { p_abuf1 } ) ) ; -cby_0__1__direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( io_outpad ) ) ; -endmodule - - -module cby_0__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__41 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_0__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_0__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , - chany_bottom_out , chany_top_out , left_grid_pin_0_ , ccff_tail , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , right_width_0_height_0__pin_0_ , - right_width_0_height_0__pin_1_upper , - right_width_0_height_0__pin_1_lower , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:19] chany_bottom_in ; -input [0:19] chany_top_in ; -input [0:0] ccff_head ; -output [0:19] chany_bottom_out ; -output [0:19] chany_top_out ; -output [0:0] left_grid_pin_0_ ; -output [0:0] ccff_tail ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] right_width_0_height_0__pin_0_ ; -output [0:0] right_width_0_height_0__pin_1_upper ; -output [0:0] right_width_0_height_0__pin_1_lower ; -input VDD ; -input VSS ; - -wire ropt_net_168 ; -wire [0:3] mux_right_ipin_0_undriven_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_0_sram ; -supply1 VDD ; -supply0 VSS ; - -cby_0__1__mux_tree_tapbuf_size10 mux_right_ipin_0 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , - chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , - chany_top_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_right_ipin_0_undriven_sram_inv ) , - .out ( left_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_164 ) ) ; -cby_0__1__mux_tree_tapbuf_size10_mem mem_right_ipin_0 ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( { ccff_tail_mid } ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cby_0__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_178 } ) , - .io_outpad ( right_width_0_height_0__pin_0_ ) , - .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_8_ } ) , - .ccff_tail ( { ropt_net_170 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( ropt_net_168 ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1636 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1637 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1638 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1639 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1640 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1641 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1642 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1643 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1644 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1645 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1646 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1647 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1648 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1649 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1650 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__conb_1 optlc_165 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_164 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_165 ) , - .X ( ropt_net_210 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_745 ( - .A ( chany_bottom_in[10] ) , .X ( ropt_net_233 ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_167 ) , - .X ( right_width_0_height_0__pin_1_lower[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( ropt_net_168 ) , - .X ( right_width_0_height_0__pin_1_upper[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_169 ) , - .X ( ropt_net_211 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_749 ( .A ( ropt_net_170 ) , - .X ( ropt_net_223 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_171 ) , - .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_751 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_226 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_786 ( .A ( ropt_net_205 ) , - .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_206 ) , - .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_752 ( .A ( chany_bottom_in[1] ) , - .X ( ropt_net_235 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_753 ( - .A ( chany_bottom_in[14] ) , .X ( ropt_net_231 ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_754 ( .A ( chany_bottom_in[7] ) , - .X ( ropt_net_230 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_755 ( - .A ( chany_bottom_in[16] ) , .X ( ropt_net_228 ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_756 ( .A ( chany_top_in[13] ) , - .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_757 ( .A ( ropt_net_178 ) , - .X ( ropt_net_224 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_758 ( - .A ( chany_bottom_in[18] ) , .X ( ropt_net_234 ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_759 ( .A ( chany_top_in[18] ) , - .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_760 ( .A ( chany_top_in[9] ) , - .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chany_top_in[0] ) , - .X ( chany_bottom_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( .A ( chany_bottom_in[5] ) , - .X ( ropt_net_227 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( chany_top_in[7] ) , - .X ( ropt_net_225 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_184 ) , - .X ( ropt_net_212 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_764 ( .A ( chany_top_in[6] ) , - .X ( ropt_net_229 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_186 ) , - .X ( ropt_net_205 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_187 ) , - .X ( ropt_net_214 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_232 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_207 ) , - .X ( chany_bottom_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_189 ) , - .X ( ropt_net_215 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_31__30 ( .A ( chany_top_in[10] ) , - .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( ropt_net_208 ) , - .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( ropt_net_209 ) , - .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_190 ) , - .X ( ropt_net_209 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_191 ) , - .X ( ropt_net_220 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_192 ) , - .X ( ropt_net_213 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_37__36 ( .A ( chany_top_in[16] ) , - .X ( ropt_net_202 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_193 ) , - .X ( ropt_net_208 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_194 ) , - .X ( ropt_net_217 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_195 ) , - .X ( ropt_net_206 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_196 ) , - .X ( ropt_net_218 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_47 ( .A ( chany_bottom_in[0] ) , - .X ( ropt_net_189 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( ropt_net_210 ) , - .X ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_197 ) , - .X ( ropt_net_216 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_198 ) , - .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_51 ( .A ( chany_bottom_in[4] ) , - .X ( ropt_net_191 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( ropt_net_211 ) , - .X ( chany_bottom_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_53 ( .A ( chany_bottom_in[6] ) , - .X ( ropt_net_192 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_212 ) , - .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( ropt_net_213 ) , - .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_795 ( .A ( ropt_net_214 ) , - .X ( chany_top_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( ropt_net_215 ) , - .X ( chany_top_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_58 ( .A ( chany_bottom_in[11] ) , - .X ( ropt_net_186 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_59 ( .A ( chany_bottom_in[12] ) , - .X ( ropt_net_187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_60 ( .A ( chany_bottom_in[13] ) , - .X ( ropt_net_196 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_216 ) , - .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_62 ( .A ( chany_bottom_in[15] ) , - .X ( ropt_net_184 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_800 ( .A ( ropt_net_217 ) , - .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_199 ) , - .X ( ropt_net_219 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_218 ) , - .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_200 ) , - .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_201 ) , - .X ( ropt_net_222 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_68 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_203 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_69 ( .A ( chany_top_in[3] ) , - .X ( ropt_net_201 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_802 ( .A ( ropt_net_219 ) , - .X ( chany_top_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_202 ) , - .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_803 ( .A ( ropt_net_220 ) , - .X ( chany_top_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_804 ( .A ( ropt_net_221 ) , - .X ( chany_bottom_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_74 ( .A ( chany_top_in[8] ) , - .X ( BUF_net_74 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_203 ) , - .X ( ropt_net_207 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( ropt_net_222 ) , - .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_223 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_224 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_79 ( .A ( chany_top_in[14] ) , - .X ( ropt_net_190 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_80 ( .A ( chany_top_in[15] ) , - .X ( ropt_net_194 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_81 ( .A ( chany_top_in[17] ) , - .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_817 ( .A ( ropt_net_225 ) , - .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_226 ) , - .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_227 ) , - .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_228 ) , - .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_229 ) , - .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_230 ) , - .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_231 ) , - .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( ropt_net_232 ) , - .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_826 ( .A ( ropt_net_233 ) , - .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_827 ( .A ( ropt_net_234 ) , - .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_235 ) , - .X ( chany_top_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_96 ( .A ( chany_bottom_in[8] ) , - .X ( BUF_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_108 ( .A ( chany_top_in[1] ) , - .X ( ropt_net_200 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y0 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_121 ( .A ( chany_top_in[19] ) , - .X ( ropt_net_198 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_122 ( .A ( aps_rename_8_ ) , - .X ( ropt_net_167 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_125 ( .A ( BUF_net_74 ) , - .X ( ropt_net_221 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_126 ( .A ( chany_top_in[11] ) , - .X ( ropt_net_171 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_127 ( .A ( chany_top_in[12] ) , - .X ( ropt_net_169 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y0 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_131 ( .A ( chany_bottom_in[2] ) , - .X ( ropt_net_199 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_132 ( .A ( chany_bottom_in[3] ) , - .X ( ropt_net_195 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x184000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_137 ( .A ( BUF_net_96 ) , - .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x193200y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x446200y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_144 ( .A ( chany_bottom_in[17] ) , - .X ( ropt_net_193 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_146 ( .A ( chany_bottom_in[19] ) , - .X ( ropt_net_197 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x165600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x202400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_150 ( .A ( chany_top_in[4] ) , - .X ( ropt_net_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x202400y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x400200y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x184000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x193200y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x225400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x243800y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x492200y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x294400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x354200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x441600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x570400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x588800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x294400y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x340400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x377200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x414000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x450800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x487600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x524400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x533600y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x55200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x101200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x138000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x174800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x211600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x248400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x322000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x358800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x404800y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x450800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x487600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x561200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x570400y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x257600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x276000y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x354200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x220800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x239200y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x354200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x372600y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x418600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x455400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x492200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x529000y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x92000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x128800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x165600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x202400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x239200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x276000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x285200y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x326600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x363400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x501400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x519800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x644000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x473800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x510600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x547400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x584200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x368000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x386400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x395600y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x473800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x510600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x547400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x584200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x478400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x561200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x570400y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x409400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x455400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x492200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x529000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x565800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x584200y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x294400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x349600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x464600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x556600y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x36800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x46000y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x124200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x161000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x197800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x234600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x271400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x345000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x381800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x418600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x455400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x547400y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x220800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x239200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x248400y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x538200y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x119600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x128800y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x170200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x207000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x216200y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x55200y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x437000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x446200y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x36800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__2__direct_interc ( in , out ) ; -input [0:0] in ; -output [0:0] out ; - -assign out[0] = in[0] ; -endmodule - - -module cbx_1__2__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( prog_clk , - ccff_head , ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:0] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_20__61 ( .A ( mem_out[0] ) , - .X ( net_net_76 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_76 ( .A ( net_net_76 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__2__EMBEDDED_IO ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , - FPGA_OUT , FPGA_DIR , p_abuf0 , VDD , VSS ) ; -input SOC_IN ; -output SOC_OUT ; -output SOC_DIR ; -output FPGA_IN ; -input FPGA_OUT ; -input FPGA_DIR ; -output p_abuf0 ; -input VDD ; -input VSS ; - -supply1 VDD ; -wire aps_rename_1_ ; -supply0 VSS ; - -assign SOC_OUT = FPGA_OUT ; - -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__59 ( .A ( SOC_IN ) , .X ( FPGA_IN ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__60 ( .A ( FPGA_DIR ) , - .X ( aps_rename_1_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_75 ( .A ( aps_rename_1_ ) , - .X ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_63 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__2__logical_tile_io_mode_physical__iopad ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , VDD , VSS , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] iopad_outpad ; -input [0:0] ccff_head ; -output [0:0] iopad_inpad ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; -output p_abuf0 ; - -wire [0:0] EMBEDDED_IO_0_en ; -supply1 VDD ; -supply0 VSS ; - -cbx_1__2__EMBEDDED_IO EMBEDDED_IO_0_ ( - .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , - .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , - .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , - .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -cbx_1__2__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -endmodule - - -module cbx_1__2__logical_tile_io_mode_io_ ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , - ccff_tail , VDD , VSS , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] io_outpad ; -input [0:0] ccff_head ; -output [0:0] io_inpad ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; -output p_abuf0 ; - -supply1 VDD ; -supply0 VSS ; - -cbx_1__2__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , - .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , - .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__2__direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( io_outpad ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__58 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__57 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__56 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__55 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__54 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__53 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__52 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__51 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__50 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__49 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__48 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__47 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__46 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__45 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__44 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__43 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__42 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_64 ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__2_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , - chanx_left_out , chanx_right_out , top_grid_pin_0_ , bottom_grid_pin_0_ , - bottom_grid_pin_1_ , bottom_grid_pin_2_ , bottom_grid_pin_3_ , - bottom_grid_pin_4_ , bottom_grid_pin_5_ , bottom_grid_pin_6_ , - bottom_grid_pin_7_ , bottom_grid_pin_8_ , bottom_grid_pin_9_ , - bottom_grid_pin_10_ , bottom_grid_pin_11_ , bottom_grid_pin_12_ , - bottom_grid_pin_13_ , bottom_grid_pin_14_ , bottom_grid_pin_15_ , - ccff_tail , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , bottom_width_0_height_0__pin_0_ , - bottom_width_0_height_0__pin_1_upper , - bottom_width_0_height_0__pin_1_lower , SC_IN_TOP , SC_IN_BOT , - SC_OUT_TOP , SC_OUT_BOT , VDD , VSS , prog_clk__FEEDTHRU_1 , - prog_clk__FEEDTHRU_2 ) ; -input [0:0] prog_clk ; -input [0:19] chanx_left_in ; -input [0:19] chanx_right_in ; -input [0:0] ccff_head ; -output [0:19] chanx_left_out ; -output [0:19] chanx_right_out ; -output [0:0] top_grid_pin_0_ ; -output [0:0] bottom_grid_pin_0_ ; -output [0:0] bottom_grid_pin_1_ ; -output [0:0] bottom_grid_pin_2_ ; -output [0:0] bottom_grid_pin_3_ ; -output [0:0] bottom_grid_pin_4_ ; -output [0:0] bottom_grid_pin_5_ ; -output [0:0] bottom_grid_pin_6_ ; -output [0:0] bottom_grid_pin_7_ ; -output [0:0] bottom_grid_pin_8_ ; -output [0:0] bottom_grid_pin_9_ ; -output [0:0] bottom_grid_pin_10_ ; -output [0:0] bottom_grid_pin_11_ ; -output [0:0] bottom_grid_pin_12_ ; -output [0:0] bottom_grid_pin_13_ ; -output [0:0] bottom_grid_pin_14_ ; -output [0:0] bottom_grid_pin_15_ ; -output [0:0] ccff_tail ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] bottom_width_0_height_0__pin_0_ ; -output [0:0] bottom_width_0_height_0__pin_1_upper ; -output [0:0] bottom_width_0_height_0__pin_1_lower ; -input SC_IN_TOP ; -input SC_IN_BOT ; -output SC_OUT_TOP ; -output SC_OUT_BOT ; -input VDD ; -input VSS ; -output [0:0] prog_clk__FEEDTHRU_1 ; -output [0:0] prog_clk__FEEDTHRU_2 ; - -wire ropt_net_112 ; -wire [0:3] mux_bottom_ipin_0_undriven_sram_inv ; -wire [0:3] mux_top_ipin_0_undriven_sram_inv ; -wire [0:3] mux_top_ipin_10_undriven_sram_inv ; -wire [0:3] mux_top_ipin_11_undriven_sram_inv ; -wire [0:3] mux_top_ipin_12_undriven_sram_inv ; -wire [0:3] mux_top_ipin_13_undriven_sram_inv ; -wire [0:3] mux_top_ipin_14_undriven_sram_inv ; -wire [0:3] mux_top_ipin_15_undriven_sram_inv ; -wire [0:3] mux_top_ipin_1_undriven_sram_inv ; -wire [0:3] mux_top_ipin_2_undriven_sram_inv ; -wire [0:3] mux_top_ipin_3_undriven_sram_inv ; -wire [0:3] mux_top_ipin_4_undriven_sram_inv ; -wire [0:3] mux_top_ipin_5_undriven_sram_inv ; -wire [0:3] mux_top_ipin_6_undriven_sram_inv ; -wire [0:3] mux_top_ipin_7_undriven_sram_inv ; -wire [0:3] mux_top_ipin_8_undriven_sram_inv ; -wire [0:3] mux_top_ipin_9_undriven_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:3] mux_tree_tapbuf_size10_2_sram ; -wire [0:3] mux_tree_tapbuf_size10_3_sram ; -wire [0:3] mux_tree_tapbuf_size10_4_sram ; -wire [0:3] mux_tree_tapbuf_size10_5_sram ; -wire [0:3] mux_tree_tapbuf_size10_6_sram ; -wire [0:3] mux_tree_tapbuf_size10_7_sram ; -wire [0:3] mux_tree_tapbuf_size10_8_sram ; -wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:3] mux_tree_tapbuf_size8_2_sram ; -wire [0:3] mux_tree_tapbuf_size8_3_sram ; -wire [0:3] mux_tree_tapbuf_size8_4_sram ; -wire [0:3] mux_tree_tapbuf_size8_5_sram ; -wire [0:3] mux_tree_tapbuf_size8_6_sram ; -wire [0:3] mux_tree_tapbuf_size8_7_sram ; -wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ; -supply1 VDD ; -supply0 VSS ; - -assign SC_IN_TOP = SC_IN_BOT ; - -cbx_1__2__mux_tree_tapbuf_size10_0 mux_bottom_ipin_0 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , - chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , - chanx_right_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_bottom_ipin_0_undriven_sram_inv ) , - .out ( top_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_108 ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_1 mux_top_ipin_0 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , - chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , - chanx_right_in[17] } ) , - .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_top_ipin_0_undriven_sram_inv ) , - .out ( bottom_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_108 ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_5 mux_top_ipin_3 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , - chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[14] , - chanx_right_in[14] } ) , - .sram ( mux_tree_tapbuf_size10_2_sram ) , - .sram_inv ( mux_top_ipin_3_undriven_sram_inv ) , - .out ( { ropt_net_117 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_107 ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_6 mux_top_ipin_4 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , - chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[15] , - chanx_right_in[15] } ) , - .sram ( mux_tree_tapbuf_size10_3_sram ) , - .sram_inv ( mux_top_ipin_4_undriven_sram_inv ) , - .out ( bottom_grid_pin_4_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_108 ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_7 mux_top_ipin_7 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[8] , chanx_right_in[8] , - chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , - chanx_right_in[18] } ) , - .sram ( mux_tree_tapbuf_size10_4_sram ) , - .sram_inv ( mux_top_ipin_7_undriven_sram_inv ) , - .out ( bottom_grid_pin_7_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_107 ) ) ; -cbx_1__2__mux_tree_tapbuf_size10 mux_top_ipin_8 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , - chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , - chanx_right_in[19] } ) , - .sram ( mux_tree_tapbuf_size10_5_sram ) , - .sram_inv ( mux_top_ipin_8_undriven_sram_inv ) , - .out ( bottom_grid_pin_8_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_106 ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_2 mux_top_ipin_11 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , - chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[16] , - chanx_right_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_6_sram ) , - .sram_inv ( mux_top_ipin_11_undriven_sram_inv ) , - .out ( bottom_grid_pin_11_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_106 ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_3 mux_top_ipin_12 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , - chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[17] , - chanx_right_in[17] } ) , - .sram ( mux_tree_tapbuf_size10_7_sram ) , - .sram_inv ( mux_top_ipin_12_undriven_sram_inv ) , - .out ( bottom_grid_pin_12_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_108 ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_4 mux_top_ipin_15 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , - chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , - chanx_right_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_8_sram ) , - .sram_inv ( mux_top_ipin_15_undriven_sram_inv ) , - .out ( bottom_grid_pin_15_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_108 ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_mem_0 mem_bottom_ipin_0 ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_0 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_mem_5 mem_top_ipin_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_mem_6 mem_top_ipin_4 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_mem_7 mem_top_ipin_7 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_mem mem_top_ipin_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_11 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_12 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_15 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , - .mem_out ( mux_tree_tapbuf_size10_8_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_0 mux_top_ipin_1 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , - chanx_left_in[14] , chanx_right_in[14] } ) , - .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_top_ipin_1_undriven_sram_inv ) , - .out ( bottom_grid_pin_1_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_109 ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_4 mux_top_ipin_2 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , - chanx_left_in[15] , chanx_right_in[15] } ) , - .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_top_ipin_2_undriven_sram_inv ) , - .out ( bottom_grid_pin_2_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_106 ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_5 mux_top_ipin_5 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , - chanx_left_in[18] , chanx_right_in[18] } ) , - .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_top_ipin_5_undriven_sram_inv ) , - .out ( bottom_grid_pin_5_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_107 ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_6 mux_top_ipin_6 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , - chanx_left_in[19] , chanx_right_in[19] } ) , - .sram ( mux_tree_tapbuf_size8_3_sram ) , - .sram_inv ( mux_top_ipin_6_undriven_sram_inv ) , - .out ( bottom_grid_pin_6_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_107 ) ) ; -cbx_1__2__mux_tree_tapbuf_size8 mux_top_ipin_9 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , - chanx_left_in[14] , chanx_right_in[14] } ) , - .sram ( mux_tree_tapbuf_size8_4_sram ) , - .sram_inv ( mux_top_ipin_9_undriven_sram_inv ) , - .out ( bottom_grid_pin_9_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_109 ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_1 mux_top_ipin_10 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , - chanx_left_in[15] , chanx_right_in[15] } ) , - .sram ( mux_tree_tapbuf_size8_5_sram ) , - .sram_inv ( mux_top_ipin_10_undriven_sram_inv ) , - .out ( bottom_grid_pin_10_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_106 ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_2 mux_top_ipin_13 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , - chanx_left_in[18] , chanx_right_in[18] } ) , - .sram ( mux_tree_tapbuf_size8_6_sram ) , - .sram_inv ( mux_top_ipin_13_undriven_sram_inv ) , - .out ( bottom_grid_pin_13_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_107 ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_3 mux_top_ipin_14 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , - chanx_left_in[19] , chanx_right_in[19] } ) , - .sram ( mux_tree_tapbuf_size8_7_sram ) , - .sram_inv ( mux_top_ipin_14_undriven_sram_inv ) , - .out ( bottom_grid_pin_14_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_106 ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_mem_0 mem_top_ipin_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_mem_4 mem_top_ipin_2 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_mem_5 mem_top_ipin_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_mem_6 mem_top_ipin_6 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_mem mem_top_ipin_9 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_mem_1 mem_top_ipin_10 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_mem_2 mem_top_ipin_13 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_mem_3 mem_top_ipin_14 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__2__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_114 } ) , - .io_outpad ( bottom_width_0_height_0__pin_0_ ) , - .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_3_ } ) , - .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf0 ( ropt_net_112 ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1618 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1619 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1620 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1621 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1622 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1623 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1624 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1625 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1626 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1627 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1628 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1629 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1630 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1631 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1632 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1633 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1634 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chanx_left_in[1] ) , - .X ( chanx_right_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , - .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chanx_left_in[4] ) , - .X ( chanx_right_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chanx_left_in[5] ) , - .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chanx_left_in[6] ) , - .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chanx_left_in[7] ) , - .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chanx_left_in[9] ) , - .X ( ropt_net_130 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_12__11 ( .A ( chanx_left_in[11] ) , - .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chanx_left_in[12] ) , - .X ( chanx_right_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_2 \prog_clk[0]_bip377 ( .A ( prog_clk[0] ) , - .X ( ctsbuf_net_2111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chanx_left_in[14] ) , - .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_112 ) , - .X ( ropt_net_137 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_330707 ( .A ( ctsbuf_net_2111 ) , - .X ( prog_clk__FEEDTHRU_1[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chanx_left_in[17] ) , - .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_20__19 ( .A ( chanx_left_in[19] ) , - .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_right_in[0] ) , - .X ( ropt_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , - .X ( ropt_net_134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chanx_right_in[2] ) , - .X ( ropt_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chanx_right_in[3] ) , - .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__24 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chanx_right_in[5] ) , - .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_331708 ( .A ( ctsbuf_net_2111 ) , - .X ( prog_clk__FEEDTHRU_2[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chanx_right_in[7] ) , - .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( .A ( chanx_right_in[6] ) , - .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_114 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( ropt_net_115 ) , - .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_138 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_33__32 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_117 ) , - .X ( ropt_net_141 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_137 ) , - .X ( bottom_width_0_height_0__pin_1_upper[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_741 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_37__36 ( .A ( chanx_right_in[16] ) , - .X ( chanx_left_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_119 ) , - .X ( chanx_right_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_39__38 ( .A ( chanx_right_in[18] ) , - .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_40__39 ( .A ( chanx_right_in[19] ) , - .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_41__40 ( .A ( aps_rename_3_ ) , - .X ( ropt_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_42__41 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_115 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_66 ( .A ( chanx_left_in[0] ) , - .X ( chanx_right_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_744 ( .A ( chanx_right_in[14] ) , - .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_138 ) , - .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( ropt_net_139 ) , - .X ( chanx_left_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_121 ) , - .X ( ropt_net_142 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_780 ( .A ( ropt_net_140 ) , - .X ( chanx_left_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_785 ( .A ( ropt_net_141 ) , - .X ( bottom_grid_pin_3_[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_786 ( .A ( ropt_net_142 ) , - .X ( bottom_width_0_height_0__pin_1_lower[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_143 ) , - .X ( chanx_left_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_139 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_79 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_119 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_750 ( .A ( chanx_left_in[13] ) , - .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_124 ) , - .X ( ropt_net_145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_752 ( .A ( chanx_left_in[16] ) , - .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( ropt_net_144 ) , - .X ( chanx_right_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_753 ( .A ( chanx_left_in[10] ) , - .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_88 ( .A ( chanx_left_in[15] ) , - .X ( ropt_net_124 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( ropt_net_145 ) , - .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_90 ( .A ( chanx_right_in[9] ) , - .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_146 ) , - .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_92 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_93 ( .A ( chanx_right_in[13] ) , - .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_94 ( .A ( chanx_right_in[15] ) , - .X ( ropt_net_135 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_96 ( .A ( chanx_left_in[2] ) , - .X ( ropt_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_754 ( .A ( ropt_net_127 ) , - .X ( chanx_left_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_147 ) , - .X ( chanx_left_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_128 ) , - .X ( ropt_net_144 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_129 ) , - .X ( ropt_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_130 ) , - .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_131 ) , - .X ( chanx_left_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_132 ) , - .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_133 ) , - .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_134 ) , - .X ( ropt_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_135 ) , - .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y0 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y0 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x266800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x303600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x349600y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x437000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x483000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x584200y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x243800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x289800y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x368000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x414000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x460000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x496800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x515200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x524400y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x170200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x188600y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x391000y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x584200y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x147200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x207000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x308200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x317400y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x478400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x538200y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x73600y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x225400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x285200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x294400y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x400200y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x455400y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x322000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x202400y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x289800y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x579600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x73600y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x119600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x211600y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x561200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x579600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x197800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x234600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x441600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x492200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x510600y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x529000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x538200y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x161000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x179400y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x409400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x575000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x584200y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x73600y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x253000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x271400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x322000y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x455400y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x579600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x326600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x243800y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x289800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x432400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x409400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x156400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x239200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x73600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x82800y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x234600y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x542800y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x151800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x161000y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x322000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x358800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x400200y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x441600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x450800y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x496800y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x193200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x202400y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x478400y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x225400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x404800y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x455400y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x501400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x519800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x529000y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x225400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x262200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x271400y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x354200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x363400y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x409400y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x487600y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x119600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x506000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x515200y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x561200y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x644000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x202400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x220800y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x266800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x358800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x423200y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x469200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x570400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x588800y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x184000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x234600y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x312800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x331200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x432400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x552000y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x285200y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x423200y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x542800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x243800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x253000y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x400200y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x515200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x524400y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x602600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x639400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x593400y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__56 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__55 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__54 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__53 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__52 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__51 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__50 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__49 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__48 ( .A ( mem_out[3] ) , - .X ( net_net_72 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_90 ( .A ( net_net_72 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__47 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__46 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__45 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__44 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__43 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__42 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__41 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__1_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , - chanx_left_out , chanx_right_out , bottom_grid_pin_0_ , - bottom_grid_pin_1_ , bottom_grid_pin_2_ , bottom_grid_pin_3_ , - bottom_grid_pin_4_ , bottom_grid_pin_5_ , bottom_grid_pin_6_ , - bottom_grid_pin_7_ , bottom_grid_pin_8_ , bottom_grid_pin_9_ , - bottom_grid_pin_10_ , bottom_grid_pin_11_ , bottom_grid_pin_12_ , - bottom_grid_pin_13_ , bottom_grid_pin_14_ , bottom_grid_pin_15_ , - ccff_tail , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , SC_OUT_BOT , VDD , VSS , - prog_clk__FEEDTHRU_1 ) ; -input [0:0] prog_clk ; -input [0:19] chanx_left_in ; -input [0:19] chanx_right_in ; -input [0:0] ccff_head ; -output [0:19] chanx_left_out ; -output [0:19] chanx_right_out ; -output [0:0] bottom_grid_pin_0_ ; -output [0:0] bottom_grid_pin_1_ ; -output [0:0] bottom_grid_pin_2_ ; -output [0:0] bottom_grid_pin_3_ ; -output [0:0] bottom_grid_pin_4_ ; -output [0:0] bottom_grid_pin_5_ ; -output [0:0] bottom_grid_pin_6_ ; -output [0:0] bottom_grid_pin_7_ ; -output [0:0] bottom_grid_pin_8_ ; -output [0:0] bottom_grid_pin_9_ ; -output [0:0] bottom_grid_pin_10_ ; -output [0:0] bottom_grid_pin_11_ ; -output [0:0] bottom_grid_pin_12_ ; -output [0:0] bottom_grid_pin_13_ ; -output [0:0] bottom_grid_pin_14_ ; -output [0:0] bottom_grid_pin_15_ ; -output [0:0] ccff_tail ; -input SC_IN_TOP ; -input SC_IN_BOT ; -output SC_OUT_TOP ; -output SC_OUT_BOT ; -input VDD ; -input VSS ; -output [0:0] prog_clk__FEEDTHRU_1 ; - -wire [0:3] mux_top_ipin_0_undriven_sram_inv ; -wire [0:3] mux_top_ipin_10_undriven_sram_inv ; -wire [0:3] mux_top_ipin_11_undriven_sram_inv ; -wire [0:3] mux_top_ipin_12_undriven_sram_inv ; -wire [0:3] mux_top_ipin_13_undriven_sram_inv ; -wire [0:3] mux_top_ipin_14_undriven_sram_inv ; -wire [0:3] mux_top_ipin_15_undriven_sram_inv ; -wire [0:3] mux_top_ipin_1_undriven_sram_inv ; -wire [0:3] mux_top_ipin_2_undriven_sram_inv ; -wire [0:3] mux_top_ipin_3_undriven_sram_inv ; -wire [0:3] mux_top_ipin_4_undriven_sram_inv ; -wire [0:3] mux_top_ipin_5_undriven_sram_inv ; -wire [0:3] mux_top_ipin_6_undriven_sram_inv ; -wire [0:3] mux_top_ipin_7_undriven_sram_inv ; -wire [0:3] mux_top_ipin_8_undriven_sram_inv ; -wire [0:3] mux_top_ipin_9_undriven_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:3] mux_tree_tapbuf_size10_2_sram ; -wire [0:3] mux_tree_tapbuf_size10_3_sram ; -wire [0:3] mux_tree_tapbuf_size10_4_sram ; -wire [0:3] mux_tree_tapbuf_size10_5_sram ; -wire [0:3] mux_tree_tapbuf_size10_6_sram ; -wire [0:3] mux_tree_tapbuf_size10_7_sram ; -wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:3] mux_tree_tapbuf_size8_2_sram ; -wire [0:3] mux_tree_tapbuf_size8_3_sram ; -wire [0:3] mux_tree_tapbuf_size8_4_sram ; -wire [0:3] mux_tree_tapbuf_size8_5_sram ; -wire [0:3] mux_tree_tapbuf_size8_6_sram ; -wire [0:3] mux_tree_tapbuf_size8_7_sram ; -wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ; -supply1 VDD ; -supply0 VSS ; - -assign SC_IN_TOP = SC_IN_BOT ; - -cbx_1__1__mux_tree_tapbuf_size10_0 mux_top_ipin_0 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , - chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , - chanx_right_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_top_ipin_0_undriven_sram_inv ) , - .out ( bottom_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_104 ) ) ; -cbx_1__1__mux_tree_tapbuf_size10_4 mux_top_ipin_3 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , - chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , - chanx_right_in[19] } ) , - .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_top_ipin_3_undriven_sram_inv ) , - .out ( bottom_grid_pin_3_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_105 ) ) ; -cbx_1__1__mux_tree_tapbuf_size10_5 mux_top_ipin_4 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , - chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[14] , - chanx_right_in[14] } ) , - .sram ( mux_tree_tapbuf_size10_2_sram ) , - .sram_inv ( mux_top_ipin_4_undriven_sram_inv ) , - .out ( bottom_grid_pin_4_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_102 ) ) ; -cbx_1__1__mux_tree_tapbuf_size10_6 mux_top_ipin_7 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , - chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , - chanx_right_in[17] } ) , - .sram ( mux_tree_tapbuf_size10_3_sram ) , - .sram_inv ( mux_top_ipin_7_undriven_sram_inv ) , - .out ( bottom_grid_pin_7_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_104 ) ) ; -cbx_1__1__mux_tree_tapbuf_size10 mux_top_ipin_8 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[8] , chanx_right_in[8] , - chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , - chanx_right_in[18] } ) , - .sram ( mux_tree_tapbuf_size10_4_sram ) , - .sram_inv ( mux_top_ipin_8_undriven_sram_inv ) , - .out ( bottom_grid_pin_8_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_103 ) ) ; -cbx_1__1__mux_tree_tapbuf_size10_1 mux_top_ipin_11 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , - chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[15] , - chanx_right_in[15] } ) , - .sram ( mux_tree_tapbuf_size10_5_sram ) , - .sram_inv ( mux_top_ipin_11_undriven_sram_inv ) , - .out ( bottom_grid_pin_11_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_105 ) ) ; -cbx_1__1__mux_tree_tapbuf_size10_2 mux_top_ipin_12 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , - chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[16] , - chanx_right_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_6_sram ) , - .sram_inv ( mux_top_ipin_12_undriven_sram_inv ) , - .out ( bottom_grid_pin_12_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_103 ) ) ; -cbx_1__1__mux_tree_tapbuf_size10_3 mux_top_ipin_15 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , - chanx_left_in[15] , chanx_right_in[15] , chanx_left_in[19] , - chanx_right_in[19] } ) , - .sram ( mux_tree_tapbuf_size10_7_sram ) , - .sram_inv ( mux_top_ipin_15_undriven_sram_inv ) , - .out ( bottom_grid_pin_15_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_105 ) ) ; -cbx_1__1__mux_tree_tapbuf_size10_mem_0 mem_top_ipin_0 ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__1__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__1__mux_tree_tapbuf_size10_mem_5 mem_top_ipin_4 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__1__mux_tree_tapbuf_size10_mem_6 mem_top_ipin_7 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__1__mux_tree_tapbuf_size10_mem mem_top_ipin_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__1__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_11 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__1__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_12 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__1__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_15 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .ccff_tail ( { ropt_net_124 } ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_0 mux_top_ipin_1 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , - chanx_left_in[13] , chanx_right_in[13] } ) , - .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_top_ipin_1_undriven_sram_inv ) , - .out ( bottom_grid_pin_1_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_105 ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_4 mux_top_ipin_2 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , - chanx_left_in[14] , chanx_right_in[14] } ) , - .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_top_ipin_2_undriven_sram_inv ) , - .out ( bottom_grid_pin_2_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_102 ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_5 mux_top_ipin_5 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , - chanx_left_in[17] , chanx_right_in[17] } ) , - .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_top_ipin_5_undriven_sram_inv ) , - .out ( bottom_grid_pin_5_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_104 ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_6 mux_top_ipin_6 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , - chanx_left_in[18] , chanx_right_in[18] } ) , - .sram ( mux_tree_tapbuf_size8_3_sram ) , - .sram_inv ( mux_top_ipin_6_undriven_sram_inv ) , - .out ( bottom_grid_pin_6_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_103 ) ) ; -cbx_1__1__mux_tree_tapbuf_size8 mux_top_ipin_9 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , - chanx_left_in[13] , chanx_right_in[13] } ) , - .sram ( mux_tree_tapbuf_size8_4_sram ) , - .sram_inv ( mux_top_ipin_9_undriven_sram_inv ) , - .out ( bottom_grid_pin_9_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_103 ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_1 mux_top_ipin_10 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , - chanx_left_in[14] , chanx_right_in[14] } ) , - .sram ( mux_tree_tapbuf_size8_5_sram ) , - .sram_inv ( mux_top_ipin_10_undriven_sram_inv ) , - .out ( bottom_grid_pin_10_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_102 ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_2 mux_top_ipin_13 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , - chanx_left_in[17] , chanx_right_in[17] } ) , - .sram ( mux_tree_tapbuf_size8_6_sram ) , - .sram_inv ( mux_top_ipin_13_undriven_sram_inv ) , - .out ( bottom_grid_pin_13_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_104 ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_3 mux_top_ipin_14 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , - chanx_left_in[18] , chanx_right_in[18] } ) , - .sram ( mux_tree_tapbuf_size8_7_sram ) , - .sram_inv ( mux_top_ipin_14_undriven_sram_inv ) , - .out ( bottom_grid_pin_14_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_103 ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_mem_0 mem_top_ipin_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_mem_4 mem_top_ipin_2 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_mem_5 mem_top_ipin_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_mem_6 mem_top_ipin_6 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_mem mem_top_ipin_9 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_mem_1 mem_top_ipin_10 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_mem_2 mem_top_ipin_13 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_mem_3 mem_top_ipin_14 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1600 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1601 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1602 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1603 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1604 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1605 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1606 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1607 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1608 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1609 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1610 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1611 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1612 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1613 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1614 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1615 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1616 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chanx_left_in[0] ) , - .X ( chanx_right_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_134 ) , - .X ( chanx_left_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chanx_left_in[2] ) , - .X ( chanx_right_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , - .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__4 ( .A ( chanx_left_in[4] ) , - .X ( ropt_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__7 ( .A ( chanx_left_in[7] ) , - .X ( ropt_net_130 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chanx_left_in[10] ) , - .X ( ropt_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( ropt_net_135 ) , - .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__clkbuf_1 \prog_clk[0]_bip373 ( .A ( prog_clk[0] ) , - .X ( ctsbuf_net_1106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( chanx_right_in[4] ) , - .X ( chanx_left_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_326699 ( .A ( ctsbuf_net_1106 ) , - .X ( prog_clk__FEEDTHRU_1[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_136 ) , - .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( ropt_net_108 ) , - .X ( ropt_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chanx_left_in[17] ) , - .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_137 ) , - .X ( chanx_left_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_138 ) , - .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_right_in[0] ) , - .X ( chanx_left_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , - .X ( ropt_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chanx_right_in[2] ) , - .X ( chanx_left_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chanx_right_in[3] ) , - .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_728 ( .A ( chanx_left_in[13] ) , - .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chanx_right_in[5] ) , - .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chanx_right_in[7] ) , - .X ( ropt_net_145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_110 ) , - .X ( ropt_net_141 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chanx_right_in[9] ) , - .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( chanx_right_in[15] ) , - .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_32__31 ( .A ( chanx_right_in[11] ) , - .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_126 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_35__34 ( .A ( chanx_right_in[14] ) , - .X ( ropt_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( chanx_left_in[9] ) , - .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_37__36 ( .A ( chanx_right_in[16] ) , - .X ( ropt_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_38__37 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_39__38 ( .A ( chanx_right_in[18] ) , - .X ( ropt_net_125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( chanx_left_in[5] ) , - .X ( ropt_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_41__40 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_770 ( .A ( ropt_net_139 ) , - .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_59 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( chanx_left_in[18] ) , - .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_772 ( .A ( ropt_net_140 ) , - .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_774 ( .A ( ropt_net_141 ) , - .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_63 ( .A ( chanx_left_in[14] ) , - .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_64 ( .A ( chanx_left_in[15] ) , - .X ( ropt_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_116 ) , - .X ( ropt_net_135 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( .A ( ropt_net_142 ) , - .X ( chanx_right_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( ropt_net_143 ) , - .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_777 ( .A ( ropt_net_144 ) , - .X ( chanx_left_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( chanx_left_in[11] ) , - .X ( ropt_net_139 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_70 ( .A ( chanx_right_in[19] ) , - .X ( ropt_net_127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( chanx_left_in[8] ) , - .X ( chanx_right_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( chanx_left_in[16] ) , - .X ( ropt_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_739 ( .A ( chanx_left_in[1] ) , - .X ( chanx_right_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_121 ) , - .X ( ropt_net_138 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( .A ( chanx_right_in[12] ) , - .X ( chanx_left_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_145 ) , - .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_79 ( .A ( chanx_left_in[19] ) , - .X ( ropt_net_116 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_123 ) , - .X ( ropt_net_137 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_124 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_125 ) , - .X ( ropt_net_136 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( chanx_left_in[12] ) , - .X ( chanx_right_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_146 ) , - .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_88 ( .A ( chanx_right_in[10] ) , - .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_147 ) , - .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_148 ) , - .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_149 ) , - .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_126 ) , - .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( .A ( ropt_net_127 ) , - .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_128 ) , - .X ( ropt_net_142 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_129 ) , - .X ( ropt_net_144 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_130 ) , - .X ( ropt_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_131 ) , - .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_132 ) , - .X ( ropt_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_133 ) , - .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y0 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y0 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x82800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x128800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x138000y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x317400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x437000y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x506000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x542800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x552000y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x36800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x368000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x414000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x450800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x547400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x556600y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x101200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x248400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x331200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x446200y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x478400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x496800y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x616400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x69000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x78200y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x124200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x142600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x151800y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x197800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x207000y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x253000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x312800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x349600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x55200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x105800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x230000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x239200y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x285200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x437000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x570400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x588800y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x193200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x211600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x262200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x271400y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x243800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x303600y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x322000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x358800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x538200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x161000y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x280600y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x326600y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x372600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x450800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x515200y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x561200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x579600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x216200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x234600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x243800y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x322000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x331200y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x427800y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x147200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x165600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x174800y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x253000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x289800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x299000y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x110400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x193200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x317400y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x363400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x400200y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x441600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x460000y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x262200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x354200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x404800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x487600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x496800y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x165600y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x322000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x432400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x450800y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x188600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x225400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x243800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x326600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x335800y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x414000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x450800y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x575000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x584200y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x285200y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x363400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x243800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x262200y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x308200y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x354200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x423200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x460000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x579600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x409400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x492200y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x570400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x188600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x317400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x335800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x588800y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x354200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x391000y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x478400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x496800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x220800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x303600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x312800y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x400200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x437000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x473800y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x515200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x533600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x542800y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x73600y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x161000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x197800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x234600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x253000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x262200y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x340400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x391000y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x478400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x496800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x202400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x239200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x276000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x285200y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x326600y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x414000y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x460000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x496800y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x538200y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x110400y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x156400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x174800y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x220800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x230000y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x276000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x473800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x492200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x73600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x82800y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x128800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x138000y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x312800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x349600y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x437000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x455400y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x73600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x239200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x473800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x492200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x73600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x165600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x202400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x262200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x280600y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x326600y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x147200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x289800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x308200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x317400y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x363400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x538200y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x616400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x188600y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x271400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x280600y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x326600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x386400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x404800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x414000y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x538200y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x239200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x345000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x501400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x510600y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( prog_clk , - ccff_head , ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:0] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_24__70 ( .A ( mem_out[0] ) , - .X ( net_net_108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_163 ( .A ( net_net_108 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__0__EMBEDDED_IO ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , - FPGA_OUT , FPGA_DIR , p_abuf0 , VDD , VSS ) ; -input SOC_IN ; -output SOC_OUT ; -output SOC_DIR ; -output FPGA_IN ; -input FPGA_OUT ; -input FPGA_DIR ; -output p_abuf0 ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -assign SOC_OUT = FPGA_OUT ; - -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__68 ( .A ( SOC_IN ) , .X ( FPGA_IN ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 FTB_23__69 ( .A ( FPGA_DIR ) , - .X ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_82 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__0__logical_tile_io_mode_physical__iopad ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , VDD , VSS , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] iopad_outpad ; -input [0:0] ccff_head ; -output [0:0] iopad_inpad ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; -output p_abuf0 ; - -wire [0:0] EMBEDDED_IO_0_en ; -supply1 VDD ; -supply0 VSS ; - -cbx_1__0__EMBEDDED_IO EMBEDDED_IO_0_ ( - .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , - .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , - .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , - .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -endmodule - - -module cbx_1__0__logical_tile_io_mode_io_ ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , - ccff_tail , VDD , VSS , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] io_outpad ; -input [0:0] ccff_head ; -output [0:0] io_inpad ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; -output p_abuf0 ; - -supply1 VDD ; -supply0 VSS ; - -cbx_1__0__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , - .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , - .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__0__direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( io_outpad ) ) ; -endmodule - - -module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_4 ( prog_clk , - ccff_head , ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:0] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__67 ( .A ( mem_out[0] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__0__EMBEDDED_IO_4 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , - FPGA_OUT , FPGA_DIR , p_abuf0 , VDD , VSS ) ; -input SOC_IN ; -output SOC_OUT ; -output SOC_DIR ; -output FPGA_IN ; -input FPGA_OUT ; -input FPGA_DIR ; -output p_abuf0 ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -assign SOC_OUT = FPGA_OUT ; - -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__65 ( .A ( SOC_IN ) , .X ( FPGA_IN ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 FTB_20__66 ( .A ( FPGA_DIR ) , - .X ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_150 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__0__logical_tile_io_mode_physical__iopad_4 ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , VDD , VSS , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] iopad_outpad ; -input [0:0] ccff_head ; -output [0:0] iopad_inpad ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; -output p_abuf0 ; - -wire [0:0] EMBEDDED_IO_0_en ; -supply1 VDD ; -supply0 VSS ; - -cbx_1__0__EMBEDDED_IO_4 EMBEDDED_IO_0_ ( - .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , - .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , - .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , - .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_4 EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -endmodule - - -module cbx_1__0__logical_tile_io_mode_io__4 ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , - ccff_tail , VDD , VSS , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] io_outpad ; -input [0:0] ccff_head ; -output [0:0] io_inpad ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; -output p_abuf0 ; - -supply1 VDD ; -supply0 VSS ; - -cbx_1__0__logical_tile_io_mode_physical__iopad_4 logical_tile_io_mode_physical__iopad_0 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , - .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , - .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__0__direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( io_outpad ) ) ; -endmodule - - -module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_3 ( prog_clk , - ccff_head , ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:0] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__64 ( .A ( mem_out[0] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__0__EMBEDDED_IO_3 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , - FPGA_OUT , FPGA_DIR , p_abuf0 , VDD , VSS ) ; -input SOC_IN ; -output SOC_OUT ; -output SOC_DIR ; -output FPGA_IN ; -input FPGA_OUT ; -input FPGA_DIR ; -output p_abuf0 ; -input VDD ; -input VSS ; - -supply1 VDD ; -wire aps_rename_3_ ; -supply0 VSS ; - -assign SOC_OUT = FPGA_OUT ; - -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__62 ( .A ( SOC_IN ) , .X ( FPGA_IN ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__63 ( .A ( FPGA_DIR ) , - .X ( aps_rename_3_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_78 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_162 ( .A ( aps_rename_3_ ) , - .X ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__0__logical_tile_io_mode_physical__iopad_3 ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , VDD , VSS , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] iopad_outpad ; -input [0:0] ccff_head ; -output [0:0] iopad_inpad ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; -output p_abuf0 ; - -wire [0:0] EMBEDDED_IO_0_en ; -supply1 VDD ; -supply0 VSS ; - -cbx_1__0__EMBEDDED_IO_3 EMBEDDED_IO_0_ ( - .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , - .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , - .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , - .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_3 EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -endmodule - - -module cbx_1__0__logical_tile_io_mode_io__3 ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , - ccff_tail , VDD , VSS , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] io_outpad ; -input [0:0] ccff_head ; -output [0:0] io_inpad ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; -output p_abuf0 ; - -supply1 VDD ; -supply0 VSS ; - -cbx_1__0__logical_tile_io_mode_physical__iopad_3 logical_tile_io_mode_physical__iopad_0 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , - .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , - .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__0__direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( io_outpad ) ) ; -endmodule - - -module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_2 ( prog_clk , - ccff_head , ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:0] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__61 ( .A ( mem_out[0] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__0__EMBEDDED_IO_2 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , - FPGA_OUT , FPGA_DIR , p_abuf0 , p_abuf1 , VDD , VSS ) ; -input SOC_IN ; -output SOC_OUT ; -output SOC_DIR ; -output FPGA_IN ; -input FPGA_OUT ; -input FPGA_DIR ; -output p_abuf0 ; -output p_abuf1 ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -assign SOC_OUT = FPGA_OUT ; - -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__59 ( .A ( SOC_IN ) , .X ( p_abuf1 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__60 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_75 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_76 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__0__logical_tile_io_mode_physical__iopad_2 ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] iopad_outpad ; -input [0:0] ccff_head ; -output [0:0] iopad_inpad ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; -output p_abuf0 ; -output p_abuf1 ; - -wire [0:0] EMBEDDED_IO_0_en ; -supply1 VDD ; -supply0 VSS ; - -cbx_1__0__EMBEDDED_IO_2 EMBEDDED_IO_0_ ( - .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , - .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , - .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , - .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , - .p_abuf1 ( p_abuf1 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_2 EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -endmodule - - -module cbx_1__0__logical_tile_io_mode_io__2 ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , - ccff_tail , VDD , VSS , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] io_outpad ; -input [0:0] ccff_head ; -output [0:0] io_inpad ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; -output p_abuf0 ; - -supply1 VDD ; -supply0 VSS ; - -cbx_1__0__logical_tile_io_mode_physical__iopad_2 logical_tile_io_mode_physical__iopad_0 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , - .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , - .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; -cbx_1__0__direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( { p_abuf1 } ) ) ; -cbx_1__0__direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( io_outpad ) ) ; -endmodule - - -module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_1 ( prog_clk , - ccff_head , ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:0] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__58 ( .A ( mem_out[0] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__0__EMBEDDED_IO_1 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , - FPGA_OUT , FPGA_DIR , p_abuf0 , VDD , VSS ) ; -input SOC_IN ; -output SOC_OUT ; -output SOC_DIR ; -output FPGA_IN ; -input FPGA_OUT ; -input FPGA_DIR ; -output p_abuf0 ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -assign SOC_OUT = FPGA_OUT ; - -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__56 ( .A ( SOC_IN ) , .X ( FPGA_IN ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__57 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_141 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__0__logical_tile_io_mode_physical__iopad_1 ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , VDD , VSS , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] iopad_outpad ; -input [0:0] ccff_head ; -output [0:0] iopad_inpad ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; -output p_abuf0 ; - -wire [0:0] EMBEDDED_IO_0_en ; -supply1 VDD ; -supply0 VSS ; - -cbx_1__0__EMBEDDED_IO_1 EMBEDDED_IO_0_ ( - .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , - .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , - .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , - .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_1 EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -endmodule - - -module cbx_1__0__logical_tile_io_mode_io__1 ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , - ccff_tail , VDD , VSS , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] io_outpad ; -input [0:0] ccff_head ; -output [0:0] io_inpad ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; -output p_abuf0 ; - -supply1 VDD ; -supply0 VSS ; - -cbx_1__0__logical_tile_io_mode_physical__iopad_1 logical_tile_io_mode_physical__iopad_0 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , - .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , - .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__0__direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( io_outpad ) ) ; -endmodule - - -module cbx_1__0__direct_interc ( in , out ) ; -input [0:0] in ; -output [0:0] out ; - -assign out[0] = in[0] ; -endmodule - - -module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_0 ( prog_clk , - ccff_head , ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:0] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__55 ( .A ( mem_out[0] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__0__EMBEDDED_IO_0 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , - FPGA_OUT , FPGA_DIR , p_abuf0 , p_abuf1 , VDD , VSS ) ; -input SOC_IN ; -output SOC_OUT ; -output SOC_DIR ; -output FPGA_IN ; -input FPGA_OUT ; -input FPGA_DIR ; -output p_abuf0 ; -output p_abuf1 ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -assign SOC_OUT = FPGA_OUT ; - -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__53 ( .A ( SOC_IN ) , .X ( p_abuf1 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__54 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_71 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_146 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__0__logical_tile_io_mode_physical__iopad_0 ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] iopad_outpad ; -input [0:0] ccff_head ; -output [0:0] iopad_inpad ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; -output p_abuf0 ; -output p_abuf1 ; - -wire [0:0] EMBEDDED_IO_0_en ; -supply1 VDD ; -supply0 VSS ; - -cbx_1__0__EMBEDDED_IO_0 EMBEDDED_IO_0_ ( - .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , - .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , - .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , - .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , - .p_abuf1 ( p_abuf1 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_0 EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -endmodule - - -module cbx_1__0__logical_tile_io_mode_io__0 ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , - ccff_tail , VDD , VSS , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] io_outpad ; -input [0:0] ccff_head ; -output [0:0] io_inpad ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; -output p_abuf0 ; - -supply1 VDD ; -supply0 VSS ; - -cbx_1__0__logical_tile_io_mode_physical__iopad_0 logical_tile_io_mode_physical__iopad_0 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , - .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , - .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; -cbx_1__0__direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( { p_abuf1 } ) ) ; -cbx_1__0__direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( io_outpad ) ) ; -endmodule - - -module cbx_1__0__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__52 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__0__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__51 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__0__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__50 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__0__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__49 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__0__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__48 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__0__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__47 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__0__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__0__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__0__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__0__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__0__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__0__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__0_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , - chanx_left_out , chanx_right_out , bottom_grid_pin_0_ , - bottom_grid_pin_2_ , bottom_grid_pin_4_ , bottom_grid_pin_6_ , - bottom_grid_pin_8_ , bottom_grid_pin_10_ , ccff_tail , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , top_width_0_height_0__pin_0_ , - top_width_0_height_0__pin_2_ , top_width_0_height_0__pin_4_ , - top_width_0_height_0__pin_6_ , top_width_0_height_0__pin_8_ , - top_width_0_height_0__pin_10_ , top_width_0_height_0__pin_1_upper , - top_width_0_height_0__pin_1_lower , top_width_0_height_0__pin_3_upper , - top_width_0_height_0__pin_3_lower , top_width_0_height_0__pin_5_upper , - top_width_0_height_0__pin_5_lower , top_width_0_height_0__pin_7_upper , - top_width_0_height_0__pin_7_lower , top_width_0_height_0__pin_9_upper , - top_width_0_height_0__pin_9_lower , top_width_0_height_0__pin_11_upper , - top_width_0_height_0__pin_11_lower , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , - SC_OUT_BOT , VDD , VSS , prog_clk__FEEDTHRU_1 ) ; -input [0:0] prog_clk ; -input [0:19] chanx_left_in ; -input [0:19] chanx_right_in ; -input [0:0] ccff_head ; -output [0:19] chanx_left_out ; -output [0:19] chanx_right_out ; -output [0:0] bottom_grid_pin_0_ ; -output [0:0] bottom_grid_pin_2_ ; -output [0:0] bottom_grid_pin_4_ ; -output [0:0] bottom_grid_pin_6_ ; -output [0:0] bottom_grid_pin_8_ ; -output [0:0] bottom_grid_pin_10_ ; -output [0:0] ccff_tail ; -input [0:5] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:5] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:5] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] top_width_0_height_0__pin_0_ ; -input [0:0] top_width_0_height_0__pin_2_ ; -input [0:0] top_width_0_height_0__pin_4_ ; -input [0:0] top_width_0_height_0__pin_6_ ; -input [0:0] top_width_0_height_0__pin_8_ ; -input [0:0] top_width_0_height_0__pin_10_ ; -output [0:0] top_width_0_height_0__pin_1_upper ; -output [0:0] top_width_0_height_0__pin_1_lower ; -output [0:0] top_width_0_height_0__pin_3_upper ; -output [0:0] top_width_0_height_0__pin_3_lower ; -output [0:0] top_width_0_height_0__pin_5_upper ; -output [0:0] top_width_0_height_0__pin_5_lower ; -output [0:0] top_width_0_height_0__pin_7_upper ; -output [0:0] top_width_0_height_0__pin_7_lower ; -output [0:0] top_width_0_height_0__pin_9_upper ; -output [0:0] top_width_0_height_0__pin_9_lower ; -output [0:0] top_width_0_height_0__pin_11_upper ; -output [0:0] top_width_0_height_0__pin_11_lower ; -input SC_IN_TOP ; -input SC_IN_BOT ; -output SC_OUT_TOP ; -output SC_OUT_BOT ; -input VDD ; -input VSS ; -output [0:0] prog_clk__FEEDTHRU_1 ; - -wire ropt_net_191 ; -wire ropt_net_197 ; -wire ropt_net_179 ; -wire ropt_net_177 ; -wire ropt_net_190 ; -wire ropt_net_178 ; -wire [0:3] mux_top_ipin_0_undriven_sram_inv ; -wire [0:3] mux_top_ipin_1_undriven_sram_inv ; -wire [0:3] mux_top_ipin_2_undriven_sram_inv ; -wire [0:3] mux_top_ipin_3_undriven_sram_inv ; -wire [0:3] mux_top_ipin_4_undriven_sram_inv ; -wire [0:3] mux_top_ipin_5_undriven_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:3] mux_tree_tapbuf_size10_2_sram ; -wire [0:3] mux_tree_tapbuf_size10_3_sram ; -wire [0:3] mux_tree_tapbuf_size10_4_sram ; -wire [0:3] mux_tree_tapbuf_size10_5_sram ; -wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; -wire [0:0] logical_tile_io_mode_io__0_ccff_tail ; -wire [0:0] logical_tile_io_mode_io__1_ccff_tail ; -wire [0:0] logical_tile_io_mode_io__2_ccff_tail ; -wire [0:0] logical_tile_io_mode_io__3_ccff_tail ; -wire [0:0] logical_tile_io_mode_io__4_ccff_tail ; -supply1 VDD ; -supply0 VSS ; - -assign SC_IN_TOP = SC_IN_BOT ; - -cbx_1__0__mux_tree_tapbuf_size10_0 mux_top_ipin_0 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , - chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , - chanx_right_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_top_ipin_0_undriven_sram_inv ) , - .out ( bottom_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_174 ) ) ; -cbx_1__0__mux_tree_tapbuf_size10_1 mux_top_ipin_1 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , - chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , - chanx_right_in[17] } ) , - .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_top_ipin_1_undriven_sram_inv ) , - .out ( bottom_grid_pin_2_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_173 ) ) ; -cbx_1__0__mux_tree_tapbuf_size10_2 mux_top_ipin_2 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , - chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , - chanx_right_in[18] } ) , - .sram ( mux_tree_tapbuf_size10_2_sram ) , - .sram_inv ( mux_top_ipin_2_undriven_sram_inv ) , - .out ( bottom_grid_pin_4_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_173 ) ) ; -cbx_1__0__mux_tree_tapbuf_size10_3 mux_top_ipin_3 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , - chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , - chanx_right_in[19] } ) , - .sram ( mux_tree_tapbuf_size10_3_sram ) , - .sram_inv ( mux_top_ipin_3_undriven_sram_inv ) , - .out ( bottom_grid_pin_6_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_173 ) ) ; -cbx_1__0__mux_tree_tapbuf_size10_4 mux_top_ipin_4 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , - chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[14] , - chanx_right_in[14] } ) , - .sram ( mux_tree_tapbuf_size10_4_sram ) , - .sram_inv ( mux_top_ipin_4_undriven_sram_inv ) , - .out ( bottom_grid_pin_8_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_174 ) ) ; -cbx_1__0__mux_tree_tapbuf_size10 mux_top_ipin_5 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , - chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[15] , - chanx_right_in[15] } ) , - .sram ( mux_tree_tapbuf_size10_5_sram ) , - .sram_inv ( mux_top_ipin_5_undriven_sram_inv ) , - .out ( bottom_grid_pin_10_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_174 ) ) ; -cbx_1__0__mux_tree_tapbuf_size10_mem_0 mem_top_ipin_0 ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__0__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__0__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_2 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__0__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__0__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_4 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__0__mux_tree_tapbuf_size10_mem mem_top_ipin_5 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , - .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__0__logical_tile_io_mode_io__0 logical_tile_io_mode_io__0 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_196 } ) , - .io_outpad ( top_width_0_height_0__pin_0_ ) , - .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_8_ } ) , - .ccff_tail ( logical_tile_io_mode_io__0_ccff_tail ) , .VDD ( VDD ) , - .VSS ( VSS ) , .p_abuf0 ( ropt_net_191 ) ) ; -cbx_1__0__logical_tile_io_mode_io__1 logical_tile_io_mode_io__1 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[1] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[1] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_200 } ) , - .io_outpad ( top_width_0_height_0__pin_2_ ) , - .ccff_head ( logical_tile_io_mode_io__0_ccff_tail ) , - .io_inpad ( { aps_rename_10_ } ) , - .ccff_tail ( logical_tile_io_mode_io__1_ccff_tail ) , .VDD ( VDD ) , - .VSS ( VSS ) , .p_abuf0 ( ropt_net_197 ) ) ; -cbx_1__0__logical_tile_io_mode_io__2 logical_tile_io_mode_io__2 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[2] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[2] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_198 } ) , - .io_outpad ( top_width_0_height_0__pin_4_ ) , - .ccff_head ( logical_tile_io_mode_io__1_ccff_tail ) , - .io_inpad ( { aps_rename_12_ } ) , - .ccff_tail ( logical_tile_io_mode_io__2_ccff_tail ) , .VDD ( VDD ) , - .VSS ( VSS ) , .p_abuf0 ( ropt_net_179 ) ) ; -cbx_1__0__logical_tile_io_mode_io__3 logical_tile_io_mode_io__3 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[3] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[3] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_193 } ) , - .io_outpad ( top_width_0_height_0__pin_6_ ) , - .ccff_head ( logical_tile_io_mode_io__2_ccff_tail ) , - .io_inpad ( { aps_rename_13_ } ) , - .ccff_tail ( logical_tile_io_mode_io__3_ccff_tail ) , .VDD ( VDD ) , - .VSS ( VSS ) , .p_abuf0 ( ropt_net_177 ) ) ; -cbx_1__0__logical_tile_io_mode_io__4 logical_tile_io_mode_io__4 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[4] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[4] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_201 } ) , - .io_outpad ( top_width_0_height_0__pin_8_ ) , - .ccff_head ( logical_tile_io_mode_io__3_ccff_tail ) , - .io_inpad ( { aps_rename_14_ } ) , - .ccff_tail ( logical_tile_io_mode_io__4_ccff_tail ) , .VDD ( VDD ) , - .VSS ( VSS ) , .p_abuf0 ( ropt_net_190 ) ) ; -cbx_1__0__logical_tile_io_mode_io_ logical_tile_io_mode_io__5 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[5] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[5] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[5] ) , - .io_outpad ( top_width_0_height_0__pin_10_ ) , - .ccff_head ( logical_tile_io_mode_io__4_ccff_tail ) , - .io_inpad ( { aps_rename_15_ } ) , - .ccff_tail ( { ropt_net_212 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( ropt_net_178 ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1582 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1583 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1584 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1585 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1586 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1587 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1588 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1589 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1590 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1591 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1592 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1593 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1594 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1595 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1596 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1597 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1598 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__conb_1 optlc_166 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_173 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_168 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_174 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__clkbuf_1 \prog_clk[0]_bip435 ( .A ( prog_clk[0] ) , - .X ( ctsbuf_net_1176 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , - .X ( ropt_net_207 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_177 ) , - .X ( ropt_net_243 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_326761 ( .A ( ctsbuf_net_1176 ) , - .X ( prog_clk__FEEDTHRU_1[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_849 ( .A ( ropt_net_239 ) , - .X ( chanx_left_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_178 ) , - .X ( ropt_net_247 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_266 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chanx_left_in[9] ) , - .X ( ropt_net_208 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_179 ) , - .X ( ropt_net_249 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( ropt_net_180 ) , - .X ( ropt_net_245 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_792 ( .A ( ropt_net_181 ) , - .X ( top_width_0_height_0__pin_11_lower[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( ropt_net_182 ) , - .X ( ropt_net_270 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_244 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__15 ( .A ( chanx_left_in[15] ) , - .X ( ropt_net_222 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_184 ) , - .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( chanx_right_in[5] ) , - .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_233 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( chanx_right_in[7] ) , - .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_187 ) , - .X ( top_width_0_height_0__pin_3_lower[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , - .X ( ropt_net_219 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_850 ( .A ( ropt_net_240 ) , - .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_188 ) , - .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_246 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_190 ) , - .X ( ropt_net_250 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_224 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_191 ) , - .X ( top_width_0_height_0__pin_1_upper[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_192 ) , - .X ( ropt_net_240 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__29 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_221 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__30 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_223 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_851 ( .A ( ropt_net_241 ) , - .X ( chanx_left_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__32 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_216 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_193 ) , - .X ( ropt_net_262 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_194 ) , - .X ( top_width_0_height_0__pin_1_lower[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_36__35 ( .A ( chanx_right_in[15] ) , - .X ( ropt_net_226 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_37__36 ( .A ( chanx_right_in[16] ) , - .X ( ropt_net_229 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( ropt_net_195 ) , - .X ( ropt_net_264 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_39__38 ( .A ( chanx_right_in[18] ) , - .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_852 ( .A ( ropt_net_242 ) , - .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_41__40 ( .A ( aps_rename_8_ ) , - .X ( aps_rename_9_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_853 ( .A ( ropt_net_243 ) , - .X ( top_width_0_height_0__pin_7_upper[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_43__42 ( .A ( aps_rename_12_ ) , - .X ( ropt_net_182 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_196 ) , - .X ( ropt_net_254 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_197 ) , - .X ( top_width_0_height_0__pin_3_upper[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_46__45 ( .A ( aps_rename_15_ ) , - .X ( ropt_net_181 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_47__46 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_180 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_85 ( .A ( chanx_left_in[0] ) , - .X ( ropt_net_209 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_86 ( .A ( chanx_left_in[1] ) , - .X ( ropt_net_225 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_87 ( .A ( chanx_left_in[4] ) , - .X ( ropt_net_214 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_88 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_184 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_809 ( .A ( ropt_net_198 ) , - .X ( ropt_net_268 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_90 ( .A ( chanx_left_in[11] ) , - .X ( ropt_net_227 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_810 ( .A ( ropt_net_199 ) , - .X ( ropt_net_265 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_92 ( .A ( chanx_left_in[16] ) , - .X ( ropt_net_213 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_93 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_210 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_94 ( .A ( chanx_right_in[3] ) , - .X ( ropt_net_220 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_854 ( .A ( ropt_net_244 ) , - .X ( chanx_left_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_857 ( .A ( ropt_net_245 ) , - .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_858 ( .A ( ropt_net_246 ) , - .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_811 ( .A ( ropt_net_200 ) , - .X ( ropt_net_267 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_860 ( .A ( ropt_net_247 ) , - .X ( top_width_0_height_0__pin_11_upper[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_100 ( .A ( chanx_right_in[14] ) , - .X ( ropt_net_231 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_862 ( .A ( ropt_net_248 ) , - .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_812 ( .A ( ropt_net_201 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_103 ( .A ( aps_rename_9_ ) , - .X ( ropt_net_194 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_104 ( .A ( aps_rename_10_ ) , - .X ( ropt_net_187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_864 ( .A ( ropt_net_249 ) , - .X ( top_width_0_height_0__pin_5_upper[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_865 ( .A ( ropt_net_250 ) , - .X ( top_width_0_height_0__pin_9_upper[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( chanx_right_in[2] ) , - .X ( chanx_left_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_814 ( .A ( chanx_left_in[5] ) , - .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_815 ( .A ( chanx_left_in[7] ) , - .X ( ropt_net_269 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_205 ) , - .X ( ropt_net_256 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_817 ( .A ( chanx_right_in[13] ) , - .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_207 ) , - .X ( ropt_net_248 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_208 ) , - .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_209 ) , - .X ( ropt_net_260 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_210 ) , - .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_211 ) , - .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_212 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_213 ) , - .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_131 ( .A ( chanx_left_in[2] ) , - .X ( ropt_net_228 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_866 ( .A ( ropt_net_251 ) , - .X ( chanx_left_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_133 ( .A ( chanx_left_in[10] ) , - .X ( ropt_net_211 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_134 ( .A ( chanx_left_in[12] ) , - .X ( ropt_net_205 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_135 ( .A ( chanx_left_in[13] ) , - .X ( ropt_net_217 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_136 ( .A ( chanx_left_in[19] ) , - .X ( ropt_net_215 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_137 ( .A ( chanx_right_in[0] ) , - .X ( ropt_net_232 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_138 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_218 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( ropt_net_214 ) , - .X ( ropt_net_259 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_144 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_188 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_145 ( .A ( chanx_right_in[19] ) , - .X ( ropt_net_192 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_826 ( .A ( ropt_net_215 ) , - .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_867 ( .A ( ropt_net_252 ) , - .X ( chanx_left_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_154 ( .A ( chanx_left_in[14] ) , - .X ( ropt_net_230 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_827 ( .A ( ropt_net_216 ) , - .X ( ropt_net_241 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_217 ) , - .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_829 ( .A ( ropt_net_218 ) , - .X ( ropt_net_252 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_219 ) , - .X ( ropt_net_239 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_220 ) , - .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_160 ( .A ( aps_rename_13_ ) , - .X ( ropt_net_199 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_161 ( .A ( aps_rename_14_ ) , - .X ( ropt_net_195 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_832 ( .A ( ropt_net_221 ) , - .X ( ropt_net_242 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_833 ( .A ( ropt_net_222 ) , - .X ( ropt_net_255 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_834 ( .A ( ropt_net_223 ) , - .X ( ropt_net_257 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_835 ( .A ( ropt_net_224 ) , - .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_836 ( .A ( ropt_net_225 ) , - .X ( ropt_net_258 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_838 ( .A ( ropt_net_226 ) , - .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_839 ( .A ( ropt_net_227 ) , - .X ( ropt_net_261 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_840 ( .A ( ropt_net_228 ) , - .X ( chanx_right_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_841 ( .A ( ropt_net_229 ) , - .X ( ropt_net_263 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_843 ( .A ( ropt_net_230 ) , - .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_844 ( .A ( ropt_net_231 ) , - .X ( ropt_net_253 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_845 ( .A ( ropt_net_232 ) , - .X ( ropt_net_251 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_847 ( .A ( ropt_net_233 ) , - .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_868 ( .A ( ropt_net_253 ) , - .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_871 ( .A ( ropt_net_254 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_873 ( .A ( ropt_net_255 ) , - .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_874 ( .A ( ropt_net_256 ) , - .X ( chanx_right_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_875 ( .A ( ropt_net_257 ) , - .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_876 ( .A ( ropt_net_258 ) , - .X ( chanx_right_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_877 ( .A ( ropt_net_259 ) , - .X ( chanx_right_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_878 ( .A ( ropt_net_260 ) , - .X ( chanx_right_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_879 ( .A ( ropt_net_261 ) , - .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_880 ( .A ( ropt_net_262 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_882 ( .A ( ropt_net_263 ) , - .X ( chanx_left_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_889 ( .A ( ropt_net_264 ) , - .X ( top_width_0_height_0__pin_9_lower[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_890 ( .A ( ropt_net_265 ) , - .X ( top_width_0_height_0__pin_7_lower[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_892 ( .A ( ropt_net_266 ) , - .X ( chanx_right_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_893 ( .A ( ropt_net_267 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_894 ( .A ( ropt_net_268 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_896 ( .A ( ropt_net_269 ) , - .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_899 ( .A ( ropt_net_270 ) , - .X ( top_width_0_height_0__pin_5_lower[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y0 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y0 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x82800y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x179400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x197800y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x552000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x561200y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x184000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x193200y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x538200y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x119600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x128800y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x538200y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x105800y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x303600y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x345000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x427800y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x506000y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x644000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x165600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x202400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x239200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x276000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x165600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x202400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x239200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x276000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x312800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x349600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x409400y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x496800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x119600y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x197800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x234600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x271400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x386400y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x427800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x455400y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x161000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x197800y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x276000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x464600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x483000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x492200y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x276000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x312800y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x368000y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x446200y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x234600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x253000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x345000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x409400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x464600y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x165600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x253000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x289800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x326600y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x441600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x460000y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x506000y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x115000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x211600y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x331200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x427800y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x473800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x161000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x197800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x253000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x271400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x322000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x358800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x395600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x414000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x151800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x188600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x262200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x322000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x409400y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x455400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x533600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x115000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x151800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x188600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x225400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x262200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x299000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x335800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x372600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x409400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x469200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x487600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x533600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x119600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x128800y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x174800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x211600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x248400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x266800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x317400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x335800y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x161000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x179400y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x294400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x391000y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x156400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x193200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x202400y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x354200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x450800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x119600y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x165600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x202400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x239200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x276000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x312800y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x358800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x395600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x455400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x492200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x501400y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x202400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x220800y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x299000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x317400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x326600y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x464600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x547400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x584200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x36800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x156400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x193200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x211600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x220800y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x262200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x299000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x335800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x354200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x363400y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x409400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x418600y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x257600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x276000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x326600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x363400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x409400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x418600y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x538200y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x147200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x165600y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x211600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x262200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x294400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x312800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x322000y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x409400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x524400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x533600y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x575000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x584200y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x230000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x358800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x409400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x418600y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x496800y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x225400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x243800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x253000y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x340400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x423200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x441600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x450800y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x496800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x119600y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x262200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x464600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x483000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x492200y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x533600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x579600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x193200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x211600y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x289800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x326600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x363400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x400200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x437000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x473800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x510600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x529000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x538200y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x156400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x538200y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x165600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x243800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x538200y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_35__40 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_34__39 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__38 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__37 ( .A ( mem_out[1] ) , - .X ( net_net_51 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_51 ( .A ( net_net_51 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_22 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__36 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_21 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__35 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_20 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__34 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_19 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__33 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_18 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__32 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_17 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__31 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__30 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__29 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__28 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__27 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__26 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__25 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__24 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__23 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__22 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__21 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__20 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__19 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__18 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__17 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__16 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__15 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__14 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_22 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_21 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_20 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_19 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__13 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size5_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__12 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size5_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__11 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__10 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__9 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size6_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__8 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__7 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__6 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2_ ( prog_clk , chany_bottom_in , bottom_right_grid_pin_1_ , - bottom_left_grid_pin_42_ , bottom_left_grid_pin_43_ , - bottom_left_grid_pin_44_ , bottom_left_grid_pin_45_ , - bottom_left_grid_pin_46_ , bottom_left_grid_pin_47_ , - bottom_left_grid_pin_48_ , bottom_left_grid_pin_49_ , chanx_left_in , - left_top_grid_pin_1_ , left_bottom_grid_pin_34_ , - left_bottom_grid_pin_35_ , left_bottom_grid_pin_36_ , - left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , - left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , - left_bottom_grid_pin_41_ , ccff_head , chany_bottom_out , chanx_left_out , - ccff_tail , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , SC_OUT_BOT , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:19] chany_bottom_in ; -input [0:0] bottom_right_grid_pin_1_ ; -input [0:0] bottom_left_grid_pin_42_ ; -input [0:0] bottom_left_grid_pin_43_ ; -input [0:0] bottom_left_grid_pin_44_ ; -input [0:0] bottom_left_grid_pin_45_ ; -input [0:0] bottom_left_grid_pin_46_ ; -input [0:0] bottom_left_grid_pin_47_ ; -input [0:0] bottom_left_grid_pin_48_ ; -input [0:0] bottom_left_grid_pin_49_ ; -input [0:19] chanx_left_in ; -input [0:0] left_top_grid_pin_1_ ; -input [0:0] left_bottom_grid_pin_34_ ; -input [0:0] left_bottom_grid_pin_35_ ; -input [0:0] left_bottom_grid_pin_36_ ; -input [0:0] left_bottom_grid_pin_37_ ; -input [0:0] left_bottom_grid_pin_38_ ; -input [0:0] left_bottom_grid_pin_39_ ; -input [0:0] left_bottom_grid_pin_40_ ; -input [0:0] left_bottom_grid_pin_41_ ; -input [0:0] ccff_head ; -output [0:19] chany_bottom_out ; -output [0:19] chanx_left_out ; -output [0:0] ccff_tail ; -input SC_IN_TOP ; -input SC_IN_BOT ; -output SC_OUT_TOP ; -output SC_OUT_BOT ; -input VDD ; -input VSS ; - -wire [0:1] mux_bottom_track_11_undriven_sram_inv ; -wire [0:1] mux_bottom_track_13_undriven_sram_inv ; -wire [0:1] mux_bottom_track_15_undriven_sram_inv ; -wire [0:1] mux_bottom_track_17_undriven_sram_inv ; -wire [0:1] mux_bottom_track_19_undriven_sram_inv ; -wire [0:2] mux_bottom_track_1_undriven_sram_inv ; -wire [0:1] mux_bottom_track_21_undriven_sram_inv ; -wire [0:1] mux_bottom_track_23_undriven_sram_inv ; -wire [0:1] mux_bottom_track_25_undriven_sram_inv ; -wire [0:1] mux_bottom_track_27_undriven_sram_inv ; -wire [0:1] mux_bottom_track_29_undriven_sram_inv ; -wire [0:2] mux_bottom_track_3_undriven_sram_inv ; -wire [0:2] mux_bottom_track_5_undriven_sram_inv ; -wire [0:2] mux_bottom_track_7_undriven_sram_inv ; -wire [0:1] mux_bottom_track_9_undriven_sram_inv ; -wire [0:1] mux_left_track_11_undriven_sram_inv ; -wire [0:1] mux_left_track_13_undriven_sram_inv ; -wire [0:1] mux_left_track_15_undriven_sram_inv ; -wire [0:1] mux_left_track_17_undriven_sram_inv ; -wire [0:1] mux_left_track_19_undriven_sram_inv ; -wire [0:2] mux_left_track_1_undriven_sram_inv ; -wire [0:1] mux_left_track_21_undriven_sram_inv ; -wire [0:1] mux_left_track_23_undriven_sram_inv ; -wire [0:1] mux_left_track_25_undriven_sram_inv ; -wire [0:1] mux_left_track_27_undriven_sram_inv ; -wire [0:1] mux_left_track_29_undriven_sram_inv ; -wire [0:1] mux_left_track_31_undriven_sram_inv ; -wire [0:1] mux_left_track_33_undriven_sram_inv ; -wire [0:1] mux_left_track_35_undriven_sram_inv ; -wire [0:1] mux_left_track_37_undriven_sram_inv ; -wire [0:1] mux_left_track_39_undriven_sram_inv ; -wire [0:2] mux_left_track_3_undriven_sram_inv ; -wire [0:2] mux_left_track_5_undriven_sram_inv ; -wire [0:2] mux_left_track_7_undriven_sram_inv ; -wire [0:1] mux_left_track_9_undriven_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_10_sram ; -wire [0:1] mux_tree_tapbuf_size2_11_sram ; -wire [0:1] mux_tree_tapbuf_size2_12_sram ; -wire [0:1] mux_tree_tapbuf_size2_13_sram ; -wire [0:1] mux_tree_tapbuf_size2_14_sram ; -wire [0:1] mux_tree_tapbuf_size2_15_sram ; -wire [0:1] mux_tree_tapbuf_size2_16_sram ; -wire [0:1] mux_tree_tapbuf_size2_17_sram ; -wire [0:1] mux_tree_tapbuf_size2_18_sram ; -wire [0:1] mux_tree_tapbuf_size2_19_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_20_sram ; -wire [0:1] mux_tree_tapbuf_size2_21_sram ; -wire [0:1] mux_tree_tapbuf_size2_22_sram ; -wire [0:1] mux_tree_tapbuf_size2_23_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_5_sram ; -wire [0:1] mux_tree_tapbuf_size2_6_sram ; -wire [0:1] mux_tree_tapbuf_size2_7_sram ; -wire [0:1] mux_tree_tapbuf_size2_8_sram ; -wire [0:1] mux_tree_tapbuf_size2_9_sram ; -wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_19_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_20_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_21_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_22_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; -wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:1] mux_tree_tapbuf_size3_2_sram ; -wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size5_0_sram ; -wire [0:2] mux_tree_tapbuf_size5_1_sram ; -wire [0:2] mux_tree_tapbuf_size5_2_sram ; -wire [0:2] mux_tree_tapbuf_size5_3_sram ; -wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size6_1_sram ; -wire [0:2] mux_tree_tapbuf_size6_2_sram ; -wire [0:2] mux_tree_tapbuf_size6_3_sram ; -wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ; -supply1 VDD ; -supply0 VSS ; - -assign SC_IN_TOP = SC_IN_BOT ; - -sb_2__2__mux_tree_tapbuf_size6_0 mux_bottom_track_1 ( - .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_43_[0] , - bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , - bottom_left_grid_pin_49_[0] , chanx_left_in[1] } ) , - .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_bottom_track_1_undriven_sram_inv ) , - .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_82 ) ) ; -sb_2__2__mux_tree_tapbuf_size6_1 mux_bottom_track_5 ( - .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_43_[0] , - bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , - bottom_left_grid_pin_49_[0] , chanx_left_in[3] } ) , - .sram ( mux_tree_tapbuf_size6_1_sram ) , - .sram_inv ( mux_bottom_track_5_undriven_sram_inv ) , - .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_84 ) ) ; -sb_2__2__mux_tree_tapbuf_size6_2 mux_left_track_1 ( - .in ( { chany_bottom_in[19] , left_top_grid_pin_1_[0] , - left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , - left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , - .sram ( mux_tree_tapbuf_size6_2_sram ) , - .sram_inv ( mux_left_track_1_undriven_sram_inv ) , - .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_83 ) ) ; -sb_2__2__mux_tree_tapbuf_size6 mux_left_track_5 ( - .in ( { chany_bottom_in[1] , left_top_grid_pin_1_[0] , - left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , - left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , - .sram ( mux_tree_tapbuf_size6_3_sram ) , - .sram_inv ( mux_left_track_5_undriven_sram_inv ) , - .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_83 ) ) ; -sb_2__2__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_1 ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__2__mux_tree_tapbuf_size6_mem_1 mem_bottom_track_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__2__mux_tree_tapbuf_size6_mem_2 mem_left_track_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__2__mux_tree_tapbuf_size6_mem mem_left_track_5 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__2__mux_tree_tapbuf_size5_0 mux_bottom_track_3 ( - .in ( { bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , - bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , - chanx_left_in[2] } ) , - .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_bottom_track_3_undriven_sram_inv ) , - .out ( chany_bottom_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_82 ) ) ; -sb_2__2__mux_tree_tapbuf_size5_1 mux_bottom_track_7 ( - .in ( { bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , - bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , - chanx_left_in[4] } ) , - .sram ( mux_tree_tapbuf_size5_1_sram ) , - .sram_inv ( mux_bottom_track_7_undriven_sram_inv ) , - .out ( chany_bottom_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_84 ) ) ; -sb_2__2__mux_tree_tapbuf_size5_2 mux_left_track_3 ( - .in ( { chany_bottom_in[0] , left_bottom_grid_pin_34_[0] , - left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , - left_bottom_grid_pin_40_[0] } ) , - .sram ( mux_tree_tapbuf_size5_2_sram ) , - .sram_inv ( mux_left_track_3_undriven_sram_inv ) , - .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_82 ) ) ; -sb_2__2__mux_tree_tapbuf_size5 mux_left_track_7 ( - .in ( { chany_bottom_in[2] , left_bottom_grid_pin_34_[0] , - left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , - left_bottom_grid_pin_40_[0] } ) , - .sram ( mux_tree_tapbuf_size5_3_sram ) , - .sram_inv ( mux_left_track_7_undriven_sram_inv ) , - .out ( chanx_left_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_82 ) ) ; -sb_2__2__mux_tree_tapbuf_size5_mem_0 mem_bottom_track_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__2__mux_tree_tapbuf_size5_mem_1 mem_bottom_track_7 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__2__mux_tree_tapbuf_size5_mem_2 mem_left_track_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__2__mux_tree_tapbuf_size5_mem mem_left_track_7 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__2__mux_tree_tapbuf_size2_9 mux_bottom_track_9 ( - .in ( { bottom_right_grid_pin_1_[0] , chanx_left_in[5] } ) , - .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_bottom_track_9_undriven_sram_inv ) , - .out ( chany_bottom_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_84 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_0 mux_bottom_track_11 ( - .in ( { bottom_left_grid_pin_42_[0] , chanx_left_in[6] } ) , - .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_bottom_track_11_undriven_sram_inv ) , - .out ( chany_bottom_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_84 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_1 mux_bottom_track_13 ( - .in ( { bottom_left_grid_pin_43_[0] , chanx_left_in[7] } ) , - .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_bottom_track_13_undriven_sram_inv ) , - .out ( chany_bottom_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_81 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_2 mux_bottom_track_15 ( - .in ( { bottom_left_grid_pin_44_[0] , chanx_left_in[8] } ) , - .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_bottom_track_15_undriven_sram_inv ) , - .out ( chany_bottom_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_81 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_3 mux_bottom_track_17 ( - .in ( { bottom_left_grid_pin_45_[0] , chanx_left_in[9] } ) , - .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_bottom_track_17_undriven_sram_inv ) , - .out ( chany_bottom_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_81 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_4 mux_bottom_track_19 ( - .in ( { bottom_left_grid_pin_46_[0] , chanx_left_in[10] } ) , - .sram ( mux_tree_tapbuf_size2_5_sram ) , - .sram_inv ( mux_bottom_track_19_undriven_sram_inv ) , - .out ( chany_bottom_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_84 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_5 mux_bottom_track_21 ( - .in ( { bottom_left_grid_pin_47_[0] , chanx_left_in[11] } ) , - .sram ( mux_tree_tapbuf_size2_6_sram ) , - .sram_inv ( mux_bottom_track_21_undriven_sram_inv ) , - .out ( chany_bottom_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_81 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_6 mux_bottom_track_23 ( - .in ( { bottom_left_grid_pin_48_[0] , chanx_left_in[12] } ) , - .sram ( mux_tree_tapbuf_size2_7_sram ) , - .sram_inv ( mux_bottom_track_23_undriven_sram_inv ) , - .out ( chany_bottom_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_84 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_7 mux_bottom_track_27 ( - .in ( { bottom_left_grid_pin_42_[0] , chanx_left_in[14] } ) , - .sram ( mux_tree_tapbuf_size2_8_sram ) , - .sram_inv ( mux_bottom_track_27_undriven_sram_inv ) , - .out ( chany_bottom_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_84 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_8 mux_bottom_track_29 ( - .in ( { bottom_left_grid_pin_43_[0] , chanx_left_in[15] } ) , - .sram ( mux_tree_tapbuf_size2_9_sram ) , - .sram_inv ( mux_bottom_track_29_undriven_sram_inv ) , - .out ( chany_bottom_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_81 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_10 mux_left_track_11 ( - .in ( { chany_bottom_in[4] , left_bottom_grid_pin_34_[0] } ) , - .sram ( mux_tree_tapbuf_size2_10_sram ) , - .sram_inv ( mux_left_track_11_undriven_sram_inv ) , - .out ( chanx_left_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_82 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_11 mux_left_track_13 ( - .in ( { chany_bottom_in[5] , left_bottom_grid_pin_35_[0] } ) , - .sram ( mux_tree_tapbuf_size2_11_sram ) , - .sram_inv ( mux_left_track_13_undriven_sram_inv ) , - .out ( chanx_left_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_83 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_12 mux_left_track_15 ( - .in ( { chany_bottom_in[6] , left_bottom_grid_pin_36_[0] } ) , - .sram ( mux_tree_tapbuf_size2_12_sram ) , - .sram_inv ( mux_left_track_15_undriven_sram_inv ) , - .out ( chanx_left_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_83 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_13 mux_left_track_17 ( - .in ( { chany_bottom_in[7] , left_bottom_grid_pin_37_[0] } ) , - .sram ( mux_tree_tapbuf_size2_13_sram ) , - .sram_inv ( mux_left_track_17_undriven_sram_inv ) , - .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_83 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_14 mux_left_track_19 ( - .in ( { chany_bottom_in[8] , left_bottom_grid_pin_38_[0] } ) , - .sram ( mux_tree_tapbuf_size2_14_sram ) , - .sram_inv ( mux_left_track_19_undriven_sram_inv ) , - .out ( chanx_left_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_83 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_15 mux_left_track_21 ( - .in ( { chany_bottom_in[9] , left_bottom_grid_pin_39_[0] } ) , - .sram ( mux_tree_tapbuf_size2_15_sram ) , - .sram_inv ( mux_left_track_21_undriven_sram_inv ) , - .out ( chanx_left_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_82 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_16 mux_left_track_23 ( - .in ( { chany_bottom_in[10] , left_bottom_grid_pin_40_[0] } ) , - .sram ( mux_tree_tapbuf_size2_16_sram ) , - .sram_inv ( mux_left_track_23_undriven_sram_inv ) , - .out ( chanx_left_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_82 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_17 mux_left_track_27 ( - .in ( { chany_bottom_in[12] , left_bottom_grid_pin_34_[0] } ) , - .sram ( mux_tree_tapbuf_size2_17_sram ) , - .sram_inv ( mux_left_track_27_undriven_sram_inv ) , - .out ( chanx_left_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_82 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_18 mux_left_track_29 ( - .in ( { chany_bottom_in[13] , left_bottom_grid_pin_35_[0] } ) , - .sram ( mux_tree_tapbuf_size2_18_sram ) , - .sram_inv ( mux_left_track_29_undriven_sram_inv ) , - .out ( chanx_left_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_82 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_19 mux_left_track_31 ( - .in ( { chany_bottom_in[14] , left_bottom_grid_pin_36_[0] } ) , - .sram ( mux_tree_tapbuf_size2_19_sram ) , - .sram_inv ( mux_left_track_31_undriven_sram_inv ) , - .out ( chanx_left_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_83 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_20 mux_left_track_33 ( - .in ( { chany_bottom_in[15] , left_bottom_grid_pin_37_[0] } ) , - .sram ( mux_tree_tapbuf_size2_20_sram ) , - .sram_inv ( mux_left_track_33_undriven_sram_inv ) , - .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_83 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_21 mux_left_track_35 ( - .in ( { chany_bottom_in[16] , left_bottom_grid_pin_38_[0] } ) , - .sram ( mux_tree_tapbuf_size2_21_sram ) , - .sram_inv ( mux_left_track_35_undriven_sram_inv ) , - .out ( chanx_left_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_81 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_22 mux_left_track_37 ( - .in ( { chany_bottom_in[17] , left_bottom_grid_pin_39_[0] } ) , - .sram ( mux_tree_tapbuf_size2_22_sram ) , - .sram_inv ( mux_left_track_37_undriven_sram_inv ) , - .out ( chanx_left_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_83 ) ) ; -sb_2__2__mux_tree_tapbuf_size2 mux_left_track_39 ( - .in ( { chany_bottom_in[18] , left_bottom_grid_pin_40_[0] } ) , - .sram ( mux_tree_tapbuf_size2_23_sram ) , - .sram_inv ( mux_left_track_39_undriven_sram_inv ) , - .out ( chanx_left_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_82 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_9 mem_bottom_track_9 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_0 mem_bottom_track_11 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_1 mem_bottom_track_13 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_2 mem_bottom_track_15 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_3 mem_bottom_track_17 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_4 mem_bottom_track_19 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_5 mem_bottom_track_21 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_6 mem_bottom_track_23 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_7 mem_bottom_track_27 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_8_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_8 mem_bottom_track_29 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_9_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_10 mem_left_track_11 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_10_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_11 mem_left_track_13 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_11_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_12 mem_left_track_15 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_12_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_13 mem_left_track_17 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_13_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_14 mem_left_track_19 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_14_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_15 mem_left_track_21 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_15_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_16 mem_left_track_23 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_16_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_17 mem_left_track_27 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_17_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_18 mem_left_track_29 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_18_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_19 mem_left_track_31 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_19_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_20 mem_left_track_33 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_20_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_21 mem_left_track_35 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_21_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_22 mem_left_track_37 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_22_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem mem_left_track_39 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , - .ccff_tail ( { ropt_net_91 } ) , - .mem_out ( mux_tree_tapbuf_size2_23_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__2__mux_tree_tapbuf_size3_0 mux_bottom_track_25 ( - .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_49_[0] , - chanx_left_in[13] } ) , - .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_bottom_track_25_undriven_sram_inv ) , - .out ( chany_bottom_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_84 ) ) ; -sb_2__2__mux_tree_tapbuf_size3 mux_left_track_9 ( - .in ( { chany_bottom_in[3] , left_top_grid_pin_1_[0] , - left_bottom_grid_pin_41_[0] } ) , - .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_left_track_9_undriven_sram_inv ) , - .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_82 ) ) ; -sb_2__2__mux_tree_tapbuf_size3_1 mux_left_track_25 ( - .in ( { chany_bottom_in[11] , left_top_grid_pin_1_[0] , - left_bottom_grid_pin_41_[0] } ) , - .sram ( mux_tree_tapbuf_size3_2_sram ) , - .sram_inv ( mux_left_track_25_undriven_sram_inv ) , - .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_82 ) ) ; -sb_2__2__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_25 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__2__mux_tree_tapbuf_size3_mem mem_left_track_9 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__2__mux_tree_tapbuf_size3_mem_1 mem_left_track_25 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1543 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1544 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1545 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1546 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1547 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1548 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1549 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1550 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1551 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1552 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1553 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1554 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1555 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1556 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1557 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1558 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1559 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1560 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1561 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1562 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1563 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1564 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1565 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1566 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1567 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1568 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1569 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1570 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1571 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1572 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1573 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1574 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1575 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1576 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1577 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1578 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1579 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1580 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_688 ( .A ( ropt_net_94 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_689 ( .A ( ropt_net_95 ) , - .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_690 ( .A ( ropt_net_96 ) , - .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_72 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_81 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__4 ( .A ( chanx_left_in[19] ) , - .X ( ropt_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_6__5 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_86 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_691 ( .A ( ropt_net_97 ) , - .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_692 ( .A ( ropt_net_98 ) , - .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_693 ( .A ( ropt_net_99 ) , - .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_694 ( .A ( ropt_net_100 ) , - .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_74 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_82 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_76 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_83 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_78 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_84 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_681 ( .A ( ropt_net_86 ) , - .X ( ropt_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_682 ( .A ( chanx_left_in[0] ) , - .X ( ropt_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_683 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_684 ( .A ( chanx_left_in[16] ) , - .X ( ropt_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_685 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_97 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_686 ( .A ( ropt_net_91 ) , - .X ( ropt_net_94 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_687 ( .A ( ropt_net_92 ) , - .X ( ropt_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y0 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y0 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x257600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x276000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x358800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x418600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x437000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x584200y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x616400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x699200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x257600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x276000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x386400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x423200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x607200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x625600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x782000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x818800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x855600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x294400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x312800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 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\xofiller!sky130_fd_sc_hd__fill_8!x653200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x690000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x708400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x759000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x768200y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x800400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x837200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x874000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x910800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x294400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 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VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x133400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x142600y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x188600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x239200y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x331200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x391000y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x437000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x446200y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x524400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x542800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x630200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x680800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x699200y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x814200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x851000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x133400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x193200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x340400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x349600y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x427800y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x506000y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x547400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x584200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x602600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x110400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x161000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x179400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x188600y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x266800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x303600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x322000y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x437000y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x556600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x565800y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x680800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x404800y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x450800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x529000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x565800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x602600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x639400y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x754400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x791200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x828000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x864800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x101200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x179400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x239200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x276000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x294400y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x427800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x446200y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x524400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x680800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x699200y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x179400y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x345000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x395600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x404800y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x450800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x487600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x524400y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x602600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x639400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x657800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x814200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x648600y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x694600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x713000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x722200y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x768200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x805000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x841800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x878600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x36800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x46000y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x92000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x128800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x179400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x239200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x276000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x312800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x381800y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x460000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x699200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x717600y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x805000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x841800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x55200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x92000y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x138000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x174800y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x437000y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x483000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x570400y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x616400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x676200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x694600y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x736000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x754400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x800400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x837200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x874000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x910800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x340400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x358800y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x437000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x519800y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x708400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x717600y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x82800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x119600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x128800y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x170200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x207000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x243800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x253000y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x299000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x317400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x538200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x556600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x565800y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x644000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x653200y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x731400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x768200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x805000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x841800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x878600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x55200y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x133400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x170200y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x331200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x349600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x358800y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x400200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x437000y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x524400y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x602600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x639400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x722200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x814200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x851000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x124200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x133400y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x179400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x299000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x464600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x515200y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x598000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x616400y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x662400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x680800y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x722200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x740600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x749800y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x828000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x864800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x901600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x59800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x96600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x188600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x225400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x262200y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x340400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x460000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x496800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x515200y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x533600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x64400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x101200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x119600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x317400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x432400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x450800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x533600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x694600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x754400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x791200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x828000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x864800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x901600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x59800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x69000y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x211600y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x230000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x239200y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x285200y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x363400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x400200y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x731400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x740600y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x782000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x818800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x855600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x36800y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x257600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x276000y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x322000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x358800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x538200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x547400y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x708400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x745200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x782000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x818800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x855600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x892400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x910800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x745200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x782000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x818800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x855600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x138000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x174800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x211600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x248400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x322000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x473800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x492200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x579600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x598000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x749800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x786600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x823400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x860200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x897000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x55200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x92000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x110400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x119600y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x165600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x211600y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x294400y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x381800y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x575000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x593400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x754400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x791200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x828000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x864800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x59800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x96600y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x174800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x257600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x276000y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x354200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x441600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x584200y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x128800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x147200y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x179400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x216200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x253000y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x299000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x317400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x326600y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x483000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x607200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x625600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x676200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x713000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x749800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x786600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x823400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x860200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x133400y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x165600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x184000y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x262200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x289800y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x335800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x391000y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x510600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x529000y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x575000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x584200y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x184000y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x414000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x450800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x708400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x745200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x782000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x818800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x855600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x814200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x851000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x257600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x372600y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x414000y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x492200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x529000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x565800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x602600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x639400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x676200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x713000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x749800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x786600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x823400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x860200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x846400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x864800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y870400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y870400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y897600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y897600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x846400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x864800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y924800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y924800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y952000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y952000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__60 ( .A ( mem_out[1] ) , - .X ( net_net_79 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_78 ( .A ( net_net_79 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__59 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__58 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__57 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__56 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__55 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__54 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__53 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__52 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__51 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__50 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_67 ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__49 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__48 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__47 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__46 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_65 ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( BUF_net_65 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_107 ( .A ( BUF_net_65 ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size9_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__45 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:8] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_106 ( - .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__44 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__43 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__42 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__41 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__40 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__39 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__38 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__37 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__36 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__35 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size14_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__34 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size14_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__33 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size14_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:13] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size14 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:13] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__32 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__31 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__30 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__29 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__28 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1_ ( prog_clk , chany_top_in , top_left_grid_pin_42_ , - top_left_grid_pin_43_ , top_left_grid_pin_44_ , top_left_grid_pin_45_ , - top_left_grid_pin_46_ , top_left_grid_pin_47_ , top_left_grid_pin_48_ , - top_left_grid_pin_49_ , top_right_grid_pin_1_ , chany_bottom_in , - bottom_right_grid_pin_1_ , bottom_left_grid_pin_42_ , - bottom_left_grid_pin_43_ , bottom_left_grid_pin_44_ , - bottom_left_grid_pin_45_ , bottom_left_grid_pin_46_ , - bottom_left_grid_pin_47_ , bottom_left_grid_pin_48_ , - bottom_left_grid_pin_49_ , chanx_left_in , left_bottom_grid_pin_34_ , - left_bottom_grid_pin_35_ , left_bottom_grid_pin_36_ , - left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , - left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , - left_bottom_grid_pin_41_ , ccff_head , chany_top_out , chany_bottom_out , - chanx_left_out , ccff_tail , VDD , VSS , Test_en__FEEDTHRU_0 , - Test_en__FEEDTHRU_1 , clk__FEEDTHRU_0 , clk__FEEDTHRU_1 ) ; -input [0:0] prog_clk ; -input [0:19] chany_top_in ; -input [0:0] top_left_grid_pin_42_ ; -input [0:0] top_left_grid_pin_43_ ; -input [0:0] top_left_grid_pin_44_ ; -input [0:0] top_left_grid_pin_45_ ; -input [0:0] top_left_grid_pin_46_ ; -input [0:0] top_left_grid_pin_47_ ; -input [0:0] top_left_grid_pin_48_ ; -input [0:0] top_left_grid_pin_49_ ; -input [0:0] top_right_grid_pin_1_ ; -input [0:19] chany_bottom_in ; -input [0:0] bottom_right_grid_pin_1_ ; -input [0:0] bottom_left_grid_pin_42_ ; -input [0:0] bottom_left_grid_pin_43_ ; -input [0:0] bottom_left_grid_pin_44_ ; -input [0:0] bottom_left_grid_pin_45_ ; -input [0:0] bottom_left_grid_pin_46_ ; -input [0:0] bottom_left_grid_pin_47_ ; -input [0:0] bottom_left_grid_pin_48_ ; -input [0:0] bottom_left_grid_pin_49_ ; -input [0:19] chanx_left_in ; -input [0:0] left_bottom_grid_pin_34_ ; -input [0:0] left_bottom_grid_pin_35_ ; -input [0:0] left_bottom_grid_pin_36_ ; -input [0:0] left_bottom_grid_pin_37_ ; -input [0:0] left_bottom_grid_pin_38_ ; -input [0:0] left_bottom_grid_pin_39_ ; -input [0:0] left_bottom_grid_pin_40_ ; -input [0:0] left_bottom_grid_pin_41_ ; -input [0:0] ccff_head ; -output [0:19] chany_top_out ; -output [0:19] chany_bottom_out ; -output [0:19] chanx_left_out ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; -input [0:0] Test_en__FEEDTHRU_0 ; -output [0:0] Test_en__FEEDTHRU_1 ; -input [0:0] clk__FEEDTHRU_0 ; -output [0:0] clk__FEEDTHRU_1 ; - -wire [0:2] mux_bottom_track_17_undriven_sram_inv ; -wire [0:3] mux_bottom_track_1_undriven_sram_inv ; -wire [0:2] mux_bottom_track_25_undriven_sram_inv ; -wire [0:2] mux_bottom_track_33_undriven_sram_inv ; -wire [0:3] mux_bottom_track_3_undriven_sram_inv ; -wire [0:3] mux_bottom_track_5_undriven_sram_inv ; -wire [0:3] mux_bottom_track_9_undriven_sram_inv ; -wire [0:2] mux_left_track_11_undriven_sram_inv ; -wire [0:2] mux_left_track_13_undriven_sram_inv ; -wire [0:2] mux_left_track_15_undriven_sram_inv ; -wire [0:1] mux_left_track_17_undriven_sram_inv ; -wire [0:1] mux_left_track_19_undriven_sram_inv ; -wire [0:2] mux_left_track_1_undriven_sram_inv ; -wire [0:1] mux_left_track_21_undriven_sram_inv ; -wire [0:1] mux_left_track_23_undriven_sram_inv ; -wire [0:1] mux_left_track_25_undriven_sram_inv ; -wire [0:1] mux_left_track_29_undriven_sram_inv ; -wire [0:1] mux_left_track_31_undriven_sram_inv ; -wire [0:1] mux_left_track_33_undriven_sram_inv ; -wire [0:1] mux_left_track_35_undriven_sram_inv ; -wire [0:1] mux_left_track_37_undriven_sram_inv ; -wire [0:1] mux_left_track_39_undriven_sram_inv ; -wire [0:2] mux_left_track_3_undriven_sram_inv ; -wire [0:2] mux_left_track_5_undriven_sram_inv ; -wire [0:2] mux_left_track_7_undriven_sram_inv ; -wire [0:2] mux_left_track_9_undriven_sram_inv ; -wire [0:3] mux_top_track_0_undriven_sram_inv ; -wire [0:2] mux_top_track_16_undriven_sram_inv ; -wire [0:2] mux_top_track_24_undriven_sram_inv ; -wire [0:3] mux_top_track_2_undriven_sram_inv ; -wire [0:2] mux_top_track_32_undriven_sram_inv ; -wire [0:3] mux_top_track_4_undriven_sram_inv ; -wire [0:3] mux_top_track_8_undriven_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size14_0_sram ; -wire [0:3] mux_tree_tapbuf_size14_1_sram ; -wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail ; -wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_5_sram ; -wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; -wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:1] mux_tree_tapbuf_size3_2_sram ; -wire [0:1] mux_tree_tapbuf_size3_3_sram ; -wire [0:1] mux_tree_tapbuf_size3_4_sram ; -wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size4_0_sram ; -wire [0:2] mux_tree_tapbuf_size4_1_sram ; -wire [0:2] mux_tree_tapbuf_size4_2_sram ; -wire [0:2] mux_tree_tapbuf_size4_3_sram ; -wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size6_1_sram ; -wire [0:2] mux_tree_tapbuf_size6_2_sram ; -wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size7_0_sram ; -wire [0:2] mux_tree_tapbuf_size7_1_sram ; -wire [0:2] mux_tree_tapbuf_size7_2_sram ; -wire [0:2] mux_tree_tapbuf_size7_3_sram ; -wire [0:2] mux_tree_tapbuf_size7_4_sram ; -wire [0:2] mux_tree_tapbuf_size7_5_sram ; -wire [0:2] mux_tree_tapbuf_size7_6_sram ; -wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:3] mux_tree_tapbuf_size8_2_sram ; -wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size9_0_sram ; -wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ; -supply1 VDD ; -supply0 VSS ; - -assign clk__FEEDTHRU_1[0] = clk__FEEDTHRU_0[0] ; - -sb_2__1__mux_tree_tapbuf_size10 mux_top_track_0 ( - .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , - top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , - top_right_grid_pin_1_[0] , chany_bottom_in[2] , chany_bottom_in[12] , - chanx_left_in[0] , chanx_left_in[7] , chanx_left_in[14] } ) , - .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_top_track_0_undriven_sram_inv ) , - .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_126 ) ) ; -sb_2__1__mux_tree_tapbuf_size10_0 mux_bottom_track_1 ( - .in ( { chany_top_in[2] , chany_top_in[12] , bottom_right_grid_pin_1_[0] , - bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , - bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , - chanx_left_in[1] , chanx_left_in[8] , chanx_left_in[15] } ) , - .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_bottom_track_1_undriven_sram_inv ) , - .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_126 ) ) ; -sb_2__1__mux_tree_tapbuf_size10_mem mem_top_track_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__1__mux_tree_tapbuf_size10_mem_0 mem_bottom_track_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__1__mux_tree_tapbuf_size8_1 mux_top_track_2 ( - .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , - top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , - chany_bottom_in[4] , chany_bottom_in[13] , chanx_left_in[6] , - chanx_left_in[13] } ) , - .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_top_track_2_undriven_sram_inv ) , - .out ( chany_top_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_127 ) ) ; -sb_2__1__mux_tree_tapbuf_size8 mux_top_track_8 ( - .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_46_[0] , - top_right_grid_pin_1_[0] , chany_bottom_in[6] , chany_bottom_in[16] , - chanx_left_in[4] , chanx_left_in[11] , chanx_left_in[18] } ) , - .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_top_track_8_undriven_sram_inv ) , - .out ( chany_top_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_127 ) ) ; -sb_2__1__mux_tree_tapbuf_size8_0 mux_bottom_track_9 ( - .in ( { chany_top_in[6] , chany_top_in[16] , bottom_right_grid_pin_1_[0] , - bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_49_[0] , - chanx_left_in[4] , chanx_left_in[11] , chanx_left_in[18] } ) , - .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_bottom_track_9_undriven_sram_inv ) , - .out ( chany_bottom_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_125 ) ) ; -sb_2__1__mux_tree_tapbuf_size8_mem_1 mem_top_track_2 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__1__mux_tree_tapbuf_size8_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__1__mux_tree_tapbuf_size8_mem_0 mem_bottom_track_9 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__1__mux_tree_tapbuf_size14 mux_top_track_4 ( - .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_43_[0] , - top_left_grid_pin_44_[0] , top_left_grid_pin_45_[0] , - top_left_grid_pin_46_[0] , top_left_grid_pin_47_[0] , - top_left_grid_pin_48_[0] , top_left_grid_pin_49_[0] , - top_right_grid_pin_1_[0] , chany_bottom_in[5] , chany_bottom_in[14] , - chanx_left_in[5] , chanx_left_in[12] , chanx_left_in[19] } ) , - .sram ( mux_tree_tapbuf_size14_0_sram ) , - .sram_inv ( mux_top_track_4_undriven_sram_inv ) , - .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_127 ) ) ; -sb_2__1__mux_tree_tapbuf_size14_0 mux_bottom_track_5 ( - .in ( { chany_top_in[5] , chany_top_in[14] , bottom_right_grid_pin_1_[0] , - bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_43_[0] , - bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_45_[0] , - bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_47_[0] , - bottom_left_grid_pin_48_[0] , bottom_left_grid_pin_49_[0] , - chanx_left_in[3] , chanx_left_in[10] , chanx_left_in[17] } ) , - .sram ( mux_tree_tapbuf_size14_1_sram ) , - .sram_inv ( mux_bottom_track_5_undriven_sram_inv ) , - .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_125 ) ) ; -sb_2__1__mux_tree_tapbuf_size14_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size14_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__1__mux_tree_tapbuf_size14_mem_0 mem_bottom_track_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size14_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__1__mux_tree_tapbuf_size7_5 mux_top_track_16 ( - .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_47_[0] , - chany_bottom_in[8] , chany_bottom_in[17] , chanx_left_in[3] , - chanx_left_in[10] , chanx_left_in[17] } ) , - .sram ( mux_tree_tapbuf_size7_0_sram ) , - .sram_inv ( mux_top_track_16_undriven_sram_inv ) , - .out ( chany_top_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_126 ) ) ; -sb_2__1__mux_tree_tapbuf_size7 mux_top_track_24 ( - .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_48_[0] , - chany_bottom_in[9] , chany_bottom_in[18] , chanx_left_in[2] , - chanx_left_in[9] , chanx_left_in[16] } ) , - .sram ( mux_tree_tapbuf_size7_1_sram ) , - .sram_inv ( mux_top_track_24_undriven_sram_inv ) , - .out ( chany_top_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_126 ) ) ; -sb_2__1__mux_tree_tapbuf_size7_0 mux_bottom_track_17 ( - .in ( { chany_top_in[8] , chany_top_in[17] , bottom_left_grid_pin_42_[0] , - bottom_left_grid_pin_46_[0] , chanx_left_in[5] , chanx_left_in[12] , - chanx_left_in[19] } ) , - .sram ( mux_tree_tapbuf_size7_2_sram ) , - .sram_inv ( mux_bottom_track_17_undriven_sram_inv ) , - .out ( chany_bottom_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_126 ) ) ; -sb_2__1__mux_tree_tapbuf_size7_1 mux_left_track_1 ( - .in ( { chany_top_in[0] , chany_top_in[2] , chany_bottom_in[2] , - left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , - left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , - .sram ( mux_tree_tapbuf_size7_3_sram ) , - .sram_inv ( mux_left_track_1_undriven_sram_inv ) , - .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_128 ) ) ; -sb_2__1__mux_tree_tapbuf_size7_2 mux_left_track_3 ( - .in ( { chany_top_in[4] , chany_bottom_in[0] , chany_bottom_in[4] , - left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , - left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , - .sram ( mux_tree_tapbuf_size7_4_sram ) , - .sram_inv ( mux_left_track_3_undriven_sram_inv ) , - .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_128 ) ) ; -sb_2__1__mux_tree_tapbuf_size7_3 mux_left_track_5 ( - .in ( { chany_top_in[5] , chany_bottom_in[1] , chany_bottom_in[5] , - left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , - left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , - .sram ( mux_tree_tapbuf_size7_5_sram ) , - .sram_inv ( mux_left_track_5_undriven_sram_inv ) , - .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_128 ) ) ; -sb_2__1__mux_tree_tapbuf_size7_4 mux_left_track_7 ( - .in ( { chany_top_in[6] , chany_bottom_in[3] , chany_bottom_in[6] , - left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , - left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , - .sram ( mux_tree_tapbuf_size7_6_sram ) , - .sram_inv ( mux_left_track_7_undriven_sram_inv ) , - .out ( chanx_left_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_128 ) ) ; -sb_2__1__mux_tree_tapbuf_size7_mem_5 mem_top_track_16 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__1__mux_tree_tapbuf_size7_mem mem_top_track_24 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__1__mux_tree_tapbuf_size7_mem_0 mem_bottom_track_17 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__1__mux_tree_tapbuf_size7_mem_1 mem_left_track_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__1__mux_tree_tapbuf_size7_mem_2 mem_left_track_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__1__mux_tree_tapbuf_size7_mem_3 mem_left_track_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__1__mux_tree_tapbuf_size7_mem_4 mem_left_track_7 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__1__mux_tree_tapbuf_size6 mux_top_track_32 ( - .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_49_[0] , - chany_bottom_in[10] , chanx_left_in[1] , chanx_left_in[8] , - chanx_left_in[15] } ) , - .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_top_track_32_undriven_sram_inv ) , - .out ( chany_top_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_126 ) ) ; -sb_2__1__mux_tree_tapbuf_size6_0 mux_bottom_track_25 ( - .in ( { chany_top_in[9] , chany_top_in[18] , bottom_left_grid_pin_43_[0] , - bottom_left_grid_pin_47_[0] , chanx_left_in[6] , chanx_left_in[13] } ) , - .sram ( mux_tree_tapbuf_size6_1_sram ) , - .sram_inv ( mux_bottom_track_25_undriven_sram_inv ) , - .out ( chany_bottom_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_125 ) ) ; -sb_2__1__mux_tree_tapbuf_size6_1 mux_bottom_track_33 ( - .in ( { chany_top_in[10] , bottom_left_grid_pin_44_[0] , - bottom_left_grid_pin_48_[0] , chanx_left_in[0] , chanx_left_in[7] , - chanx_left_in[14] } ) , - .sram ( mux_tree_tapbuf_size6_2_sram ) , - .sram_inv ( mux_bottom_track_33_undriven_sram_inv ) , - .out ( chany_bottom_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_126 ) ) ; -sb_2__1__mux_tree_tapbuf_size6_mem mem_top_track_32 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__1__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_25 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__1__mux_tree_tapbuf_size6_mem_1 mem_bottom_track_33 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__1__mux_tree_tapbuf_size9 mux_bottom_track_3 ( - .in ( { chany_top_in[4] , chany_top_in[13] , bottom_left_grid_pin_42_[0] , - bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , - bottom_left_grid_pin_48_[0] , chanx_left_in[2] , chanx_left_in[9] , - chanx_left_in[16] } ) , - .sram ( mux_tree_tapbuf_size9_0_sram ) , - .sram_inv ( mux_bottom_track_3_undriven_sram_inv ) , - .out ( { ropt_net_132 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_125 ) ) ; -sb_2__1__mux_tree_tapbuf_size9_mem mem_bottom_track_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size9_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__1__mux_tree_tapbuf_size4 mux_left_track_9 ( - .in ( { chany_top_in[8] , chany_bottom_in[7] , chany_bottom_in[8] , - left_bottom_grid_pin_34_[0] } ) , - .sram ( mux_tree_tapbuf_size4_0_sram ) , - .sram_inv ( mux_left_track_9_undriven_sram_inv ) , - .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_128 ) ) ; -sb_2__1__mux_tree_tapbuf_size4_0 mux_left_track_11 ( - .in ( { chany_top_in[9] , chany_bottom_in[9] , chany_bottom_in[11] , - left_bottom_grid_pin_35_[0] } ) , - .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_left_track_11_undriven_sram_inv ) , - .out ( chanx_left_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_128 ) ) ; -sb_2__1__mux_tree_tapbuf_size4_1 mux_left_track_13 ( - .in ( { chany_top_in[10] , chany_bottom_in[10] , chany_bottom_in[15] , - left_bottom_grid_pin_36_[0] } ) , - .sram ( mux_tree_tapbuf_size4_2_sram ) , - .sram_inv ( mux_left_track_13_undriven_sram_inv ) , - .out ( { ropt_net_130 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_125 ) ) ; -sb_2__1__mux_tree_tapbuf_size4_2 mux_left_track_15 ( - .in ( { chany_top_in[12] , chany_bottom_in[12] , chany_bottom_in[19] , - left_bottom_grid_pin_37_[0] } ) , - .sram ( mux_tree_tapbuf_size4_3_sram ) , - .sram_inv ( mux_left_track_15_undriven_sram_inv ) , - .out ( chanx_left_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_125 ) ) ; -sb_2__1__mux_tree_tapbuf_size4_mem mem_left_track_9 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__1__mux_tree_tapbuf_size4_mem_0 mem_left_track_11 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__1__mux_tree_tapbuf_size4_mem_1 mem_left_track_13 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__1__mux_tree_tapbuf_size4_mem_2 mem_left_track_15 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__1__mux_tree_tapbuf_size3_0 mux_left_track_17 ( - .in ( { chany_top_in[13] , chany_bottom_in[13] , - left_bottom_grid_pin_38_[0] } ) , - .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_left_track_17_undriven_sram_inv ) , - .out ( { ropt_net_131 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_125 ) ) ; -sb_2__1__mux_tree_tapbuf_size3_1 mux_left_track_19 ( - .in ( { chany_top_in[14] , chany_bottom_in[14] , - left_bottom_grid_pin_39_[0] } ) , - .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_left_track_19_undriven_sram_inv ) , - .out ( chanx_left_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_127 ) ) ; -sb_2__1__mux_tree_tapbuf_size3_2 mux_left_track_21 ( - .in ( { chany_top_in[16] , chany_bottom_in[16] , - left_bottom_grid_pin_40_[0] } ) , - .sram ( mux_tree_tapbuf_size3_2_sram ) , - .sram_inv ( mux_left_track_21_undriven_sram_inv ) , - .out ( chanx_left_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_128 ) ) ; -sb_2__1__mux_tree_tapbuf_size3_3 mux_left_track_23 ( - .in ( { chany_top_in[17] , chany_bottom_in[17] , - left_bottom_grid_pin_41_[0] } ) , - .sram ( mux_tree_tapbuf_size3_3_sram ) , - .sram_inv ( mux_left_track_23_undriven_sram_inv ) , - .out ( chanx_left_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_127 ) ) ; -sb_2__1__mux_tree_tapbuf_size3 mux_left_track_25 ( - .in ( { chany_top_in[18] , chany_bottom_in[18] , - left_bottom_grid_pin_34_[0] } ) , - .sram ( mux_tree_tapbuf_size3_4_sram ) , - .sram_inv ( mux_left_track_25_undriven_sram_inv ) , - .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_128 ) ) ; -sb_2__1__mux_tree_tapbuf_size3_mem_0 mem_left_track_17 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__1__mux_tree_tapbuf_size3_mem_1 mem_left_track_19 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__1__mux_tree_tapbuf_size3_mem_2 mem_left_track_21 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__1__mux_tree_tapbuf_size3_mem_3 mem_left_track_23 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__1__mux_tree_tapbuf_size3_mem mem_left_track_25 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__1__mux_tree_tapbuf_size2_0 mux_left_track_29 ( - .in ( { chany_top_in[19] , left_bottom_grid_pin_36_[0] } ) , - .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_left_track_29_undriven_sram_inv ) , - .out ( chanx_left_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_128 ) ) ; -sb_2__1__mux_tree_tapbuf_size2_1 mux_left_track_31 ( - .in ( { chany_top_in[15] , left_bottom_grid_pin_37_[0] } ) , - .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_left_track_31_undriven_sram_inv ) , - .out ( chanx_left_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_127 ) ) ; -sb_2__1__mux_tree_tapbuf_size2_2 mux_left_track_33 ( - .in ( { chany_top_in[11] , left_bottom_grid_pin_38_[0] } ) , - .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_left_track_33_undriven_sram_inv ) , - .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_127 ) ) ; -sb_2__1__mux_tree_tapbuf_size2_3 mux_left_track_35 ( - .in ( { chany_top_in[7] , left_bottom_grid_pin_39_[0] } ) , - .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_left_track_35_undriven_sram_inv ) , - .out ( chanx_left_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_127 ) ) ; -sb_2__1__mux_tree_tapbuf_size2_4 mux_left_track_37 ( - .in ( { chany_top_in[3] , left_bottom_grid_pin_40_[0] } ) , - .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_left_track_37_undriven_sram_inv ) , - .out ( chanx_left_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_127 ) ) ; -sb_2__1__mux_tree_tapbuf_size2 mux_left_track_39 ( - .in ( { chany_top_in[1] , left_bottom_grid_pin_41_[0] } ) , - .sram ( mux_tree_tapbuf_size2_5_sram ) , - .sram_inv ( mux_left_track_39_undriven_sram_inv ) , - .out ( chanx_left_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_127 ) ) ; -sb_2__1__mux_tree_tapbuf_size2_mem_0 mem_left_track_29 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__1__mux_tree_tapbuf_size2_mem_1 mem_left_track_31 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__1__mux_tree_tapbuf_size2_mem_2 mem_left_track_33 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__1__mux_tree_tapbuf_size2_mem_3 mem_left_track_35 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__1__mux_tree_tapbuf_size2_mem_4 mem_left_track_37 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__1__mux_tree_tapbuf_size2_mem mem_left_track_39 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .ccff_tail ( { ropt_net_134 } ) , - .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1500 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1501 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1502 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1503 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1504 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1505 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1506 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1507 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1508 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1509 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1510 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1511 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1512 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1513 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1514 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1515 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1516 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1517 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1518 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1519 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1520 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1521 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1522 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1523 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1524 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1525 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1526 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1527 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1528 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1529 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1530 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1531 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1532 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1533 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1534 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1535 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1536 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1537 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1538 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1539 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1540 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1541 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_126 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__3 ( .A ( chany_top_in[6] ) , - .X ( ropt_net_145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_120 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chany_top_in[9] ) , - .X ( ropt_net_156 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__6 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__7 ( .A ( chany_top_in[12] ) , - .X ( ropt_net_151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_122 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chany_top_in[14] ) , - .X ( ropt_net_150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chany_top_in[16] ) , - .X ( ropt_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( chany_top_in[17] ) , - .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__12 ( .A ( chany_top_in[18] ) , - .X ( ropt_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chany_bottom_in[2] ) , - .X ( ropt_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__14 ( .A ( chany_bottom_in[4] ) , - .X ( ropt_net_142 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__15 ( .A ( chany_bottom_in[5] ) , - .X ( ropt_net_144 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__16 ( .A ( chany_bottom_in[6] ) , - .X ( aps_rename_1_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_130 ) , - .X ( ropt_net_168 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( ropt_net_131 ) , - .X ( chanx_left_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_132 ) , - .X ( ropt_net_169 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__20 ( .A ( chany_bottom_in[12] ) , - .X ( ropt_net_158 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_161 ) , - .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_23__22 ( .A ( chany_bottom_in[14] ) , - .X ( ropt_net_139 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_162 ) , - .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_25__24 ( .A ( chany_bottom_in[17] ) , - .X ( ropt_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_26__25 ( .A ( chany_bottom_in[18] ) , - .X ( ropt_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_163 ) , - .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_133 ) , - .X ( ropt_net_173 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_759 ( .A ( ropt_net_164 ) , - .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_165 ) , - .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_166 ) , - .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( ropt_net_134 ) , - .X ( ropt_net_180 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( - .A ( chany_bottom_in[16] ) , .X ( ropt_net_182 ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( - .A ( chany_bottom_in[13] ) , .X ( ropt_net_181 ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( chany_top_in[13] ) , - .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_167 ) , - .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_763 ( .A ( ropt_net_168 ) , - .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_77 ( - .A ( left_bottom_grid_pin_35_[0] ) , .X ( ropt_net_133 ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_81 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( chany_top_in[8] ) , - .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_766 ( .A ( ropt_net_169 ) , - .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_139 ) , - .X ( ropt_net_161 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_140 ) , - .X ( ropt_net_164 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( chany_bottom_in[8] ) , - .X ( ropt_net_166 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( ropt_net_170 ) , - .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_98 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_183 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_99 ( .A ( chany_top_in[4] ) , - .X ( ropt_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_100 ( .A ( Test_en__FEEDTHRU_0[0] ) , - .X ( ropt_net_152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( ropt_net_142 ) , - .X ( ropt_net_167 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_103 ( .A ( aps_rename_1_ ) , - .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_769 ( .A ( ropt_net_171 ) , - .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_143 ) , - .X ( ropt_net_177 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_144 ) , - .X ( ropt_net_176 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_145 ) , - .X ( ropt_net_163 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_742 ( .A ( ropt_net_146 ) , - .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_172 ) , - .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_113 ( .A ( chany_bottom_in[10] ) , - .X ( ropt_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_147 ) , - .X ( ropt_net_162 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_148 ) , - .X ( ropt_net_174 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_149 ) , - .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_150 ) , - .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( ropt_net_151 ) , - .X ( ropt_net_171 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_152 ) , - .X ( ropt_net_178 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( .A ( ropt_net_153 ) , - .X ( ropt_net_179 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_154 ) , - .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_155 ) , - .X ( ropt_net_175 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_156 ) , - .X ( ropt_net_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_157 ) , - .X ( ropt_net_170 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_158 ) , - .X ( ropt_net_172 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_771 ( .A ( ropt_net_173 ) , - .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_772 ( .A ( ropt_net_174 ) , - .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_773 ( .A ( ropt_net_175 ) , - .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_774 ( .A ( ropt_net_176 ) , - .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( ropt_net_177 ) , - .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( ropt_net_178 ) , - .X ( Test_en__FEEDTHRU_1[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( ropt_net_179 ) , - .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_180 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_181 ) , - .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_182 ) , - .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_183 ) , - .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y0 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y0 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x257600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x276000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x285200y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x851000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x257600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x276000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x285200y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x625600y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x717600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x257600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x276000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x331200y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x805000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x841800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x878600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x630200y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x717600y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x759000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x860200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x220800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x510600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x685400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x703800y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x823400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x860200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x897000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x105800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x115000y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x161000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x179400y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x225400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x317400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x326600y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x579600y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x736000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x786600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x69000y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x115000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x151800y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x197800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x483000y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x529000y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x837200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x874000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x910800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x101200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x151800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x161000y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x207000y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x253000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x303600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x312800y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x358800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x395600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x404800y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x450800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x487600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x524400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x533600y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x579600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x588800y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x713000y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x795800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x115000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x165600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x216200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x266800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x326600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x335800y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x450800y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x496800y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x575000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x584200y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x630200y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x676200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x694600y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x860200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x897000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x59800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x170200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x207000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x322000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x372600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x409400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x487600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x496800y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x653200y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x777400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x795800y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x837200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x101200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x179400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x188600y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x276000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x285200y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x538200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x671600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x731400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x749800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x73600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x82800y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x165600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x174800y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x257600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x506000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x588800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x607200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x736000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x754400y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x55200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x501400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x584200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x694600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x754400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x791200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x874000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x910800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x101200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x138000y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x285200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x335800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x354200y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x400200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x418600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x662400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x717600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x736000y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x823400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x860200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x239200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x289800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x308200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x358800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x409400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x492200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x529000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x547400y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x625600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x708400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x726800y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x809600y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x851000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x161000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x179400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x515200y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x561200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x579600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x722200y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x768200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x786600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x147200y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x193200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x266800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x303600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x322000y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x363400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x464600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x473800y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x515200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x575000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x584200y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x699200y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x745200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x754400y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x874000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x910800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x73600y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x138000y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x289800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x423200y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x469200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x487600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x496800y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x611800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x630200y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x676200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x713000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x749800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x786600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x805000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x814200y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x855600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x124200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x289800y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x409400y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x487600y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x565800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x575000y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x621000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x630200y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x676200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x726800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x786600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x878600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x73600y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x105800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x115000y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x147200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x197800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x276000y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x322000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x331200y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x423200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x441600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x492200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x510600y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x630200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x639400y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x717600y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x96600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x105800y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x138000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x174800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x234600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x271400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x308200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x450800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x487600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x547400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x565800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x616400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x671600y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x713000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x731400y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x814200y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x892400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x910800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x55200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x119600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x179400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x262200y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x340400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x358800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x409400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x496800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x570400y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x759000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x786600y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x828000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y598400 ( - .VPWR ( VDD ) , .VGND ( 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.VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x662400y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x708400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x717600y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x69000y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x115000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x151800y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x239200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x322000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x340400y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x460000y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x657800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x713000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x731400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x782000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x55200y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x133400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x170200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x207000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x225400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x308200y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x354200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x538200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x593400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x602600y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x621000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x639400y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x754400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x791200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x828000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x864800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x901600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x542800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x552000y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x703800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x722200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x110400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x161000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x179400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x202400y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x248400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x299000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x358800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x432400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x450800y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x529000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x565800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x575000y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x621000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x630200y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x749800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x786600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x823400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x860200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x897000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x128800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x414000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x506000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x579600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x639400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x676200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x713000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x722200y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x768200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x777400y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x855600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x105800y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x202400y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x285200y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x331200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x391000y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x437000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x510600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x529000y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x740600y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x818800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x855600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x892400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x910800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x69000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x202400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x239200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x276000y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x354200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x372600y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x460000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x478400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x487600y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x565800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x584200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x593400y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x639400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x731400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x823400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x860200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x69000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x179400y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x308200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x326600y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x427800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x455400y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x492200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x510600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x519800y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x565800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x584200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x708400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x717600y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x763600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x823400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x860200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x897000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x294400y870400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x340400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x358800y870400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x556600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x575000y870400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x621000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x722200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x740600y870400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x818800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x855600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y870400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y870400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x156400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x193200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y897600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x391000y897600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x478400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x496800y897600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x611800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x722200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x731400y897600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x101200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x138000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x230000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x248400y924800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x335800y924800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x556600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x616400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x634800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x644000y924800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y924800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x257600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x276000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x285200y952000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x322000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x680800y952000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y952000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x257600y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x276000y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x579600y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x598000y979200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x846400y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x864800y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y979200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y979200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x257600y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x276000y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x285200y1006400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x575000y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x593400y1006400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x763600y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x800400y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x837200y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x874000y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x910800y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x257600y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x276000y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y1033600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y1060800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y1060800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__39 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__38 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__37 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__36 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__35 ( .A ( mem_out[1] ) , - .X ( net_net_64 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_64 ( .A ( net_net_64 ) , - .X ( net_net_63 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_92 ( .A ( net_net_63 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__34 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__33 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__32 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__31 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__30 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__29 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__28 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__27 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__26 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__25 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__24 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__23 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_18 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__22 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_17 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__21 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__20 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__19 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__18 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__17 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__16 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_51 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__15 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__14 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__13 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__12 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__11 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__10 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0_ ( prog_clk , chany_top_in , top_left_grid_pin_42_ , - top_left_grid_pin_43_ , top_left_grid_pin_44_ , top_left_grid_pin_45_ , - top_left_grid_pin_46_ , top_left_grid_pin_47_ , top_left_grid_pin_48_ , - top_left_grid_pin_49_ , top_right_grid_pin_1_ , chanx_left_in , - left_bottom_grid_pin_1_ , left_bottom_grid_pin_3_ , - left_bottom_grid_pin_5_ , left_bottom_grid_pin_7_ , - left_bottom_grid_pin_9_ , left_bottom_grid_pin_11_ , ccff_head , - chany_top_out , chanx_left_out , ccff_tail , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:19] chany_top_in ; -input [0:0] top_left_grid_pin_42_ ; -input [0:0] top_left_grid_pin_43_ ; -input [0:0] top_left_grid_pin_44_ ; -input [0:0] top_left_grid_pin_45_ ; -input [0:0] top_left_grid_pin_46_ ; -input [0:0] top_left_grid_pin_47_ ; -input [0:0] top_left_grid_pin_48_ ; -input [0:0] top_left_grid_pin_49_ ; -input [0:0] top_right_grid_pin_1_ ; -input [0:19] chanx_left_in ; -input [0:0] left_bottom_grid_pin_1_ ; -input [0:0] left_bottom_grid_pin_3_ ; -input [0:0] left_bottom_grid_pin_5_ ; -input [0:0] left_bottom_grid_pin_7_ ; -input [0:0] left_bottom_grid_pin_9_ ; -input [0:0] left_bottom_grid_pin_11_ ; -input [0:0] ccff_head ; -output [0:19] chany_top_out ; -output [0:19] chanx_left_out ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; - -wire [0:1] mux_left_track_11_undriven_sram_inv ; -wire [0:1] mux_left_track_13_undriven_sram_inv ; -wire [0:1] mux_left_track_15_undriven_sram_inv ; -wire [0:1] mux_left_track_17_undriven_sram_inv ; -wire [0:1] mux_left_track_19_undriven_sram_inv ; -wire [0:2] mux_left_track_1_undriven_sram_inv ; -wire [0:1] mux_left_track_25_undriven_sram_inv ; -wire [0:1] mux_left_track_27_undriven_sram_inv ; -wire [0:1] mux_left_track_29_undriven_sram_inv ; -wire [0:1] mux_left_track_31_undriven_sram_inv ; -wire [0:1] mux_left_track_33_undriven_sram_inv ; -wire [0:1] mux_left_track_35_undriven_sram_inv ; -wire [0:2] mux_left_track_3_undriven_sram_inv ; -wire [0:2] mux_left_track_5_undriven_sram_inv ; -wire [0:2] mux_left_track_7_undriven_sram_inv ; -wire [0:1] mux_left_track_9_undriven_sram_inv ; -wire [0:2] mux_top_track_0_undriven_sram_inv ; -wire [0:1] mux_top_track_10_undriven_sram_inv ; -wire [0:1] mux_top_track_12_undriven_sram_inv ; -wire [0:1] mux_top_track_14_undriven_sram_inv ; -wire [0:1] mux_top_track_16_undriven_sram_inv ; -wire [0:1] mux_top_track_18_undriven_sram_inv ; -wire [0:1] mux_top_track_20_undriven_sram_inv ; -wire [0:1] mux_top_track_22_undriven_sram_inv ; -wire [0:1] mux_top_track_24_undriven_sram_inv ; -wire [0:1] mux_top_track_26_undriven_sram_inv ; -wire [0:2] mux_top_track_2_undriven_sram_inv ; -wire [0:2] mux_top_track_4_undriven_sram_inv ; -wire [0:2] mux_top_track_6_undriven_sram_inv ; -wire [0:1] mux_top_track_8_undriven_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_10_sram ; -wire [0:1] mux_tree_tapbuf_size2_11_sram ; -wire [0:1] mux_tree_tapbuf_size2_12_sram ; -wire [0:1] mux_tree_tapbuf_size2_13_sram ; -wire [0:1] mux_tree_tapbuf_size2_14_sram ; -wire [0:1] mux_tree_tapbuf_size2_15_sram ; -wire [0:1] mux_tree_tapbuf_size2_16_sram ; -wire [0:1] mux_tree_tapbuf_size2_17_sram ; -wire [0:1] mux_tree_tapbuf_size2_18_sram ; -wire [0:1] mux_tree_tapbuf_size2_19_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_5_sram ; -wire [0:1] mux_tree_tapbuf_size2_6_sram ; -wire [0:1] mux_tree_tapbuf_size2_7_sram ; -wire [0:1] mux_tree_tapbuf_size2_8_sram ; -wire [0:1] mux_tree_tapbuf_size2_9_sram ; -wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; -wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size4_0_sram ; -wire [0:2] mux_tree_tapbuf_size4_1_sram ; -wire [0:2] mux_tree_tapbuf_size4_2_sram ; -wire [0:2] mux_tree_tapbuf_size4_3_sram ; -wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size5_0_sram ; -wire [0:2] mux_tree_tapbuf_size5_1_sram ; -wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size6_1_sram ; -wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; -supply1 VDD ; -supply0 VSS ; - -sb_2__0__mux_tree_tapbuf_size6_0 mux_top_track_0 ( - .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , - top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , - top_right_grid_pin_1_[0] , chanx_left_in[0] } ) , - .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_top_track_0_undriven_sram_inv ) , - .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_120 ) ) ; -sb_2__0__mux_tree_tapbuf_size6 mux_top_track_4 ( - .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , - top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , - top_right_grid_pin_1_[0] , chanx_left_in[18] } ) , - .sram ( mux_tree_tapbuf_size6_1_sram ) , - .sram_inv ( mux_top_track_4_undriven_sram_inv ) , - .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_119 ) ) ; -sb_2__0__mux_tree_tapbuf_size6_mem_0 mem_top_track_0 ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__0__mux_tree_tapbuf_size6_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__0__mux_tree_tapbuf_size5_0 mux_top_track_2 ( - .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , - top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , - chanx_left_in[19] } ) , - .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_top_track_2_undriven_sram_inv ) , - .out ( chany_top_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_120 ) ) ; -sb_2__0__mux_tree_tapbuf_size5 mux_top_track_6 ( - .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , - top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , - chanx_left_in[17] } ) , - .sram ( mux_tree_tapbuf_size5_1_sram ) , - .sram_inv ( mux_top_track_6_undriven_sram_inv ) , - .out ( chany_top_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_121 ) ) ; -sb_2__0__mux_tree_tapbuf_size5_mem_0 mem_top_track_2 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__0__mux_tree_tapbuf_size5_mem mem_top_track_6 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__0__mux_tree_tapbuf_size3 mux_top_track_8 ( - .in ( { top_left_grid_pin_42_[0] , top_right_grid_pin_1_[0] , - chanx_left_in[16] } ) , - .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_top_track_8_undriven_sram_inv ) , - .out ( chany_top_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_121 ) ) ; -sb_2__0__mux_tree_tapbuf_size3_0 mux_top_track_24 ( - .in ( { top_left_grid_pin_42_[0] , top_right_grid_pin_1_[0] , - chanx_left_in[8] } ) , - .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_top_track_24_undriven_sram_inv ) , - .out ( chany_top_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_119 ) ) ; -sb_2__0__mux_tree_tapbuf_size3_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__0__mux_tree_tapbuf_size3_mem_0 mem_top_track_24 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__0__mux_tree_tapbuf_size2_12 mux_top_track_10 ( - .in ( { top_left_grid_pin_43_[0] , chanx_left_in[15] } ) , - .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_top_track_10_undriven_sram_inv ) , - .out ( chany_top_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_119 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_13 mux_top_track_12 ( - .in ( { top_left_grid_pin_44_[0] , chanx_left_in[14] } ) , - .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_top_track_12_undriven_sram_inv ) , - .out ( chany_top_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_120 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_14 mux_top_track_14 ( - .in ( { top_left_grid_pin_45_[0] , chanx_left_in[13] } ) , - .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_top_track_14_undriven_sram_inv ) , - .out ( chany_top_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_120 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_15 mux_top_track_16 ( - .in ( { top_left_grid_pin_46_[0] , chanx_left_in[12] } ) , - .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_top_track_16_undriven_sram_inv ) , - .out ( chany_top_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_120 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_16 mux_top_track_18 ( - .in ( { top_left_grid_pin_47_[0] , chanx_left_in[11] } ) , - .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_top_track_18_undriven_sram_inv ) , - .out ( chany_top_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_121 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_17 mux_top_track_20 ( - .in ( { top_left_grid_pin_48_[0] , chanx_left_in[10] } ) , - .sram ( mux_tree_tapbuf_size2_5_sram ) , - .sram_inv ( mux_top_track_20_undriven_sram_inv ) , - .out ( chany_top_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_119 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_18 mux_top_track_22 ( - .in ( { top_left_grid_pin_49_[0] , chanx_left_in[9] } ) , - .sram ( mux_tree_tapbuf_size2_6_sram ) , - .sram_inv ( mux_top_track_22_undriven_sram_inv ) , - .out ( chany_top_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_119 ) ) ; -sb_2__0__mux_tree_tapbuf_size2 mux_top_track_26 ( - .in ( { top_left_grid_pin_43_[0] , chanx_left_in[7] } ) , - .sram ( mux_tree_tapbuf_size2_7_sram ) , - .sram_inv ( mux_top_track_26_undriven_sram_inv ) , - .out ( chany_top_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_120 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_11 mux_left_track_9 ( - .in ( { chany_top_in[16] , left_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size2_8_sram ) , - .sram_inv ( mux_left_track_9_undriven_sram_inv ) , - .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_122 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_0 mux_left_track_11 ( - .in ( { chany_top_in[15] , left_bottom_grid_pin_3_[0] } ) , - .sram ( mux_tree_tapbuf_size2_9_sram ) , - .sram_inv ( mux_left_track_11_undriven_sram_inv ) , - .out ( chanx_left_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_120 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_1 mux_left_track_13 ( - .in ( { chany_top_in[14] , left_bottom_grid_pin_5_[0] } ) , - .sram ( mux_tree_tapbuf_size2_10_sram ) , - .sram_inv ( mux_left_track_13_undriven_sram_inv ) , - .out ( chanx_left_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_120 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_2 mux_left_track_15 ( - .in ( { chany_top_in[13] , left_bottom_grid_pin_7_[0] } ) , - .sram ( mux_tree_tapbuf_size2_11_sram ) , - .sram_inv ( mux_left_track_15_undriven_sram_inv ) , - .out ( chanx_left_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_119 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_3 mux_left_track_17 ( - .in ( { chany_top_in[12] , left_bottom_grid_pin_9_[0] } ) , - .sram ( mux_tree_tapbuf_size2_12_sram ) , - .sram_inv ( mux_left_track_17_undriven_sram_inv ) , - .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_121 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_4 mux_left_track_19 ( - .in ( { chany_top_in[11] , left_bottom_grid_pin_11_[0] } ) , - .sram ( mux_tree_tapbuf_size2_13_sram ) , - .sram_inv ( mux_left_track_19_undriven_sram_inv ) , - .out ( chanx_left_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_119 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_5 mux_left_track_25 ( - .in ( { chany_top_in[8] , left_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size2_14_sram ) , - .sram_inv ( mux_left_track_25_undriven_sram_inv ) , - .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_120 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_6 mux_left_track_27 ( - .in ( { chany_top_in[7] , left_bottom_grid_pin_3_[0] } ) , - .sram ( mux_tree_tapbuf_size2_15_sram ) , - .sram_inv ( mux_left_track_27_undriven_sram_inv ) , - .out ( chanx_left_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_122 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_7 mux_left_track_29 ( - .in ( { chany_top_in[6] , left_bottom_grid_pin_5_[0] } ) , - .sram ( mux_tree_tapbuf_size2_16_sram ) , - .sram_inv ( mux_left_track_29_undriven_sram_inv ) , - .out ( { ropt_net_126 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_119 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_8 mux_left_track_31 ( - .in ( { chany_top_in[5] , left_bottom_grid_pin_7_[0] } ) , - .sram ( mux_tree_tapbuf_size2_17_sram ) , - .sram_inv ( mux_left_track_31_undriven_sram_inv ) , - .out ( chanx_left_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_122 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_9 mux_left_track_33 ( - .in ( { chany_top_in[4] , left_bottom_grid_pin_9_[0] } ) , - .sram ( mux_tree_tapbuf_size2_18_sram ) , - .sram_inv ( mux_left_track_33_undriven_sram_inv ) , - .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_119 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_10 mux_left_track_35 ( - .in ( { chany_top_in[3] , left_bottom_grid_pin_11_[0] } ) , - .sram ( mux_tree_tapbuf_size2_19_sram ) , - .sram_inv ( mux_left_track_35_undriven_sram_inv ) , - .out ( chanx_left_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_121 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_12 mem_top_track_10 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_13 mem_top_track_12 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_14 mem_top_track_14 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_15 mem_top_track_16 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_16 mem_top_track_18 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_17 mem_top_track_20 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_18 mem_top_track_22 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem mem_top_track_26 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_11 mem_left_track_9 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_8_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_0 mem_left_track_11 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_9_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_1 mem_left_track_13 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_10_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_2 mem_left_track_15 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_11_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_3 mem_left_track_17 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_12_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_4 mem_left_track_19 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_13_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_5 mem_left_track_25 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_14_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_6 mem_left_track_27 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_15_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_7 mem_left_track_29 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_16_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_8 mem_left_track_31 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_17_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_9 mem_left_track_33 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_18_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_10 mem_left_track_35 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , - .ccff_tail ( { ropt_net_130 } ) , - .mem_out ( mux_tree_tapbuf_size2_19_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__0__mux_tree_tapbuf_size4_0 mux_left_track_1 ( - .in ( { chany_top_in[0] , left_bottom_grid_pin_1_[0] , - left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] } ) , - .sram ( mux_tree_tapbuf_size4_0_sram ) , - .sram_inv ( mux_left_track_1_undriven_sram_inv ) , - .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_122 ) ) ; -sb_2__0__mux_tree_tapbuf_size4_1 mux_left_track_3 ( - .in ( { chany_top_in[19] , left_bottom_grid_pin_3_[0] , - left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] } ) , - .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_left_track_3_undriven_sram_inv ) , - .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_122 ) ) ; -sb_2__0__mux_tree_tapbuf_size4_2 mux_left_track_5 ( - .in ( { chany_top_in[18] , left_bottom_grid_pin_1_[0] , - left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] } ) , - .sram ( mux_tree_tapbuf_size4_2_sram ) , - .sram_inv ( mux_left_track_5_undriven_sram_inv ) , - .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_122 ) ) ; -sb_2__0__mux_tree_tapbuf_size4 mux_left_track_7 ( - .in ( { chany_top_in[17] , left_bottom_grid_pin_3_[0] , - left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] } ) , - .sram ( mux_tree_tapbuf_size4_3_sram ) , - .sram_inv ( mux_left_track_7_undriven_sram_inv ) , - .out ( chanx_left_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_122 ) ) ; -sb_2__0__mux_tree_tapbuf_size4_mem_0 mem_left_track_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__0__mux_tree_tapbuf_size4_mem_1 mem_left_track_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__0__mux_tree_tapbuf_size4_mem_2 mem_left_track_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__0__mux_tree_tapbuf_size4_mem mem_left_track_7 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1461 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1462 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1463 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1464 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1465 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1466 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1467 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1468 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1469 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1470 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1471 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1472 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1473 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1474 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1475 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1476 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1477 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1478 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1479 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1480 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1481 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1482 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1483 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1484 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1485 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1486 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1487 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1488 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1489 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1490 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1491 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1492 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1493 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1494 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1495 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1496 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1497 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1498 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_139 ) , - .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_708 ( .A ( ropt_net_126 ) , - .X ( ropt_net_139 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_721 ( .A ( ropt_net_140 ) , - .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_141 ) , - .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__4 ( .A ( chanx_left_in[1] ) , - .X ( ropt_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_119 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_120 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__8 ( .A ( chanx_left_in[5] ) , - .X ( ropt_net_134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__9 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_137 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_723 ( .A ( ropt_net_142 ) , - .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( ropt_net_143 ) , - .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( ropt_net_144 ) , - .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( ropt_net_145 ) , - .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_78 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( ropt_net_146 ) , - .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_728 ( .A ( ropt_net_147 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_86 ( .A ( chanx_left_in[2] ) , - .X ( ropt_net_136 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_87 ( .A ( chanx_left_in[3] ) , - .X ( ropt_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_88 ( .A ( chanx_left_in[4] ) , - .X ( ropt_net_135 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_709 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_710 ( .A ( chany_top_in[9] ) , - .X ( ropt_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_711 ( .A ( chany_top_in[1] ) , - .X ( ropt_net_150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_712 ( .A ( ropt_net_130 ) , - .X ( ropt_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_713 ( .A ( ropt_net_131 ) , - .X ( ropt_net_141 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_714 ( .A ( ropt_net_132 ) , - .X ( ropt_net_142 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_715 ( .A ( ropt_net_133 ) , - .X ( ropt_net_144 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_716 ( .A ( ropt_net_134 ) , - .X ( ropt_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_717 ( .A ( ropt_net_135 ) , - .X ( ropt_net_145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_718 ( .A ( ropt_net_136 ) , - .X ( ropt_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_137 ) , - .X ( ropt_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_148 ) , - .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_730 ( .A ( ropt_net_149 ) , - .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_150 ) , - .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y0 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y0 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 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VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x257600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x276000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x285200y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x303600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x340400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y136000 ( - .VGND ( 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( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x220800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x239200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x285200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y163200 ( 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\xofiller!sky130_fd_sc_hd__fill_8!x809600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x846400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x864800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x358800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x312800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x349600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x386400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x423200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x460000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x496800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x754400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x791200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x828000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x864800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x115000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x266800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x303600y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x427800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x188600y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x473800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x510600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x547400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x584200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x657800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x694600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x731400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x768200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x805000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x841800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x69000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x105800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x142600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x179400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x216200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x253000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x289800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x326600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x363400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x427800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x446200y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x708400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x745200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x782000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x818800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x855600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x892400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x910800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x36800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x46000y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x207000y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x349600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x473800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x510600y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x846400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x864800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x73600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x82800y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x165600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x202400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x239200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x248400y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x409400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x492200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x547400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x639400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x676200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x713000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x749800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x786600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x823400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x860200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x897000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x101200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x138000y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x184000y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x262200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x299000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x317400y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x391000y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x437000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x473800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x524400y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x754400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x791200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x828000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x864800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x36800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x46000y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x124200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x161000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x207000y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x253000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x271400y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x349600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x409400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x418600y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x496800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x542800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x561200y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x754400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x791200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x828000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x864800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x901600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x110400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x202400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x239200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x276000y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x395600y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x496800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x533600y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x579600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x588800y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x846400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x864800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x55200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x138000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x174800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x211600y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x289800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x299000y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x400200y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x515200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x598000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x690000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x763600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x800400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x837200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x874000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x910800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x92000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x220800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x303600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x340400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x377200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x414000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x524400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x575000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x584200y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x616400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x703800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x722200y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x768200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x805000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x841800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x147200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x165600y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x253000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x289800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x432400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x450800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x460000y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x575000y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x644000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x662400y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x814200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x851000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x156400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x193200y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x322000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x358800y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x547400y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x593400y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x676200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x694600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x786600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x823400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x860200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x36800y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x78200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x87400y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x207000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x243800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x358800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x598000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x616400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x625600y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x703800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x722200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x731400y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x110400y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x151800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x211600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x538200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x556600y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x754400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x846400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x864800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x105800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x142600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x179400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x197800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x207000y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x363400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x524400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x542800y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x625600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x634800y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x717600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x768200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x805000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x841800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x878600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x69000y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x234600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x271400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x322000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x395600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x625600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x634800y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x653200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x837200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x147200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x165600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x216200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x409400y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x487600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x570400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x588800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x598000y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x676200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x713000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x749800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x768200y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x73600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x124200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x161000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x197800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x248400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x266800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x289800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x299000y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x345000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x381800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x432400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x469200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x506000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x616400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x625600y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x671600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x690000y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x768200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x805000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x841800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x110400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x161000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x197800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x216200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x299000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x335800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x391000y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x469200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x519800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x538200y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x584200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x657800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x694600y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x818800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x855600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x892400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x910800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x115000y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x193200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x230000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x248400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x257600y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x409400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x593400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x611800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x703800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x754400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x860200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x105800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x142600y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x188600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x207000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x216200y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x303600y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x409400y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x556600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x565800y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x736000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x128800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x174800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x184000y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x266800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x317400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x763600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x823400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x860200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x294400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x354200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x437000y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x625600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x644000y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x690000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x736000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x818800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x855600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x892400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x910800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x257600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x276000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x437000y870400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y870400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x538200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x547400y870400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x625600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x791200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x828000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x864800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y870400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y870400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x257600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x276000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x312800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x322000y897600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x455400y897600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x506000y897600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x611800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x630200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x639400y897600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x800400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x864800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x901600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x386400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x598000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x607200y924800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x639400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x814200y924800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x864800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y924800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y924800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y952000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y952000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_28__62 ( .A ( mem_out[2] ) , - .X ( net_net_120 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_120 ( .A ( net_net_120 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__61 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__60 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size3_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__59 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__58 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__57 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__56 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__55 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size3_4 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__54 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__53 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__52 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_126 ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__51 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__50 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__49 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__48 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__47 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__46 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__45 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__44 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__43 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_125 ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_6 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__42 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__41 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size14_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__40 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size14_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__39 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size14_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:13] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size14 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:13] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size9_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__38 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size9_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__37 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size9_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__36 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size9_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:8] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size9_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:8] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:8] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__35 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2_ ( prog_clk , chanx_right_in , right_top_grid_pin_1_ , - right_bottom_grid_pin_34_ , right_bottom_grid_pin_35_ , - right_bottom_grid_pin_36_ , right_bottom_grid_pin_37_ , - right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ , - right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ , chany_bottom_in , - bottom_left_grid_pin_42_ , bottom_left_grid_pin_43_ , - bottom_left_grid_pin_44_ , bottom_left_grid_pin_45_ , - bottom_left_grid_pin_46_ , bottom_left_grid_pin_47_ , - bottom_left_grid_pin_48_ , bottom_left_grid_pin_49_ , chanx_left_in , - left_top_grid_pin_1_ , left_bottom_grid_pin_34_ , - left_bottom_grid_pin_35_ , left_bottom_grid_pin_36_ , - left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , - left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , - left_bottom_grid_pin_41_ , ccff_head , chanx_right_out , - chany_bottom_out , chanx_left_out , ccff_tail , SC_IN_TOP , SC_IN_BOT , - SC_OUT_TOP , SC_OUT_BOT , VDD , VSS , Test_en__FEEDTHRU_0 , - Test_en__FEEDTHRU_1 , Test_en__FEEDTHRU_2 , clk__FEEDTHRU_0 , - clk__FEEDTHRU_1 , clk__FEEDTHRU_2 ) ; -input [0:0] prog_clk ; -input [0:19] chanx_right_in ; -input [0:0] right_top_grid_pin_1_ ; -input [0:0] right_bottom_grid_pin_34_ ; -input [0:0] right_bottom_grid_pin_35_ ; -input [0:0] right_bottom_grid_pin_36_ ; -input [0:0] right_bottom_grid_pin_37_ ; -input [0:0] right_bottom_grid_pin_38_ ; -input [0:0] right_bottom_grid_pin_39_ ; -input [0:0] right_bottom_grid_pin_40_ ; -input [0:0] right_bottom_grid_pin_41_ ; -input [0:19] chany_bottom_in ; -input [0:0] bottom_left_grid_pin_42_ ; -input [0:0] bottom_left_grid_pin_43_ ; -input [0:0] bottom_left_grid_pin_44_ ; -input [0:0] bottom_left_grid_pin_45_ ; -input [0:0] bottom_left_grid_pin_46_ ; -input [0:0] bottom_left_grid_pin_47_ ; -input [0:0] bottom_left_grid_pin_48_ ; -input [0:0] bottom_left_grid_pin_49_ ; -input [0:19] chanx_left_in ; -input [0:0] left_top_grid_pin_1_ ; -input [0:0] left_bottom_grid_pin_34_ ; -input [0:0] left_bottom_grid_pin_35_ ; -input [0:0] left_bottom_grid_pin_36_ ; -input [0:0] left_bottom_grid_pin_37_ ; -input [0:0] left_bottom_grid_pin_38_ ; -input [0:0] left_bottom_grid_pin_39_ ; -input [0:0] left_bottom_grid_pin_40_ ; -input [0:0] left_bottom_grid_pin_41_ ; -input [0:0] ccff_head ; -output [0:19] chanx_right_out ; -output [0:19] chany_bottom_out ; -output [0:19] chanx_left_out ; -output [0:0] ccff_tail ; -input SC_IN_TOP ; -input SC_IN_BOT ; -output SC_OUT_TOP ; -output SC_OUT_BOT ; -input VDD ; -input VSS ; -input [0:0] Test_en__FEEDTHRU_0 ; -output [0:0] Test_en__FEEDTHRU_1 ; -output [0:0] Test_en__FEEDTHRU_2 ; -input [0:0] clk__FEEDTHRU_0 ; -output [0:0] clk__FEEDTHRU_1 ; -output [0:0] clk__FEEDTHRU_2 ; - -wire [0:2] mux_bottom_track_11_undriven_sram_inv ; -wire [0:1] mux_bottom_track_13_undriven_sram_inv ; -wire [0:1] mux_bottom_track_15_undriven_sram_inv ; -wire [0:1] mux_bottom_track_17_undriven_sram_inv ; -wire [0:1] mux_bottom_track_19_undriven_sram_inv ; -wire [0:2] mux_bottom_track_1_undriven_sram_inv ; -wire [0:1] mux_bottom_track_21_undriven_sram_inv ; -wire [0:1] mux_bottom_track_23_undriven_sram_inv ; -wire [0:2] mux_bottom_track_25_undriven_sram_inv ; -wire [0:1] mux_bottom_track_27_undriven_sram_inv ; -wire [0:2] mux_bottom_track_3_undriven_sram_inv ; -wire [0:2] mux_bottom_track_5_undriven_sram_inv ; -wire [0:2] mux_bottom_track_7_undriven_sram_inv ; -wire [0:2] mux_bottom_track_9_undriven_sram_inv ; -wire [0:2] mux_left_track_17_undriven_sram_inv ; -wire [0:3] mux_left_track_1_undriven_sram_inv ; -wire [0:2] mux_left_track_25_undriven_sram_inv ; -wire [0:2] mux_left_track_33_undriven_sram_inv ; -wire [0:3] mux_left_track_3_undriven_sram_inv ; -wire [0:3] mux_left_track_5_undriven_sram_inv ; -wire [0:3] mux_left_track_9_undriven_sram_inv ; -wire [0:3] mux_right_track_0_undriven_sram_inv ; -wire [0:2] mux_right_track_16_undriven_sram_inv ; -wire [0:2] mux_right_track_24_undriven_sram_inv ; -wire [0:3] mux_right_track_2_undriven_sram_inv ; -wire [0:2] mux_right_track_32_undriven_sram_inv ; -wire [0:3] mux_right_track_4_undriven_sram_inv ; -wire [0:3] mux_right_track_8_undriven_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size14_0_sram ; -wire [0:3] mux_tree_tapbuf_size14_1_sram ; -wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail ; -wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; -wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:1] mux_tree_tapbuf_size3_2_sram ; -wire [0:1] mux_tree_tapbuf_size3_3_sram ; -wire [0:1] mux_tree_tapbuf_size3_4_sram ; -wire [0:1] mux_tree_tapbuf_size3_5_sram ; -wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size4_0_sram ; -wire [0:2] mux_tree_tapbuf_size4_1_sram ; -wire [0:2] mux_tree_tapbuf_size4_2_sram ; -wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size5_0_sram ; -wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size7_0_sram ; -wire [0:2] mux_tree_tapbuf_size7_1_sram ; -wire [0:2] mux_tree_tapbuf_size7_2_sram ; -wire [0:2] mux_tree_tapbuf_size7_3_sram ; -wire [0:2] mux_tree_tapbuf_size7_4_sram ; -wire [0:2] mux_tree_tapbuf_size7_5_sram ; -wire [0:2] mux_tree_tapbuf_size7_6_sram ; -wire [0:2] mux_tree_tapbuf_size7_7_sram ; -wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_7_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size9_0_sram ; -wire [0:3] mux_tree_tapbuf_size9_1_sram ; -wire [0:3] mux_tree_tapbuf_size9_2_sram ; -wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size9_mem_2_ccff_tail ; -supply1 VDD ; -supply0 VSS ; - -assign SC_IN_TOP = SC_IN_BOT ; -assign clk__FEEDTHRU_2[0] = clk__FEEDTHRU_0[0] ; -assign clk__FEEDTHRU_1[0] = clk__FEEDTHRU_2[0] ; - -sb_1__2__mux_tree_tapbuf_size10 mux_right_track_0 ( - .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] , - right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , - right_bottom_grid_pin_41_[0] , chany_bottom_in[5] , - chany_bottom_in[12] , chany_bottom_in[19] , chanx_left_in[2] , - chanx_left_in[12] } ) , - .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_right_track_0_undriven_sram_inv ) , - .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_157 ) ) ; -sb_1__2__mux_tree_tapbuf_size10_mem mem_right_track_0 ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__2__mux_tree_tapbuf_size9 mux_right_track_2 ( - .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , - right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , - chany_bottom_in[4] , chany_bottom_in[11] , chany_bottom_in[18] , - chanx_left_in[4] , chanx_left_in[13] } ) , - .sram ( mux_tree_tapbuf_size9_0_sram ) , - .sram_inv ( mux_right_track_2_undriven_sram_inv ) , - .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_157 ) ) ; -sb_1__2__mux_tree_tapbuf_size9_0 mux_left_track_1 ( - .in ( { chanx_right_in[2] , chanx_right_in[12] , chany_bottom_in[6] , - chany_bottom_in[13] , left_top_grid_pin_1_[0] , - left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , - left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , - .sram ( mux_tree_tapbuf_size9_1_sram ) , - .sram_inv ( mux_left_track_1_undriven_sram_inv ) , - .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_155 ) ) ; -sb_1__2__mux_tree_tapbuf_size9_1 mux_left_track_3 ( - .in ( { chanx_right_in[4] , chanx_right_in[13] , chany_bottom_in[0] , - chany_bottom_in[7] , chany_bottom_in[14] , - left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , - left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , - .sram ( mux_tree_tapbuf_size9_2_sram ) , - .sram_inv ( mux_left_track_3_undriven_sram_inv ) , - .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_154 ) ) ; -sb_1__2__mux_tree_tapbuf_size9_mem mem_right_track_2 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size9_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__2__mux_tree_tapbuf_size9_mem_0 mem_left_track_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size9_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__2__mux_tree_tapbuf_size9_mem_1 mem_left_track_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size9_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__2__mux_tree_tapbuf_size14 mux_right_track_4 ( - .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_34_[0] , - right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_36_[0] , - right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_38_[0] , - right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_40_[0] , - right_bottom_grid_pin_41_[0] , chany_bottom_in[3] , - chany_bottom_in[10] , chany_bottom_in[17] , chanx_left_in[5] , - chanx_left_in[14] } ) , - .sram ( mux_tree_tapbuf_size14_0_sram ) , - .sram_inv ( mux_right_track_4_undriven_sram_inv ) , - .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_157 ) ) ; -sb_1__2__mux_tree_tapbuf_size14_0 mux_left_track_5 ( - .in ( { chanx_right_in[5] , chanx_right_in[14] , chany_bottom_in[1] , - chany_bottom_in[8] , chany_bottom_in[15] , left_top_grid_pin_1_[0] , - left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_35_[0] , - left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_37_[0] , - left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_39_[0] , - left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_41_[0] } ) , - .sram ( mux_tree_tapbuf_size14_1_sram ) , - .sram_inv ( mux_left_track_5_undriven_sram_inv ) , - .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_154 ) ) ; -sb_1__2__mux_tree_tapbuf_size14_mem mem_right_track_4 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size14_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__2__mux_tree_tapbuf_size14_mem_0 mem_left_track_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size14_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__2__mux_tree_tapbuf_size8 mux_right_track_8 ( - .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_37_[0] , - right_bottom_grid_pin_41_[0] , chany_bottom_in[2] , - chany_bottom_in[9] , chany_bottom_in[16] , chanx_left_in[6] , - chanx_left_in[16] } ) , - .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_right_track_8_undriven_sram_inv ) , - .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_153 ) ) ; -sb_1__2__mux_tree_tapbuf_size8_0 mux_left_track_9 ( - .in ( { chanx_right_in[6] , chanx_right_in[16] , chany_bottom_in[2] , - chany_bottom_in[9] , chany_bottom_in[16] , left_top_grid_pin_1_[0] , - left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_41_[0] } ) , - .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_left_track_9_undriven_sram_inv ) , - .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_155 ) ) ; -sb_1__2__mux_tree_tapbuf_size8_mem mem_right_track_8 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__2__mux_tree_tapbuf_size8_mem_0 mem_left_track_9 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__2__mux_tree_tapbuf_size7_6 mux_right_track_16 ( - .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_38_[0] , - chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[15] , - chanx_left_in[8] , chanx_left_in[17] } ) , - .sram ( mux_tree_tapbuf_size7_0_sram ) , - .sram_inv ( mux_right_track_16_undriven_sram_inv ) , - .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_153 ) ) ; -sb_1__2__mux_tree_tapbuf_size7 mux_right_track_24 ( - .in ( { right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_39_[0] , - chany_bottom_in[0] , chany_bottom_in[7] , chany_bottom_in[14] , - chanx_left_in[9] , chanx_left_in[18] } ) , - .sram ( mux_tree_tapbuf_size7_1_sram ) , - .sram_inv ( mux_right_track_24_undriven_sram_inv ) , - .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_153 ) ) ; -sb_1__2__mux_tree_tapbuf_size7_0 mux_bottom_track_1 ( - .in ( { chanx_right_in[2] , bottom_left_grid_pin_42_[0] , - bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , - bottom_left_grid_pin_48_[0] , chanx_left_in[1] , chanx_left_in[2] } ) , - .sram ( mux_tree_tapbuf_size7_2_sram ) , - .sram_inv ( mux_bottom_track_1_undriven_sram_inv ) , - .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_155 ) ) ; -sb_1__2__mux_tree_tapbuf_size7_1 mux_bottom_track_3 ( - .in ( { chanx_right_in[4] , bottom_left_grid_pin_43_[0] , - bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , - bottom_left_grid_pin_49_[0] , chanx_left_in[3] , chanx_left_in[4] } ) , - .sram ( mux_tree_tapbuf_size7_3_sram ) , - .sram_inv ( mux_bottom_track_3_undriven_sram_inv ) , - .out ( chany_bottom_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_156 ) ) ; -sb_1__2__mux_tree_tapbuf_size7_2 mux_bottom_track_5 ( - .in ( { chanx_right_in[5] , bottom_left_grid_pin_42_[0] , - bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , - bottom_left_grid_pin_48_[0] , chanx_left_in[5] , chanx_left_in[7] } ) , - .sram ( mux_tree_tapbuf_size7_4_sram ) , - .sram_inv ( mux_bottom_track_5_undriven_sram_inv ) , - .out ( { ropt_net_169 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_154 ) ) ; -sb_1__2__mux_tree_tapbuf_size7_3 mux_bottom_track_7 ( - .in ( { chanx_right_in[6] , bottom_left_grid_pin_43_[0] , - bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , - bottom_left_grid_pin_49_[0] , chanx_left_in[6] , chanx_left_in[11] } ) , - .sram ( mux_tree_tapbuf_size7_5_sram ) , - .sram_inv ( mux_bottom_track_7_undriven_sram_inv ) , - .out ( chany_bottom_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_154 ) ) ; -sb_1__2__mux_tree_tapbuf_size7_4 mux_left_track_17 ( - .in ( { chanx_right_in[8] , chanx_right_in[17] , chany_bottom_in[3] , - chany_bottom_in[10] , chany_bottom_in[17] , - left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_38_[0] } ) , - .sram ( mux_tree_tapbuf_size7_6_sram ) , - .sram_inv ( mux_left_track_17_undriven_sram_inv ) , - .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_155 ) ) ; -sb_1__2__mux_tree_tapbuf_size7_5 mux_left_track_25 ( - .in ( { chanx_right_in[9] , chanx_right_in[18] , chany_bottom_in[4] , - chany_bottom_in[11] , chany_bottom_in[18] , - left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_39_[0] } ) , - .sram ( mux_tree_tapbuf_size7_7_sram ) , - .sram_inv ( mux_left_track_25_undriven_sram_inv ) , - .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_156 ) ) ; -sb_1__2__mux_tree_tapbuf_size7_mem_6 mem_right_track_16 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__2__mux_tree_tapbuf_size7_mem mem_right_track_24 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__2__mux_tree_tapbuf_size7_mem_0 mem_bottom_track_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__2__mux_tree_tapbuf_size7_mem_1 mem_bottom_track_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__2__mux_tree_tapbuf_size7_mem_2 mem_bottom_track_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__2__mux_tree_tapbuf_size7_mem_3 mem_bottom_track_7 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__2__mux_tree_tapbuf_size7_mem_4 mem_left_track_17 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__2__mux_tree_tapbuf_size7_mem_5 mem_left_track_25 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__2__mux_tree_tapbuf_size5 mux_right_track_32 ( - .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_40_[0] , - chany_bottom_in[6] , chany_bottom_in[13] , chanx_left_in[10] } ) , - .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_right_track_32_undriven_sram_inv ) , - .out ( chanx_right_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_153 ) ) ; -sb_1__2__mux_tree_tapbuf_size5_mem mem_right_track_32 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__2__mux_tree_tapbuf_size4 mux_bottom_track_9 ( - .in ( { chanx_right_in[8] , bottom_left_grid_pin_42_[0] , - chanx_left_in[8] , chanx_left_in[15] } ) , - .sram ( mux_tree_tapbuf_size4_0_sram ) , - .sram_inv ( mux_bottom_track_9_undriven_sram_inv ) , - .out ( { ropt_net_168 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_154 ) ) ; -sb_1__2__mux_tree_tapbuf_size4_0 mux_bottom_track_11 ( - .in ( { chanx_right_in[9] , bottom_left_grid_pin_43_[0] , - chanx_left_in[9] , chanx_left_in[19] } ) , - .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_bottom_track_11_undriven_sram_inv ) , - .out ( chany_bottom_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_154 ) ) ; -sb_1__2__mux_tree_tapbuf_size4_1 mux_bottom_track_25 ( - .in ( { chanx_right_in[18] , chanx_right_in[19] , - bottom_left_grid_pin_42_[0] , chanx_left_in[18] } ) , - .sram ( mux_tree_tapbuf_size4_2_sram ) , - .sram_inv ( mux_bottom_track_25_undriven_sram_inv ) , - .out ( { ropt_net_162 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_153 ) ) ; -sb_1__2__mux_tree_tapbuf_size4_mem mem_bottom_track_9 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__2__mux_tree_tapbuf_size4_mem_0 mem_bottom_track_11 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__2__mux_tree_tapbuf_size4_mem_1 mem_bottom_track_25 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__2__mux_tree_tapbuf_size3_0 mux_bottom_track_13 ( - .in ( { chanx_right_in[10] , bottom_left_grid_pin_44_[0] , - chanx_left_in[10] } ) , - .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_bottom_track_13_undriven_sram_inv ) , - .out ( chany_bottom_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_156 ) ) ; -sb_1__2__mux_tree_tapbuf_size3_1 mux_bottom_track_15 ( - .in ( { chanx_right_in[12] , bottom_left_grid_pin_45_[0] , - chanx_left_in[12] } ) , - .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_bottom_track_15_undriven_sram_inv ) , - .out ( chany_bottom_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_156 ) ) ; -sb_1__2__mux_tree_tapbuf_size3_2 mux_bottom_track_17 ( - .in ( { chanx_right_in[13] , bottom_left_grid_pin_46_[0] , - chanx_left_in[13] } ) , - .sram ( mux_tree_tapbuf_size3_2_sram ) , - .sram_inv ( mux_bottom_track_17_undriven_sram_inv ) , - .out ( chany_bottom_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_156 ) ) ; -sb_1__2__mux_tree_tapbuf_size3_3 mux_bottom_track_19 ( - .in ( { chanx_right_in[14] , bottom_left_grid_pin_47_[0] , - chanx_left_in[14] } ) , - .sram ( mux_tree_tapbuf_size3_3_sram ) , - .sram_inv ( mux_bottom_track_19_undriven_sram_inv ) , - .out ( chany_bottom_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_156 ) ) ; -sb_1__2__mux_tree_tapbuf_size3_4 mux_bottom_track_21 ( - .in ( { chanx_right_in[16] , bottom_left_grid_pin_48_[0] , - chanx_left_in[16] } ) , - .sram ( mux_tree_tapbuf_size3_4_sram ) , - .sram_inv ( mux_bottom_track_21_undriven_sram_inv ) , - .out ( chany_bottom_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_156 ) ) ; -sb_1__2__mux_tree_tapbuf_size3 mux_bottom_track_23 ( - .in ( { chanx_right_in[17] , bottom_left_grid_pin_49_[0] , - chanx_left_in[17] } ) , - .sram ( mux_tree_tapbuf_size3_5_sram ) , - .sram_inv ( mux_bottom_track_23_undriven_sram_inv ) , - .out ( chany_bottom_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_153 ) ) ; -sb_1__2__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_13 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__2__mux_tree_tapbuf_size3_mem_1 mem_bottom_track_15 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__2__mux_tree_tapbuf_size3_mem_2 mem_bottom_track_17 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__2__mux_tree_tapbuf_size3_mem_3 mem_bottom_track_19 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__2__mux_tree_tapbuf_size3_mem_4 mem_bottom_track_21 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__2__mux_tree_tapbuf_size3_mem mem_bottom_track_23 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__2__mux_tree_tapbuf_size2 mux_bottom_track_27 ( - .in ( { chanx_right_in[15] , bottom_left_grid_pin_43_[0] } ) , - .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_bottom_track_27_undriven_sram_inv ) , - .out ( chany_bottom_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_153 ) ) ; -sb_1__2__mux_tree_tapbuf_size2_mem mem_bottom_track_27 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__2__mux_tree_tapbuf_size6 mux_left_track_33 ( - .in ( { chanx_right_in[10] , chany_bottom_in[5] , chany_bottom_in[12] , - chany_bottom_in[19] , left_bottom_grid_pin_36_[0] , - left_bottom_grid_pin_40_[0] } ) , - .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_left_track_33_undriven_sram_inv ) , - .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_154 ) ) ; -sb_1__2__mux_tree_tapbuf_size6_mem mem_left_track_33 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , - .ccff_tail ( { ropt_net_164 } ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1422 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1423 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1424 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1425 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1426 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1427 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1428 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1429 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1430 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1431 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1432 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1433 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1434 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1435 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1436 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1437 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1438 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1439 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1440 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1441 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1442 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1443 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1444 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1445 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1446 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1447 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1448 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1449 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1450 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1451 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1452 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1453 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1454 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1455 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1456 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1457 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1458 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1459 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_811 ( .A ( ropt_net_193 ) , - .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_150 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_152 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__4 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_179 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chanx_right_in[5] ) , - .X ( ropt_net_188 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__6 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_177 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_154 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_156 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_191 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_156 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , - .HI ( optlc_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( chanx_right_in[2] ) , - .X ( ropt_net_194 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_159 ) , - .X ( ropt_net_205 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( .A ( ropt_net_160 ) , - .X ( ropt_net_209 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chanx_right_in[14] ) , - .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_194 ) , - .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__16 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_184 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( chanx_right_in[18] ) , - .X ( ropt_net_211 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_162 ) , - .X ( ropt_net_204 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_163 ) , - .X ( ropt_net_197 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__20 ( .A ( chanx_left_in[4] ) , - .X ( ropt_net_189 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( ropt_net_195 ) , - .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( ropt_net_164 ) , - .X ( ropt_net_208 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_165 ) , - .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_25__24 ( .A ( chanx_left_in[9] ) , - .X ( ropt_net_182 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_26__25 ( .A ( chanx_left_in[10] ) , - .X ( ropt_net_186 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( - .A ( Test_en__FEEDTHRU_0[0] ) , .X ( ropt_net_215 ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_782 ( - .A ( Test_en__FEEDTHRU_0[0] ) , .X ( ropt_net_216 ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_783 ( .A ( ropt_net_168 ) , - .X ( ropt_net_210 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_784 ( .A ( ropt_net_169 ) , - .X ( ropt_net_214 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_31__30 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_180 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_785 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_213 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_160 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_196 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_814 ( .A ( ropt_net_196 ) , - .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_816 ( .A ( ropt_net_197 ) , - .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_787 ( .A ( chanx_left_in[5] ) , - .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_173 ) , - .X ( ropt_net_199 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_75 ( .A ( chanx_right_in[3] ) , - .X ( BUF_net_75 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( chanx_left_in[18] ) , - .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_818 ( .A ( ropt_net_198 ) , - .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_78 ( .A ( chanx_right_in[11] ) , - .X ( BUF_net_78 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_819 ( .A ( ropt_net_199 ) , - .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( chanx_left_in[6] ) , - .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_822 ( .A ( ropt_net_200 ) , - .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_212 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_823 ( .A ( ropt_net_201 ) , - .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_84 ( .A ( chanx_left_in[2] ) , - .X ( BUF_net_84 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_792 ( .A ( ropt_net_177 ) , - .X ( ropt_net_193 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_86 ( .A ( chanx_left_in[8] ) , - .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_178 ) , - .X ( ropt_net_202 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_179 ) , - .X ( ropt_net_198 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_180 ) , - .X ( ropt_net_201 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_90 ( .A ( chanx_left_in[16] ) , - .X ( ropt_net_183 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_181 ) , - .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_824 ( .A ( ropt_net_202 ) , - .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_826 ( .A ( ropt_net_203 ) , - .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_100 ( .A ( chanx_right_in[0] ) , - .X ( ropt_net_163 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( ropt_net_182 ) , - .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_183 ) , - .X ( ropt_net_195 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_184 ) , - .X ( ropt_net_206 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_185 ) , - .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_186 ) , - .X ( ropt_net_200 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_187 ) , - .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_188 ) , - .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_189 ) , - .X ( ropt_net_203 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_190 ) , - .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_191 ) , - .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_827 ( .A ( ropt_net_204 ) , - .X ( chany_bottom_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_828 ( .A ( ropt_net_205 ) , - .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_113 ( .A ( chanx_left_in[12] ) , - .X ( ropt_net_185 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_829 ( .A ( ropt_net_206 ) , - .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_830 ( .A ( ropt_net_207 ) , - .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_208 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_832 ( .A ( ropt_net_209 ) , - .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_122 ( .A ( chanx_right_in[16] ) , - .X ( ropt_net_159 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_834 ( .A ( ropt_net_210 ) , - .X ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_129 ( .A ( chanx_right_in[1] ) , - .X ( ropt_net_173 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_835 ( .A ( ropt_net_211 ) , - .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_131 ( .A ( BUF_net_75 ) , - .X ( ropt_net_207 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_132 ( .A ( chanx_right_in[7] ) , - .X ( ropt_net_190 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_836 ( .A ( ropt_net_212 ) , - .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_134 ( .A ( BUF_net_78 ) , - .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_837 ( .A ( ropt_net_213 ) , - .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_839 ( .A ( ropt_net_214 ) , - .X ( chany_bottom_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_840 ( .A ( ropt_net_215 ) , - .X ( Test_en__FEEDTHRU_1[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_138 ( .A ( chanx_left_in[0] ) , - .X ( ropt_net_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_139 ( .A ( BUF_net_84 ) , - .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_841 ( .A ( ropt_net_216 ) , - .X ( Test_en__FEEDTHRU_2[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_141 ( .A ( chanx_left_in[13] ) , - .X ( ropt_net_181 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_142 ( .A ( chanx_left_in[14] ) , - .X ( ropt_net_178 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y0 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y0 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x294400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x312800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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-sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x285200y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x317400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x335800y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x400200y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x892400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x910800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x257600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x276000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x358800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x377200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x427800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x487600y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x924600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x961400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x998200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1035000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1071800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1108600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1145400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1163800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1173000y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x193200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x202400y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x248400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x340400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x501400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x510600y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x611800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x621000y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x800400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x818800y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x170200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x207000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x303600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x322000y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x409400y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x450800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x460000y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x506000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x542800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x552000y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x699200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x708400y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x754400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x846400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x864800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x924600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x961400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x998200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1058000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x142600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x161000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x170200y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x216200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x253000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x478400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x496800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x506000y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x552000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x570400y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x722200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x740600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x749800y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x975200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1012000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1048800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1108600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1145400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1163800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1173000y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x36800y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x115000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x276000y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x322000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x358800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x418600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x469200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x519800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x529000y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x644000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x653200y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x699200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x717600y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x924600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1085600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x101200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x138000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x156400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x207000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x225400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x234600y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x322000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x432400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x469200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x519800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x565800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x602600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x653200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x772800y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x961400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x970600y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1058000y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x188600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x197800y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x243800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x427800y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x473800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x510600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x547400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x565800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x616400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x625600y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x708400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x768200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x851000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x906200y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x952200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x989000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x998200y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x69000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x78200y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x358800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x432400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x483000y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x529000y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x680800y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x759000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x924600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x933800y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x161000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x202400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x239200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x312800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x552000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x561200y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x814200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x851000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1108600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1117800y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x179400y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x197800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x464600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x483000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x565800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x602600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x611800y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x690000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x726800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x989000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1039600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1090200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1099400y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x119600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x253000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x289800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x349600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x409400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x478400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x998200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x147200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x248400y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x303600y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x349600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x427800y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x506000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x584200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x593400y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x639400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x676200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x713000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x731400y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x777400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x837200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x929200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x966000y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x230000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x239200y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x395600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x414000y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x460000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x690000y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x731400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x749800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x759000y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x354200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x409400y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x487600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x524400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x533600y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x579600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x648600y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x726800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x745200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x754400y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x800400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x883200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x933800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x952200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1002800y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x234600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x253000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x303600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x395600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x483000y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x529000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x565800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x625600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x676200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x713000y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x759000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x777400y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x823400y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x841800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x906200y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x984400y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x161000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x197800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x234600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x253000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x303600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x340400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x432400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x450800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x501400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x519800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x529000y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x575000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x717600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x814200y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x901600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x984400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1021200y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1099400y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x188600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x207000y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x285200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x386400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x423200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x460000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x478400y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x736000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x754400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x887800y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x929200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x966000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1007400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1025800y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1067200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1104000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1140800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x119600y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x207000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x243800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x280600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x299000y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x345000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x432400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x469200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x547400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x657800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x713000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x749800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x800400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x837200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1030400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1067200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1117800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1154600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1173000y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x156400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x193200y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x271400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x308200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x345000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x455400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x492200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x529000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x565800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x602600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x639400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x676200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x713000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x749800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x786600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x795800y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x841800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x924600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x961400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x998200y598400 ( - .VGND ( VSS ) , .VPWR ( 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.VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x266800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x285200y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x409400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x418600y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x496800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x570400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x653200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x690000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x699200y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x814200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x851000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1030400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1067200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1085600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1140800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x151800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x188600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x225400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x262200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x299000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x335800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x372600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x690000y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x768200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x805000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x841800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x924600y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1002800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1039600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1076400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1094800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x115000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x151800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x188600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x248400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x285200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x303600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x312800y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x358800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x427800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1025800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1062600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1099400y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x73600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x156400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x193200y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x271400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x308200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x345000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x395600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x432400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x469200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x708400y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x786600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x823400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x860200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x887800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x897000y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x943000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x979800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1016600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1035000y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1081000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1099400y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x110400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x119600y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x197800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x207000y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x248400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x322000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x358800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x464600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x483000y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x529000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x565800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x584200y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x740600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x897000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x970600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1007400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1044200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1081000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1117800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1154600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1173000y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x36800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x276000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x285200y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x464600y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x616400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x634800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x754400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x791200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x924600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x961400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x998200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1016600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1140800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x36800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x46000y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x78200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x115000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x124200y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x170200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x207000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x243800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x262200y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x308200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x358800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x501400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x510600y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x552000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x561200y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x639400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x754400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x823400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x860200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x897000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x933800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x970600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1007400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1044200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1081000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1117800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1154600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1173000y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x101200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x138000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x174800y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x216200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x266800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x414000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x708400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x745200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x782000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x818800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x855600y816000 ( - .VGND ( VSS ) , .VPWR ( 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) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1163800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1173000y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x220800y843200 ( - .VGND ( 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.VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x708400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x745200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x782000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x818800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x855600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x892400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x929200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x966000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1002800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1039600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1076400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1113200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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-sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x846400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x864800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y870400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x924600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x961400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x998200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1035000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1071800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1108600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1145400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1163800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1173000y870400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y897600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x943000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x979800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1016600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1053400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1090200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1127000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1163800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1173000y897600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x515200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x533600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x542800y924800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x708400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x745200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x782000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x818800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x855600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y924800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x924600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x961400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x998200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1035000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1071800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1108600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1145400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1163800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1173000y924800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y952000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x924600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x961400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x998200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1035000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1071800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1108600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1145400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1163800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1173000y952000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_28__81 ( .A ( mem_out[2] ) , - .X ( net_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_100 ( .A ( net_net_100 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__80 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__79 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__78 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__77 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__76 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__75 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__74 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__73 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__72 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__71 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__70 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_mem_8 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__69 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_mem_10 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__68 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_mem_9 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__67 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__66 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_8 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_10 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_9 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size16_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:4] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__65 ( .A ( mem_out[4] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size16_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:4] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__64 ( .A ( mem_out[4] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size16_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:4] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__63 ( .A ( mem_out[4] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size16_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:4] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__62 ( .A ( mem_out[4] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size16_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:15] in ; -input [0:4] sram ; -input [0:4] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l5_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size16_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:15] in ; -input [0:4] sram ; -input [0:4] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_15_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , - .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_83 ( - .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( BUF_net_83 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_128 ( .A ( BUF_net_83 ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size16_2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:15] in ; -input [0:4] sram ; -input [0:4] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_15_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , - .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size16 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:15] in ; -input [0:4] sram ; -input [0:4] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_15_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , - .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__61 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__60 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__59 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__58 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__57 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__56 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__55 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__54 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_3 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:11] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:11] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_127 ( - .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:11] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:11] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_5 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:11] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_4 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:11] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:11] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_6 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:11] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1_ ( prog_clk , chany_top_in , top_left_grid_pin_42_ , - top_left_grid_pin_43_ , top_left_grid_pin_44_ , top_left_grid_pin_45_ , - top_left_grid_pin_46_ , top_left_grid_pin_47_ , top_left_grid_pin_48_ , - top_left_grid_pin_49_ , chanx_right_in , right_bottom_grid_pin_34_ , - right_bottom_grid_pin_35_ , right_bottom_grid_pin_36_ , - right_bottom_grid_pin_37_ , right_bottom_grid_pin_38_ , - right_bottom_grid_pin_39_ , right_bottom_grid_pin_40_ , - right_bottom_grid_pin_41_ , chany_bottom_in , bottom_left_grid_pin_42_ , - bottom_left_grid_pin_43_ , bottom_left_grid_pin_44_ , - bottom_left_grid_pin_45_ , bottom_left_grid_pin_46_ , - bottom_left_grid_pin_47_ , bottom_left_grid_pin_48_ , - bottom_left_grid_pin_49_ , chanx_left_in , left_bottom_grid_pin_34_ , - left_bottom_grid_pin_35_ , left_bottom_grid_pin_36_ , - left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , - left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , - left_bottom_grid_pin_41_ , ccff_head , chany_top_out , chanx_right_out , - chany_bottom_out , chanx_left_out , ccff_tail , VDD , VSS , - prog_clk__FEEDTHRU_1 , Test_en__FEEDTHRU_0 , Test_en__FEEDTHRU_1 , - clk__FEEDTHRU_0 , clk__FEEDTHRU_1 , - grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 , - grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) ; -input [0:0] prog_clk ; -input [0:19] chany_top_in ; -input [0:0] top_left_grid_pin_42_ ; -input [0:0] top_left_grid_pin_43_ ; -input [0:0] top_left_grid_pin_44_ ; -input [0:0] top_left_grid_pin_45_ ; -input [0:0] top_left_grid_pin_46_ ; -input [0:0] top_left_grid_pin_47_ ; -input [0:0] top_left_grid_pin_48_ ; -input [0:0] top_left_grid_pin_49_ ; -input [0:19] chanx_right_in ; -input [0:0] right_bottom_grid_pin_34_ ; -input [0:0] right_bottom_grid_pin_35_ ; -input [0:0] right_bottom_grid_pin_36_ ; -input [0:0] right_bottom_grid_pin_37_ ; -input [0:0] right_bottom_grid_pin_38_ ; -input [0:0] right_bottom_grid_pin_39_ ; -input [0:0] right_bottom_grid_pin_40_ ; -input [0:0] right_bottom_grid_pin_41_ ; -input [0:19] chany_bottom_in ; -input [0:0] bottom_left_grid_pin_42_ ; -input [0:0] bottom_left_grid_pin_43_ ; -input [0:0] bottom_left_grid_pin_44_ ; -input [0:0] bottom_left_grid_pin_45_ ; -input [0:0] bottom_left_grid_pin_46_ ; -input [0:0] bottom_left_grid_pin_47_ ; -input [0:0] bottom_left_grid_pin_48_ ; -input [0:0] bottom_left_grid_pin_49_ ; -input [0:19] chanx_left_in ; -input [0:0] left_bottom_grid_pin_34_ ; -input [0:0] left_bottom_grid_pin_35_ ; -input [0:0] left_bottom_grid_pin_36_ ; -input [0:0] left_bottom_grid_pin_37_ ; -input [0:0] left_bottom_grid_pin_38_ ; -input [0:0] left_bottom_grid_pin_39_ ; -input [0:0] left_bottom_grid_pin_40_ ; -input [0:0] left_bottom_grid_pin_41_ ; -input [0:0] ccff_head ; -output [0:19] chany_top_out ; -output [0:19] chanx_right_out ; -output [0:19] chany_bottom_out ; -output [0:19] chanx_left_out ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; -output [0:0] prog_clk__FEEDTHRU_1 ; -input [0:0] Test_en__FEEDTHRU_0 ; -output [0:0] Test_en__FEEDTHRU_1 ; -input [0:0] clk__FEEDTHRU_0 ; -output [0:0] clk__FEEDTHRU_1 ; -input [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ; -output [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ; - -wire [0:3] mux_bottom_track_17_undriven_sram_inv ; -wire [0:3] mux_bottom_track_1_undriven_sram_inv ; -wire [0:3] mux_bottom_track_25_undriven_sram_inv ; -wire [0:2] mux_bottom_track_33_undriven_sram_inv ; -wire [0:3] mux_bottom_track_3_undriven_sram_inv ; -wire [0:4] mux_bottom_track_5_undriven_sram_inv ; -wire [0:3] mux_bottom_track_9_undriven_sram_inv ; -wire [0:3] mux_left_track_17_undriven_sram_inv ; -wire [0:3] mux_left_track_1_undriven_sram_inv ; -wire [0:3] mux_left_track_25_undriven_sram_inv ; -wire [0:2] mux_left_track_33_undriven_sram_inv ; -wire [0:3] mux_left_track_3_undriven_sram_inv ; -wire [0:4] mux_left_track_5_undriven_sram_inv ; -wire [0:3] mux_left_track_9_undriven_sram_inv ; -wire [0:3] mux_right_track_0_undriven_sram_inv ; -wire [0:3] mux_right_track_16_undriven_sram_inv ; -wire [0:3] mux_right_track_24_undriven_sram_inv ; -wire [0:3] mux_right_track_2_undriven_sram_inv ; -wire [0:2] mux_right_track_32_undriven_sram_inv ; -wire [0:4] mux_right_track_4_undriven_sram_inv ; -wire [0:3] mux_right_track_8_undriven_sram_inv ; -wire [0:3] mux_top_track_0_undriven_sram_inv ; -wire [0:3] mux_top_track_16_undriven_sram_inv ; -wire [0:3] mux_top_track_24_undriven_sram_inv ; -wire [0:3] mux_top_track_2_undriven_sram_inv ; -wire [0:2] mux_top_track_32_undriven_sram_inv ; -wire [0:4] mux_top_track_4_undriven_sram_inv ; -wire [0:3] mux_top_track_8_undriven_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_10_sram ; -wire [0:3] mux_tree_tapbuf_size10_11_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:3] mux_tree_tapbuf_size10_2_sram ; -wire [0:3] mux_tree_tapbuf_size10_3_sram ; -wire [0:3] mux_tree_tapbuf_size10_4_sram ; -wire [0:3] mux_tree_tapbuf_size10_5_sram ; -wire [0:3] mux_tree_tapbuf_size10_6_sram ; -wire [0:3] mux_tree_tapbuf_size10_7_sram ; -wire [0:3] mux_tree_tapbuf_size10_8_sram ; -wire [0:3] mux_tree_tapbuf_size10_9_sram ; -wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_10_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_11_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_8_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_9_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size12_0_sram ; -wire [0:3] mux_tree_tapbuf_size12_1_sram ; -wire [0:3] mux_tree_tapbuf_size12_2_sram ; -wire [0:3] mux_tree_tapbuf_size12_3_sram ; -wire [0:3] mux_tree_tapbuf_size12_4_sram ; -wire [0:3] mux_tree_tapbuf_size12_5_sram ; -wire [0:3] mux_tree_tapbuf_size12_6_sram ; -wire [0:3] mux_tree_tapbuf_size12_7_sram ; -wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size12_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size12_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail ; -wire [0:4] mux_tree_tapbuf_size16_0_sram ; -wire [0:4] mux_tree_tapbuf_size16_1_sram ; -wire [0:4] mux_tree_tapbuf_size16_2_sram ; -wire [0:4] mux_tree_tapbuf_size16_3_sram ; -wire [0:0] mux_tree_tapbuf_size16_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size16_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size16_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size16_mem_3_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size7_0_sram ; -wire [0:2] mux_tree_tapbuf_size7_1_sram ; -wire [0:2] mux_tree_tapbuf_size7_2_sram ; -wire [0:2] mux_tree_tapbuf_size7_3_sram ; -wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; -supply1 VDD ; -supply0 VSS ; - -assign clk__FEEDTHRU_1[0] = clk__FEEDTHRU_0[0] ; - -sb_1__1__mux_tree_tapbuf_size12_6 mux_top_track_0 ( - .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , - top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , - chanx_right_in[1] , chanx_right_in[2] , chanx_right_in[12] , - chany_bottom_in[2] , chany_bottom_in[12] , chanx_left_in[0] , - chanx_left_in[2] , chanx_left_in[12] } ) , - .sram ( mux_tree_tapbuf_size12_0_sram ) , - .sram_inv ( mux_top_track_0_undriven_sram_inv ) , - .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_145 ) ) ; -sb_1__1__mux_tree_tapbuf_size12 mux_top_track_2 ( - .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , - top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , - chanx_right_in[3] , chanx_right_in[4] , chanx_right_in[13] , - chany_bottom_in[4] , chany_bottom_in[13] , chanx_left_in[4] , - chanx_left_in[13] , chanx_left_in[19] } ) , - .sram ( mux_tree_tapbuf_size12_1_sram ) , - .sram_inv ( mux_top_track_2_undriven_sram_inv ) , - .out ( chany_top_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_149 ) ) ; -sb_1__1__mux_tree_tapbuf_size12_4 mux_right_track_0 ( - .in ( { chany_top_in[2] , chany_top_in[12] , chany_top_in[19] , - right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , - right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , - chany_bottom_in[2] , chany_bottom_in[12] , chany_bottom_in[15] , - chanx_left_in[2] , chanx_left_in[12] } ) , - .sram ( mux_tree_tapbuf_size12_2_sram ) , - .sram_inv ( mux_right_track_0_undriven_sram_inv ) , - .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_145 ) ) ; -sb_1__1__mux_tree_tapbuf_size12_5 mux_right_track_2 ( - .in ( { chany_top_in[0] , chany_top_in[4] , chany_top_in[13] , - right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , - right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] , - chany_bottom_in[4] , chany_bottom_in[11] , chany_bottom_in[13] , - chanx_left_in[4] , chanx_left_in[13] } ) , - .sram ( mux_tree_tapbuf_size12_3_sram ) , - .sram_inv ( mux_right_track_2_undriven_sram_inv ) , - .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_146 ) ) ; -sb_1__1__mux_tree_tapbuf_size12_0 mux_bottom_track_1 ( - .in ( { chany_top_in[2] , chany_top_in[12] , chanx_right_in[2] , - chanx_right_in[12] , chanx_right_in[15] , - bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , - bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , - chanx_left_in[1] , chanx_left_in[2] , chanx_left_in[12] } ) , - .sram ( mux_tree_tapbuf_size12_4_sram ) , - .sram_inv ( mux_bottom_track_1_undriven_sram_inv ) , - .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_147 ) ) ; -sb_1__1__mux_tree_tapbuf_size12_1 mux_bottom_track_3 ( - .in ( { chany_top_in[4] , chany_top_in[13] , chanx_right_in[4] , - chanx_right_in[11] , chanx_right_in[13] , - bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , - bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , - chanx_left_in[3] , chanx_left_in[4] , chanx_left_in[13] } ) , - .sram ( mux_tree_tapbuf_size12_5_sram ) , - .sram_inv ( mux_bottom_track_3_undriven_sram_inv ) , - .out ( chany_bottom_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_147 ) ) ; -sb_1__1__mux_tree_tapbuf_size12_2 mux_left_track_1 ( - .in ( { chany_top_in[0] , chany_top_in[2] , chany_top_in[12] , - chanx_right_in[2] , chanx_right_in[12] , chany_bottom_in[2] , - chany_bottom_in[12] , chany_bottom_in[19] , - left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , - left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , - .sram ( mux_tree_tapbuf_size12_6_sram ) , - .sram_inv ( mux_left_track_1_undriven_sram_inv ) , - .out ( { ropt_net_158 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_147 ) ) ; -sb_1__1__mux_tree_tapbuf_size12_3 mux_left_track_3 ( - .in ( { chany_top_in[4] , chany_top_in[13] , chany_top_in[19] , - chanx_right_in[4] , chanx_right_in[13] , chany_bottom_in[0] , - chany_bottom_in[4] , chany_bottom_in[13] , - left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , - left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , - .sram ( mux_tree_tapbuf_size12_7_sram ) , - .sram_inv ( mux_left_track_3_undriven_sram_inv ) , - .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_148 ) ) ; -sb_1__1__mux_tree_tapbuf_size12_mem_6 mem_top_track_0 ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__1__mux_tree_tapbuf_size12_mem mem_top_track_2 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__1__mux_tree_tapbuf_size12_mem_4 mem_right_track_0 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__1__mux_tree_tapbuf_size12_mem_5 mem_right_track_2 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__1__mux_tree_tapbuf_size12_mem_0 mem_bottom_track_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__1__mux_tree_tapbuf_size12_mem_1 mem_bottom_track_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__1__mux_tree_tapbuf_size12_mem_2 mem_left_track_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__1__mux_tree_tapbuf_size12_mem_3 mem_left_track_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__1__mux_tree_tapbuf_size16 mux_top_track_4 ( - .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_43_[0] , - top_left_grid_pin_44_[0] , top_left_grid_pin_45_[0] , - top_left_grid_pin_46_[0] , top_left_grid_pin_47_[0] , - top_left_grid_pin_48_[0] , top_left_grid_pin_49_[0] , - chanx_right_in[5] , chanx_right_in[7] , chanx_right_in[14] , - chany_bottom_in[5] , chany_bottom_in[14] , chanx_left_in[5] , - chanx_left_in[14] , chanx_left_in[15] } ) , - .sram ( mux_tree_tapbuf_size16_0_sram ) , - .sram_inv ( mux_top_track_4_undriven_sram_inv ) , - .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_149 ) ) ; -sb_1__1__mux_tree_tapbuf_size16_2 mux_right_track_4 ( - .in ( { chany_top_in[1] , chany_top_in[5] , chany_top_in[14] , - right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_35_[0] , - right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_37_[0] , - right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_39_[0] , - right_bottom_grid_pin_40_[0] , right_bottom_grid_pin_41_[0] , - chany_bottom_in[5] , chany_bottom_in[7] , chany_bottom_in[14] , - chanx_left_in[5] , chanx_left_in[14] } ) , - .sram ( mux_tree_tapbuf_size16_1_sram ) , - .sram_inv ( mux_right_track_4_undriven_sram_inv ) , - .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_146 ) ) ; -sb_1__1__mux_tree_tapbuf_size16_0 mux_bottom_track_5 ( - .in ( { chany_top_in[5] , chany_top_in[14] , chanx_right_in[5] , - chanx_right_in[7] , chanx_right_in[14] , bottom_left_grid_pin_42_[0] , - bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_44_[0] , - bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_46_[0] , - bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_48_[0] , - bottom_left_grid_pin_49_[0] , chanx_left_in[5] , chanx_left_in[7] , - chanx_left_in[14] } ) , - .sram ( mux_tree_tapbuf_size16_2_sram ) , - .sram_inv ( mux_bottom_track_5_undriven_sram_inv ) , - .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_148 ) ) ; -sb_1__1__mux_tree_tapbuf_size16_1 mux_left_track_5 ( - .in ( { chany_top_in[5] , chany_top_in[14] , chany_top_in[15] , - chanx_right_in[5] , chanx_right_in[14] , chany_bottom_in[1] , - chany_bottom_in[5] , chany_bottom_in[14] , - left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_35_[0] , - left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_37_[0] , - left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_39_[0] , - left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_41_[0] } ) , - .sram ( mux_tree_tapbuf_size16_3_sram ) , - .sram_inv ( mux_left_track_5_undriven_sram_inv ) , - .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_148 ) ) ; -sb_1__1__mux_tree_tapbuf_size16_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size16_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size16_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__1__mux_tree_tapbuf_size16_mem_2 mem_right_track_4 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size16_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size16_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__1__mux_tree_tapbuf_size16_mem_0 mem_bottom_track_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size16_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size16_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__1__mux_tree_tapbuf_size16_mem_1 mem_left_track_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size16_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size16_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__1__mux_tree_tapbuf_size10 mux_top_track_8 ( - .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_46_[0] , - chanx_right_in[6] , chanx_right_in[11] , chanx_right_in[16] , - chany_bottom_in[6] , chany_bottom_in[16] , chanx_left_in[6] , - chanx_left_in[11] , chanx_left_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_top_track_8_undriven_sram_inv ) , - .out ( chany_top_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_145 ) ) ; -sb_1__1__mux_tree_tapbuf_size10_9 mux_top_track_16 ( - .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_47_[0] , - chanx_right_in[8] , chanx_right_in[15] , chanx_right_in[17] , - chany_bottom_in[8] , chany_bottom_in[17] , chanx_left_in[7] , - chanx_left_in[8] , chanx_left_in[17] } ) , - .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_top_track_16_undriven_sram_inv ) , - .out ( chany_top_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_148 ) ) ; -sb_1__1__mux_tree_tapbuf_size10_10 mux_top_track_24 ( - .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_48_[0] , - chanx_right_in[9] , chanx_right_in[18] , chanx_right_in[19] , - chany_bottom_in[9] , chany_bottom_in[18] , chanx_left_in[3] , - chanx_left_in[9] , chanx_left_in[18] } ) , - .sram ( mux_tree_tapbuf_size10_2_sram ) , - .sram_inv ( mux_top_track_24_undriven_sram_inv ) , - .out ( chany_top_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_145 ) ) ; -sb_1__1__mux_tree_tapbuf_size10_8 mux_right_track_8 ( - .in ( { chany_top_in[3] , chany_top_in[6] , chany_top_in[16] , - right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_38_[0] , - chany_bottom_in[3] , chany_bottom_in[6] , chany_bottom_in[16] , - chanx_left_in[6] , chanx_left_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_3_sram ) , - .sram_inv ( mux_right_track_8_undriven_sram_inv ) , - .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_146 ) ) ; -sb_1__1__mux_tree_tapbuf_size10_6 mux_right_track_16 ( - .in ( { chany_top_in[7] , chany_top_in[8] , chany_top_in[17] , - right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_39_[0] , - chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[17] , - chanx_left_in[8] , chanx_left_in[17] } ) , - .sram ( mux_tree_tapbuf_size10_4_sram ) , - .sram_inv ( mux_right_track_16_undriven_sram_inv ) , - .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_146 ) ) ; -sb_1__1__mux_tree_tapbuf_size10_7 mux_right_track_24 ( - .in ( { chany_top_in[9] , chany_top_in[11] , chany_top_in[18] , - right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_40_[0] , - chany_bottom_in[0] , chany_bottom_in[9] , chany_bottom_in[18] , - chanx_left_in[9] , chanx_left_in[18] } ) , - .sram ( mux_tree_tapbuf_size10_5_sram ) , - .sram_inv ( mux_right_track_24_undriven_sram_inv ) , - .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_145 ) ) ; -sb_1__1__mux_tree_tapbuf_size10_2 mux_bottom_track_9 ( - .in ( { chany_top_in[6] , chany_top_in[16] , chanx_right_in[3] , - chanx_right_in[6] , chanx_right_in[16] , bottom_left_grid_pin_42_[0] , - bottom_left_grid_pin_46_[0] , chanx_left_in[6] , chanx_left_in[11] , - chanx_left_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_6_sram ) , - .sram_inv ( mux_bottom_track_9_undriven_sram_inv ) , - .out ( chany_bottom_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_147 ) ) ; -sb_1__1__mux_tree_tapbuf_size10_0 mux_bottom_track_17 ( - .in ( { chany_top_in[8] , chany_top_in[17] , chanx_right_in[1] , - chanx_right_in[8] , chanx_right_in[17] , bottom_left_grid_pin_43_[0] , - bottom_left_grid_pin_47_[0] , chanx_left_in[8] , chanx_left_in[15] , - chanx_left_in[17] } ) , - .sram ( mux_tree_tapbuf_size10_7_sram ) , - .sram_inv ( mux_bottom_track_17_undriven_sram_inv ) , - .out ( chany_bottom_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_146 ) ) ; -sb_1__1__mux_tree_tapbuf_size10_1 mux_bottom_track_25 ( - .in ( { chany_top_in[9] , chany_top_in[18] , chanx_right_in[0] , - chanx_right_in[9] , chanx_right_in[18] , bottom_left_grid_pin_44_[0] , - bottom_left_grid_pin_48_[0] , chanx_left_in[9] , chanx_left_in[18] , - chanx_left_in[19] } ) , - .sram ( mux_tree_tapbuf_size10_8_sram ) , - .sram_inv ( mux_bottom_track_25_undriven_sram_inv ) , - .out ( chany_bottom_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_145 ) ) ; -sb_1__1__mux_tree_tapbuf_size10_5 mux_left_track_9 ( - .in ( { chany_top_in[6] , chany_top_in[11] , chany_top_in[16] , - chanx_right_in[6] , chanx_right_in[16] , chany_bottom_in[3] , - chany_bottom_in[6] , chany_bottom_in[16] , - left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_38_[0] } ) , - .sram ( mux_tree_tapbuf_size10_9_sram ) , - .sram_inv ( mux_left_track_9_undriven_sram_inv ) , - .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_147 ) ) ; -sb_1__1__mux_tree_tapbuf_size10_3 mux_left_track_17 ( - .in ( { chany_top_in[7] , chany_top_in[8] , chany_top_in[17] , - chanx_right_in[8] , chanx_right_in[17] , chany_bottom_in[7] , - chany_bottom_in[8] , chany_bottom_in[17] , - left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_39_[0] } ) , - .sram ( mux_tree_tapbuf_size10_10_sram ) , - .sram_inv ( mux_left_track_17_undriven_sram_inv ) , - .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_148 ) ) ; -sb_1__1__mux_tree_tapbuf_size10_4 mux_left_track_25 ( - .in ( { chany_top_in[3] , chany_top_in[9] , chany_top_in[18] , - chanx_right_in[9] , chanx_right_in[18] , chany_bottom_in[9] , - chany_bottom_in[11] , chany_bottom_in[18] , - left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_40_[0] } ) , - .sram ( mux_tree_tapbuf_size10_11_sram ) , - .sram_inv ( mux_left_track_25_undriven_sram_inv ) , - .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_147 ) ) ; -sb_1__1__mux_tree_tapbuf_size10_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size16_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__1__mux_tree_tapbuf_size10_mem_9 mem_top_track_16 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__1__mux_tree_tapbuf_size10_mem_10 mem_top_track_24 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__1__mux_tree_tapbuf_size10_mem_8 mem_right_track_8 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size16_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__1__mux_tree_tapbuf_size10_mem_6 mem_right_track_16 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__1__mux_tree_tapbuf_size10_mem_7 mem_right_track_24 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__1__mux_tree_tapbuf_size10_mem_2 mem_bottom_track_9 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size16_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__1__mux_tree_tapbuf_size10_mem_0 mem_bottom_track_17 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__1__mux_tree_tapbuf_size10_mem_1 mem_bottom_track_25 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_8_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__1__mux_tree_tapbuf_size10_mem_5 mem_left_track_9 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size16_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_9_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_9_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__1__mux_tree_tapbuf_size10_mem_3 mem_left_track_17 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_9_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_10_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_10_sram ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -sb_1__1__mux_tree_tapbuf_size10_mem_4 mem_left_track_25 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_10_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_11_sram ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -sb_1__1__mux_tree_tapbuf_size7 mux_top_track_32 ( - .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_49_[0] , - chanx_right_in[0] , chanx_right_in[10] , chany_bottom_in[10] , - chanx_left_in[1] , chanx_left_in[10] } ) , - .sram ( mux_tree_tapbuf_size7_0_sram ) , - .sram_inv ( mux_top_track_32_undriven_sram_inv ) , - .out ( chany_top_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_145 ) ) ; -sb_1__1__mux_tree_tapbuf_size7_2 mux_right_track_32 ( - .in ( { chany_top_in[10] , chany_top_in[15] , - right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_41_[0] , - chany_bottom_in[10] , chany_bottom_in[19] , chanx_left_in[10] } ) , - .sram ( mux_tree_tapbuf_size7_1_sram ) , - .sram_inv ( mux_right_track_32_undriven_sram_inv ) , - .out ( chanx_right_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_146 ) ) ; -sb_1__1__mux_tree_tapbuf_size7_0 mux_bottom_track_33 ( - .in ( { chany_top_in[10] , chanx_right_in[10] , chanx_right_in[19] , - bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_49_[0] , - chanx_left_in[0] , chanx_left_in[10] } ) , - .sram ( mux_tree_tapbuf_size7_2_sram ) , - .sram_inv ( mux_bottom_track_33_undriven_sram_inv ) , - .out ( chany_bottom_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_147 ) ) ; -sb_1__1__mux_tree_tapbuf_size7_1 mux_left_track_33 ( - .in ( { chany_top_in[1] , chany_top_in[10] , chanx_right_in[10] , - chany_bottom_in[10] , chany_bottom_in[15] , - left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_41_[0] } ) , - .sram ( mux_tree_tapbuf_size7_3_sram ) , - .sram_inv ( mux_left_track_33_undriven_sram_inv ) , - .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_148 ) ) ; -sb_1__1__mux_tree_tapbuf_size7_mem mem_top_track_32 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__1__mux_tree_tapbuf_size7_mem_2 mem_right_track_32 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__1__mux_tree_tapbuf_size7_mem_0 mem_bottom_track_33 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__1__mux_tree_tapbuf_size7_mem_1 mem_left_track_33 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , - .ccff_tail ( { ropt_net_155 } ) , - .mem_out ( mux_tree_tapbuf_size7_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1379 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1380 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1381 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1382 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1383 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1384 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1385 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1386 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1387 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1388 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1389 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1390 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1391 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1392 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1393 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1394 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1395 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1396 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1397 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1398 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1399 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1400 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1401 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1402 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1403 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1404 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1405 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1406 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1407 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1408 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1409 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1410 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1411 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1412 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1413 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1414 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1415 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1416 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1417 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1418 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1419 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1420 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__conb_1 optlc_140 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_142 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__2 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_179 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_top_in[6] ) , - .X ( ropt_net_194 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chany_top_in[8] ) , - .X ( ropt_net_178 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chany_top_in[9] ) , - .X ( ropt_net_170 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_top_in[10] ) , - .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chany_top_in[12] ) , - .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__8 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_174 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chany_top_in[14] ) , - .X ( ropt_net_196 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__10 ( .A ( chany_top_in[16] ) , - .X ( ropt_net_166 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__11 ( .A ( chany_top_in[17] ) , - .X ( ropt_net_197 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__12 ( .A ( chany_top_in[18] ) , - .X ( ropt_net_189 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_855 ( .A ( ropt_net_200 ) , - .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_144 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_146 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , - .HI ( optlc_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_198 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__clkbuf_1 \prog_clk[0]_bip415 ( .A ( prog_clk[0] ) , - .X ( ctsbuf_net_1151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_20__19 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_192 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_right_in[12] ) , - .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( chanx_left_in[14] ) , - .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_23__22 ( .A ( chanx_right_in[14] ) , - .X ( ropt_net_173 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chanx_right_in[16] ) , - .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_25__24 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_184 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_26__25 ( .A ( chanx_right_in[18] ) , - .X ( ropt_net_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chany_bottom_in[2] ) , - .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_28__27 ( .A ( chany_bottom_in[4] ) , - .X ( ropt_net_171 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_359774 ( .A ( ctsbuf_net_1151 ) , - .X ( prog_clk__FEEDTHRU_1[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_802 ( .A ( chanx_left_in[5] ) , - .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_856 ( .A ( ropt_net_201 ) , - .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_32__31 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_33__32 ( .A ( chany_bottom_in[10] ) , - .X ( ropt_net_193 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_154 ) , - .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_35__34 ( .A ( chany_bottom_in[13] ) , - .X ( ropt_net_199 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_804 ( .A ( ropt_net_155 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_37__36 ( .A ( chany_bottom_in[16] ) , - .X ( ropt_net_186 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_858 ( .A ( ropt_net_202 ) , - .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_39__38 ( .A ( chany_bottom_in[18] ) , - .X ( ropt_net_182 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( - .A ( Test_en__FEEDTHRU_0[0] ) , .X ( ropt_net_225 ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( chanx_right_in[4] ) , - .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_807 ( .A ( ropt_net_158 ) , - .X ( ropt_net_224 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_808 ( .A ( chanx_right_in[5] ) , - .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( chanx_right_in[2] ) , - .X ( ropt_net_201 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_810 ( .A ( chany_bottom_in[6] ) , - .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_46__45 ( .A ( chanx_left_in[10] ) , - .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_47__46 ( .A ( chanx_left_in[12] ) , - .X ( ropt_net_185 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_48__47 ( .A ( chanx_left_in[13] ) , - .X ( ropt_net_169 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_811 ( .A ( chany_bottom_in[5] ) , - .X ( ropt_net_227 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_50__49 ( .A ( chanx_left_in[16] ) , - .X ( ropt_net_181 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_51__50 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_183 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_52__51 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_172 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_860 ( .A ( ropt_net_203 ) , - .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_812 ( - .A ( chany_bottom_in[17] ) , .X ( ropt_net_226 ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_85 ( .A ( chany_top_in[4] ) , - .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_861 ( .A ( ropt_net_204 ) , - .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_862 ( .A ( ropt_net_205 ) , - .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_88 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_176 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( chanx_left_in[2] ) , - .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_165 ) , - .X ( ropt_net_210 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_91 ( .A ( chany_bottom_in[8] ) , - .X ( ropt_net_154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_863 ( .A ( ropt_net_206 ) , - .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_166 ) , - .X ( ropt_net_223 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_167 ) , - .X ( ropt_net_206 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_95 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_180 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_96 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_177 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_97 ( .A ( chanx_left_in[9] ) , - .X ( ropt_net_168 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_864 ( .A ( ropt_net_207 ) , - .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_817 ( .A ( ropt_net_168 ) , - .X ( ropt_net_220 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_169 ) , - .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_170 ) , - .X ( ropt_net_208 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_171 ) , - .X ( ropt_net_200 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_172 ) , - .X ( ropt_net_215 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_108 ( .A ( chanx_left_in[4] ) , - .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_173 ) , - .X ( ropt_net_207 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_174 ) , - .X ( ropt_net_216 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_175 ) , - .X ( ropt_net_204 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_119 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_195 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_120 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_191 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_121 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_167 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_122 ( .A ( chany_bottom_in[12] ) , - .X ( ropt_net_188 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_123 ( .A ( chany_bottom_in[14] ) , - .X ( ropt_net_175 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_865 ( .A ( ropt_net_208 ) , - .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( ropt_net_176 ) , - .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_867 ( .A ( ropt_net_209 ) , - .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_868 ( .A ( ropt_net_210 ) , - .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_826 ( .A ( ropt_net_177 ) , - .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_871 ( .A ( ropt_net_211 ) , - .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_875 ( .A ( ropt_net_212 ) , - .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_876 ( .A ( ropt_net_213 ) , - .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_827 ( .A ( ropt_net_178 ) , - .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_136 ( - .A ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] ) , - .X ( ropt_net_190 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_179 ) , - .X ( ropt_net_219 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_829 ( .A ( ropt_net_180 ) , - .X ( ropt_net_209 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_181 ) , - .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_182 ) , - .X ( ropt_net_214 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_832 ( .A ( ropt_net_183 ) , - .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_833 ( .A ( ropt_net_184 ) , - .X ( ropt_net_222 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_834 ( .A ( ropt_net_185 ) , - .X ( ropt_net_218 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_835 ( .A ( ropt_net_186 ) , - .X ( ropt_net_205 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_836 ( .A ( ropt_net_187 ) , - .X ( ropt_net_211 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_837 ( .A ( ropt_net_188 ) , - .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_838 ( .A ( ropt_net_189 ) , - .X ( ropt_net_203 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_839 ( .A ( ropt_net_190 ) , - .X ( ropt_net_221 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_840 ( .A ( ropt_net_191 ) , - .X ( ropt_net_212 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_841 ( .A ( ropt_net_192 ) , - .X ( ropt_net_213 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_842 ( .A ( ropt_net_193 ) , - .X ( ropt_net_217 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_843 ( .A ( ropt_net_194 ) , - .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_844 ( .A ( ropt_net_195 ) , - .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_845 ( .A ( ropt_net_196 ) , - .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_846 ( .A ( ropt_net_197 ) , - .X ( ropt_net_202 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_849 ( .A ( ropt_net_198 ) , - .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_851 ( .A ( ropt_net_199 ) , - .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_878 ( .A ( ropt_net_214 ) , - .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_880 ( .A ( ropt_net_215 ) , - .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_881 ( .A ( ropt_net_216 ) , - .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_882 ( .A ( ropt_net_217 ) , - .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_883 ( .A ( ropt_net_218 ) , - .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_885 ( .A ( ropt_net_219 ) , - .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_886 ( .A ( ropt_net_220 ) , - .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_887 ( .A ( ropt_net_221 ) , - .X ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_888 ( .A ( ropt_net_222 ) , - .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_890 ( .A ( ropt_net_223 ) , - .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_893 ( .A ( ropt_net_224 ) , - .X ( chanx_left_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_897 ( .A ( ropt_net_225 ) , - .X ( Test_en__FEEDTHRU_1[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_898 ( .A ( ropt_net_226 ) , - .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_899 ( .A ( ropt_net_227 ) , - .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y0 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y0 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 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VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x961400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x998200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1035000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1071800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1108600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1145400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1163800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1173000y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x92000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x142600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x151800y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x197800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x248400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x299000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x335800y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x391000y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x437000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x446200y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x524400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x542800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x552000y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x630200y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x717600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x726800y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x993600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1044200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1094800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1145400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1163800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1173000y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x147200y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x193200y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x239200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x276000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x358800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x377200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x423200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x441600y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; 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VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x906200y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x952200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x961400y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1007400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1058000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1094800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1131600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x92000y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x138000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x174800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x211600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x230000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x280600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x299000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x409400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x492200y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x607200y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x685400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x694600y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x777400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x795800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x846400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x892400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x910800y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1030400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1067200y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1113200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x128800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x138000y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x312800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x381800y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x478400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x529000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x579600y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x625600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x722200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x814200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x851000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x887800y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x966000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1016600y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1104000y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x36800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x184000y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x230000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x289800y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x432400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x441600y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x487600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x496800y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x579600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x588800y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x676200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x685400y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x731400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x740600y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x892400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1104000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1140800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x36800y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x78200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x87400y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x216200y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x262200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x299000y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x377200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x455400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x492200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x529000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x588800y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x754400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x837200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x887800y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x933800y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x979800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1030400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1048800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1058000y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1099400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1136200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1173000y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x101200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x138000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x174800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x211600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x248400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x257600y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x303600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x340400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x432400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x450800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x460000y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x506000y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x630200y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x676200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x713000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x749800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x768200y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x814200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x823400y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x869400y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x947600y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x110400y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x239200y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x409400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x460000y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x506000y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x588800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x639400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x717600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x768200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x805000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x814200y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x860200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x887800y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x933800y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x979800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1030400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1067200y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1145400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1163800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1173000y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x184000y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x262200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x363400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x473800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x510600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x529000y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x547400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x598000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x616400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x625600y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x722200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x731400y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x777400y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x823400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x924600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x961400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x998200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1016600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x188600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x225400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x271400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x308200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x345000y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x391000y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x437000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x515200y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x860200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x887800y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x933800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x970600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1007400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1025800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x105800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x115000y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x161000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x170200y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x248400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x285200y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x363400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x519800y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x565800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x616400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x634800y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x676200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x694600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x786600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x920000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x979800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1016600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1025800y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x73600y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x119600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x138000y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x216200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x276000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x409400y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x455400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x492200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x529000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x565800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x602600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x639400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x722200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x740600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x749800y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x795800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x814200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x864800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x887800y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x961400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1021200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1071800y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x73600y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x216200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x253000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x303600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x322000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x409400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x418600y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x588800y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x713000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x722200y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x768200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x777400y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x823400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x860200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x984400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x271400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x289800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x556600y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x602600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x657800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x694600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x713000y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x791200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x193200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x230000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x248400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x257600y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x303600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x312800y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x358800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x515200y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x561200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x570400y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x616400y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x662400y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x708400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x717600y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x814200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x897000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x975200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x299000y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x345000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x381800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x441600y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x529000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x579600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x598000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x740600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x759000y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x805000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x864800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1012000y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x188600y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x234600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x285200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x294400y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x501400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x510600y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x556600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x680800y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x795800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x878600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x915400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1016600y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x174800y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x220800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x303600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x340400y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x460000y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x506000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x524400y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x570400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x621000y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x828000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x961400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x998200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1007400y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1085600y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x105800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x115000y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x202400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x239200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x322000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x340400y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x469200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x556600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x565800y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x611800y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x699200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x708400y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x749800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x786600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x823400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x860200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x869400y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x947600y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1025800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1044200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1053400y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x87400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x105800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x156400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x193200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x253000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x289800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x299000y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x345000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x510600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x519800y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x565800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x602600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x639400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x740600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x749800y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x887800y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x933800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x970600y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1016600y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x101200y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x326600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x335800y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x538200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x556600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x607200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x657800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x694600y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x846400y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x892400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x929200y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x975200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x993600y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x73600y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x110400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x119600y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x165600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x211600y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x257600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x276000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x358800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x478400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x644000y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x690000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x749800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x759000y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x805000y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x851000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x956800y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x220800y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x312800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x331200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x340400y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x400200y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x671600y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x717600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x736000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x745200y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x791200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x809600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x860200y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x906200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x924600y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x970600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x989000y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1035000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1071800y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x165600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x225400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x262200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x271400y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x317400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x326600y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x441600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x460000y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x506000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x524400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x575000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x699200y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x777400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x887800y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x933800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x998200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1016600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1025800y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x193200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x271400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x308200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x326600y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x473800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x483000y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x529000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x565800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x584200y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x630200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x680800y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x699200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x717600y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x832600y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x910800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x920000y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x966000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x984400y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1030400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1122400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1159200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x73600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x82800y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x395600y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x441600y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x487600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x538200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x722200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x731400y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x814200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x823400y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x906200y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x993600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1076400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1094800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1136200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1173000y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x147200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x165600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x257600y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x345000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x538200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x588800y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x731400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x768200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x777400y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x823400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x841800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x851000y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x989000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1007400y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1053400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1090200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1136200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1173000y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x119600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x128800y870400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x207000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x243800y870400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x289800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x326600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x335800y870400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x487600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x561200y870400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x639400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x648600y870400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x694600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x713000y870400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x759000y870400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x805000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x814200y870400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x860200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x970600y870400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1016600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1127000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1163800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1173000y870400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x257600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x276000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x285200y897600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y897600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x464600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x473800y897600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x519800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x602600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x621000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x680800y897600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x924600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y897600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1140800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x92000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x142600y924800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x188600y924800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x432400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x607200y924800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x726800y924800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y924800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x961400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1062600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1099400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1136200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1173000y924800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x335800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x400200y952000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x892400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x929200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x966000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1002800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1039600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1076400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1113200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x331200y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x423200y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x460000y979200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y979200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x257600y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x276000y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x358800y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y1006400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x400200y1006400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x432400y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x892400y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x910800y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x257600y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x276000y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x285200y1033600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y1033600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y1060800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y1060800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__60 ( .A ( mem_out[2] ) , - .X ( net_net_84 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_84 ( .A ( net_net_84 ) , - .X ( net_net_83 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_103 ( .A ( net_net_83 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__59 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__58 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__57 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size11_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__56 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size11_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__55 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size11_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:10] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[10] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size11 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:10] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[10] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__54 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__53 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size3_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__52 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size3_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__51 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__50 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__49 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__48 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__47 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size3_5 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size3_4 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__46 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__45 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__44 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__43 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__42 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__41 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__40 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__39 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__38 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__37 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__36 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_7 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_6 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__35 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__34 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__33 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0_ ( prog_clk , chany_top_in , top_left_grid_pin_42_ , - top_left_grid_pin_43_ , top_left_grid_pin_44_ , top_left_grid_pin_45_ , - top_left_grid_pin_46_ , top_left_grid_pin_47_ , top_left_grid_pin_48_ , - top_left_grid_pin_49_ , chanx_right_in , right_bottom_grid_pin_1_ , - right_bottom_grid_pin_3_ , right_bottom_grid_pin_5_ , - right_bottom_grid_pin_7_ , right_bottom_grid_pin_9_ , - right_bottom_grid_pin_11_ , chanx_left_in , left_bottom_grid_pin_1_ , - left_bottom_grid_pin_3_ , left_bottom_grid_pin_5_ , - left_bottom_grid_pin_7_ , left_bottom_grid_pin_9_ , - left_bottom_grid_pin_11_ , ccff_head , chany_top_out , chanx_right_out , - chanx_left_out , ccff_tail , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , - SC_OUT_BOT , VDD , VSS , prog_clk__FEEDTHRU_1 , prog_clk__FEEDTHRU_2 ) ; -input [0:0] prog_clk ; -input [0:19] chany_top_in ; -input [0:0] top_left_grid_pin_42_ ; -input [0:0] top_left_grid_pin_43_ ; -input [0:0] top_left_grid_pin_44_ ; -input [0:0] top_left_grid_pin_45_ ; -input [0:0] top_left_grid_pin_46_ ; -input [0:0] top_left_grid_pin_47_ ; -input [0:0] top_left_grid_pin_48_ ; -input [0:0] top_left_grid_pin_49_ ; -input [0:19] chanx_right_in ; -input [0:0] right_bottom_grid_pin_1_ ; -input [0:0] right_bottom_grid_pin_3_ ; -input [0:0] right_bottom_grid_pin_5_ ; -input [0:0] right_bottom_grid_pin_7_ ; -input [0:0] right_bottom_grid_pin_9_ ; -input [0:0] right_bottom_grid_pin_11_ ; -input [0:19] chanx_left_in ; -input [0:0] left_bottom_grid_pin_1_ ; -input [0:0] left_bottom_grid_pin_3_ ; -input [0:0] left_bottom_grid_pin_5_ ; -input [0:0] left_bottom_grid_pin_7_ ; -input [0:0] left_bottom_grid_pin_9_ ; -input [0:0] left_bottom_grid_pin_11_ ; -input [0:0] ccff_head ; -output [0:19] chany_top_out ; -output [0:19] chanx_right_out ; -output [0:19] chanx_left_out ; -output [0:0] ccff_tail ; -input SC_IN_TOP ; -input SC_IN_BOT ; -output SC_OUT_TOP ; -output SC_OUT_BOT ; -input VDD ; -input VSS ; -output [0:0] prog_clk__FEEDTHRU_1 ; -output [0:0] prog_clk__FEEDTHRU_2 ; - -wire [0:2] mux_left_track_17_undriven_sram_inv ; -wire [0:3] mux_left_track_1_undriven_sram_inv ; -wire [0:2] mux_left_track_25_undriven_sram_inv ; -wire [0:2] mux_left_track_33_undriven_sram_inv ; -wire [0:2] mux_left_track_3_undriven_sram_inv ; -wire [0:3] mux_left_track_5_undriven_sram_inv ; -wire [0:2] mux_left_track_9_undriven_sram_inv ; -wire [0:2] mux_right_track_0_undriven_sram_inv ; -wire [0:2] mux_right_track_16_undriven_sram_inv ; -wire [0:2] mux_right_track_24_undriven_sram_inv ; -wire [0:3] mux_right_track_2_undriven_sram_inv ; -wire [0:2] mux_right_track_32_undriven_sram_inv ; -wire [0:3] mux_right_track_4_undriven_sram_inv ; -wire [0:2] mux_right_track_8_undriven_sram_inv ; -wire [0:3] mux_top_track_0_undriven_sram_inv ; -wire [0:2] mux_top_track_10_undriven_sram_inv ; -wire [0:1] mux_top_track_12_undriven_sram_inv ; -wire [0:1] mux_top_track_14_undriven_sram_inv ; -wire [0:1] mux_top_track_16_undriven_sram_inv ; -wire [0:1] mux_top_track_18_undriven_sram_inv ; -wire [0:1] mux_top_track_20_undriven_sram_inv ; -wire [0:1] mux_top_track_22_undriven_sram_inv ; -wire [0:1] mux_top_track_24_undriven_sram_inv ; -wire [0:2] mux_top_track_2_undriven_sram_inv ; -wire [0:1] mux_top_track_38_undriven_sram_inv ; -wire [0:2] mux_top_track_4_undriven_sram_inv ; -wire [0:2] mux_top_track_6_undriven_sram_inv ; -wire [0:2] mux_top_track_8_undriven_sram_inv ; -wire [0:3] mux_tree_tapbuf_size11_0_sram ; -wire [0:3] mux_tree_tapbuf_size11_1_sram ; -wire [0:0] mux_tree_tapbuf_size11_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size11_mem_1_ccff_tail ; -wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; -wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:1] mux_tree_tapbuf_size3_2_sram ; -wire [0:1] mux_tree_tapbuf_size3_3_sram ; -wire [0:1] mux_tree_tapbuf_size3_4_sram ; -wire [0:1] mux_tree_tapbuf_size3_5_sram ; -wire [0:1] mux_tree_tapbuf_size3_6_sram ; -wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size4_0_sram ; -wire [0:2] mux_tree_tapbuf_size4_1_sram ; -wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size5_0_sram ; -wire [0:2] mux_tree_tapbuf_size5_1_sram ; -wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size6_1_sram ; -wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size7_0_sram ; -wire [0:2] mux_tree_tapbuf_size7_1_sram ; -wire [0:2] mux_tree_tapbuf_size7_2_sram ; -wire [0:2] mux_tree_tapbuf_size7_3_sram ; -wire [0:2] mux_tree_tapbuf_size7_4_sram ; -wire [0:2] mux_tree_tapbuf_size7_5_sram ; -wire [0:2] mux_tree_tapbuf_size7_6_sram ; -wire [0:2] mux_tree_tapbuf_size7_7_sram ; -wire [0:2] mux_tree_tapbuf_size7_8_sram ; -wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_7_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_8_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:3] mux_tree_tapbuf_size8_2_sram ; -wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; -supply1 VDD ; -supply0 VSS ; - -assign SC_IN_TOP = SC_IN_BOT ; -assign prog_clk__FEEDTHRU_1[0] = prog_clk__FEEDTHRU_2[0] ; - -sb_1__0__mux_tree_tapbuf_size8 mux_top_track_0 ( - .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , - top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , - chanx_right_in[1] , chanx_right_in[2] , chanx_left_in[0] , - chanx_left_in[2] } ) , - .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_top_track_0_undriven_sram_inv ) , - .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_120 ) ) ; -sb_1__0__mux_tree_tapbuf_size8_1 mux_right_track_2 ( - .in ( { chany_top_in[0] , chany_top_in[7] , chany_top_in[14] , - right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_7_[0] , - right_bottom_grid_pin_11_[0] , chanx_left_in[4] , chanx_left_in[13] } ) , - .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_right_track_2_undriven_sram_inv ) , - .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_123 ) ) ; -sb_1__0__mux_tree_tapbuf_size8_0 mux_left_track_1 ( - .in ( { chany_top_in[0] , chany_top_in[7] , chany_top_in[14] , - chanx_right_in[2] , chanx_right_in[12] , left_bottom_grid_pin_1_[0] , - left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] } ) , - .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_left_track_1_undriven_sram_inv ) , - .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_120 ) ) ; -sb_1__0__mux_tree_tapbuf_size8_mem mem_top_track_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__0__mux_tree_tapbuf_size8_mem_1 mem_right_track_2 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__0__mux_tree_tapbuf_size8_mem_0 mem_left_track_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__0__mux_tree_tapbuf_size7_6 mux_top_track_2 ( - .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , - top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , - chanx_right_in[3] , chanx_right_in[4] , chanx_left_in[4] } ) , - .sram ( mux_tree_tapbuf_size7_0_sram ) , - .sram_inv ( mux_top_track_2_undriven_sram_inv ) , - .out ( chany_top_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_121 ) ) ; -sb_1__0__mux_tree_tapbuf_size7_7 mux_top_track_4 ( - .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , - top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , - chanx_right_in[5] , chanx_right_in[7] , chanx_left_in[5] } ) , - .sram ( mux_tree_tapbuf_size7_1_sram ) , - .sram_inv ( mux_top_track_4_undriven_sram_inv ) , - .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_122 ) ) ; -sb_1__0__mux_tree_tapbuf_size7 mux_top_track_6 ( - .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , - top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , - chanx_right_in[6] , chanx_right_in[11] , chanx_left_in[6] } ) , - .sram ( mux_tree_tapbuf_size7_2_sram ) , - .sram_inv ( mux_top_track_6_undriven_sram_inv ) , - .out ( chany_top_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_122 ) ) ; -sb_1__0__mux_tree_tapbuf_size7_3 mux_right_track_0 ( - .in ( { chany_top_in[6] , chany_top_in[13] , right_bottom_grid_pin_1_[0] , - right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] , - chanx_left_in[2] , chanx_left_in[12] } ) , - .sram ( mux_tree_tapbuf_size7_3_sram ) , - .sram_inv ( mux_right_track_0_undriven_sram_inv ) , - .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_121 ) ) ; -sb_1__0__mux_tree_tapbuf_size7_5 mux_right_track_8 ( - .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , - right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_9_[0] , - chanx_left_in[6] , chanx_left_in[16] } ) , - .sram ( mux_tree_tapbuf_size7_4_sram ) , - .sram_inv ( mux_right_track_8_undriven_sram_inv ) , - .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_124 ) ) ; -sb_1__0__mux_tree_tapbuf_size7_4 mux_right_track_16 ( - .in ( { chany_top_in[3] , chany_top_in[10] , chany_top_in[17] , - right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_11_[0] , - chanx_left_in[8] , chanx_left_in[17] } ) , - .sram ( mux_tree_tapbuf_size7_5_sram ) , - .sram_inv ( mux_right_track_16_undriven_sram_inv ) , - .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_124 ) ) ; -sb_1__0__mux_tree_tapbuf_size7_1 mux_left_track_3 ( - .in ( { chany_top_in[6] , chany_top_in[13] , chanx_right_in[4] , - chanx_right_in[13] , left_bottom_grid_pin_3_[0] , - left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] } ) , - .sram ( mux_tree_tapbuf_size7_6_sram ) , - .sram_inv ( mux_left_track_3_undriven_sram_inv ) , - .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_120 ) ) ; -sb_1__0__mux_tree_tapbuf_size7_2 mux_left_track_9 ( - .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , - chanx_right_in[6] , chanx_right_in[16] , left_bottom_grid_pin_1_[0] , - left_bottom_grid_pin_9_[0] } ) , - .sram ( mux_tree_tapbuf_size7_7_sram ) , - .sram_inv ( mux_left_track_9_undriven_sram_inv ) , - .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_120 ) ) ; -sb_1__0__mux_tree_tapbuf_size7_0 mux_left_track_17 ( - .in ( { chany_top_in[3] , chany_top_in[10] , chany_top_in[17] , - chanx_right_in[8] , chanx_right_in[17] , left_bottom_grid_pin_3_[0] , - left_bottom_grid_pin_11_[0] } ) , - .sram ( mux_tree_tapbuf_size7_8_sram ) , - .sram_inv ( mux_left_track_17_undriven_sram_inv ) , - .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_120 ) ) ; -sb_1__0__mux_tree_tapbuf_size7_mem_6 mem_top_track_2 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__0__mux_tree_tapbuf_size7_mem_7 mem_top_track_4 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__0__mux_tree_tapbuf_size7_mem mem_top_track_6 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__0__mux_tree_tapbuf_size7_mem_3 mem_right_track_0 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__0__mux_tree_tapbuf_size7_mem_5 mem_right_track_8 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size11_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__0__mux_tree_tapbuf_size7_mem_4 mem_right_track_16 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__0__mux_tree_tapbuf_size7_mem_1 mem_left_track_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__0__mux_tree_tapbuf_size7_mem_2 mem_left_track_9 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size11_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__0__mux_tree_tapbuf_size7_mem_0 mem_left_track_17 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_8_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_8_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__0__mux_tree_tapbuf_size4 mux_top_track_8 ( - .in ( { top_left_grid_pin_42_[0] , chanx_right_in[8] , - chanx_right_in[15] , chanx_left_in[8] } ) , - .sram ( mux_tree_tapbuf_size4_0_sram ) , - .sram_inv ( mux_top_track_8_undriven_sram_inv ) , - .out ( chany_top_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_122 ) ) ; -sb_1__0__mux_tree_tapbuf_size4_0 mux_top_track_10 ( - .in ( { top_left_grid_pin_43_[0] , chanx_right_in[9] , - chanx_right_in[19] , chanx_left_in[9] } ) , - .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_top_track_10_undriven_sram_inv ) , - .out ( chany_top_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_124 ) ) ; -sb_1__0__mux_tree_tapbuf_size4_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__0__mux_tree_tapbuf_size4_mem_0 mem_top_track_10 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__0__mux_tree_tapbuf_size3_0 mux_top_track_12 ( - .in ( { top_left_grid_pin_44_[0] , chanx_right_in[10] , - chanx_left_in[10] } ) , - .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_top_track_12_undriven_sram_inv ) , - .out ( chany_top_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_121 ) ) ; -sb_1__0__mux_tree_tapbuf_size3_1 mux_top_track_14 ( - .in ( { top_left_grid_pin_45_[0] , chanx_right_in[12] , - chanx_left_in[12] } ) , - .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_top_track_14_undriven_sram_inv ) , - .out ( chany_top_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_121 ) ) ; -sb_1__0__mux_tree_tapbuf_size3_2 mux_top_track_16 ( - .in ( { top_left_grid_pin_46_[0] , chanx_right_in[13] , - chanx_left_in[13] } ) , - .sram ( mux_tree_tapbuf_size3_2_sram ) , - .sram_inv ( mux_top_track_16_undriven_sram_inv ) , - .out ( chany_top_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_120 ) ) ; -sb_1__0__mux_tree_tapbuf_size3_3 mux_top_track_18 ( - .in ( { top_left_grid_pin_47_[0] , chanx_right_in[14] , - chanx_left_in[14] } ) , - .sram ( mux_tree_tapbuf_size3_3_sram ) , - .sram_inv ( mux_top_track_18_undriven_sram_inv ) , - .out ( chany_top_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_121 ) ) ; -sb_1__0__mux_tree_tapbuf_size3_4 mux_top_track_20 ( - .in ( { top_left_grid_pin_48_[0] , chanx_right_in[16] , - chanx_left_in[16] } ) , - .sram ( mux_tree_tapbuf_size3_4_sram ) , - .sram_inv ( mux_top_track_20_undriven_sram_inv ) , - .out ( chany_top_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_122 ) ) ; -sb_1__0__mux_tree_tapbuf_size3_5 mux_top_track_22 ( - .in ( { top_left_grid_pin_49_[0] , chanx_right_in[17] , - chanx_left_in[17] } ) , - .sram ( mux_tree_tapbuf_size3_5_sram ) , - .sram_inv ( mux_top_track_22_undriven_sram_inv ) , - .out ( chany_top_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_122 ) ) ; -sb_1__0__mux_tree_tapbuf_size3 mux_top_track_24 ( - .in ( { top_left_grid_pin_42_[0] , chanx_right_in[18] , - chanx_left_in[18] } ) , - .sram ( mux_tree_tapbuf_size3_6_sram ) , - .sram_inv ( mux_top_track_24_undriven_sram_inv ) , - .out ( chany_top_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_121 ) ) ; -sb_1__0__mux_tree_tapbuf_size3_mem_0 mem_top_track_12 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__0__mux_tree_tapbuf_size3_mem_1 mem_top_track_14 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__0__mux_tree_tapbuf_size3_mem_2 mem_top_track_16 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__0__mux_tree_tapbuf_size3_mem_3 mem_top_track_18 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__0__mux_tree_tapbuf_size3_mem_4 mem_top_track_20 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__0__mux_tree_tapbuf_size3_mem_5 mem_top_track_22 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__0__mux_tree_tapbuf_size3_mem mem_top_track_24 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__0__mux_tree_tapbuf_size2 mux_top_track_38 ( - .in ( { chanx_right_in[0] , chanx_left_in[1] } ) , - .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_top_track_38_undriven_sram_inv ) , - .out ( chany_top_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_121 ) ) ; -sb_1__0__mux_tree_tapbuf_size2_mem mem_top_track_38 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__0__mux_tree_tapbuf_size11 mux_right_track_4 ( - .in ( { chany_top_in[1] , chany_top_in[8] , chany_top_in[15] , - right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_3_[0] , - right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_7_[0] , - right_bottom_grid_pin_9_[0] , right_bottom_grid_pin_11_[0] , - chanx_left_in[5] , chanx_left_in[14] } ) , - .sram ( mux_tree_tapbuf_size11_0_sram ) , - .sram_inv ( mux_right_track_4_undriven_sram_inv ) , - .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_123 ) ) ; -sb_1__0__mux_tree_tapbuf_size11_0 mux_left_track_5 ( - .in ( { chany_top_in[5] , chany_top_in[12] , chany_top_in[19] , - chanx_right_in[5] , chanx_right_in[14] , left_bottom_grid_pin_1_[0] , - left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_5_[0] , - left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_9_[0] , - left_bottom_grid_pin_11_[0] } ) , - .sram ( mux_tree_tapbuf_size11_1_sram ) , - .sram_inv ( mux_left_track_5_undriven_sram_inv ) , - .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_120 ) ) ; -sb_1__0__mux_tree_tapbuf_size11_mem mem_right_track_4 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size11_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size11_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__0__mux_tree_tapbuf_size11_mem_0 mem_left_track_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size11_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size11_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__0__mux_tree_tapbuf_size6 mux_right_track_24 ( - .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , - right_bottom_grid_pin_5_[0] , chanx_left_in[9] , chanx_left_in[18] } ) , - .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_right_track_24_undriven_sram_inv ) , - .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_124 ) ) ; -sb_1__0__mux_tree_tapbuf_size6_0 mux_left_track_25 ( - .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , - chanx_right_in[9] , chanx_right_in[18] , left_bottom_grid_pin_5_[0] } ) , - .sram ( mux_tree_tapbuf_size6_1_sram ) , - .sram_inv ( mux_left_track_25_undriven_sram_inv ) , - .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_122 ) ) ; -sb_1__0__mux_tree_tapbuf_size6_mem mem_right_track_24 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__0__mux_tree_tapbuf_size6_mem_0 mem_left_track_25 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_8_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__0__mux_tree_tapbuf_size5 mux_right_track_32 ( - .in ( { chany_top_in[5] , chany_top_in[12] , chany_top_in[19] , - right_bottom_grid_pin_7_[0] , chanx_left_in[10] } ) , - .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_right_track_32_undriven_sram_inv ) , - .out ( chanx_right_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_121 ) ) ; -sb_1__0__mux_tree_tapbuf_size5_0 mux_left_track_33 ( - .in ( { chany_top_in[1] , chany_top_in[8] , chany_top_in[15] , - chanx_right_in[10] , left_bottom_grid_pin_7_[0] } ) , - .sram ( mux_tree_tapbuf_size5_1_sram ) , - .sram_inv ( mux_left_track_33_undriven_sram_inv ) , - .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_120 ) ) ; -sb_1__0__mux_tree_tapbuf_size5_mem mem_right_track_32 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__0__mux_tree_tapbuf_size5_mem_0 mem_left_track_33 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .ccff_tail ( { ropt_net_147 } ) , - .mem_out ( mux_tree_tapbuf_size5_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1340 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1341 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1342 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1343 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1344 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1345 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1346 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1347 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1348 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1349 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1350 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1351 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1352 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1353 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1354 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1355 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1356 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1357 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1358 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1359 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1360 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1361 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1362 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1363 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1364 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1365 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1366 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1367 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1368 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1369 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1370 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1371 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1372 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1373 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1374 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1375 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1376 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1377 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__conb_1 optlc_114 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_120 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chanx_right_in[2] ) , - .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__3 ( .A ( chanx_right_in[5] ) , - .X ( ropt_net_154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_161 ) , - .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_121 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__8 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_158 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_162 ) , - .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__10 ( .A ( chanx_right_in[14] ) , - .X ( ropt_net_151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_123 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , - .HI ( optlc_net_124 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__clkbuf_1 \prog_clk[0]_bip390 ( .A ( prog_clk[0] ) , - .X ( \prog_clk__FEEDTHRU_2[0]0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( .A ( ropt_net_129 ) , - .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chanx_left_in[2] ) , - .X ( ropt_net_152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( chanx_left_in[19] ) , - .X ( ropt_net_169 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chanx_left_in[5] ) , - .X ( ropt_net_150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 cts_buf_368758 ( .A ( \prog_clk__FEEDTHRU_2[0]0 ) , - .X ( prog_clk__FEEDTHRU_2[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_784 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_179 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_785 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_175 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__21 ( .A ( chanx_left_in[9] ) , - .X ( ropt_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chanx_left_in[10] ) , - .X ( ropt_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_134 ) , - .X ( ropt_net_171 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_787 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_176 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_788 ( .A ( chanx_left_in[12] ) , - .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_137 ) , - .X ( ropt_net_163 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( chanx_right_in[18] ) , - .X ( ropt_net_174 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_821 ( .A ( ropt_net_163 ) , - .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_822 ( .A ( ropt_net_164 ) , - .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( chanx_left_in[13] ) , - .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( chanx_left_in[16] ) , - .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( chanx_right_in[6] ) , - .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_178 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_823 ( .A ( ropt_net_165 ) , - .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_166 ) , - .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_825 ( .A ( ropt_net_167 ) , - .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_826 ( .A ( ropt_net_168 ) , - .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_70 ( .A ( chanx_left_in[3] ) , - .X ( ropt_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_71 ( .A ( chanx_left_in[4] ) , - .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_72 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_73 ( .A ( chanx_left_in[7] ) , - .X ( ropt_net_160 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_74 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_156 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_75 ( .A ( chanx_left_in[11] ) , - .X ( ropt_net_137 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_827 ( .A ( ropt_net_169 ) , - .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_170 ) , - .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_78 ( .A ( chanx_left_in[14] ) , - .X ( ropt_net_159 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_79 ( .A ( chanx_left_in[15] ) , - .X ( ropt_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_143 ) , - .X ( ropt_net_164 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_830 ( .A ( ropt_net_171 ) , - .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_832 ( .A ( ropt_net_172 ) , - .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_177 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( ropt_net_145 ) , - .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_146 ) , - .X ( ropt_net_167 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_147 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_148 ) , - .X ( ropt_net_172 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_149 ) , - .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_150 ) , - .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_833 ( .A ( ropt_net_173 ) , - .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_99 ( .A ( top_left_grid_pin_43_[0] ) , - .X ( ropt_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_837 ( .A ( ropt_net_174 ) , - .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_151 ) , - .X ( ropt_net_161 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_105 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_152 ) , - .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_107 ( .A ( chanx_right_in[16] ) , - .X ( ropt_net_134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_153 ) , - .X ( ropt_net_162 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_154 ) , - .X ( ropt_net_166 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_155 ) , - .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_156 ) , - .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_157 ) , - .X ( ropt_net_173 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_810 ( .A ( ropt_net_158 ) , - .X ( ropt_net_170 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_159 ) , - .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_160 ) , - .X ( ropt_net_168 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_838 ( .A ( ropt_net_175 ) , - .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_839 ( .A ( ropt_net_176 ) , - .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_840 ( .A ( ropt_net_177 ) , - .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_841 ( .A ( ropt_net_178 ) , - .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_842 ( .A ( ropt_net_179 ) , - .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y0 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x924600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x961400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x998200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1035000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1071800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1108600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1145400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1163800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1173000y0 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x538200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x754400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x791200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x828000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x864800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x901600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x938400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x975200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1012000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1048800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1085600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1122400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1159200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x754400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x791200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x828000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x864800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x924600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x961400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x998200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1035000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1071800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1108600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1163800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1173000y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x147200y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x188600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x225400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x262200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x299000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x335800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x372600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x409400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x814200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x851000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x924600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x961400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x998200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1035000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1071800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1108600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1145400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1163800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1173000y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1173000y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x515200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x607200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y163200 ( - .VGND ( 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.VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x998200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1035000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1071800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1108600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1145400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1163800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1173000y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x621000y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x667000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x685400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x731400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x768200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x805000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x841800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x878600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x915400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x952200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x989000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1025800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1062600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1099400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1136200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1173000y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x128800y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x161000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x197800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x234600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x271400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x289800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x409400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x519800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x538200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x814200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x851000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x924600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x961400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x998200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1035000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x179400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x216200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x234600y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x354200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x616400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x653200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x690000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x708400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x717600y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x910800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x947600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x984400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1021200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1058000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1094800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1131600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x340400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x349600y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x464600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x625600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x644000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x653200y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x887800y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1048800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1085600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1122400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1159200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x73600y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x115000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x151800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x722200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x740600y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x786600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x823400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x860200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x878600y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1016600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1076400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1094800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x147200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x165600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x404800y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x483000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x501400y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x579600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x598000y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x754400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x763600y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x805000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x823400y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x924600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x961400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1071800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1136200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1173000y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x92000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x101200y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x179400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x216200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x253000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x289800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x437000y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x625600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x644000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x694600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x713000y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x869400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x887800y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x966000y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1044200y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1085600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1140800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x36800y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x69000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x78200y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x124200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x142600y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x423200y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x501400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x593400y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x639400y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x685400y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x772800y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x933800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x970600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1007400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1025800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1035000y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1081000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1099400y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x55200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x92000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x101200y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x331200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x464600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x483000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x492200y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x759000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x786600y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x832600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x851000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x860200y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x979800y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1025800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1044200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1053400y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1094800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x101200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x138000y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x381800y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x427800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x487600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x524400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x542800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x676200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x713000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x795800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x805000y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x851000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x924600y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1002800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1012000y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1058000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x197800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x234600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x326600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x363400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x427800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x570400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x648600y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x694600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x713000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x722200y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x800400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x846400y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x933800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x165600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x202400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x239200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x308200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x326600y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x423200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x460000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x478400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x529000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x565800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x602600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x639400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x657800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x708400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x745200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x782000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x800400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x809600y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x855600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x970600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1021200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1058000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x101200y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x271400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x289800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x473800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x510600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x588800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x607200y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x653200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x690000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x708400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x717600y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x795800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x814200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x901600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x984400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1002800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1053400y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x202400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x239200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x257600y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x335800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x372600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x519800y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x565800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x584200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x593400y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x639400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x749800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x887800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x938400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1016600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1035000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1044200y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1090200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1099400y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x151800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x243800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x294400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x312800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x363400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x441600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x510600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x529000y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x644000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x690000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x740600y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x786600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x805000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x924600y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1002800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1053400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1090200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1127000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1163800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1173000y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x220800y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x262200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x331200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x349600y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x579600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x598000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x607200y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x759000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x786600y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x828000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x864800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x929200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x966000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1002800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1012000y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1058000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x142600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x179400y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x225400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x308200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x345000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x432400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x450800y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x529000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x565800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x584200y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x662400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x680800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x731400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x782000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x800400y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x878600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x151800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x161000y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x239200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x289800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x299000y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x377200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x395600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x404800y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x450800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x579600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x588800y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x634800y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x713000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x823400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x860200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x956800y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1035000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1053400y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x161000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x197800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x234600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x271400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x289800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x427800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x492200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x529000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x538200y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x584200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x602600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x611800y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x657800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x694600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x745200y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x791200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x800400y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x878600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x897000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x989000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x303600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x312800y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x358800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x409400y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x455400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x492200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x542800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x561200y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x644000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x653200y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x694600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x731400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x740600y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x795800y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x841800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x961400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1012000y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x234600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x345000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x437000y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x515200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x533600y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x579600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x639400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x722200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x740600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x823400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x860200y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x901600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x938400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x326600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x386400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x478400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x496800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x547400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x556600y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x602600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x639400y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x795800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x814200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x823400y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1035000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1053400y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x294400y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x427800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x446200y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x487600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x602600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x680800y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x763600y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x920000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x966000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1002800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1012000y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x202400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x239200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x368000y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x483000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x501400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x547400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x584200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x621000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x657800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x676200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x795800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x814200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x823400y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x864800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x924600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x257600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x276000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x391000y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x515200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x524400y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x570400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x657800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x708400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x892400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x929200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x966000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1002800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1039600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1076400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1113200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x331200y870400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x483000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y870400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x418600y897600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x846400y897600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x892400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x910800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x257600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x276000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x432400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x607200y924800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x841800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y924800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y952000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y952000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_24__40 ( .A ( mem_out[1] ) , - .X ( net_net_64 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_89 ( .A ( net_net_64 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__39 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__38 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__37 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__36 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__35 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__34 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__33 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__32 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__31 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__30 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__29 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__28 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__27 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__26 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__25 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__24 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__23 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_43 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__22 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__21 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__20 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__19 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__18 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__17 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2_ ( prog_clk , chanx_right_in , right_top_grid_pin_1_ , - right_bottom_grid_pin_34_ , right_bottom_grid_pin_35_ , - right_bottom_grid_pin_36_ , right_bottom_grid_pin_37_ , - right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ , - right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ , chany_bottom_in , - bottom_left_grid_pin_1_ , ccff_head , chanx_right_out , chany_bottom_out , - ccff_tail , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , SC_OUT_BOT , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:19] chanx_right_in ; -input [0:0] right_top_grid_pin_1_ ; -input [0:0] right_bottom_grid_pin_34_ ; -input [0:0] right_bottom_grid_pin_35_ ; -input [0:0] right_bottom_grid_pin_36_ ; -input [0:0] right_bottom_grid_pin_37_ ; -input [0:0] right_bottom_grid_pin_38_ ; -input [0:0] right_bottom_grid_pin_39_ ; -input [0:0] right_bottom_grid_pin_40_ ; -input [0:0] right_bottom_grid_pin_41_ ; -input [0:19] chany_bottom_in ; -input [0:0] bottom_left_grid_pin_1_ ; -input [0:0] ccff_head ; -output [0:19] chanx_right_out ; -output [0:19] chany_bottom_out ; -output [0:0] ccff_tail ; -input SC_IN_TOP ; -input SC_IN_BOT ; -output SC_OUT_TOP ; -output SC_OUT_BOT ; -input VDD ; -input VSS ; - -wire [0:1] mux_bottom_track_1_undriven_sram_inv ; -wire [0:1] mux_bottom_track_25_undriven_sram_inv ; -wire [0:1] mux_bottom_track_5_undriven_sram_inv ; -wire [0:1] mux_bottom_track_9_undriven_sram_inv ; -wire [0:2] mux_right_track_0_undriven_sram_inv ; -wire [0:1] mux_right_track_10_undriven_sram_inv ; -wire [0:1] mux_right_track_12_undriven_sram_inv ; -wire [0:1] mux_right_track_14_undriven_sram_inv ; -wire [0:1] mux_right_track_16_undriven_sram_inv ; -wire [0:1] mux_right_track_18_undriven_sram_inv ; -wire [0:1] mux_right_track_20_undriven_sram_inv ; -wire [0:1] mux_right_track_22_undriven_sram_inv ; -wire [0:1] mux_right_track_24_undriven_sram_inv ; -wire [0:1] mux_right_track_26_undriven_sram_inv ; -wire [0:1] mux_right_track_28_undriven_sram_inv ; -wire [0:2] mux_right_track_2_undriven_sram_inv ; -wire [0:1] mux_right_track_30_undriven_sram_inv ; -wire [0:1] mux_right_track_32_undriven_sram_inv ; -wire [0:1] mux_right_track_34_undriven_sram_inv ; -wire [0:1] mux_right_track_36_undriven_sram_inv ; -wire [0:1] mux_right_track_38_undriven_sram_inv ; -wire [0:2] mux_right_track_4_undriven_sram_inv ; -wire [0:2] mux_right_track_6_undriven_sram_inv ; -wire [0:1] mux_right_track_8_undriven_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_10_sram ; -wire [0:1] mux_tree_tapbuf_size2_11_sram ; -wire [0:1] mux_tree_tapbuf_size2_12_sram ; -wire [0:1] mux_tree_tapbuf_size2_13_sram ; -wire [0:1] mux_tree_tapbuf_size2_14_sram ; -wire [0:1] mux_tree_tapbuf_size2_15_sram ; -wire [0:1] mux_tree_tapbuf_size2_16_sram ; -wire [0:1] mux_tree_tapbuf_size2_17_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_5_sram ; -wire [0:1] mux_tree_tapbuf_size2_6_sram ; -wire [0:1] mux_tree_tapbuf_size2_7_sram ; -wire [0:1] mux_tree_tapbuf_size2_8_sram ; -wire [0:1] mux_tree_tapbuf_size2_9_sram ; -wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; -wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size5_0_sram ; -wire [0:2] mux_tree_tapbuf_size5_1_sram ; -wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size6_1_sram ; -wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; -supply1 VDD ; -supply0 VSS ; - -assign SC_IN_TOP = SC_IN_BOT ; - -sb_0__2__mux_tree_tapbuf_size6_0 mux_right_track_0 ( - .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] , - right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , - right_bottom_grid_pin_41_[0] , chany_bottom_in[18] } ) , - .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_right_track_0_undriven_sram_inv ) , - .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_114 ) ) ; -sb_0__2__mux_tree_tapbuf_size6 mux_right_track_4 ( - .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] , - right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , - right_bottom_grid_pin_41_[0] , chany_bottom_in[16] } ) , - .sram ( mux_tree_tapbuf_size6_1_sram ) , - .sram_inv ( mux_right_track_4_undriven_sram_inv ) , - .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_115 ) ) ; -sb_0__2__mux_tree_tapbuf_size6_mem_0 mem_right_track_0 ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__2__mux_tree_tapbuf_size6_mem mem_right_track_4 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__2__mux_tree_tapbuf_size5_0 mux_right_track_2 ( - .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , - right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , - chany_bottom_in[17] } ) , - .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_right_track_2_undriven_sram_inv ) , - .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_116 ) ) ; -sb_0__2__mux_tree_tapbuf_size5 mux_right_track_6 ( - .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , - right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , - chany_bottom_in[15] } ) , - .sram ( mux_tree_tapbuf_size5_1_sram ) , - .sram_inv ( mux_right_track_6_undriven_sram_inv ) , - .out ( chanx_right_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_116 ) ) ; -sb_0__2__mux_tree_tapbuf_size5_mem_0 mem_right_track_2 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__2__mux_tree_tapbuf_size5_mem mem_right_track_6 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__2__mux_tree_tapbuf_size3 mux_right_track_8 ( - .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_41_[0] , - chany_bottom_in[14] } ) , - .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_right_track_8_undriven_sram_inv ) , - .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_116 ) ) ; -sb_0__2__mux_tree_tapbuf_size3_0 mux_right_track_24 ( - .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_41_[0] , - chany_bottom_in[6] } ) , - .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_right_track_24_undriven_sram_inv ) , - .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_116 ) ) ; -sb_0__2__mux_tree_tapbuf_size3_mem mem_right_track_8 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__2__mux_tree_tapbuf_size3_mem_0 mem_right_track_24 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__2__mux_tree_tapbuf_size2_4 mux_right_track_10 ( - .in ( { right_bottom_grid_pin_34_[0] , chany_bottom_in[13] } ) , - .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_right_track_10_undriven_sram_inv ) , - .out ( chanx_right_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_116 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_5 mux_right_track_12 ( - .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[12] } ) , - .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_right_track_12_undriven_sram_inv ) , - .out ( chanx_right_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_114 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_6 mux_right_track_14 ( - .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[11] } ) , - .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_right_track_14_undriven_sram_inv ) , - .out ( chanx_right_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_115 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_7 mux_right_track_16 ( - .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[10] } ) , - .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_right_track_16_undriven_sram_inv ) , - .out ( { ropt_net_125 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_117 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_8 mux_right_track_18 ( - .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[9] } ) , - .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_right_track_18_undriven_sram_inv ) , - .out ( chanx_right_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_117 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_9 mux_right_track_20 ( - .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[8] } ) , - .sram ( mux_tree_tapbuf_size2_5_sram ) , - .sram_inv ( mux_right_track_20_undriven_sram_inv ) , - .out ( chanx_right_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_114 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_10 mux_right_track_22 ( - .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[7] } ) , - .sram ( mux_tree_tapbuf_size2_6_sram ) , - .sram_inv ( mux_right_track_22_undriven_sram_inv ) , - .out ( chanx_right_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_114 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_11 mux_right_track_26 ( - .in ( { right_bottom_grid_pin_34_[0] , chany_bottom_in[5] } ) , - .sram ( mux_tree_tapbuf_size2_7_sram ) , - .sram_inv ( mux_right_track_26_undriven_sram_inv ) , - .out ( chanx_right_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_115 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_12 mux_right_track_28 ( - .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[4] } ) , - .sram ( mux_tree_tapbuf_size2_8_sram ) , - .sram_inv ( mux_right_track_28_undriven_sram_inv ) , - .out ( { ropt_net_122 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_117 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_13 mux_right_track_30 ( - .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[3] } ) , - .sram ( mux_tree_tapbuf_size2_9_sram ) , - .sram_inv ( mux_right_track_30_undriven_sram_inv ) , - .out ( chanx_right_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_117 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_14 mux_right_track_32 ( - .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[2] } ) , - .sram ( mux_tree_tapbuf_size2_10_sram ) , - .sram_inv ( mux_right_track_32_undriven_sram_inv ) , - .out ( chanx_right_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_117 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_15 mux_right_track_34 ( - .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[1] } ) , - .sram ( mux_tree_tapbuf_size2_11_sram ) , - .sram_inv ( mux_right_track_34_undriven_sram_inv ) , - .out ( chanx_right_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_117 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_16 mux_right_track_36 ( - .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[0] } ) , - .sram ( mux_tree_tapbuf_size2_12_sram ) , - .sram_inv ( mux_right_track_36_undriven_sram_inv ) , - .out ( chanx_right_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_114 ) ) ; -sb_0__2__mux_tree_tapbuf_size2 mux_right_track_38 ( - .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[19] } ) , - .sram ( mux_tree_tapbuf_size2_13_sram ) , - .sram_inv ( mux_right_track_38_undriven_sram_inv ) , - .out ( chanx_right_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_114 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_0 mux_bottom_track_1 ( - .in ( { chanx_right_in[18] , bottom_left_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size2_14_sram ) , - .sram_inv ( mux_bottom_track_1_undriven_sram_inv ) , - .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_114 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_2 mux_bottom_track_5 ( - .in ( { chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size2_15_sram ) , - .sram_inv ( mux_bottom_track_5_undriven_sram_inv ) , - .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_114 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_3 mux_bottom_track_9 ( - .in ( { chanx_right_in[14] , bottom_left_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size2_16_sram ) , - .sram_inv ( mux_bottom_track_9_undriven_sram_inv ) , - .out ( chany_bottom_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_114 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_1 mux_bottom_track_25 ( - .in ( { chanx_right_in[6] , bottom_left_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size2_17_sram ) , - .sram_inv ( mux_bottom_track_25_undriven_sram_inv ) , - .out ( chany_bottom_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_116 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_4 mem_right_track_10 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_5 mem_right_track_12 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_6 mem_right_track_14 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_7 mem_right_track_16 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_8 mem_right_track_18 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_9 mem_right_track_20 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_10 mem_right_track_22 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_11 mem_right_track_26 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_12 mem_right_track_28 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_8_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_13 mem_right_track_30 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_9_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_14 mem_right_track_32 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_10_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_15 mem_right_track_34 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_11_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_16 mem_right_track_36 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_12_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem mem_right_track_38 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_13_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_0 mem_bottom_track_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_14_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_2 mem_bottom_track_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_15_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_3 mem_bottom_track_9 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_16_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_1 mem_bottom_track_25 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_17_sram ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1303 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1304 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1305 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1306 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1307 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1308 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1309 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1310 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1311 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1312 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1313 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1314 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1315 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1316 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1317 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1318 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1319 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1320 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1321 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1322 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1323 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1324 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1325 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1326 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1327 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1328 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1329 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1330 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1331 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1332 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1333 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1334 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1335 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1336 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1337 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1338 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_114 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_115 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_116 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_113 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_117 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_716 ( .A ( chanx_right_in[3] ) , - .X ( ropt_net_138 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_717 ( .A ( ropt_net_120 ) , - .X ( ropt_net_145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_718 ( .A ( chanx_right_in[12] ) , - .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_122 ) , - .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_123 ) , - .X ( ropt_net_144 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( ropt_net_136 ) , - .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_137 ) , - .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_721 ( .A ( chanx_right_in[2] ) , - .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_138 ) , - .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_125 ) , - .X ( ropt_net_142 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_723 ( .A ( chanx_right_in[17] ) , - .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_724 ( .A ( ropt_net_127 ) , - .X ( ropt_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_17__16 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_120 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( chanx_right_in[19] ) , - .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( chanx_right_in[11] ) , - .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_741 ( .A ( ropt_net_139 ) , - .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_140 ) , - .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_744 ( .A ( ropt_net_141 ) , - .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_52 ( .A ( chanx_right_in[5] ) , - .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_746 ( .A ( ropt_net_142 ) , - .X ( chanx_right_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_747 ( .A ( ropt_net_143 ) , - .X ( chany_bottom_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_748 ( .A ( ropt_net_144 ) , - .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( .A ( ropt_net_145 ) , - .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_59 ( .A ( chanx_right_in[13] ) , - .X ( BUF_net_59 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_60 ( .A ( chanx_right_in[15] ) , - .X ( BUF_net_60 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( ropt_net_130 ) , - .X ( ropt_net_136 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( .A ( ropt_net_131 ) , - .X ( ropt_net_137 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( chanx_right_in[7] ) , - .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_133 ) , - .X ( ropt_net_141 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_86 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_88 ( .A ( BUF_net_59 ) , - .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_92 ( .A ( chanx_right_in[0] ) , - .X ( ropt_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_93 ( .A ( chanx_right_in[1] ) , - .X ( ropt_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y0 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_96 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_99 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_100 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_130 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_102 ( .A ( BUF_net_60 ) , - .X ( ropt_net_139 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y0 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x248400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x437000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x36800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x138000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x174800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x211600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x230000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x239200y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x55200y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x216200y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x335800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x345000y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x110400y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x151800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x170200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x262200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x331200y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x588800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x708400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x745200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x782000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x754400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x805000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x841800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x851000y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x110400y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x188600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x225400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x303600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x322000y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x368000y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x414000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x450800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x469200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x703800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x722200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x731400y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x777400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x795800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x805000y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x73600y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x156400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x174800y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x257600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x276000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x285200y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x478400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x524400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x542800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x625600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x680800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x731400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x768200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x818800y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x864800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x901600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x92000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x174800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x211600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x262200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x299000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x308200y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x354200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x372600y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x418600y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x464600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x547400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x565800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x575000y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x621000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x92000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x174800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x211600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x248400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x322000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x358800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x464600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x483000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x529000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x565800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x602600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x639400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x805000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x855600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x892400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x910800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x128800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x138000y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x184000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x234600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x271400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x368000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x533600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x552000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x561200y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x685400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x703800y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x745200y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x791200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x92000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x101200y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x142600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x161000y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x202400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x239200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x276000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x294400y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x340400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x414000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x432400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x483000y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x529000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x565800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x584200y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x630200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x713000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x749800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x860200y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x892400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x910800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x708400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x745200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x754400y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x800400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x846400y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x128800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x138000y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x363400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x538200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x625600y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x667000y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x713000y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x846400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x243800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x317400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x326600y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x409400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x460000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x496800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x515200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x524400y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x607200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x616400y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x699200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x717600y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x763600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x800400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x846400y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x202400y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x354200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x427800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x496800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x680800y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x805000y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x874000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x910800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x331200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x423200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x460000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x496800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x556600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x722200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x740600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x864800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x257600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x354200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x832600y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x892400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x910800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x211600y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x289800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x326600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x363400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x400200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x437000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x473800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x510600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x547400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x584200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x657800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x694600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x294400y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x464600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x483000y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x529000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x565800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x602600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x621000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x703800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x832600y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x864800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x901600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x220800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x239200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x248400y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x331200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x349600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x432400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x547400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x584200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x621000y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x639400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x648600y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x694600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x731400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x768200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x786600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x257600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x276000y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x354200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x427800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x446200y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x524400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x542800y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x809600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x818800y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x851000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x331200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x349600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x358800y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x437000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x473800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x510600y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x588800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x607200y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x671600y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x749800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x786600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x823400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x860200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; 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VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x768200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x805000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x823400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x878600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x368000y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x409400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x446200y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x492200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x529000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x565800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x602600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x621000y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x809600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x828000y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x409400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x418600y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x460000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x496800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x515200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x524400y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x602600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x639400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x676200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x713000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x749800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x786600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x823400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x892400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x910800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x846400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x864800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x892400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x910800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x809600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x828000y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y843200 ( - .VGND ( VSS ) , .VPWR ( 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.VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y870400 ( - .VGND ( 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.VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y897600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x846400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x864800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y924800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y924800 ( - .VGND ( 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VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y952000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y952000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__59 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__58 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__57 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__56 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__55 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__54 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_127 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_27__53 ( .A ( mem_out[1] ) , - .X ( net_net_86 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_85 ( .A ( net_net_86 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__52 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__51 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__50 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__49 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__48 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__47 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__46 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size4_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__45 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__44 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__43 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__42 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size4_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__41 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__40 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size4_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__39 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_126 ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_65 ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size4_5 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_124 ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size5_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__38 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__37 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size5_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__36 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size5_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__35 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__34 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size5_3 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_63 ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( BUF_net_63 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_123 ( .A ( BUF_net_63 ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__33 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__32 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__31 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__30 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__29 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__28 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__27 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_62 ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( BUF_net_62 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_122 ( .A ( BUF_net_62 ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6_3 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6_5 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6_4 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1_ ( prog_clk , chany_top_in , top_left_grid_pin_1_ , - chanx_right_in , right_bottom_grid_pin_34_ , right_bottom_grid_pin_35_ , - right_bottom_grid_pin_36_ , right_bottom_grid_pin_37_ , - right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ , - right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ , chany_bottom_in , - bottom_left_grid_pin_1_ , ccff_head , chany_top_out , chanx_right_out , - chany_bottom_out , ccff_tail , VDD , VSS , prog_clk__FEEDTHRU_1 ) ; -input [0:0] prog_clk ; -input [0:19] chany_top_in ; -input [0:0] top_left_grid_pin_1_ ; -input [0:19] chanx_right_in ; -input [0:0] right_bottom_grid_pin_34_ ; -input [0:0] right_bottom_grid_pin_35_ ; -input [0:0] right_bottom_grid_pin_36_ ; -input [0:0] right_bottom_grid_pin_37_ ; -input [0:0] right_bottom_grid_pin_38_ ; -input [0:0] right_bottom_grid_pin_39_ ; -input [0:0] right_bottom_grid_pin_40_ ; -input [0:0] right_bottom_grid_pin_41_ ; -input [0:19] chany_bottom_in ; -input [0:0] bottom_left_grid_pin_1_ ; -input [0:0] ccff_head ; -output [0:19] chany_top_out ; -output [0:19] chanx_right_out ; -output [0:19] chany_bottom_out ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; -output [0:0] prog_clk__FEEDTHRU_1 ; - -wire [0:2] mux_bottom_track_17_undriven_sram_inv ; -wire [0:2] mux_bottom_track_1_undriven_sram_inv ; -wire [0:2] mux_bottom_track_25_undriven_sram_inv ; -wire [0:1] mux_bottom_track_33_undriven_sram_inv ; -wire [0:2] mux_bottom_track_3_undriven_sram_inv ; -wire [0:2] mux_bottom_track_5_undriven_sram_inv ; -wire [0:2] mux_bottom_track_9_undriven_sram_inv ; -wire [0:2] mux_right_track_0_undriven_sram_inv ; -wire [0:2] mux_right_track_10_undriven_sram_inv ; -wire [0:2] mux_right_track_12_undriven_sram_inv ; -wire [0:2] mux_right_track_14_undriven_sram_inv ; -wire [0:1] mux_right_track_16_undriven_sram_inv ; -wire [0:1] mux_right_track_18_undriven_sram_inv ; -wire [0:1] mux_right_track_20_undriven_sram_inv ; -wire [0:1] mux_right_track_22_undriven_sram_inv ; -wire [0:2] mux_right_track_24_undriven_sram_inv ; -wire [0:1] mux_right_track_26_undriven_sram_inv ; -wire [0:1] mux_right_track_28_undriven_sram_inv ; -wire [0:2] mux_right_track_2_undriven_sram_inv ; -wire [0:1] mux_right_track_30_undriven_sram_inv ; -wire [0:1] mux_right_track_32_undriven_sram_inv ; -wire [0:1] mux_right_track_34_undriven_sram_inv ; -wire [0:1] mux_right_track_36_undriven_sram_inv ; -wire [0:2] mux_right_track_4_undriven_sram_inv ; -wire [0:2] mux_right_track_6_undriven_sram_inv ; -wire [0:2] mux_right_track_8_undriven_sram_inv ; -wire [0:2] mux_top_track_0_undriven_sram_inv ; -wire [0:2] mux_top_track_16_undriven_sram_inv ; -wire [0:2] mux_top_track_24_undriven_sram_inv ; -wire [0:2] mux_top_track_2_undriven_sram_inv ; -wire [0:2] mux_top_track_32_undriven_sram_inv ; -wire [0:2] mux_top_track_4_undriven_sram_inv ; -wire [0:2] mux_top_track_8_undriven_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_5_sram ; -wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; -wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:1] mux_tree_tapbuf_size3_2_sram ; -wire [0:1] mux_tree_tapbuf_size3_3_sram ; -wire [0:1] mux_tree_tapbuf_size3_4_sram ; -wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size4_0_sram ; -wire [0:2] mux_tree_tapbuf_size4_1_sram ; -wire [0:2] mux_tree_tapbuf_size4_2_sram ; -wire [0:2] mux_tree_tapbuf_size4_3_sram ; -wire [0:2] mux_tree_tapbuf_size4_4_sram ; -wire [0:2] mux_tree_tapbuf_size4_5_sram ; -wire [0:2] mux_tree_tapbuf_size4_6_sram ; -wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_6_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size5_0_sram ; -wire [0:2] mux_tree_tapbuf_size5_1_sram ; -wire [0:2] mux_tree_tapbuf_size5_2_sram ; -wire [0:2] mux_tree_tapbuf_size5_3_sram ; -wire [0:2] mux_tree_tapbuf_size5_4_sram ; -wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size6_1_sram ; -wire [0:2] mux_tree_tapbuf_size6_2_sram ; -wire [0:2] mux_tree_tapbuf_size6_3_sram ; -wire [0:2] mux_tree_tapbuf_size6_4_sram ; -wire [0:2] mux_tree_tapbuf_size6_5_sram ; -wire [0:2] mux_tree_tapbuf_size6_6_sram ; -wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_6_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size7_0_sram ; -wire [0:2] mux_tree_tapbuf_size7_1_sram ; -wire [0:2] mux_tree_tapbuf_size7_2_sram ; -wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; -supply1 VDD ; -supply0 VSS ; - -sb_0__1__mux_tree_tapbuf_size6_4 mux_top_track_0 ( - .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] , chanx_right_in[8] , - chanx_right_in[15] , chany_bottom_in[2] , chany_bottom_in[12] } ) , - .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_top_track_0_undriven_sram_inv ) , - .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_156 ) ) ; -sb_0__1__mux_tree_tapbuf_size6_5 mux_top_track_4 ( - .in ( { top_left_grid_pin_1_[0] , chanx_right_in[3] , chanx_right_in[10] , - chanx_right_in[17] , chany_bottom_in[5] , chany_bottom_in[14] } ) , - .sram ( mux_tree_tapbuf_size6_1_sram ) , - .sram_inv ( mux_top_track_4_undriven_sram_inv ) , - .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_156 ) ) ; -sb_0__1__mux_tree_tapbuf_size6 mux_top_track_8 ( - .in ( { top_left_grid_pin_1_[0] , chanx_right_in[4] , chanx_right_in[11] , - chanx_right_in[18] , chany_bottom_in[6] , chany_bottom_in[16] } ) , - .sram ( mux_tree_tapbuf_size6_2_sram ) , - .sram_inv ( mux_top_track_8_undriven_sram_inv ) , - .out ( chany_top_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_157 ) ) ; -sb_0__1__mux_tree_tapbuf_size6_3 mux_right_track_0 ( - .in ( { chany_top_in[2] , right_bottom_grid_pin_34_[0] , - right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , - right_bottom_grid_pin_40_[0] , chany_bottom_in[2] } ) , - .sram ( mux_tree_tapbuf_size6_3_sram ) , - .sram_inv ( mux_right_track_0_undriven_sram_inv ) , - .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_152 ) ) ; -sb_0__1__mux_tree_tapbuf_size6_0 mux_bottom_track_1 ( - .in ( { chany_top_in[2] , chany_top_in[12] , chanx_right_in[5] , - chanx_right_in[12] , chanx_right_in[19] , bottom_left_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size6_4_sram ) , - .sram_inv ( mux_bottom_track_1_undriven_sram_inv ) , - .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_155 ) ) ; -sb_0__1__mux_tree_tapbuf_size6_1 mux_bottom_track_5 ( - .in ( { chany_top_in[5] , chany_top_in[14] , chanx_right_in[3] , - chanx_right_in[10] , chanx_right_in[17] , bottom_left_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size6_5_sram ) , - .sram_inv ( mux_bottom_track_5_undriven_sram_inv ) , - .out ( { ropt_net_167 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_151 ) ) ; -sb_0__1__mux_tree_tapbuf_size6_2 mux_bottom_track_9 ( - .in ( { chany_top_in[6] , chany_top_in[16] , chanx_right_in[2] , - chanx_right_in[9] , chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size6_6_sram ) , - .sram_inv ( mux_bottom_track_9_undriven_sram_inv ) , - .out ( chany_bottom_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_151 ) ) ; -sb_0__1__mux_tree_tapbuf_size6_mem_4 mem_top_track_0 ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__1__mux_tree_tapbuf_size6_mem_5 mem_top_track_4 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__1__mux_tree_tapbuf_size6_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__1__mux_tree_tapbuf_size6_mem_3 mem_right_track_0 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__1__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__1__mux_tree_tapbuf_size6_mem_1 mem_bottom_track_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__1__mux_tree_tapbuf_size6_mem_2 mem_bottom_track_9 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__1__mux_tree_tapbuf_size5 mux_top_track_2 ( - .in ( { chanx_right_in[2] , chanx_right_in[9] , chanx_right_in[16] , - chany_bottom_in[4] , chany_bottom_in[13] } ) , - .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_top_track_2_undriven_sram_inv ) , - .out ( { ropt_net_168 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_156 ) ) ; -sb_0__1__mux_tree_tapbuf_size5_3 mux_top_track_16 ( - .in ( { chanx_right_in[5] , chanx_right_in[12] , chanx_right_in[19] , - chany_bottom_in[8] , chany_bottom_in[17] } ) , - .sram ( mux_tree_tapbuf_size5_1_sram ) , - .sram_inv ( mux_top_track_16_undriven_sram_inv ) , - .out ( chany_top_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_157 ) ) ; -sb_0__1__mux_tree_tapbuf_size5_2 mux_bottom_track_3 ( - .in ( { chany_top_in[4] , chany_top_in[13] , chanx_right_in[4] , - chanx_right_in[11] , chanx_right_in[18] } ) , - .sram ( mux_tree_tapbuf_size5_2_sram ) , - .sram_inv ( mux_bottom_track_3_undriven_sram_inv ) , - .out ( chany_bottom_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_155 ) ) ; -sb_0__1__mux_tree_tapbuf_size5_0 mux_bottom_track_17 ( - .in ( { chany_top_in[8] , chany_top_in[17] , chanx_right_in[1] , - chanx_right_in[8] , chanx_right_in[15] } ) , - .sram ( mux_tree_tapbuf_size5_3_sram ) , - .sram_inv ( mux_bottom_track_17_undriven_sram_inv ) , - .out ( chany_bottom_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_151 ) ) ; -sb_0__1__mux_tree_tapbuf_size5_1 mux_bottom_track_25 ( - .in ( { chany_top_in[9] , chany_top_in[18] , chanx_right_in[0] , - chanx_right_in[7] , chanx_right_in[14] } ) , - .sram ( mux_tree_tapbuf_size5_4_sram ) , - .sram_inv ( mux_bottom_track_25_undriven_sram_inv ) , - .out ( chany_bottom_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_154 ) ) ; -sb_0__1__mux_tree_tapbuf_size5_mem mem_top_track_2 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__1__mux_tree_tapbuf_size5_mem_3 mem_top_track_16 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__1__mux_tree_tapbuf_size5_mem_2 mem_bottom_track_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__1__mux_tree_tapbuf_size5_mem_0 mem_bottom_track_17 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__1__mux_tree_tapbuf_size5_mem_1 mem_bottom_track_25 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__1__mux_tree_tapbuf_size4_5 mux_top_track_24 ( - .in ( { chanx_right_in[6] , chanx_right_in[13] , chany_bottom_in[9] , - chany_bottom_in[18] } ) , - .sram ( mux_tree_tapbuf_size4_0_sram ) , - .sram_inv ( mux_top_track_24_undriven_sram_inv ) , - .out ( { ropt_net_160 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_153 ) ) ; -sb_0__1__mux_tree_tapbuf_size4 mux_top_track_32 ( - .in ( { chanx_right_in[0] , chanx_right_in[7] , chanx_right_in[14] , - chany_bottom_in[10] } ) , - .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_top_track_32_undriven_sram_inv ) , - .out ( chany_top_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_153 ) ) ; -sb_0__1__mux_tree_tapbuf_size4_4 mux_right_track_8 ( - .in ( { chany_top_in[7] , chany_top_in[8] , right_bottom_grid_pin_34_[0] , - chany_bottom_in[8] } ) , - .sram ( mux_tree_tapbuf_size4_2_sram ) , - .sram_inv ( mux_right_track_8_undriven_sram_inv ) , - .out ( { ropt_net_163 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_153 ) ) ; -sb_0__1__mux_tree_tapbuf_size4_0 mux_right_track_10 ( - .in ( { chany_top_in[9] , chany_top_in[11] , - right_bottom_grid_pin_35_[0] , chany_bottom_in[9] } ) , - .sram ( mux_tree_tapbuf_size4_3_sram ) , - .sram_inv ( mux_right_track_10_undriven_sram_inv ) , - .out ( chanx_right_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_155 ) ) ; -sb_0__1__mux_tree_tapbuf_size4_1 mux_right_track_12 ( - .in ( { chany_top_in[10] , chany_top_in[15] , - right_bottom_grid_pin_36_[0] , chany_bottom_in[10] } ) , - .sram ( mux_tree_tapbuf_size4_4_sram ) , - .sram_inv ( mux_right_track_12_undriven_sram_inv ) , - .out ( chanx_right_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_153 ) ) ; -sb_0__1__mux_tree_tapbuf_size4_2 mux_right_track_14 ( - .in ( { chany_top_in[12] , chany_top_in[19] , - right_bottom_grid_pin_37_[0] , chany_bottom_in[12] } ) , - .sram ( mux_tree_tapbuf_size4_5_sram ) , - .sram_inv ( mux_right_track_14_undriven_sram_inv ) , - .out ( { ropt_net_166 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_155 ) ) ; -sb_0__1__mux_tree_tapbuf_size4_3 mux_right_track_24 ( - .in ( { chany_top_in[18] , right_bottom_grid_pin_34_[0] , - chany_bottom_in[18] , chany_bottom_in[19] } ) , - .sram ( mux_tree_tapbuf_size4_6_sram ) , - .sram_inv ( mux_right_track_24_undriven_sram_inv ) , - .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_154 ) ) ; -sb_0__1__mux_tree_tapbuf_size4_mem_5 mem_top_track_24 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__1__mux_tree_tapbuf_size4_mem mem_top_track_32 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__1__mux_tree_tapbuf_size4_mem_4 mem_right_track_8 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__1__mux_tree_tapbuf_size4_mem_0 mem_right_track_10 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__1__mux_tree_tapbuf_size4_mem_1 mem_right_track_12 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__1__mux_tree_tapbuf_size4_mem_2 mem_right_track_14 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__1__mux_tree_tapbuf_size4_mem_3 mem_right_track_24 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__1__mux_tree_tapbuf_size7_0 mux_right_track_2 ( - .in ( { chany_top_in[0] , chany_top_in[4] , right_bottom_grid_pin_35_[0] , - right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , - right_bottom_grid_pin_41_[0] , chany_bottom_in[4] } ) , - .sram ( mux_tree_tapbuf_size7_0_sram ) , - .sram_inv ( mux_right_track_2_undriven_sram_inv ) , - .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_151 ) ) ; -sb_0__1__mux_tree_tapbuf_size7_1 mux_right_track_4 ( - .in ( { chany_top_in[1] , chany_top_in[5] , right_bottom_grid_pin_34_[0] , - right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , - right_bottom_grid_pin_40_[0] , chany_bottom_in[5] } ) , - .sram ( mux_tree_tapbuf_size7_1_sram ) , - .sram_inv ( mux_right_track_4_undriven_sram_inv ) , - .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_152 ) ) ; -sb_0__1__mux_tree_tapbuf_size7 mux_right_track_6 ( - .in ( { chany_top_in[3] , chany_top_in[6] , right_bottom_grid_pin_35_[0] , - right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , - right_bottom_grid_pin_41_[0] , chany_bottom_in[6] } ) , - .sram ( mux_tree_tapbuf_size7_2_sram ) , - .sram_inv ( mux_right_track_6_undriven_sram_inv ) , - .out ( chanx_right_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_153 ) ) ; -sb_0__1__mux_tree_tapbuf_size7_mem_0 mem_right_track_2 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__1__mux_tree_tapbuf_size7_mem_1 mem_right_track_4 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__1__mux_tree_tapbuf_size7_mem mem_right_track_6 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__1__mux_tree_tapbuf_size3_1 mux_right_track_16 ( - .in ( { chany_top_in[13] , right_bottom_grid_pin_38_[0] , - chany_bottom_in[13] } ) , - .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_right_track_16_undriven_sram_inv ) , - .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_151 ) ) ; -sb_0__1__mux_tree_tapbuf_size3_2 mux_right_track_18 ( - .in ( { chany_top_in[14] , right_bottom_grid_pin_39_[0] , - chany_bottom_in[14] } ) , - .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_right_track_18_undriven_sram_inv ) , - .out ( chanx_right_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_152 ) ) ; -sb_0__1__mux_tree_tapbuf_size3_3 mux_right_track_20 ( - .in ( { chany_top_in[16] , right_bottom_grid_pin_40_[0] , - chany_bottom_in[16] } ) , - .sram ( mux_tree_tapbuf_size3_2_sram ) , - .sram_inv ( mux_right_track_20_undriven_sram_inv ) , - .out ( chanx_right_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_152 ) ) ; -sb_0__1__mux_tree_tapbuf_size3 mux_right_track_22 ( - .in ( { chany_top_in[17] , right_bottom_grid_pin_41_[0] , - chany_bottom_in[17] } ) , - .sram ( mux_tree_tapbuf_size3_3_sram ) , - .sram_inv ( mux_right_track_22_undriven_sram_inv ) , - .out ( chanx_right_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_154 ) ) ; -sb_0__1__mux_tree_tapbuf_size3_0 mux_bottom_track_33 ( - .in ( { chany_top_in[10] , chanx_right_in[6] , chanx_right_in[13] } ) , - .sram ( mux_tree_tapbuf_size3_4_sram ) , - .sram_inv ( mux_bottom_track_33_undriven_sram_inv ) , - .out ( chany_bottom_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_152 ) ) ; -sb_0__1__mux_tree_tapbuf_size3_mem_1 mem_right_track_16 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__1__mux_tree_tapbuf_size3_mem_2 mem_right_track_18 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__1__mux_tree_tapbuf_size3_mem_3 mem_right_track_20 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__1__mux_tree_tapbuf_size3_mem mem_right_track_22 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__1__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_33 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , - .ccff_tail ( { ropt_net_179 } ) , - .mem_out ( mux_tree_tapbuf_size3_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__1__mux_tree_tapbuf_size2_0 mux_right_track_26 ( - .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[15] } ) , - .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_right_track_26_undriven_sram_inv ) , - .out ( { ropt_net_173 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_152 ) ) ; -sb_0__1__mux_tree_tapbuf_size2_1 mux_right_track_28 ( - .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[11] } ) , - .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_right_track_28_undriven_sram_inv ) , - .out ( chanx_right_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_152 ) ) ; -sb_0__1__mux_tree_tapbuf_size2_2 mux_right_track_30 ( - .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[7] } ) , - .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_right_track_30_undriven_sram_inv ) , - .out ( chanx_right_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_152 ) ) ; -sb_0__1__mux_tree_tapbuf_size2_3 mux_right_track_32 ( - .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[3] } ) , - .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_right_track_32_undriven_sram_inv ) , - .out ( chanx_right_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_152 ) ) ; -sb_0__1__mux_tree_tapbuf_size2_4 mux_right_track_34 ( - .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[1] } ) , - .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_right_track_34_undriven_sram_inv ) , - .out ( chanx_right_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_151 ) ) ; -sb_0__1__mux_tree_tapbuf_size2 mux_right_track_36 ( - .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[0] } ) , - .sram ( mux_tree_tapbuf_size2_5_sram ) , - .sram_inv ( mux_right_track_36_undriven_sram_inv ) , - .out ( chanx_right_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_151 ) ) ; -sb_0__1__mux_tree_tapbuf_size2_mem_0 mem_right_track_26 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__1__mux_tree_tapbuf_size2_mem_1 mem_right_track_28 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__1__mux_tree_tapbuf_size2_mem_2 mem_right_track_30 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__1__mux_tree_tapbuf_size2_mem_3 mem_right_track_32 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__1__mux_tree_tapbuf_size2_mem_4 mem_right_track_34 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__1__mux_tree_tapbuf_size2_mem mem_right_track_36 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1264 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1265 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1266 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1267 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1268 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1269 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1270 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1271 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1272 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1273 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1274 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1275 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1276 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1277 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1278 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1279 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1280 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1281 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1282 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1283 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1284 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1285 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1286 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1287 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1288 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1289 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1290 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1291 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1292 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1293 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1294 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1295 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1296 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1297 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1298 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1299 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1300 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1301 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_top_in[2] ) , - .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( ropt_net_182 ) , - .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_137 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_top_in[6] ) , - .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_141 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_144 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_top_in[10] ) , - .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_146 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , - .HI ( optlc_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chany_top_in[14] ) , - .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chany_top_in[16] ) , - .X ( ropt_net_180 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_151 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , - .HI ( optlc_net_156 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_153 ( .LO ( SYNOPSYS_UNCONNECTED_7 ) , - .HI ( optlc_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_814 ( .A ( ropt_net_183 ) , - .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__clkbuf_1 \prog_clk[0]_bip420 ( .A ( prog_clk[0] ) , - .X ( ctsbuf_net_1159 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_792 ( .A ( ropt_net_160 ) , - .X ( ropt_net_184 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chany_bottom_in[5] ) , - .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chany_bottom_in[6] ) , - .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chany_bottom_in[8] ) , - .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_184 ) , - .X ( chany_top_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_345765 ( .A ( ctsbuf_net_1159 ) , - .X ( prog_clk__FEEDTHRU_1[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_816 ( .A ( ropt_net_185 ) , - .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( chany_top_in[18] ) , - .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chany_bottom_in[14] ) , - .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_25__24 ( .A ( chany_bottom_in[16] ) , - .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_817 ( .A ( ropt_net_186 ) , - .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_162 ) , - .X ( ropt_net_185 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_73 ( .A ( chany_top_in[4] ) , - .X ( BUF_net_73 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_818 ( .A ( ropt_net_187 ) , - .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_163 ) , - .X ( ropt_net_188 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_820 ( .A ( ropt_net_188 ) , - .X ( chanx_right_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_826 ( .A ( ropt_net_189 ) , - .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_827 ( .A ( ropt_net_190 ) , - .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_164 ) , - .X ( ropt_net_182 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( - .A ( right_bottom_grid_pin_41_[0] ) , .X ( ropt_net_191 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_166 ) , - .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_82 ( .A ( chany_bottom_in[10] ) , - .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_829 ( .A ( ropt_net_191 ) , - .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_192 ) , - .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_167 ) , - .X ( chany_bottom_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_168 ) , - .X ( chany_top_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_169 ) , - .X ( ropt_net_183 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_170 ) , - .X ( ropt_net_187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_803 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_192 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_193 ) , - .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_804 ( .A ( chany_top_in[17] ) , - .X ( ropt_net_193 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( .A ( ropt_net_173 ) , - .X ( ropt_net_190 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_113 ( .A ( chany_top_in[8] ) , - .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_117 ( .A ( BUF_net_73 ) , - .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_118 ( .A ( chany_bottom_in[2] ) , - .X ( ropt_net_189 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_128 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_162 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( chany_top_in[9] ) , - .X ( ropt_net_186 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_131 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_164 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_133 ( .A ( chany_bottom_in[13] ) , - .X ( ropt_net_170 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_134 ( .A ( chany_bottom_in[18] ) , - .X ( ropt_net_169 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_807 ( .A ( chany_top_in[12] ) , - .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_808 ( - .A ( chany_bottom_in[17] ) , .X ( chany_top_out[18] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_809 ( .A ( chany_bottom_in[4] ) , - .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_810 ( - .A ( chany_bottom_in[12] ) , .X ( chany_top_out[13] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_179 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_180 ) , - .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y0 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y0 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x36800y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x216200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x271400y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x266800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x322000y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x358800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x395600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x202400y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x248400y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x289800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x326600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x345000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x510600y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x92000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x101200y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x142600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x179400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x197800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x207000y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x322000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x340400y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x386400y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x432400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x598000y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x814200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x851000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x147200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x165600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x174800y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x220800y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x266800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x285200y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x363400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x464600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x524400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x722200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x731400y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x800400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x253000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x289800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x372600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x409400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x437000y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x552000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x570400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x731400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x768200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x777400y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x294400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x312800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x322000y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x478400y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x524400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x722200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x740600y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x892400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x910800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x147200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x239200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x478400y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x556600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x565800y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x611800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x621000y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x703800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x713000y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x832600y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x165600y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x211600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x230000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x280600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x299000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x349600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x409400y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x487600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x506000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x515200y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x533600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x584200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x602600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x726800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x892400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x910800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x147200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x156400y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x234600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x271400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x289800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x299000y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x354200y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x432400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x469200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x487600y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x565800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x584200y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x625600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x676200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x722200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x731400y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x809600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x828000y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x243800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x289800y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x335800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x409400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x418600y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x460000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x478400y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x556600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x575000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x584200y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x740600y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x782000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x791200y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x832600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x851000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x147200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x239200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x276000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x349600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x450800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x460000y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x506000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x524400y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x570400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x777400y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x823400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x860200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x147200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x156400y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x308200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x345000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x510600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x519800y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x565800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x575000y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x621000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x639400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x648600y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x694600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x805000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x823400y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x855600y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x110400y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x156400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x193200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x266800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x303600y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x349600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x418600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x437000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x446200y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x492200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x501400y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x547400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x584200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x602600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x685400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x731400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x749800y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x782000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x828000y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x73600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x82800y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x124200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x133400y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x211600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x220800y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x266800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x303600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x363400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x391000y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x469200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x506000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x542800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x602600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x621000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x630200y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x708400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x726800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x55200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x105800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x128800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x188600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x225400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x262200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x299000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x335800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x372600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x409400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x427800y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x469200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x487600y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x533600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x542800y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x588800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x598000y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x644000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x653200y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x699200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x749800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x805000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x92000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x101200y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x179400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x294400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x312800y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x358800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x464600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x483000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x492200y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x575000y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x653200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x731400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x740600y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x786600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x795800y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x837200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x855600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x892400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x910800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x133400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x170200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x207000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x243800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x262200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x345000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x381800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x400200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x450800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x460000y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x506000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x524400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x533600y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x611800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x630200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x639400y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x722200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x805000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x841800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x128800y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x207000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x243800y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x322000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x358800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x464600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x547400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x584200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x634800y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x680800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x690000y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x736000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x768200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x786600y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x832600y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x892400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x910800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x147200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x266800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x303600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x340400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x423200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x519800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x575000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x584200y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x828000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x837200y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x220800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x239200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x248400y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x289800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x326600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x335800y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x409400y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x455400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x492200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x501400y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x616400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x634800y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x676200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x763600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x855600y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x147200y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x225400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x243800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x331200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x381800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x418600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x455400y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x501400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x519800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x529000y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x575000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x593400y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x639400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x690000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x763600y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x809600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x828000y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x165600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x216200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x253000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x427800y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x473800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x492200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x501400y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x547400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x565800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x616400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x749800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x786600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x823400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x133400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x170200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x207000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x368000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x386400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x395600y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x473800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x483000y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x561200y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x639400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x676200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x713000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x731400y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x851000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x110400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x119600y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x161000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x197800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x207000y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x253000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x289800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x308200y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x354200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x409400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x418600y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x501400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x519800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x529000y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x611800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x703800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x722200y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x768200y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x892400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x910800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x184000y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x262200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x299000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x335800y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x414000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x450800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x469200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x478400y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x561200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x579600y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x625600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x644000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x653200y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x699200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x708400y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x754400y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x147200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x193200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x266800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x276000y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x354200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x427800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x487600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x496800y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x515200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x565800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x575000y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x657800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x708400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x717600y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x892400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x910800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x128800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x211600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x220800y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x266800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x303600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x340400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x450800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x469200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x519800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x529000y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x575000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x593400y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x772800y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x818800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x828000y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x147200y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x225400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x262200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x289800y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x335800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x409400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x418600y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x501400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x519800y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x653200y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x892400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x910800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x110400y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x151800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x188600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x266800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x303600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x312800y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x358800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x377200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x460000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x478400y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x524400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x542800y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x588800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x717600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x726800y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x128800y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x354200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x473800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x492200y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x575000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x584200y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x648600y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x763600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x800400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x147200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x197800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x234600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x285200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x303600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x312800y870400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x358800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x377200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x542800y870400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x708400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x828000y870400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y870400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x151800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x188600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x207000y897600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x285200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x303600y897600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x400200y897600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x515200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x680800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x699200y897600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x786600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x805000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x814200y897600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x892400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x910800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x188600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x225400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x262200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x331200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x423200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x460000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x478400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x529000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x565800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x616400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x625600y924800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x703800y924800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x749800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x786600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x823400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x860200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y924800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x73600y952000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x105800y952000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x193200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x230000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x294400y952000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x335800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x450800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x501400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x814200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x851000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y952000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y979200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x409400y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x55200y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x64400y1006400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x197800y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x234600y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x271400y1006400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x322000y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x340400y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x349600y1006400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x36800y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x220800y1033600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x271400y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x280600y1033600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y1060800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y1060800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__39 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__38 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__37 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__36 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__35 ( .A ( mem_out[1] ) , - .X ( net_aps_35 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_62 ( .A ( net_aps_35 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__34 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__33 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__32 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__31 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__30 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__29 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__28 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__27 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__26 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__25 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__24 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__23 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__22 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__21 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__20 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_41 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_40 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0_ ( prog_clk , chany_top_in , top_left_grid_pin_1_ , - chanx_right_in , right_bottom_grid_pin_1_ , right_bottom_grid_pin_3_ , - right_bottom_grid_pin_5_ , right_bottom_grid_pin_7_ , - right_bottom_grid_pin_9_ , right_bottom_grid_pin_11_ , ccff_head , - chany_top_out , chanx_right_out , ccff_tail , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:19] chany_top_in ; -input [0:0] top_left_grid_pin_1_ ; -input [0:19] chanx_right_in ; -input [0:0] right_bottom_grid_pin_1_ ; -input [0:0] right_bottom_grid_pin_3_ ; -input [0:0] right_bottom_grid_pin_5_ ; -input [0:0] right_bottom_grid_pin_7_ ; -input [0:0] right_bottom_grid_pin_9_ ; -input [0:0] right_bottom_grid_pin_11_ ; -input [0:0] ccff_head ; -output [0:19] chany_top_out ; -output [0:19] chanx_right_out ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; - -wire [0:2] mux_right_track_0_undriven_sram_inv ; -wire [0:1] mux_right_track_10_undriven_sram_inv ; -wire [0:1] mux_right_track_12_undriven_sram_inv ; -wire [0:1] mux_right_track_14_undriven_sram_inv ; -wire [0:1] mux_right_track_16_undriven_sram_inv ; -wire [0:1] mux_right_track_18_undriven_sram_inv ; -wire [0:1] mux_right_track_24_undriven_sram_inv ; -wire [0:1] mux_right_track_26_undriven_sram_inv ; -wire [0:1] mux_right_track_28_undriven_sram_inv ; -wire [0:2] mux_right_track_2_undriven_sram_inv ; -wire [0:1] mux_right_track_30_undriven_sram_inv ; -wire [0:1] mux_right_track_32_undriven_sram_inv ; -wire [0:1] mux_right_track_34_undriven_sram_inv ; -wire [0:2] mux_right_track_4_undriven_sram_inv ; -wire [0:2] mux_right_track_6_undriven_sram_inv ; -wire [0:1] mux_right_track_8_undriven_sram_inv ; -wire [0:1] mux_top_track_0_undriven_sram_inv ; -wire [0:1] mux_top_track_24_undriven_sram_inv ; -wire [0:1] mux_top_track_4_undriven_sram_inv ; -wire [0:1] mux_top_track_8_undriven_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_10_sram ; -wire [0:1] mux_tree_tapbuf_size2_11_sram ; -wire [0:1] mux_tree_tapbuf_size2_12_sram ; -wire [0:1] mux_tree_tapbuf_size2_13_sram ; -wire [0:1] mux_tree_tapbuf_size2_14_sram ; -wire [0:1] mux_tree_tapbuf_size2_15_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_5_sram ; -wire [0:1] mux_tree_tapbuf_size2_6_sram ; -wire [0:1] mux_tree_tapbuf_size2_7_sram ; -wire [0:1] mux_tree_tapbuf_size2_8_sram ; -wire [0:1] mux_tree_tapbuf_size2_9_sram ; -wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size4_0_sram ; -wire [0:2] mux_tree_tapbuf_size4_1_sram ; -wire [0:2] mux_tree_tapbuf_size4_2_sram ; -wire [0:2] mux_tree_tapbuf_size4_3_sram ; -wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; -supply1 VDD ; -supply0 VSS ; - -sb_0__0__mux_tree_tapbuf_size2_12 mux_top_track_0 ( - .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] } ) , - .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_top_track_0_undriven_sram_inv ) , - .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_80 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_14 mux_top_track_4 ( - .in ( { top_left_grid_pin_1_[0] , chanx_right_in[3] } ) , - .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_top_track_4_undriven_sram_inv ) , - .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_80 ) ) ; -sb_0__0__mux_tree_tapbuf_size2 mux_top_track_8 ( - .in ( { top_left_grid_pin_1_[0] , chanx_right_in[5] } ) , - .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_top_track_8_undriven_sram_inv ) , - .out ( chany_top_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_80 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_13 mux_top_track_24 ( - .in ( { top_left_grid_pin_1_[0] , chanx_right_in[13] } ) , - .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_top_track_24_undriven_sram_inv ) , - .out ( chany_top_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_81 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_11 mux_right_track_8 ( - .in ( { chany_top_in[3] , right_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_right_track_8_undriven_sram_inv ) , - .out ( { ropt_net_83 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_81 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_0 mux_right_track_10 ( - .in ( { chany_top_in[4] , right_bottom_grid_pin_3_[0] } ) , - .sram ( mux_tree_tapbuf_size2_5_sram ) , - .sram_inv ( mux_right_track_10_undriven_sram_inv ) , - .out ( chanx_right_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_81 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_1 mux_right_track_12 ( - .in ( { chany_top_in[5] , right_bottom_grid_pin_5_[0] } ) , - .sram ( mux_tree_tapbuf_size2_6_sram ) , - .sram_inv ( mux_right_track_12_undriven_sram_inv ) , - .out ( { ropt_net_84 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_78 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_2 mux_right_track_14 ( - .in ( { chany_top_in[6] , right_bottom_grid_pin_7_[0] } ) , - .sram ( mux_tree_tapbuf_size2_7_sram ) , - .sram_inv ( mux_right_track_14_undriven_sram_inv ) , - .out ( chanx_right_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_78 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_3 mux_right_track_16 ( - .in ( { chany_top_in[7] , right_bottom_grid_pin_9_[0] } ) , - .sram ( mux_tree_tapbuf_size2_8_sram ) , - .sram_inv ( mux_right_track_16_undriven_sram_inv ) , - .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_78 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_4 mux_right_track_18 ( - .in ( { chany_top_in[8] , right_bottom_grid_pin_11_[0] } ) , - .sram ( mux_tree_tapbuf_size2_9_sram ) , - .sram_inv ( mux_right_track_18_undriven_sram_inv ) , - .out ( chanx_right_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_81 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_5 mux_right_track_24 ( - .in ( { chany_top_in[11] , right_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size2_10_sram ) , - .sram_inv ( mux_right_track_24_undriven_sram_inv ) , - .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_79 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_6 mux_right_track_26 ( - .in ( { chany_top_in[12] , right_bottom_grid_pin_3_[0] } ) , - .sram ( mux_tree_tapbuf_size2_11_sram ) , - .sram_inv ( mux_right_track_26_undriven_sram_inv ) , - .out ( chanx_right_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_79 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_7 mux_right_track_28 ( - .in ( { chany_top_in[13] , right_bottom_grid_pin_5_[0] } ) , - .sram ( mux_tree_tapbuf_size2_12_sram ) , - .sram_inv ( mux_right_track_28_undriven_sram_inv ) , - .out ( chanx_right_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_79 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_8 mux_right_track_30 ( - .in ( { chany_top_in[14] , right_bottom_grid_pin_7_[0] } ) , - .sram ( mux_tree_tapbuf_size2_13_sram ) , - .sram_inv ( mux_right_track_30_undriven_sram_inv ) , - .out ( chanx_right_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_78 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_9 mux_right_track_32 ( - .in ( { chany_top_in[15] , right_bottom_grid_pin_9_[0] } ) , - .sram ( mux_tree_tapbuf_size2_14_sram ) , - .sram_inv ( mux_right_track_32_undriven_sram_inv ) , - .out ( chanx_right_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_78 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_10 mux_right_track_34 ( - .in ( { chany_top_in[16] , right_bottom_grid_pin_11_[0] } ) , - .sram ( mux_tree_tapbuf_size2_15_sram ) , - .sram_inv ( mux_right_track_34_undriven_sram_inv ) , - .out ( chanx_right_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_78 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_12 mem_top_track_0 ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_14 mem_top_track_4 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_13 mem_top_track_24 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_11 mem_right_track_8 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_0 mem_right_track_10 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_1 mem_right_track_12 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_2 mem_right_track_14 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_3 mem_right_track_16 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_8_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_4 mem_right_track_18 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_9_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_5 mem_right_track_24 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_10_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_6 mem_right_track_26 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_11_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_7 mem_right_track_28 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_12_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_8 mem_right_track_30 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_13_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_9 mem_right_track_32 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_14_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_10 mem_right_track_34 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .ccff_tail ( { ropt_net_85 } ) , - .mem_out ( mux_tree_tapbuf_size2_15_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__0__mux_tree_tapbuf_size4_0 mux_right_track_0 ( - .in ( { chany_top_in[19] , right_bottom_grid_pin_1_[0] , - right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] } ) , - .sram ( mux_tree_tapbuf_size4_0_sram ) , - .sram_inv ( mux_right_track_0_undriven_sram_inv ) , - .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_78 ) ) ; -sb_0__0__mux_tree_tapbuf_size4_1 mux_right_track_2 ( - .in ( { chany_top_in[0] , right_bottom_grid_pin_3_[0] , - right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_11_[0] } ) , - .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_right_track_2_undriven_sram_inv ) , - .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_79 ) ) ; -sb_0__0__mux_tree_tapbuf_size4_2 mux_right_track_4 ( - .in ( { chany_top_in[1] , right_bottom_grid_pin_1_[0] , - right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] } ) , - .sram ( mux_tree_tapbuf_size4_2_sram ) , - .sram_inv ( mux_right_track_4_undriven_sram_inv ) , - .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_79 ) ) ; -sb_0__0__mux_tree_tapbuf_size4 mux_right_track_6 ( - .in ( { chany_top_in[2] , right_bottom_grid_pin_3_[0] , - right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_11_[0] } ) , - .sram ( mux_tree_tapbuf_size4_3_sram ) , - .sram_inv ( mux_right_track_6_undriven_sram_inv ) , - .out ( chanx_right_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_79 ) ) ; -sb_0__0__mux_tree_tapbuf_size4_mem_0 mem_right_track_0 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__0__mux_tree_tapbuf_size4_mem_1 mem_right_track_2 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__0__mux_tree_tapbuf_size4_mem_2 mem_right_track_4 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__0__mux_tree_tapbuf_size4_mem mem_right_track_6 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1227 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1228 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1229 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1230 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1231 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1232 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1233 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1234 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1235 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1236 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1237 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1238 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1239 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1240 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1241 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1242 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1243 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1244 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1245 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1246 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1247 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1248 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1249 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1250 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1251 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1252 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1253 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1254 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1255 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1256 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1257 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1258 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1259 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1260 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1261 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1262 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__0 ( .A ( chany_top_in[9] ) , - .X ( ropt_net_94 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_76 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_78 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_78 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_79 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_80 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_80 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chanx_right_in[0] ) , - .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_82 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_81 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_685 ( .A ( ropt_net_83 ) , - .X ( chanx_right_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_686 ( .A ( ropt_net_84 ) , - .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_687 ( .A ( ropt_net_85 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_688 ( .A ( chany_top_in[18] ) , - .X ( ropt_net_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_689 ( .A ( chanx_right_in[6] ) , - .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_690 ( .A ( chanx_right_in[15] ) , - .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_691 ( .A ( chanx_right_in[18] ) , - .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_692 ( .A ( ropt_net_90 ) , - .X ( ropt_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chanx_right_in[14] ) , - .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_693 ( .A ( ropt_net_91 ) , - .X ( ropt_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_694 ( .A ( ropt_net_92 ) , - .X ( ropt_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_695 ( .A ( ropt_net_93 ) , - .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_696 ( .A ( ropt_net_94 ) , - .X ( ropt_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_697 ( .A ( ropt_net_98 ) , - .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_46 ( .A ( chany_top_in[17] ) , - .X ( ropt_net_91 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_698 ( .A ( ropt_net_99 ) , - .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_48 ( .A ( chanx_right_in[2] ) , - .X ( chany_top_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_49 ( .A ( chanx_right_in[4] ) , - .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_699 ( .A ( ropt_net_100 ) , - .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_51 ( .A ( chanx_right_in[7] ) , - .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_52 ( .A ( chanx_right_in[8] ) , - .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_53 ( .A ( chanx_right_in[9] ) , - .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_54 ( .A ( chanx_right_in[10] ) , - .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_55 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_56 ( .A ( chanx_right_in[12] ) , - .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_700 ( .A ( ropt_net_101 ) , - .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_58 ( .A ( chanx_right_in[16] ) , - .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_59 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_90 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_701 ( .A ( ropt_net_102 ) , - .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_61 ( .A ( chanx_right_in[19] ) , - .X ( ropt_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_702 ( .A ( ropt_net_103 ) , - .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_67 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_93 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y0 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y0 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x220800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x322000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x358800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x846400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x864800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x331200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x349600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x358800y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; 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.VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y136000 ( - .VGND ( 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.VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x846400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x864800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x846400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x864800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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.VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x754400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x791200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x828000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x892400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x910800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x368000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x386400y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x823400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x860200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x538200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x731400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x768200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x805000y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x892400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x910800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x368000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x460000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x496800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x515200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x565800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x602600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x639400y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x749800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x786600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x805000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x427800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x529000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x639400y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x754400y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x892400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x910800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x147200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x165600y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x501400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x519800y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x561200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x570400y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x717600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x800400y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x349600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x391000y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x437000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x455400y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x533600y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x648600y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x763600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x828000y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x860200y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x892400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x910800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x331200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x349600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x395600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x473800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x561200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x611800y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x657800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x791200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x800400y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x846400y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x147200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x165600y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x211600y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x257600y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x303600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x312800y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x358800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x432400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x515200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x524400y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x570400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x630200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x680800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x731400y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x777400y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x823400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x874000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x910800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x220800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x303600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x340400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x377200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x414000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x584200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x621000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x754400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x791200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x128800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x211600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x248400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x322000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x358800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x501400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x552000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x561200y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x639400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x657800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x667000y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x892400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x910800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x248400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x395600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x414000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x496800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x607200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x616400y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x128800y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x207000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x243800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x326600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x363400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x409400y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x487600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x496800y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x616400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x653200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x690000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x892400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x910800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x147200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x207000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x243800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x749800y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x464600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x483000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x529000y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x616400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x809600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x828000y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x878600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x92000y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x133400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x170200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x207000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x216200y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x368000y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x414000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x184000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x193200y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x271400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x308200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x345000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x391000y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x510600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x529000y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x570400y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x690000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x708400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x717600y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x795800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x814200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x823400y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x855600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x892400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x910800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x331200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x340400y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x496800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x570400y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x680800y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x763600y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x805000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x841800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x184000y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x266800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x285200y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x335800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x464600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x846400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x864800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y870400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x124200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x161000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x197800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x234600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x271400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x308200y870400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x386400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x616400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x147200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x165600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x220800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x276000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x340400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y897600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x391000y897600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x464600y897600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x138000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x174800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y952000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y952000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_mem_23 ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_40__57 ( .A ( mem_out[1] ) , - .X ( net_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_110 ( .A ( net_net_110 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_mem_22 ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_39__56 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_mem_21 ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_38__55 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_23 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_22 ( in , sram , sram_inv , out , VDD , VSS , - p_abuf0 , p_abuf1 , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -output p_abuf0 ; -output p_abuf1 ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf1 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_92 ( .A ( p_abuf1 ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_93 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_21 ( in , sram , sram_inv , out , VDD , VSS , - p_abuf0 , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -output p_abuf0 ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_91 ( .A ( out[0] ) , .X ( p_abuf0 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff ( - Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk , VDD , VSS , p_abuf0 , - p_abuf1 , p_abuf2 ) ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:0] ff_D ; -input [0:0] ff_DI ; -output [0:0] ff_Q ; -input [0:0] ff_clk ; -input VDD ; -input VSS ; -output p_abuf0 ; -output p_abuf1 ; -output p_abuf2 ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , - .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( p_abuf2 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_58 ( .A ( p_abuf2 ) , .X ( ff_Q[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_60 ( .A ( p_abuf2 ) , .X ( p_abuf1 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_130 ( .A ( p_abuf2 ) , .X ( p_abuf0 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_14 ( - Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk , VDD , VSS ) ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:0] ff_D ; -input [0:0] ff_DI ; -output [0:0] ff_Q ; -input [0:0] ff_clk ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , - .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_37__54 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_mux_tree_size2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem ( prog_clk , - ccff_head , ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:16] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_5_ ( .D ( mem_out[4] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_6_ ( .D ( mem_out[5] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_7_ ( .D ( mem_out[6] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_8_ ( .D ( mem_out[7] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_9_ ( .D ( mem_out[8] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_10_ ( .D ( mem_out[9] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_11_ ( .D ( mem_out[10] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_12_ ( .D ( mem_out[11] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_13_ ( .D ( mem_out[12] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_14_ ( .D ( mem_out[13] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_15_ ( .D ( mem_out[14] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_16_ ( .D ( mem_out[15] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_36__53 ( .A ( mem_out[16] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_frac_lut4_mux ( in , sram , sram_inv , lut3_out , lut4_out , - VDD , VSS ) ; -input [0:15] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:1] lut3_out ; -output [0:0] lut4_out ; -input VDD ; -input VSS ; - -wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_4_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_5_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( - .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( - .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( - .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( - .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_6_ ( - .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__buf_2_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__buf_2_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__buf_2_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_frac_lut4 ( in , sram , sram_inv , mode , mode_inv , - lut3_out , lut4_out , VDD , VSS ) ; -input [0:3] in ; -input [0:15] sram ; -input [0:15] sram_inv ; -input [0:0] mode ; -input [0:0] mode_inv ; -output [0:1] lut3_out ; -output [0:0] lut4_out ; -input VDD ; -input VSS ; - -wire [0:0] sky130_fd_sc_hd__buf_2_0_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_1_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_2_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; -wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ; -wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ; -wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ; -wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ; -wire [0:0] sky130_fd_sc_hd__or2_1_0_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , - .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , - .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , - .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , - .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( - .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , - .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , - .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , - .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , - .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( - .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -grid_clb_frac_lut4_mux frac_lut4_mux_0_ ( .in ( sram ) , - .sram ( { sky130_fd_sc_hd__buf_2_0_X[0] , sky130_fd_sc_hd__buf_2_1_X[0] , - sky130_fd_sc_hd__buf_2_2_X[0] , sky130_fd_sc_hd__buf_2_3_X[0] } ) , - .sram_inv ( { sky130_fd_sc_hd__inv_1_0_Y[0] , - sky130_fd_sc_hd__inv_1_1_Y[0] , sky130_fd_sc_hd__inv_1_2_Y[0] , - sky130_fd_sc_hd__inv_1_3_Y[0] } ) , - .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4 ( - prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out , - frac_lut4_lut4_out , ccff_tail , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:3] frac_lut4_in ; -input [0:0] ccff_head ; -output [0:1] frac_lut4_lut3_out ; -output [0:0] frac_lut4_lut4_out ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; - -wire [0:15] frac_lut4_0__undriven_sram_inv ; -wire [0:0] frac_lut4_0_mode ; -wire [0:15] frac_lut4_0_sram ; -supply1 VDD ; -supply0 VSS ; - -grid_clb_frac_lut4 frac_lut4_0_ ( .in ( frac_lut4_in ) , - .sram ( frac_lut4_0_sram ) , - .sram_inv ( frac_lut4_0__undriven_sram_inv ) , - .mode ( frac_lut4_0_mode ) , - .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , - .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , - .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , - frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] , - frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , - frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , - frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , - frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic ( - prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , VDD , - VSS , p0 ) ; -input [0:0] prog_clk ; -input [0:3] frac_logic_in ; -input [0:0] ccff_head ; -output [0:1] frac_logic_out ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; -wire [0:1] mux_frac_logic_out_0_undriven_sram_inv ; -wire [0:1] mux_tree_size2_0_sram ; -supply1 VDD ; -supply0 VSS ; - -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( - .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , - .ccff_head ( ccff_head ) , - .frac_lut4_lut3_out ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] , - frac_logic_out[1] } ) , - - .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , - .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -grid_clb_mux_tree_size2 mux_frac_logic_out_0 ( - .in ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] - } ) , - .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_frac_logic_out_0_undriven_sram_inv ) , - .out ( frac_logic_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -grid_clb_mux_tree_size2_mem mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -grid_clb_direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( frac_logic_out[1] ) ) ; -grid_clb_direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( frac_logic_in[0] ) ) ; -grid_clb_direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( frac_logic_in[1] ) ) ; -grid_clb_direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( frac_logic_in[2] ) ) ; -grid_clb_direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( frac_logic_in[3] ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric ( - prog_clk , Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , - fabric_clk , ccff_head , fabric_out , fabric_regout , fabric_sc_out , - ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , p_abuf2 , p_abuf3 , p_abuf5 , - p_abuf6 , p0 ) ; -input [0:0] prog_clk ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:3] fabric_in ; -input [0:0] fabric_regin ; -input [0:0] fabric_sc_in ; -input [0:0] fabric_clk ; -input [0:0] ccff_head ; -output [0:1] fabric_out ; -output [0:0] fabric_regout ; -output [0:0] fabric_sc_out ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; -output p_abuf0 ; -output p_abuf1 ; -output p_abuf2 ; -output p_abuf3 ; -output p_abuf5 ; -output p_abuf6 ; -input p0 ; - -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; -wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; -wire [0:1] mux_fabric_out_0_undriven_sram_inv ; -wire [0:1] mux_fabric_out_1_undriven_sram_inv ; -wire [0:1] mux_ff_0_D_0_undriven_sram_inv ; -wire [0:1] mux_tree_size2_0_sram ; -wire [0:1] mux_tree_size2_1_sram ; -wire [0:0] mux_tree_size2_2_out ; -wire [0:1] mux_tree_size2_2_sram ; -wire [0:0] mux_tree_size2_mem_0_ccff_tail ; -wire [0:0] mux_tree_size2_mem_1_ccff_tail ; -supply1 VDD ; -supply0 VSS ; - -assign p_abuf1 = p_abuf2 ; - -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( - .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , - .ccff_head ( ccff_head ) , - .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , - .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_14 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( - .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , - .ff_DI ( fabric_sc_in ) , - .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , - .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( - .Test_en ( Test_en ) , .clk ( clk ) , - .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , - .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , - .ff_Q ( fabric_sc_out ) , - .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( fabric_regout[0] ) , - .p_abuf1 ( p_abuf0 ) , .p_abuf2 ( p_abuf2 ) ) ; -grid_clb_mux_tree_size2_21 mux_fabric_out_0 ( - .in ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] - } ) , - .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_fabric_out_0_undriven_sram_inv ) , - .out ( fabric_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf0 ( p_abuf3 ) , .p0 ( p0 ) ) ; -grid_clb_mux_tree_size2_22 mux_fabric_out_1 ( - .in ( { fabric_sc_out[0] , - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] - } ) , - .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( mux_fabric_out_1_undriven_sram_inv ) , - .out ( fabric_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf0 ( p_abuf5 ) , .p_abuf1 ( p_abuf6 ) , .p0 ( p0 ) ) ; -grid_clb_mux_tree_size2_23 mux_ff_0_D_0 ( - .in ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , - fabric_regin[0] } ) , - .sram ( mux_tree_size2_2_sram ) , - .sram_inv ( mux_ff_0_D_0_undriven_sram_inv ) , - .out ( mux_tree_size2_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -grid_clb_mux_tree_size2_mem_21 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -grid_clb_mux_tree_size2_mem_22 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_size2_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -grid_clb_mux_tree_size2_mem_23 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , - .mem_out ( mux_tree_size2_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -grid_clb_direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( { p_abuf2 } ) ) ; -grid_clb_direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( { p_abuf2 } ) ) ; -grid_clb_direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( fabric_in[0] ) ) ; -grid_clb_direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_6 } ) , - .out ( fabric_in[1] ) ) ; -grid_clb_direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_7 } ) , - .out ( fabric_in[2] ) ) ; -grid_clb_direct_interc direct_interc_5_ ( - .in ( { SYNOPSYS_UNCONNECTED_8 } ) , - .out ( fabric_in[3] ) ) ; -grid_clb_direct_interc direct_interc_6_ ( - .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( fabric_sc_in ) ) ; -grid_clb_direct_interc direct_interc_7_ ( - .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( fabric_clk ) ) ; -grid_clb_direct_interc direct_interc_8_ ( - .in ( { SYNOPSYS_UNCONNECTED_11 } ) , - - .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) ) ; -grid_clb_direct_interc direct_interc_9_ ( - .in ( { SYNOPSYS_UNCONNECTED_12 } ) , - - .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ) ; -grid_clb_direct_interc direct_interc_10_ ( - .in ( { SYNOPSYS_UNCONNECTED_13 } ) , - .out ( fabric_clk ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle ( prog_clk , Test_en , - clk , fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , - fle_regout , fle_sc_out , ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , - p_abuf2 , p_abuf3 , p_abuf5 , p_abuf6 , p0 ) ; -input [0:0] prog_clk ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:3] fle_in ; -input [0:0] fle_regin ; -input [0:0] fle_sc_in ; -input [0:0] fle_clk ; -input [0:0] ccff_head ; -output [0:1] fle_out ; -output [0:0] fle_regout ; -output [0:0] fle_sc_out ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; -output p_abuf0 ; -output p_abuf1 ; -output p_abuf2 ; -output p_abuf3 ; -output p_abuf5 ; -output p_abuf6 ; -input p0 ; - -supply1 VDD ; -supply0 VSS ; - -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( - .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , - .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , - .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , - .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , - .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p_abuf2 ( p_abuf2 ) , - .p_abuf3 ( p_abuf3 ) , .p_abuf5 ( p_abuf5 ) , .p_abuf6 ( p_abuf6 ) , - .p0 ( p0 ) ) ; -grid_clb_direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( { p_abuf6 } ) ) ; -grid_clb_direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( { p_abuf1 } ) ) ; -grid_clb_direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( { p_abuf2 } ) ) ; -grid_clb_direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fle_in[0] ) ) ; -grid_clb_direct_interc direct_interc_5_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( fle_in[1] ) ) ; -grid_clb_direct_interc direct_interc_6_ ( - .in ( { SYNOPSYS_UNCONNECTED_6 } ) , - .out ( fle_in[2] ) ) ; -grid_clb_direct_interc direct_interc_7_ ( - .in ( { SYNOPSYS_UNCONNECTED_7 } ) , - .out ( fle_in[3] ) ) ; -grid_clb_direct_interc direct_interc_8_ ( - .in ( { SYNOPSYS_UNCONNECTED_8 } ) , - .out ( fle_regin ) ) ; -grid_clb_direct_interc direct_interc_9_ ( - .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( fle_sc_in ) ) ; -grid_clb_direct_interc direct_interc_10_ ( - .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( fle_clk ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_mem_20 ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_35__52 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_mem_19 ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_34__51 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_mem_18 ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__50 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_20 ( in , sram , sram_inv , out , VDD , VSS , - p3 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p3 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_19 ( in , sram , sram_inv , out , VDD , VSS , - p_abuf0 , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -output p_abuf0 ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_124 ( .A ( BUF_net_89 ) , - .X ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_89 ( .A ( out[0] ) , - .X ( BUF_net_89 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_18 ( in , sram , sram_inv , out , VDD , VSS , - p_abuf0 , p_abuf1 , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -output p_abuf0 ; -output p_abuf1 ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf1 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_86 ( .A ( p_abuf1 ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_87 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_13 ( - Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk , VDD , VSS ) ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:0] ff_D ; -input [0:0] ff_DI ; -output [0:0] ff_Q ; -input [0:0] ff_clk ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , - .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_12 ( - Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk , VDD , VSS ) ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:0] ff_D ; -input [0:0] ff_DI ; -output [0:0] ff_Q ; -input [0:0] ff_clk ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , - .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_mem_30 ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_32__49 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_30 ( in , sram , sram_inv , out , VDD , VSS , - p3 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p3 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_6 ( prog_clk , - ccff_head , ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:16] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_5_ ( .D ( mem_out[4] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_6_ ( .D ( mem_out[5] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_7_ ( .D ( mem_out[6] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_8_ ( .D ( mem_out[7] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_9_ ( .D ( mem_out[8] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_10_ ( .D ( mem_out[9] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_11_ ( .D ( mem_out[10] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_12_ ( .D ( mem_out[11] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_13_ ( .D ( mem_out[12] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_14_ ( .D ( mem_out[13] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_15_ ( .D ( mem_out[14] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_16_ ( .D ( mem_out[15] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__48 ( .A ( mem_out[16] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_frac_lut4_mux_6 ( in , sram , sram_inv , lut3_out , lut4_out , - VDD , VSS ) ; -input [0:15] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:1] lut3_out ; -output [0:0] lut4_out ; -input VDD ; -input VSS ; - -wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_4_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_5_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( - .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( - .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( - .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( - .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_6_ ( - .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__buf_2_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__buf_2_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__buf_2_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_frac_lut4_6 ( in , sram , sram_inv , mode , mode_inv , - lut3_out , lut4_out , VDD , VSS ) ; -input [0:3] in ; -input [0:15] sram ; -input [0:15] sram_inv ; -input [0:0] mode ; -input [0:0] mode_inv ; -output [0:1] lut3_out ; -output [0:0] lut4_out ; -input VDD ; -input VSS ; - -wire [0:0] sky130_fd_sc_hd__buf_2_0_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_1_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_2_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; -wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ; -wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ; -wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ; -wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ; -wire [0:0] sky130_fd_sc_hd__or2_1_0_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , - .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , - .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , - .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , - .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( - .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , - .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , - .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , - .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , - .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( - .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -grid_clb_frac_lut4_mux_6 frac_lut4_mux_0_ ( .in ( sram ) , - .sram ( { sky130_fd_sc_hd__buf_2_0_X[0] , sky130_fd_sc_hd__buf_2_1_X[0] , - sky130_fd_sc_hd__buf_2_2_X[0] , sky130_fd_sc_hd__buf_2_3_X[0] } ) , - .sram_inv ( { sky130_fd_sc_hd__inv_1_0_Y[0] , - sky130_fd_sc_hd__inv_1_1_Y[0] , sky130_fd_sc_hd__inv_1_2_Y[0] , - sky130_fd_sc_hd__inv_1_3_Y[0] } ) , - .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_6 ( - prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out , - frac_lut4_lut4_out , ccff_tail , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:3] frac_lut4_in ; -input [0:0] ccff_head ; -output [0:1] frac_lut4_lut3_out ; -output [0:0] frac_lut4_lut4_out ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; - -wire [0:15] frac_lut4_0__undriven_sram_inv ; -wire [0:0] frac_lut4_0_mode ; -wire [0:15] frac_lut4_0_sram ; -supply1 VDD ; -supply0 VSS ; - -grid_clb_frac_lut4_6 frac_lut4_0_ ( .in ( frac_lut4_in ) , - .sram ( frac_lut4_0_sram ) , - .sram_inv ( frac_lut4_0__undriven_sram_inv ) , - .mode ( frac_lut4_0_mode ) , - .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , - .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_6 frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , - .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , - frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] , - frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , - frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , - frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , - frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_6 ( - prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , VDD , - VSS , p3 ) ; -input [0:0] prog_clk ; -input [0:3] frac_logic_in ; -input [0:0] ccff_head ; -output [0:1] frac_logic_out ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; -input p3 ; - -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; -wire [0:1] mux_frac_logic_out_0_undriven_sram_inv ; -wire [0:1] mux_tree_size2_0_sram ; -supply1 VDD ; -supply0 VSS ; - -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( - .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , - .ccff_head ( ccff_head ) , - .frac_lut4_lut3_out ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] , - frac_logic_out[1] } ) , - - .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , - .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -grid_clb_mux_tree_size2_30 mux_frac_logic_out_0 ( - .in ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] - } ) , - .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_frac_logic_out_0_undriven_sram_inv ) , - .out ( frac_logic_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p3 ( p3 ) ) ; -grid_clb_mux_tree_size2_mem_30 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -grid_clb_direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( frac_logic_out[1] ) ) ; -grid_clb_direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( frac_logic_in[0] ) ) ; -grid_clb_direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( frac_logic_in[1] ) ) ; -grid_clb_direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( frac_logic_in[2] ) ) ; -grid_clb_direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( frac_logic_in[3] ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_6 ( - prog_clk , Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , - fabric_clk , ccff_head , fabric_out , fabric_regout , fabric_sc_out , - ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , p_abuf2 , p0 , p3 ) ; -input [0:0] prog_clk ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:3] fabric_in ; -input [0:0] fabric_regin ; -input [0:0] fabric_sc_in ; -input [0:0] fabric_clk ; -input [0:0] ccff_head ; -output [0:1] fabric_out ; -output [0:0] fabric_regout ; -output [0:0] fabric_sc_out ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; -output p_abuf0 ; -output p_abuf1 ; -output p_abuf2 ; -input p0 ; -input p3 ; - -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; -wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; -wire [0:1] mux_fabric_out_0_undriven_sram_inv ; -wire [0:1] mux_fabric_out_1_undriven_sram_inv ; -wire [0:1] mux_ff_0_D_0_undriven_sram_inv ; -wire [0:1] mux_tree_size2_0_sram ; -wire [0:1] mux_tree_size2_1_sram ; -wire [0:0] mux_tree_size2_2_out ; -wire [0:1] mux_tree_size2_2_sram ; -wire [0:0] mux_tree_size2_mem_0_ccff_tail ; -wire [0:0] mux_tree_size2_mem_1_ccff_tail ; -supply1 VDD ; -supply0 VSS ; - -assign fabric_regout[0] = fabric_sc_out[0] ; - -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( - .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , - .ccff_head ( ccff_head ) , - .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , - .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p3 ( p3 ) ) ; -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_12 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( - .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , - .ff_DI ( fabric_sc_in ) , - .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , - .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_13 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( - .Test_en ( Test_en ) , .clk ( clk ) , - .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , - .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , - .ff_Q ( fabric_sc_out ) , - .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -grid_clb_mux_tree_size2_18 mux_fabric_out_0 ( - .in ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] - } ) , - .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_fabric_out_0_undriven_sram_inv ) , - .out ( fabric_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p0 ( p0 ) ) ; -grid_clb_mux_tree_size2_19 mux_fabric_out_1 ( - .in ( { fabric_sc_out[0] , - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] - } ) , - .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( mux_fabric_out_1_undriven_sram_inv ) , - .out ( fabric_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf0 ( p_abuf2 ) , .p0 ( p0 ) ) ; -grid_clb_mux_tree_size2_20 mux_ff_0_D_0 ( - .in ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , - fabric_regin[0] } ) , - .sram ( mux_tree_size2_2_sram ) , - .sram_inv ( mux_ff_0_D_0_undriven_sram_inv ) , - .out ( mux_tree_size2_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p3 ( p3 ) ) ; -grid_clb_mux_tree_size2_mem_18 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -grid_clb_mux_tree_size2_mem_19 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_size2_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -grid_clb_mux_tree_size2_mem_20 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , - .mem_out ( mux_tree_size2_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -grid_clb_direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fabric_sc_out ) ) ; -grid_clb_direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fabric_sc_out ) ) ; -grid_clb_direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( fabric_in[0] ) ) ; -grid_clb_direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_6 } ) , - .out ( fabric_in[1] ) ) ; -grid_clb_direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_7 } ) , - .out ( fabric_in[2] ) ) ; -grid_clb_direct_interc direct_interc_5_ ( - .in ( { SYNOPSYS_UNCONNECTED_8 } ) , - .out ( fabric_in[3] ) ) ; -grid_clb_direct_interc direct_interc_6_ ( - .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( fabric_sc_in ) ) ; -grid_clb_direct_interc direct_interc_7_ ( - .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( fabric_clk ) ) ; -grid_clb_direct_interc direct_interc_8_ ( - .in ( { SYNOPSYS_UNCONNECTED_11 } ) , - - .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) ) ; -grid_clb_direct_interc direct_interc_9_ ( - .in ( { SYNOPSYS_UNCONNECTED_12 } ) , - - .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ) ; -grid_clb_direct_interc direct_interc_10_ ( - .in ( { SYNOPSYS_UNCONNECTED_13 } ) , - .out ( fabric_clk ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_6 ( prog_clk , Test_en , - clk , fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , - fle_regout , fle_sc_out , ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , - p_abuf2 , p0 , p3 ) ; -input [0:0] prog_clk ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:3] fle_in ; -input [0:0] fle_regin ; -input [0:0] fle_sc_in ; -input [0:0] fle_clk ; -input [0:0] ccff_head ; -output [0:1] fle_out ; -output [0:0] fle_regout ; -output [0:0] fle_sc_out ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; -output p_abuf0 ; -output p_abuf1 ; -output p_abuf2 ; -input p0 ; -input p3 ; - -supply1 VDD ; -supply0 VSS ; - -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( - .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , - .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , - .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , - .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , - .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p_abuf2 ( p_abuf2 ) , - .p0 ( p0 ) , .p3 ( p3 ) ) ; -grid_clb_direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( { p_abuf1 } ) ) ; -grid_clb_direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( fle_regout ) ) ; -grid_clb_direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fle_sc_out ) ) ; -grid_clb_direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fle_in[0] ) ) ; -grid_clb_direct_interc direct_interc_5_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( fle_in[1] ) ) ; -grid_clb_direct_interc direct_interc_6_ ( - .in ( { SYNOPSYS_UNCONNECTED_6 } ) , - .out ( fle_in[2] ) ) ; -grid_clb_direct_interc direct_interc_7_ ( - .in ( { SYNOPSYS_UNCONNECTED_7 } ) , - .out ( fle_in[3] ) ) ; -grid_clb_direct_interc direct_interc_8_ ( - .in ( { SYNOPSYS_UNCONNECTED_8 } ) , - .out ( fle_regin ) ) ; -grid_clb_direct_interc direct_interc_9_ ( - .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( fle_sc_in ) ) ; -grid_clb_direct_interc direct_interc_10_ ( - .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( fle_clk ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_mem_17 ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__47 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_mem_16 ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__46 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_mem_15 ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_28__45 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_17 ( in , sram , sram_inv , out , VDD , VSS , - p3 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p3 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_16 ( in , sram , sram_inv , out , VDD , VSS , - p_abuf0 , p3 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -output p_abuf0 ; -input p3 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_123 ( .A ( out[0] ) , .X ( p_abuf0 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_15 ( in , sram , sram_inv , out , VDD , VSS , - p_abuf0 , p_abuf1 , p3 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -output p_abuf0 ; -output p_abuf1 ; -input p3 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf1 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_82 ( .A ( p_abuf1 ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_83 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_11 ( - Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk , VDD , VSS ) ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:0] ff_D ; -input [0:0] ff_DI ; -output [0:0] ff_Q ; -input [0:0] ff_clk ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , - .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_10 ( - Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk , VDD , VSS ) ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:0] ff_D ; -input [0:0] ff_DI ; -output [0:0] ff_Q ; -input [0:0] ff_clk ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , - .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_mem_29 ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_27__44 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_29 ( in , sram , sram_inv , out , VDD , VSS , - p3 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p3 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_5 ( prog_clk , - ccff_head , ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:16] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_5_ ( .D ( mem_out[4] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_6_ ( .D ( mem_out[5] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_7_ ( .D ( mem_out[6] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_8_ ( .D ( mem_out[7] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_9_ ( .D ( mem_out[8] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_10_ ( .D ( mem_out[9] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_11_ ( .D ( mem_out[10] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_12_ ( .D ( mem_out[11] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_13_ ( .D ( mem_out[12] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_14_ ( .D ( mem_out[13] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_15_ ( .D ( mem_out[14] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_16_ ( .D ( mem_out[15] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_26__43 ( .A ( mem_out[16] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_frac_lut4_mux_5 ( in , sram , sram_inv , lut3_out , lut4_out , - VDD , VSS ) ; -input [0:15] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:1] lut3_out ; -output [0:0] lut4_out ; -input VDD ; -input VSS ; - -wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_4_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_5_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( - .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( - .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( - .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( - .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_6_ ( - .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__buf_2_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__buf_2_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__buf_2_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_frac_lut4_5 ( in , sram , sram_inv , mode , mode_inv , - lut3_out , lut4_out , VDD , VSS ) ; -input [0:3] in ; -input [0:15] sram ; -input [0:15] sram_inv ; -input [0:0] mode ; -input [0:0] mode_inv ; -output [0:1] lut3_out ; -output [0:0] lut4_out ; -input VDD ; -input VSS ; - -wire [0:0] sky130_fd_sc_hd__buf_2_0_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_1_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_2_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; -wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ; -wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ; -wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ; -wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ; -wire [0:0] sky130_fd_sc_hd__or2_1_0_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , - .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , - .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , - .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , - .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( - .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , - .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , - .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , - .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , - .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( - .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -grid_clb_frac_lut4_mux_5 frac_lut4_mux_0_ ( .in ( sram ) , - .sram ( { sky130_fd_sc_hd__buf_2_0_X[0] , sky130_fd_sc_hd__buf_2_1_X[0] , - sky130_fd_sc_hd__buf_2_2_X[0] , sky130_fd_sc_hd__buf_2_3_X[0] } ) , - .sram_inv ( { sky130_fd_sc_hd__inv_1_0_Y[0] , - sky130_fd_sc_hd__inv_1_1_Y[0] , sky130_fd_sc_hd__inv_1_2_Y[0] , - sky130_fd_sc_hd__inv_1_3_Y[0] } ) , - .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_5 ( - prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out , - frac_lut4_lut4_out , ccff_tail , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:3] frac_lut4_in ; -input [0:0] ccff_head ; -output [0:1] frac_lut4_lut3_out ; -output [0:0] frac_lut4_lut4_out ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; - -wire [0:15] frac_lut4_0__undriven_sram_inv ; -wire [0:0] frac_lut4_0_mode ; -wire [0:15] frac_lut4_0_sram ; -supply1 VDD ; -supply0 VSS ; - -grid_clb_frac_lut4_5 frac_lut4_0_ ( .in ( frac_lut4_in ) , - .sram ( frac_lut4_0_sram ) , - .sram_inv ( frac_lut4_0__undriven_sram_inv ) , - .mode ( frac_lut4_0_mode ) , - .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , - .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_5 frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , - .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , - frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] , - frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , - frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , - frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , - frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_5 ( - prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , VDD , - VSS , p3 ) ; -input [0:0] prog_clk ; -input [0:3] frac_logic_in ; -input [0:0] ccff_head ; -output [0:1] frac_logic_out ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; -input p3 ; - -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; -wire [0:1] mux_frac_logic_out_0_undriven_sram_inv ; -wire [0:1] mux_tree_size2_0_sram ; -supply1 VDD ; -supply0 VSS ; - -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( - .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , - .ccff_head ( ccff_head ) , - .frac_lut4_lut3_out ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] , - frac_logic_out[1] } ) , - - .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , - .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -grid_clb_mux_tree_size2_29 mux_frac_logic_out_0 ( - .in ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] - } ) , - .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_frac_logic_out_0_undriven_sram_inv ) , - .out ( frac_logic_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p3 ( p3 ) ) ; -grid_clb_mux_tree_size2_mem_29 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -grid_clb_direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( frac_logic_out[1] ) ) ; -grid_clb_direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( frac_logic_in[0] ) ) ; -grid_clb_direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( frac_logic_in[1] ) ) ; -grid_clb_direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( frac_logic_in[2] ) ) ; -grid_clb_direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( frac_logic_in[3] ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_5 ( - prog_clk , Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , - fabric_clk , ccff_head , fabric_out , fabric_regout , fabric_sc_out , - ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , p_abuf2 , p3 ) ; -input [0:0] prog_clk ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:3] fabric_in ; -input [0:0] fabric_regin ; -input [0:0] fabric_sc_in ; -input [0:0] fabric_clk ; -input [0:0] ccff_head ; -output [0:1] fabric_out ; -output [0:0] fabric_regout ; -output [0:0] fabric_sc_out ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; -output p_abuf0 ; -output p_abuf1 ; -output p_abuf2 ; -input p3 ; - -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; -wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; -wire [0:1] mux_fabric_out_0_undriven_sram_inv ; -wire [0:1] mux_fabric_out_1_undriven_sram_inv ; -wire [0:1] mux_ff_0_D_0_undriven_sram_inv ; -wire [0:1] mux_tree_size2_0_sram ; -wire [0:1] mux_tree_size2_1_sram ; -wire [0:0] mux_tree_size2_2_out ; -wire [0:1] mux_tree_size2_2_sram ; -wire [0:0] mux_tree_size2_mem_0_ccff_tail ; -wire [0:0] mux_tree_size2_mem_1_ccff_tail ; -supply1 VDD ; -supply0 VSS ; - -assign fabric_regout[0] = fabric_sc_out[0] ; - -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( - .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , - .ccff_head ( ccff_head ) , - .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , - .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p3 ( p3 ) ) ; -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_10 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( - .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , - .ff_DI ( fabric_sc_in ) , - .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , - .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_11 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( - .Test_en ( Test_en ) , .clk ( clk ) , - .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , - .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , - .ff_Q ( fabric_sc_out ) , - .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -grid_clb_mux_tree_size2_15 mux_fabric_out_0 ( - .in ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] - } ) , - .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_fabric_out_0_undriven_sram_inv ) , - .out ( fabric_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p3 ( p3 ) ) ; -grid_clb_mux_tree_size2_16 mux_fabric_out_1 ( - .in ( { fabric_sc_out[0] , - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] - } ) , - .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( mux_fabric_out_1_undriven_sram_inv ) , - .out ( fabric_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf0 ( p_abuf2 ) , .p3 ( p3 ) ) ; -grid_clb_mux_tree_size2_17 mux_ff_0_D_0 ( - .in ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , - fabric_regin[0] } ) , - .sram ( mux_tree_size2_2_sram ) , - .sram_inv ( mux_ff_0_D_0_undriven_sram_inv ) , - .out ( mux_tree_size2_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p3 ( p3 ) ) ; -grid_clb_mux_tree_size2_mem_15 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -grid_clb_mux_tree_size2_mem_16 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_size2_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -grid_clb_mux_tree_size2_mem_17 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , - .mem_out ( mux_tree_size2_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -grid_clb_direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fabric_sc_out ) ) ; -grid_clb_direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fabric_sc_out ) ) ; -grid_clb_direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( fabric_in[0] ) ) ; -grid_clb_direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_6 } ) , - .out ( fabric_in[1] ) ) ; -grid_clb_direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_7 } ) , - .out ( fabric_in[2] ) ) ; -grid_clb_direct_interc direct_interc_5_ ( - .in ( { SYNOPSYS_UNCONNECTED_8 } ) , - .out ( fabric_in[3] ) ) ; -grid_clb_direct_interc direct_interc_6_ ( - .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( fabric_sc_in ) ) ; -grid_clb_direct_interc direct_interc_7_ ( - .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( fabric_clk ) ) ; -grid_clb_direct_interc direct_interc_8_ ( - .in ( { SYNOPSYS_UNCONNECTED_11 } ) , - - .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) ) ; -grid_clb_direct_interc direct_interc_9_ ( - .in ( { SYNOPSYS_UNCONNECTED_12 } ) , - - .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ) ; -grid_clb_direct_interc direct_interc_10_ ( - .in ( { SYNOPSYS_UNCONNECTED_13 } ) , - .out ( fabric_clk ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_5 ( prog_clk , Test_en , - clk , fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , - fle_regout , fle_sc_out , ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , - p_abuf2 , p3 ) ; -input [0:0] prog_clk ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:3] fle_in ; -input [0:0] fle_regin ; -input [0:0] fle_sc_in ; -input [0:0] fle_clk ; -input [0:0] ccff_head ; -output [0:1] fle_out ; -output [0:0] fle_regout ; -output [0:0] fle_sc_out ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; -output p_abuf0 ; -output p_abuf1 ; -output p_abuf2 ; -input p3 ; - -supply1 VDD ; -supply0 VSS ; - -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( - .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , - .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , - .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , - .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , - .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p_abuf2 ( p_abuf2 ) , - .p3 ( p3 ) ) ; -grid_clb_direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( { p_abuf1 } ) ) ; -grid_clb_direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( fle_regout ) ) ; -grid_clb_direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fle_sc_out ) ) ; -grid_clb_direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fle_in[0] ) ) ; -grid_clb_direct_interc direct_interc_5_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( fle_in[1] ) ) ; -grid_clb_direct_interc direct_interc_6_ ( - .in ( { SYNOPSYS_UNCONNECTED_6 } ) , - .out ( fle_in[2] ) ) ; -grid_clb_direct_interc direct_interc_7_ ( - .in ( { SYNOPSYS_UNCONNECTED_7 } ) , - .out ( fle_in[3] ) ) ; -grid_clb_direct_interc direct_interc_8_ ( - .in ( { SYNOPSYS_UNCONNECTED_8 } ) , - .out ( fle_regin ) ) ; -grid_clb_direct_interc direct_interc_9_ ( - .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( fle_sc_in ) ) ; -grid_clb_direct_interc direct_interc_10_ ( - .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( fle_clk ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_mem_14 ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__42 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_mem_13 ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__41 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_mem_12 ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__40 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_14 ( in , sram , sram_inv , out , VDD , VSS , - p2 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p2 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_13 ( in , sram , sram_inv , out , VDD , VSS , - p_abuf0 , p_abuf1 , p3 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -output p_abuf0 ; -output p_abuf1 ; -input p3 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf1 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_80 ( .A ( p_abuf1 ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_81 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_12 ( in , sram , sram_inv , out , VDD , VSS , - p_abuf0 , p3 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -output p_abuf0 ; -input p3 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_79 ( .A ( out[0] ) , .X ( p_abuf0 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_9 ( - Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk , VDD , VSS ) ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:0] ff_D ; -input [0:0] ff_DI ; -output [0:0] ff_Q ; -input [0:0] ff_clk ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , - .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_8 ( - Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk , VDD , VSS ) ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:0] ff_D ; -input [0:0] ff_DI ; -output [0:0] ff_Q ; -input [0:0] ff_clk ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , - .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_mem_28 ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_22__39 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_28 ( in , sram , sram_inv , out , VDD , VSS , - p2 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p2 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_4 ( prog_clk , - ccff_head , ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:16] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_5_ ( .D ( mem_out[4] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_6_ ( .D ( mem_out[5] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_7_ ( .D ( mem_out[6] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_8_ ( .D ( mem_out[7] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_9_ ( .D ( mem_out[8] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_10_ ( .D ( mem_out[9] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_11_ ( .D ( mem_out[10] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_12_ ( .D ( mem_out[11] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_13_ ( .D ( mem_out[12] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_14_ ( .D ( mem_out[13] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_15_ ( .D ( mem_out[14] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_16_ ( .D ( mem_out[15] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__38 ( .A ( mem_out[16] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_frac_lut4_mux_4 ( in , sram , sram_inv , lut3_out , lut4_out , - VDD , VSS ) ; -input [0:15] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:1] lut3_out ; -output [0:0] lut4_out ; -input VDD ; -input VSS ; - -wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_4_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_5_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( - .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( - .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( - .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( - .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_6_ ( - .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__buf_2_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__buf_2_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__buf_2_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_frac_lut4_4 ( in , sram , sram_inv , mode , mode_inv , - lut3_out , lut4_out , VDD , VSS ) ; -input [0:3] in ; -input [0:15] sram ; -input [0:15] sram_inv ; -input [0:0] mode ; -input [0:0] mode_inv ; -output [0:1] lut3_out ; -output [0:0] lut4_out ; -input VDD ; -input VSS ; - -wire [0:0] sky130_fd_sc_hd__buf_2_0_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_1_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_2_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; -wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ; -wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ; -wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ; -wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ; -wire [0:0] sky130_fd_sc_hd__or2_1_0_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , - .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , - .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , - .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , - .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( - .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , - .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , - .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , - .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , - .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( - .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -grid_clb_frac_lut4_mux_4 frac_lut4_mux_0_ ( .in ( sram ) , - .sram ( { sky130_fd_sc_hd__buf_2_0_X[0] , sky130_fd_sc_hd__buf_2_1_X[0] , - sky130_fd_sc_hd__buf_2_2_X[0] , sky130_fd_sc_hd__buf_2_3_X[0] } ) , - .sram_inv ( { sky130_fd_sc_hd__inv_1_0_Y[0] , - sky130_fd_sc_hd__inv_1_1_Y[0] , sky130_fd_sc_hd__inv_1_2_Y[0] , - sky130_fd_sc_hd__inv_1_3_Y[0] } ) , - .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_4 ( - prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out , - frac_lut4_lut4_out , ccff_tail , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:3] frac_lut4_in ; -input [0:0] ccff_head ; -output [0:1] frac_lut4_lut3_out ; -output [0:0] frac_lut4_lut4_out ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; - -wire [0:15] frac_lut4_0__undriven_sram_inv ; -wire [0:0] frac_lut4_0_mode ; -wire [0:15] frac_lut4_0_sram ; -supply1 VDD ; -supply0 VSS ; - -grid_clb_frac_lut4_4 frac_lut4_0_ ( .in ( frac_lut4_in ) , - .sram ( frac_lut4_0_sram ) , - .sram_inv ( frac_lut4_0__undriven_sram_inv ) , - .mode ( frac_lut4_0_mode ) , - .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , - .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_4 frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , - .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , - frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] , - frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , - frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , - frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , - frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_4 ( - prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , VDD , - VSS , p2 ) ; -input [0:0] prog_clk ; -input [0:3] frac_logic_in ; -input [0:0] ccff_head ; -output [0:1] frac_logic_out ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; -input p2 ; - -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; -wire [0:1] mux_frac_logic_out_0_undriven_sram_inv ; -wire [0:1] mux_tree_size2_0_sram ; -supply1 VDD ; -supply0 VSS ; - -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( - .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , - .ccff_head ( ccff_head ) , - .frac_lut4_lut3_out ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] , - frac_logic_out[1] } ) , - - .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , - .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -grid_clb_mux_tree_size2_28 mux_frac_logic_out_0 ( - .in ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] - } ) , - .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_frac_logic_out_0_undriven_sram_inv ) , - .out ( frac_logic_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; -grid_clb_mux_tree_size2_mem_28 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -grid_clb_direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( frac_logic_out[1] ) ) ; -grid_clb_direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( frac_logic_in[0] ) ) ; -grid_clb_direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( frac_logic_in[1] ) ) ; -grid_clb_direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( frac_logic_in[2] ) ) ; -grid_clb_direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( frac_logic_in[3] ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_4 ( - prog_clk , Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , - fabric_clk , ccff_head , fabric_out , fabric_regout , fabric_sc_out , - ccff_tail , VDD , VSS , p_abuf0 , p_abuf2 , p_abuf3 , p2 , p3 ) ; -input [0:0] prog_clk ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:3] fabric_in ; -input [0:0] fabric_regin ; -input [0:0] fabric_sc_in ; -input [0:0] fabric_clk ; -input [0:0] ccff_head ; -output [0:1] fabric_out ; -output [0:0] fabric_regout ; -output [0:0] fabric_sc_out ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; -output p_abuf0 ; -output p_abuf2 ; -output p_abuf3 ; -input p2 ; -input p3 ; - -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; -wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; -wire [0:1] mux_fabric_out_0_undriven_sram_inv ; -wire [0:1] mux_fabric_out_1_undriven_sram_inv ; -wire [0:1] mux_ff_0_D_0_undriven_sram_inv ; -wire [0:1] mux_tree_size2_0_sram ; -wire [0:1] mux_tree_size2_1_sram ; -wire [0:0] mux_tree_size2_2_out ; -wire [0:1] mux_tree_size2_2_sram ; -wire [0:0] mux_tree_size2_mem_0_ccff_tail ; -wire [0:0] mux_tree_size2_mem_1_ccff_tail ; -supply1 VDD ; -supply0 VSS ; - -assign fabric_regout[0] = fabric_sc_out[0] ; - -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( - .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , - .ccff_head ( ccff_head ) , - .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , - .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_8 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( - .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , - .ff_DI ( fabric_sc_in ) , - .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , - .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_9 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( - .Test_en ( Test_en ) , .clk ( clk ) , - .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , - .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , - .ff_Q ( fabric_sc_out ) , - .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -grid_clb_mux_tree_size2_12 mux_fabric_out_0 ( - .in ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] - } ) , - .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_fabric_out_0_undriven_sram_inv ) , - .out ( fabric_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf0 ( p_abuf0 ) , .p3 ( p3 ) ) ; -grid_clb_mux_tree_size2_13 mux_fabric_out_1 ( - .in ( { fabric_sc_out[0] , - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] - } ) , - .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( mux_fabric_out_1_undriven_sram_inv ) , - .out ( fabric_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf0 ( p_abuf2 ) , .p_abuf1 ( p_abuf3 ) , .p3 ( p3 ) ) ; -grid_clb_mux_tree_size2_14 mux_ff_0_D_0 ( - .in ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , - fabric_regin[0] } ) , - .sram ( mux_tree_size2_2_sram ) , - .sram_inv ( mux_ff_0_D_0_undriven_sram_inv ) , - .out ( mux_tree_size2_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; -grid_clb_mux_tree_size2_mem_12 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -grid_clb_mux_tree_size2_mem_13 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_size2_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -grid_clb_mux_tree_size2_mem_14 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , - .mem_out ( mux_tree_size2_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -grid_clb_direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fabric_sc_out ) ) ; -grid_clb_direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fabric_sc_out ) ) ; -grid_clb_direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( fabric_in[0] ) ) ; -grid_clb_direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_6 } ) , - .out ( fabric_in[1] ) ) ; -grid_clb_direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_7 } ) , - .out ( fabric_in[2] ) ) ; -grid_clb_direct_interc direct_interc_5_ ( - .in ( { SYNOPSYS_UNCONNECTED_8 } ) , - .out ( fabric_in[3] ) ) ; -grid_clb_direct_interc direct_interc_6_ ( - .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( fabric_sc_in ) ) ; -grid_clb_direct_interc direct_interc_7_ ( - .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( fabric_clk ) ) ; -grid_clb_direct_interc direct_interc_8_ ( - .in ( { SYNOPSYS_UNCONNECTED_11 } ) , - - .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) ) ; -grid_clb_direct_interc direct_interc_9_ ( - .in ( { SYNOPSYS_UNCONNECTED_12 } ) , - - .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ) ; -grid_clb_direct_interc direct_interc_10_ ( - .in ( { SYNOPSYS_UNCONNECTED_13 } ) , - .out ( fabric_clk ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_4 ( prog_clk , Test_en , - clk , fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , - fle_regout , fle_sc_out , ccff_tail , VDD , VSS , p_abuf0 , p_abuf2 , - p_abuf3 , p2 , p3 ) ; -input [0:0] prog_clk ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:3] fle_in ; -input [0:0] fle_regin ; -input [0:0] fle_sc_in ; -input [0:0] fle_clk ; -input [0:0] ccff_head ; -output [0:1] fle_out ; -output [0:0] fle_regout ; -output [0:0] fle_sc_out ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; -output p_abuf0 ; -output p_abuf2 ; -output p_abuf3 ; -input p2 ; -input p3 ; - -supply1 VDD ; -supply0 VSS ; - -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( - .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , - .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , - .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , - .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , - .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf0 ( p_abuf0 ) , .p_abuf2 ( p_abuf2 ) , .p_abuf3 ( p_abuf3 ) , - .p2 ( p2 ) , .p3 ( p3 ) ) ; -grid_clb_direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( { p_abuf3 } ) ) ; -grid_clb_direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( fle_regout ) ) ; -grid_clb_direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fle_sc_out ) ) ; -grid_clb_direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fle_in[0] ) ) ; -grid_clb_direct_interc direct_interc_5_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( fle_in[1] ) ) ; -grid_clb_direct_interc direct_interc_6_ ( - .in ( { SYNOPSYS_UNCONNECTED_6 } ) , - .out ( fle_in[2] ) ) ; -grid_clb_direct_interc direct_interc_7_ ( - .in ( { SYNOPSYS_UNCONNECTED_7 } ) , - .out ( fle_in[3] ) ) ; -grid_clb_direct_interc direct_interc_8_ ( - .in ( { SYNOPSYS_UNCONNECTED_8 } ) , - .out ( fle_regin ) ) ; -grid_clb_direct_interc direct_interc_9_ ( - .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( fle_sc_in ) ) ; -grid_clb_direct_interc direct_interc_10_ ( - .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( fle_clk ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_mem_11 ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__37 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_mem_10 ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__36 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_mem_9 ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__35 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_11 ( in , sram , sram_inv , out , VDD , VSS , - p2 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p2 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_10 ( in , sram , sram_inv , out , VDD , VSS , - p_abuf0 , p_abuf1 , p2 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -output p_abuf0 ; -output p_abuf1 ; -input p2 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf1 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_76 ( .A ( p_abuf1 ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_77 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_9 ( in , sram , sram_inv , out , VDD , VSS , - p_abuf0 , p2 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -output p_abuf0 ; -input p2 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p2 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_75 ( .A ( out[0] ) , .X ( p_abuf0 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_7 ( - Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk , VDD , VSS ) ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:0] ff_D ; -input [0:0] ff_DI ; -output [0:0] ff_Q ; -input [0:0] ff_clk ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , - .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_6 ( - Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk , VDD , VSS ) ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:0] ff_D ; -input [0:0] ff_DI ; -output [0:0] ff_Q ; -input [0:0] ff_clk ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , - .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_mem_27 ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__34 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_27 ( in , sram , sram_inv , out , VDD , VSS , - p2 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p2 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_3 ( prog_clk , - ccff_head , ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:16] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_5_ ( .D ( mem_out[4] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_6_ ( .D ( mem_out[5] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_7_ ( .D ( mem_out[6] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_8_ ( .D ( mem_out[7] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_9_ ( .D ( mem_out[8] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_10_ ( .D ( mem_out[9] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_11_ ( .D ( mem_out[10] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_12_ ( .D ( mem_out[11] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_13_ ( .D ( mem_out[12] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_14_ ( .D ( mem_out[13] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_15_ ( .D ( mem_out[14] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_16_ ( .D ( mem_out[15] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__33 ( .A ( mem_out[16] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_frac_lut4_mux_3 ( in , sram , sram_inv , lut3_out , lut4_out , - VDD , VSS ) ; -input [0:15] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:1] lut3_out ; -output [0:0] lut4_out ; -input VDD ; -input VSS ; - -wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_4_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_5_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( - .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( - .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( - .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_5_ ( - .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_6_ ( - .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__buf_2_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__buf_2_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__buf_2_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_frac_lut4_3 ( in , sram , sram_inv , mode , mode_inv , - lut3_out , lut4_out , VDD , VSS ) ; -input [0:3] in ; -input [0:15] sram ; -input [0:15] sram_inv ; -input [0:0] mode ; -input [0:0] mode_inv ; -output [0:1] lut3_out ; -output [0:0] lut4_out ; -input VDD ; -input VSS ; - -wire [0:0] sky130_fd_sc_hd__buf_2_0_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_1_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_2_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; -wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ; -wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ; -wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ; -wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ; -wire [0:0] sky130_fd_sc_hd__or2_1_0_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , - .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , - .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , - .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , - .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( - .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , - .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , - .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , - .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , - .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( - .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -grid_clb_frac_lut4_mux_3 frac_lut4_mux_0_ ( .in ( sram ) , - .sram ( { sky130_fd_sc_hd__buf_2_0_X[0] , sky130_fd_sc_hd__buf_2_1_X[0] , - sky130_fd_sc_hd__buf_2_2_X[0] , sky130_fd_sc_hd__buf_2_3_X[0] } ) , - .sram_inv ( { sky130_fd_sc_hd__inv_1_0_Y[0] , - sky130_fd_sc_hd__inv_1_1_Y[0] , sky130_fd_sc_hd__inv_1_2_Y[0] , - sky130_fd_sc_hd__inv_1_3_Y[0] } ) , - .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_3 ( - prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out , - frac_lut4_lut4_out , ccff_tail , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:3] frac_lut4_in ; -input [0:0] ccff_head ; -output [0:1] frac_lut4_lut3_out ; -output [0:0] frac_lut4_lut4_out ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; - -wire [0:15] frac_lut4_0__undriven_sram_inv ; -wire [0:0] frac_lut4_0_mode ; -wire [0:15] frac_lut4_0_sram ; -supply1 VDD ; -supply0 VSS ; - -grid_clb_frac_lut4_3 frac_lut4_0_ ( .in ( frac_lut4_in ) , - .sram ( frac_lut4_0_sram ) , - .sram_inv ( frac_lut4_0__undriven_sram_inv ) , - .mode ( frac_lut4_0_mode ) , - .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , - .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_3 frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , - .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , - frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] , - frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , - frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , - frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , - frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_3 ( - prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , VDD , - VSS , p2 ) ; -input [0:0] prog_clk ; -input [0:3] frac_logic_in ; -input [0:0] ccff_head ; -output [0:1] frac_logic_out ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; -input p2 ; - -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; -wire [0:1] mux_frac_logic_out_0_undriven_sram_inv ; -wire [0:1] mux_tree_size2_0_sram ; -supply1 VDD ; -supply0 VSS ; - -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( - .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , - .ccff_head ( ccff_head ) , - .frac_lut4_lut3_out ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] , - frac_logic_out[1] } ) , - - .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , - .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -grid_clb_mux_tree_size2_27 mux_frac_logic_out_0 ( - .in ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] - } ) , - .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_frac_logic_out_0_undriven_sram_inv ) , - .out ( frac_logic_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; -grid_clb_mux_tree_size2_mem_27 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -grid_clb_direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( frac_logic_out[1] ) ) ; -grid_clb_direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( frac_logic_in[0] ) ) ; -grid_clb_direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( frac_logic_in[1] ) ) ; -grid_clb_direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( frac_logic_in[2] ) ) ; -grid_clb_direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( frac_logic_in[3] ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_3 ( - prog_clk , Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , - fabric_clk , ccff_head , fabric_out , fabric_regout , fabric_sc_out , - ccff_tail , VDD , VSS , p_abuf0 , p_abuf2 , p_abuf3 , p2 ) ; -input [0:0] prog_clk ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:3] fabric_in ; -input [0:0] fabric_regin ; -input [0:0] fabric_sc_in ; -input [0:0] fabric_clk ; -input [0:0] ccff_head ; -output [0:1] fabric_out ; -output [0:0] fabric_regout ; -output [0:0] fabric_sc_out ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; -output p_abuf0 ; -output p_abuf2 ; -output p_abuf3 ; -input p2 ; - -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; -wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; -wire [0:1] mux_fabric_out_0_undriven_sram_inv ; -wire [0:1] mux_fabric_out_1_undriven_sram_inv ; -wire [0:1] mux_ff_0_D_0_undriven_sram_inv ; -wire [0:1] mux_tree_size2_0_sram ; -wire [0:1] mux_tree_size2_1_sram ; -wire [0:0] mux_tree_size2_2_out ; -wire [0:1] mux_tree_size2_2_sram ; -wire [0:0] mux_tree_size2_mem_0_ccff_tail ; -wire [0:0] mux_tree_size2_mem_1_ccff_tail ; -supply1 VDD ; -supply0 VSS ; - -assign fabric_regout[0] = fabric_sc_out[0] ; - -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( - .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , - .ccff_head ( ccff_head ) , - .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , - .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( - .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , - .ff_DI ( fabric_sc_in ) , - .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , - .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_7 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( - .Test_en ( Test_en ) , .clk ( clk ) , - .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , - .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , - .ff_Q ( fabric_sc_out ) , - .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -grid_clb_mux_tree_size2_9 mux_fabric_out_0 ( - .in ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] - } ) , - .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_fabric_out_0_undriven_sram_inv ) , - .out ( fabric_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf0 ( p_abuf0 ) , .p2 ( p2 ) ) ; -grid_clb_mux_tree_size2_10 mux_fabric_out_1 ( - .in ( { fabric_sc_out[0] , - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] - } ) , - .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( mux_fabric_out_1_undriven_sram_inv ) , - .out ( fabric_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf0 ( p_abuf2 ) , .p_abuf1 ( p_abuf3 ) , .p2 ( p2 ) ) ; -grid_clb_mux_tree_size2_11 mux_ff_0_D_0 ( - .in ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , - fabric_regin[0] } ) , - .sram ( mux_tree_size2_2_sram ) , - .sram_inv ( mux_ff_0_D_0_undriven_sram_inv ) , - .out ( mux_tree_size2_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; -grid_clb_mux_tree_size2_mem_9 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -grid_clb_mux_tree_size2_mem_10 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_size2_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -grid_clb_mux_tree_size2_mem_11 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , - .mem_out ( mux_tree_size2_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -grid_clb_direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fabric_sc_out ) ) ; -grid_clb_direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fabric_sc_out ) ) ; -grid_clb_direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( fabric_in[0] ) ) ; -grid_clb_direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_6 } ) , - .out ( fabric_in[1] ) ) ; -grid_clb_direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_7 } ) , - .out ( fabric_in[2] ) ) ; -grid_clb_direct_interc direct_interc_5_ ( - .in ( { SYNOPSYS_UNCONNECTED_8 } ) , - .out ( fabric_in[3] ) ) ; -grid_clb_direct_interc direct_interc_6_ ( - .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( fabric_sc_in ) ) ; -grid_clb_direct_interc direct_interc_7_ ( - .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( fabric_clk ) ) ; -grid_clb_direct_interc direct_interc_8_ ( - .in ( { SYNOPSYS_UNCONNECTED_11 } ) , - - .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) ) ; -grid_clb_direct_interc direct_interc_9_ ( - .in ( { SYNOPSYS_UNCONNECTED_12 } ) , - - .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ) ; -grid_clb_direct_interc direct_interc_10_ ( - .in ( { SYNOPSYS_UNCONNECTED_13 } ) , - .out ( fabric_clk ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_3 ( prog_clk , Test_en , - clk , fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , - fle_regout , fle_sc_out , ccff_tail , VDD , VSS , p_abuf0 , p_abuf2 , - p_abuf3 , p2 ) ; -input [0:0] prog_clk ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:3] fle_in ; -input [0:0] fle_regin ; -input [0:0] fle_sc_in ; -input [0:0] fle_clk ; -input [0:0] ccff_head ; -output [0:1] fle_out ; -output [0:0] fle_regout ; -output [0:0] fle_sc_out ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; -output p_abuf0 ; -output p_abuf2 ; -output p_abuf3 ; -input p2 ; - -supply1 VDD ; -supply0 VSS ; - -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( - .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , - .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , - .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , - .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , - .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf0 ( p_abuf0 ) , .p_abuf2 ( p_abuf2 ) , .p_abuf3 ( p_abuf3 ) , - .p2 ( p2 ) ) ; -grid_clb_direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( { p_abuf3 } ) ) ; -grid_clb_direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( fle_regout ) ) ; -grid_clb_direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fle_sc_out ) ) ; -grid_clb_direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fle_in[0] ) ) ; -grid_clb_direct_interc direct_interc_5_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( fle_in[1] ) ) ; -grid_clb_direct_interc direct_interc_6_ ( - .in ( { SYNOPSYS_UNCONNECTED_6 } ) , - .out ( fle_in[2] ) ) ; -grid_clb_direct_interc direct_interc_7_ ( - .in ( { SYNOPSYS_UNCONNECTED_7 } ) , - .out ( fle_in[3] ) ) ; -grid_clb_direct_interc direct_interc_8_ ( - .in ( { SYNOPSYS_UNCONNECTED_8 } ) , - .out ( fle_regin ) ) ; -grid_clb_direct_interc direct_interc_9_ ( - .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( fle_sc_in ) ) ; -grid_clb_direct_interc direct_interc_10_ ( - .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( fle_clk ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_mem_8 ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__32 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_mem_7 ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__31 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__30 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_8 ( in , sram , sram_inv , out , VDD , VSS , - p2 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p2 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_7 ( in , sram , sram_inv , out , VDD , VSS , - p_abuf0 , p_abuf1 , p2 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -output p_abuf0 ; -output p_abuf1 ; -input p2 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf1 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_72 ( .A ( p_abuf1 ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_73 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_6 ( in , sram , sram_inv , out , VDD , VSS , - p_abuf0 , p_abuf1 , p2 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -output p_abuf0 ; -output p_abuf1 ; -input p2 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf1 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_70 ( .A ( p_abuf1 ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_71 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_5 ( - Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk , VDD , VSS ) ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:0] ff_D ; -input [0:0] ff_DI ; -output [0:0] ff_Q ; -input [0:0] ff_clk ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , - .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_4 ( - Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk , VDD , VSS ) ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:0] ff_D ; -input [0:0] ff_DI ; -output [0:0] ff_Q ; -input [0:0] ff_clk ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , - .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_mem_26 ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__29 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_26 ( in , sram , sram_inv , out , VDD , VSS , - p2 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p2 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_2 ( prog_clk , - ccff_head , ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:16] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_5_ ( .D ( mem_out[4] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_6_ ( .D ( mem_out[5] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_7_ ( .D ( mem_out[6] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_8_ ( .D ( mem_out[7] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_9_ ( .D ( mem_out[8] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_10_ ( .D ( mem_out[9] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_11_ ( .D ( mem_out[10] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_12_ ( .D ( mem_out[11] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_13_ ( .D ( mem_out[12] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_14_ ( .D ( mem_out[13] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_15_ ( .D ( mem_out[14] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_16_ ( .D ( mem_out[15] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__28 ( .A ( mem_out[16] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_frac_lut4_mux_2 ( in , sram , sram_inv , lut3_out , lut4_out , - VDD , VSS ) ; -input [0:15] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:1] lut3_out ; -output [0:0] lut4_out ; -input VDD ; -input VSS ; - -wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_4_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_5_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( - .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( - .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( - .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( - .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_6_ ( - .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__buf_2_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__buf_2_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__buf_2_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_frac_lut4_2 ( in , sram , sram_inv , mode , mode_inv , - lut3_out , lut4_out , VDD , VSS ) ; -input [0:3] in ; -input [0:15] sram ; -input [0:15] sram_inv ; -input [0:0] mode ; -input [0:0] mode_inv ; -output [0:1] lut3_out ; -output [0:0] lut4_out ; -input VDD ; -input VSS ; - -wire [0:0] sky130_fd_sc_hd__buf_2_0_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_1_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_2_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; -wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ; -wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ; -wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ; -wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ; -wire [0:0] sky130_fd_sc_hd__or2_1_0_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , - .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , - .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , - .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , - .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( - .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , - .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , - .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , - .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , - .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( - .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -grid_clb_frac_lut4_mux_2 frac_lut4_mux_0_ ( .in ( sram ) , - .sram ( { sky130_fd_sc_hd__buf_2_0_X[0] , sky130_fd_sc_hd__buf_2_1_X[0] , - sky130_fd_sc_hd__buf_2_2_X[0] , sky130_fd_sc_hd__buf_2_3_X[0] } ) , - .sram_inv ( { sky130_fd_sc_hd__inv_1_0_Y[0] , - sky130_fd_sc_hd__inv_1_1_Y[0] , sky130_fd_sc_hd__inv_1_2_Y[0] , - sky130_fd_sc_hd__inv_1_3_Y[0] } ) , - .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_2 ( - prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out , - frac_lut4_lut4_out , ccff_tail , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:3] frac_lut4_in ; -input [0:0] ccff_head ; -output [0:1] frac_lut4_lut3_out ; -output [0:0] frac_lut4_lut4_out ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; - -wire [0:15] frac_lut4_0__undriven_sram_inv ; -wire [0:0] frac_lut4_0_mode ; -wire [0:15] frac_lut4_0_sram ; -supply1 VDD ; -supply0 VSS ; - -grid_clb_frac_lut4_2 frac_lut4_0_ ( .in ( frac_lut4_in ) , - .sram ( frac_lut4_0_sram ) , - .sram_inv ( frac_lut4_0__undriven_sram_inv ) , - .mode ( frac_lut4_0_mode ) , - .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , - .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_2 frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , - .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , - frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] , - frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , - frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , - frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , - frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_2 ( - prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , VDD , - VSS , p2 ) ; -input [0:0] prog_clk ; -input [0:3] frac_logic_in ; -input [0:0] ccff_head ; -output [0:1] frac_logic_out ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; -input p2 ; - -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; -wire [0:1] mux_frac_logic_out_0_undriven_sram_inv ; -wire [0:1] mux_tree_size2_0_sram ; -supply1 VDD ; -supply0 VSS ; - -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( - .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , - .ccff_head ( ccff_head ) , - .frac_lut4_lut3_out ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] , - frac_logic_out[1] } ) , - - .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , - .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -grid_clb_mux_tree_size2_26 mux_frac_logic_out_0 ( - .in ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] - } ) , - .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_frac_logic_out_0_undriven_sram_inv ) , - .out ( frac_logic_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; -grid_clb_mux_tree_size2_mem_26 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -grid_clb_direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( frac_logic_out[1] ) ) ; -grid_clb_direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( frac_logic_in[0] ) ) ; -grid_clb_direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( frac_logic_in[1] ) ) ; -grid_clb_direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( frac_logic_in[2] ) ) ; -grid_clb_direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( frac_logic_in[3] ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_2 ( - prog_clk , Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , - fabric_clk , ccff_head , fabric_out , fabric_regout , fabric_sc_out , - ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , p_abuf2 , p_abuf3 , p2 ) ; -input [0:0] prog_clk ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:3] fabric_in ; -input [0:0] fabric_regin ; -input [0:0] fabric_sc_in ; -input [0:0] fabric_clk ; -input [0:0] ccff_head ; -output [0:1] fabric_out ; -output [0:0] fabric_regout ; -output [0:0] fabric_sc_out ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; -output p_abuf0 ; -output p_abuf1 ; -output p_abuf2 ; -output p_abuf3 ; -input p2 ; - -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; -wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; -wire [0:1] mux_fabric_out_0_undriven_sram_inv ; -wire [0:1] mux_fabric_out_1_undriven_sram_inv ; -wire [0:1] mux_ff_0_D_0_undriven_sram_inv ; -wire [0:1] mux_tree_size2_0_sram ; -wire [0:1] mux_tree_size2_1_sram ; -wire [0:0] mux_tree_size2_2_out ; -wire [0:1] mux_tree_size2_2_sram ; -wire [0:0] mux_tree_size2_mem_0_ccff_tail ; -wire [0:0] mux_tree_size2_mem_1_ccff_tail ; -supply1 VDD ; -supply0 VSS ; - -assign fabric_regout[0] = fabric_sc_out[0] ; - -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( - .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , - .ccff_head ( ccff_head ) , - .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , - .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( - .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , - .ff_DI ( fabric_sc_in ) , - .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , - .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( - .Test_en ( Test_en ) , .clk ( clk ) , - .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , - .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , - .ff_Q ( fabric_sc_out ) , - .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -grid_clb_mux_tree_size2_6 mux_fabric_out_0 ( - .in ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] - } ) , - .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_fabric_out_0_undriven_sram_inv ) , - .out ( fabric_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p2 ( p2 ) ) ; -grid_clb_mux_tree_size2_7 mux_fabric_out_1 ( - .in ( { fabric_sc_out[0] , - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] - } ) , - .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( mux_fabric_out_1_undriven_sram_inv ) , - .out ( fabric_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf0 ( p_abuf2 ) , .p_abuf1 ( p_abuf3 ) , .p2 ( p2 ) ) ; -grid_clb_mux_tree_size2_8 mux_ff_0_D_0 ( - .in ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , - fabric_regin[0] } ) , - .sram ( mux_tree_size2_2_sram ) , - .sram_inv ( mux_ff_0_D_0_undriven_sram_inv ) , - .out ( mux_tree_size2_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; -grid_clb_mux_tree_size2_mem_6 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -grid_clb_mux_tree_size2_mem_7 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_size2_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -grid_clb_mux_tree_size2_mem_8 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , - .mem_out ( mux_tree_size2_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -grid_clb_direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fabric_sc_out ) ) ; -grid_clb_direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fabric_sc_out ) ) ; -grid_clb_direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( fabric_in[0] ) ) ; -grid_clb_direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_6 } ) , - .out ( fabric_in[1] ) ) ; -grid_clb_direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_7 } ) , - .out ( fabric_in[2] ) ) ; -grid_clb_direct_interc direct_interc_5_ ( - .in ( { SYNOPSYS_UNCONNECTED_8 } ) , - .out ( fabric_in[3] ) ) ; -grid_clb_direct_interc direct_interc_6_ ( - .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( fabric_sc_in ) ) ; -grid_clb_direct_interc direct_interc_7_ ( - .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( fabric_clk ) ) ; -grid_clb_direct_interc direct_interc_8_ ( - .in ( { SYNOPSYS_UNCONNECTED_11 } ) , - - .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) ) ; -grid_clb_direct_interc direct_interc_9_ ( - .in ( { SYNOPSYS_UNCONNECTED_12 } ) , - - .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ) ; -grid_clb_direct_interc direct_interc_10_ ( - .in ( { SYNOPSYS_UNCONNECTED_13 } ) , - .out ( fabric_clk ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_2 ( prog_clk , Test_en , - clk , fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , - fle_regout , fle_sc_out , ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , - p_abuf2 , p_abuf3 , p2 ) ; -input [0:0] prog_clk ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:3] fle_in ; -input [0:0] fle_regin ; -input [0:0] fle_sc_in ; -input [0:0] fle_clk ; -input [0:0] ccff_head ; -output [0:1] fle_out ; -output [0:0] fle_regout ; -output [0:0] fle_sc_out ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; -output p_abuf0 ; -output p_abuf1 ; -output p_abuf2 ; -output p_abuf3 ; -input p2 ; - -supply1 VDD ; -supply0 VSS ; - -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( - .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , - .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , - .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , - .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , - .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p_abuf2 ( p_abuf2 ) , - .p_abuf3 ( p_abuf3 ) , .p2 ( p2 ) ) ; -grid_clb_direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( { p_abuf1 } ) ) ; -grid_clb_direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( { p_abuf3 } ) ) ; -grid_clb_direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fle_regout ) ) ; -grid_clb_direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fle_sc_out ) ) ; -grid_clb_direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( fle_in[0] ) ) ; -grid_clb_direct_interc direct_interc_5_ ( - .in ( { SYNOPSYS_UNCONNECTED_6 } ) , - .out ( fle_in[1] ) ) ; -grid_clb_direct_interc direct_interc_6_ ( - .in ( { SYNOPSYS_UNCONNECTED_7 } ) , - .out ( fle_in[2] ) ) ; -grid_clb_direct_interc direct_interc_7_ ( - .in ( { SYNOPSYS_UNCONNECTED_8 } ) , - .out ( fle_in[3] ) ) ; -grid_clb_direct_interc direct_interc_8_ ( - .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( fle_regin ) ) ; -grid_clb_direct_interc direct_interc_9_ ( - .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( fle_sc_in ) ) ; -grid_clb_direct_interc direct_interc_10_ ( - .in ( { SYNOPSYS_UNCONNECTED_11 } ) , - .out ( fle_clk ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__27 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__26 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__25 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_5 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_4 ( in , sram , sram_inv , out , VDD , VSS , - p_abuf0 , p1 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -output p_abuf0 ; -input p1 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p1 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_69 ( .A ( out[0] ) , .X ( p_abuf0 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_3 ( in , sram , sram_inv , out , VDD , VSS , - p_abuf0 , p_abuf1 , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -output p_abuf0 ; -output p_abuf1 ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf1 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_66 ( .A ( p_abuf1 ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_67 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_3 ( - Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk , VDD , VSS ) ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:0] ff_D ; -input [0:0] ff_DI ; -output [0:0] ff_Q ; -input [0:0] ff_clk ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , - .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_2 ( - Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk , VDD , VSS ) ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:0] ff_D ; -input [0:0] ff_DI ; -output [0:0] ff_Q ; -input [0:0] ff_clk ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , - .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_mem_25 ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__24 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_25 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_1 ( prog_clk , - ccff_head , ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:16] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_5_ ( .D ( mem_out[4] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_6_ ( .D ( mem_out[5] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_7_ ( .D ( mem_out[6] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_8_ ( .D ( mem_out[7] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_9_ ( .D ( mem_out[8] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_10_ ( .D ( mem_out[9] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_11_ ( .D ( mem_out[10] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_12_ ( .D ( mem_out[11] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_13_ ( .D ( mem_out[12] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_14_ ( .D ( mem_out[13] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_15_ ( .D ( mem_out[14] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_16_ ( .D ( mem_out[15] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__23 ( .A ( mem_out[16] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_frac_lut4_mux_1 ( in , sram , sram_inv , lut3_out , lut4_out , - VDD , VSS ) ; -input [0:15] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:1] lut3_out ; -output [0:0] lut4_out ; -input VDD ; -input VSS ; - -wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_4_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_5_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( - .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( - .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( - .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( - .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_6_ ( - .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__buf_2_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__buf_2_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__buf_2_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_frac_lut4_1 ( in , sram , sram_inv , mode , mode_inv , - lut3_out , lut4_out , VDD , VSS ) ; -input [0:3] in ; -input [0:15] sram ; -input [0:15] sram_inv ; -input [0:0] mode ; -input [0:0] mode_inv ; -output [0:1] lut3_out ; -output [0:0] lut4_out ; -input VDD ; -input VSS ; - -wire [0:0] sky130_fd_sc_hd__buf_2_0_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_1_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_2_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; -wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ; -wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ; -wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ; -wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ; -wire [0:0] sky130_fd_sc_hd__or2_1_0_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , - .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , - .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , - .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , - .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( - .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , - .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , - .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , - .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , - .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( - .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -grid_clb_frac_lut4_mux_1 frac_lut4_mux_0_ ( .in ( sram ) , - .sram ( { sky130_fd_sc_hd__buf_2_0_X[0] , sky130_fd_sc_hd__buf_2_1_X[0] , - sky130_fd_sc_hd__buf_2_2_X[0] , sky130_fd_sc_hd__buf_2_3_X[0] } ) , - .sram_inv ( { sky130_fd_sc_hd__inv_1_0_Y[0] , - sky130_fd_sc_hd__inv_1_1_Y[0] , sky130_fd_sc_hd__inv_1_2_Y[0] , - sky130_fd_sc_hd__inv_1_3_Y[0] } ) , - .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_1 ( - prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out , - frac_lut4_lut4_out , ccff_tail , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:3] frac_lut4_in ; -input [0:0] ccff_head ; -output [0:1] frac_lut4_lut3_out ; -output [0:0] frac_lut4_lut4_out ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; - -wire [0:15] frac_lut4_0__undriven_sram_inv ; -wire [0:0] frac_lut4_0_mode ; -wire [0:15] frac_lut4_0_sram ; -supply1 VDD ; -supply0 VSS ; - -grid_clb_frac_lut4_1 frac_lut4_0_ ( .in ( frac_lut4_in ) , - .sram ( frac_lut4_0_sram ) , - .sram_inv ( frac_lut4_0__undriven_sram_inv ) , - .mode ( frac_lut4_0_mode ) , - .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , - .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_1 frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , - .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , - frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] , - frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , - frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , - frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , - frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_1 ( - prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , VDD , - VSS , p0 ) ; -input [0:0] prog_clk ; -input [0:3] frac_logic_in ; -input [0:0] ccff_head ; -output [0:1] frac_logic_out ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; -wire [0:1] mux_frac_logic_out_0_undriven_sram_inv ; -wire [0:1] mux_tree_size2_0_sram ; -supply1 VDD ; -supply0 VSS ; - -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( - .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , - .ccff_head ( ccff_head ) , - .frac_lut4_lut3_out ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] , - frac_logic_out[1] } ) , - - .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , - .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -grid_clb_mux_tree_size2_25 mux_frac_logic_out_0 ( - .in ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] - } ) , - .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_frac_logic_out_0_undriven_sram_inv ) , - .out ( frac_logic_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -grid_clb_mux_tree_size2_mem_25 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -grid_clb_direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( frac_logic_out[1] ) ) ; -grid_clb_direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( frac_logic_in[0] ) ) ; -grid_clb_direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( frac_logic_in[1] ) ) ; -grid_clb_direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( frac_logic_in[2] ) ) ; -grid_clb_direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( frac_logic_in[3] ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_1 ( - prog_clk , Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , - fabric_clk , ccff_head , fabric_out , fabric_regout , fabric_sc_out , - ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , p_abuf2 , p0 , p1 ) ; -input [0:0] prog_clk ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:3] fabric_in ; -input [0:0] fabric_regin ; -input [0:0] fabric_sc_in ; -input [0:0] fabric_clk ; -input [0:0] ccff_head ; -output [0:1] fabric_out ; -output [0:0] fabric_regout ; -output [0:0] fabric_sc_out ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; -output p_abuf0 ; -output p_abuf1 ; -output p_abuf2 ; -input p0 ; -input p1 ; - -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; -wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; -wire [0:1] mux_fabric_out_0_undriven_sram_inv ; -wire [0:1] mux_fabric_out_1_undriven_sram_inv ; -wire [0:1] mux_ff_0_D_0_undriven_sram_inv ; -wire [0:1] mux_tree_size2_0_sram ; -wire [0:1] mux_tree_size2_1_sram ; -wire [0:0] mux_tree_size2_2_out ; -wire [0:1] mux_tree_size2_2_sram ; -wire [0:0] mux_tree_size2_mem_0_ccff_tail ; -wire [0:0] mux_tree_size2_mem_1_ccff_tail ; -supply1 VDD ; -supply0 VSS ; - -assign fabric_regout[0] = fabric_sc_out[0] ; - -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( - .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , - .ccff_head ( ccff_head ) , - .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , - .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( - .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , - .ff_DI ( fabric_sc_in ) , - .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , - .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( - .Test_en ( Test_en ) , .clk ( clk ) , - .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , - .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , - .ff_Q ( fabric_sc_out ) , - .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -grid_clb_mux_tree_size2_3 mux_fabric_out_0 ( - .in ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] - } ) , - .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_fabric_out_0_undriven_sram_inv ) , - .out ( fabric_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p0 ( p0 ) ) ; -grid_clb_mux_tree_size2_4 mux_fabric_out_1 ( - .in ( { fabric_sc_out[0] , - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] - } ) , - .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( mux_fabric_out_1_undriven_sram_inv ) , - .out ( fabric_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf0 ( p_abuf2 ) , .p1 ( p1 ) ) ; -grid_clb_mux_tree_size2_5 mux_ff_0_D_0 ( - .in ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , - fabric_regin[0] } ) , - .sram ( mux_tree_size2_2_sram ) , - .sram_inv ( mux_ff_0_D_0_undriven_sram_inv ) , - .out ( mux_tree_size2_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -grid_clb_mux_tree_size2_mem_3 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -grid_clb_mux_tree_size2_mem_4 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_size2_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -grid_clb_mux_tree_size2_mem_5 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , - .mem_out ( mux_tree_size2_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -grid_clb_direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fabric_sc_out ) ) ; -grid_clb_direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fabric_sc_out ) ) ; -grid_clb_direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( fabric_in[0] ) ) ; -grid_clb_direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_6 } ) , - .out ( fabric_in[1] ) ) ; -grid_clb_direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_7 } ) , - .out ( fabric_in[2] ) ) ; -grid_clb_direct_interc direct_interc_5_ ( - .in ( { SYNOPSYS_UNCONNECTED_8 } ) , - .out ( fabric_in[3] ) ) ; -grid_clb_direct_interc direct_interc_6_ ( - .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( fabric_sc_in ) ) ; -grid_clb_direct_interc direct_interc_7_ ( - .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( fabric_clk ) ) ; -grid_clb_direct_interc direct_interc_8_ ( - .in ( { SYNOPSYS_UNCONNECTED_11 } ) , - - .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) ) ; -grid_clb_direct_interc direct_interc_9_ ( - .in ( { SYNOPSYS_UNCONNECTED_12 } ) , - - .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ) ; -grid_clb_direct_interc direct_interc_10_ ( - .in ( { SYNOPSYS_UNCONNECTED_13 } ) , - .out ( fabric_clk ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_1 ( prog_clk , Test_en , - clk , fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , - fle_regout , fle_sc_out , ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , - p_abuf2 , p0 , p1 ) ; -input [0:0] prog_clk ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:3] fle_in ; -input [0:0] fle_regin ; -input [0:0] fle_sc_in ; -input [0:0] fle_clk ; -input [0:0] ccff_head ; -output [0:1] fle_out ; -output [0:0] fle_regout ; -output [0:0] fle_sc_out ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; -output p_abuf0 ; -output p_abuf1 ; -output p_abuf2 ; -input p0 ; -input p1 ; - -supply1 VDD ; -supply0 VSS ; - -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( - .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , - .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , - .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , - .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , - .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p_abuf2 ( p_abuf2 ) , - .p0 ( p0 ) , .p1 ( p1 ) ) ; -grid_clb_direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( { p_abuf1 } ) ) ; -grid_clb_direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( fle_regout ) ) ; -grid_clb_direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fle_sc_out ) ) ; -grid_clb_direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fle_in[0] ) ) ; -grid_clb_direct_interc direct_interc_5_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( fle_in[1] ) ) ; -grid_clb_direct_interc direct_interc_6_ ( - .in ( { SYNOPSYS_UNCONNECTED_6 } ) , - .out ( fle_in[2] ) ) ; -grid_clb_direct_interc direct_interc_7_ ( - .in ( { SYNOPSYS_UNCONNECTED_7 } ) , - .out ( fle_in[3] ) ) ; -grid_clb_direct_interc direct_interc_8_ ( - .in ( { SYNOPSYS_UNCONNECTED_8 } ) , - .out ( fle_regin ) ) ; -grid_clb_direct_interc direct_interc_9_ ( - .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( fle_sc_in ) ) ; -grid_clb_direct_interc direct_interc_10_ ( - .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( fle_clk ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__22 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__21 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__20 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_2 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_1 ( in , sram , sram_inv , out , VDD , VSS , - p_abuf0 , p_abuf1 , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -output p_abuf0 ; -output p_abuf1 ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf1 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_64 ( .A ( p_abuf1 ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_65 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_0 ( in , sram , sram_inv , out , VDD , VSS , - p_abuf0 , p_abuf1 , p1 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -output p_abuf0 ; -output p_abuf1 ; -input p1 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf1 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_62 ( .A ( p_abuf1 ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_63 ( .A ( p_abuf1 ) , - .X ( BUF_net_63 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_131 ( .A ( BUF_net_63 ) , - .X ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( - Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk , VDD , VSS ) ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:0] ff_D ; -input [0:0] ff_DI ; -output [0:0] ff_Q ; -input [0:0] ff_clk ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , - .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( - Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk , VDD , VSS ) ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:0] ff_D ; -input [0:0] ff_DI ; -output [0:0] ff_Q ; -input [0:0] ff_clk ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , - .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_direct_interc ( in , out ) ; -input [0:0] in ; -output [0:0] out ; - -assign out[0] = in[0] ; -endmodule - - -module grid_clb_mux_tree_size2_mem_24 ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__19 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_24 ( in , sram , sram_inv , out , VDD , VSS , - p1 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p1 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_0 ( prog_clk , - ccff_head , ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:16] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_5_ ( .D ( mem_out[4] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_6_ ( .D ( mem_out[5] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_7_ ( .D ( mem_out[6] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_8_ ( .D ( mem_out[7] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_9_ ( .D ( mem_out[8] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_10_ ( .D ( mem_out[9] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_11_ ( .D ( mem_out[10] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_12_ ( .D ( mem_out[11] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_13_ ( .D ( mem_out[12] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_14_ ( .D ( mem_out[13] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_15_ ( .D ( mem_out[14] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_16_ ( .D ( mem_out[15] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__18 ( .A ( mem_out[16] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_frac_lut4_mux_0 ( in , sram , sram_inv , lut3_out , lut4_out , - VDD , VSS ) ; -input [0:15] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:1] lut3_out ; -output [0:0] lut4_out ; -input VDD ; -input VSS ; - -wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_4_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_5_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( - .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( - .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( - .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( - .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_6_ ( - .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__buf_2_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__buf_2_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__buf_2_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module grid_clb_frac_lut4_0 ( in , sram , sram_inv , mode , mode_inv , - lut3_out , lut4_out , VDD , VSS ) ; -input [0:3] in ; -input [0:15] sram ; -input [0:15] sram_inv ; -input [0:0] mode ; -input [0:0] mode_inv ; -output [0:1] lut3_out ; -output [0:0] lut4_out ; -input VDD ; -input VSS ; - -wire [0:0] sky130_fd_sc_hd__buf_2_0_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_1_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_2_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; -wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ; -wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ; -wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ; -wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ; -wire [0:0] sky130_fd_sc_hd__or2_1_0_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , - .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , - .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , - .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , - .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( - .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , - .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , - .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , - .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , - .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( - .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -grid_clb_frac_lut4_mux_0 frac_lut4_mux_0_ ( .in ( sram ) , - .sram ( { sky130_fd_sc_hd__buf_2_0_X[0] , sky130_fd_sc_hd__buf_2_1_X[0] , - sky130_fd_sc_hd__buf_2_2_X[0] , sky130_fd_sc_hd__buf_2_3_X[0] } ) , - .sram_inv ( { sky130_fd_sc_hd__inv_1_0_Y[0] , - sky130_fd_sc_hd__inv_1_1_Y[0] , sky130_fd_sc_hd__inv_1_2_Y[0] , - sky130_fd_sc_hd__inv_1_3_Y[0] } ) , - .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( - prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out , - frac_lut4_lut4_out , ccff_tail , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:3] frac_lut4_in ; -input [0:0] ccff_head ; -output [0:1] frac_lut4_lut3_out ; -output [0:0] frac_lut4_lut4_out ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; - -wire [0:15] frac_lut4_0__undriven_sram_inv ; -wire [0:0] frac_lut4_0_mode ; -wire [0:15] frac_lut4_0_sram ; -supply1 VDD ; -supply0 VSS ; - -grid_clb_frac_lut4_0 frac_lut4_0_ ( .in ( frac_lut4_in ) , - .sram ( frac_lut4_0_sram ) , - .sram_inv ( frac_lut4_0__undriven_sram_inv ) , - .mode ( frac_lut4_0_mode ) , - .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , - .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_0 frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , - .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , - frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] , - frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , - frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , - frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , - frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( - prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , VDD , - VSS , p1 ) ; -input [0:0] prog_clk ; -input [0:3] frac_logic_in ; -input [0:0] ccff_head ; -output [0:1] frac_logic_out ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; -input p1 ; - -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; -wire [0:1] mux_frac_logic_out_0_undriven_sram_inv ; -wire [0:1] mux_tree_size2_0_sram ; -supply1 VDD ; -supply0 VSS ; - -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( - .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , - .ccff_head ( ccff_head ) , - .frac_lut4_lut3_out ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] , - frac_logic_out[1] } ) , - - .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , - .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -grid_clb_mux_tree_size2_24 mux_frac_logic_out_0 ( - .in ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] - } ) , - .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_frac_logic_out_0_undriven_sram_inv ) , - .out ( frac_logic_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p1 ( p1 ) ) ; -grid_clb_mux_tree_size2_mem_24 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -grid_clb_direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( frac_logic_out[1] ) ) ; -grid_clb_direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( frac_logic_in[0] ) ) ; -grid_clb_direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( frac_logic_in[1] ) ) ; -grid_clb_direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( frac_logic_in[2] ) ) ; -grid_clb_direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( frac_logic_in[3] ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( - prog_clk , Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , - fabric_clk , ccff_head , fabric_out , fabric_regout , fabric_sc_out , - ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , p_abuf2 , p_abuf3 , p0 , p1 ) ; -input [0:0] prog_clk ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:3] fabric_in ; -input [0:0] fabric_regin ; -input [0:0] fabric_sc_in ; -input [0:0] fabric_clk ; -input [0:0] ccff_head ; -output [0:1] fabric_out ; -output [0:0] fabric_regout ; -output [0:0] fabric_sc_out ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; -output p_abuf0 ; -output p_abuf1 ; -output p_abuf2 ; -output p_abuf3 ; -input p0 ; -input p1 ; - -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; -wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; -wire [0:1] mux_fabric_out_0_undriven_sram_inv ; -wire [0:1] mux_fabric_out_1_undriven_sram_inv ; -wire [0:1] mux_ff_0_D_0_undriven_sram_inv ; -wire [0:1] mux_tree_size2_0_sram ; -wire [0:1] mux_tree_size2_1_sram ; -wire [0:0] mux_tree_size2_2_out ; -wire [0:1] mux_tree_size2_2_sram ; -wire [0:0] mux_tree_size2_mem_0_ccff_tail ; -wire [0:0] mux_tree_size2_mem_1_ccff_tail ; -supply1 VDD ; -supply0 VSS ; - -assign fabric_regout[0] = fabric_sc_out[0] ; - -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( - .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , - .ccff_head ( ccff_head ) , - .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , - .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p1 ( p1 ) ) ; -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( - .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , - .ff_DI ( fabric_sc_in ) , - .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , - .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( - .Test_en ( Test_en ) , .clk ( clk ) , - .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , - .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , - .ff_Q ( fabric_sc_out ) , - .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -grid_clb_mux_tree_size2_0 mux_fabric_out_0 ( - .in ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] - } ) , - .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_fabric_out_0_undriven_sram_inv ) , - .out ( fabric_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p1 ( p1 ) ) ; -grid_clb_mux_tree_size2_1 mux_fabric_out_1 ( - .in ( { fabric_sc_out[0] , - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] - } ) , - .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( mux_fabric_out_1_undriven_sram_inv ) , - .out ( fabric_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf0 ( p_abuf2 ) , .p_abuf1 ( p_abuf3 ) , .p0 ( p0 ) ) ; -grid_clb_mux_tree_size2_2 mux_ff_0_D_0 ( - .in ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , - fabric_regin[0] } ) , - .sram ( mux_tree_size2_2_sram ) , - .sram_inv ( mux_ff_0_D_0_undriven_sram_inv ) , - .out ( mux_tree_size2_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -grid_clb_mux_tree_size2_mem_0 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -grid_clb_mux_tree_size2_mem_1 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_size2_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -grid_clb_mux_tree_size2_mem_2 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , - .mem_out ( mux_tree_size2_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -grid_clb_direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fabric_sc_out ) ) ; -grid_clb_direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fabric_sc_out ) ) ; -grid_clb_direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( fabric_in[0] ) ) ; -grid_clb_direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_6 } ) , - .out ( fabric_in[1] ) ) ; -grid_clb_direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_7 } ) , - .out ( fabric_in[2] ) ) ; -grid_clb_direct_interc direct_interc_5_ ( - .in ( { SYNOPSYS_UNCONNECTED_8 } ) , - .out ( fabric_in[3] ) ) ; -grid_clb_direct_interc direct_interc_6_ ( - .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( fabric_sc_in ) ) ; -grid_clb_direct_interc direct_interc_7_ ( - .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( fabric_clk ) ) ; -grid_clb_direct_interc direct_interc_8_ ( - .in ( { SYNOPSYS_UNCONNECTED_11 } ) , - - .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) ) ; -grid_clb_direct_interc direct_interc_9_ ( - .in ( { SYNOPSYS_UNCONNECTED_12 } ) , - - .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ) ; -grid_clb_direct_interc direct_interc_10_ ( - .in ( { SYNOPSYS_UNCONNECTED_13 } ) , - .out ( fabric_clk ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_0 ( prog_clk , Test_en , - clk , fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , - fle_regout , fle_sc_out , ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , - p_abuf2 , p_abuf3 , p0 , p1 ) ; -input [0:0] prog_clk ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:3] fle_in ; -input [0:0] fle_regin ; -input [0:0] fle_sc_in ; -input [0:0] fle_clk ; -input [0:0] ccff_head ; -output [0:1] fle_out ; -output [0:0] fle_regout ; -output [0:0] fle_sc_out ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; -output p_abuf0 ; -output p_abuf1 ; -output p_abuf2 ; -output p_abuf3 ; -input p0 ; -input p1 ; - -supply1 VDD ; -supply0 VSS ; - -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( - .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , - .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , - .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , - .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , - .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p_abuf2 ( p_abuf2 ) , - .p_abuf3 ( p_abuf3 ) , .p0 ( p0 ) , .p1 ( p1 ) ) ; -grid_clb_direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( { p_abuf1 } ) ) ; -grid_clb_direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( { p_abuf3 } ) ) ; -grid_clb_direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fle_regout ) ) ; -grid_clb_direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fle_sc_out ) ) ; -grid_clb_direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( fle_in[0] ) ) ; -grid_clb_direct_interc direct_interc_5_ ( - .in ( { SYNOPSYS_UNCONNECTED_6 } ) , - .out ( fle_in[1] ) ) ; -grid_clb_direct_interc direct_interc_6_ ( - .in ( { SYNOPSYS_UNCONNECTED_7 } ) , - .out ( fle_in[2] ) ) ; -grid_clb_direct_interc direct_interc_7_ ( - .in ( { SYNOPSYS_UNCONNECTED_8 } ) , - .out ( fle_in[3] ) ) ; -grid_clb_direct_interc direct_interc_8_ ( - .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( fle_regin ) ) ; -grid_clb_direct_interc direct_interc_9_ ( - .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( fle_sc_in ) ) ; -grid_clb_direct_interc direct_interc_10_ ( - .in ( { SYNOPSYS_UNCONNECTED_11 } ) , - .out ( fle_clk ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_clb_ ( prog_clk , Test_en , clk , - clb_I0 , clb_I0i , clb_I1 , clb_I1i , clb_I2 , clb_I2i , clb_I3 , - clb_I3i , clb_I4 , clb_I4i , clb_I5 , clb_I5i , clb_I6 , clb_I6i , - clb_I7 , clb_I7i , clb_regin , clb_sc_in , clb_clk , ccff_head , clb_O , - clb_regout , clb_sc_out , ccff_tail , VDD , VSS , p_abuf0 , p_abuf3 , - p_abuf5 , p_abuf7 , p_abuf9 , p_abuf11 , p_abuf13 , p_abuf15 , p_abuf17 , - p_abuf19 , p_abuf21 , p_abuf23 , p_abuf25 , p_abuf27 , p_abuf29 , - p_abuf31 , p_abuf33 , p0 , p1 , p2 , p3 , p4 ) ; -input [0:0] prog_clk ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:2] clb_I0 ; -input [0:0] clb_I0i ; -input [0:2] clb_I1 ; -input [0:0] clb_I1i ; -input [0:2] clb_I2 ; -input [0:0] clb_I2i ; -input [0:2] clb_I3 ; -input [0:0] clb_I3i ; -input [0:2] clb_I4 ; -input [0:0] clb_I4i ; -input [0:2] clb_I5 ; -input [0:0] clb_I5i ; -input [0:2] clb_I6 ; -input [0:0] clb_I6i ; -input [0:2] clb_I7 ; -input [0:0] clb_I7i ; -input [0:0] clb_regin ; -input [0:0] clb_sc_in ; -input [0:0] clb_clk ; -input [0:0] ccff_head ; -output [0:15] clb_O ; -output [0:0] clb_regout ; -output [0:0] clb_sc_out ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; -output p_abuf0 ; -output p_abuf3 ; -output p_abuf5 ; -output p_abuf7 ; -output p_abuf9 ; -output p_abuf11 ; -output p_abuf13 ; -output p_abuf15 ; -output p_abuf17 ; -output p_abuf19 ; -output p_abuf21 ; -output p_abuf23 ; -output p_abuf25 ; -output p_abuf27 ; -output p_abuf29 ; -output p_abuf31 ; -output p_abuf33 ; -input p0 ; -input p1 ; -input p2 ; -input p3 ; -input p4 ; - -wire [0:0] logical_tile_clb_mode_default__fle_0_ccff_tail ; -wire [0:0] logical_tile_clb_mode_default__fle_0_fle_regout ; -wire [0:0] logical_tile_clb_mode_default__fle_0_fle_sc_out ; -wire [0:0] logical_tile_clb_mode_default__fle_1_ccff_tail ; -wire [0:0] logical_tile_clb_mode_default__fle_1_fle_regout ; -wire [0:0] logical_tile_clb_mode_default__fle_1_fle_sc_out ; -wire [0:0] logical_tile_clb_mode_default__fle_2_ccff_tail ; -wire [0:0] logical_tile_clb_mode_default__fle_2_fle_regout ; -wire [0:0] logical_tile_clb_mode_default__fle_2_fle_sc_out ; -wire [0:0] logical_tile_clb_mode_default__fle_3_ccff_tail ; -wire [0:0] logical_tile_clb_mode_default__fle_3_fle_regout ; -wire [0:0] logical_tile_clb_mode_default__fle_3_fle_sc_out ; -wire [0:0] logical_tile_clb_mode_default__fle_4_ccff_tail ; -wire [0:0] logical_tile_clb_mode_default__fle_4_fle_regout ; -wire [0:0] logical_tile_clb_mode_default__fle_4_fle_sc_out ; -wire [0:0] logical_tile_clb_mode_default__fle_5_ccff_tail ; -wire [0:0] logical_tile_clb_mode_default__fle_5_fle_regout ; -wire [0:0] logical_tile_clb_mode_default__fle_5_fle_sc_out ; -wire [0:0] logical_tile_clb_mode_default__fle_6_ccff_tail ; -wire [0:0] logical_tile_clb_mode_default__fle_6_fle_regout ; -wire [0:0] logical_tile_clb_mode_default__fle_6_fle_sc_out ; -supply1 VDD ; -supply0 VSS ; - -grid_clb_logical_tile_clb_mode_default__fle_0 logical_tile_clb_mode_default__fle_0 ( - .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fle_in ( { clb_I0[0] , clb_I0[1] , clb_I0[2] , clb_I0i[0] } ) , - .fle_regin ( clb_regin ) , .fle_sc_in ( clb_sc_in ) , - .fle_clk ( clb_clk ) , .ccff_head ( ccff_head ) , - .fle_out ( { clb_O[1] , clb_O[0] } ) , - .fle_regout ( logical_tile_clb_mode_default__fle_0_fle_regout ) , - .fle_sc_out ( logical_tile_clb_mode_default__fle_0_fle_sc_out ) , - .ccff_tail ( logical_tile_clb_mode_default__fle_0_ccff_tail ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf3 ) , - .p_abuf1 ( p_abuf4 ) , .p_abuf2 ( p_abuf5 ) , .p_abuf3 ( p_abuf6 ) , - .p0 ( p0 ) , .p1 ( p2 ) ) ; -grid_clb_logical_tile_clb_mode_default__fle_1 logical_tile_clb_mode_default__fle_1 ( - .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fle_in ( { clb_I1[0] , clb_I1[1] , clb_I1[2] , clb_I1i[0] } ) , - .fle_regin ( logical_tile_clb_mode_default__fle_0_fle_regout ) , - .fle_sc_in ( logical_tile_clb_mode_default__fle_0_fle_sc_out ) , - .fle_clk ( clb_clk ) , - .ccff_head ( logical_tile_clb_mode_default__fle_0_ccff_tail ) , - .fle_out ( { clb_O[3] , clb_O[2] } ) , - .fle_regout ( logical_tile_clb_mode_default__fle_1_fle_regout ) , - .fle_sc_out ( logical_tile_clb_mode_default__fle_1_fle_sc_out ) , - .ccff_tail ( logical_tile_clb_mode_default__fle_1_ccff_tail ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf7 ) , - .p_abuf1 ( p_abuf8 ) , .p_abuf2 ( p_abuf9 ) , .p0 ( p0 ) , .p1 ( p2 ) ) ; -grid_clb_logical_tile_clb_mode_default__fle_2 logical_tile_clb_mode_default__fle_2 ( - .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fle_in ( { clb_I2[0] , clb_I2[1] , clb_I2[2] , clb_I2i[0] } ) , - .fle_regin ( logical_tile_clb_mode_default__fle_1_fle_regout ) , - .fle_sc_in ( logical_tile_clb_mode_default__fle_1_fle_sc_out ) , - .fle_clk ( clb_clk ) , - .ccff_head ( logical_tile_clb_mode_default__fle_1_ccff_tail ) , - .fle_out ( { clb_O[5] , clb_O[4] } ) , - .fle_regout ( logical_tile_clb_mode_default__fle_2_fle_regout ) , - .fle_sc_out ( logical_tile_clb_mode_default__fle_2_fle_sc_out ) , - .ccff_tail ( logical_tile_clb_mode_default__fle_2_ccff_tail ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf11 ) , - .p_abuf1 ( p_abuf12 ) , .p_abuf2 ( p_abuf13 ) , .p_abuf3 ( p_abuf14 ) , - .p2 ( p3 ) ) ; -grid_clb_logical_tile_clb_mode_default__fle_3 logical_tile_clb_mode_default__fle_3 ( - .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fle_in ( { clb_I3[0] , clb_I3[1] , clb_I3[2] , clb_I3i[0] } ) , - .fle_regin ( logical_tile_clb_mode_default__fle_2_fle_regout ) , - .fle_sc_in ( logical_tile_clb_mode_default__fle_2_fle_sc_out ) , - .fle_clk ( clb_clk ) , - .ccff_head ( logical_tile_clb_mode_default__fle_2_ccff_tail ) , - .fle_out ( { clb_O[7] , clb_O[6] } ) , - .fle_regout ( logical_tile_clb_mode_default__fle_3_fle_regout ) , - .fle_sc_out ( logical_tile_clb_mode_default__fle_3_fle_sc_out ) , - .ccff_tail ( logical_tile_clb_mode_default__fle_3_ccff_tail ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf15 ) , - .p_abuf2 ( p_abuf17 ) , .p_abuf3 ( p_abuf18 ) , .p2 ( p3 ) ) ; -grid_clb_logical_tile_clb_mode_default__fle_4 logical_tile_clb_mode_default__fle_4 ( - .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fle_in ( { clb_I4[0] , clb_I4[1] , clb_I4[2] , clb_I4i[0] } ) , - .fle_regin ( logical_tile_clb_mode_default__fle_3_fle_regout ) , - .fle_sc_in ( logical_tile_clb_mode_default__fle_3_fle_sc_out ) , - .fle_clk ( clb_clk ) , - .ccff_head ( logical_tile_clb_mode_default__fle_3_ccff_tail ) , - .fle_out ( { clb_O[9] , clb_O[8] } ) , - .fle_regout ( logical_tile_clb_mode_default__fle_4_fle_regout ) , - .fle_sc_out ( logical_tile_clb_mode_default__fle_4_fle_sc_out ) , - .ccff_tail ( logical_tile_clb_mode_default__fle_4_ccff_tail ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf19 ) , - .p_abuf2 ( p_abuf21 ) , .p_abuf3 ( p_abuf22 ) , .p2 ( p3 ) , .p3 ( p4 ) ) ; -grid_clb_logical_tile_clb_mode_default__fle_5 logical_tile_clb_mode_default__fle_5 ( - .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fle_in ( { clb_I5[0] , clb_I5[1] , clb_I5[2] , clb_I5i[0] } ) , - .fle_regin ( logical_tile_clb_mode_default__fle_4_fle_regout ) , - .fle_sc_in ( logical_tile_clb_mode_default__fle_4_fle_sc_out ) , - .fle_clk ( clb_clk ) , - .ccff_head ( logical_tile_clb_mode_default__fle_4_ccff_tail ) , - .fle_out ( { clb_O[11] , clb_O[10] } ) , - .fle_regout ( logical_tile_clb_mode_default__fle_5_fle_regout ) , - .fle_sc_out ( logical_tile_clb_mode_default__fle_5_fle_sc_out ) , - .ccff_tail ( logical_tile_clb_mode_default__fle_5_ccff_tail ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf23 ) , - .p_abuf1 ( p_abuf24 ) , .p_abuf2 ( p_abuf25 ) , .p3 ( p4 ) ) ; -grid_clb_logical_tile_clb_mode_default__fle_6 logical_tile_clb_mode_default__fle_6 ( - .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fle_in ( { clb_I6[0] , clb_I6[1] , clb_I6[2] , clb_I6i[0] } ) , - .fle_regin ( logical_tile_clb_mode_default__fle_5_fle_regout ) , - .fle_sc_in ( logical_tile_clb_mode_default__fle_5_fle_sc_out ) , - .fle_clk ( clb_clk ) , - .ccff_head ( logical_tile_clb_mode_default__fle_5_ccff_tail ) , - .fle_out ( { clb_O[13] , clb_O[12] } ) , - .fle_regout ( logical_tile_clb_mode_default__fle_6_fle_regout ) , - .fle_sc_out ( logical_tile_clb_mode_default__fle_6_fle_sc_out ) , - .ccff_tail ( logical_tile_clb_mode_default__fle_6_ccff_tail ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf27 ) , - .p_abuf1 ( p_abuf28 ) , .p_abuf2 ( p_abuf29 ) , .p0 ( p1 ) , .p3 ( p4 ) ) ; -grid_clb_logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_7 ( - .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fle_in ( { clb_I7[0] , clb_I7[1] , clb_I7[2] , clb_I7i[0] } ) , - .fle_regin ( logical_tile_clb_mode_default__fle_6_fle_regout ) , - .fle_sc_in ( logical_tile_clb_mode_default__fle_6_fle_sc_out ) , - .fle_clk ( clb_clk ) , - .ccff_head ( logical_tile_clb_mode_default__fle_6_ccff_tail ) , - .fle_out ( { clb_O[15] , clb_O[14] } ) , - .fle_regout ( clb_regout ) , .fle_sc_out ( clb_sc_out ) , - .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p_abuf2 ( p_abuf2 ) , - .p_abuf3 ( p_abuf31 ) , .p_abuf5 ( p_abuf33 ) , .p_abuf6 ( p_abuf34 ) , - .p0 ( p1 ) ) ; -grid_clb_direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( { p_abuf6 } ) ) ; -grid_clb_direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( { p_abuf4 } ) ) ; -grid_clb_direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( { p_abuf8 } ) ) ; -grid_clb_direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( { p_abuf14 } ) ) ; -grid_clb_direct_interc direct_interc_5_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( { p_abuf12 } ) ) ; -grid_clb_direct_interc direct_interc_6_ ( - .in ( { SYNOPSYS_UNCONNECTED_6 } ) , - .out ( { p_abuf18 } ) ) ; -grid_clb_direct_interc direct_interc_8_ ( - .in ( { SYNOPSYS_UNCONNECTED_7 } ) , - .out ( { p_abuf22 } ) ) ; -grid_clb_direct_interc direct_interc_11_ ( - .in ( { SYNOPSYS_UNCONNECTED_8 } ) , - .out ( { p_abuf24 } ) ) ; -grid_clb_direct_interc direct_interc_13_ ( - .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( { p_abuf28 } ) ) ; -grid_clb_direct_interc direct_interc_14_ ( - .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( { p_abuf34 } ) ) ; -grid_clb_direct_interc direct_interc_16_ ( - .in ( { SYNOPSYS_UNCONNECTED_11 } ) , - .out ( { p_abuf1 } ) ) ; -grid_clb_direct_interc direct_interc_17_ ( - .in ( { SYNOPSYS_UNCONNECTED_12 } ) , - .out ( { p_abuf2 } ) ) ; -grid_clb_direct_interc direct_interc_18_ ( - .in ( { SYNOPSYS_UNCONNECTED_13 } ) , - .out ( clb_I0[0] ) ) ; -grid_clb_direct_interc direct_interc_19_ ( - .in ( { SYNOPSYS_UNCONNECTED_14 } ) , - .out ( clb_I0[1] ) ) ; -grid_clb_direct_interc direct_interc_20_ ( - .in ( { SYNOPSYS_UNCONNECTED_15 } ) , - .out ( clb_I0[2] ) ) ; -grid_clb_direct_interc direct_interc_21_ ( - .in ( { SYNOPSYS_UNCONNECTED_16 } ) , - .out ( clb_I0i ) ) ; -grid_clb_direct_interc direct_interc_22_ ( - .in ( { SYNOPSYS_UNCONNECTED_17 } ) , - .out ( clb_regin ) ) ; -grid_clb_direct_interc direct_interc_23_ ( - .in ( { SYNOPSYS_UNCONNECTED_18 } ) , - .out ( clb_sc_in ) ) ; -grid_clb_direct_interc direct_interc_24_ ( - .in ( { SYNOPSYS_UNCONNECTED_19 } ) , - .out ( clb_clk ) ) ; -grid_clb_direct_interc direct_interc_25_ ( - .in ( { SYNOPSYS_UNCONNECTED_20 } ) , - .out ( clb_I1[0] ) ) ; -grid_clb_direct_interc direct_interc_26_ ( - .in ( { SYNOPSYS_UNCONNECTED_21 } ) , - .out ( clb_I1[1] ) ) ; -grid_clb_direct_interc direct_interc_27_ ( - .in ( { SYNOPSYS_UNCONNECTED_22 } ) , - .out ( clb_I1[2] ) ) ; -grid_clb_direct_interc direct_interc_28_ ( - .in ( { SYNOPSYS_UNCONNECTED_23 } ) , - .out ( clb_I1i ) ) ; -grid_clb_direct_interc direct_interc_29_ ( - .in ( { SYNOPSYS_UNCONNECTED_24 } ) , - .out ( logical_tile_clb_mode_default__fle_0_fle_regout ) ) ; -grid_clb_direct_interc direct_interc_30_ ( - .in ( { SYNOPSYS_UNCONNECTED_25 } ) , - .out ( logical_tile_clb_mode_default__fle_0_fle_sc_out ) ) ; -grid_clb_direct_interc direct_interc_31_ ( - .in ( { SYNOPSYS_UNCONNECTED_26 } ) , - .out ( clb_clk ) ) ; -grid_clb_direct_interc direct_interc_32_ ( - .in ( { SYNOPSYS_UNCONNECTED_27 } ) , - .out ( clb_I2[0] ) ) ; -grid_clb_direct_interc direct_interc_33_ ( - .in ( { SYNOPSYS_UNCONNECTED_28 } ) , - .out ( clb_I2[1] ) ) ; -grid_clb_direct_interc direct_interc_34_ ( - .in ( { SYNOPSYS_UNCONNECTED_29 } ) , - .out ( clb_I2[2] ) ) ; -grid_clb_direct_interc direct_interc_35_ ( - .in ( { SYNOPSYS_UNCONNECTED_30 } ) , - .out ( clb_I2i ) ) ; -grid_clb_direct_interc direct_interc_36_ ( - .in ( { SYNOPSYS_UNCONNECTED_31 } ) , - .out ( logical_tile_clb_mode_default__fle_1_fle_regout ) ) ; -grid_clb_direct_interc direct_interc_37_ ( - .in ( { SYNOPSYS_UNCONNECTED_32 } ) , - .out ( logical_tile_clb_mode_default__fle_1_fle_sc_out ) ) ; -grid_clb_direct_interc direct_interc_38_ ( - .in ( { SYNOPSYS_UNCONNECTED_33 } ) , - .out ( clb_clk ) ) ; -grid_clb_direct_interc direct_interc_39_ ( - .in ( { SYNOPSYS_UNCONNECTED_34 } ) , - .out ( clb_I3[0] ) ) ; -grid_clb_direct_interc direct_interc_40_ ( - .in ( { SYNOPSYS_UNCONNECTED_35 } ) , - .out ( clb_I3[1] ) ) ; -grid_clb_direct_interc direct_interc_41_ ( - .in ( { SYNOPSYS_UNCONNECTED_36 } ) , - .out ( clb_I3[2] ) ) ; -grid_clb_direct_interc direct_interc_42_ ( - .in ( { SYNOPSYS_UNCONNECTED_37 } ) , - .out ( clb_I3i ) ) ; -grid_clb_direct_interc direct_interc_43_ ( - .in ( { SYNOPSYS_UNCONNECTED_38 } ) , - .out ( logical_tile_clb_mode_default__fle_2_fle_regout ) ) ; -grid_clb_direct_interc direct_interc_44_ ( - .in ( { SYNOPSYS_UNCONNECTED_39 } ) , - .out ( logical_tile_clb_mode_default__fle_2_fle_sc_out ) ) ; -grid_clb_direct_interc direct_interc_45_ ( - .in ( { SYNOPSYS_UNCONNECTED_40 } ) , - .out ( clb_clk ) ) ; -grid_clb_direct_interc direct_interc_46_ ( - .in ( { SYNOPSYS_UNCONNECTED_41 } ) , - .out ( clb_I4[0] ) ) ; -grid_clb_direct_interc direct_interc_47_ ( - .in ( { SYNOPSYS_UNCONNECTED_42 } ) , - .out ( clb_I4[1] ) ) ; -grid_clb_direct_interc direct_interc_48_ ( - .in ( { SYNOPSYS_UNCONNECTED_43 } ) , - .out ( clb_I4[2] ) ) ; -grid_clb_direct_interc direct_interc_49_ ( - .in ( { SYNOPSYS_UNCONNECTED_44 } ) , - .out ( clb_I4i ) ) ; -grid_clb_direct_interc direct_interc_50_ ( - .in ( { SYNOPSYS_UNCONNECTED_45 } ) , - .out ( logical_tile_clb_mode_default__fle_3_fle_regout ) ) ; -grid_clb_direct_interc direct_interc_51_ ( - .in ( { SYNOPSYS_UNCONNECTED_46 } ) , - .out ( logical_tile_clb_mode_default__fle_3_fle_sc_out ) ) ; -grid_clb_direct_interc direct_interc_52_ ( - .in ( { SYNOPSYS_UNCONNECTED_47 } ) , - .out ( clb_clk ) ) ; -grid_clb_direct_interc direct_interc_53_ ( - .in ( { SYNOPSYS_UNCONNECTED_48 } ) , - .out ( clb_I5[0] ) ) ; -grid_clb_direct_interc direct_interc_54_ ( - .in ( { SYNOPSYS_UNCONNECTED_49 } ) , - .out ( clb_I5[1] ) ) ; -grid_clb_direct_interc direct_interc_55_ ( - .in ( { SYNOPSYS_UNCONNECTED_50 } ) , - .out ( clb_I5[2] ) ) ; -grid_clb_direct_interc direct_interc_56_ ( - .in ( { SYNOPSYS_UNCONNECTED_51 } ) , - .out ( clb_I5i ) ) ; -grid_clb_direct_interc direct_interc_57_ ( - .in ( { SYNOPSYS_UNCONNECTED_52 } ) , - .out ( logical_tile_clb_mode_default__fle_4_fle_regout ) ) ; -grid_clb_direct_interc direct_interc_58_ ( - .in ( { SYNOPSYS_UNCONNECTED_53 } ) , - .out ( logical_tile_clb_mode_default__fle_4_fle_sc_out ) ) ; -grid_clb_direct_interc direct_interc_59_ ( - .in ( { SYNOPSYS_UNCONNECTED_54 } ) , - .out ( clb_clk ) ) ; -grid_clb_direct_interc direct_interc_60_ ( - .in ( { SYNOPSYS_UNCONNECTED_55 } ) , - .out ( clb_I6[0] ) ) ; -grid_clb_direct_interc direct_interc_61_ ( - .in ( { SYNOPSYS_UNCONNECTED_56 } ) , - .out ( clb_I6[1] ) ) ; -grid_clb_direct_interc direct_interc_62_ ( - .in ( { SYNOPSYS_UNCONNECTED_57 } ) , - .out ( clb_I6[2] ) ) ; -grid_clb_direct_interc direct_interc_63_ ( - .in ( { SYNOPSYS_UNCONNECTED_58 } ) , - .out ( clb_I6i ) ) ; -grid_clb_direct_interc direct_interc_64_ ( - .in ( { SYNOPSYS_UNCONNECTED_59 } ) , - .out ( logical_tile_clb_mode_default__fle_5_fle_regout ) ) ; -grid_clb_direct_interc direct_interc_65_ ( - .in ( { SYNOPSYS_UNCONNECTED_60 } ) , - .out ( logical_tile_clb_mode_default__fle_5_fle_sc_out ) ) ; -grid_clb_direct_interc direct_interc_66_ ( - .in ( { SYNOPSYS_UNCONNECTED_61 } ) , - .out ( clb_clk ) ) ; -grid_clb_direct_interc direct_interc_67_ ( - .in ( { SYNOPSYS_UNCONNECTED_62 } ) , - .out ( clb_I7[0] ) ) ; -grid_clb_direct_interc direct_interc_68_ ( - .in ( { SYNOPSYS_UNCONNECTED_63 } ) , - .out ( clb_I7[1] ) ) ; -grid_clb_direct_interc direct_interc_69_ ( - .in ( { SYNOPSYS_UNCONNECTED_64 } ) , - .out ( clb_I7[2] ) ) ; -grid_clb_direct_interc direct_interc_70_ ( - .in ( { SYNOPSYS_UNCONNECTED_65 } ) , - .out ( clb_I7i ) ) ; -grid_clb_direct_interc direct_interc_71_ ( - .in ( { SYNOPSYS_UNCONNECTED_66 } ) , - .out ( logical_tile_clb_mode_default__fle_6_fle_regout ) ) ; -grid_clb_direct_interc direct_interc_72_ ( - .in ( { SYNOPSYS_UNCONNECTED_67 } ) , - .out ( logical_tile_clb_mode_default__fle_6_fle_sc_out ) ) ; -grid_clb_direct_interc direct_interc_73_ ( - .in ( { SYNOPSYS_UNCONNECTED_68 } ) , - .out ( clb_clk ) ) ; -endmodule - - -module grid_clb ( prog_clk , Test_en , clk , top_width_0_height_0__pin_0_ , - top_width_0_height_0__pin_1_ , top_width_0_height_0__pin_2_ , - top_width_0_height_0__pin_3_ , top_width_0_height_0__pin_4_ , - top_width_0_height_0__pin_5_ , top_width_0_height_0__pin_6_ , - top_width_0_height_0__pin_7_ , top_width_0_height_0__pin_8_ , - top_width_0_height_0__pin_9_ , top_width_0_height_0__pin_10_ , - top_width_0_height_0__pin_11_ , top_width_0_height_0__pin_12_ , - top_width_0_height_0__pin_13_ , top_width_0_height_0__pin_14_ , - top_width_0_height_0__pin_15_ , top_width_0_height_0__pin_32_ , - top_width_0_height_0__pin_33_ , right_width_0_height_0__pin_16_ , - right_width_0_height_0__pin_17_ , right_width_0_height_0__pin_18_ , - right_width_0_height_0__pin_19_ , right_width_0_height_0__pin_20_ , - right_width_0_height_0__pin_21_ , right_width_0_height_0__pin_22_ , - right_width_0_height_0__pin_23_ , right_width_0_height_0__pin_24_ , - right_width_0_height_0__pin_25_ , right_width_0_height_0__pin_26_ , - right_width_0_height_0__pin_27_ , right_width_0_height_0__pin_28_ , - right_width_0_height_0__pin_29_ , right_width_0_height_0__pin_30_ , - right_width_0_height_0__pin_31_ , left_width_0_height_0__pin_52_ , - ccff_head , top_width_0_height_0__pin_34_upper , - top_width_0_height_0__pin_34_lower , top_width_0_height_0__pin_35_upper , - top_width_0_height_0__pin_35_lower , top_width_0_height_0__pin_36_upper , - top_width_0_height_0__pin_36_lower , top_width_0_height_0__pin_37_upper , - top_width_0_height_0__pin_37_lower , top_width_0_height_0__pin_38_upper , - top_width_0_height_0__pin_38_lower , top_width_0_height_0__pin_39_upper , - top_width_0_height_0__pin_39_lower , top_width_0_height_0__pin_40_upper , - top_width_0_height_0__pin_40_lower , top_width_0_height_0__pin_41_upper , - top_width_0_height_0__pin_41_lower , - right_width_0_height_0__pin_42_upper , - right_width_0_height_0__pin_42_lower , - right_width_0_height_0__pin_43_upper , - right_width_0_height_0__pin_43_lower , - right_width_0_height_0__pin_44_upper , - right_width_0_height_0__pin_44_lower , - right_width_0_height_0__pin_45_upper , - right_width_0_height_0__pin_45_lower , - right_width_0_height_0__pin_46_upper , - right_width_0_height_0__pin_46_lower , - right_width_0_height_0__pin_47_upper , - right_width_0_height_0__pin_47_lower , - right_width_0_height_0__pin_48_upper , - right_width_0_height_0__pin_48_lower , - right_width_0_height_0__pin_49_upper , - right_width_0_height_0__pin_49_lower , bottom_width_0_height_0__pin_50_ , - bottom_width_0_height_0__pin_51_ , ccff_tail , SC_IN_TOP , SC_IN_BOT , - SC_OUT_TOP , SC_OUT_BOT , VDD , VSS , prog_clk__FEEDTHRU_1 , - prog_clk__FEEDTHRU_2 , prog_clk__FEEDTHRU_3 , prog_clk__FEEDTHRU_4 , - Test_en__FEEDTHRU_1 , clk__FEEDTHRU_1 ) ; -input [0:0] prog_clk ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:0] top_width_0_height_0__pin_0_ ; -input [0:0] top_width_0_height_0__pin_1_ ; -input [0:0] top_width_0_height_0__pin_2_ ; -input [0:0] top_width_0_height_0__pin_3_ ; -input [0:0] top_width_0_height_0__pin_4_ ; -input [0:0] top_width_0_height_0__pin_5_ ; -input [0:0] top_width_0_height_0__pin_6_ ; -input [0:0] top_width_0_height_0__pin_7_ ; -input [0:0] top_width_0_height_0__pin_8_ ; -input [0:0] top_width_0_height_0__pin_9_ ; -input [0:0] top_width_0_height_0__pin_10_ ; -input [0:0] top_width_0_height_0__pin_11_ ; -input [0:0] top_width_0_height_0__pin_12_ ; -input [0:0] top_width_0_height_0__pin_13_ ; -input [0:0] top_width_0_height_0__pin_14_ ; -input [0:0] top_width_0_height_0__pin_15_ ; -input [0:0] top_width_0_height_0__pin_32_ ; -input [0:0] top_width_0_height_0__pin_33_ ; -input [0:0] right_width_0_height_0__pin_16_ ; -input [0:0] right_width_0_height_0__pin_17_ ; -input [0:0] right_width_0_height_0__pin_18_ ; -input [0:0] right_width_0_height_0__pin_19_ ; -input [0:0] right_width_0_height_0__pin_20_ ; -input [0:0] right_width_0_height_0__pin_21_ ; -input [0:0] right_width_0_height_0__pin_22_ ; -input [0:0] right_width_0_height_0__pin_23_ ; -input [0:0] right_width_0_height_0__pin_24_ ; -input [0:0] right_width_0_height_0__pin_25_ ; -input [0:0] right_width_0_height_0__pin_26_ ; -input [0:0] right_width_0_height_0__pin_27_ ; -input [0:0] right_width_0_height_0__pin_28_ ; -input [0:0] right_width_0_height_0__pin_29_ ; -input [0:0] right_width_0_height_0__pin_30_ ; -input [0:0] right_width_0_height_0__pin_31_ ; -input [0:0] left_width_0_height_0__pin_52_ ; -input [0:0] ccff_head ; -output [0:0] top_width_0_height_0__pin_34_upper ; -output [0:0] top_width_0_height_0__pin_34_lower ; -output [0:0] top_width_0_height_0__pin_35_upper ; -output [0:0] top_width_0_height_0__pin_35_lower ; -output [0:0] top_width_0_height_0__pin_36_upper ; -output [0:0] top_width_0_height_0__pin_36_lower ; -output [0:0] top_width_0_height_0__pin_37_upper ; -output [0:0] top_width_0_height_0__pin_37_lower ; -output [0:0] top_width_0_height_0__pin_38_upper ; -output [0:0] top_width_0_height_0__pin_38_lower ; -output [0:0] top_width_0_height_0__pin_39_upper ; -output [0:0] top_width_0_height_0__pin_39_lower ; -output [0:0] top_width_0_height_0__pin_40_upper ; -output [0:0] top_width_0_height_0__pin_40_lower ; -output [0:0] top_width_0_height_0__pin_41_upper ; -output [0:0] top_width_0_height_0__pin_41_lower ; -output [0:0] right_width_0_height_0__pin_42_upper ; -output [0:0] right_width_0_height_0__pin_42_lower ; -output [0:0] right_width_0_height_0__pin_43_upper ; -output [0:0] right_width_0_height_0__pin_43_lower ; -output [0:0] right_width_0_height_0__pin_44_upper ; -output [0:0] right_width_0_height_0__pin_44_lower ; -output [0:0] right_width_0_height_0__pin_45_upper ; -output [0:0] right_width_0_height_0__pin_45_lower ; -output [0:0] right_width_0_height_0__pin_46_upper ; -output [0:0] right_width_0_height_0__pin_46_lower ; -output [0:0] right_width_0_height_0__pin_47_upper ; -output [0:0] right_width_0_height_0__pin_47_lower ; -output [0:0] right_width_0_height_0__pin_48_upper ; -output [0:0] right_width_0_height_0__pin_48_lower ; -output [0:0] right_width_0_height_0__pin_49_upper ; -output [0:0] right_width_0_height_0__pin_49_lower ; -output [0:0] bottom_width_0_height_0__pin_50_ ; -output [0:0] bottom_width_0_height_0__pin_51_ ; -output [0:0] ccff_tail ; -input SC_IN_TOP ; -input SC_IN_BOT ; -output SC_OUT_TOP ; -output SC_OUT_BOT ; -input VDD ; -input VSS ; -output [0:0] prog_clk__FEEDTHRU_1 ; -output [0:0] prog_clk__FEEDTHRU_2 ; -output [0:0] prog_clk__FEEDTHRU_3 ; -output [0:0] prog_clk__FEEDTHRU_4 ; -output [0:0] Test_en__FEEDTHRU_1 ; -output [0:0] clk__FEEDTHRU_1 ; - -wire ropt_net_156 ; -wire ropt_net_153 ; -wire ropt_net_151 ; -wire ropt_net_150 ; -wire ropt_net_167 ; -wire ropt_net_154 ; -wire ropt_net_168 ; -wire ropt_net_152 ; -wire ropt_net_163 ; -wire ropt_net_162 ; -supply1 VDD ; -supply0 VSS ; - -assign SC_IN_TOP = SC_IN_BOT ; -assign prog_clk__FEEDTHRU_2[0] = prog_clk__FEEDTHRU_4[0] ; -assign prog_clk__FEEDTHRU_3[0] = prog_clk__FEEDTHRU_4[0] ; - -grid_clb_logical_tile_clb_mode_clb_ logical_tile_clb_mode_clb__0 ( - .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .clb_I0 ( { top_width_0_height_0__pin_0_[0] , - top_width_0_height_0__pin_1_[0] , top_width_0_height_0__pin_2_[0] } ) , - .clb_I0i ( top_width_0_height_0__pin_3_ ) , - .clb_I1 ( { top_width_0_height_0__pin_4_[0] , - top_width_0_height_0__pin_5_[0] , top_width_0_height_0__pin_6_[0] } ) , - .clb_I1i ( top_width_0_height_0__pin_7_ ) , - .clb_I2 ( { top_width_0_height_0__pin_8_[0] , - top_width_0_height_0__pin_9_[0] , top_width_0_height_0__pin_10_[0] } ) , - .clb_I2i ( top_width_0_height_0__pin_11_ ) , - .clb_I3 ( { top_width_0_height_0__pin_12_[0] , - top_width_0_height_0__pin_13_[0] , top_width_0_height_0__pin_14_[0] } ) , - .clb_I3i ( top_width_0_height_0__pin_15_ ) , - .clb_I4 ( { right_width_0_height_0__pin_16_[0] , - right_width_0_height_0__pin_17_[0] , - right_width_0_height_0__pin_18_[0] } ) , - .clb_I4i ( right_width_0_height_0__pin_19_ ) , - .clb_I5 ( { right_width_0_height_0__pin_20_[0] , - right_width_0_height_0__pin_21_[0] , - right_width_0_height_0__pin_22_[0] } ) , - .clb_I5i ( right_width_0_height_0__pin_23_ ) , - .clb_I6 ( { right_width_0_height_0__pin_24_[0] , - right_width_0_height_0__pin_25_[0] , - right_width_0_height_0__pin_26_[0] } ) , - .clb_I6i ( right_width_0_height_0__pin_27_ ) , - .clb_I7 ( { right_width_0_height_0__pin_28_[0] , - right_width_0_height_0__pin_29_[0] , - right_width_0_height_0__pin_30_[0] } ) , - .clb_I7i ( right_width_0_height_0__pin_31_ ) , - .clb_regin ( top_width_0_height_0__pin_32_ ) , - .clb_sc_in ( { SC_IN_BOT } ) , - .clb_clk ( left_width_0_height_0__pin_52_ ) , .ccff_head ( ccff_head ) , - .clb_O ( { aps_rename_138_ , aps_rename_139_ , - top_width_0_height_0__pin_36_lower[0] , aps_rename_142_ , - aps_rename_144_ , aps_rename_145_ , aps_rename_146_ , - top_width_0_height_0__pin_41_lower[0] , aps_rename_148_ , - aps_rename_150_ , aps_rename_151_ , aps_rename_153_ , - aps_rename_154_ , aps_rename_156_ , aps_rename_157_ , - aps_rename_158_ } ) , - .clb_regout ( { ropt_net_161 } ) , - .clb_sc_out ( { aps_rename_160_ } ) , - .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf0 ( ropt_net_162 ) , - .p_abuf3 ( top_width_0_height_0__pin_35_upper[0] ) , - .p_abuf5 ( top_width_0_height_0__pin_34_upper[0] ) , - .p_abuf7 ( ropt_net_156 ) , - .p_abuf9 ( top_width_0_height_0__pin_36_upper[0] ) , - .p_abuf11 ( ropt_net_151 ) , .p_abuf13 ( ropt_net_153 ) , - .p_abuf15 ( top_width_0_height_0__pin_41_upper[0] ) , - .p_abuf17 ( top_width_0_height_0__pin_40_upper[0] ) , - .p_abuf19 ( ropt_net_167 ) , .p_abuf21 ( ropt_net_150 ) , - .p_abuf23 ( ropt_net_168 ) , .p_abuf25 ( ropt_net_154 ) , - .p_abuf27 ( ropt_net_152 ) , - .p_abuf29 ( right_width_0_height_0__pin_46_upper[0] ) , - .p_abuf31 ( right_width_0_height_0__pin_49_upper[0] ) , - .p_abuf33 ( ropt_net_163 ) , .p0 ( optlc_net_137 ) , - .p1 ( optlc_net_138 ) , .p2 ( optlc_net_139 ) , .p3 ( optlc_net_140 ) , - .p4 ( optlc_net_141 ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1188 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1189 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1190 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1191 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1192 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1193 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1194 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1195 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1196 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1197 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1198 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1199 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1200 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1201 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1202 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1203 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1204 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1205 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1206 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1207 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1208 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1209 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1210 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1211 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1212 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1213 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1214 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1215 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1216 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1217 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1218 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1219 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1220 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1221 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1222 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1223 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1224 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1225 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( Test_en[0] ) , - .X ( ropt_net_166 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_2 \clk[0]_bip538 ( .A ( clk[0] ) , - .X ( ctsbuf_net_1142 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_989 ( .A ( ropt_net_167 ) , - .X ( right_width_0_height_0__pin_43_upper[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_137 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_137 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__4 ( .A ( aps_rename_142_ ) , - .X ( aps_rename_143_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_139 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_138 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_141 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_139 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__clkbuf_1 \prog_clk[0]_bip539 ( .A ( prog_clk[0] ) , - .X ( ctsbuf_net_6147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_143 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_990 ( .A ( ropt_net_168 ) , - .X ( right_width_0_height_0__pin_45_upper[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_145 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , - .HI ( optlc_net_141 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__11 ( .A ( aps_rename_151_ ) , - .X ( aps_rename_152_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_955 ( .A ( ropt_net_148 ) , - .X ( top_width_0_height_0__pin_38_lower[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__13 ( .A ( aps_rename_154_ ) , - .X ( aps_rename_155_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_364903 ( .A ( ctsbuf_net_1142 ) , - .X ( clk__FEEDTHRU_1[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_956 ( .A ( ropt_net_149 ) , - .X ( top_width_0_height_0__pin_39_lower[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__16 ( .A ( aps_rename_158_ ) , - .X ( aps_rename_159_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__17 ( .A ( aps_rename_160_ ) , - .X ( ropt_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_94 ( .A ( aps_rename_138_ ) , - .X ( BUF_net_94 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_95 ( .A ( aps_rename_139_ ) , - .X ( BUF_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_957 ( .A ( ropt_net_150 ) , - .X ( right_width_0_height_0__pin_42_upper[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_97 ( .A ( aps_rename_143_ ) , - .X ( top_width_0_height_0__pin_37_lower[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_98 ( .A ( aps_rename_144_ ) , - .X ( ropt_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_99 ( .A ( aps_rename_145_ ) , - .X ( ropt_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_100 ( .A ( aps_rename_146_ ) , - .X ( BUF_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_958 ( .A ( ropt_net_151 ) , - .X ( top_width_0_height_0__pin_39_upper[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_959 ( .A ( ropt_net_152 ) , - .X ( right_width_0_height_0__pin_47_upper[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_103 ( .A ( aps_rename_150_ ) , - .X ( BUF_net_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 cts_buf_389928 ( .A ( prog_clk__FEEDTHRU_4[0] ) , - .X ( prog_clk__FEEDTHRU_1[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_12 cts_buf_393932 ( .A ( ctsbuf_net_6147 ) , - .X ( prog_clk__FEEDTHRU_4[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_960 ( .A ( ropt_net_153 ) , - .X ( top_width_0_height_0__pin_38_upper[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_964 ( .A ( ropt_net_154 ) , - .X ( right_width_0_height_0__pin_44_upper[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_994 ( .A ( ropt_net_169 ) , - .X ( right_width_0_height_0__pin_49_lower[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_965 ( .A ( aps_rename_156_ ) , - .X ( right_width_0_height_0__pin_47_lower[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_966 ( .A ( ropt_net_156 ) , - .X ( top_width_0_height_0__pin_37_upper[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_968 ( .A ( ropt_net_157 ) , - .X ( ropt_net_172 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_116 ( .A ( aps_rename_152_ ) , - .X ( right_width_0_height_0__pin_44_lower[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_998 ( .A ( ropt_net_170 ) , - .X ( right_width_0_height_0__pin_48_upper[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_118 ( .A ( aps_rename_155_ ) , - .X ( right_width_0_height_0__pin_46_lower[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_999 ( .A ( ropt_net_171 ) , - .X ( right_width_0_height_0__pin_48_lower[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_120 ( .A ( aps_rename_157_ ) , - .X ( ropt_net_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_121 ( .A ( aps_rename_159_ ) , - .X ( ropt_net_164 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_126 ( .A ( BUF_net_94 ) , - .X ( top_width_0_height_0__pin_34_lower[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_127 ( .A ( BUF_net_95 ) , - .X ( top_width_0_height_0__pin_35_lower[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_128 ( .A ( BUF_net_100 ) , - .X ( ropt_net_174 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_969 ( .A ( aps_rename_153_ ) , - .X ( right_width_0_height_0__pin_45_lower[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_132 ( .A ( aps_rename_148_ ) , - .X ( ropt_net_159 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_1004 ( .A ( ropt_net_172 ) , - .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_972 ( .A ( ropt_net_159 ) , - .X ( right_width_0_height_0__pin_42_lower[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_974 ( .A ( BUF_net_103 ) , - .X ( right_width_0_height_0__pin_43_lower[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_978 ( .A ( ropt_net_161 ) , - .X ( ropt_net_173 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_984 ( .A ( ropt_net_162 ) , - .X ( SC_OUT_TOP ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_985 ( .A ( ropt_net_163 ) , - .X ( ropt_net_170 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_986 ( .A ( ropt_net_164 ) , - .X ( ropt_net_169 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_987 ( .A ( ropt_net_165 ) , - .X ( ropt_net_171 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_988 ( .A ( ropt_net_166 ) , - .X ( Test_en__FEEDTHRU_1[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_1005 ( .A ( ropt_net_173 ) , - .X ( bottom_width_0_height_0__pin_50_[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_1007 ( .A ( ropt_net_174 ) , - .X ( top_width_0_height_0__pin_40_lower[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y0 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x924600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x961400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x998200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1035000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1071800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1108600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1145400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1163800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1173000y0 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x248400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x285200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x611800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x630200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x860200y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x73600y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x151800y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x496800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x579600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x588800y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x823400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1035000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1136200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1173000y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x101200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x243800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x326600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x335800y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x409400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x460000y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x506000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x565800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x584200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x101200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x193200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x211600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x220800y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x299000y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x542800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x625600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x634800y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1012000y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x101200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x119600y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x239200y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x317400y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x363400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x391000y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x515200y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x142600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x161000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x335800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x354200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x717600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x736000y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x851000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1012000y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x101200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x262200y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x299000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x441600y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x487600y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x800400y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x41400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x59800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x69000y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x230000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x262200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x271400y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x570400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x579600y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x887800y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x340400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x667000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x726800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x864800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x952200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x961400y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1044200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1062600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1071800y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x55200y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x133400y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x432400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x469200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x639400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x690000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x708400y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x791200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x828000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x887800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x979800y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1058000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1099400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1136200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1173000y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x101200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x225400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x276000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x400200y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x519800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x611800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x621000y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x989000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1113200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x101200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x184000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x193200y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x239200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x731400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x768200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x851000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x901600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x920000y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x966000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x984400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1067200y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1104000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1140800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x101200y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x179400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x188600y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x308200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x464600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x552000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x837200y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1099400y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x55200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x64400y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x147200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x165600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x216200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x266800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x285200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x335800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x354200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x437000y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x478400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x496800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x579600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x598000y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x717600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x887800y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x933800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x984400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1044200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1117800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x607200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x703800y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x749800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x800400y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x837200y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x883200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x933800y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x174800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x230000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x239200y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x317400y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x920000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x970600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x979800y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1025800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1035000y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1113200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x101200y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x598000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x105800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x142600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x151800y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x312800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x524400y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x602600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x611800y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x657800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x676200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x979800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x92000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x174800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x193200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x243800y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x331200y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x736000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x754400y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x832600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x851000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x860200y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x933800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1048800y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1094800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1131600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x174800y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x441600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x538200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x556600y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x634800y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x713000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x818800y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x860200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x887800y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x933800y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x979800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1012000y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1053400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1090200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1136200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1173000y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x101200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x138000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x230000y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x248400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x271400y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x349600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x400200y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x529000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x561200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x579600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x662400y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x740600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x759000y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x777400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x795800y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1044200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1053400y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1099400y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1136200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1173000y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x253000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x289800y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x483000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x492200y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x570400y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x731400y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x846400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x864800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x887800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x952200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x970600y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1016600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1067200y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1145400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1163800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1173000y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x92000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x101200y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x179400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x230000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x432400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x450800y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x529000y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x607200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x690000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x993600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1012000y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1090200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1108600y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x101200y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x188600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x271400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x322000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x331200y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x418600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x483000y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x506000y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x584200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x593400y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x722200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x740600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x823400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x860200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1117800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1154600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1173000y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x105800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x124200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x133400y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x220800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x230000y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x400200y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x501400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x552000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x602600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x621000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x630200y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x671600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x690000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x699200y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x786600y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x864800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x883200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x892400y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1085600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1104000y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1145400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1163800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1173000y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x464600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x483000y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x644000y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x731400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x749800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x759000y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1062600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1071800y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x188600y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x234600y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x349600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x713000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x156400y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x335800y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x473800y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x552000y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x630200y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x786600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x823400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x832600y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x929200y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1016600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1099400y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x101200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x138000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x147200y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x239200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x248400y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x303600y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x506000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x524400y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x685400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x924600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x317400y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x855600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x929200y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x101200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x119600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x128800y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x174800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x427800y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y870400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x496800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x515200y870400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x556600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x713000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1035000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1053400y870400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x285200y897600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x345000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x409400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x460000y897600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x538200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x584200y897600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x602600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x625600y897600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x703800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x795800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x814200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x823400y897600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x510600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x754400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x763600y924800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1090200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1099400y924800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y952000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x924600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x961400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x998200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1035000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1071800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1108600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1145400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1163800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1173000y952000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module fpga_core ( prog_clk , Test_en , clk , gfpga_pad_EMBEDDED_IO_SOC_IN , - gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , - ccff_head , ccff_tail , sc_head , sc_tail , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:17] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:17] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:17] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -input sc_head ; -output sc_tail ; -input VDD ; -input VSS ; - -wire [0:0] cbx_1__0__0_bottom_grid_pin_0_ ; -wire [0:0] cbx_1__0__0_bottom_grid_pin_10_ ; -wire [0:0] cbx_1__0__0_bottom_grid_pin_2_ ; -wire [0:0] cbx_1__0__0_bottom_grid_pin_4_ ; -wire [0:0] cbx_1__0__0_bottom_grid_pin_6_ ; -wire [0:0] cbx_1__0__0_bottom_grid_pin_8_ ; -wire [0:19] cbx_1__0__0_chanx_left_out ; -wire [0:19] cbx_1__0__0_chanx_right_out ; -wire [0:0] cbx_1__0__1_bottom_grid_pin_0_ ; -wire [0:0] cbx_1__0__1_bottom_grid_pin_10_ ; -wire [0:0] cbx_1__0__1_bottom_grid_pin_2_ ; -wire [0:0] cbx_1__0__1_bottom_grid_pin_4_ ; -wire [0:0] cbx_1__0__1_bottom_grid_pin_6_ ; -wire [0:0] cbx_1__0__1_bottom_grid_pin_8_ ; -wire [0:19] cbx_1__0__1_chanx_left_out ; -wire [0:19] cbx_1__0__1_chanx_right_out ; -wire [0:0] cbx_1__1__0_bottom_grid_pin_0_ ; -wire [0:0] cbx_1__1__0_bottom_grid_pin_10_ ; -wire [0:0] cbx_1__1__0_bottom_grid_pin_11_ ; -wire [0:0] cbx_1__1__0_bottom_grid_pin_12_ ; -wire [0:0] cbx_1__1__0_bottom_grid_pin_13_ ; -wire [0:0] cbx_1__1__0_bottom_grid_pin_14_ ; -wire [0:0] cbx_1__1__0_bottom_grid_pin_15_ ; -wire [0:0] cbx_1__1__0_bottom_grid_pin_1_ ; -wire [0:0] cbx_1__1__0_bottom_grid_pin_2_ ; -wire [0:0] cbx_1__1__0_bottom_grid_pin_3_ ; -wire [0:0] cbx_1__1__0_bottom_grid_pin_4_ ; -wire [0:0] cbx_1__1__0_bottom_grid_pin_5_ ; -wire [0:0] cbx_1__1__0_bottom_grid_pin_6_ ; -wire [0:0] cbx_1__1__0_bottom_grid_pin_7_ ; -wire [0:0] cbx_1__1__0_bottom_grid_pin_8_ ; -wire [0:0] cbx_1__1__0_bottom_grid_pin_9_ ; -wire [0:0] cbx_1__1__0_ccff_tail ; -wire [0:19] cbx_1__1__0_chanx_left_out ; -wire [0:19] cbx_1__1__0_chanx_right_out ; -wire [0:0] cbx_1__1__1_bottom_grid_pin_0_ ; -wire [0:0] cbx_1__1__1_bottom_grid_pin_10_ ; -wire [0:0] cbx_1__1__1_bottom_grid_pin_11_ ; -wire [0:0] cbx_1__1__1_bottom_grid_pin_12_ ; -wire [0:0] cbx_1__1__1_bottom_grid_pin_13_ ; -wire [0:0] cbx_1__1__1_bottom_grid_pin_14_ ; -wire [0:0] cbx_1__1__1_bottom_grid_pin_15_ ; -wire [0:0] cbx_1__1__1_bottom_grid_pin_1_ ; -wire [0:0] cbx_1__1__1_bottom_grid_pin_2_ ; -wire [0:0] cbx_1__1__1_bottom_grid_pin_3_ ; -wire [0:0] cbx_1__1__1_bottom_grid_pin_4_ ; -wire [0:0] cbx_1__1__1_bottom_grid_pin_5_ ; -wire [0:0] cbx_1__1__1_bottom_grid_pin_6_ ; -wire [0:0] cbx_1__1__1_bottom_grid_pin_7_ ; -wire [0:0] cbx_1__1__1_bottom_grid_pin_8_ ; -wire [0:0] cbx_1__1__1_bottom_grid_pin_9_ ; -wire [0:0] cbx_1__1__1_ccff_tail ; -wire [0:19] cbx_1__1__1_chanx_left_out ; -wire [0:19] cbx_1__1__1_chanx_right_out ; -wire [0:0] cbx_1__2__0_bottom_grid_pin_0_ ; -wire [0:0] cbx_1__2__0_bottom_grid_pin_10_ ; -wire [0:0] cbx_1__2__0_bottom_grid_pin_11_ ; -wire [0:0] cbx_1__2__0_bottom_grid_pin_12_ ; -wire [0:0] cbx_1__2__0_bottom_grid_pin_13_ ; -wire [0:0] cbx_1__2__0_bottom_grid_pin_14_ ; -wire [0:0] cbx_1__2__0_bottom_grid_pin_15_ ; -wire [0:0] cbx_1__2__0_bottom_grid_pin_1_ ; -wire [0:0] cbx_1__2__0_bottom_grid_pin_2_ ; -wire [0:0] cbx_1__2__0_bottom_grid_pin_3_ ; -wire [0:0] cbx_1__2__0_bottom_grid_pin_4_ ; -wire [0:0] cbx_1__2__0_bottom_grid_pin_5_ ; -wire [0:0] cbx_1__2__0_bottom_grid_pin_6_ ; -wire [0:0] cbx_1__2__0_bottom_grid_pin_7_ ; -wire [0:0] cbx_1__2__0_bottom_grid_pin_8_ ; -wire [0:0] cbx_1__2__0_bottom_grid_pin_9_ ; -wire [0:19] cbx_1__2__0_chanx_left_out ; -wire [0:19] cbx_1__2__0_chanx_right_out ; -wire [0:0] cbx_1__2__0_top_grid_pin_0_ ; -wire [0:0] cbx_1__2__1_bottom_grid_pin_0_ ; -wire [0:0] cbx_1__2__1_bottom_grid_pin_10_ ; -wire [0:0] cbx_1__2__1_bottom_grid_pin_11_ ; -wire [0:0] cbx_1__2__1_bottom_grid_pin_12_ ; -wire [0:0] cbx_1__2__1_bottom_grid_pin_13_ ; -wire [0:0] cbx_1__2__1_bottom_grid_pin_14_ ; -wire [0:0] cbx_1__2__1_bottom_grid_pin_15_ ; -wire [0:0] cbx_1__2__1_bottom_grid_pin_1_ ; -wire [0:0] cbx_1__2__1_bottom_grid_pin_2_ ; -wire [0:0] cbx_1__2__1_bottom_grid_pin_3_ ; -wire [0:0] cbx_1__2__1_bottom_grid_pin_4_ ; -wire [0:0] cbx_1__2__1_bottom_grid_pin_5_ ; -wire [0:0] cbx_1__2__1_bottom_grid_pin_6_ ; -wire [0:0] cbx_1__2__1_bottom_grid_pin_7_ ; -wire [0:0] cbx_1__2__1_bottom_grid_pin_8_ ; -wire [0:0] cbx_1__2__1_bottom_grid_pin_9_ ; -wire [0:19] cbx_1__2__1_chanx_left_out ; -wire [0:19] cbx_1__2__1_chanx_right_out ; -wire [0:0] cbx_1__2__1_top_grid_pin_0_ ; -wire [0:19] cby_0__1__0_chany_bottom_out ; -wire [0:19] cby_0__1__0_chany_top_out ; -wire [0:0] cby_0__1__0_left_grid_pin_0_ ; -wire [0:19] cby_0__1__1_chany_bottom_out ; -wire [0:19] cby_0__1__1_chany_top_out ; -wire [0:0] cby_0__1__1_left_grid_pin_0_ ; -wire [0:0] cby_1__1__0_ccff_tail ; -wire [0:19] cby_1__1__0_chany_bottom_out ; -wire [0:19] cby_1__1__0_chany_top_out ; -wire [0:0] cby_1__1__0_left_grid_pin_16_ ; -wire [0:0] cby_1__1__0_left_grid_pin_17_ ; -wire [0:0] cby_1__1__0_left_grid_pin_18_ ; -wire [0:0] cby_1__1__0_left_grid_pin_19_ ; -wire [0:0] cby_1__1__0_left_grid_pin_20_ ; -wire [0:0] cby_1__1__0_left_grid_pin_21_ ; -wire [0:0] cby_1__1__0_left_grid_pin_22_ ; -wire [0:0] cby_1__1__0_left_grid_pin_23_ ; -wire [0:0] cby_1__1__0_left_grid_pin_24_ ; -wire [0:0] cby_1__1__0_left_grid_pin_25_ ; -wire [0:0] cby_1__1__0_left_grid_pin_26_ ; -wire [0:0] cby_1__1__0_left_grid_pin_27_ ; -wire [0:0] cby_1__1__0_left_grid_pin_28_ ; -wire [0:0] cby_1__1__0_left_grid_pin_29_ ; -wire [0:0] cby_1__1__0_left_grid_pin_30_ ; -wire [0:0] cby_1__1__0_left_grid_pin_31_ ; -wire [0:0] cby_1__1__1_ccff_tail ; -wire [0:19] cby_1__1__1_chany_bottom_out ; -wire [0:19] cby_1__1__1_chany_top_out ; -wire [0:0] cby_1__1__1_left_grid_pin_16_ ; -wire [0:0] cby_1__1__1_left_grid_pin_17_ ; -wire [0:0] cby_1__1__1_left_grid_pin_18_ ; -wire [0:0] cby_1__1__1_left_grid_pin_19_ ; -wire [0:0] cby_1__1__1_left_grid_pin_20_ ; -wire [0:0] cby_1__1__1_left_grid_pin_21_ ; -wire [0:0] cby_1__1__1_left_grid_pin_22_ ; -wire [0:0] cby_1__1__1_left_grid_pin_23_ ; -wire [0:0] cby_1__1__1_left_grid_pin_24_ ; -wire [0:0] cby_1__1__1_left_grid_pin_25_ ; -wire [0:0] cby_1__1__1_left_grid_pin_26_ ; -wire [0:0] cby_1__1__1_left_grid_pin_27_ ; -wire [0:0] cby_1__1__1_left_grid_pin_28_ ; -wire [0:0] cby_1__1__1_left_grid_pin_29_ ; -wire [0:0] cby_1__1__1_left_grid_pin_30_ ; -wire [0:0] cby_1__1__1_left_grid_pin_31_ ; -wire [0:19] cby_2__1__0_chany_bottom_out ; -wire [0:19] cby_2__1__0_chany_top_out ; -wire [0:0] cby_2__1__0_left_grid_pin_16_ ; -wire [0:0] cby_2__1__0_left_grid_pin_17_ ; -wire [0:0] cby_2__1__0_left_grid_pin_18_ ; -wire [0:0] cby_2__1__0_left_grid_pin_19_ ; -wire [0:0] cby_2__1__0_left_grid_pin_20_ ; -wire [0:0] cby_2__1__0_left_grid_pin_21_ ; -wire [0:0] cby_2__1__0_left_grid_pin_22_ ; -wire [0:0] cby_2__1__0_left_grid_pin_23_ ; -wire [0:0] cby_2__1__0_left_grid_pin_24_ ; -wire [0:0] cby_2__1__0_left_grid_pin_25_ ; -wire [0:0] cby_2__1__0_left_grid_pin_26_ ; -wire [0:0] cby_2__1__0_left_grid_pin_27_ ; -wire [0:0] cby_2__1__0_left_grid_pin_28_ ; -wire [0:0] cby_2__1__0_left_grid_pin_29_ ; -wire [0:0] cby_2__1__0_left_grid_pin_30_ ; -wire [0:0] cby_2__1__0_left_grid_pin_31_ ; -wire [0:0] cby_2__1__0_right_grid_pin_0_ ; -wire [0:19] cby_2__1__1_chany_bottom_out ; -wire [0:19] cby_2__1__1_chany_top_out ; -wire [0:0] cby_2__1__1_left_grid_pin_16_ ; -wire [0:0] cby_2__1__1_left_grid_pin_17_ ; -wire [0:0] cby_2__1__1_left_grid_pin_18_ ; -wire [0:0] cby_2__1__1_left_grid_pin_19_ ; -wire [0:0] cby_2__1__1_left_grid_pin_20_ ; -wire [0:0] cby_2__1__1_left_grid_pin_21_ ; -wire [0:0] cby_2__1__1_left_grid_pin_22_ ; -wire [0:0] cby_2__1__1_left_grid_pin_23_ ; -wire [0:0] cby_2__1__1_left_grid_pin_24_ ; -wire [0:0] cby_2__1__1_left_grid_pin_25_ ; -wire [0:0] cby_2__1__1_left_grid_pin_26_ ; -wire [0:0] cby_2__1__1_left_grid_pin_27_ ; -wire [0:0] cby_2__1__1_left_grid_pin_28_ ; -wire [0:0] cby_2__1__1_left_grid_pin_29_ ; -wire [0:0] cby_2__1__1_left_grid_pin_30_ ; -wire [0:0] cby_2__1__1_left_grid_pin_31_ ; -wire [0:0] cby_2__1__1_right_grid_pin_0_ ; -wire [0:0] direct_interc_0_out ; -wire [0:0] direct_interc_1_out ; -wire [0:0] direct_interc_2_out ; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_50_ ; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_51_ ; -wire [0:0] grid_clb_0_ccff_tail ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_42_lower ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_42_upper ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_43_lower ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_43_upper ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_44_lower ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_44_upper ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_45_lower ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_45_upper ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_46_lower ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_46_upper ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_47_lower ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_47_upper ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_48_lower ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_48_upper ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_49_lower ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_49_upper ; -wire [0:0] grid_clb_0_top_width_0_height_0__pin_34_lower ; -wire [0:0] grid_clb_0_top_width_0_height_0__pin_34_upper ; -wire [0:0] grid_clb_0_top_width_0_height_0__pin_35_lower ; -wire [0:0] grid_clb_0_top_width_0_height_0__pin_35_upper ; -wire [0:0] grid_clb_0_top_width_0_height_0__pin_36_lower ; -wire [0:0] grid_clb_0_top_width_0_height_0__pin_36_upper ; -wire [0:0] grid_clb_0_top_width_0_height_0__pin_37_lower ; -wire [0:0] grid_clb_0_top_width_0_height_0__pin_37_upper ; -wire [0:0] grid_clb_0_top_width_0_height_0__pin_38_lower ; -wire [0:0] grid_clb_0_top_width_0_height_0__pin_38_upper ; -wire [0:0] grid_clb_0_top_width_0_height_0__pin_39_lower ; -wire [0:0] grid_clb_0_top_width_0_height_0__pin_39_upper ; -wire [0:0] grid_clb_0_top_width_0_height_0__pin_40_lower ; -wire [0:0] grid_clb_0_top_width_0_height_0__pin_40_upper ; -wire [0:0] grid_clb_0_top_width_0_height_0__pin_41_lower ; -wire [0:0] grid_clb_0_top_width_0_height_0__pin_41_upper ; -wire [0:0] grid_clb_1__1__undriven_left_width_0_height_0__pin_52_ ; -wire [0:0] grid_clb_1__2__undriven_left_width_0_height_0__pin_52_ ; -wire [0:0] grid_clb_1__2__undriven_top_width_0_height_0__pin_32_ ; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_50_ ; -wire [0:0] grid_clb_1_ccff_tail ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_42_lower ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_42_upper ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_43_lower ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_43_upper ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_44_lower ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_44_upper ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_45_lower ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_45_upper ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_46_lower ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_46_upper ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_47_lower ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_47_upper ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_48_lower ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_48_upper ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_49_lower ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_49_upper ; -wire [0:0] grid_clb_1_top_width_0_height_0__pin_34_lower ; -wire [0:0] grid_clb_1_top_width_0_height_0__pin_34_upper ; -wire [0:0] grid_clb_1_top_width_0_height_0__pin_35_lower ; -wire [0:0] grid_clb_1_top_width_0_height_0__pin_35_upper ; -wire [0:0] grid_clb_1_top_width_0_height_0__pin_36_lower ; -wire [0:0] grid_clb_1_top_width_0_height_0__pin_36_upper ; -wire [0:0] grid_clb_1_top_width_0_height_0__pin_37_lower ; -wire [0:0] grid_clb_1_top_width_0_height_0__pin_37_upper ; -wire [0:0] grid_clb_1_top_width_0_height_0__pin_38_lower ; -wire [0:0] grid_clb_1_top_width_0_height_0__pin_38_upper ; -wire [0:0] grid_clb_1_top_width_0_height_0__pin_39_lower ; -wire [0:0] grid_clb_1_top_width_0_height_0__pin_39_upper ; -wire [0:0] grid_clb_1_top_width_0_height_0__pin_40_lower ; -wire [0:0] grid_clb_1_top_width_0_height_0__pin_40_upper ; -wire [0:0] grid_clb_1_top_width_0_height_0__pin_41_lower ; -wire [0:0] grid_clb_1_top_width_0_height_0__pin_41_upper ; -wire [0:0] grid_clb_2__1__undriven_bottom_width_0_height_0__pin_50_ ; -wire [0:0] grid_clb_2__1__undriven_left_width_0_height_0__pin_52_ ; -wire [0:0] grid_clb_2__2__undriven_left_width_0_height_0__pin_52_ ; -wire [0:0] grid_clb_2_ccff_tail ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_42_lower ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_42_upper ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_43_lower ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_43_upper ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_44_lower ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_44_upper ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_45_lower ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_45_upper ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_46_lower ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_46_upper ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_47_lower ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_47_upper ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_48_lower ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_48_upper ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_49_lower ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_49_upper ; -wire [0:0] grid_clb_2_top_width_0_height_0__pin_34_lower ; -wire [0:0] grid_clb_2_top_width_0_height_0__pin_34_upper ; -wire [0:0] grid_clb_2_top_width_0_height_0__pin_35_lower ; -wire [0:0] grid_clb_2_top_width_0_height_0__pin_35_upper ; -wire [0:0] grid_clb_2_top_width_0_height_0__pin_36_lower ; -wire [0:0] grid_clb_2_top_width_0_height_0__pin_36_upper ; -wire [0:0] grid_clb_2_top_width_0_height_0__pin_37_lower ; -wire [0:0] grid_clb_2_top_width_0_height_0__pin_37_upper ; -wire [0:0] grid_clb_2_top_width_0_height_0__pin_38_lower ; -wire [0:0] grid_clb_2_top_width_0_height_0__pin_38_upper ; -wire [0:0] grid_clb_2_top_width_0_height_0__pin_39_lower ; -wire [0:0] grid_clb_2_top_width_0_height_0__pin_39_upper ; -wire [0:0] grid_clb_2_top_width_0_height_0__pin_40_lower ; -wire [0:0] grid_clb_2_top_width_0_height_0__pin_40_upper ; -wire [0:0] grid_clb_2_top_width_0_height_0__pin_41_lower ; -wire [0:0] grid_clb_2_top_width_0_height_0__pin_41_upper ; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_50_ ; -wire [0:0] grid_clb_3_ccff_tail ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_42_lower ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_42_upper ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_43_lower ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_43_upper ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_44_lower ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_44_upper ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_45_lower ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_45_upper ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_46_lower ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_46_upper ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_47_lower ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_47_upper ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_48_lower ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_48_upper ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_49_lower ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_49_upper ; -wire [0:0] grid_clb_3_top_width_0_height_0__pin_34_lower ; -wire [0:0] grid_clb_3_top_width_0_height_0__pin_34_upper ; -wire [0:0] grid_clb_3_top_width_0_height_0__pin_35_lower ; -wire [0:0] grid_clb_3_top_width_0_height_0__pin_35_upper ; -wire [0:0] grid_clb_3_top_width_0_height_0__pin_36_lower ; -wire [0:0] grid_clb_3_top_width_0_height_0__pin_36_upper ; -wire [0:0] grid_clb_3_top_width_0_height_0__pin_37_lower ; -wire [0:0] grid_clb_3_top_width_0_height_0__pin_37_upper ; -wire [0:0] grid_clb_3_top_width_0_height_0__pin_38_lower ; -wire [0:0] grid_clb_3_top_width_0_height_0__pin_38_upper ; -wire [0:0] grid_clb_3_top_width_0_height_0__pin_39_lower ; -wire [0:0] grid_clb_3_top_width_0_height_0__pin_39_upper ; -wire [0:0] grid_clb_3_top_width_0_height_0__pin_40_lower ; -wire [0:0] grid_clb_3_top_width_0_height_0__pin_40_upper ; -wire [0:0] grid_clb_3_top_width_0_height_0__pin_41_lower ; -wire [0:0] grid_clb_3_top_width_0_height_0__pin_41_upper ; -wire [0:0] grid_io_bottom_0_ccff_tail ; -wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_11_lower ; -wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_11_upper ; -wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_1_lower ; -wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_1_upper ; -wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_3_lower ; -wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_3_upper ; -wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_5_lower ; -wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_5_upper ; -wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_7_lower ; -wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_7_upper ; -wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_9_lower ; -wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_9_upper ; -wire [0:0] grid_io_bottom_1_ccff_tail ; -wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_11_lower ; -wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_11_upper ; -wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_1_lower ; -wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_1_upper ; -wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_3_lower ; -wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_3_upper ; -wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_5_lower ; -wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_5_upper ; -wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_7_lower ; -wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_7_upper ; -wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_9_lower ; -wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_9_upper ; -wire [0:0] grid_io_left_0_ccff_tail ; -wire [0:0] grid_io_left_0_right_width_0_height_0__pin_1_lower ; -wire [0:0] grid_io_left_0_right_width_0_height_0__pin_1_upper ; -wire [0:0] grid_io_left_1_ccff_tail ; -wire [0:0] grid_io_left_1_right_width_0_height_0__pin_1_lower ; -wire [0:0] grid_io_left_1_right_width_0_height_0__pin_1_upper ; -wire [0:0] grid_io_right_0_ccff_tail ; -wire [0:0] grid_io_right_0_left_width_0_height_0__pin_1_lower ; -wire [0:0] grid_io_right_0_left_width_0_height_0__pin_1_upper ; -wire [0:0] grid_io_right_1_ccff_tail ; -wire [0:0] grid_io_right_1_left_width_0_height_0__pin_1_lower ; -wire [0:0] grid_io_right_1_left_width_0_height_0__pin_1_upper ; -wire [0:0] grid_io_top_0_bottom_width_0_height_0__pin_1_lower ; -wire [0:0] grid_io_top_0_bottom_width_0_height_0__pin_1_upper ; -wire [0:0] grid_io_top_0_ccff_tail ; -wire [0:0] grid_io_top_1_bottom_width_0_height_0__pin_1_lower ; -wire [0:0] grid_io_top_1_bottom_width_0_height_0__pin_1_upper ; -wire [0:0] grid_io_top_1_ccff_tail ; -wire [0:19] sb_0__0__0_chanx_right_out ; -wire [0:19] sb_0__0__0_chany_top_out ; -wire [0:0] sb_0__1__0_ccff_tail ; -wire [0:19] sb_0__1__0_chanx_right_out ; -wire [0:19] sb_0__1__0_chany_bottom_out ; -wire [0:19] sb_0__1__0_chany_top_out ; -wire [0:0] sb_0__2__0_ccff_tail ; -wire [0:19] sb_0__2__0_chanx_right_out ; -wire [0:19] sb_0__2__0_chany_bottom_out ; -wire [0:0] sb_1__0__0_ccff_tail ; -wire [0:19] sb_1__0__0_chanx_left_out ; -wire [0:19] sb_1__0__0_chanx_right_out ; -wire [0:19] sb_1__0__0_chany_top_out ; -wire [0:0] sb_1__1__0_ccff_tail ; -wire [0:19] sb_1__1__0_chanx_left_out ; -wire [0:19] sb_1__1__0_chanx_right_out ; -wire [0:19] sb_1__1__0_chany_bottom_out ; -wire [0:19] sb_1__1__0_chany_top_out ; -wire [0:0] sb_1__2__0_ccff_tail ; -wire [0:19] sb_1__2__0_chanx_left_out ; -wire [0:19] sb_1__2__0_chanx_right_out ; -wire [0:19] sb_1__2__0_chany_bottom_out ; -wire [0:0] sb_2__0__0_ccff_tail ; -wire [0:19] sb_2__0__0_chanx_left_out ; -wire [0:19] sb_2__0__0_chany_top_out ; -wire [0:0] sb_2__1__0_ccff_tail ; -wire [0:19] sb_2__1__0_chanx_left_out ; -wire [0:19] sb_2__1__0_chany_bottom_out ; -wire [0:19] sb_2__1__0_chany_top_out ; -wire [0:0] sb_2__2__0_ccff_tail ; -wire [0:19] sb_2__2__0_chanx_left_out ; -wire [0:19] sb_2__2__0_chany_bottom_out ; -supply1 VDD ; -supply0 VSS ; -wire [0:0] prog_clk__FEEDTHRU_1 ; -wire [0:0] prog_clk__FEEDTHRU_2 ; -wire [0:0] prog_clk__FEEDTHRU_3 ; -wire [0:0] prog_clk__FEEDTHRU_4 ; -wire [0:0] prog_clk__FEEDTHRU_5 ; -wire [0:0] prog_clk__FEEDTHRU_6 ; -wire [0:0] prog_clk__FEEDTHRU_7 ; -wire [0:0] prog_clk__FEEDTHRU_8 ; -wire [0:0] prog_clk__FEEDTHRU_9 ; -wire [0:0] prog_clk__FEEDTHRU_10 ; -wire [0:0] prog_clk__FEEDTHRU_11 ; -wire [0:0] prog_clk__FEEDTHRU_12 ; -wire [0:0] prog_clk__FEEDTHRU_13 ; -wire [0:0] prog_clk__FEEDTHRU_14 ; -wire [0:0] prog_clk__FEEDTHRU_15 ; -wire [0:0] prog_clk__FEEDTHRU_16 ; -wire [0:0] prog_clk__FEEDTHRU_17 ; -wire [0:0] prog_clk__FEEDTHRU_18 ; -wire [0:0] prog_clk__FEEDTHRU_19 ; -wire [0:0] Test_en__FEEDTHRU_1 ; -wire [0:0] Test_en__FEEDTHRU_2 ; -wire [0:0] Test_en__FEEDTHRU_3 ; -wire [0:0] Test_en__FEEDTHRU_4 ; -wire [0:0] Test_en__FEEDTHRU_5 ; -wire [0:0] Test_en__FEEDTHRU_6 ; -wire [0:0] clk__FEEDTHRU_1 ; -wire [0:0] clk__FEEDTHRU_2 ; -wire [0:0] clk__FEEDTHRU_3 ; -wire [0:0] clk__FEEDTHRU_4 ; -wire [0:0] clk__FEEDTHRU_5 ; -wire [0:0] clk__FEEDTHRU_6 ; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ; -// - -grid_clb grid_clb_1__1_ ( - .prog_clk ( { ctsbuf_net_1921 } ) , - .Test_en ( Test_en__FEEDTHRU_6 ) , .clk ( clk__FEEDTHRU_6 ) , - .top_width_0_height_0__pin_0_ ( cbx_1__1__0_bottom_grid_pin_0_ ) , - .top_width_0_height_0__pin_1_ ( cbx_1__1__0_bottom_grid_pin_1_ ) , - .top_width_0_height_0__pin_2_ ( cbx_1__1__0_bottom_grid_pin_2_ ) , - .top_width_0_height_0__pin_3_ ( cbx_1__1__0_bottom_grid_pin_3_ ) , - .top_width_0_height_0__pin_4_ ( cbx_1__1__0_bottom_grid_pin_4_ ) , - .top_width_0_height_0__pin_5_ ( cbx_1__1__0_bottom_grid_pin_5_ ) , - .top_width_0_height_0__pin_6_ ( cbx_1__1__0_bottom_grid_pin_6_ ) , - .top_width_0_height_0__pin_7_ ( cbx_1__1__0_bottom_grid_pin_7_ ) , - .top_width_0_height_0__pin_8_ ( cbx_1__1__0_bottom_grid_pin_8_ ) , - .top_width_0_height_0__pin_9_ ( cbx_1__1__0_bottom_grid_pin_9_ ) , - .top_width_0_height_0__pin_10_ ( cbx_1__1__0_bottom_grid_pin_10_ ) , - .top_width_0_height_0__pin_11_ ( cbx_1__1__0_bottom_grid_pin_11_ ) , - .top_width_0_height_0__pin_12_ ( cbx_1__1__0_bottom_grid_pin_12_ ) , - .top_width_0_height_0__pin_13_ ( cbx_1__1__0_bottom_grid_pin_13_ ) , - .top_width_0_height_0__pin_14_ ( cbx_1__1__0_bottom_grid_pin_14_ ) , - .top_width_0_height_0__pin_15_ ( cbx_1__1__0_bottom_grid_pin_15_ ) , - .top_width_0_height_0__pin_32_ ( direct_interc_0_out ) , - .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1 } ) , - .right_width_0_height_0__pin_16_ ( cby_1__1__0_left_grid_pin_16_ ) , - .right_width_0_height_0__pin_17_ ( cby_1__1__0_left_grid_pin_17_ ) , - .right_width_0_height_0__pin_18_ ( cby_1__1__0_left_grid_pin_18_ ) , - .right_width_0_height_0__pin_19_ ( cby_1__1__0_left_grid_pin_19_ ) , - .right_width_0_height_0__pin_20_ ( cby_1__1__0_left_grid_pin_20_ ) , - .right_width_0_height_0__pin_21_ ( cby_1__1__0_left_grid_pin_21_ ) , - .right_width_0_height_0__pin_22_ ( cby_1__1__0_left_grid_pin_22_ ) , - .right_width_0_height_0__pin_23_ ( cby_1__1__0_left_grid_pin_23_ ) , - .right_width_0_height_0__pin_24_ ( cby_1__1__0_left_grid_pin_24_ ) , - .right_width_0_height_0__pin_25_ ( cby_1__1__0_left_grid_pin_25_ ) , - .right_width_0_height_0__pin_26_ ( cby_1__1__0_left_grid_pin_26_ ) , - .right_width_0_height_0__pin_27_ ( cby_1__1__0_left_grid_pin_27_ ) , - .right_width_0_height_0__pin_28_ ( cby_1__1__0_left_grid_pin_28_ ) , - .right_width_0_height_0__pin_29_ ( cby_1__1__0_left_grid_pin_29_ ) , - .right_width_0_height_0__pin_30_ ( cby_1__1__0_left_grid_pin_30_ ) , - .right_width_0_height_0__pin_31_ ( cby_1__1__0_left_grid_pin_31_ ) , - .left_width_0_height_0__pin_52_ ( grid_clb_1__1__undriven_left_width_0_height_0__pin_52_ ) , - .ccff_head ( grid_io_left_0_ccff_tail ) , - .top_width_0_height_0__pin_34_upper ( grid_clb_0_top_width_0_height_0__pin_34_upper ) , - .top_width_0_height_0__pin_34_lower ( grid_clb_0_top_width_0_height_0__pin_34_lower ) , - .top_width_0_height_0__pin_35_upper ( grid_clb_0_top_width_0_height_0__pin_35_upper ) , - .top_width_0_height_0__pin_35_lower ( grid_clb_0_top_width_0_height_0__pin_35_lower ) , - .top_width_0_height_0__pin_36_upper ( grid_clb_0_top_width_0_height_0__pin_36_upper ) , - .top_width_0_height_0__pin_36_lower ( grid_clb_0_top_width_0_height_0__pin_36_lower ) , - .top_width_0_height_0__pin_37_upper ( grid_clb_0_top_width_0_height_0__pin_37_upper ) , - .top_width_0_height_0__pin_37_lower ( grid_clb_0_top_width_0_height_0__pin_37_lower ) , - .top_width_0_height_0__pin_38_upper ( grid_clb_0_top_width_0_height_0__pin_38_upper ) , - .top_width_0_height_0__pin_38_lower ( grid_clb_0_top_width_0_height_0__pin_38_lower ) , - .top_width_0_height_0__pin_39_upper ( grid_clb_0_top_width_0_height_0__pin_39_upper ) , - .top_width_0_height_0__pin_39_lower ( grid_clb_0_top_width_0_height_0__pin_39_lower ) , - .top_width_0_height_0__pin_40_upper ( grid_clb_0_top_width_0_height_0__pin_40_upper ) , - .top_width_0_height_0__pin_40_lower ( grid_clb_0_top_width_0_height_0__pin_40_lower ) , - .top_width_0_height_0__pin_41_upper ( grid_clb_0_top_width_0_height_0__pin_41_upper ) , - .top_width_0_height_0__pin_41_lower ( grid_clb_0_top_width_0_height_0__pin_41_lower ) , - .right_width_0_height_0__pin_42_upper ( grid_clb_0_right_width_0_height_0__pin_42_upper ) , - .right_width_0_height_0__pin_42_lower ( grid_clb_0_right_width_0_height_0__pin_42_lower ) , - .right_width_0_height_0__pin_43_upper ( grid_clb_0_right_width_0_height_0__pin_43_upper ) , - .right_width_0_height_0__pin_43_lower ( grid_clb_0_right_width_0_height_0__pin_43_lower ) , - .right_width_0_height_0__pin_44_upper ( grid_clb_0_right_width_0_height_0__pin_44_upper ) , - .right_width_0_height_0__pin_44_lower ( grid_clb_0_right_width_0_height_0__pin_44_lower ) , - .right_width_0_height_0__pin_45_upper ( grid_clb_0_right_width_0_height_0__pin_45_upper ) , - .right_width_0_height_0__pin_45_lower ( grid_clb_0_right_width_0_height_0__pin_45_lower ) , - .right_width_0_height_0__pin_46_upper ( grid_clb_0_right_width_0_height_0__pin_46_upper ) , - .right_width_0_height_0__pin_46_lower ( grid_clb_0_right_width_0_height_0__pin_46_lower ) , - .right_width_0_height_0__pin_47_upper ( grid_clb_0_right_width_0_height_0__pin_47_upper ) , - .right_width_0_height_0__pin_47_lower ( grid_clb_0_right_width_0_height_0__pin_47_lower ) , - .right_width_0_height_0__pin_48_upper ( grid_clb_0_right_width_0_height_0__pin_48_upper ) , - .right_width_0_height_0__pin_48_lower ( grid_clb_0_right_width_0_height_0__pin_48_lower ) , - .right_width_0_height_0__pin_49_upper ( grid_clb_0_right_width_0_height_0__pin_49_upper ) , - .right_width_0_height_0__pin_49_lower ( grid_clb_0_right_width_0_height_0__pin_49_lower ) , - .bottom_width_0_height_0__pin_50_ ( grid_clb_0_bottom_width_0_height_0__pin_50_ ) , - .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_2 } ) , - .ccff_tail ( grid_clb_0_ccff_tail ) , .SC_IN_TOP ( scff_Wires_3_ ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_3 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4 ) , .SC_OUT_BOT ( scff_Wires_5_ ) , - .VDD ( VDD ) , .VSS ( VSS ) , - .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_3 ) , - .prog_clk__FEEDTHRU_2 ( prog_clk__FEEDTHRU_4 ) , - .prog_clk__FEEDTHRU_3 ( { SYNOPSYS_UNCONNECTED_5 } ) , - .prog_clk__FEEDTHRU_4 ( { SYNOPSYS_UNCONNECTED_6 } ) , - .Test_en__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_7 } ) , - .clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_8 } ) ) ; -grid_clb grid_clb_1__2_ ( - .prog_clk ( { ctsbuf_net_1113 } ) , - .Test_en ( Test_en__FEEDTHRU_4 ) , .clk ( clk__FEEDTHRU_4 ) , - .top_width_0_height_0__pin_0_ ( cbx_1__2__0_bottom_grid_pin_0_ ) , - .top_width_0_height_0__pin_1_ ( cbx_1__2__0_bottom_grid_pin_1_ ) , - .top_width_0_height_0__pin_2_ ( cbx_1__2__0_bottom_grid_pin_2_ ) , - .top_width_0_height_0__pin_3_ ( cbx_1__2__0_bottom_grid_pin_3_ ) , - .top_width_0_height_0__pin_4_ ( cbx_1__2__0_bottom_grid_pin_4_ ) , - .top_width_0_height_0__pin_5_ ( cbx_1__2__0_bottom_grid_pin_5_ ) , - .top_width_0_height_0__pin_6_ ( cbx_1__2__0_bottom_grid_pin_6_ ) , - .top_width_0_height_0__pin_7_ ( cbx_1__2__0_bottom_grid_pin_7_ ) , - .top_width_0_height_0__pin_8_ ( cbx_1__2__0_bottom_grid_pin_8_ ) , - .top_width_0_height_0__pin_9_ ( cbx_1__2__0_bottom_grid_pin_9_ ) , - .top_width_0_height_0__pin_10_ ( cbx_1__2__0_bottom_grid_pin_10_ ) , - .top_width_0_height_0__pin_11_ ( cbx_1__2__0_bottom_grid_pin_11_ ) , - .top_width_0_height_0__pin_12_ ( cbx_1__2__0_bottom_grid_pin_12_ ) , - .top_width_0_height_0__pin_13_ ( cbx_1__2__0_bottom_grid_pin_13_ ) , - .top_width_0_height_0__pin_14_ ( cbx_1__2__0_bottom_grid_pin_14_ ) , - .top_width_0_height_0__pin_15_ ( cbx_1__2__0_bottom_grid_pin_15_ ) , - .top_width_0_height_0__pin_32_ ( grid_clb_1__2__undriven_top_width_0_height_0__pin_32_ ) , - .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_9 } ) , - .right_width_0_height_0__pin_16_ ( cby_1__1__1_left_grid_pin_16_ ) , - .right_width_0_height_0__pin_17_ ( cby_1__1__1_left_grid_pin_17_ ) , - .right_width_0_height_0__pin_18_ ( cby_1__1__1_left_grid_pin_18_ ) , - .right_width_0_height_0__pin_19_ ( cby_1__1__1_left_grid_pin_19_ ) , - .right_width_0_height_0__pin_20_ ( cby_1__1__1_left_grid_pin_20_ ) , - .right_width_0_height_0__pin_21_ ( cby_1__1__1_left_grid_pin_21_ ) , - .right_width_0_height_0__pin_22_ ( cby_1__1__1_left_grid_pin_22_ ) , - .right_width_0_height_0__pin_23_ ( cby_1__1__1_left_grid_pin_23_ ) , - .right_width_0_height_0__pin_24_ ( cby_1__1__1_left_grid_pin_24_ ) , - .right_width_0_height_0__pin_25_ ( cby_1__1__1_left_grid_pin_25_ ) , - .right_width_0_height_0__pin_26_ ( cby_1__1__1_left_grid_pin_26_ ) , - .right_width_0_height_0__pin_27_ ( cby_1__1__1_left_grid_pin_27_ ) , - .right_width_0_height_0__pin_28_ ( cby_1__1__1_left_grid_pin_28_ ) , - .right_width_0_height_0__pin_29_ ( cby_1__1__1_left_grid_pin_29_ ) , - .right_width_0_height_0__pin_30_ ( cby_1__1__1_left_grid_pin_30_ ) , - .right_width_0_height_0__pin_31_ ( cby_1__1__1_left_grid_pin_31_ ) , - .left_width_0_height_0__pin_52_ ( grid_clb_1__2__undriven_left_width_0_height_0__pin_52_ ) , - .ccff_head ( grid_io_left_1_ccff_tail ) , - .top_width_0_height_0__pin_34_upper ( grid_clb_1_top_width_0_height_0__pin_34_upper ) , - .top_width_0_height_0__pin_34_lower ( grid_clb_1_top_width_0_height_0__pin_34_lower ) , - .top_width_0_height_0__pin_35_upper ( grid_clb_1_top_width_0_height_0__pin_35_upper ) , - .top_width_0_height_0__pin_35_lower ( grid_clb_1_top_width_0_height_0__pin_35_lower ) , - .top_width_0_height_0__pin_36_upper ( grid_clb_1_top_width_0_height_0__pin_36_upper ) , - .top_width_0_height_0__pin_36_lower ( grid_clb_1_top_width_0_height_0__pin_36_lower ) , - .top_width_0_height_0__pin_37_upper ( grid_clb_1_top_width_0_height_0__pin_37_upper ) , - .top_width_0_height_0__pin_37_lower ( grid_clb_1_top_width_0_height_0__pin_37_lower ) , - .top_width_0_height_0__pin_38_upper ( grid_clb_1_top_width_0_height_0__pin_38_upper ) , - .top_width_0_height_0__pin_38_lower ( grid_clb_1_top_width_0_height_0__pin_38_lower ) , - .top_width_0_height_0__pin_39_upper ( grid_clb_1_top_width_0_height_0__pin_39_upper ) , - .top_width_0_height_0__pin_39_lower ( grid_clb_1_top_width_0_height_0__pin_39_lower ) , - .top_width_0_height_0__pin_40_upper ( grid_clb_1_top_width_0_height_0__pin_40_upper ) , - .top_width_0_height_0__pin_40_lower ( grid_clb_1_top_width_0_height_0__pin_40_lower ) , - .top_width_0_height_0__pin_41_upper ( grid_clb_1_top_width_0_height_0__pin_41_upper ) , - .top_width_0_height_0__pin_41_lower ( grid_clb_1_top_width_0_height_0__pin_41_lower ) , - .right_width_0_height_0__pin_42_upper ( grid_clb_1_right_width_0_height_0__pin_42_upper ) , - .right_width_0_height_0__pin_42_lower ( grid_clb_1_right_width_0_height_0__pin_42_lower ) , - .right_width_0_height_0__pin_43_upper ( grid_clb_1_right_width_0_height_0__pin_43_upper ) , - .right_width_0_height_0__pin_43_lower ( grid_clb_1_right_width_0_height_0__pin_43_lower ) , - .right_width_0_height_0__pin_44_upper ( grid_clb_1_right_width_0_height_0__pin_44_upper ) , - .right_width_0_height_0__pin_44_lower ( grid_clb_1_right_width_0_height_0__pin_44_lower ) , - .right_width_0_height_0__pin_45_upper ( grid_clb_1_right_width_0_height_0__pin_45_upper ) , - .right_width_0_height_0__pin_45_lower ( grid_clb_1_right_width_0_height_0__pin_45_lower ) , - .right_width_0_height_0__pin_46_upper ( grid_clb_1_right_width_0_height_0__pin_46_upper ) , - .right_width_0_height_0__pin_46_lower ( grid_clb_1_right_width_0_height_0__pin_46_lower ) , - .right_width_0_height_0__pin_47_upper ( grid_clb_1_right_width_0_height_0__pin_47_upper ) , - .right_width_0_height_0__pin_47_lower ( grid_clb_1_right_width_0_height_0__pin_47_lower ) , - .right_width_0_height_0__pin_48_upper ( grid_clb_1_right_width_0_height_0__pin_48_upper ) , - .right_width_0_height_0__pin_48_lower ( grid_clb_1_right_width_0_height_0__pin_48_lower ) , - .right_width_0_height_0__pin_49_upper ( grid_clb_1_right_width_0_height_0__pin_49_upper ) , - .right_width_0_height_0__pin_49_lower ( grid_clb_1_right_width_0_height_0__pin_49_lower ) , - .bottom_width_0_height_0__pin_50_ ( grid_clb_1_bottom_width_0_height_0__pin_50_ ) , - .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_10 } ) , - .ccff_tail ( grid_clb_1_ccff_tail ) , .SC_IN_TOP ( scff_Wires_1_ ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_11 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_12 ) , .SC_OUT_BOT ( scff_Wires_2_ ) , - .VDD ( VDD ) , .VSS ( VSS ) , - .prog_clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_13 } ) , - .prog_clk__FEEDTHRU_2 ( { SYNOPSYS_UNCONNECTED_14 } ) , - .prog_clk__FEEDTHRU_3 ( prog_clk__FEEDTHRU_6 ) , - .prog_clk__FEEDTHRU_4 ( { SYNOPSYS_UNCONNECTED_15 } ) , - .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_5 ) , - .clk__FEEDTHRU_1 ( clk__FEEDTHRU_5 ) ) ; -grid_clb grid_clb_2__1_ ( .prog_clk ( prog_clk__FEEDTHRU_16 ) , - .Test_en ( Test_en__FEEDTHRU_3 ) , .clk ( clk__FEEDTHRU_3 ) , - .top_width_0_height_0__pin_0_ ( cbx_1__1__1_bottom_grid_pin_0_ ) , - .top_width_0_height_0__pin_1_ ( cbx_1__1__1_bottom_grid_pin_1_ ) , - .top_width_0_height_0__pin_2_ ( cbx_1__1__1_bottom_grid_pin_2_ ) , - .top_width_0_height_0__pin_3_ ( cbx_1__1__1_bottom_grid_pin_3_ ) , - .top_width_0_height_0__pin_4_ ( cbx_1__1__1_bottom_grid_pin_4_ ) , - .top_width_0_height_0__pin_5_ ( cbx_1__1__1_bottom_grid_pin_5_ ) , - .top_width_0_height_0__pin_6_ ( cbx_1__1__1_bottom_grid_pin_6_ ) , - .top_width_0_height_0__pin_7_ ( cbx_1__1__1_bottom_grid_pin_7_ ) , - .top_width_0_height_0__pin_8_ ( cbx_1__1__1_bottom_grid_pin_8_ ) , - .top_width_0_height_0__pin_9_ ( cbx_1__1__1_bottom_grid_pin_9_ ) , - .top_width_0_height_0__pin_10_ ( cbx_1__1__1_bottom_grid_pin_10_ ) , - .top_width_0_height_0__pin_11_ ( cbx_1__1__1_bottom_grid_pin_11_ ) , - .top_width_0_height_0__pin_12_ ( cbx_1__1__1_bottom_grid_pin_12_ ) , - .top_width_0_height_0__pin_13_ ( cbx_1__1__1_bottom_grid_pin_13_ ) , - .top_width_0_height_0__pin_14_ ( cbx_1__1__1_bottom_grid_pin_14_ ) , - .top_width_0_height_0__pin_15_ ( cbx_1__1__1_bottom_grid_pin_15_ ) , - .top_width_0_height_0__pin_32_ ( direct_interc_1_out ) , - .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_16 } ) , - .right_width_0_height_0__pin_16_ ( cby_2__1__0_left_grid_pin_16_ ) , - .right_width_0_height_0__pin_17_ ( cby_2__1__0_left_grid_pin_17_ ) , - .right_width_0_height_0__pin_18_ ( cby_2__1__0_left_grid_pin_18_ ) , - .right_width_0_height_0__pin_19_ ( cby_2__1__0_left_grid_pin_19_ ) , - .right_width_0_height_0__pin_20_ ( cby_2__1__0_left_grid_pin_20_ ) , - .right_width_0_height_0__pin_21_ ( cby_2__1__0_left_grid_pin_21_ ) , - .right_width_0_height_0__pin_22_ ( cby_2__1__0_left_grid_pin_22_ ) , - .right_width_0_height_0__pin_23_ ( cby_2__1__0_left_grid_pin_23_ ) , - .right_width_0_height_0__pin_24_ ( cby_2__1__0_left_grid_pin_24_ ) , - .right_width_0_height_0__pin_25_ ( cby_2__1__0_left_grid_pin_25_ ) , - .right_width_0_height_0__pin_26_ ( cby_2__1__0_left_grid_pin_26_ ) , - .right_width_0_height_0__pin_27_ ( cby_2__1__0_left_grid_pin_27_ ) , - .right_width_0_height_0__pin_28_ ( cby_2__1__0_left_grid_pin_28_ ) , - .right_width_0_height_0__pin_29_ ( cby_2__1__0_left_grid_pin_29_ ) , - .right_width_0_height_0__pin_30_ ( cby_2__1__0_left_grid_pin_30_ ) , - .right_width_0_height_0__pin_31_ ( cby_2__1__0_left_grid_pin_31_ ) , - .left_width_0_height_0__pin_52_ ( grid_clb_2__1__undriven_left_width_0_height_0__pin_52_ ) , - .ccff_head ( cby_1__1__0_ccff_tail ) , - .top_width_0_height_0__pin_34_upper ( grid_clb_2_top_width_0_height_0__pin_34_upper ) , - .top_width_0_height_0__pin_34_lower ( grid_clb_2_top_width_0_height_0__pin_34_lower ) , - .top_width_0_height_0__pin_35_upper ( grid_clb_2_top_width_0_height_0__pin_35_upper ) , - .top_width_0_height_0__pin_35_lower ( grid_clb_2_top_width_0_height_0__pin_35_lower ) , - .top_width_0_height_0__pin_36_upper ( grid_clb_2_top_width_0_height_0__pin_36_upper ) , - .top_width_0_height_0__pin_36_lower ( grid_clb_2_top_width_0_height_0__pin_36_lower ) , - .top_width_0_height_0__pin_37_upper ( grid_clb_2_top_width_0_height_0__pin_37_upper ) , - .top_width_0_height_0__pin_37_lower ( grid_clb_2_top_width_0_height_0__pin_37_lower ) , - .top_width_0_height_0__pin_38_upper ( grid_clb_2_top_width_0_height_0__pin_38_upper ) , - .top_width_0_height_0__pin_38_lower ( grid_clb_2_top_width_0_height_0__pin_38_lower ) , - .top_width_0_height_0__pin_39_upper ( grid_clb_2_top_width_0_height_0__pin_39_upper ) , - .top_width_0_height_0__pin_39_lower ( grid_clb_2_top_width_0_height_0__pin_39_lower ) , - .top_width_0_height_0__pin_40_upper ( grid_clb_2_top_width_0_height_0__pin_40_upper ) , - .top_width_0_height_0__pin_40_lower ( grid_clb_2_top_width_0_height_0__pin_40_lower ) , - .top_width_0_height_0__pin_41_upper ( grid_clb_2_top_width_0_height_0__pin_41_upper ) , - .top_width_0_height_0__pin_41_lower ( grid_clb_2_top_width_0_height_0__pin_41_lower ) , - .right_width_0_height_0__pin_42_upper ( grid_clb_2_right_width_0_height_0__pin_42_upper ) , - .right_width_0_height_0__pin_42_lower ( grid_clb_2_right_width_0_height_0__pin_42_lower ) , - .right_width_0_height_0__pin_43_upper ( grid_clb_2_right_width_0_height_0__pin_43_upper ) , - .right_width_0_height_0__pin_43_lower ( grid_clb_2_right_width_0_height_0__pin_43_lower ) , - .right_width_0_height_0__pin_44_upper ( grid_clb_2_right_width_0_height_0__pin_44_upper ) , - .right_width_0_height_0__pin_44_lower ( grid_clb_2_right_width_0_height_0__pin_44_lower ) , - .right_width_0_height_0__pin_45_upper ( grid_clb_2_right_width_0_height_0__pin_45_upper ) , - .right_width_0_height_0__pin_45_lower ( grid_clb_2_right_width_0_height_0__pin_45_lower ) , - .right_width_0_height_0__pin_46_upper ( grid_clb_2_right_width_0_height_0__pin_46_upper ) , - .right_width_0_height_0__pin_46_lower ( grid_clb_2_right_width_0_height_0__pin_46_lower ) , - .right_width_0_height_0__pin_47_upper ( grid_clb_2_right_width_0_height_0__pin_47_upper ) , - .right_width_0_height_0__pin_47_lower ( grid_clb_2_right_width_0_height_0__pin_47_lower ) , - .right_width_0_height_0__pin_48_upper ( grid_clb_2_right_width_0_height_0__pin_48_upper ) , - .right_width_0_height_0__pin_48_lower ( grid_clb_2_right_width_0_height_0__pin_48_lower ) , - .right_width_0_height_0__pin_49_upper ( grid_clb_2_right_width_0_height_0__pin_49_upper ) , - .right_width_0_height_0__pin_49_lower ( grid_clb_2_right_width_0_height_0__pin_49_lower ) , - .bottom_width_0_height_0__pin_50_ ( grid_clb_2__1__undriven_bottom_width_0_height_0__pin_50_ ) , - .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_17 } ) , - .ccff_tail ( grid_clb_2_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_18 ) , .SC_IN_BOT ( scff_Wires_8_ ) , - .SC_OUT_TOP ( scff_Wires_9_ ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_19 ) , - .VDD ( VDD ) , .VSS ( VSS ) , - .prog_clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_20 } ) , - .prog_clk__FEEDTHRU_2 ( prog_clk__FEEDTHRU_17 ) , - .prog_clk__FEEDTHRU_3 ( { SYNOPSYS_UNCONNECTED_21 } ) , - .prog_clk__FEEDTHRU_4 ( prog_clk__FEEDTHRU_19 ) , - .Test_en__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_22 } ) , - .clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_23 } ) ) ; -grid_clb grid_clb_2__2_ ( - .prog_clk ( { ctsbuf_net_1315 } ) , - .Test_en ( Test_en__FEEDTHRU_1 ) , .clk ( clk__FEEDTHRU_1 ) , - .top_width_0_height_0__pin_0_ ( cbx_1__2__1_bottom_grid_pin_0_ ) , - .top_width_0_height_0__pin_1_ ( cbx_1__2__1_bottom_grid_pin_1_ ) , - .top_width_0_height_0__pin_2_ ( cbx_1__2__1_bottom_grid_pin_2_ ) , - .top_width_0_height_0__pin_3_ ( cbx_1__2__1_bottom_grid_pin_3_ ) , - .top_width_0_height_0__pin_4_ ( cbx_1__2__1_bottom_grid_pin_4_ ) , - .top_width_0_height_0__pin_5_ ( cbx_1__2__1_bottom_grid_pin_5_ ) , - .top_width_0_height_0__pin_6_ ( cbx_1__2__1_bottom_grid_pin_6_ ) , - .top_width_0_height_0__pin_7_ ( cbx_1__2__1_bottom_grid_pin_7_ ) , - .top_width_0_height_0__pin_8_ ( cbx_1__2__1_bottom_grid_pin_8_ ) , - .top_width_0_height_0__pin_9_ ( cbx_1__2__1_bottom_grid_pin_9_ ) , - .top_width_0_height_0__pin_10_ ( cbx_1__2__1_bottom_grid_pin_10_ ) , - .top_width_0_height_0__pin_11_ ( cbx_1__2__1_bottom_grid_pin_11_ ) , - .top_width_0_height_0__pin_12_ ( cbx_1__2__1_bottom_grid_pin_12_ ) , - .top_width_0_height_0__pin_13_ ( cbx_1__2__1_bottom_grid_pin_13_ ) , - .top_width_0_height_0__pin_14_ ( cbx_1__2__1_bottom_grid_pin_14_ ) , - .top_width_0_height_0__pin_15_ ( cbx_1__2__1_bottom_grid_pin_15_ ) , - .top_width_0_height_0__pin_32_ ( direct_interc_2_out ) , - .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_24 } ) , - .right_width_0_height_0__pin_16_ ( cby_2__1__1_left_grid_pin_16_ ) , - .right_width_0_height_0__pin_17_ ( cby_2__1__1_left_grid_pin_17_ ) , - .right_width_0_height_0__pin_18_ ( cby_2__1__1_left_grid_pin_18_ ) , - .right_width_0_height_0__pin_19_ ( cby_2__1__1_left_grid_pin_19_ ) , - .right_width_0_height_0__pin_20_ ( cby_2__1__1_left_grid_pin_20_ ) , - .right_width_0_height_0__pin_21_ ( cby_2__1__1_left_grid_pin_21_ ) , - .right_width_0_height_0__pin_22_ ( cby_2__1__1_left_grid_pin_22_ ) , - .right_width_0_height_0__pin_23_ ( cby_2__1__1_left_grid_pin_23_ ) , - .right_width_0_height_0__pin_24_ ( cby_2__1__1_left_grid_pin_24_ ) , - .right_width_0_height_0__pin_25_ ( cby_2__1__1_left_grid_pin_25_ ) , - .right_width_0_height_0__pin_26_ ( cby_2__1__1_left_grid_pin_26_ ) , - .right_width_0_height_0__pin_27_ ( cby_2__1__1_left_grid_pin_27_ ) , - .right_width_0_height_0__pin_28_ ( cby_2__1__1_left_grid_pin_28_ ) , - .right_width_0_height_0__pin_29_ ( cby_2__1__1_left_grid_pin_29_ ) , - .right_width_0_height_0__pin_30_ ( cby_2__1__1_left_grid_pin_30_ ) , - .right_width_0_height_0__pin_31_ ( cby_2__1__1_left_grid_pin_31_ ) , - .left_width_0_height_0__pin_52_ ( grid_clb_2__2__undriven_left_width_0_height_0__pin_52_ ) , - .ccff_head ( cby_1__1__1_ccff_tail ) , - .top_width_0_height_0__pin_34_upper ( grid_clb_3_top_width_0_height_0__pin_34_upper ) , - .top_width_0_height_0__pin_34_lower ( grid_clb_3_top_width_0_height_0__pin_34_lower ) , - .top_width_0_height_0__pin_35_upper ( grid_clb_3_top_width_0_height_0__pin_35_upper ) , - .top_width_0_height_0__pin_35_lower ( grid_clb_3_top_width_0_height_0__pin_35_lower ) , - .top_width_0_height_0__pin_36_upper ( grid_clb_3_top_width_0_height_0__pin_36_upper ) , - .top_width_0_height_0__pin_36_lower ( grid_clb_3_top_width_0_height_0__pin_36_lower ) , - .top_width_0_height_0__pin_37_upper ( grid_clb_3_top_width_0_height_0__pin_37_upper ) , - .top_width_0_height_0__pin_37_lower ( grid_clb_3_top_width_0_height_0__pin_37_lower ) , - .top_width_0_height_0__pin_38_upper ( grid_clb_3_top_width_0_height_0__pin_38_upper ) , - .top_width_0_height_0__pin_38_lower ( grid_clb_3_top_width_0_height_0__pin_38_lower ) , - .top_width_0_height_0__pin_39_upper ( grid_clb_3_top_width_0_height_0__pin_39_upper ) , - .top_width_0_height_0__pin_39_lower ( grid_clb_3_top_width_0_height_0__pin_39_lower ) , - .top_width_0_height_0__pin_40_upper ( grid_clb_3_top_width_0_height_0__pin_40_upper ) , - .top_width_0_height_0__pin_40_lower ( grid_clb_3_top_width_0_height_0__pin_40_lower ) , - .top_width_0_height_0__pin_41_upper ( grid_clb_3_top_width_0_height_0__pin_41_upper ) , - .top_width_0_height_0__pin_41_lower ( grid_clb_3_top_width_0_height_0__pin_41_lower ) , - .right_width_0_height_0__pin_42_upper ( grid_clb_3_right_width_0_height_0__pin_42_upper ) , - .right_width_0_height_0__pin_42_lower ( grid_clb_3_right_width_0_height_0__pin_42_lower ) , - .right_width_0_height_0__pin_43_upper ( grid_clb_3_right_width_0_height_0__pin_43_upper ) , - .right_width_0_height_0__pin_43_lower ( grid_clb_3_right_width_0_height_0__pin_43_lower ) , - .right_width_0_height_0__pin_44_upper ( grid_clb_3_right_width_0_height_0__pin_44_upper ) , - .right_width_0_height_0__pin_44_lower ( grid_clb_3_right_width_0_height_0__pin_44_lower ) , - .right_width_0_height_0__pin_45_upper ( grid_clb_3_right_width_0_height_0__pin_45_upper ) , - .right_width_0_height_0__pin_45_lower ( grid_clb_3_right_width_0_height_0__pin_45_lower ) , - .right_width_0_height_0__pin_46_upper ( grid_clb_3_right_width_0_height_0__pin_46_upper ) , - .right_width_0_height_0__pin_46_lower ( grid_clb_3_right_width_0_height_0__pin_46_lower ) , - .right_width_0_height_0__pin_47_upper ( grid_clb_3_right_width_0_height_0__pin_47_upper ) , - .right_width_0_height_0__pin_47_lower ( grid_clb_3_right_width_0_height_0__pin_47_lower ) , - .right_width_0_height_0__pin_48_upper ( grid_clb_3_right_width_0_height_0__pin_48_upper ) , - .right_width_0_height_0__pin_48_lower ( grid_clb_3_right_width_0_height_0__pin_48_lower ) , - .right_width_0_height_0__pin_49_upper ( grid_clb_3_right_width_0_height_0__pin_49_upper ) , - .right_width_0_height_0__pin_49_lower ( grid_clb_3_right_width_0_height_0__pin_49_lower ) , - .bottom_width_0_height_0__pin_50_ ( grid_clb_3_bottom_width_0_height_0__pin_50_ ) , - .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_25 } ) , - .ccff_tail ( grid_clb_3_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_26 ) , .SC_IN_BOT ( scff_Wires_10_ ) , - .SC_OUT_TOP ( scff_Wires_11_ ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_27 ) , - .VDD ( VDD ) , .VSS ( VSS ) , - .prog_clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_28 } ) , - .prog_clk__FEEDTHRU_2 ( { SYNOPSYS_UNCONNECTED_29 } ) , - .prog_clk__FEEDTHRU_3 ( prog_clk__FEEDTHRU_13 ) , - .prog_clk__FEEDTHRU_4 ( prog_clk__FEEDTHRU_15 ) , - .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_2 ) , - .clk__FEEDTHRU_1 ( clk__FEEDTHRU_2 ) ) ; -sb_0__0_ sb_0__0_ ( - .prog_clk ( { ctsbuf_net_1719 } ) , - .chany_top_in ( cby_0__1__0_chany_bottom_out ) , - .top_left_grid_pin_1_ ( grid_io_left_0_right_width_0_height_0__pin_1_lower ) , - .chanx_right_in ( cbx_1__0__0_chanx_left_out ) , - .right_bottom_grid_pin_1_ ( grid_io_bottom_0_top_width_0_height_0__pin_1_upper ) , - .right_bottom_grid_pin_3_ ( grid_io_bottom_0_top_width_0_height_0__pin_3_upper ) , - .right_bottom_grid_pin_5_ ( grid_io_bottom_0_top_width_0_height_0__pin_5_upper ) , - .right_bottom_grid_pin_7_ ( grid_io_bottom_0_top_width_0_height_0__pin_7_upper ) , - .right_bottom_grid_pin_9_ ( grid_io_bottom_0_top_width_0_height_0__pin_9_upper ) , - .right_bottom_grid_pin_11_ ( grid_io_bottom_0_top_width_0_height_0__pin_11_upper ) , - .ccff_head ( grid_io_bottom_0_ccff_tail ) , - .chany_top_out ( sb_0__0__0_chany_top_out ) , - .chanx_right_out ( sb_0__0__0_chanx_right_out ) , - .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__1_ sb_0__1_ ( .prog_clk ( prog_clk__FEEDTHRU_4 ) , - .chany_top_in ( cby_0__1__1_chany_bottom_out ) , - .top_left_grid_pin_1_ ( grid_io_left_1_right_width_0_height_0__pin_1_lower ) , - .chanx_right_in ( cbx_1__1__0_chanx_left_out ) , - .right_bottom_grid_pin_34_ ( grid_clb_0_top_width_0_height_0__pin_34_upper ) , - .right_bottom_grid_pin_35_ ( grid_clb_0_top_width_0_height_0__pin_35_upper ) , - .right_bottom_grid_pin_36_ ( grid_clb_0_top_width_0_height_0__pin_36_upper ) , - .right_bottom_grid_pin_37_ ( grid_clb_0_top_width_0_height_0__pin_37_upper ) , - .right_bottom_grid_pin_38_ ( grid_clb_0_top_width_0_height_0__pin_38_upper ) , - .right_bottom_grid_pin_39_ ( grid_clb_0_top_width_0_height_0__pin_39_upper ) , - .right_bottom_grid_pin_40_ ( grid_clb_0_top_width_0_height_0__pin_40_upper ) , - .right_bottom_grid_pin_41_ ( grid_clb_0_top_width_0_height_0__pin_41_upper ) , - .chany_bottom_in ( cby_0__1__0_chany_top_out ) , - .bottom_left_grid_pin_1_ ( grid_io_left_0_right_width_0_height_0__pin_1_upper ) , - .ccff_head ( cbx_1__1__0_ccff_tail ) , - .chany_top_out ( sb_0__1__0_chany_top_out ) , - .chanx_right_out ( sb_0__1__0_chanx_right_out ) , - .chany_bottom_out ( sb_0__1__0_chany_bottom_out ) , - .ccff_tail ( sb_0__1__0_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , - .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_5 ) ) ; -sb_0__2_ sb_0__2_ ( .prog_clk ( prog_clk__FEEDTHRU_7 ) , - .chanx_right_in ( cbx_1__2__0_chanx_left_out ) , - .right_top_grid_pin_1_ ( grid_io_top_0_bottom_width_0_height_0__pin_1_upper ) , - .right_bottom_grid_pin_34_ ( grid_clb_1_top_width_0_height_0__pin_34_upper ) , - .right_bottom_grid_pin_35_ ( grid_clb_1_top_width_0_height_0__pin_35_upper ) , - .right_bottom_grid_pin_36_ ( grid_clb_1_top_width_0_height_0__pin_36_upper ) , - .right_bottom_grid_pin_37_ ( grid_clb_1_top_width_0_height_0__pin_37_upper ) , - .right_bottom_grid_pin_38_ ( grid_clb_1_top_width_0_height_0__pin_38_upper ) , - .right_bottom_grid_pin_39_ ( grid_clb_1_top_width_0_height_0__pin_39_upper ) , - .right_bottom_grid_pin_40_ ( grid_clb_1_top_width_0_height_0__pin_40_upper ) , - .right_bottom_grid_pin_41_ ( grid_clb_1_top_width_0_height_0__pin_41_upper ) , - .chany_bottom_in ( cby_0__1__1_chany_top_out ) , - .bottom_left_grid_pin_1_ ( grid_io_left_1_right_width_0_height_0__pin_1_upper ) , - .ccff_head ( grid_io_top_0_ccff_tail ) , - .chanx_right_out ( sb_0__2__0_chanx_right_out ) , - .chany_bottom_out ( sb_0__2__0_chany_bottom_out ) , - .ccff_tail ( sb_0__2__0_ccff_tail ) , .SC_IN_TOP ( sc_head ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_30 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_31 ) , .SC_OUT_BOT ( scff_Wires_0_ ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__0_ sb_1__0_ ( .prog_clk ( prog_clk ) , - .chany_top_in ( cby_1__1__0_chany_bottom_out ) , - .top_left_grid_pin_42_ ( grid_clb_0_right_width_0_height_0__pin_42_lower ) , - .top_left_grid_pin_43_ ( grid_clb_0_right_width_0_height_0__pin_43_lower ) , - .top_left_grid_pin_44_ ( grid_clb_0_right_width_0_height_0__pin_44_lower ) , - .top_left_grid_pin_45_ ( grid_clb_0_right_width_0_height_0__pin_45_lower ) , - .top_left_grid_pin_46_ ( grid_clb_0_right_width_0_height_0__pin_46_lower ) , - .top_left_grid_pin_47_ ( grid_clb_0_right_width_0_height_0__pin_47_lower ) , - .top_left_grid_pin_48_ ( grid_clb_0_right_width_0_height_0__pin_48_lower ) , - .top_left_grid_pin_49_ ( grid_clb_0_right_width_0_height_0__pin_49_lower ) , - .chanx_right_in ( cbx_1__0__1_chanx_left_out ) , - .right_bottom_grid_pin_1_ ( grid_io_bottom_1_top_width_0_height_0__pin_1_upper ) , - .right_bottom_grid_pin_3_ ( grid_io_bottom_1_top_width_0_height_0__pin_3_upper ) , - .right_bottom_grid_pin_5_ ( grid_io_bottom_1_top_width_0_height_0__pin_5_upper ) , - .right_bottom_grid_pin_7_ ( grid_io_bottom_1_top_width_0_height_0__pin_7_upper ) , - .right_bottom_grid_pin_9_ ( grid_io_bottom_1_top_width_0_height_0__pin_9_upper ) , - .right_bottom_grid_pin_11_ ( grid_io_bottom_1_top_width_0_height_0__pin_11_upper ) , - .chanx_left_in ( cbx_1__0__0_chanx_right_out ) , - .left_bottom_grid_pin_1_ ( grid_io_bottom_0_top_width_0_height_0__pin_1_lower ) , - .left_bottom_grid_pin_3_ ( grid_io_bottom_0_top_width_0_height_0__pin_3_lower ) , - .left_bottom_grid_pin_5_ ( grid_io_bottom_0_top_width_0_height_0__pin_5_lower ) , - .left_bottom_grid_pin_7_ ( grid_io_bottom_0_top_width_0_height_0__pin_7_lower ) , - .left_bottom_grid_pin_9_ ( grid_io_bottom_0_top_width_0_height_0__pin_9_lower ) , - .left_bottom_grid_pin_11_ ( grid_io_bottom_0_top_width_0_height_0__pin_11_lower ) , - .ccff_head ( grid_io_bottom_1_ccff_tail ) , - .chany_top_out ( sb_1__0__0_chany_top_out ) , - .chanx_right_out ( sb_1__0__0_chanx_right_out ) , - .chanx_left_out ( sb_1__0__0_chanx_left_out ) , - .ccff_tail ( sb_1__0__0_ccff_tail ) , .SC_IN_TOP ( scff_Wires_6_ ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_32 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_33 ) , .SC_OUT_BOT ( scff_Wires_7_ ) , - .VDD ( VDD ) , .VSS ( VSS ) , - .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_1 ) , - .prog_clk__FEEDTHRU_2 ( prog_clk__FEEDTHRU_8 ) ) ; -sb_1__1_ sb_1__1_ ( - .prog_clk ( { ctsbuf_net_2123 } ) , - .chany_top_in ( cby_1__1__1_chany_bottom_out ) , - .top_left_grid_pin_42_ ( grid_clb_1_right_width_0_height_0__pin_42_lower ) , - .top_left_grid_pin_43_ ( grid_clb_1_right_width_0_height_0__pin_43_lower ) , - .top_left_grid_pin_44_ ( grid_clb_1_right_width_0_height_0__pin_44_lower ) , - .top_left_grid_pin_45_ ( grid_clb_1_right_width_0_height_0__pin_45_lower ) , - .top_left_grid_pin_46_ ( grid_clb_1_right_width_0_height_0__pin_46_lower ) , - .top_left_grid_pin_47_ ( grid_clb_1_right_width_0_height_0__pin_47_lower ) , - .top_left_grid_pin_48_ ( grid_clb_1_right_width_0_height_0__pin_48_lower ) , - .top_left_grid_pin_49_ ( grid_clb_1_right_width_0_height_0__pin_49_lower ) , - .chanx_right_in ( cbx_1__1__1_chanx_left_out ) , - .right_bottom_grid_pin_34_ ( grid_clb_2_top_width_0_height_0__pin_34_upper ) , - .right_bottom_grid_pin_35_ ( grid_clb_2_top_width_0_height_0__pin_35_upper ) , - .right_bottom_grid_pin_36_ ( grid_clb_2_top_width_0_height_0__pin_36_upper ) , - .right_bottom_grid_pin_37_ ( grid_clb_2_top_width_0_height_0__pin_37_upper ) , - .right_bottom_grid_pin_38_ ( grid_clb_2_top_width_0_height_0__pin_38_upper ) , - .right_bottom_grid_pin_39_ ( grid_clb_2_top_width_0_height_0__pin_39_upper ) , - .right_bottom_grid_pin_40_ ( grid_clb_2_top_width_0_height_0__pin_40_upper ) , - .right_bottom_grid_pin_41_ ( grid_clb_2_top_width_0_height_0__pin_41_upper ) , - .chany_bottom_in ( cby_1__1__0_chany_top_out ) , - .bottom_left_grid_pin_42_ ( grid_clb_0_right_width_0_height_0__pin_42_upper ) , - .bottom_left_grid_pin_43_ ( grid_clb_0_right_width_0_height_0__pin_43_upper ) , - .bottom_left_grid_pin_44_ ( grid_clb_0_right_width_0_height_0__pin_44_upper ) , - .bottom_left_grid_pin_45_ ( grid_clb_0_right_width_0_height_0__pin_45_upper ) , - .bottom_left_grid_pin_46_ ( grid_clb_0_right_width_0_height_0__pin_46_upper ) , - .bottom_left_grid_pin_47_ ( grid_clb_0_right_width_0_height_0__pin_47_upper ) , - .bottom_left_grid_pin_48_ ( grid_clb_0_right_width_0_height_0__pin_48_upper ) , - .bottom_left_grid_pin_49_ ( grid_clb_0_right_width_0_height_0__pin_49_upper ) , - .chanx_left_in ( cbx_1__1__0_chanx_right_out ) , - .left_bottom_grid_pin_34_ ( grid_clb_0_top_width_0_height_0__pin_34_lower ) , - .left_bottom_grid_pin_35_ ( grid_clb_0_top_width_0_height_0__pin_35_lower ) , - .left_bottom_grid_pin_36_ ( grid_clb_0_top_width_0_height_0__pin_36_lower ) , - .left_bottom_grid_pin_37_ ( grid_clb_0_top_width_0_height_0__pin_37_lower ) , - .left_bottom_grid_pin_38_ ( grid_clb_0_top_width_0_height_0__pin_38_lower ) , - .left_bottom_grid_pin_39_ ( grid_clb_0_top_width_0_height_0__pin_39_lower ) , - .left_bottom_grid_pin_40_ ( grid_clb_0_top_width_0_height_0__pin_40_lower ) , - .left_bottom_grid_pin_41_ ( grid_clb_0_top_width_0_height_0__pin_41_lower ) , - .ccff_head ( cbx_1__1__1_ccff_tail ) , - .chany_top_out ( sb_1__1__0_chany_top_out ) , - .chanx_right_out ( sb_1__1__0_chanx_right_out ) , - .chany_bottom_out ( sb_1__1__0_chany_bottom_out ) , - .chanx_left_out ( sb_1__1__0_chanx_left_out ) , - .ccff_tail ( sb_1__1__0_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , - .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_10 ) , - .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_5 ) , - .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_6 ) , - .clk__FEEDTHRU_0 ( clk__FEEDTHRU_5 ) , - .clk__FEEDTHRU_1 ( clk__FEEDTHRU_6 ) , - .grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_0_bottom_width_0_height_0__pin_50_ ) , - .grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) ) ; -sb_1__2_ sb_1__2_ ( .prog_clk ( prog_clk__FEEDTHRU_11 ) , - .chanx_right_in ( cbx_1__2__1_chanx_left_out ) , - .right_top_grid_pin_1_ ( grid_io_top_1_bottom_width_0_height_0__pin_1_upper ) , - .right_bottom_grid_pin_34_ ( grid_clb_3_top_width_0_height_0__pin_34_upper ) , - .right_bottom_grid_pin_35_ ( grid_clb_3_top_width_0_height_0__pin_35_upper ) , - .right_bottom_grid_pin_36_ ( grid_clb_3_top_width_0_height_0__pin_36_upper ) , - .right_bottom_grid_pin_37_ ( grid_clb_3_top_width_0_height_0__pin_37_upper ) , - .right_bottom_grid_pin_38_ ( grid_clb_3_top_width_0_height_0__pin_38_upper ) , - .right_bottom_grid_pin_39_ ( grid_clb_3_top_width_0_height_0__pin_39_upper ) , - .right_bottom_grid_pin_40_ ( grid_clb_3_top_width_0_height_0__pin_40_upper ) , - .right_bottom_grid_pin_41_ ( grid_clb_3_top_width_0_height_0__pin_41_upper ) , - .chany_bottom_in ( cby_1__1__1_chany_top_out ) , - .bottom_left_grid_pin_42_ ( grid_clb_1_right_width_0_height_0__pin_42_upper ) , - .bottom_left_grid_pin_43_ ( grid_clb_1_right_width_0_height_0__pin_43_upper ) , - .bottom_left_grid_pin_44_ ( grid_clb_1_right_width_0_height_0__pin_44_upper ) , - .bottom_left_grid_pin_45_ ( grid_clb_1_right_width_0_height_0__pin_45_upper ) , - .bottom_left_grid_pin_46_ ( grid_clb_1_right_width_0_height_0__pin_46_upper ) , - .bottom_left_grid_pin_47_ ( grid_clb_1_right_width_0_height_0__pin_47_upper ) , - .bottom_left_grid_pin_48_ ( grid_clb_1_right_width_0_height_0__pin_48_upper ) , - .bottom_left_grid_pin_49_ ( grid_clb_1_right_width_0_height_0__pin_49_upper ) , - .chanx_left_in ( cbx_1__2__0_chanx_right_out ) , - .left_top_grid_pin_1_ ( grid_io_top_0_bottom_width_0_height_0__pin_1_lower ) , - .left_bottom_grid_pin_34_ ( grid_clb_1_top_width_0_height_0__pin_34_lower ) , - .left_bottom_grid_pin_35_ ( grid_clb_1_top_width_0_height_0__pin_35_lower ) , - .left_bottom_grid_pin_36_ ( grid_clb_1_top_width_0_height_0__pin_36_lower ) , - .left_bottom_grid_pin_37_ ( grid_clb_1_top_width_0_height_0__pin_37_lower ) , - .left_bottom_grid_pin_38_ ( grid_clb_1_top_width_0_height_0__pin_38_lower ) , - .left_bottom_grid_pin_39_ ( grid_clb_1_top_width_0_height_0__pin_39_lower ) , - .left_bottom_grid_pin_40_ ( grid_clb_1_top_width_0_height_0__pin_40_lower ) , - .left_bottom_grid_pin_41_ ( grid_clb_1_top_width_0_height_0__pin_41_lower ) , - .ccff_head ( grid_io_top_1_ccff_tail ) , - .chanx_right_out ( sb_1__2__0_chanx_right_out ) , - .chany_bottom_out ( sb_1__2__0_chany_bottom_out ) , - .chanx_left_out ( sb_1__2__0_chanx_left_out ) , - .ccff_tail ( sb_1__2__0_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_34 ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_35 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_36 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_37 ) , .VDD ( VDD ) , .VSS ( VSS ) , - .Test_en__FEEDTHRU_0 ( Test_en ) , - .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_4 ) , - .Test_en__FEEDTHRU_2 ( Test_en__FEEDTHRU_1 ) , .clk__FEEDTHRU_0 ( clk ) , - .clk__FEEDTHRU_1 ( clk__FEEDTHRU_4 ) , - .clk__FEEDTHRU_2 ( clk__FEEDTHRU_1 ) ) ; -sb_2__0_ sb_2__0_ ( - .prog_clk ( { ctsbuf_net_2729 } ) , - .chany_top_in ( cby_2__1__0_chany_bottom_out ) , - .top_left_grid_pin_42_ ( grid_clb_2_right_width_0_height_0__pin_42_lower ) , - .top_left_grid_pin_43_ ( grid_clb_2_right_width_0_height_0__pin_43_lower ) , - .top_left_grid_pin_44_ ( grid_clb_2_right_width_0_height_0__pin_44_lower ) , - .top_left_grid_pin_45_ ( grid_clb_2_right_width_0_height_0__pin_45_lower ) , - .top_left_grid_pin_46_ ( grid_clb_2_right_width_0_height_0__pin_46_lower ) , - .top_left_grid_pin_47_ ( grid_clb_2_right_width_0_height_0__pin_47_lower ) , - .top_left_grid_pin_48_ ( grid_clb_2_right_width_0_height_0__pin_48_lower ) , - .top_left_grid_pin_49_ ( grid_clb_2_right_width_0_height_0__pin_49_lower ) , - .top_right_grid_pin_1_ ( grid_io_right_0_left_width_0_height_0__pin_1_lower ) , - .chanx_left_in ( cbx_1__0__1_chanx_right_out ) , - .left_bottom_grid_pin_1_ ( grid_io_bottom_1_top_width_0_height_0__pin_1_lower ) , - .left_bottom_grid_pin_3_ ( grid_io_bottom_1_top_width_0_height_0__pin_3_lower ) , - .left_bottom_grid_pin_5_ ( grid_io_bottom_1_top_width_0_height_0__pin_5_lower ) , - .left_bottom_grid_pin_7_ ( grid_io_bottom_1_top_width_0_height_0__pin_7_lower ) , - .left_bottom_grid_pin_9_ ( grid_io_bottom_1_top_width_0_height_0__pin_9_lower ) , - .left_bottom_grid_pin_11_ ( grid_io_bottom_1_top_width_0_height_0__pin_11_lower ) , - .ccff_head ( grid_io_right_0_ccff_tail ) , - .chany_top_out ( sb_2__0__0_chany_top_out ) , - .chanx_left_out ( sb_2__0__0_chanx_left_out ) , - .ccff_tail ( sb_2__0__0_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__1_ sb_2__1_ ( .prog_clk ( prog_clk__FEEDTHRU_18 ) , - .chany_top_in ( cby_2__1__1_chany_bottom_out ) , - .top_left_grid_pin_42_ ( grid_clb_3_right_width_0_height_0__pin_42_lower ) , - .top_left_grid_pin_43_ ( grid_clb_3_right_width_0_height_0__pin_43_lower ) , - .top_left_grid_pin_44_ ( grid_clb_3_right_width_0_height_0__pin_44_lower ) , - .top_left_grid_pin_45_ ( grid_clb_3_right_width_0_height_0__pin_45_lower ) , - .top_left_grid_pin_46_ ( grid_clb_3_right_width_0_height_0__pin_46_lower ) , - .top_left_grid_pin_47_ ( grid_clb_3_right_width_0_height_0__pin_47_lower ) , - .top_left_grid_pin_48_ ( grid_clb_3_right_width_0_height_0__pin_48_lower ) , - .top_left_grid_pin_49_ ( grid_clb_3_right_width_0_height_0__pin_49_lower ) , - .top_right_grid_pin_1_ ( grid_io_right_1_left_width_0_height_0__pin_1_lower ) , - .chany_bottom_in ( cby_2__1__0_chany_top_out ) , - .bottom_right_grid_pin_1_ ( grid_io_right_0_left_width_0_height_0__pin_1_upper ) , - .bottom_left_grid_pin_42_ ( grid_clb_2_right_width_0_height_0__pin_42_upper ) , - .bottom_left_grid_pin_43_ ( grid_clb_2_right_width_0_height_0__pin_43_upper ) , - .bottom_left_grid_pin_44_ ( grid_clb_2_right_width_0_height_0__pin_44_upper ) , - .bottom_left_grid_pin_45_ ( grid_clb_2_right_width_0_height_0__pin_45_upper ) , - .bottom_left_grid_pin_46_ ( grid_clb_2_right_width_0_height_0__pin_46_upper ) , - .bottom_left_grid_pin_47_ ( grid_clb_2_right_width_0_height_0__pin_47_upper ) , - .bottom_left_grid_pin_48_ ( grid_clb_2_right_width_0_height_0__pin_48_upper ) , - .bottom_left_grid_pin_49_ ( grid_clb_2_right_width_0_height_0__pin_49_upper ) , - .chanx_left_in ( cbx_1__1__1_chanx_right_out ) , - .left_bottom_grid_pin_34_ ( grid_clb_2_top_width_0_height_0__pin_34_lower ) , - .left_bottom_grid_pin_35_ ( grid_clb_2_top_width_0_height_0__pin_35_lower ) , - .left_bottom_grid_pin_36_ ( grid_clb_2_top_width_0_height_0__pin_36_lower ) , - .left_bottom_grid_pin_37_ ( grid_clb_2_top_width_0_height_0__pin_37_lower ) , - .left_bottom_grid_pin_38_ ( grid_clb_2_top_width_0_height_0__pin_38_lower ) , - .left_bottom_grid_pin_39_ ( grid_clb_2_top_width_0_height_0__pin_39_lower ) , - .left_bottom_grid_pin_40_ ( grid_clb_2_top_width_0_height_0__pin_40_lower ) , - .left_bottom_grid_pin_41_ ( grid_clb_2_top_width_0_height_0__pin_41_lower ) , - .ccff_head ( grid_io_right_1_ccff_tail ) , - .chany_top_out ( sb_2__1__0_chany_top_out ) , - .chany_bottom_out ( sb_2__1__0_chany_bottom_out ) , - .chanx_left_out ( sb_2__1__0_chanx_left_out ) , - .ccff_tail ( sb_2__1__0_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , - .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_2 ) , - .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_3 ) , - .clk__FEEDTHRU_0 ( clk__FEEDTHRU_2 ) , - .clk__FEEDTHRU_1 ( clk__FEEDTHRU_3 ) ) ; -sb_2__2_ sb_2__2_ ( .prog_clk ( prog_clk__FEEDTHRU_14 ) , - .chany_bottom_in ( cby_2__1__1_chany_top_out ) , - .bottom_right_grid_pin_1_ ( grid_io_right_1_left_width_0_height_0__pin_1_upper ) , - .bottom_left_grid_pin_42_ ( grid_clb_3_right_width_0_height_0__pin_42_upper ) , - .bottom_left_grid_pin_43_ ( grid_clb_3_right_width_0_height_0__pin_43_upper ) , - .bottom_left_grid_pin_44_ ( grid_clb_3_right_width_0_height_0__pin_44_upper ) , - .bottom_left_grid_pin_45_ ( grid_clb_3_right_width_0_height_0__pin_45_upper ) , - .bottom_left_grid_pin_46_ ( grid_clb_3_right_width_0_height_0__pin_46_upper ) , - .bottom_left_grid_pin_47_ ( grid_clb_3_right_width_0_height_0__pin_47_upper ) , - .bottom_left_grid_pin_48_ ( grid_clb_3_right_width_0_height_0__pin_48_upper ) , - .bottom_left_grid_pin_49_ ( grid_clb_3_right_width_0_height_0__pin_49_upper ) , - .chanx_left_in ( cbx_1__2__1_chanx_right_out ) , - .left_top_grid_pin_1_ ( grid_io_top_1_bottom_width_0_height_0__pin_1_lower ) , - .left_bottom_grid_pin_34_ ( grid_clb_3_top_width_0_height_0__pin_34_lower ) , - .left_bottom_grid_pin_35_ ( grid_clb_3_top_width_0_height_0__pin_35_lower ) , - .left_bottom_grid_pin_36_ ( grid_clb_3_top_width_0_height_0__pin_36_lower ) , - .left_bottom_grid_pin_37_ ( grid_clb_3_top_width_0_height_0__pin_37_lower ) , - .left_bottom_grid_pin_38_ ( grid_clb_3_top_width_0_height_0__pin_38_lower ) , - .left_bottom_grid_pin_39_ ( grid_clb_3_top_width_0_height_0__pin_39_lower ) , - .left_bottom_grid_pin_40_ ( grid_clb_3_top_width_0_height_0__pin_40_lower ) , - .left_bottom_grid_pin_41_ ( grid_clb_3_top_width_0_height_0__pin_41_lower ) , - .ccff_head ( ccff_head ) , - .chany_bottom_out ( sb_2__2__0_chany_bottom_out ) , - .chanx_left_out ( sb_2__2__0_chanx_left_out ) , - .ccff_tail ( sb_2__2__0_ccff_tail ) , .SC_IN_TOP ( scff_Wires_12_ ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_38 ) , .SC_OUT_TOP ( sc_tail ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_39 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__0_ cbx_1__0_ ( - .prog_clk ( { ctsbuf_net_2426 } ) , - .chanx_left_in ( sb_0__0__0_chanx_right_out ) , - .chanx_right_in ( sb_1__0__0_chanx_left_out ) , - .ccff_head ( sb_1__0__0_ccff_tail ) , - .chanx_left_out ( cbx_1__0__0_chanx_left_out ) , - .chanx_right_out ( cbx_1__0__0_chanx_right_out ) , - .bottom_grid_pin_0_ ( cbx_1__0__0_bottom_grid_pin_0_ ) , - .bottom_grid_pin_2_ ( cbx_1__0__0_bottom_grid_pin_2_ ) , - .bottom_grid_pin_4_ ( cbx_1__0__0_bottom_grid_pin_4_ ) , - .bottom_grid_pin_6_ ( cbx_1__0__0_bottom_grid_pin_6_ ) , - .bottom_grid_pin_8_ ( cbx_1__0__0_bottom_grid_pin_8_ ) , - .bottom_grid_pin_10_ ( cbx_1__0__0_bottom_grid_pin_10_ ) , - .ccff_tail ( grid_io_bottom_0_ccff_tail ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[4:9] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[4:9] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[4:9] ) , - .top_width_0_height_0__pin_0_ ( cbx_1__0__0_bottom_grid_pin_0_ ) , - .top_width_0_height_0__pin_2_ ( cbx_1__0__0_bottom_grid_pin_2_ ) , - .top_width_0_height_0__pin_4_ ( cbx_1__0__0_bottom_grid_pin_4_ ) , - .top_width_0_height_0__pin_6_ ( cbx_1__0__0_bottom_grid_pin_6_ ) , - .top_width_0_height_0__pin_8_ ( cbx_1__0__0_bottom_grid_pin_8_ ) , - .top_width_0_height_0__pin_10_ ( cbx_1__0__0_bottom_grid_pin_10_ ) , - .top_width_0_height_0__pin_1_upper ( grid_io_bottom_0_top_width_0_height_0__pin_1_upper ) , - .top_width_0_height_0__pin_1_lower ( grid_io_bottom_0_top_width_0_height_0__pin_1_lower ) , - .top_width_0_height_0__pin_3_upper ( grid_io_bottom_0_top_width_0_height_0__pin_3_upper ) , - .top_width_0_height_0__pin_3_lower ( grid_io_bottom_0_top_width_0_height_0__pin_3_lower ) , - .top_width_0_height_0__pin_5_upper ( grid_io_bottom_0_top_width_0_height_0__pin_5_upper ) , - .top_width_0_height_0__pin_5_lower ( grid_io_bottom_0_top_width_0_height_0__pin_5_lower ) , - .top_width_0_height_0__pin_7_upper ( grid_io_bottom_0_top_width_0_height_0__pin_7_upper ) , - .top_width_0_height_0__pin_7_lower ( grid_io_bottom_0_top_width_0_height_0__pin_7_lower ) , - .top_width_0_height_0__pin_9_upper ( grid_io_bottom_0_top_width_0_height_0__pin_9_upper ) , - .top_width_0_height_0__pin_9_lower ( grid_io_bottom_0_top_width_0_height_0__pin_9_lower ) , - .top_width_0_height_0__pin_11_upper ( grid_io_bottom_0_top_width_0_height_0__pin_11_upper ) , - .top_width_0_height_0__pin_11_lower ( grid_io_bottom_0_top_width_0_height_0__pin_11_lower ) , - .SC_IN_TOP ( scff_Wires_5_ ) , .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_40 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_41 ) , .SC_OUT_BOT ( scff_Wires_6_ ) , - .VDD ( VDD ) , .VSS ( VSS ) , - .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_2 ) ) ; -cbx_1__0_ cbx_2__0_ ( - .prog_clk ( { ctsbuf_net_2729 } ) , - .chanx_left_in ( sb_1__0__0_chanx_right_out ) , - .chanx_right_in ( sb_2__0__0_chanx_left_out ) , - .ccff_head ( sb_2__0__0_ccff_tail ) , - .chanx_left_out ( cbx_1__0__1_chanx_left_out ) , - .chanx_right_out ( cbx_1__0__1_chanx_right_out ) , - .bottom_grid_pin_0_ ( cbx_1__0__1_bottom_grid_pin_0_ ) , - .bottom_grid_pin_2_ ( cbx_1__0__1_bottom_grid_pin_2_ ) , - .bottom_grid_pin_4_ ( cbx_1__0__1_bottom_grid_pin_4_ ) , - .bottom_grid_pin_6_ ( cbx_1__0__1_bottom_grid_pin_6_ ) , - .bottom_grid_pin_8_ ( cbx_1__0__1_bottom_grid_pin_8_ ) , - .bottom_grid_pin_10_ ( cbx_1__0__1_bottom_grid_pin_10_ ) , - .ccff_tail ( grid_io_bottom_1_ccff_tail ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[10:15] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[10:15] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[10:15] ) , - .top_width_0_height_0__pin_0_ ( cbx_1__0__1_bottom_grid_pin_0_ ) , - .top_width_0_height_0__pin_2_ ( cbx_1__0__1_bottom_grid_pin_2_ ) , - .top_width_0_height_0__pin_4_ ( cbx_1__0__1_bottom_grid_pin_4_ ) , - .top_width_0_height_0__pin_6_ ( cbx_1__0__1_bottom_grid_pin_6_ ) , - .top_width_0_height_0__pin_8_ ( cbx_1__0__1_bottom_grid_pin_8_ ) , - .top_width_0_height_0__pin_10_ ( cbx_1__0__1_bottom_grid_pin_10_ ) , - .top_width_0_height_0__pin_1_upper ( grid_io_bottom_1_top_width_0_height_0__pin_1_upper ) , - .top_width_0_height_0__pin_1_lower ( grid_io_bottom_1_top_width_0_height_0__pin_1_lower ) , - .top_width_0_height_0__pin_3_upper ( grid_io_bottom_1_top_width_0_height_0__pin_3_upper ) , - .top_width_0_height_0__pin_3_lower ( grid_io_bottom_1_top_width_0_height_0__pin_3_lower ) , - .top_width_0_height_0__pin_5_upper ( grid_io_bottom_1_top_width_0_height_0__pin_5_upper ) , - .top_width_0_height_0__pin_5_lower ( grid_io_bottom_1_top_width_0_height_0__pin_5_lower ) , - .top_width_0_height_0__pin_7_upper ( grid_io_bottom_1_top_width_0_height_0__pin_7_upper ) , - .top_width_0_height_0__pin_7_lower ( grid_io_bottom_1_top_width_0_height_0__pin_7_lower ) , - .top_width_0_height_0__pin_9_upper ( grid_io_bottom_1_top_width_0_height_0__pin_9_upper ) , - .top_width_0_height_0__pin_9_lower ( grid_io_bottom_1_top_width_0_height_0__pin_9_lower ) , - .top_width_0_height_0__pin_11_upper ( grid_io_bottom_1_top_width_0_height_0__pin_11_upper ) , - .top_width_0_height_0__pin_11_lower ( grid_io_bottom_1_top_width_0_height_0__pin_11_lower ) , - .SC_IN_TOP ( scff_Wires_7_ ) , .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_42 ) , - .SC_OUT_TOP ( scff_Wires_8_ ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_43 ) , - .VDD ( VDD ) , .VSS ( VSS ) , - .prog_clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_44 } ) ) ; -cbx_1__1_ cbx_1__1_ ( .prog_clk ( prog_clk__FEEDTHRU_3 ) , - .chanx_left_in ( sb_0__1__0_chanx_right_out ) , - .chanx_right_in ( sb_1__1__0_chanx_left_out ) , - .ccff_head ( sb_1__1__0_ccff_tail ) , - .chanx_left_out ( cbx_1__1__0_chanx_left_out ) , - .chanx_right_out ( cbx_1__1__0_chanx_right_out ) , - .bottom_grid_pin_0_ ( cbx_1__1__0_bottom_grid_pin_0_ ) , - .bottom_grid_pin_1_ ( cbx_1__1__0_bottom_grid_pin_1_ ) , - .bottom_grid_pin_2_ ( cbx_1__1__0_bottom_grid_pin_2_ ) , - .bottom_grid_pin_3_ ( cbx_1__1__0_bottom_grid_pin_3_ ) , - .bottom_grid_pin_4_ ( cbx_1__1__0_bottom_grid_pin_4_ ) , - .bottom_grid_pin_5_ ( cbx_1__1__0_bottom_grid_pin_5_ ) , - .bottom_grid_pin_6_ ( cbx_1__1__0_bottom_grid_pin_6_ ) , - .bottom_grid_pin_7_ ( cbx_1__1__0_bottom_grid_pin_7_ ) , - .bottom_grid_pin_8_ ( cbx_1__1__0_bottom_grid_pin_8_ ) , - .bottom_grid_pin_9_ ( cbx_1__1__0_bottom_grid_pin_9_ ) , - .bottom_grid_pin_10_ ( cbx_1__1__0_bottom_grid_pin_10_ ) , - .bottom_grid_pin_11_ ( cbx_1__1__0_bottom_grid_pin_11_ ) , - .bottom_grid_pin_12_ ( cbx_1__1__0_bottom_grid_pin_12_ ) , - .bottom_grid_pin_13_ ( cbx_1__1__0_bottom_grid_pin_13_ ) , - .bottom_grid_pin_14_ ( cbx_1__1__0_bottom_grid_pin_14_ ) , - .bottom_grid_pin_15_ ( cbx_1__1__0_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__0_ccff_tail ) , .SC_IN_TOP ( scff_Wires_2_ ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_45 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_46 ) , .SC_OUT_BOT ( scff_Wires_3_ ) , - .VDD ( VDD ) , .VSS ( VSS ) , - .prog_clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_47 } ) ) ; -cbx_1__1_ cbx_2__1_ ( .prog_clk ( prog_clk__FEEDTHRU_17 ) , - .chanx_left_in ( sb_1__1__0_chanx_right_out ) , - .chanx_right_in ( sb_2__1__0_chanx_left_out ) , - .ccff_head ( sb_2__1__0_ccff_tail ) , - .chanx_left_out ( cbx_1__1__1_chanx_left_out ) , - .chanx_right_out ( cbx_1__1__1_chanx_right_out ) , - .bottom_grid_pin_0_ ( cbx_1__1__1_bottom_grid_pin_0_ ) , - .bottom_grid_pin_1_ ( cbx_1__1__1_bottom_grid_pin_1_ ) , - .bottom_grid_pin_2_ ( cbx_1__1__1_bottom_grid_pin_2_ ) , - .bottom_grid_pin_3_ ( cbx_1__1__1_bottom_grid_pin_3_ ) , - .bottom_grid_pin_4_ ( cbx_1__1__1_bottom_grid_pin_4_ ) , - .bottom_grid_pin_5_ ( cbx_1__1__1_bottom_grid_pin_5_ ) , - .bottom_grid_pin_6_ ( cbx_1__1__1_bottom_grid_pin_6_ ) , - .bottom_grid_pin_7_ ( cbx_1__1__1_bottom_grid_pin_7_ ) , - .bottom_grid_pin_8_ ( cbx_1__1__1_bottom_grid_pin_8_ ) , - .bottom_grid_pin_9_ ( cbx_1__1__1_bottom_grid_pin_9_ ) , - .bottom_grid_pin_10_ ( cbx_1__1__1_bottom_grid_pin_10_ ) , - .bottom_grid_pin_11_ ( cbx_1__1__1_bottom_grid_pin_11_ ) , - .bottom_grid_pin_12_ ( cbx_1__1__1_bottom_grid_pin_12_ ) , - .bottom_grid_pin_13_ ( cbx_1__1__1_bottom_grid_pin_13_ ) , - .bottom_grid_pin_14_ ( cbx_1__1__1_bottom_grid_pin_14_ ) , - .bottom_grid_pin_15_ ( cbx_1__1__1_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__1_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_48 ) , .SC_IN_BOT ( scff_Wires_9_ ) , - .SC_OUT_TOP ( scff_Wires_10_ ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_49 ) , - .VDD ( VDD ) , .VSS ( VSS ) , - .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_18 ) ) ; -cbx_1__2_ cbx_1__2_ ( .prog_clk ( prog_clk__FEEDTHRU_6 ) , - .chanx_left_in ( sb_0__2__0_chanx_right_out ) , - .chanx_right_in ( sb_1__2__0_chanx_left_out ) , - .ccff_head ( sb_1__2__0_ccff_tail ) , - .chanx_left_out ( cbx_1__2__0_chanx_left_out ) , - .chanx_right_out ( cbx_1__2__0_chanx_right_out ) , - .top_grid_pin_0_ ( cbx_1__2__0_top_grid_pin_0_ ) , - .bottom_grid_pin_0_ ( cbx_1__2__0_bottom_grid_pin_0_ ) , - .bottom_grid_pin_1_ ( cbx_1__2__0_bottom_grid_pin_1_ ) , - .bottom_grid_pin_2_ ( cbx_1__2__0_bottom_grid_pin_2_ ) , - .bottom_grid_pin_3_ ( cbx_1__2__0_bottom_grid_pin_3_ ) , - .bottom_grid_pin_4_ ( cbx_1__2__0_bottom_grid_pin_4_ ) , - .bottom_grid_pin_5_ ( cbx_1__2__0_bottom_grid_pin_5_ ) , - .bottom_grid_pin_6_ ( cbx_1__2__0_bottom_grid_pin_6_ ) , - .bottom_grid_pin_7_ ( cbx_1__2__0_bottom_grid_pin_7_ ) , - .bottom_grid_pin_8_ ( cbx_1__2__0_bottom_grid_pin_8_ ) , - .bottom_grid_pin_9_ ( cbx_1__2__0_bottom_grid_pin_9_ ) , - .bottom_grid_pin_10_ ( cbx_1__2__0_bottom_grid_pin_10_ ) , - .bottom_grid_pin_11_ ( cbx_1__2__0_bottom_grid_pin_11_ ) , - .bottom_grid_pin_12_ ( cbx_1__2__0_bottom_grid_pin_12_ ) , - .bottom_grid_pin_13_ ( cbx_1__2__0_bottom_grid_pin_13_ ) , - .bottom_grid_pin_14_ ( cbx_1__2__0_bottom_grid_pin_14_ ) , - .bottom_grid_pin_15_ ( cbx_1__2__0_bottom_grid_pin_15_ ) , - .ccff_tail ( grid_io_top_0_ccff_tail ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , - .bottom_width_0_height_0__pin_0_ ( cbx_1__2__0_top_grid_pin_0_ ) , - .bottom_width_0_height_0__pin_1_upper ( grid_io_top_0_bottom_width_0_height_0__pin_1_upper ) , - .bottom_width_0_height_0__pin_1_lower ( grid_io_top_0_bottom_width_0_height_0__pin_1_lower ) , - .SC_IN_TOP ( scff_Wires_0_ ) , .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_50 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_51 ) , .SC_OUT_BOT ( scff_Wires_1_ ) , - .VDD ( VDD ) , .VSS ( VSS ) , - .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_7 ) , - .prog_clk__FEEDTHRU_2 ( { SYNOPSYS_UNCONNECTED_52 } ) ) ; -cbx_1__2_ cbx_2__2_ ( .prog_clk ( prog_clk__FEEDTHRU_13 ) , - .chanx_left_in ( sb_1__2__0_chanx_right_out ) , - .chanx_right_in ( sb_2__2__0_chanx_left_out ) , - .ccff_head ( sb_2__2__0_ccff_tail ) , - .chanx_left_out ( cbx_1__2__1_chanx_left_out ) , - .chanx_right_out ( cbx_1__2__1_chanx_right_out ) , - .top_grid_pin_0_ ( cbx_1__2__1_top_grid_pin_0_ ) , - .bottom_grid_pin_0_ ( cbx_1__2__1_bottom_grid_pin_0_ ) , - .bottom_grid_pin_1_ ( cbx_1__2__1_bottom_grid_pin_1_ ) , - .bottom_grid_pin_2_ ( cbx_1__2__1_bottom_grid_pin_2_ ) , - .bottom_grid_pin_3_ ( cbx_1__2__1_bottom_grid_pin_3_ ) , - .bottom_grid_pin_4_ ( cbx_1__2__1_bottom_grid_pin_4_ ) , - .bottom_grid_pin_5_ ( cbx_1__2__1_bottom_grid_pin_5_ ) , - .bottom_grid_pin_6_ ( cbx_1__2__1_bottom_grid_pin_6_ ) , - .bottom_grid_pin_7_ ( cbx_1__2__1_bottom_grid_pin_7_ ) , - .bottom_grid_pin_8_ ( cbx_1__2__1_bottom_grid_pin_8_ ) , - .bottom_grid_pin_9_ ( cbx_1__2__1_bottom_grid_pin_9_ ) , - .bottom_grid_pin_10_ ( cbx_1__2__1_bottom_grid_pin_10_ ) , - .bottom_grid_pin_11_ ( cbx_1__2__1_bottom_grid_pin_11_ ) , - .bottom_grid_pin_12_ ( cbx_1__2__1_bottom_grid_pin_12_ ) , - .bottom_grid_pin_13_ ( cbx_1__2__1_bottom_grid_pin_13_ ) , - .bottom_grid_pin_14_ ( cbx_1__2__1_bottom_grid_pin_14_ ) , - .bottom_grid_pin_15_ ( cbx_1__2__1_bottom_grid_pin_15_ ) , - .ccff_tail ( grid_io_top_1_ccff_tail ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[1] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[1] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[1] ) , - .bottom_width_0_height_0__pin_0_ ( cbx_1__2__1_top_grid_pin_0_ ) , - .bottom_width_0_height_0__pin_1_upper ( grid_io_top_1_bottom_width_0_height_0__pin_1_upper ) , - .bottom_width_0_height_0__pin_1_lower ( grid_io_top_1_bottom_width_0_height_0__pin_1_lower ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_53 ) , .SC_IN_BOT ( scff_Wires_11_ ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_54 ) , .SC_OUT_BOT ( scff_Wires_12_ ) , - .VDD ( VDD ) , .VSS ( VSS ) , - .prog_clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_55 } ) , - .prog_clk__FEEDTHRU_2 ( prog_clk__FEEDTHRU_14 ) ) ; -cby_0__1_ cby_0__1_ ( - .prog_clk ( { ctsbuf_net_1719 } ) , - .chany_bottom_in ( sb_0__0__0_chany_top_out ) , - .chany_top_in ( sb_0__1__0_chany_bottom_out ) , - .ccff_head ( sb_0__1__0_ccff_tail ) , - .chany_bottom_out ( cby_0__1__0_chany_bottom_out ) , - .chany_top_out ( cby_0__1__0_chany_top_out ) , - .left_grid_pin_0_ ( cby_0__1__0_left_grid_pin_0_ ) , - .ccff_tail ( grid_io_left_0_ccff_tail ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[16] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[16] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[16] ) , - .right_width_0_height_0__pin_0_ ( cby_0__1__0_left_grid_pin_0_ ) , - .right_width_0_height_0__pin_1_upper ( grid_io_left_0_right_width_0_height_0__pin_1_upper ) , - .right_width_0_height_0__pin_1_lower ( grid_io_left_0_right_width_0_height_0__pin_1_lower ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -cby_0__1_ cby_0__2_ ( .prog_clk ( prog_clk__FEEDTHRU_5 ) , - .chany_bottom_in ( sb_0__1__0_chany_top_out ) , - .chany_top_in ( sb_0__2__0_chany_bottom_out ) , - .ccff_head ( sb_0__2__0_ccff_tail ) , - .chany_bottom_out ( cby_0__1__1_chany_bottom_out ) , - .chany_top_out ( cby_0__1__1_chany_top_out ) , - .left_grid_pin_0_ ( cby_0__1__1_left_grid_pin_0_ ) , - .ccff_tail ( grid_io_left_1_ccff_tail ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[17] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[17] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[17] ) , - .right_width_0_height_0__pin_0_ ( cby_0__1__1_left_grid_pin_0_ ) , - .right_width_0_height_0__pin_1_upper ( grid_io_left_1_right_width_0_height_0__pin_1_upper ) , - .right_width_0_height_0__pin_1_lower ( grid_io_left_1_right_width_0_height_0__pin_1_lower ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -cby_1__1_ cby_1__1_ ( - .prog_clk ( { ctsbuf_net_2325 } ) , - .chany_bottom_in ( sb_1__0__0_chany_top_out ) , - .chany_top_in ( sb_1__1__0_chany_bottom_out ) , - .ccff_head ( grid_clb_0_ccff_tail ) , - .chany_bottom_out ( cby_1__1__0_chany_bottom_out ) , - .chany_top_out ( cby_1__1__0_chany_top_out ) , - .left_grid_pin_16_ ( cby_1__1__0_left_grid_pin_16_ ) , - .left_grid_pin_17_ ( cby_1__1__0_left_grid_pin_17_ ) , - .left_grid_pin_18_ ( cby_1__1__0_left_grid_pin_18_ ) , - .left_grid_pin_19_ ( cby_1__1__0_left_grid_pin_19_ ) , - .left_grid_pin_20_ ( cby_1__1__0_left_grid_pin_20_ ) , - .left_grid_pin_21_ ( cby_1__1__0_left_grid_pin_21_ ) , - .left_grid_pin_22_ ( cby_1__1__0_left_grid_pin_22_ ) , - .left_grid_pin_23_ ( cby_1__1__0_left_grid_pin_23_ ) , - .left_grid_pin_24_ ( cby_1__1__0_left_grid_pin_24_ ) , - .left_grid_pin_25_ ( cby_1__1__0_left_grid_pin_25_ ) , - .left_grid_pin_26_ ( cby_1__1__0_left_grid_pin_26_ ) , - .left_grid_pin_27_ ( cby_1__1__0_left_grid_pin_27_ ) , - .left_grid_pin_28_ ( cby_1__1__0_left_grid_pin_28_ ) , - .left_grid_pin_29_ ( cby_1__1__0_left_grid_pin_29_ ) , - .left_grid_pin_30_ ( cby_1__1__0_left_grid_pin_30_ ) , - .left_grid_pin_31_ ( cby_1__1__0_left_grid_pin_31_ ) , - .ccff_tail ( cby_1__1__0_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , - .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_16 ) , - .prog_clk__FEEDTHRU_2 ( prog_clk__FEEDTHRU_9 ) ) ; -cby_1__1_ cby_1__2_ ( .prog_clk ( prog_clk__FEEDTHRU_10 ) , - .chany_bottom_in ( sb_1__1__0_chany_top_out ) , - .chany_top_in ( sb_1__2__0_chany_bottom_out ) , - .ccff_head ( grid_clb_1_ccff_tail ) , - .chany_bottom_out ( cby_1__1__1_chany_bottom_out ) , - .chany_top_out ( cby_1__1__1_chany_top_out ) , - .left_grid_pin_16_ ( cby_1__1__1_left_grid_pin_16_ ) , - .left_grid_pin_17_ ( cby_1__1__1_left_grid_pin_17_ ) , - .left_grid_pin_18_ ( cby_1__1__1_left_grid_pin_18_ ) , - .left_grid_pin_19_ ( cby_1__1__1_left_grid_pin_19_ ) , - .left_grid_pin_20_ ( cby_1__1__1_left_grid_pin_20_ ) , - .left_grid_pin_21_ ( cby_1__1__1_left_grid_pin_21_ ) , - .left_grid_pin_22_ ( cby_1__1__1_left_grid_pin_22_ ) , - .left_grid_pin_23_ ( cby_1__1__1_left_grid_pin_23_ ) , - .left_grid_pin_24_ ( cby_1__1__1_left_grid_pin_24_ ) , - .left_grid_pin_25_ ( cby_1__1__1_left_grid_pin_25_ ) , - .left_grid_pin_26_ ( cby_1__1__1_left_grid_pin_26_ ) , - .left_grid_pin_27_ ( cby_1__1__1_left_grid_pin_27_ ) , - .left_grid_pin_28_ ( cby_1__1__1_left_grid_pin_28_ ) , - .left_grid_pin_29_ ( cby_1__1__1_left_grid_pin_29_ ) , - .left_grid_pin_30_ ( cby_1__1__1_left_grid_pin_30_ ) , - .left_grid_pin_31_ ( cby_1__1__1_left_grid_pin_31_ ) , - .ccff_tail ( cby_1__1__1_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , - .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_12 ) , - .prog_clk__FEEDTHRU_2 ( prog_clk__FEEDTHRU_11 ) ) ; -cby_2__1_ cby_2__1_ ( .prog_clk ( prog_clk__FEEDTHRU_19 ) , - .chany_bottom_in ( sb_2__0__0_chany_top_out ) , - .chany_top_in ( sb_2__1__0_chany_bottom_out ) , - .ccff_head ( grid_clb_2_ccff_tail ) , - .chany_bottom_out ( cby_2__1__0_chany_bottom_out ) , - .chany_top_out ( cby_2__1__0_chany_top_out ) , - .right_grid_pin_0_ ( cby_2__1__0_right_grid_pin_0_ ) , - .left_grid_pin_16_ ( cby_2__1__0_left_grid_pin_16_ ) , - .left_grid_pin_17_ ( cby_2__1__0_left_grid_pin_17_ ) , - .left_grid_pin_18_ ( cby_2__1__0_left_grid_pin_18_ ) , - .left_grid_pin_19_ ( cby_2__1__0_left_grid_pin_19_ ) , - .left_grid_pin_20_ ( cby_2__1__0_left_grid_pin_20_ ) , - .left_grid_pin_21_ ( cby_2__1__0_left_grid_pin_21_ ) , - .left_grid_pin_22_ ( cby_2__1__0_left_grid_pin_22_ ) , - .left_grid_pin_23_ ( cby_2__1__0_left_grid_pin_23_ ) , - .left_grid_pin_24_ ( cby_2__1__0_left_grid_pin_24_ ) , - .left_grid_pin_25_ ( cby_2__1__0_left_grid_pin_25_ ) , - .left_grid_pin_26_ ( cby_2__1__0_left_grid_pin_26_ ) , - .left_grid_pin_27_ ( cby_2__1__0_left_grid_pin_27_ ) , - .left_grid_pin_28_ ( cby_2__1__0_left_grid_pin_28_ ) , - .left_grid_pin_29_ ( cby_2__1__0_left_grid_pin_29_ ) , - .left_grid_pin_30_ ( cby_2__1__0_left_grid_pin_30_ ) , - .left_grid_pin_31_ ( cby_2__1__0_left_grid_pin_31_ ) , - .ccff_tail ( grid_io_right_0_ccff_tail ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[2] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[2] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[2] ) , - .left_width_0_height_0__pin_0_ ( cby_2__1__0_right_grid_pin_0_ ) , - .left_width_0_height_0__pin_1_upper ( grid_io_right_0_left_width_0_height_0__pin_1_upper ) , - .left_width_0_height_0__pin_1_lower ( grid_io_right_0_left_width_0_height_0__pin_1_lower ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -cby_2__1_ cby_2__2_ ( - .prog_clk ( { ctsbuf_net_24 } ) , - .chany_bottom_in ( sb_2__1__0_chany_top_out ) , - .chany_top_in ( sb_2__2__0_chany_bottom_out ) , - .ccff_head ( grid_clb_3_ccff_tail ) , - .chany_bottom_out ( cby_2__1__1_chany_bottom_out ) , - .chany_top_out ( cby_2__1__1_chany_top_out ) , - .right_grid_pin_0_ ( cby_2__1__1_right_grid_pin_0_ ) , - .left_grid_pin_16_ ( cby_2__1__1_left_grid_pin_16_ ) , - .left_grid_pin_17_ ( cby_2__1__1_left_grid_pin_17_ ) , - .left_grid_pin_18_ ( cby_2__1__1_left_grid_pin_18_ ) , - .left_grid_pin_19_ ( cby_2__1__1_left_grid_pin_19_ ) , - .left_grid_pin_20_ ( cby_2__1__1_left_grid_pin_20_ ) , - .left_grid_pin_21_ ( cby_2__1__1_left_grid_pin_21_ ) , - .left_grid_pin_22_ ( cby_2__1__1_left_grid_pin_22_ ) , - .left_grid_pin_23_ ( cby_2__1__1_left_grid_pin_23_ ) , - .left_grid_pin_24_ ( cby_2__1__1_left_grid_pin_24_ ) , - .left_grid_pin_25_ ( cby_2__1__1_left_grid_pin_25_ ) , - .left_grid_pin_26_ ( cby_2__1__1_left_grid_pin_26_ ) , - .left_grid_pin_27_ ( cby_2__1__1_left_grid_pin_27_ ) , - .left_grid_pin_28_ ( cby_2__1__1_left_grid_pin_28_ ) , - .left_grid_pin_29_ ( cby_2__1__1_left_grid_pin_29_ ) , - .left_grid_pin_30_ ( cby_2__1__1_left_grid_pin_30_ ) , - .left_grid_pin_31_ ( cby_2__1__1_left_grid_pin_31_ ) , - .ccff_tail ( grid_io_right_1_ccff_tail ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[3] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[3] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[3] ) , - .left_width_0_height_0__pin_0_ ( cby_2__1__1_right_grid_pin_0_ ) , - .left_width_0_height_0__pin_1_upper ( grid_io_right_1_left_width_0_height_0__pin_1_upper ) , - .left_width_0_height_0__pin_1_lower ( grid_io_right_1_left_width_0_height_0__pin_1_lower ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -direct_interc_0 direct_interc_0_ ( - .in ( grid_clb_1_bottom_width_0_height_0__pin_50_ ) , - .out ( direct_interc_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -direct_interc_1 direct_interc_1_ ( - .in ( grid_clb_3_bottom_width_0_height_0__pin_50_ ) , - .out ( direct_interc_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -direct_interc_2 direct_interc_2_ ( - .in ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) , - .out ( direct_interc_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_0 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_2 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_3 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_4 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_5 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_6 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_7 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_8 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_9 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_10 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_11 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_12 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_13 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_14 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_15 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_16 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_17 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_18 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_19 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_20 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_21 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_22 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_23 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_24 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_25 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_26 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_27 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_28 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_29 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_30 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_31 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_32 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_33 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_34 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_35 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_36 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_37 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_38 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_39 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_40 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_41 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_42 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_43 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_44 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_45 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_46 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_47 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_48 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_49 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_50 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_51 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_52 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_53 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_54 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_55 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_56 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_57 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_58 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_59 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_60 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_61 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_62 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_63 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_64 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_65 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_66 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_67 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_68 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_69 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_70 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_71 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_72 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_73 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_74 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_75 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_76 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_77 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_78 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_79 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_80 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_81 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_82 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_83 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_84 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_85 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_86 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_87 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_88 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_89 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_90 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_91 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_92 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_93 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_94 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_95 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_96 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_97 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_98 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_99 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_100 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_101 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_102 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_103 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_104 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_105 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_106 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_107 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_108 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_109 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_110 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_111 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_112 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_113 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_114 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_115 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_116 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_117 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_118 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_119 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_120 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_121 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_122 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_123 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_124 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_125 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_126 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_127 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_128 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_129 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_130 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_131 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_132 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_133 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_134 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_135 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_136 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_137 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_138 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_139 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_140 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_141 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_142 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_143 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_144 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_145 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_146 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_147 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_148 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_149 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_150 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_151 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_152 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_153 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_154 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_155 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_156 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_157 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_158 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_159 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_160 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_161 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_162 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_163 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_164 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_165 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_166 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_167 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_168 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_169 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_170 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_171 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_172 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_173 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_174 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_175 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_176 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_177 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_178 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_179 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_180 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_181 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_182 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_183 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_184 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_185 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_186 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_187 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_188 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_189 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_190 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_191 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_192 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_193 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_194 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_195 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_196 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_197 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_198 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_199 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_200 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_201 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_202 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_203 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_204 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_205 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_206 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_207 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_208 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_209 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_210 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_211 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_212 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_213 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_214 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_215 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_216 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_217 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_218 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_219 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_220 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_221 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_222 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_223 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_224 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_225 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_226 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_227 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_228 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_229 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_230 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_231 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_232 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_233 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_234 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_235 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_236 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_237 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_238 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_239 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_240 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_241 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_242 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_243 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_244 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_245 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_246 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_247 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_248 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_249 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_250 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_251 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_252 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_253 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_254 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_255 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_256 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_257 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_258 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_259 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_260 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_261 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_262 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_263 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_264 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_265 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_266 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_267 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_268 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_269 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_270 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_271 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_272 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_273 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_274 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_275 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_276 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_277 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_278 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_279 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_280 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_281 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_282 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_283 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_284 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_285 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_286 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_287 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_288 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_289 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_290 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_291 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_292 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_293 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_294 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_295 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_296 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_297 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_298 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_299 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_300 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_301 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_302 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_303 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_304 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_305 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_306 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_307 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_308 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_309 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_310 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_311 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_312 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_313 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_314 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_315 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_316 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_317 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_318 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_319 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_320 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_321 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_322 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_323 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_324 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_325 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_326 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_327 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_328 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_329 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_330 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_331 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_332 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_333 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_334 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_335 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_336 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_337 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_338 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_339 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_340 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_341 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_342 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_343 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_344 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_345 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_346 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_347 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_348 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_349 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_350 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_351 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_352 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_353 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_354 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_355 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_356 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_357 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_358 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_359 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_360 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_361 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_362 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_363 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_364 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_365 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_366 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_367 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_368 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_369 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_370 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_371 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_372 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_373 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_374 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_375 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_376 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_377 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_378 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_379 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_380 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_381 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_382 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_383 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_384 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_385 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_386 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_387 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_388 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_389 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_390 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_391 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_392 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_393 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_394 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_395 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_396 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_397 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_398 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_399 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_400 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_401 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_402 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_403 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_404 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_405 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_406 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_407 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_408 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_409 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_410 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_411 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_412 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_413 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_414 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_415 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_416 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_417 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_418 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_419 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_420 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_421 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_422 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_423 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_424 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_425 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_426 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_427 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_428 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_429 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_430 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_431 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_432 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_433 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_434 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_435 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_436 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_437 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_438 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_439 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_440 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_441 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_442 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_443 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_444 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_445 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_446 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_447 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_448 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_449 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_450 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_451 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_452 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_453 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_454 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_455 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_456 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_457 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_458 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_459 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_460 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_461 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_462 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_463 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_464 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_465 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_466 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_467 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_468 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_469 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_470 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_471 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_472 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_473 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_474 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_475 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_476 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_477 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_478 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_479 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_480 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_481 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_482 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_483 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_484 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_485 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_486 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_487 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_488 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_489 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_490 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_491 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_492 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_493 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_494 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_495 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_496 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_497 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_498 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_499 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_500 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_501 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_502 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_503 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_504 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_505 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_506 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_507 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_508 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_509 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_510 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_511 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_512 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_513 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_514 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_515 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_516 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_517 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_518 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_519 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_520 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_521 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_522 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_523 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_524 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_525 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_526 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_527 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_528 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_529 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_530 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_531 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_532 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_533 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_534 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_535 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_536 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_537 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_538 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_539 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_540 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_541 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_542 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_543 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_544 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_545 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_546 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_547 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_548 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_549 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_550 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_551 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_552 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_553 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_554 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_555 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_556 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_557 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_558 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_559 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_560 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_561 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_562 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_563 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_564 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_565 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_566 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_567 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_568 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_569 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_570 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_571 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_572 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_573 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_574 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_575 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_576 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_577 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_578 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_579 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_580 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_581 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_582 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_583 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_584 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_585 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_586 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_587 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_588 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_589 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_590 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_591 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_592 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_593 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_594 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_595 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_596 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_597 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_598 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_599 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_600 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_601 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_602 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_603 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_604 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_605 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_606 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_607 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_608 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_609 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_610 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_611 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_612 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_613 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_614 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_615 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_616 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_617 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_618 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_619 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_620 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_621 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_622 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_623 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_624 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_625 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_626 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_627 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_628 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_629 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_630 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_631 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_632 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_633 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_634 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_635 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_636 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_637 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_638 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_639 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_640 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_641 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_642 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_643 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_644 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_645 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_646 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_647 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_648 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_649 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_650 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_651 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_652 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_653 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_654 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_655 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_656 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_657 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_658 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_659 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_660 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_661 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_662 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_663 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_664 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_665 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_666 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_667 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_668 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_669 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_670 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_671 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_672 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_673 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_674 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_675 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_676 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_677 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_678 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_679 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_680 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_681 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_682 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_683 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_684 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_685 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_686 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_687 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_688 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_689 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_690 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_691 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_692 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_693 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_694 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_695 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_696 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_697 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_698 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_699 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_700 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_701 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_702 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_703 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_704 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_705 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_706 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_707 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_708 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_709 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_710 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_711 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_712 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_713 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_714 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_715 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_716 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_717 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_718 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_719 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_720 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_721 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_722 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_723 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_724 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_725 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_726 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_727 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_728 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_729 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_730 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_731 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_732 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_733 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_734 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_735 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_736 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_737 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_738 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_739 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_740 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_741 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_742 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_743 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_744 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_745 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_746 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_747 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_748 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_749 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_750 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_751 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_752 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_753 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_754 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_755 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_756 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_757 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_758 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_759 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_760 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_761 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_762 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_763 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_764 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_765 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_766 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_767 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_768 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_769 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_770 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_771 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_772 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_773 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_774 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_775 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_776 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_777 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_778 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_779 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_780 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_781 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_782 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_783 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_784 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_785 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_786 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_787 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_788 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_789 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_790 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_791 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_792 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_793 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_794 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_795 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_796 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_797 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_798 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_799 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_800 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_801 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_802 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_803 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_804 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_805 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_806 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_807 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_808 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_809 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_810 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_811 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_812 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_813 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_814 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_815 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_816 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_817 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_818 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_819 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_820 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_821 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_822 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_823 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_824 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_825 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_826 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_827 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_828 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_829 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_830 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_831 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_832 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_833 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_834 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_835 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_836 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_837 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_838 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_839 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_840 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_841 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_842 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_843 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_844 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_845 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_846 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_847 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_848 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_849 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_850 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_851 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_852 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_853 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_854 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_855 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_856 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_857 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_858 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_859 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_860 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_861 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_862 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_863 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_864 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_865 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_866 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_867 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_868 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_869 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_870 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_871 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_872 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_873 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_874 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_875 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_876 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_877 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_878 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_879 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_880 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_881 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_882 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_883 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_884 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_885 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_886 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_887 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_888 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_889 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_890 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_891 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_892 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_893 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_894 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_895 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_896 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_897 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_898 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_899 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_900 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_901 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_902 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_903 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_904 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_905 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_906 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_907 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_908 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_909 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_910 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_911 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_912 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_913 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_914 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_915 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_916 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_917 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_918 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_919 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_920 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_921 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_922 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_923 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_924 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_925 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_926 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_927 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_928 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_929 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_930 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_931 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_932 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_933 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_934 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_935 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_936 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_937 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_938 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_939 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_940 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_941 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_942 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_943 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_944 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_945 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_946 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_947 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_948 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_949 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_950 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_951 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_952 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_953 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_954 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_955 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_956 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_957 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_958 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_959 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_960 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_961 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_962 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_963 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_964 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_965 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_966 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_967 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_968 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_969 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_970 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_971 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_972 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_973 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_974 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_975 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_976 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_977 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_978 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_979 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_980 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_981 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_982 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_983 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_984 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_985 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_986 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_987 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_988 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_989 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_990 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_991 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_992 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_993 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_994 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_995 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_996 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_997 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_998 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_999 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1000 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1001 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1002 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1003 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1004 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1005 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1006 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1007 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1008 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1009 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1010 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1011 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1012 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1013 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1014 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1015 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1016 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1017 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1018 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1019 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1020 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1021 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1022 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1023 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1024 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1025 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1026 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1027 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1028 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1029 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1030 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1031 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1032 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1033 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1034 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1035 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1036 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1037 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1038 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1039 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1040 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1041 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1042 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1043 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1044 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1045 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1046 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1047 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1048 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1049 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1050 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1051 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1052 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1053 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1054 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1055 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1056 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1057 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1058 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1059 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1060 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1061 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1062 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1063 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1064 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1065 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1066 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1067 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1068 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1069 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1070 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1071 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1072 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1073 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1074 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1075 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1076 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1077 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1078 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1079 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1080 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1081 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1082 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1083 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1084 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1085 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1086 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1087 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1088 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1089 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1090 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1091 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1092 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1093 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1094 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1095 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1096 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1097 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1098 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1099 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1100 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1101 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1102 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1103 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1104 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1105 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1106 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1107 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1108 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1109 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1110 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1111 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1112 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1113 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1114 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1115 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1116 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1117 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1118 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1119 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1120 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1121 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1122 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1123 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1124 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1125 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1126 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1127 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1128 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1129 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1130 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1131 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1132 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1133 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1134 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1135 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1136 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1137 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1138 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1139 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1140 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1141 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1142 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1143 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1144 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1145 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1146 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1147 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1148 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1149 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1150 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1151 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1152 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1153 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1154 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1155 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1156 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1157 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1158 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1159 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1160 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1161 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1162 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1163 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1164 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1165 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1166 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1167 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1168 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1169 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1170 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1171 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1172 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1173 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1174 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1175 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1176 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1177 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1178 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1179 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1180 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1181 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1182 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1183 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1184 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1185 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1186 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__clkinv_2 cts_inv_80028275 ( .A ( ctsbuf_net_46 ) , - .Y ( ctsbuf_net_24 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 cts_inv_80108283 ( .A ( prog_clk__FEEDTHRU_15[0] ) , - .Y ( ctsbuf_net_46 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__inv_6 cts_inv_80408313 ( .A ( ctsbuf_net_1214 ) , - .Y ( ctsbuf_net_1113 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 cts_inv_80448317 ( .A ( prog_clk__FEEDTHRU_5[0] ) , - .Y ( ctsbuf_net_1214 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__clkinv_16 cts_inv_80538326 ( .A ( ctsbuf_net_1416 ) , - .Y ( ctsbuf_net_1315 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_2 cts_inv_80578330 ( .A ( prog_clk__FEEDTHRU_12[0] ) , - .Y ( ctsbuf_net_1416 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__clkinv_2 cts_inv_80898362 ( .A ( ctsbuf_net_1820 ) , - .Y ( ctsbuf_net_1719 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 cts_inv_80938366 ( .A ( prog_clk__FEEDTHRU_2[0] ) , - .Y ( ctsbuf_net_1820 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__clkinv_16 cts_inv_80978370 ( .A ( ctsbuf_net_2022 ) , - .Y ( ctsbuf_net_1921 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_2 cts_inv_81018374 ( .A ( prog_clk__FEEDTHRU_2[0] ) , - .Y ( ctsbuf_net_2022 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__clkinv_16 cts_inv_81108383 ( .A ( ctsbuf_net_2224 ) , - .Y ( ctsbuf_net_2123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_2 cts_inv_81148387 ( .A ( prog_clk__FEEDTHRU_9[0] ) , - .Y ( ctsbuf_net_2224 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__clkinv_8 cts_inv_81198392 ( .A ( ctsbuf_net_2527 ) , - .Y ( ctsbuf_net_2325 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_4 cts_inv_81238396 ( .A ( ctsbuf_net_2628 ) , - .Y ( ctsbuf_net_2426 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_2 cts_inv_81278400 ( .A ( prog_clk__FEEDTHRU_8[0] ) , - .Y ( ctsbuf_net_2527 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 cts_inv_81318404 ( .A ( prog_clk__FEEDTHRU_1[0] ) , - .Y ( ctsbuf_net_2628 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_4 cts_inv_81368409 ( .A ( ctsbuf_net_2830 ) , - .Y ( ctsbuf_net_2729 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_81408413 ( .A ( prog_clk[0] ) , - .Y ( ctsbuf_net_2830 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y0 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1347800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1366200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2341400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2359800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3371800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3404000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3440800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3477600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3514400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3551200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3588000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3624800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3661600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3698400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3735200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3772000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3808800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3845600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3882400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3919200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3956000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3992800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4103200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4140000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4176800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4213600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4250400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4287200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4324000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4342400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4351600y0 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y0 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2341400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2359800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4328600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1361600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1370800y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2341400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2359800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4328600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1361600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1370800y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3408600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2341400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2359800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4328600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1361600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1370800y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2341400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2359800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4328600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1361600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1370800y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2341400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2359800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4328600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1361600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1370800y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2341400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2359800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4328600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1361600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1370800y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2341400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2359800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4328600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1361600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1370800y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2341400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2359800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4328600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1361600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1370800y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2341400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2359800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4328600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1361600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1370800y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2341400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2359800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4328600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1361600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1370800y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2341400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2359800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4328600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1361600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1370800y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2341400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2359800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4328600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1361600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1370800y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2341400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2359800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4328600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1361600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1370800y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2341400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2359800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4328600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1361600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1370800y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2341400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2359800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4328600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1361600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1370800y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2341400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2359800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4328600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1361600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1370800y870400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2856600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2879600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2916400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2953200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2990000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3026800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3063600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3100400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3137200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3174000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3210800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3247600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3284400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3321200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3358000y870400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y870400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y897600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1347800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1366200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2341400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2359800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2856600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2888800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2925600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2962400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2999200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3036000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3072800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3109600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3146400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3183200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3220000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3256800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3293600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3330400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3348800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3358000y897600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4328600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y897600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y924800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y924800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y924800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y924800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y952000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y952000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y952000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y952000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y979200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y979200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y979200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y979200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y1006400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y1006400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y1006400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1006400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y1033600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y1033600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y1033600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1033600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y1060800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y1060800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y1060800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1060800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y1088000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y1088000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y1088000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1088000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y1115200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y1115200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y1115200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1115200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y1142400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y1142400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y1142400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1142400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y1169600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y1169600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y1169600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1169600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y1196800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y1196800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y1196800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1196800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y1224000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y1224000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y1224000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1224000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y1251200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y1251200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y1251200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1251200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y1278400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y1278400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y1278400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1278400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y1305600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y1305600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y1305600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1305600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y1332800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y1332800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y1332800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1332800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y1360000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y1360000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y1360000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1360000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y1387200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y1387200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y1387200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1387200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y1414400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y1414400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y1414400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1414400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y1441600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y1441600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y1441600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1441600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y1468800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y1468800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y1468800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1468800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y1496000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y1496000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y1496000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1496000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y1523200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y1523200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y1523200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1523200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y1550400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y1550400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y1550400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1550400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y1577600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y1577600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y1577600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1577600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y1604800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y1604800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y1604800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1604800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y1632000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y1632000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y1632000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1632000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y1659200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y1659200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y1659200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1659200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y1686400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y1686400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y1686400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1686400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y1713600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y1713600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y1713600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1713600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y1740800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y1740800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y1740800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1740800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y1768000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y1768000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y1768000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1768000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y1795200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y1795200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1757200y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1867600y1795200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2042400y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2079200y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2116000y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2152800y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2162000y1795200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2180400y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2217200y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2254000y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2290800y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2327600y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2364400y1795200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2856600y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3059000y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3077400y1795200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3818000y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3854800y1795200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4843800y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5046200y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5064600y1795200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y1795200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1795200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y1822400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y1822400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1757200y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1867600y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1904400y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1941200y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2143600y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2162000y1822400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2185000y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2221800y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2258600y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2295400y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2332200y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3077400y1822400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3818000y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3854800y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3891600y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3928400y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3965200y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4075600y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4112400y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4149200y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4186000y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4222800y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4259600y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4296400y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4333200y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4351600y1822400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5064600y1822400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y1822400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1822400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y1849600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y1849600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1803200y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1821600y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5041600y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5060000y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y1849600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1849600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y1876800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y1876800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1803200y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1821600y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5041600y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5060000y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y1876800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1876800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1361600y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1370800y1904000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1826200y1904000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3082000y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3118800y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3155600y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3192400y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3229200y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3266000y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3302800y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3339600y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3358000y1904000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3371800y1904000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3436200y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3473000y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3509800y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3546600y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3583400y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3620200y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3657000y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3693800y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3730600y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3767400y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3804200y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3813400y1904000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5106000y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5142800y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5179600y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5216400y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5253200y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5290000y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5326800y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5345200y1904000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1904000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y1931200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1347800y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1366200y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1826200y1931200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3082000y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3118800y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3155600y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3192400y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3229200y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3266000y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3302800y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3339600y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3358000y1931200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3371800y1931200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3795000y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3813400y1931200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5106000y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5142800y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5179600y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5216400y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5253200y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5290000y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5326800y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5345200y1931200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1931200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1931200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y1958400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y1958400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1803200y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1821600y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5041600y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5060000y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y1958400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1958400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y1985600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y1985600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1757200y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y1985600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1985600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y2012800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y2012800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1803200y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1821600y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5041600y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5060000y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y2012800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2012800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y2040000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y2040000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1757200y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y2040000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2040000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y2067200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y2067200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1803200y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1821600y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5041600y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5060000y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y2067200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2067200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y2094400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y2094400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1757200y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y2094400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2094400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y2121600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y2121600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1803200y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1821600y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5041600y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5060000y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y2121600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2121600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y2148800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y2148800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1757200y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y2148800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2148800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y2176000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y2176000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1803200y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1821600y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5041600y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5060000y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y2176000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2176000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y2203200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y2203200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1757200y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y2203200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2203200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y2230400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y2230400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1803200y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1821600y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5041600y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5060000y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y2230400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2230400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y2257600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y2257600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1757200y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y2257600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2257600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y2284800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y2284800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1803200y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1821600y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5041600y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5060000y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y2284800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2284800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y2312000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y2312000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1757200y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y2312000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2312000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y2339200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y2339200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1803200y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1821600y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5041600y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5060000y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y2339200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2339200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y2366400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y2366400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1757200y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y2366400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2366400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y2393600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y2393600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1803200y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1821600y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5041600y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5060000y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y2393600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2393600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y2420800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y2420800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1757200y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y2420800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2420800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y2448000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y2448000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1803200y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1821600y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5041600y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5060000y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y2448000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2448000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y2475200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y2475200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1757200y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y2475200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2475200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y2502400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y2502400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1803200y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1821600y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5041600y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5060000y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y2502400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2502400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y2529600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y2529600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1757200y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y2529600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2529600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y2556800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y2556800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1803200y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1821600y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5041600y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5060000y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y2556800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2556800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y2584000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y2584000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1757200y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y2584000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2584000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y2611200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y2611200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1803200y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1821600y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5041600y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5060000y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y2611200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2611200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y2638400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y2638400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1757200y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y2638400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2638400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y2665600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y2665600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1803200y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1821600y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5041600y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5060000y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y2665600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2665600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y2692800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y2692800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1803200y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1821600y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5041600y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5060000y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y2692800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2692800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1361600y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1370800y2720000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1826200y2720000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3082000y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3118800y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3155600y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3192400y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3229200y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3247600y2720000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3813400y2720000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5106000y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5142800y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5179600y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5216400y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5253200y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5290000y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5326800y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5345200y2720000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2720000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y2747200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1347800y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1366200y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1826200y2747200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3082000y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3118800y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3155600y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3192400y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3229200y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3247600y2747200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3266000y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3302800y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3339600y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3358000y2747200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3813400y2747200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5106000y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5142800y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5179600y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5216400y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5253200y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5290000y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5326800y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5345200y2747200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2747200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2747200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y2774400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y2774400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1803200y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1821600y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5041600y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5060000y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y2774400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2774400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y2801600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y2801600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1803200y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1821600y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5041600y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5060000y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y2801600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2801600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y2828800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y2828800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1757200y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1867600y2828800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2359800y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2856600y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3059000y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3077400y2828800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3818000y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3854800y2828800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4843800y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5046200y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5064600y2828800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y2828800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2828800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y2856000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y2856000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1757200y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1867600y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1904400y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1941200y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2088400y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2125200y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2162000y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2198800y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2235600y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2272400y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2309200y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2346000y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2364400y2856000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3077400y2856000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3818000y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3854800y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3891600y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3928400y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3965200y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4075600y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4112400y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4149200y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4186000y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4222800y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4259600y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4296400y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4333200y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4351600y2856000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5064600y2856000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y2856000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2856000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y2883200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y2883200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y2883200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2883200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y2910400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y2910400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y2910400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2910400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y2937600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y2937600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y2937600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2937600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y2964800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y2964800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y2964800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2964800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y2992000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y2992000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y2992000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2992000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y3019200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y3019200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y3019200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3019200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y3046400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y3046400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y3046400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3046400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y3073600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y3073600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y3073600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3073600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y3100800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y3100800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y3100800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3100800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y3128000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y3128000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y3128000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3128000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y3155200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y3155200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y3155200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3155200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y3182400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y3182400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y3182400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3182400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y3209600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y3209600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y3209600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3209600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y3236800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y3236800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y3236800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3236800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y3264000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y3264000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y3264000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3264000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y3291200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y3291200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y3291200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3291200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y3318400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y3318400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y3318400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3318400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y3345600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y3345600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y3345600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3345600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y3372800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y3372800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y3372800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3372800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y3400000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y3400000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y3400000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3400000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y3427200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y3427200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y3427200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3427200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y3454400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y3454400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y3454400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3454400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y3481600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y3481600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y3481600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3481600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y3508800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y3508800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y3508800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3508800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y3536000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y3536000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y3536000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3536000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y3563200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y3563200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y3563200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3563200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y3590400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y3590400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y3590400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3590400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y3617600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y3617600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y3617600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3617600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y3644800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y3644800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y3644800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3644800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y3672000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y3672000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y3672000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3672000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y3699200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y3699200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y3699200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3699200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y3726400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y3726400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y3726400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3726400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y3753600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y3753600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1757200y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1867600y3753600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2042400y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2079200y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2116000y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2152800y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2189600y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2226400y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2263200y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2300000y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2336800y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2355200y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2364400y3753600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2856600y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3059000y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3077400y3753600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3781200y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3799600y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3808800y3753600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3850200y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4843800y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5046200y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5064600y3753600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y3753600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3753600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y3780800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y3780800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1757200y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1867600y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1904400y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1941200y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1978000y3780800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2088400y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2125200y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2162000y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2198800y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2235600y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2272400y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2309200y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2346000y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2364400y3780800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3077400y3780800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3818000y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3836400y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3956000y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3992800y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4002000y3780800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4043400y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4080200y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4117000y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4153800y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4190600y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4227400y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4264200y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4301000y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4337800y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5064600y3780800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y3780800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3780800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y3808000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y3808000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1803200y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1821600y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5041600y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5060000y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y3808000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3808000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y3835200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y3835200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1803200y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1821600y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5041600y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5060000y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y3835200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3835200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1361600y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1370800y3862400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1826200y3862400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3082000y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3118800y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3155600y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3192400y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3229200y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3266000y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3302800y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3339600y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3358000y3862400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3813400y3862400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5106000y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5142800y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5179600y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5216400y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5253200y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5290000y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5326800y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5345200y3862400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3862400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y3889600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1347800y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1366200y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1826200y3889600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3082000y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3118800y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3155600y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3192400y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3229200y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3266000y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3302800y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3339600y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3358000y3889600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3703000y3889600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3795000y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3813400y3889600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5106000y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5142800y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5179600y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5216400y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5253200y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5290000y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5326800y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5345200y3889600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3889600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3889600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y3916800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y3916800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1803200y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1821600y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5023200y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5060000y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y3916800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3916800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y3944000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y3944000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1757200y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5046200y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5064600y3944000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y3944000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3944000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y3971200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y3971200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1803200y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1821600y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5041600y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5060000y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y3971200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3971200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y3998400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y3998400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1757200y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y3998400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3998400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y4025600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y4025600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1803200y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1821600y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5041600y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5060000y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y4025600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4025600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y4052800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y4052800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1757200y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y4052800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4052800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y4080000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y4080000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1803200y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1821600y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5041600y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5060000y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y4080000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4080000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y4107200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y4107200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1757200y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y4107200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4107200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y4134400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y4134400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1803200y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1821600y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5041600y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5060000y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y4134400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4134400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y4161600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y4161600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1757200y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y4161600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4161600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y4188800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y4188800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1803200y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1821600y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5041600y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5060000y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y4188800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4188800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y4216000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y4216000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1757200y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y4216000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4216000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y4243200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y4243200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1803200y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1821600y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5041600y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5060000y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y4243200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4243200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y4270400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y4270400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1757200y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y4270400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4270400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y4297600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y4297600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1803200y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1821600y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5041600y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5060000y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y4297600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4297600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y4324800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y4324800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1757200y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y4324800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4324800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y4352000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y4352000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1803200y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1821600y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5041600y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5060000y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y4352000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4352000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y4379200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y4379200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1757200y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y4379200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4379200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y4406400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y4406400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1803200y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1821600y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5041600y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5060000y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y4406400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4406400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y4433600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y4433600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1757200y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y4433600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4433600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y4460800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y4460800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1803200y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1821600y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5041600y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5060000y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y4460800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4460800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y4488000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y4488000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1757200y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y4488000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4488000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y4515200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y4515200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1803200y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1821600y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5041600y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5060000y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y4515200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4515200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y4542400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y4542400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1757200y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y4542400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4542400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y4569600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y4569600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1803200y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1821600y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5041600y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5060000y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y4569600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4569600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y4596800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y4596800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1757200y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y4596800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4596800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y4624000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y4624000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1803200y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1821600y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5041600y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5060000y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y4624000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4624000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y4651200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y4651200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1803200y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1821600y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5041600y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5060000y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y4651200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4651200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1361600y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1370800y4678400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1826200y4678400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3082000y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3118800y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3155600y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3192400y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3229200y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3266000y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3302800y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3339600y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3358000y4678400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3813400y4678400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5106000y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5142800y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5179600y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5216400y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5253200y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5290000y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5326800y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5345200y4678400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4678400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y4705600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1347800y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1366200y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1826200y4705600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3082000y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3118800y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3155600y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3192400y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3229200y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3266000y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3302800y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3339600y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3358000y4705600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3813400y4705600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5106000y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5142800y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5179600y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5216400y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5253200y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5290000y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5326800y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5345200y4705600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4705600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4705600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y4732800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y4732800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1803200y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1821600y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5041600y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5060000y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y4732800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4732800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y4760000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y4760000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1803200y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1821600y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5004800y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5041600y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5060000y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y4760000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4760000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y4787200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y4787200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1757200y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1867600y4787200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2359800y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2856600y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3059000y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3077400y4787200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3818000y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3854800y4787200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4310200y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4843800y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5046200y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5064600y4787200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y4787200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4787200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y4814400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y4814400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1757200y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1867600y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1904400y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1941200y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2088400y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2125200y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2162000y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2198800y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2235600y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2272400y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2309200y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2346000y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2364400y4814400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3077400y4814400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3818000y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3854800y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3891600y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3928400y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3965200y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4075600y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4112400y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4149200y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4186000y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4222800y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4259600y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4296400y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4333200y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4351600y4814400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5064600y4814400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y4814400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4814400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y4841600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y4841600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y4841600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4841600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y4868800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y4868800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y4868800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4868800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y4896000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y4896000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y4896000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4896000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y4923200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y4923200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y4923200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4923200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y4950400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y4950400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y4950400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4950400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y4977600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y4977600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y4977600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4977600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y5004800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y5004800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y5004800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5004800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y5032000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y5032000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y5032000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5032000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y5059200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y5059200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y5059200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5059200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y5086400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y5086400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y5086400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5086400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y5113600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y5113600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y5113600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5113600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y5140800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y5140800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y5140800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5140800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y5168000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y5168000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y5168000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5168000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y5195200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y5195200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y5195200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5195200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y5222400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y5222400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y5222400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5222400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y5249600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y5249600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y5249600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5249600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y5276800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y5276800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y5276800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5276800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y5304000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y5304000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y5304000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5304000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y5331200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y5331200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y5331200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5331200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y5358400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y5358400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y5358400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5358400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y5385600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y5385600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y5385600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5385600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y5412800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y5412800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y5412800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5412800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y5440000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y5440000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y5440000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5440000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y5467200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y5467200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y5467200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5467200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y5494400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y5494400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y5494400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5494400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y5521600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y5521600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y5521600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5521600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y5548800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y5548800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y5548800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5548800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y5576000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y5576000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y5576000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5576000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y5603200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y5603200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y5603200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5603200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y5630400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y5630400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2787600y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6283600y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6320400y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6338800y5630400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5630400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y5657600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y5657600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y5657600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6812600y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5657600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y5684800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y5684800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2024000y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2060800y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2079200y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2796800y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2815200y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4048000y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4066400y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4784000y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4802400y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5842000y5684800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6260600y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5684800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1361600y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1370800y5712000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2341400y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2359800y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4328600y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5712000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y5739200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2341400y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2359800y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4328600y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5739200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1361600y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1370800y5766400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5766400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y5793600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2341400y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2359800y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4328600y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5793600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1361600y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1370800y5820800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5820800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y5848000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2341400y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2359800y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4328600y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5848000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1361600y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1370800y5875200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5875200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y5902400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2341400y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2359800y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4328600y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5902400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1361600y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1370800y5929600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5929600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y5956800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2341400y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2359800y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4328600y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5956800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1361600y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1370800y5984000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5984000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y6011200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2341400y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2359800y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4328600y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y6011200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1361600y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1370800y6038400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y6038400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y6065600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2341400y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2359800y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4328600y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y6065600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1361600y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1370800y6092800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y6092800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y6120000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2341400y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2359800y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4328600y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y6120000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1361600y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1370800y6147200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y6147200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y6174400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2341400y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2359800y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4328600y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y6174400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1361600y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1370800y6201600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y6201600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y6228800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2341400y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2359800y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4328600y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y6228800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1361600y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1370800y6256000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y6256000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y6283200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2341400y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2359800y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4328600y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y6283200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1361600y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1370800y6310400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y6310400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y6337600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2341400y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2359800y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4328600y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y6337600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1361600y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1370800y6364800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y6364800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y6392000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2341400y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2359800y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4328600y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y6392000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1361600y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1370800y6419200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y6419200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y6446400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2341400y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2359800y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4328600y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y6446400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1361600y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1370800y6473600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y6473600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y6500800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2341400y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2359800y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4328600y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y6500800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1361600y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1370800y6528000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y6528000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y6555200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2341400y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2359800y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4328600y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y6555200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1361600y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1370800y6582400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y6582400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y6609600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2341400y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2359800y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4328600y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y6609600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1361600y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1370800y6636800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y6636800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y6664000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2341400y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2359800y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4328600y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y6664000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1361600y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1370800y6691200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y6691200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y6718400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2341400y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2359800y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4328600y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y6718400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1361600y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1370800y6745600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y6745600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y6772800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2341400y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2359800y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4328600y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y6772800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1361600y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1370800y6800000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y6800000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y6827200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2341400y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2359800y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4328600y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y6827200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1361600y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1370800y6854400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y6854400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y6881600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2341400y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2359800y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4328600y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y6881600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1361600y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1370800y6908800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y6908800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y6936000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1347800y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1366200y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2341400y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2359800y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4328600y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4347000y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5322200y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5340600y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6315800y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6334200y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6831000y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y6936000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - diff --git a/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.nominal_25.spef.gz b/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.nominal_25.spef.gz deleted file mode 100644 index aa36d43..0000000 Binary files a/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.nominal_25.spef.gz and /dev/null differ diff --git a/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v b/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v deleted file mode 100644 index ea250cb..0000000 --- a/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v +++ /dev/null @@ -1,33549 +0,0 @@ -// -// -// -// -// -// -module direct_interc_2 ( in , out ) ; -input [0:0] in ; -output [0:0] out ; - -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__2 ( .A ( in[0] ) , .X ( out[0] ) ) ; -endmodule - - -module direct_interc_1 ( in , out ) ; -input [0:0] in ; -output [0:0] out ; - -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__1 ( .A ( in[0] ) , .X ( out[0] ) ) ; -endmodule - - -module direct_interc_0 ( in , out ) ; -input [0:0] in ; -output [0:0] out ; - -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__0 ( .A ( in[0] ) , .X ( out[0] ) ) ; -endmodule - - -module cby_2__1__direct_interc ( in , out ) ; -input [0:0] in ; -output [0:0] out ; - -assign out[0] = in[0] ; -endmodule - - -module cby_2__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( prog_clk , - ccff_head , ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:0] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_20__60 ( .A ( mem_out[0] ) , - .X ( net_net_80 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_80 ( .A ( net_net_80 ) , - .X ( net_net_79 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_101 ( .A ( net_net_79 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_2__1__EMBEDDED_IO ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , - FPGA_OUT , FPGA_DIR , p_abuf0 ) ; -input SOC_IN ; -output SOC_OUT ; -output SOC_DIR ; -output FPGA_IN ; -input FPGA_OUT ; -input FPGA_DIR ; -output p_abuf0 ; - -assign SOC_OUT = FPGA_OUT ; - -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__58 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 FTB_19__59 ( .A ( FPGA_DIR ) , - .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_62 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; -endmodule - - -module cby_2__1__logical_tile_io_mode_physical__iopad ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] iopad_outpad ; -input [0:0] ccff_head ; -output [0:0] iopad_inpad ; -output [0:0] ccff_tail ; -output p_abuf0 ; - -wire [0:0] EMBEDDED_IO_0_en ; - -cby_2__1__EMBEDDED_IO EMBEDDED_IO_0_ ( - .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , - .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , - .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , - .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; -cby_2__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) ) ; -endmodule - - -module cby_2__1__logical_tile_io_mode_io_ ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , - ccff_tail , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] io_outpad ; -input [0:0] ccff_head ; -output [0:0] io_inpad ; -output [0:0] ccff_tail ; -output p_abuf0 ; - -cby_2__1__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , - .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , - .p_abuf0 ( p_abuf0 ) ) ; -cby_2__1__direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( io_outpad ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__57 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__56 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__55 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__54 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__53 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__52 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__51 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__50 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_4 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__49 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__48 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__47 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__46 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__45 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__44 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__43 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__42 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__41 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cby_2__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , - chany_bottom_out , chany_top_out , right_grid_pin_0_ , left_grid_pin_16_ , - left_grid_pin_17_ , left_grid_pin_18_ , left_grid_pin_19_ , - left_grid_pin_20_ , left_grid_pin_21_ , left_grid_pin_22_ , - left_grid_pin_23_ , left_grid_pin_24_ , left_grid_pin_25_ , - left_grid_pin_26_ , left_grid_pin_27_ , left_grid_pin_28_ , - left_grid_pin_29_ , left_grid_pin_30_ , left_grid_pin_31_ , ccff_tail , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , left_width_0_height_0__pin_0_ , - left_width_0_height_0__pin_1_upper , left_width_0_height_0__pin_1_lower ) ; -input [0:0] prog_clk ; -input [0:19] chany_bottom_in ; -input [0:19] chany_top_in ; -input [0:0] ccff_head ; -output [0:19] chany_bottom_out ; -output [0:19] chany_top_out ; -output [0:0] right_grid_pin_0_ ; -output [0:0] left_grid_pin_16_ ; -output [0:0] left_grid_pin_17_ ; -output [0:0] left_grid_pin_18_ ; -output [0:0] left_grid_pin_19_ ; -output [0:0] left_grid_pin_20_ ; -output [0:0] left_grid_pin_21_ ; -output [0:0] left_grid_pin_22_ ; -output [0:0] left_grid_pin_23_ ; -output [0:0] left_grid_pin_24_ ; -output [0:0] left_grid_pin_25_ ; -output [0:0] left_grid_pin_26_ ; -output [0:0] left_grid_pin_27_ ; -output [0:0] left_grid_pin_28_ ; -output [0:0] left_grid_pin_29_ ; -output [0:0] left_grid_pin_30_ ; -output [0:0] left_grid_pin_31_ ; -output [0:0] ccff_tail ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] left_width_0_height_0__pin_0_ ; -output [0:0] left_width_0_height_0__pin_1_upper ; -output [0:0] left_width_0_height_0__pin_1_lower ; - -wire ropt_net_114 ; -wire [0:3] mux_left_ipin_0_undriven_sram_inv ; -wire [0:3] mux_right_ipin_0_undriven_sram_inv ; -wire [0:3] mux_right_ipin_10_undriven_sram_inv ; -wire [0:3] mux_right_ipin_11_undriven_sram_inv ; -wire [0:3] mux_right_ipin_12_undriven_sram_inv ; -wire [0:3] mux_right_ipin_13_undriven_sram_inv ; -wire [0:3] mux_right_ipin_14_undriven_sram_inv ; -wire [0:3] mux_right_ipin_15_undriven_sram_inv ; -wire [0:3] mux_right_ipin_1_undriven_sram_inv ; -wire [0:3] mux_right_ipin_2_undriven_sram_inv ; -wire [0:3] mux_right_ipin_3_undriven_sram_inv ; -wire [0:3] mux_right_ipin_4_undriven_sram_inv ; -wire [0:3] mux_right_ipin_5_undriven_sram_inv ; -wire [0:3] mux_right_ipin_6_undriven_sram_inv ; -wire [0:3] mux_right_ipin_7_undriven_sram_inv ; -wire [0:3] mux_right_ipin_8_undriven_sram_inv ; -wire [0:3] mux_right_ipin_9_undriven_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:3] mux_tree_tapbuf_size10_2_sram ; -wire [0:3] mux_tree_tapbuf_size10_3_sram ; -wire [0:3] mux_tree_tapbuf_size10_4_sram ; -wire [0:3] mux_tree_tapbuf_size10_5_sram ; -wire [0:3] mux_tree_tapbuf_size10_6_sram ; -wire [0:3] mux_tree_tapbuf_size10_7_sram ; -wire [0:3] mux_tree_tapbuf_size10_8_sram ; -wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:3] mux_tree_tapbuf_size8_2_sram ; -wire [0:3] mux_tree_tapbuf_size8_3_sram ; -wire [0:3] mux_tree_tapbuf_size8_4_sram ; -wire [0:3] mux_tree_tapbuf_size8_5_sram ; -wire [0:3] mux_tree_tapbuf_size8_6_sram ; -wire [0:3] mux_tree_tapbuf_size8_7_sram ; -wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ; - -cby_2__1__mux_tree_tapbuf_size10_0 mux_left_ipin_0 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , - chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , - chany_top_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_left_ipin_0_undriven_sram_inv ) , - .out ( right_grid_pin_0_ ) , .p0 ( optlc_net_111 ) ) ; -cby_2__1__mux_tree_tapbuf_size10_1 mux_right_ipin_0 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , - chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[17] , - chany_top_in[17] } ) , - .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_right_ipin_0_undriven_sram_inv ) , - .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_110 ) ) ; -cby_2__1__mux_tree_tapbuf_size10_5 mux_right_ipin_3 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , - chany_bottom_in[8] , chany_top_in[8] , chany_bottom_in[14] , - chany_top_in[14] } ) , - .sram ( mux_tree_tapbuf_size10_2_sram ) , - .sram_inv ( mux_right_ipin_3_undriven_sram_inv ) , - .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_109 ) ) ; -cby_2__1__mux_tree_tapbuf_size10_6 mux_right_ipin_4 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , - chany_bottom_in[9] , chany_top_in[9] , chany_bottom_in[15] , - chany_top_in[15] } ) , - .sram ( mux_tree_tapbuf_size10_3_sram ) , - .sram_inv ( mux_right_ipin_4_undriven_sram_inv ) , - .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_108 ) ) ; -cby_2__1__mux_tree_tapbuf_size10_7 mux_right_ipin_7 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[8] , chany_top_in[8] , - chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[18] , - chany_top_in[18] } ) , - .sram ( mux_tree_tapbuf_size10_4_sram ) , - .sram_inv ( mux_right_ipin_7_undriven_sram_inv ) , - .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_109 ) ) ; -cby_2__1__mux_tree_tapbuf_size10 mux_right_ipin_8 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , - chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[19] , - chany_top_in[19] } ) , - .sram ( mux_tree_tapbuf_size10_5_sram ) , - .sram_inv ( mux_right_ipin_8_undriven_sram_inv ) , - .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_108 ) ) ; -cby_2__1__mux_tree_tapbuf_size10_2 mux_right_ipin_11 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , - chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[16] , - chany_top_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_6_sram ) , - .sram_inv ( mux_right_ipin_11_undriven_sram_inv ) , - .out ( left_grid_pin_27_ ) , .p0 ( optlc_net_109 ) ) ; -cby_2__1__mux_tree_tapbuf_size10_3 mux_right_ipin_12 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , - chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[17] , - chany_top_in[17] } ) , - .sram ( mux_tree_tapbuf_size10_7_sram ) , - .sram_inv ( mux_right_ipin_12_undriven_sram_inv ) , - .out ( left_grid_pin_28_ ) , .p0 ( optlc_net_108 ) ) ; -cby_2__1__mux_tree_tapbuf_size10_4 mux_right_ipin_15 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , - chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , - chany_top_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_8_sram ) , - .sram_inv ( mux_right_ipin_15_undriven_sram_inv ) , - .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_111 ) ) ; -cby_2__1__mux_tree_tapbuf_size10_mem_0 mem_left_ipin_0 ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; -cby_2__1__mux_tree_tapbuf_size10_mem_1 mem_right_ipin_0 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ; -cby_2__1__mux_tree_tapbuf_size10_mem_5 mem_right_ipin_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ; -cby_2__1__mux_tree_tapbuf_size10_mem_6 mem_right_ipin_4 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ; -cby_2__1__mux_tree_tapbuf_size10_mem_7 mem_right_ipin_7 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ; -cby_2__1__mux_tree_tapbuf_size10_mem mem_right_ipin_8 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ; -cby_2__1__mux_tree_tapbuf_size10_mem_2 mem_right_ipin_11 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ; -cby_2__1__mux_tree_tapbuf_size10_mem_3 mem_right_ipin_12 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ; -cby_2__1__mux_tree_tapbuf_size10_mem_4 mem_right_ipin_15 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , - .mem_out ( mux_tree_tapbuf_size10_8_sram ) ) ; -cby_2__1__mux_tree_tapbuf_size8_0 mux_right_ipin_1 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , - chany_bottom_in[14] , chany_top_in[14] } ) , - .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_right_ipin_1_undriven_sram_inv ) , - .out ( left_grid_pin_17_ ) , .p0 ( optlc_net_111 ) ) ; -cby_2__1__mux_tree_tapbuf_size8_4 mux_right_ipin_2 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , - chany_bottom_in[15] , chany_top_in[15] } ) , - .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_right_ipin_2_undriven_sram_inv ) , - .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_108 ) ) ; -cby_2__1__mux_tree_tapbuf_size8_5 mux_right_ipin_5 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , - chany_bottom_in[18] , chany_top_in[18] } ) , - .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_right_ipin_5_undriven_sram_inv ) , - .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_111 ) ) ; -cby_2__1__mux_tree_tapbuf_size8_6 mux_right_ipin_6 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[11] , chany_top_in[11] , - chany_bottom_in[19] , chany_top_in[19] } ) , - .sram ( mux_tree_tapbuf_size8_3_sram ) , - .sram_inv ( mux_right_ipin_6_undriven_sram_inv ) , - .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_110 ) ) ; -cby_2__1__mux_tree_tapbuf_size8 mux_right_ipin_9 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , - chany_bottom_in[14] , chany_top_in[14] } ) , - .sram ( mux_tree_tapbuf_size8_4_sram ) , - .sram_inv ( mux_right_ipin_9_undriven_sram_inv ) , - .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_111 ) ) ; -cby_2__1__mux_tree_tapbuf_size8_1 mux_right_ipin_10 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , - chany_bottom_in[15] , chany_top_in[15] } ) , - .sram ( mux_tree_tapbuf_size8_5_sram ) , - .sram_inv ( mux_right_ipin_10_undriven_sram_inv ) , - .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_108 ) ) ; -cby_2__1__mux_tree_tapbuf_size8_2 mux_right_ipin_13 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , - chany_bottom_in[18] , chany_top_in[18] } ) , - .sram ( mux_tree_tapbuf_size8_6_sram ) , - .sram_inv ( mux_right_ipin_13_undriven_sram_inv ) , - .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_111 ) ) ; -cby_2__1__mux_tree_tapbuf_size8_3 mux_right_ipin_14 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[11] , chany_top_in[11] , - chany_bottom_in[19] , chany_top_in[19] } ) , - .sram ( mux_tree_tapbuf_size8_7_sram ) , - .sram_inv ( mux_right_ipin_14_undriven_sram_inv ) , - .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_110 ) ) ; -cby_2__1__mux_tree_tapbuf_size8_mem_0 mem_right_ipin_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ; -cby_2__1__mux_tree_tapbuf_size8_mem_4 mem_right_ipin_2 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ; -cby_2__1__mux_tree_tapbuf_size8_mem_5 mem_right_ipin_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ; -cby_2__1__mux_tree_tapbuf_size8_mem_6 mem_right_ipin_6 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_3_sram ) ) ; -cby_2__1__mux_tree_tapbuf_size8_mem mem_right_ipin_9 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_4_sram ) ) ; -cby_2__1__mux_tree_tapbuf_size8_mem_1 mem_right_ipin_10 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_5_sram ) ) ; -cby_2__1__mux_tree_tapbuf_size8_mem_2 mem_right_ipin_13 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_6_sram ) ) ; -cby_2__1__mux_tree_tapbuf_size8_mem_3 mem_right_ipin_14 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_7_sram ) ) ; -cby_2__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , - .io_outpad ( left_width_0_height_0__pin_0_ ) , - .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_8_ } ) , - .ccff_tail ( ccff_tail ) , .p_abuf0 ( ropt_net_114 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_bottom_in[0] ) , - .X ( ropt_net_115 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chany_bottom_in[1] ) , - .X ( chany_top_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_bottom_in[2] ) , - .X ( chany_top_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_bottom_in[3] ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chany_bottom_in[4] ) , - .X ( chany_top_out[4] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_108 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_bottom_in[6] ) , - .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_109 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chany_bottom_in[8] ) , - .X ( chany_top_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_691 ( .A ( ropt_net_114 ) , - .X ( left_width_0_height_0__pin_1_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_689 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_116 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__11 ( .A ( chany_bottom_in[11] ) , - .X ( aps_rename_3_ ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__12 ( .A ( chany_bottom_in[12] ) , - .X ( aps_rename_4_ ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chany_bottom_in[13] ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__14 ( .A ( chany_bottom_in[14] ) , - .X ( aps_rename_5_ ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__15 ( .A ( chany_bottom_in[15] ) , - .X ( aps_rename_6_ ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chany_bottom_in[16] ) , - .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_692 ( .A ( ropt_net_115 ) , - .X ( chany_top_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chany_bottom_in[18] ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_110 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chany_top_in[0] ) , - .X ( chany_bottom_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chany_top_in[1] ) , - .X ( chany_bottom_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chany_top_in[2] ) , - .X ( chany_bottom_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chany_top_in[3] ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_111 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chany_top_in[5] ) , - .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_690 ( - .A ( chany_bottom_in[17] ) , .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chany_top_in[7] ) , - .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_693 ( .A ( ropt_net_116 ) , - .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chany_top_in[9] ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_694 ( .A ( ropt_net_117 ) , - .X ( left_width_0_height_0__pin_1_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_32__31 ( .A ( chany_top_in[11] ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_36__35 ( .A ( chany_top_in[15] ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_37__36 ( .A ( chany_top_in[16] ) , - .X ( chany_bottom_out[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_39__38 ( .A ( chany_top_in[18] ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_41__40 ( .A ( aps_rename_8_ ) , - .X ( aps_rename_9_ ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_66 ( .A ( chany_bottom_in[5] ) , - .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_67 ( .A ( chany_bottom_in[7] ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_74 ( .A ( chany_top_in[8] ) , - .X ( chany_bottom_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_77 ( .A ( chany_top_in[17] ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_78 ( .A ( aps_rename_9_ ) , - .X ( ropt_net_117 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_82 ( .A ( chany_bottom_in[19] ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_83 ( .A ( chany_top_in[10] ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_85 ( .A ( aps_rename_3_ ) , - .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_86 ( .A ( aps_rename_4_ ) , - .X ( chany_top_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_87 ( .A ( aps_rename_5_ ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_88 ( .A ( aps_rename_6_ ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_90 ( .A ( chany_top_in[12] ) , - .X ( chany_bottom_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_94 ( .A ( chany_top_in[4] ) , - .X ( chany_bottom_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_95 ( .A ( chany_top_in[6] ) , - .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_96 ( .A ( chany_top_in[14] ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_97 ( .A ( chany_top_in[19] ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_98 ( .A ( chany_bottom_in[10] ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_99 ( .A ( chany_top_in[13] ) , - .X ( chany_bottom_out[13] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__55 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__54 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__53 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__52 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__51 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__50 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__49 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__48 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_8__47 ( .A ( mem_out[3] ) , - .X ( net_net_72 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_96 ( .A ( net_net_72 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__46 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__45 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__44 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__43 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__42 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__41 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__40 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cby_1__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , - chany_bottom_out , chany_top_out , left_grid_pin_16_ , left_grid_pin_17_ , - left_grid_pin_18_ , left_grid_pin_19_ , left_grid_pin_20_ , - left_grid_pin_21_ , left_grid_pin_22_ , left_grid_pin_23_ , - left_grid_pin_24_ , left_grid_pin_25_ , left_grid_pin_26_ , - left_grid_pin_27_ , left_grid_pin_28_ , left_grid_pin_29_ , - left_grid_pin_30_ , left_grid_pin_31_ , ccff_tail , prog_clk__FEEDTHRU_1 , - prog_clk__FEEDTHRU_2 ) ; -input [0:0] prog_clk ; -input [0:19] chany_bottom_in ; -input [0:19] chany_top_in ; -input [0:0] ccff_head ; -output [0:19] chany_bottom_out ; -output [0:19] chany_top_out ; -output [0:0] left_grid_pin_16_ ; -output [0:0] left_grid_pin_17_ ; -output [0:0] left_grid_pin_18_ ; -output [0:0] left_grid_pin_19_ ; -output [0:0] left_grid_pin_20_ ; -output [0:0] left_grid_pin_21_ ; -output [0:0] left_grid_pin_22_ ; -output [0:0] left_grid_pin_23_ ; -output [0:0] left_grid_pin_24_ ; -output [0:0] left_grid_pin_25_ ; -output [0:0] left_grid_pin_26_ ; -output [0:0] left_grid_pin_27_ ; -output [0:0] left_grid_pin_28_ ; -output [0:0] left_grid_pin_29_ ; -output [0:0] left_grid_pin_30_ ; -output [0:0] left_grid_pin_31_ ; -output [0:0] ccff_tail ; -output [0:0] prog_clk__FEEDTHRU_1 ; -output [0:0] prog_clk__FEEDTHRU_2 ; - -wire [0:3] mux_right_ipin_0_undriven_sram_inv ; -wire [0:3] mux_right_ipin_10_undriven_sram_inv ; -wire [0:3] mux_right_ipin_11_undriven_sram_inv ; -wire [0:3] mux_right_ipin_12_undriven_sram_inv ; -wire [0:3] mux_right_ipin_13_undriven_sram_inv ; -wire [0:3] mux_right_ipin_14_undriven_sram_inv ; -wire [0:3] mux_right_ipin_15_undriven_sram_inv ; -wire [0:3] mux_right_ipin_1_undriven_sram_inv ; -wire [0:3] mux_right_ipin_2_undriven_sram_inv ; -wire [0:3] mux_right_ipin_3_undriven_sram_inv ; -wire [0:3] mux_right_ipin_4_undriven_sram_inv ; -wire [0:3] mux_right_ipin_5_undriven_sram_inv ; -wire [0:3] mux_right_ipin_6_undriven_sram_inv ; -wire [0:3] mux_right_ipin_7_undriven_sram_inv ; -wire [0:3] mux_right_ipin_8_undriven_sram_inv ; -wire [0:3] mux_right_ipin_9_undriven_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:3] mux_tree_tapbuf_size10_2_sram ; -wire [0:3] mux_tree_tapbuf_size10_3_sram ; -wire [0:3] mux_tree_tapbuf_size10_4_sram ; -wire [0:3] mux_tree_tapbuf_size10_5_sram ; -wire [0:3] mux_tree_tapbuf_size10_6_sram ; -wire [0:3] mux_tree_tapbuf_size10_7_sram ; -wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:3] mux_tree_tapbuf_size8_2_sram ; -wire [0:3] mux_tree_tapbuf_size8_3_sram ; -wire [0:3] mux_tree_tapbuf_size8_4_sram ; -wire [0:3] mux_tree_tapbuf_size8_5_sram ; -wire [0:3] mux_tree_tapbuf_size8_6_sram ; -wire [0:3] mux_tree_tapbuf_size8_7_sram ; -wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ; - -cby_1__1__mux_tree_tapbuf_size10_0 mux_right_ipin_0 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , - chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , - chany_top_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_right_ipin_0_undriven_sram_inv ) , - .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_103 ) ) ; -cby_1__1__mux_tree_tapbuf_size10_4 mux_right_ipin_3 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , - chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[19] , - chany_top_in[19] } ) , - .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_right_ipin_3_undriven_sram_inv ) , - .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_105 ) ) ; -cby_1__1__mux_tree_tapbuf_size10_5 mux_right_ipin_4 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , - chany_bottom_in[8] , chany_top_in[8] , chany_bottom_in[14] , - chany_top_in[14] } ) , - .sram ( mux_tree_tapbuf_size10_2_sram ) , - .sram_inv ( mux_right_ipin_4_undriven_sram_inv ) , - .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_103 ) ) ; -cby_1__1__mux_tree_tapbuf_size10_6 mux_right_ipin_7 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , - chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[17] , - chany_top_in[17] } ) , - .sram ( mux_tree_tapbuf_size10_3_sram ) , - .sram_inv ( mux_right_ipin_7_undriven_sram_inv ) , - .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_104 ) ) ; -cby_1__1__mux_tree_tapbuf_size10 mux_right_ipin_8 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[8] , chany_top_in[8] , - chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[18] , - chany_top_in[18] } ) , - .sram ( mux_tree_tapbuf_size10_4_sram ) , - .sram_inv ( mux_right_ipin_8_undriven_sram_inv ) , - .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_106 ) ) ; -cby_1__1__mux_tree_tapbuf_size10_1 mux_right_ipin_11 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , - chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[15] , - chany_top_in[15] } ) , - .sram ( mux_tree_tapbuf_size10_5_sram ) , - .sram_inv ( mux_right_ipin_11_undriven_sram_inv ) , - .out ( left_grid_pin_27_ ) , .p0 ( optlc_net_106 ) ) ; -cby_1__1__mux_tree_tapbuf_size10_2 mux_right_ipin_12 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , - chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[16] , - chany_top_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_6_sram ) , - .sram_inv ( mux_right_ipin_12_undriven_sram_inv ) , - .out ( left_grid_pin_28_ ) , .p0 ( optlc_net_106 ) ) ; -cby_1__1__mux_tree_tapbuf_size10_3 mux_right_ipin_15 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , - chany_bottom_in[15] , chany_top_in[15] , chany_bottom_in[19] , - chany_top_in[19] } ) , - .sram ( mux_tree_tapbuf_size10_7_sram ) , - .sram_inv ( mux_right_ipin_15_undriven_sram_inv ) , - .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_104 ) ) ; -cby_1__1__mux_tree_tapbuf_size10_mem_0 mem_right_ipin_0 ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; -cby_1__1__mux_tree_tapbuf_size10_mem_4 mem_right_ipin_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ; -cby_1__1__mux_tree_tapbuf_size10_mem_5 mem_right_ipin_4 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ; -cby_1__1__mux_tree_tapbuf_size10_mem_6 mem_right_ipin_7 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ; -cby_1__1__mux_tree_tapbuf_size10_mem mem_right_ipin_8 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ; -cby_1__1__mux_tree_tapbuf_size10_mem_1 mem_right_ipin_11 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ; -cby_1__1__mux_tree_tapbuf_size10_mem_2 mem_right_ipin_12 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ; -cby_1__1__mux_tree_tapbuf_size10_mem_3 mem_right_ipin_15 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .ccff_tail ( { ropt_net_120 } ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ; -cby_1__1__mux_tree_tapbuf_size8_0 mux_right_ipin_1 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , - chany_bottom_in[13] , chany_top_in[13] } ) , - .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_right_ipin_1_undriven_sram_inv ) , - .out ( left_grid_pin_17_ ) , .p0 ( optlc_net_105 ) ) ; -cby_1__1__mux_tree_tapbuf_size8_4 mux_right_ipin_2 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , - chany_bottom_in[14] , chany_top_in[14] } ) , - .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_right_ipin_2_undriven_sram_inv ) , - .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_103 ) ) ; -cby_1__1__mux_tree_tapbuf_size8_5 mux_right_ipin_5 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , - chany_bottom_in[17] , chany_top_in[17] } ) , - .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_right_ipin_5_undriven_sram_inv ) , - .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_105 ) ) ; -cby_1__1__mux_tree_tapbuf_size8_6 mux_right_ipin_6 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , - chany_bottom_in[18] , chany_top_in[18] } ) , - .sram ( mux_tree_tapbuf_size8_3_sram ) , - .sram_inv ( mux_right_ipin_6_undriven_sram_inv ) , - .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_103 ) ) ; -cby_1__1__mux_tree_tapbuf_size8 mux_right_ipin_9 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , - chany_bottom_in[13] , chany_top_in[13] } ) , - .sram ( mux_tree_tapbuf_size8_4_sram ) , - .sram_inv ( mux_right_ipin_9_undriven_sram_inv ) , - .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_105 ) ) ; -cby_1__1__mux_tree_tapbuf_size8_1 mux_right_ipin_10 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , - chany_bottom_in[14] , chany_top_in[14] } ) , - .sram ( mux_tree_tapbuf_size8_5_sram ) , - .sram_inv ( mux_right_ipin_10_undriven_sram_inv ) , - .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_103 ) ) ; -cby_1__1__mux_tree_tapbuf_size8_2 mux_right_ipin_13 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , - chany_bottom_in[17] , chany_top_in[17] } ) , - .sram ( mux_tree_tapbuf_size8_6_sram ) , - .sram_inv ( mux_right_ipin_13_undriven_sram_inv ) , - .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_105 ) ) ; -cby_1__1__mux_tree_tapbuf_size8_3 mux_right_ipin_14 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , - chany_bottom_in[18] , chany_top_in[18] } ) , - .sram ( mux_tree_tapbuf_size8_7_sram ) , - .sram_inv ( mux_right_ipin_14_undriven_sram_inv ) , - .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_106 ) ) ; -cby_1__1__mux_tree_tapbuf_size8_mem_0 mem_right_ipin_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ; -cby_1__1__mux_tree_tapbuf_size8_mem_4 mem_right_ipin_2 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ; -cby_1__1__mux_tree_tapbuf_size8_mem_5 mem_right_ipin_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ; -cby_1__1__mux_tree_tapbuf_size8_mem_6 mem_right_ipin_6 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_3_sram ) ) ; -cby_1__1__mux_tree_tapbuf_size8_mem mem_right_ipin_9 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_4_sram ) ) ; -cby_1__1__mux_tree_tapbuf_size8_mem_1 mem_right_ipin_10 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_5_sram ) ) ; -cby_1__1__mux_tree_tapbuf_size8_mem_2 mem_right_ipin_13 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_6_sram ) ) ; -cby_1__1__mux_tree_tapbuf_size8_mem_3 mem_right_ipin_14 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_7_sram ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_bottom_in[0] ) , - .X ( chany_top_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chany_bottom_in[1] ) , - .X ( chany_top_out[1] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_103 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_bottom_in[3] ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_104 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_757 ( .A ( ropt_net_125 ) , - .X ( chany_bottom_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_bottom_in[6] ) , - .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_758 ( .A ( ropt_net_126 ) , - .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chany_bottom_in[8] ) , - .X ( ropt_net_118 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chany_bottom_in[9] ) , - .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chany_bottom_in[10] ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_105 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chany_bottom_in[12] ) , - .X ( chany_top_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chany_bottom_in[13] ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_106 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_127 ) , - .X ( chany_bottom_out[4] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__16 ( .A ( chany_bottom_in[16] ) , - .X ( ropt_net_119 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_760 ( .A ( ropt_net_128 ) , - .X ( chany_bottom_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chany_bottom_in[18] ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_20__19 ( .A ( chany_bottom_in[19] ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chany_top_in[0] ) , - .X ( chany_bottom_out[0] ) ) ; -sky130_fd_sc_hd__buf_2 \prog_clk[0]_bip372 ( .A ( prog_clk[0] ) , - .X ( ctsbuf_net_1107 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( chany_top_in[11] ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chany_top_in[3] ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__24 ( .A ( chany_top_in[4] ) , - .X ( ropt_net_124 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_116 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chany_top_in[6] ) , - .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chany_top_in[7] ) , - .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_29__28 ( .A ( chany_top_in[8] ) , - .X ( chany_bottom_out[8] ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_325697 ( .A ( ctsbuf_net_1107 ) , - .X ( prog_clk__FEEDTHRU_2[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_31__30 ( .A ( chany_top_in[10] ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( ropt_net_129 ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_326698 ( .A ( ctsbuf_net_1107 ) , - .X ( prog_clk__FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_110 ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_728 ( - .A ( chany_bottom_in[17] ) , .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_729 ( .A ( chany_bottom_in[4] ) , - .X ( chany_top_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_730 ( .A ( chany_bottom_in[5] ) , - .X ( ropt_net_126 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_130 ) , - .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_39__38 ( .A ( chany_top_in[18] ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( .A ( chany_top_in[17] ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_59 ( .A ( chany_bottom_in[2] ) , - .X ( chany_top_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_766 ( .A ( ropt_net_131 ) , - .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_768 ( .A ( ropt_net_132 ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_63 ( .A ( chany_bottom_in[14] ) , - .X ( ropt_net_117 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( - .A ( chany_bottom_in[11] ) , .X ( ropt_net_130 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_116 ) , - .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_68 ( .A ( chany_top_in[13] ) , - .X ( BUF_net_68 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( .A ( chany_top_in[15] ) , - .X ( BUF_net_69 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_70 ( .A ( chany_top_in[16] ) , - .X ( chany_bottom_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_117 ) , - .X ( ropt_net_129 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_75 ( .A ( chany_bottom_in[7] ) , - .X ( ropt_net_110 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_76 ( .A ( chany_bottom_in[15] ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( ropt_net_118 ) , - .X ( chany_top_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_119 ) , - .X ( ropt_net_131 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_120 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_121 ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( chany_top_in[2] ) , - .X ( chany_bottom_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_87 ( .A ( chany_top_in[9] ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_88 ( .A ( chany_top_in[14] ) , - .X ( ropt_net_121 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_93 ( .A ( BUF_net_68 ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_94 ( .A ( BUF_net_69 ) , - .X ( ropt_net_132 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_95 ( .A ( chany_top_in[19] ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( chany_top_in[12] ) , - .X ( ropt_net_125 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( chany_top_in[1] ) , - .X ( ropt_net_128 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_124 ) , - .X ( ropt_net_127 ) ) ; -endmodule - - -module cby_0__1__direct_interc ( in , out ) ; -input [0:0] in ; -output [0:0] out ; - -assign out[0] = in[0] ; -endmodule - - -module cby_0__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( prog_clk , - ccff_head , ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:0] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__44 ( .A ( mem_out[0] ) , - .X ( net_net_86 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_163 ( .A ( net_net_86 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_0__1__EMBEDDED_IO ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , - FPGA_OUT , FPGA_DIR , p_abuf0 , p_abuf1 ) ; -input SOC_IN ; -output SOC_OUT ; -output SOC_DIR ; -output FPGA_IN ; -input FPGA_OUT ; -input FPGA_DIR ; -output p_abuf0 ; -output p_abuf1 ; - -wire aps_rename_2_ ; - -assign SOC_OUT = FPGA_OUT ; - -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__42 ( .A ( SOC_IN ) , .X ( p_abuf1 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__43 ( .A ( FPGA_DIR ) , - .X ( aps_rename_2_ ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_45 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_46 ( .A ( p_abuf1 ) , - .X ( BUF_net_46 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_128 ( .A ( BUF_net_46 ) , - .X ( p_abuf0 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_162 ( .A ( aps_rename_2_ ) , - .X ( SOC_DIR ) ) ; -endmodule - - -module cby_0__1__logical_tile_io_mode_physical__iopad ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , p_abuf0 , p_abuf1 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] iopad_outpad ; -input [0:0] ccff_head ; -output [0:0] iopad_inpad ; -output [0:0] ccff_tail ; -output p_abuf0 ; -output p_abuf1 ; - -wire [0:0] EMBEDDED_IO_0_en ; - -cby_0__1__EMBEDDED_IO EMBEDDED_IO_0_ ( - .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , - .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , - .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , - .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , - .p_abuf1 ( p_abuf1 ) ) ; -cby_0__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) ) ; -endmodule - - -module cby_0__1__logical_tile_io_mode_io_ ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , - ccff_tail , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] io_outpad ; -input [0:0] ccff_head ; -output [0:0] io_inpad ; -output [0:0] ccff_tail ; -output p_abuf0 ; - -cby_0__1__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , - .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , - .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; -cby_0__1__direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( { p_abuf1 } ) ) ; -cby_0__1__direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( io_outpad ) ) ; -endmodule - - -module cby_0__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__41 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_0__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cby_0__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , - chany_bottom_out , chany_top_out , left_grid_pin_0_ , ccff_tail , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , right_width_0_height_0__pin_0_ , - right_width_0_height_0__pin_1_upper , - right_width_0_height_0__pin_1_lower ) ; -input [0:0] prog_clk ; -input [0:19] chany_bottom_in ; -input [0:19] chany_top_in ; -input [0:0] ccff_head ; -output [0:19] chany_bottom_out ; -output [0:19] chany_top_out ; -output [0:0] left_grid_pin_0_ ; -output [0:0] ccff_tail ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] right_width_0_height_0__pin_0_ ; -output [0:0] right_width_0_height_0__pin_1_upper ; -output [0:0] right_width_0_height_0__pin_1_lower ; - -wire ropt_net_168 ; -wire [0:3] mux_right_ipin_0_undriven_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_0_sram ; - -cby_0__1__mux_tree_tapbuf_size10 mux_right_ipin_0 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , - chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , - chany_top_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_right_ipin_0_undriven_sram_inv ) , - .out ( left_grid_pin_0_ ) , .p0 ( optlc_net_164 ) ) ; -cby_0__1__mux_tree_tapbuf_size10_mem mem_right_ipin_0 ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( { ccff_tail_mid } ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; -cby_0__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_178 } ) , - .io_outpad ( right_width_0_height_0__pin_0_ ) , - .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_8_ } ) , - .ccff_tail ( { ropt_net_170 } ) , - .p_abuf0 ( ropt_net_168 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_165 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_164 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_165 ) , - .X ( ropt_net_210 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_745 ( - .A ( chany_bottom_in[10] ) , .X ( ropt_net_233 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_167 ) , - .X ( right_width_0_height_0__pin_1_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( ropt_net_168 ) , - .X ( right_width_0_height_0__pin_1_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_169 ) , - .X ( ropt_net_211 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_749 ( .A ( ropt_net_170 ) , - .X ( ropt_net_223 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_171 ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_751 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_226 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_786 ( .A ( ropt_net_205 ) , - .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_206 ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_752 ( .A ( chany_bottom_in[1] ) , - .X ( ropt_net_235 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_753 ( - .A ( chany_bottom_in[14] ) , .X ( ropt_net_231 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_754 ( .A ( chany_bottom_in[7] ) , - .X ( ropt_net_230 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_755 ( - .A ( chany_bottom_in[16] ) , .X ( ropt_net_228 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_756 ( .A ( chany_top_in[13] ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_757 ( .A ( ropt_net_178 ) , - .X ( ropt_net_224 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_758 ( - .A ( chany_bottom_in[18] ) , .X ( ropt_net_234 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_759 ( .A ( chany_top_in[18] ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_760 ( .A ( chany_top_in[9] ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chany_top_in[0] ) , - .X ( chany_bottom_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( .A ( chany_bottom_in[5] ) , - .X ( ropt_net_227 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( chany_top_in[7] ) , - .X ( ropt_net_225 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_184 ) , - .X ( ropt_net_212 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_764 ( .A ( chany_top_in[6] ) , - .X ( ropt_net_229 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_186 ) , - .X ( ropt_net_205 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_187 ) , - .X ( ropt_net_214 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_232 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_207 ) , - .X ( chany_bottom_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_189 ) , - .X ( ropt_net_215 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_31__30 ( .A ( chany_top_in[10] ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( ropt_net_208 ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( ropt_net_209 ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_190 ) , - .X ( ropt_net_209 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_191 ) , - .X ( ropt_net_220 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_192 ) , - .X ( ropt_net_213 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_37__36 ( .A ( chany_top_in[16] ) , - .X ( ropt_net_202 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_193 ) , - .X ( ropt_net_208 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_194 ) , - .X ( ropt_net_217 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_195 ) , - .X ( ropt_net_206 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_196 ) , - .X ( ropt_net_218 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_47 ( .A ( chany_bottom_in[0] ) , - .X ( ropt_net_189 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( ropt_net_210 ) , - .X ( chany_bottom_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_197 ) , - .X ( ropt_net_216 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_198 ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_51 ( .A ( chany_bottom_in[4] ) , - .X ( ropt_net_191 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( ropt_net_211 ) , - .X ( chany_bottom_out[12] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_53 ( .A ( chany_bottom_in[6] ) , - .X ( ropt_net_192 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_212 ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( ropt_net_213 ) , - .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_795 ( .A ( ropt_net_214 ) , - .X ( chany_top_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( ropt_net_215 ) , - .X ( chany_top_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_58 ( .A ( chany_bottom_in[11] ) , - .X ( ropt_net_186 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_59 ( .A ( chany_bottom_in[12] ) , - .X ( ropt_net_187 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_60 ( .A ( chany_bottom_in[13] ) , - .X ( ropt_net_196 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_216 ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_62 ( .A ( chany_bottom_in[15] ) , - .X ( ropt_net_184 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_800 ( .A ( ropt_net_217 ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_199 ) , - .X ( ropt_net_219 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_218 ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_200 ) , - .X ( chany_bottom_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_201 ) , - .X ( ropt_net_222 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_68 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_203 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_69 ( .A ( chany_top_in[3] ) , - .X ( ropt_net_201 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_802 ( .A ( ropt_net_219 ) , - .X ( chany_top_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_202 ) , - .X ( chany_bottom_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_803 ( .A ( ropt_net_220 ) , - .X ( chany_top_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_804 ( .A ( ropt_net_221 ) , - .X ( chany_bottom_out[8] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_74 ( .A ( chany_top_in[8] ) , - .X ( BUF_net_74 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_203 ) , - .X ( ropt_net_207 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( ropt_net_222 ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_223 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_224 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_79 ( .A ( chany_top_in[14] ) , - .X ( ropt_net_190 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_80 ( .A ( chany_top_in[15] ) , - .X ( ropt_net_194 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_81 ( .A ( chany_top_in[17] ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_817 ( .A ( ropt_net_225 ) , - .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_226 ) , - .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_227 ) , - .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_228 ) , - .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_229 ) , - .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_230 ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_231 ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( ropt_net_232 ) , - .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_826 ( .A ( ropt_net_233 ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_827 ( .A ( ropt_net_234 ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_235 ) , - .X ( chany_top_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_96 ( .A ( chany_bottom_in[8] ) , - .X ( BUF_net_96 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_108 ( .A ( chany_top_in[1] ) , - .X ( ropt_net_200 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_121 ( .A ( chany_top_in[19] ) , - .X ( ropt_net_198 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_122 ( .A ( aps_rename_8_ ) , - .X ( ropt_net_167 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_125 ( .A ( BUF_net_74 ) , - .X ( ropt_net_221 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_126 ( .A ( chany_top_in[11] ) , - .X ( ropt_net_171 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_127 ( .A ( chany_top_in[12] ) , - .X ( ropt_net_169 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_131 ( .A ( chany_bottom_in[2] ) , - .X ( ropt_net_199 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_132 ( .A ( chany_bottom_in[3] ) , - .X ( ropt_net_195 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_137 ( .A ( BUF_net_96 ) , - .X ( chany_top_out[8] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_144 ( .A ( chany_bottom_in[17] ) , - .X ( ropt_net_193 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_146 ( .A ( chany_bottom_in[19] ) , - .X ( ropt_net_197 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_150 ( .A ( chany_top_in[4] ) , - .X ( ropt_net_165 ) ) ; -endmodule - - -module cbx_1__2__direct_interc ( in , out ) ; -input [0:0] in ; -output [0:0] out ; - -assign out[0] = in[0] ; -endmodule - - -module cbx_1__2__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( prog_clk , - ccff_head , ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:0] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_20__61 ( .A ( mem_out[0] ) , - .X ( net_net_76 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_76 ( .A ( net_net_76 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__2__EMBEDDED_IO ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , - FPGA_OUT , FPGA_DIR , p_abuf0 ) ; -input SOC_IN ; -output SOC_OUT ; -output SOC_DIR ; -output FPGA_IN ; -input FPGA_OUT ; -input FPGA_DIR ; -output p_abuf0 ; - -wire aps_rename_1_ ; - -assign SOC_OUT = FPGA_OUT ; - -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__59 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__60 ( .A ( FPGA_DIR ) , - .X ( aps_rename_1_ ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_75 ( .A ( aps_rename_1_ ) , - .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_63 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; -endmodule - - -module cbx_1__2__logical_tile_io_mode_physical__iopad ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] iopad_outpad ; -input [0:0] ccff_head ; -output [0:0] iopad_inpad ; -output [0:0] ccff_tail ; -output p_abuf0 ; - -wire [0:0] EMBEDDED_IO_0_en ; - -cbx_1__2__EMBEDDED_IO EMBEDDED_IO_0_ ( - .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , - .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , - .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , - .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__2__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) ) ; -endmodule - - -module cbx_1__2__logical_tile_io_mode_io_ ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , - ccff_tail , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] io_outpad ; -input [0:0] ccff_head ; -output [0:0] io_inpad ; -output [0:0] ccff_tail ; -output p_abuf0 ; - -cbx_1__2__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , - .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , - .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__2__direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( io_outpad ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__58 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__57 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__56 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__55 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__54 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__53 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__52 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__51 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__50 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__49 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__48 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__47 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__46 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__45 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__44 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__43 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__42 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_64 ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cbx_1__2_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , - chanx_left_out , chanx_right_out , top_grid_pin_0_ , bottom_grid_pin_0_ , - bottom_grid_pin_1_ , bottom_grid_pin_2_ , bottom_grid_pin_3_ , - bottom_grid_pin_4_ , bottom_grid_pin_5_ , bottom_grid_pin_6_ , - bottom_grid_pin_7_ , bottom_grid_pin_8_ , bottom_grid_pin_9_ , - bottom_grid_pin_10_ , bottom_grid_pin_11_ , bottom_grid_pin_12_ , - bottom_grid_pin_13_ , bottom_grid_pin_14_ , bottom_grid_pin_15_ , - ccff_tail , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , bottom_width_0_height_0__pin_0_ , - bottom_width_0_height_0__pin_1_upper , - bottom_width_0_height_0__pin_1_lower , SC_IN_TOP , SC_IN_BOT , - SC_OUT_TOP , SC_OUT_BOT , prog_clk__FEEDTHRU_1 , prog_clk__FEEDTHRU_2 ) ; -input [0:0] prog_clk ; -input [0:19] chanx_left_in ; -input [0:19] chanx_right_in ; -input [0:0] ccff_head ; -output [0:19] chanx_left_out ; -output [0:19] chanx_right_out ; -output [0:0] top_grid_pin_0_ ; -output [0:0] bottom_grid_pin_0_ ; -output [0:0] bottom_grid_pin_1_ ; -output [0:0] bottom_grid_pin_2_ ; -output [0:0] bottom_grid_pin_3_ ; -output [0:0] bottom_grid_pin_4_ ; -output [0:0] bottom_grid_pin_5_ ; -output [0:0] bottom_grid_pin_6_ ; -output [0:0] bottom_grid_pin_7_ ; -output [0:0] bottom_grid_pin_8_ ; -output [0:0] bottom_grid_pin_9_ ; -output [0:0] bottom_grid_pin_10_ ; -output [0:0] bottom_grid_pin_11_ ; -output [0:0] bottom_grid_pin_12_ ; -output [0:0] bottom_grid_pin_13_ ; -output [0:0] bottom_grid_pin_14_ ; -output [0:0] bottom_grid_pin_15_ ; -output [0:0] ccff_tail ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] bottom_width_0_height_0__pin_0_ ; -output [0:0] bottom_width_0_height_0__pin_1_upper ; -output [0:0] bottom_width_0_height_0__pin_1_lower ; -input SC_IN_TOP ; -input SC_IN_BOT ; -output SC_OUT_TOP ; -output SC_OUT_BOT ; -output [0:0] prog_clk__FEEDTHRU_1 ; -output [0:0] prog_clk__FEEDTHRU_2 ; - -wire ropt_net_112 ; -wire [0:3] mux_bottom_ipin_0_undriven_sram_inv ; -wire [0:3] mux_top_ipin_0_undriven_sram_inv ; -wire [0:3] mux_top_ipin_10_undriven_sram_inv ; -wire [0:3] mux_top_ipin_11_undriven_sram_inv ; -wire [0:3] mux_top_ipin_12_undriven_sram_inv ; -wire [0:3] mux_top_ipin_13_undriven_sram_inv ; -wire [0:3] mux_top_ipin_14_undriven_sram_inv ; -wire [0:3] mux_top_ipin_15_undriven_sram_inv ; -wire [0:3] mux_top_ipin_1_undriven_sram_inv ; -wire [0:3] mux_top_ipin_2_undriven_sram_inv ; -wire [0:3] mux_top_ipin_3_undriven_sram_inv ; -wire [0:3] mux_top_ipin_4_undriven_sram_inv ; -wire [0:3] mux_top_ipin_5_undriven_sram_inv ; -wire [0:3] mux_top_ipin_6_undriven_sram_inv ; -wire [0:3] mux_top_ipin_7_undriven_sram_inv ; -wire [0:3] mux_top_ipin_8_undriven_sram_inv ; -wire [0:3] mux_top_ipin_9_undriven_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:3] mux_tree_tapbuf_size10_2_sram ; -wire [0:3] mux_tree_tapbuf_size10_3_sram ; -wire [0:3] mux_tree_tapbuf_size10_4_sram ; -wire [0:3] mux_tree_tapbuf_size10_5_sram ; -wire [0:3] mux_tree_tapbuf_size10_6_sram ; -wire [0:3] mux_tree_tapbuf_size10_7_sram ; -wire [0:3] mux_tree_tapbuf_size10_8_sram ; -wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:3] mux_tree_tapbuf_size8_2_sram ; -wire [0:3] mux_tree_tapbuf_size8_3_sram ; -wire [0:3] mux_tree_tapbuf_size8_4_sram ; -wire [0:3] mux_tree_tapbuf_size8_5_sram ; -wire [0:3] mux_tree_tapbuf_size8_6_sram ; -wire [0:3] mux_tree_tapbuf_size8_7_sram ; -wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ; - -assign SC_IN_TOP = SC_IN_BOT ; - -cbx_1__2__mux_tree_tapbuf_size10_0 mux_bottom_ipin_0 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , - chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , - chanx_right_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_bottom_ipin_0_undriven_sram_inv ) , - .out ( top_grid_pin_0_ ) , .p0 ( optlc_net_108 ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_1 mux_top_ipin_0 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , - chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , - chanx_right_in[17] } ) , - .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_top_ipin_0_undriven_sram_inv ) , - .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_108 ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_5 mux_top_ipin_3 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , - chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[14] , - chanx_right_in[14] } ) , - .sram ( mux_tree_tapbuf_size10_2_sram ) , - .sram_inv ( mux_top_ipin_3_undriven_sram_inv ) , - .out ( { ropt_net_117 } ) , - .p0 ( optlc_net_107 ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_6 mux_top_ipin_4 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , - chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[15] , - chanx_right_in[15] } ) , - .sram ( mux_tree_tapbuf_size10_3_sram ) , - .sram_inv ( mux_top_ipin_4_undriven_sram_inv ) , - .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_108 ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_7 mux_top_ipin_7 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[8] , chanx_right_in[8] , - chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , - chanx_right_in[18] } ) , - .sram ( mux_tree_tapbuf_size10_4_sram ) , - .sram_inv ( mux_top_ipin_7_undriven_sram_inv ) , - .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_107 ) ) ; -cbx_1__2__mux_tree_tapbuf_size10 mux_top_ipin_8 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , - chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , - chanx_right_in[19] } ) , - .sram ( mux_tree_tapbuf_size10_5_sram ) , - .sram_inv ( mux_top_ipin_8_undriven_sram_inv ) , - .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_106 ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_2 mux_top_ipin_11 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , - chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[16] , - chanx_right_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_6_sram ) , - .sram_inv ( mux_top_ipin_11_undriven_sram_inv ) , - .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_106 ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_3 mux_top_ipin_12 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , - chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[17] , - chanx_right_in[17] } ) , - .sram ( mux_tree_tapbuf_size10_7_sram ) , - .sram_inv ( mux_top_ipin_12_undriven_sram_inv ) , - .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_108 ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_4 mux_top_ipin_15 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , - chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , - chanx_right_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_8_sram ) , - .sram_inv ( mux_top_ipin_15_undriven_sram_inv ) , - .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_108 ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_mem_0 mem_bottom_ipin_0 ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_0 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_mem_5 mem_top_ipin_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_mem_6 mem_top_ipin_4 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_mem_7 mem_top_ipin_7 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_mem mem_top_ipin_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_11 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_12 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_15 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , - .mem_out ( mux_tree_tapbuf_size10_8_sram ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_0 mux_top_ipin_1 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , - chanx_left_in[14] , chanx_right_in[14] } ) , - .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_top_ipin_1_undriven_sram_inv ) , - .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_109 ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_4 mux_top_ipin_2 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , - chanx_left_in[15] , chanx_right_in[15] } ) , - .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_top_ipin_2_undriven_sram_inv ) , - .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_106 ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_5 mux_top_ipin_5 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , - chanx_left_in[18] , chanx_right_in[18] } ) , - .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_top_ipin_5_undriven_sram_inv ) , - .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_107 ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_6 mux_top_ipin_6 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , - chanx_left_in[19] , chanx_right_in[19] } ) , - .sram ( mux_tree_tapbuf_size8_3_sram ) , - .sram_inv ( mux_top_ipin_6_undriven_sram_inv ) , - .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_107 ) ) ; -cbx_1__2__mux_tree_tapbuf_size8 mux_top_ipin_9 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , - chanx_left_in[14] , chanx_right_in[14] } ) , - .sram ( mux_tree_tapbuf_size8_4_sram ) , - .sram_inv ( mux_top_ipin_9_undriven_sram_inv ) , - .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_109 ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_1 mux_top_ipin_10 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , - chanx_left_in[15] , chanx_right_in[15] } ) , - .sram ( mux_tree_tapbuf_size8_5_sram ) , - .sram_inv ( mux_top_ipin_10_undriven_sram_inv ) , - .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_106 ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_2 mux_top_ipin_13 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , - chanx_left_in[18] , chanx_right_in[18] } ) , - .sram ( mux_tree_tapbuf_size8_6_sram ) , - .sram_inv ( mux_top_ipin_13_undriven_sram_inv ) , - .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_107 ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_3 mux_top_ipin_14 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , - chanx_left_in[19] , chanx_right_in[19] } ) , - .sram ( mux_tree_tapbuf_size8_7_sram ) , - .sram_inv ( mux_top_ipin_14_undriven_sram_inv ) , - .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_106 ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_mem_0 mem_top_ipin_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_mem_4 mem_top_ipin_2 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_mem_5 mem_top_ipin_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_mem_6 mem_top_ipin_6 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_3_sram ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_mem mem_top_ipin_9 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_4_sram ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_mem_1 mem_top_ipin_10 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_5_sram ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_mem_2 mem_top_ipin_13 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_6_sram ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_mem_3 mem_top_ipin_14 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_7_sram ) ) ; -cbx_1__2__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_114 } ) , - .io_outpad ( bottom_width_0_height_0__pin_0_ ) , - .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_3_ } ) , - .ccff_tail ( ccff_tail ) , .p_abuf0 ( ropt_net_112 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_106 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chanx_left_in[1] ) , - .X ( chanx_right_out[1] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_107 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chanx_left_in[4] ) , - .X ( chanx_right_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chanx_left_in[5] ) , - .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chanx_left_in[6] ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chanx_left_in[7] ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_108 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chanx_left_in[9] ) , - .X ( ropt_net_130 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_109 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_12__11 ( .A ( chanx_left_in[11] ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chanx_left_in[12] ) , - .X ( chanx_right_out[12] ) ) ; -sky130_fd_sc_hd__buf_2 \prog_clk[0]_bip377 ( .A ( prog_clk[0] ) , - .X ( ctsbuf_net_2111 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chanx_left_in[14] ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_112 ) , - .X ( ropt_net_137 ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_330707 ( .A ( ctsbuf_net_2111 ) , - .X ( prog_clk__FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chanx_left_in[17] ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_132 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_20__19 ( .A ( chanx_left_in[19] ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_right_in[0] ) , - .X ( ropt_net_131 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , - .X ( ropt_net_134 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chanx_right_in[2] ) , - .X ( ropt_net_147 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chanx_right_in[3] ) , - .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__24 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_129 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chanx_right_in[5] ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_331708 ( .A ( ctsbuf_net_2111 ) , - .X ( prog_clk__FEEDTHRU_2[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chanx_right_in[7] ) , - .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( .A ( chanx_right_in[6] ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_114 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( ropt_net_115 ) , - .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_138 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_33__32 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_127 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_117 ) , - .X ( ropt_net_141 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_137 ) , - .X ( bottom_width_0_height_0__pin_1_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_741 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_146 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_37__36 ( .A ( chanx_right_in[16] ) , - .X ( chanx_left_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_119 ) , - .X ( chanx_right_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_39__38 ( .A ( chanx_right_in[18] ) , - .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_40__39 ( .A ( chanx_right_in[19] ) , - .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_41__40 ( .A ( aps_rename_3_ ) , - .X ( ropt_net_121 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_42__41 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_115 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_66 ( .A ( chanx_left_in[0] ) , - .X ( chanx_right_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_744 ( .A ( chanx_right_in[14] ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_138 ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( ropt_net_139 ) , - .X ( chanx_left_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_121 ) , - .X ( ropt_net_142 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_780 ( .A ( ropt_net_140 ) , - .X ( chanx_left_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_785 ( .A ( ropt_net_141 ) , - .X ( bottom_grid_pin_3_[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_786 ( .A ( ropt_net_142 ) , - .X ( bottom_width_0_height_0__pin_1_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_143 ) , - .X ( chanx_left_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_139 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_79 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_119 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_750 ( .A ( chanx_left_in[13] ) , - .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_124 ) , - .X ( ropt_net_145 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_752 ( .A ( chanx_left_in[16] ) , - .X ( chanx_right_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( ropt_net_144 ) , - .X ( chanx_right_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_753 ( .A ( chanx_left_in[10] ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_88 ( .A ( chanx_left_in[15] ) , - .X ( ropt_net_124 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( ropt_net_145 ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_90 ( .A ( chanx_right_in[9] ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_146 ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_92 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_133 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_93 ( .A ( chanx_right_in[13] ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_94 ( .A ( chanx_right_in[15] ) , - .X ( ropt_net_135 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_96 ( .A ( chanx_left_in[2] ) , - .X ( ropt_net_128 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_754 ( .A ( ropt_net_127 ) , - .X ( chanx_left_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_147 ) , - .X ( chanx_left_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_128 ) , - .X ( ropt_net_144 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_129 ) , - .X ( ropt_net_143 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_130 ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_131 ) , - .X ( chanx_left_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_132 ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_133 ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_134 ) , - .X ( ropt_net_140 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_135 ) , - .X ( chanx_left_out[15] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__56 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__55 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__54 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__53 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__52 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__51 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__50 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__49 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__48 ( .A ( mem_out[3] ) , - .X ( net_net_72 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_90 ( .A ( net_net_72 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__47 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__46 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__45 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__44 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__43 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__42 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__41 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cbx_1__1_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , - chanx_left_out , chanx_right_out , bottom_grid_pin_0_ , - bottom_grid_pin_1_ , bottom_grid_pin_2_ , bottom_grid_pin_3_ , - bottom_grid_pin_4_ , bottom_grid_pin_5_ , bottom_grid_pin_6_ , - bottom_grid_pin_7_ , bottom_grid_pin_8_ , bottom_grid_pin_9_ , - bottom_grid_pin_10_ , bottom_grid_pin_11_ , bottom_grid_pin_12_ , - bottom_grid_pin_13_ , bottom_grid_pin_14_ , bottom_grid_pin_15_ , - ccff_tail , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , SC_OUT_BOT , - prog_clk__FEEDTHRU_1 ) ; -input [0:0] prog_clk ; -input [0:19] chanx_left_in ; -input [0:19] chanx_right_in ; -input [0:0] ccff_head ; -output [0:19] chanx_left_out ; -output [0:19] chanx_right_out ; -output [0:0] bottom_grid_pin_0_ ; -output [0:0] bottom_grid_pin_1_ ; -output [0:0] bottom_grid_pin_2_ ; -output [0:0] bottom_grid_pin_3_ ; -output [0:0] bottom_grid_pin_4_ ; -output [0:0] bottom_grid_pin_5_ ; -output [0:0] bottom_grid_pin_6_ ; -output [0:0] bottom_grid_pin_7_ ; -output [0:0] bottom_grid_pin_8_ ; -output [0:0] bottom_grid_pin_9_ ; -output [0:0] bottom_grid_pin_10_ ; -output [0:0] bottom_grid_pin_11_ ; -output [0:0] bottom_grid_pin_12_ ; -output [0:0] bottom_grid_pin_13_ ; -output [0:0] bottom_grid_pin_14_ ; -output [0:0] bottom_grid_pin_15_ ; -output [0:0] ccff_tail ; -input SC_IN_TOP ; -input SC_IN_BOT ; -output SC_OUT_TOP ; -output SC_OUT_BOT ; -output [0:0] prog_clk__FEEDTHRU_1 ; - -wire [0:3] mux_top_ipin_0_undriven_sram_inv ; -wire [0:3] mux_top_ipin_10_undriven_sram_inv ; -wire [0:3] mux_top_ipin_11_undriven_sram_inv ; -wire [0:3] mux_top_ipin_12_undriven_sram_inv ; -wire [0:3] mux_top_ipin_13_undriven_sram_inv ; -wire [0:3] mux_top_ipin_14_undriven_sram_inv ; -wire [0:3] mux_top_ipin_15_undriven_sram_inv ; -wire [0:3] mux_top_ipin_1_undriven_sram_inv ; -wire [0:3] mux_top_ipin_2_undriven_sram_inv ; -wire [0:3] mux_top_ipin_3_undriven_sram_inv ; -wire [0:3] mux_top_ipin_4_undriven_sram_inv ; -wire [0:3] mux_top_ipin_5_undriven_sram_inv ; -wire [0:3] mux_top_ipin_6_undriven_sram_inv ; -wire [0:3] mux_top_ipin_7_undriven_sram_inv ; -wire [0:3] mux_top_ipin_8_undriven_sram_inv ; -wire [0:3] mux_top_ipin_9_undriven_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:3] mux_tree_tapbuf_size10_2_sram ; -wire [0:3] mux_tree_tapbuf_size10_3_sram ; -wire [0:3] mux_tree_tapbuf_size10_4_sram ; -wire [0:3] mux_tree_tapbuf_size10_5_sram ; -wire [0:3] mux_tree_tapbuf_size10_6_sram ; -wire [0:3] mux_tree_tapbuf_size10_7_sram ; -wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:3] mux_tree_tapbuf_size8_2_sram ; -wire [0:3] mux_tree_tapbuf_size8_3_sram ; -wire [0:3] mux_tree_tapbuf_size8_4_sram ; -wire [0:3] mux_tree_tapbuf_size8_5_sram ; -wire [0:3] mux_tree_tapbuf_size8_6_sram ; -wire [0:3] mux_tree_tapbuf_size8_7_sram ; -wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ; - -assign SC_IN_TOP = SC_IN_BOT ; - -cbx_1__1__mux_tree_tapbuf_size10_0 mux_top_ipin_0 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , - chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , - chanx_right_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_top_ipin_0_undriven_sram_inv ) , - .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_104 ) ) ; -cbx_1__1__mux_tree_tapbuf_size10_4 mux_top_ipin_3 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , - chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , - chanx_right_in[19] } ) , - .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_top_ipin_3_undriven_sram_inv ) , - .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_105 ) ) ; -cbx_1__1__mux_tree_tapbuf_size10_5 mux_top_ipin_4 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , - chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[14] , - chanx_right_in[14] } ) , - .sram ( mux_tree_tapbuf_size10_2_sram ) , - .sram_inv ( mux_top_ipin_4_undriven_sram_inv ) , - .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_102 ) ) ; -cbx_1__1__mux_tree_tapbuf_size10_6 mux_top_ipin_7 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , - chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , - chanx_right_in[17] } ) , - .sram ( mux_tree_tapbuf_size10_3_sram ) , - .sram_inv ( mux_top_ipin_7_undriven_sram_inv ) , - .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_104 ) ) ; -cbx_1__1__mux_tree_tapbuf_size10 mux_top_ipin_8 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[8] , chanx_right_in[8] , - chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , - chanx_right_in[18] } ) , - .sram ( mux_tree_tapbuf_size10_4_sram ) , - .sram_inv ( mux_top_ipin_8_undriven_sram_inv ) , - .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_103 ) ) ; -cbx_1__1__mux_tree_tapbuf_size10_1 mux_top_ipin_11 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , - chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[15] , - chanx_right_in[15] } ) , - .sram ( mux_tree_tapbuf_size10_5_sram ) , - .sram_inv ( mux_top_ipin_11_undriven_sram_inv ) , - .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_105 ) ) ; -cbx_1__1__mux_tree_tapbuf_size10_2 mux_top_ipin_12 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , - chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[16] , - chanx_right_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_6_sram ) , - .sram_inv ( mux_top_ipin_12_undriven_sram_inv ) , - .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_103 ) ) ; -cbx_1__1__mux_tree_tapbuf_size10_3 mux_top_ipin_15 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , - chanx_left_in[15] , chanx_right_in[15] , chanx_left_in[19] , - chanx_right_in[19] } ) , - .sram ( mux_tree_tapbuf_size10_7_sram ) , - .sram_inv ( mux_top_ipin_15_undriven_sram_inv ) , - .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_105 ) ) ; -cbx_1__1__mux_tree_tapbuf_size10_mem_0 mem_top_ipin_0 ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; -cbx_1__1__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ; -cbx_1__1__mux_tree_tapbuf_size10_mem_5 mem_top_ipin_4 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ; -cbx_1__1__mux_tree_tapbuf_size10_mem_6 mem_top_ipin_7 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ; -cbx_1__1__mux_tree_tapbuf_size10_mem mem_top_ipin_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ; -cbx_1__1__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_11 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ; -cbx_1__1__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_12 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ; -cbx_1__1__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_15 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .ccff_tail ( { ropt_net_124 } ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_0 mux_top_ipin_1 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , - chanx_left_in[13] , chanx_right_in[13] } ) , - .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_top_ipin_1_undriven_sram_inv ) , - .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_105 ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_4 mux_top_ipin_2 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , - chanx_left_in[14] , chanx_right_in[14] } ) , - .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_top_ipin_2_undriven_sram_inv ) , - .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_102 ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_5 mux_top_ipin_5 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , - chanx_left_in[17] , chanx_right_in[17] } ) , - .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_top_ipin_5_undriven_sram_inv ) , - .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_104 ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_6 mux_top_ipin_6 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , - chanx_left_in[18] , chanx_right_in[18] } ) , - .sram ( mux_tree_tapbuf_size8_3_sram ) , - .sram_inv ( mux_top_ipin_6_undriven_sram_inv ) , - .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_103 ) ) ; -cbx_1__1__mux_tree_tapbuf_size8 mux_top_ipin_9 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , - chanx_left_in[13] , chanx_right_in[13] } ) , - .sram ( mux_tree_tapbuf_size8_4_sram ) , - .sram_inv ( mux_top_ipin_9_undriven_sram_inv ) , - .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_103 ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_1 mux_top_ipin_10 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , - chanx_left_in[14] , chanx_right_in[14] } ) , - .sram ( mux_tree_tapbuf_size8_5_sram ) , - .sram_inv ( mux_top_ipin_10_undriven_sram_inv ) , - .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_102 ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_2 mux_top_ipin_13 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , - chanx_left_in[17] , chanx_right_in[17] } ) , - .sram ( mux_tree_tapbuf_size8_6_sram ) , - .sram_inv ( mux_top_ipin_13_undriven_sram_inv ) , - .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_104 ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_3 mux_top_ipin_14 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , - chanx_left_in[18] , chanx_right_in[18] } ) , - .sram ( mux_tree_tapbuf_size8_7_sram ) , - .sram_inv ( mux_top_ipin_14_undriven_sram_inv ) , - .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_103 ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_mem_0 mem_top_ipin_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_mem_4 mem_top_ipin_2 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_mem_5 mem_top_ipin_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_mem_6 mem_top_ipin_6 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_3_sram ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_mem mem_top_ipin_9 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_4_sram ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_mem_1 mem_top_ipin_10 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_5_sram ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_mem_2 mem_top_ipin_13 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_6_sram ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_mem_3 mem_top_ipin_14 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_7_sram ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chanx_left_in[0] ) , - .X ( chanx_right_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_134 ) , - .X ( chanx_left_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chanx_left_in[2] ) , - .X ( chanx_right_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__4 ( .A ( chanx_left_in[4] ) , - .X ( ropt_net_128 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_102 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_103 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__7 ( .A ( chanx_left_in[7] ) , - .X ( ropt_net_130 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_104 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_105 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chanx_left_in[10] ) , - .X ( ropt_net_133 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( ropt_net_135 ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__clkbuf_1 \prog_clk[0]_bip373 ( .A ( prog_clk[0] ) , - .X ( ctsbuf_net_1106 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( chanx_right_in[4] ) , - .X ( chanx_left_out[4] ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_326699 ( .A ( ctsbuf_net_1106 ) , - .X ( prog_clk__FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_136 ) , - .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( ropt_net_108 ) , - .X ( ropt_net_146 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chanx_left_in[17] ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_137 ) , - .X ( chanx_left_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_138 ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_right_in[0] ) , - .X ( chanx_left_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , - .X ( ropt_net_123 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chanx_right_in[2] ) , - .X ( chanx_left_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chanx_right_in[3] ) , - .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_728 ( .A ( chanx_left_in[13] ) , - .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chanx_right_in[5] ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_148 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chanx_right_in[7] ) , - .X ( ropt_net_145 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_110 ) , - .X ( ropt_net_141 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chanx_right_in[9] ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( chanx_right_in[15] ) , - .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_32__31 ( .A ( chanx_right_in[11] ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_134 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_126 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_35__34 ( .A ( chanx_right_in[14] ) , - .X ( ropt_net_132 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( chanx_left_in[9] ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_37__36 ( .A ( chanx_right_in[16] ) , - .X ( ropt_net_129 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_38__37 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_121 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_39__38 ( .A ( chanx_right_in[18] ) , - .X ( ropt_net_125 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( chanx_left_in[5] ) , - .X ( ropt_net_149 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_41__40 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_108 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_770 ( .A ( ropt_net_139 ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_59 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_131 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( chanx_left_in[18] ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_772 ( .A ( ropt_net_140 ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_774 ( .A ( ropt_net_141 ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_63 ( .A ( chanx_left_in[14] ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_64 ( .A ( chanx_left_in[15] ) , - .X ( ropt_net_110 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_116 ) , - .X ( ropt_net_135 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( .A ( ropt_net_142 ) , - .X ( chanx_right_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( ropt_net_143 ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_777 ( .A ( ropt_net_144 ) , - .X ( chanx_left_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( chanx_left_in[11] ) , - .X ( ropt_net_139 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_70 ( .A ( chanx_right_in[19] ) , - .X ( ropt_net_127 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( chanx_left_in[8] ) , - .X ( chanx_right_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( chanx_left_in[16] ) , - .X ( ropt_net_147 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_739 ( .A ( chanx_left_in[1] ) , - .X ( chanx_right_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_121 ) , - .X ( ropt_net_138 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( .A ( chanx_right_in[12] ) , - .X ( chanx_left_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_145 ) , - .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_79 ( .A ( chanx_left_in[19] ) , - .X ( ropt_net_116 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_123 ) , - .X ( ropt_net_137 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_124 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_125 ) , - .X ( ropt_net_136 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( chanx_left_in[12] ) , - .X ( chanx_right_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_146 ) , - .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_88 ( .A ( chanx_right_in[10] ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_147 ) , - .X ( chanx_right_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_148 ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_149 ) , - .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_126 ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( .A ( ropt_net_127 ) , - .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_128 ) , - .X ( ropt_net_142 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_129 ) , - .X ( ropt_net_144 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_130 ) , - .X ( ropt_net_143 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_131 ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_132 ) , - .X ( ropt_net_140 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_133 ) , - .X ( chanx_right_out[10] ) ) ; -endmodule - - -module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( prog_clk , - ccff_head , ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:0] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_24__70 ( .A ( mem_out[0] ) , - .X ( net_net_108 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_163 ( .A ( net_net_108 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__0__EMBEDDED_IO ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , - FPGA_OUT , FPGA_DIR , p_abuf0 ) ; -input SOC_IN ; -output SOC_OUT ; -output SOC_DIR ; -output FPGA_IN ; -input FPGA_OUT ; -input FPGA_DIR ; -output p_abuf0 ; - -assign SOC_OUT = FPGA_OUT ; - -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__68 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 FTB_23__69 ( .A ( FPGA_DIR ) , - .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_82 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; -endmodule - - -module cbx_1__0__logical_tile_io_mode_physical__iopad ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] iopad_outpad ; -input [0:0] ccff_head ; -output [0:0] iopad_inpad ; -output [0:0] ccff_tail ; -output p_abuf0 ; - -wire [0:0] EMBEDDED_IO_0_en ; - -cbx_1__0__EMBEDDED_IO EMBEDDED_IO_0_ ( - .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , - .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , - .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , - .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) ) ; -endmodule - - -module cbx_1__0__logical_tile_io_mode_io_ ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , - ccff_tail , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] io_outpad ; -input [0:0] ccff_head ; -output [0:0] io_inpad ; -output [0:0] ccff_tail ; -output p_abuf0 ; - -cbx_1__0__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , - .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , - .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__0__direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( io_outpad ) ) ; -endmodule - - -module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_4 ( prog_clk , - ccff_head , ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:0] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__67 ( .A ( mem_out[0] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__0__EMBEDDED_IO_4 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , - FPGA_OUT , FPGA_DIR , p_abuf0 ) ; -input SOC_IN ; -output SOC_OUT ; -output SOC_DIR ; -output FPGA_IN ; -input FPGA_OUT ; -input FPGA_DIR ; -output p_abuf0 ; - -assign SOC_OUT = FPGA_OUT ; - -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__65 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 FTB_20__66 ( .A ( FPGA_DIR ) , - .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_150 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; -endmodule - - -module cbx_1__0__logical_tile_io_mode_physical__iopad_4 ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] iopad_outpad ; -input [0:0] ccff_head ; -output [0:0] iopad_inpad ; -output [0:0] ccff_tail ; -output p_abuf0 ; - -wire [0:0] EMBEDDED_IO_0_en ; - -cbx_1__0__EMBEDDED_IO_4 EMBEDDED_IO_0_ ( - .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , - .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , - .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , - .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_4 EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) ) ; -endmodule - - -module cbx_1__0__logical_tile_io_mode_io__4 ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , - ccff_tail , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] io_outpad ; -input [0:0] ccff_head ; -output [0:0] io_inpad ; -output [0:0] ccff_tail ; -output p_abuf0 ; - -cbx_1__0__logical_tile_io_mode_physical__iopad_4 logical_tile_io_mode_physical__iopad_0 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , - .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , - .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__0__direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( io_outpad ) ) ; -endmodule - - -module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_3 ( prog_clk , - ccff_head , ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:0] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__64 ( .A ( mem_out[0] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__0__EMBEDDED_IO_3 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , - FPGA_OUT , FPGA_DIR , p_abuf0 ) ; -input SOC_IN ; -output SOC_OUT ; -output SOC_DIR ; -output FPGA_IN ; -input FPGA_OUT ; -input FPGA_DIR ; -output p_abuf0 ; - -wire aps_rename_3_ ; - -assign SOC_OUT = FPGA_OUT ; - -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__62 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__63 ( .A ( FPGA_DIR ) , - .X ( aps_rename_3_ ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_78 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_162 ( .A ( aps_rename_3_ ) , - .X ( SOC_DIR ) ) ; -endmodule - - -module cbx_1__0__logical_tile_io_mode_physical__iopad_3 ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] iopad_outpad ; -input [0:0] ccff_head ; -output [0:0] iopad_inpad ; -output [0:0] ccff_tail ; -output p_abuf0 ; - -wire [0:0] EMBEDDED_IO_0_en ; - -cbx_1__0__EMBEDDED_IO_3 EMBEDDED_IO_0_ ( - .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , - .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , - .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , - .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_3 EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) ) ; -endmodule - - -module cbx_1__0__logical_tile_io_mode_io__3 ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , - ccff_tail , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] io_outpad ; -input [0:0] ccff_head ; -output [0:0] io_inpad ; -output [0:0] ccff_tail ; -output p_abuf0 ; - -cbx_1__0__logical_tile_io_mode_physical__iopad_3 logical_tile_io_mode_physical__iopad_0 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , - .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , - .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__0__direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( io_outpad ) ) ; -endmodule - - -module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_2 ( prog_clk , - ccff_head , ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:0] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__61 ( .A ( mem_out[0] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__0__EMBEDDED_IO_2 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , - FPGA_OUT , FPGA_DIR , p_abuf0 , p_abuf1 ) ; -input SOC_IN ; -output SOC_OUT ; -output SOC_DIR ; -output FPGA_IN ; -input FPGA_OUT ; -input FPGA_DIR ; -output p_abuf0 ; -output p_abuf1 ; - -assign SOC_OUT = FPGA_OUT ; - -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__59 ( .A ( SOC_IN ) , .X ( p_abuf1 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__60 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_75 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_76 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; -endmodule - - -module cbx_1__0__logical_tile_io_mode_physical__iopad_2 ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , p_abuf0 , p_abuf1 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] iopad_outpad ; -input [0:0] ccff_head ; -output [0:0] iopad_inpad ; -output [0:0] ccff_tail ; -output p_abuf0 ; -output p_abuf1 ; - -wire [0:0] EMBEDDED_IO_0_en ; - -cbx_1__0__EMBEDDED_IO_2 EMBEDDED_IO_0_ ( - .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , - .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , - .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , - .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , - .p_abuf1 ( p_abuf1 ) ) ; -cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_2 EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) ) ; -endmodule - - -module cbx_1__0__logical_tile_io_mode_io__2 ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , - ccff_tail , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] io_outpad ; -input [0:0] ccff_head ; -output [0:0] io_inpad ; -output [0:0] ccff_tail ; -output p_abuf0 ; - -cbx_1__0__logical_tile_io_mode_physical__iopad_2 logical_tile_io_mode_physical__iopad_0 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , - .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , - .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; -cbx_1__0__direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( { p_abuf1 } ) ) ; -cbx_1__0__direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( io_outpad ) ) ; -endmodule - - -module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_1 ( prog_clk , - ccff_head , ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:0] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__58 ( .A ( mem_out[0] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__0__EMBEDDED_IO_1 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , - FPGA_OUT , FPGA_DIR , p_abuf0 ) ; -input SOC_IN ; -output SOC_OUT ; -output SOC_DIR ; -output FPGA_IN ; -input FPGA_OUT ; -input FPGA_DIR ; -output p_abuf0 ; - -assign SOC_OUT = FPGA_OUT ; - -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__56 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__57 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_141 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; -endmodule - - -module cbx_1__0__logical_tile_io_mode_physical__iopad_1 ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] iopad_outpad ; -input [0:0] ccff_head ; -output [0:0] iopad_inpad ; -output [0:0] ccff_tail ; -output p_abuf0 ; - -wire [0:0] EMBEDDED_IO_0_en ; - -cbx_1__0__EMBEDDED_IO_1 EMBEDDED_IO_0_ ( - .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , - .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , - .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , - .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_1 EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) ) ; -endmodule - - -module cbx_1__0__logical_tile_io_mode_io__1 ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , - ccff_tail , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] io_outpad ; -input [0:0] ccff_head ; -output [0:0] io_inpad ; -output [0:0] ccff_tail ; -output p_abuf0 ; - -cbx_1__0__logical_tile_io_mode_physical__iopad_1 logical_tile_io_mode_physical__iopad_0 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , - .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , - .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__0__direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( io_outpad ) ) ; -endmodule - - -module cbx_1__0__direct_interc ( in , out ) ; -input [0:0] in ; -output [0:0] out ; - -assign out[0] = in[0] ; -endmodule - - -module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_0 ( prog_clk , - ccff_head , ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:0] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__55 ( .A ( mem_out[0] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__0__EMBEDDED_IO_0 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , - FPGA_OUT , FPGA_DIR , p_abuf0 , p_abuf1 ) ; -input SOC_IN ; -output SOC_OUT ; -output SOC_DIR ; -output FPGA_IN ; -input FPGA_OUT ; -input FPGA_DIR ; -output p_abuf0 ; -output p_abuf1 ; - -assign SOC_OUT = FPGA_OUT ; - -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__53 ( .A ( SOC_IN ) , .X ( p_abuf1 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__54 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_71 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_146 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; -endmodule - - -module cbx_1__0__logical_tile_io_mode_physical__iopad_0 ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , p_abuf0 , p_abuf1 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] iopad_outpad ; -input [0:0] ccff_head ; -output [0:0] iopad_inpad ; -output [0:0] ccff_tail ; -output p_abuf0 ; -output p_abuf1 ; - -wire [0:0] EMBEDDED_IO_0_en ; - -cbx_1__0__EMBEDDED_IO_0 EMBEDDED_IO_0_ ( - .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , - .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , - .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , - .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , - .p_abuf1 ( p_abuf1 ) ) ; -cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_0 EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) ) ; -endmodule - - -module cbx_1__0__logical_tile_io_mode_io__0 ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , - ccff_tail , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] io_outpad ; -input [0:0] ccff_head ; -output [0:0] io_inpad ; -output [0:0] ccff_tail ; -output p_abuf0 ; - -cbx_1__0__logical_tile_io_mode_physical__iopad_0 logical_tile_io_mode_physical__iopad_0 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , - .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , - .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; -cbx_1__0__direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( { p_abuf1 } ) ) ; -cbx_1__0__direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( io_outpad ) ) ; -endmodule - - -module cbx_1__0__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__52 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__0__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__51 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__0__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__50 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__0__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__49 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__0__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__48 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__0__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__47 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__0__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; -endmodule - - -module cbx_1__0__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cbx_1__0__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cbx_1__0__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cbx_1__0__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; -endmodule - - -module cbx_1__0__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cbx_1__0_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , - chanx_left_out , chanx_right_out , bottom_grid_pin_0_ , - bottom_grid_pin_2_ , bottom_grid_pin_4_ , bottom_grid_pin_6_ , - bottom_grid_pin_8_ , bottom_grid_pin_10_ , ccff_tail , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , top_width_0_height_0__pin_0_ , - top_width_0_height_0__pin_2_ , top_width_0_height_0__pin_4_ , - top_width_0_height_0__pin_6_ , top_width_0_height_0__pin_8_ , - top_width_0_height_0__pin_10_ , top_width_0_height_0__pin_1_upper , - top_width_0_height_0__pin_1_lower , top_width_0_height_0__pin_3_upper , - top_width_0_height_0__pin_3_lower , top_width_0_height_0__pin_5_upper , - top_width_0_height_0__pin_5_lower , top_width_0_height_0__pin_7_upper , - top_width_0_height_0__pin_7_lower , top_width_0_height_0__pin_9_upper , - top_width_0_height_0__pin_9_lower , top_width_0_height_0__pin_11_upper , - top_width_0_height_0__pin_11_lower , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , - SC_OUT_BOT , prog_clk__FEEDTHRU_1 ) ; -input [0:0] prog_clk ; -input [0:19] chanx_left_in ; -input [0:19] chanx_right_in ; -input [0:0] ccff_head ; -output [0:19] chanx_left_out ; -output [0:19] chanx_right_out ; -output [0:0] bottom_grid_pin_0_ ; -output [0:0] bottom_grid_pin_2_ ; -output [0:0] bottom_grid_pin_4_ ; -output [0:0] bottom_grid_pin_6_ ; -output [0:0] bottom_grid_pin_8_ ; -output [0:0] bottom_grid_pin_10_ ; -output [0:0] ccff_tail ; -input [0:5] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:5] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:5] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] top_width_0_height_0__pin_0_ ; -input [0:0] top_width_0_height_0__pin_2_ ; -input [0:0] top_width_0_height_0__pin_4_ ; -input [0:0] top_width_0_height_0__pin_6_ ; -input [0:0] top_width_0_height_0__pin_8_ ; -input [0:0] top_width_0_height_0__pin_10_ ; -output [0:0] top_width_0_height_0__pin_1_upper ; -output [0:0] top_width_0_height_0__pin_1_lower ; -output [0:0] top_width_0_height_0__pin_3_upper ; -output [0:0] top_width_0_height_0__pin_3_lower ; -output [0:0] top_width_0_height_0__pin_5_upper ; -output [0:0] top_width_0_height_0__pin_5_lower ; -output [0:0] top_width_0_height_0__pin_7_upper ; -output [0:0] top_width_0_height_0__pin_7_lower ; -output [0:0] top_width_0_height_0__pin_9_upper ; -output [0:0] top_width_0_height_0__pin_9_lower ; -output [0:0] top_width_0_height_0__pin_11_upper ; -output [0:0] top_width_0_height_0__pin_11_lower ; -input SC_IN_TOP ; -input SC_IN_BOT ; -output SC_OUT_TOP ; -output SC_OUT_BOT ; -output [0:0] prog_clk__FEEDTHRU_1 ; - -wire ropt_net_191 ; -wire ropt_net_197 ; -wire ropt_net_179 ; -wire ropt_net_177 ; -wire ropt_net_190 ; -wire ropt_net_178 ; -wire [0:3] mux_top_ipin_0_undriven_sram_inv ; -wire [0:3] mux_top_ipin_1_undriven_sram_inv ; -wire [0:3] mux_top_ipin_2_undriven_sram_inv ; -wire [0:3] mux_top_ipin_3_undriven_sram_inv ; -wire [0:3] mux_top_ipin_4_undriven_sram_inv ; -wire [0:3] mux_top_ipin_5_undriven_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:3] mux_tree_tapbuf_size10_2_sram ; -wire [0:3] mux_tree_tapbuf_size10_3_sram ; -wire [0:3] mux_tree_tapbuf_size10_4_sram ; -wire [0:3] mux_tree_tapbuf_size10_5_sram ; -wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; -wire [0:0] logical_tile_io_mode_io__0_ccff_tail ; -wire [0:0] logical_tile_io_mode_io__1_ccff_tail ; -wire [0:0] logical_tile_io_mode_io__2_ccff_tail ; -wire [0:0] logical_tile_io_mode_io__3_ccff_tail ; -wire [0:0] logical_tile_io_mode_io__4_ccff_tail ; - -assign SC_IN_TOP = SC_IN_BOT ; - -cbx_1__0__mux_tree_tapbuf_size10_0 mux_top_ipin_0 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , - chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , - chanx_right_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_top_ipin_0_undriven_sram_inv ) , - .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_174 ) ) ; -cbx_1__0__mux_tree_tapbuf_size10_1 mux_top_ipin_1 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , - chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , - chanx_right_in[17] } ) , - .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_top_ipin_1_undriven_sram_inv ) , - .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_173 ) ) ; -cbx_1__0__mux_tree_tapbuf_size10_2 mux_top_ipin_2 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , - chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , - chanx_right_in[18] } ) , - .sram ( mux_tree_tapbuf_size10_2_sram ) , - .sram_inv ( mux_top_ipin_2_undriven_sram_inv ) , - .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_173 ) ) ; -cbx_1__0__mux_tree_tapbuf_size10_3 mux_top_ipin_3 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , - chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , - chanx_right_in[19] } ) , - .sram ( mux_tree_tapbuf_size10_3_sram ) , - .sram_inv ( mux_top_ipin_3_undriven_sram_inv ) , - .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_173 ) ) ; -cbx_1__0__mux_tree_tapbuf_size10_4 mux_top_ipin_4 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , - chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[14] , - chanx_right_in[14] } ) , - .sram ( mux_tree_tapbuf_size10_4_sram ) , - .sram_inv ( mux_top_ipin_4_undriven_sram_inv ) , - .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_174 ) ) ; -cbx_1__0__mux_tree_tapbuf_size10 mux_top_ipin_5 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , - chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[15] , - chanx_right_in[15] } ) , - .sram ( mux_tree_tapbuf_size10_5_sram ) , - .sram_inv ( mux_top_ipin_5_undriven_sram_inv ) , - .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_174 ) ) ; -cbx_1__0__mux_tree_tapbuf_size10_mem_0 mem_top_ipin_0 ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; -cbx_1__0__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ; -cbx_1__0__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_2 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ; -cbx_1__0__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ; -cbx_1__0__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_4 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ; -cbx_1__0__mux_tree_tapbuf_size10_mem mem_top_ipin_5 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , - .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ; -cbx_1__0__logical_tile_io_mode_io__0 logical_tile_io_mode_io__0 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_196 } ) , - .io_outpad ( top_width_0_height_0__pin_0_ ) , - .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_8_ } ) , - .ccff_tail ( logical_tile_io_mode_io__0_ccff_tail ) , - .p_abuf0 ( ropt_net_191 ) ) ; -cbx_1__0__logical_tile_io_mode_io__1 logical_tile_io_mode_io__1 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[1] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[1] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_200 } ) , - .io_outpad ( top_width_0_height_0__pin_2_ ) , - .ccff_head ( logical_tile_io_mode_io__0_ccff_tail ) , - .io_inpad ( { aps_rename_10_ } ) , - .ccff_tail ( logical_tile_io_mode_io__1_ccff_tail ) , - .p_abuf0 ( ropt_net_197 ) ) ; -cbx_1__0__logical_tile_io_mode_io__2 logical_tile_io_mode_io__2 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[2] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[2] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_198 } ) , - .io_outpad ( top_width_0_height_0__pin_4_ ) , - .ccff_head ( logical_tile_io_mode_io__1_ccff_tail ) , - .io_inpad ( { aps_rename_12_ } ) , - .ccff_tail ( logical_tile_io_mode_io__2_ccff_tail ) , - .p_abuf0 ( ropt_net_179 ) ) ; -cbx_1__0__logical_tile_io_mode_io__3 logical_tile_io_mode_io__3 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[3] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[3] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_193 } ) , - .io_outpad ( top_width_0_height_0__pin_6_ ) , - .ccff_head ( logical_tile_io_mode_io__2_ccff_tail ) , - .io_inpad ( { aps_rename_13_ } ) , - .ccff_tail ( logical_tile_io_mode_io__3_ccff_tail ) , - .p_abuf0 ( ropt_net_177 ) ) ; -cbx_1__0__logical_tile_io_mode_io__4 logical_tile_io_mode_io__4 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[4] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[4] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_201 } ) , - .io_outpad ( top_width_0_height_0__pin_8_ ) , - .ccff_head ( logical_tile_io_mode_io__3_ccff_tail ) , - .io_inpad ( { aps_rename_14_ } ) , - .ccff_tail ( logical_tile_io_mode_io__4_ccff_tail ) , - .p_abuf0 ( ropt_net_190 ) ) ; -cbx_1__0__logical_tile_io_mode_io_ logical_tile_io_mode_io__5 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[5] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[5] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[5] ) , - .io_outpad ( top_width_0_height_0__pin_10_ ) , - .ccff_head ( logical_tile_io_mode_io__4_ccff_tail ) , - .io_inpad ( { aps_rename_15_ } ) , - .ccff_tail ( { ropt_net_212 } ) , - .p_abuf0 ( ropt_net_178 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_166 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_173 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_168 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_174 ) ) ; -sky130_fd_sc_hd__clkbuf_1 \prog_clk[0]_bip435 ( .A ( prog_clk[0] ) , - .X ( ctsbuf_net_1176 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , - .X ( ropt_net_207 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_177 ) , - .X ( ropt_net_243 ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_326761 ( .A ( ctsbuf_net_1176 ) , - .X ( prog_clk__FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_849 ( .A ( ropt_net_239 ) , - .X ( chanx_left_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_178 ) , - .X ( ropt_net_247 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_266 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chanx_left_in[9] ) , - .X ( ropt_net_208 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_179 ) , - .X ( ropt_net_249 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( ropt_net_180 ) , - .X ( ropt_net_245 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_792 ( .A ( ropt_net_181 ) , - .X ( top_width_0_height_0__pin_11_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( ropt_net_182 ) , - .X ( ropt_net_270 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_244 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__15 ( .A ( chanx_left_in[15] ) , - .X ( ropt_net_222 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_184 ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( chanx_right_in[5] ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_233 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( chanx_right_in[7] ) , - .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_187 ) , - .X ( top_width_0_height_0__pin_3_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , - .X ( ropt_net_219 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_850 ( .A ( ropt_net_240 ) , - .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_188 ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_246 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_190 ) , - .X ( ropt_net_250 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_224 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_191 ) , - .X ( top_width_0_height_0__pin_1_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_192 ) , - .X ( ropt_net_240 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__29 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_221 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__30 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_223 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_851 ( .A ( ropt_net_241 ) , - .X ( chanx_left_out[12] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__32 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_216 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_193 ) , - .X ( ropt_net_262 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_194 ) , - .X ( top_width_0_height_0__pin_1_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_36__35 ( .A ( chanx_right_in[15] ) , - .X ( ropt_net_226 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_37__36 ( .A ( chanx_right_in[16] ) , - .X ( ropt_net_229 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( ropt_net_195 ) , - .X ( ropt_net_264 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_39__38 ( .A ( chanx_right_in[18] ) , - .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_852 ( .A ( ropt_net_242 ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_41__40 ( .A ( aps_rename_8_ ) , - .X ( aps_rename_9_ ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_853 ( .A ( ropt_net_243 ) , - .X ( top_width_0_height_0__pin_7_upper[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_43__42 ( .A ( aps_rename_12_ ) , - .X ( ropt_net_182 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_196 ) , - .X ( ropt_net_254 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_197 ) , - .X ( top_width_0_height_0__pin_3_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_46__45 ( .A ( aps_rename_15_ ) , - .X ( ropt_net_181 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_47__46 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_180 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_85 ( .A ( chanx_left_in[0] ) , - .X ( ropt_net_209 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_86 ( .A ( chanx_left_in[1] ) , - .X ( ropt_net_225 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_87 ( .A ( chanx_left_in[4] ) , - .X ( ropt_net_214 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_88 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_184 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_809 ( .A ( ropt_net_198 ) , - .X ( ropt_net_268 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_90 ( .A ( chanx_left_in[11] ) , - .X ( ropt_net_227 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_810 ( .A ( ropt_net_199 ) , - .X ( ropt_net_265 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_92 ( .A ( chanx_left_in[16] ) , - .X ( ropt_net_213 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_93 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_210 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_94 ( .A ( chanx_right_in[3] ) , - .X ( ropt_net_220 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_854 ( .A ( ropt_net_244 ) , - .X ( chanx_left_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_857 ( .A ( ropt_net_245 ) , - .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_858 ( .A ( ropt_net_246 ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_811 ( .A ( ropt_net_200 ) , - .X ( ropt_net_267 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_860 ( .A ( ropt_net_247 ) , - .X ( top_width_0_height_0__pin_11_upper[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_100 ( .A ( chanx_right_in[14] ) , - .X ( ropt_net_231 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_862 ( .A ( ropt_net_248 ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_812 ( .A ( ropt_net_201 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_103 ( .A ( aps_rename_9_ ) , - .X ( ropt_net_194 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_104 ( .A ( aps_rename_10_ ) , - .X ( ropt_net_187 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_864 ( .A ( ropt_net_249 ) , - .X ( top_width_0_height_0__pin_5_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_865 ( .A ( ropt_net_250 ) , - .X ( top_width_0_height_0__pin_9_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( chanx_right_in[2] ) , - .X ( chanx_left_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_814 ( .A ( chanx_left_in[5] ) , - .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_815 ( .A ( chanx_left_in[7] ) , - .X ( ropt_net_269 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_205 ) , - .X ( ropt_net_256 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_817 ( .A ( chanx_right_in[13] ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_207 ) , - .X ( ropt_net_248 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_208 ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_209 ) , - .X ( ropt_net_260 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_210 ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_211 ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_212 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_213 ) , - .X ( chanx_right_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_131 ( .A ( chanx_left_in[2] ) , - .X ( ropt_net_228 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_866 ( .A ( ropt_net_251 ) , - .X ( chanx_left_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_133 ( .A ( chanx_left_in[10] ) , - .X ( ropt_net_211 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_134 ( .A ( chanx_left_in[12] ) , - .X ( ropt_net_205 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_135 ( .A ( chanx_left_in[13] ) , - .X ( ropt_net_217 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_136 ( .A ( chanx_left_in[19] ) , - .X ( ropt_net_215 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_137 ( .A ( chanx_right_in[0] ) , - .X ( ropt_net_232 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_138 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_218 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( ropt_net_214 ) , - .X ( ropt_net_259 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_144 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_188 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_145 ( .A ( chanx_right_in[19] ) , - .X ( ropt_net_192 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_826 ( .A ( ropt_net_215 ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_867 ( .A ( ropt_net_252 ) , - .X ( chanx_left_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_154 ( .A ( chanx_left_in[14] ) , - .X ( ropt_net_230 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_827 ( .A ( ropt_net_216 ) , - .X ( ropt_net_241 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_217 ) , - .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_829 ( .A ( ropt_net_218 ) , - .X ( ropt_net_252 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_219 ) , - .X ( ropt_net_239 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_220 ) , - .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_160 ( .A ( aps_rename_13_ ) , - .X ( ropt_net_199 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_161 ( .A ( aps_rename_14_ ) , - .X ( ropt_net_195 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_832 ( .A ( ropt_net_221 ) , - .X ( ropt_net_242 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_833 ( .A ( ropt_net_222 ) , - .X ( ropt_net_255 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_834 ( .A ( ropt_net_223 ) , - .X ( ropt_net_257 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_835 ( .A ( ropt_net_224 ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_836 ( .A ( ropt_net_225 ) , - .X ( ropt_net_258 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_838 ( .A ( ropt_net_226 ) , - .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_839 ( .A ( ropt_net_227 ) , - .X ( ropt_net_261 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_840 ( .A ( ropt_net_228 ) , - .X ( chanx_right_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_841 ( .A ( ropt_net_229 ) , - .X ( ropt_net_263 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_843 ( .A ( ropt_net_230 ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_844 ( .A ( ropt_net_231 ) , - .X ( ropt_net_253 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_845 ( .A ( ropt_net_232 ) , - .X ( ropt_net_251 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_847 ( .A ( ropt_net_233 ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_868 ( .A ( ropt_net_253 ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_871 ( .A ( ropt_net_254 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_873 ( .A ( ropt_net_255 ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_874 ( .A ( ropt_net_256 ) , - .X ( chanx_right_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_875 ( .A ( ropt_net_257 ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_876 ( .A ( ropt_net_258 ) , - .X ( chanx_right_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_877 ( .A ( ropt_net_259 ) , - .X ( chanx_right_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_878 ( .A ( ropt_net_260 ) , - .X ( chanx_right_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_879 ( .A ( ropt_net_261 ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_880 ( .A ( ropt_net_262 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_882 ( .A ( ropt_net_263 ) , - .X ( chanx_left_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_889 ( .A ( ropt_net_264 ) , - .X ( top_width_0_height_0__pin_9_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_890 ( .A ( ropt_net_265 ) , - .X ( top_width_0_height_0__pin_7_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_892 ( .A ( ropt_net_266 ) , - .X ( chanx_right_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_893 ( .A ( ropt_net_267 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_894 ( .A ( ropt_net_268 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_896 ( .A ( ropt_net_269 ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_899 ( .A ( ropt_net_270 ) , - .X ( top_width_0_height_0__pin_5_lower[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_35__40 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_34__39 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__38 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__37 ( .A ( mem_out[1] ) , - .X ( net_net_51 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_51 ( .A ( net_net_51 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_22 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__36 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_21 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__35 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_20 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__34 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_19 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__33 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_18 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__32 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_17 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__31 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__30 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__29 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__28 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__27 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__26 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__25 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__24 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__23 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__22 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__21 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__20 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__19 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__18 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__17 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__16 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__15 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__14 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_22 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_21 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_20 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_19 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__13 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size5_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__12 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size5_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__11 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__10 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__9 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size6_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__8 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__7 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__6 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module sb_2__2_ ( prog_clk , chany_bottom_in , bottom_right_grid_pin_1_ , - bottom_left_grid_pin_42_ , bottom_left_grid_pin_43_ , - bottom_left_grid_pin_44_ , bottom_left_grid_pin_45_ , - bottom_left_grid_pin_46_ , bottom_left_grid_pin_47_ , - bottom_left_grid_pin_48_ , bottom_left_grid_pin_49_ , chanx_left_in , - left_top_grid_pin_1_ , left_bottom_grid_pin_34_ , - left_bottom_grid_pin_35_ , left_bottom_grid_pin_36_ , - left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , - left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , - left_bottom_grid_pin_41_ , ccff_head , chany_bottom_out , chanx_left_out , - ccff_tail , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , SC_OUT_BOT ) ; -input [0:0] prog_clk ; -input [0:19] chany_bottom_in ; -input [0:0] bottom_right_grid_pin_1_ ; -input [0:0] bottom_left_grid_pin_42_ ; -input [0:0] bottom_left_grid_pin_43_ ; -input [0:0] bottom_left_grid_pin_44_ ; -input [0:0] bottom_left_grid_pin_45_ ; -input [0:0] bottom_left_grid_pin_46_ ; -input [0:0] bottom_left_grid_pin_47_ ; -input [0:0] bottom_left_grid_pin_48_ ; -input [0:0] bottom_left_grid_pin_49_ ; -input [0:19] chanx_left_in ; -input [0:0] left_top_grid_pin_1_ ; -input [0:0] left_bottom_grid_pin_34_ ; -input [0:0] left_bottom_grid_pin_35_ ; -input [0:0] left_bottom_grid_pin_36_ ; -input [0:0] left_bottom_grid_pin_37_ ; -input [0:0] left_bottom_grid_pin_38_ ; -input [0:0] left_bottom_grid_pin_39_ ; -input [0:0] left_bottom_grid_pin_40_ ; -input [0:0] left_bottom_grid_pin_41_ ; -input [0:0] ccff_head ; -output [0:19] chany_bottom_out ; -output [0:19] chanx_left_out ; -output [0:0] ccff_tail ; -input SC_IN_TOP ; -input SC_IN_BOT ; -output SC_OUT_TOP ; -output SC_OUT_BOT ; - -wire [0:1] mux_bottom_track_11_undriven_sram_inv ; -wire [0:1] mux_bottom_track_13_undriven_sram_inv ; -wire [0:1] mux_bottom_track_15_undriven_sram_inv ; -wire [0:1] mux_bottom_track_17_undriven_sram_inv ; -wire [0:1] mux_bottom_track_19_undriven_sram_inv ; -wire [0:2] mux_bottom_track_1_undriven_sram_inv ; -wire [0:1] mux_bottom_track_21_undriven_sram_inv ; -wire [0:1] mux_bottom_track_23_undriven_sram_inv ; -wire [0:1] mux_bottom_track_25_undriven_sram_inv ; -wire [0:1] mux_bottom_track_27_undriven_sram_inv ; -wire [0:1] mux_bottom_track_29_undriven_sram_inv ; -wire [0:2] mux_bottom_track_3_undriven_sram_inv ; -wire [0:2] mux_bottom_track_5_undriven_sram_inv ; -wire [0:2] mux_bottom_track_7_undriven_sram_inv ; -wire [0:1] mux_bottom_track_9_undriven_sram_inv ; -wire [0:1] mux_left_track_11_undriven_sram_inv ; -wire [0:1] mux_left_track_13_undriven_sram_inv ; -wire [0:1] mux_left_track_15_undriven_sram_inv ; -wire [0:1] mux_left_track_17_undriven_sram_inv ; -wire [0:1] mux_left_track_19_undriven_sram_inv ; -wire [0:2] mux_left_track_1_undriven_sram_inv ; -wire [0:1] mux_left_track_21_undriven_sram_inv ; -wire [0:1] mux_left_track_23_undriven_sram_inv ; -wire [0:1] mux_left_track_25_undriven_sram_inv ; -wire [0:1] mux_left_track_27_undriven_sram_inv ; -wire [0:1] mux_left_track_29_undriven_sram_inv ; -wire [0:1] mux_left_track_31_undriven_sram_inv ; -wire [0:1] mux_left_track_33_undriven_sram_inv ; -wire [0:1] mux_left_track_35_undriven_sram_inv ; -wire [0:1] mux_left_track_37_undriven_sram_inv ; -wire [0:1] mux_left_track_39_undriven_sram_inv ; -wire [0:2] mux_left_track_3_undriven_sram_inv ; -wire [0:2] mux_left_track_5_undriven_sram_inv ; -wire [0:2] mux_left_track_7_undriven_sram_inv ; -wire [0:1] mux_left_track_9_undriven_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_10_sram ; -wire [0:1] mux_tree_tapbuf_size2_11_sram ; -wire [0:1] mux_tree_tapbuf_size2_12_sram ; -wire [0:1] mux_tree_tapbuf_size2_13_sram ; -wire [0:1] mux_tree_tapbuf_size2_14_sram ; -wire [0:1] mux_tree_tapbuf_size2_15_sram ; -wire [0:1] mux_tree_tapbuf_size2_16_sram ; -wire [0:1] mux_tree_tapbuf_size2_17_sram ; -wire [0:1] mux_tree_tapbuf_size2_18_sram ; -wire [0:1] mux_tree_tapbuf_size2_19_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_20_sram ; -wire [0:1] mux_tree_tapbuf_size2_21_sram ; -wire [0:1] mux_tree_tapbuf_size2_22_sram ; -wire [0:1] mux_tree_tapbuf_size2_23_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_5_sram ; -wire [0:1] mux_tree_tapbuf_size2_6_sram ; -wire [0:1] mux_tree_tapbuf_size2_7_sram ; -wire [0:1] mux_tree_tapbuf_size2_8_sram ; -wire [0:1] mux_tree_tapbuf_size2_9_sram ; -wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_19_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_20_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_21_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_22_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; -wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:1] mux_tree_tapbuf_size3_2_sram ; -wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size5_0_sram ; -wire [0:2] mux_tree_tapbuf_size5_1_sram ; -wire [0:2] mux_tree_tapbuf_size5_2_sram ; -wire [0:2] mux_tree_tapbuf_size5_3_sram ; -wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size6_1_sram ; -wire [0:2] mux_tree_tapbuf_size6_2_sram ; -wire [0:2] mux_tree_tapbuf_size6_3_sram ; -wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ; - -assign SC_IN_TOP = SC_IN_BOT ; - -sb_2__2__mux_tree_tapbuf_size6_0 mux_bottom_track_1 ( - .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_43_[0] , - bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , - bottom_left_grid_pin_49_[0] , chanx_left_in[1] } ) , - .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_bottom_track_1_undriven_sram_inv ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_82 ) ) ; -sb_2__2__mux_tree_tapbuf_size6_1 mux_bottom_track_5 ( - .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_43_[0] , - bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , - bottom_left_grid_pin_49_[0] , chanx_left_in[3] } ) , - .sram ( mux_tree_tapbuf_size6_1_sram ) , - .sram_inv ( mux_bottom_track_5_undriven_sram_inv ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_84 ) ) ; -sb_2__2__mux_tree_tapbuf_size6_2 mux_left_track_1 ( - .in ( { chany_bottom_in[19] , left_top_grid_pin_1_[0] , - left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , - left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , - .sram ( mux_tree_tapbuf_size6_2_sram ) , - .sram_inv ( mux_left_track_1_undriven_sram_inv ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_83 ) ) ; -sb_2__2__mux_tree_tapbuf_size6 mux_left_track_5 ( - .in ( { chany_bottom_in[1] , left_top_grid_pin_1_[0] , - left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , - left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , - .sram ( mux_tree_tapbuf_size6_3_sram ) , - .sram_inv ( mux_left_track_5_undriven_sram_inv ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_83 ) ) ; -sb_2__2__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_1 ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size6_mem_1 mem_bottom_track_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size6_mem_2 mem_left_track_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_2_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size6_mem mem_left_track_5 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_3_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size5_0 mux_bottom_track_3 ( - .in ( { bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , - bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , - chanx_left_in[2] } ) , - .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_bottom_track_3_undriven_sram_inv ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_82 ) ) ; -sb_2__2__mux_tree_tapbuf_size5_1 mux_bottom_track_7 ( - .in ( { bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , - bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , - chanx_left_in[4] } ) , - .sram ( mux_tree_tapbuf_size5_1_sram ) , - .sram_inv ( mux_bottom_track_7_undriven_sram_inv ) , - .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_84 ) ) ; -sb_2__2__mux_tree_tapbuf_size5_2 mux_left_track_3 ( - .in ( { chany_bottom_in[0] , left_bottom_grid_pin_34_[0] , - left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , - left_bottom_grid_pin_40_[0] } ) , - .sram ( mux_tree_tapbuf_size5_2_sram ) , - .sram_inv ( mux_left_track_3_undriven_sram_inv ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_82 ) ) ; -sb_2__2__mux_tree_tapbuf_size5 mux_left_track_7 ( - .in ( { chany_bottom_in[2] , left_bottom_grid_pin_34_[0] , - left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , - left_bottom_grid_pin_40_[0] } ) , - .sram ( mux_tree_tapbuf_size5_3_sram ) , - .sram_inv ( mux_left_track_7_undriven_sram_inv ) , - .out ( chanx_left_out[3] ) , .p0 ( optlc_net_82 ) ) ; -sb_2__2__mux_tree_tapbuf_size5_mem_0 mem_bottom_track_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size5_mem_1 mem_bottom_track_7 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size5_mem_2 mem_left_track_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_2_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size5_mem mem_left_track_7 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_3_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_9 mux_bottom_track_9 ( - .in ( { bottom_right_grid_pin_1_[0] , chanx_left_in[5] } ) , - .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_bottom_track_9_undriven_sram_inv ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_84 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_0 mux_bottom_track_11 ( - .in ( { bottom_left_grid_pin_42_[0] , chanx_left_in[6] } ) , - .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_bottom_track_11_undriven_sram_inv ) , - .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_84 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_1 mux_bottom_track_13 ( - .in ( { bottom_left_grid_pin_43_[0] , chanx_left_in[7] } ) , - .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_bottom_track_13_undriven_sram_inv ) , - .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_81 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_2 mux_bottom_track_15 ( - .in ( { bottom_left_grid_pin_44_[0] , chanx_left_in[8] } ) , - .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_bottom_track_15_undriven_sram_inv ) , - .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_81 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_3 mux_bottom_track_17 ( - .in ( { bottom_left_grid_pin_45_[0] , chanx_left_in[9] } ) , - .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_bottom_track_17_undriven_sram_inv ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_81 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_4 mux_bottom_track_19 ( - .in ( { bottom_left_grid_pin_46_[0] , chanx_left_in[10] } ) , - .sram ( mux_tree_tapbuf_size2_5_sram ) , - .sram_inv ( mux_bottom_track_19_undriven_sram_inv ) , - .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_84 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_5 mux_bottom_track_21 ( - .in ( { bottom_left_grid_pin_47_[0] , chanx_left_in[11] } ) , - .sram ( mux_tree_tapbuf_size2_6_sram ) , - .sram_inv ( mux_bottom_track_21_undriven_sram_inv ) , - .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_81 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_6 mux_bottom_track_23 ( - .in ( { bottom_left_grid_pin_48_[0] , chanx_left_in[12] } ) , - .sram ( mux_tree_tapbuf_size2_7_sram ) , - .sram_inv ( mux_bottom_track_23_undriven_sram_inv ) , - .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_84 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_7 mux_bottom_track_27 ( - .in ( { bottom_left_grid_pin_42_[0] , chanx_left_in[14] } ) , - .sram ( mux_tree_tapbuf_size2_8_sram ) , - .sram_inv ( mux_bottom_track_27_undriven_sram_inv ) , - .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_84 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_8 mux_bottom_track_29 ( - .in ( { bottom_left_grid_pin_43_[0] , chanx_left_in[15] } ) , - .sram ( mux_tree_tapbuf_size2_9_sram ) , - .sram_inv ( mux_bottom_track_29_undriven_sram_inv ) , - .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_81 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_10 mux_left_track_11 ( - .in ( { chany_bottom_in[4] , left_bottom_grid_pin_34_[0] } ) , - .sram ( mux_tree_tapbuf_size2_10_sram ) , - .sram_inv ( mux_left_track_11_undriven_sram_inv ) , - .out ( chanx_left_out[5] ) , .p0 ( optlc_net_82 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_11 mux_left_track_13 ( - .in ( { chany_bottom_in[5] , left_bottom_grid_pin_35_[0] } ) , - .sram ( mux_tree_tapbuf_size2_11_sram ) , - .sram_inv ( mux_left_track_13_undriven_sram_inv ) , - .out ( chanx_left_out[6] ) , .p0 ( optlc_net_83 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_12 mux_left_track_15 ( - .in ( { chany_bottom_in[6] , left_bottom_grid_pin_36_[0] } ) , - .sram ( mux_tree_tapbuf_size2_12_sram ) , - .sram_inv ( mux_left_track_15_undriven_sram_inv ) , - .out ( chanx_left_out[7] ) , .p0 ( optlc_net_83 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_13 mux_left_track_17 ( - .in ( { chany_bottom_in[7] , left_bottom_grid_pin_37_[0] } ) , - .sram ( mux_tree_tapbuf_size2_13_sram ) , - .sram_inv ( mux_left_track_17_undriven_sram_inv ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_83 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_14 mux_left_track_19 ( - .in ( { chany_bottom_in[8] , left_bottom_grid_pin_38_[0] } ) , - .sram ( mux_tree_tapbuf_size2_14_sram ) , - .sram_inv ( mux_left_track_19_undriven_sram_inv ) , - .out ( chanx_left_out[9] ) , .p0 ( optlc_net_83 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_15 mux_left_track_21 ( - .in ( { chany_bottom_in[9] , left_bottom_grid_pin_39_[0] } ) , - .sram ( mux_tree_tapbuf_size2_15_sram ) , - .sram_inv ( mux_left_track_21_undriven_sram_inv ) , - .out ( chanx_left_out[10] ) , .p0 ( optlc_net_82 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_16 mux_left_track_23 ( - .in ( { chany_bottom_in[10] , left_bottom_grid_pin_40_[0] } ) , - .sram ( mux_tree_tapbuf_size2_16_sram ) , - .sram_inv ( mux_left_track_23_undriven_sram_inv ) , - .out ( chanx_left_out[11] ) , .p0 ( optlc_net_82 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_17 mux_left_track_27 ( - .in ( { chany_bottom_in[12] , left_bottom_grid_pin_34_[0] } ) , - .sram ( mux_tree_tapbuf_size2_17_sram ) , - .sram_inv ( mux_left_track_27_undriven_sram_inv ) , - .out ( chanx_left_out[13] ) , .p0 ( optlc_net_82 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_18 mux_left_track_29 ( - .in ( { chany_bottom_in[13] , left_bottom_grid_pin_35_[0] } ) , - .sram ( mux_tree_tapbuf_size2_18_sram ) , - .sram_inv ( mux_left_track_29_undriven_sram_inv ) , - .out ( chanx_left_out[14] ) , .p0 ( optlc_net_82 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_19 mux_left_track_31 ( - .in ( { chany_bottom_in[14] , left_bottom_grid_pin_36_[0] } ) , - .sram ( mux_tree_tapbuf_size2_19_sram ) , - .sram_inv ( mux_left_track_31_undriven_sram_inv ) , - .out ( chanx_left_out[15] ) , .p0 ( optlc_net_83 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_20 mux_left_track_33 ( - .in ( { chany_bottom_in[15] , left_bottom_grid_pin_37_[0] } ) , - .sram ( mux_tree_tapbuf_size2_20_sram ) , - .sram_inv ( mux_left_track_33_undriven_sram_inv ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_83 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_21 mux_left_track_35 ( - .in ( { chany_bottom_in[16] , left_bottom_grid_pin_38_[0] } ) , - .sram ( mux_tree_tapbuf_size2_21_sram ) , - .sram_inv ( mux_left_track_35_undriven_sram_inv ) , - .out ( chanx_left_out[17] ) , .p0 ( optlc_net_81 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_22 mux_left_track_37 ( - .in ( { chany_bottom_in[17] , left_bottom_grid_pin_39_[0] } ) , - .sram ( mux_tree_tapbuf_size2_22_sram ) , - .sram_inv ( mux_left_track_37_undriven_sram_inv ) , - .out ( chanx_left_out[18] ) , .p0 ( optlc_net_83 ) ) ; -sb_2__2__mux_tree_tapbuf_size2 mux_left_track_39 ( - .in ( { chany_bottom_in[18] , left_bottom_grid_pin_40_[0] } ) , - .sram ( mux_tree_tapbuf_size2_23_sram ) , - .sram_inv ( mux_left_track_39_undriven_sram_inv ) , - .out ( chanx_left_out[19] ) , .p0 ( optlc_net_82 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_9 mem_bottom_track_9 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_0 mem_bottom_track_11 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_1 mem_bottom_track_13 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_2 mem_bottom_track_15 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_3 mem_bottom_track_17 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_4 mem_bottom_track_19 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_5 mem_bottom_track_21 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_6 mem_bottom_track_23 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_7 mem_bottom_track_27 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_8 mem_bottom_track_29 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_10 mem_left_track_11 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_11 mem_left_track_13 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_11_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_12 mem_left_track_15 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_12_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_13 mem_left_track_17 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_13_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_14 mem_left_track_19 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_14_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_15 mem_left_track_21 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_15_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_16 mem_left_track_23 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_16_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_17 mem_left_track_27 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_17_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_18 mem_left_track_29 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_18_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_19 mem_left_track_31 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_19_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_20 mem_left_track_33 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_20_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_21 mem_left_track_35 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_21_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_22 mem_left_track_37 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_22_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem mem_left_track_39 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , - .ccff_tail ( { ropt_net_91 } ) , - .mem_out ( mux_tree_tapbuf_size2_23_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size3_0 mux_bottom_track_25 ( - .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_49_[0] , - chanx_left_in[13] } ) , - .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_bottom_track_25_undriven_sram_inv ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_84 ) ) ; -sb_2__2__mux_tree_tapbuf_size3 mux_left_track_9 ( - .in ( { chany_bottom_in[3] , left_top_grid_pin_1_[0] , - left_bottom_grid_pin_41_[0] } ) , - .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_left_track_9_undriven_sram_inv ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_82 ) ) ; -sb_2__2__mux_tree_tapbuf_size3_1 mux_left_track_25 ( - .in ( { chany_bottom_in[11] , left_top_grid_pin_1_[0] , - left_bottom_grid_pin_41_[0] } ) , - .sram ( mux_tree_tapbuf_size3_2_sram ) , - .sram_inv ( mux_left_track_25_undriven_sram_inv ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_82 ) ) ; -sb_2__2__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_25 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size3_mem mem_left_track_9 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size3_mem_1 mem_left_track_25 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_688 ( .A ( ropt_net_94 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_689 ( .A ( ropt_net_95 ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_690 ( .A ( ropt_net_96 ) , - .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__conb_1 optlc_72 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_81 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__4 ( .A ( chanx_left_in[19] ) , - .X ( ropt_net_92 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_6__5 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_86 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_691 ( .A ( ropt_net_97 ) , - .X ( chany_bottom_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_692 ( .A ( ropt_net_98 ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_693 ( .A ( ropt_net_99 ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_694 ( .A ( ropt_net_100 ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_74 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_82 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_76 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_83 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_78 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_84 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_681 ( .A ( ropt_net_86 ) , - .X ( ropt_net_96 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_682 ( .A ( chanx_left_in[0] ) , - .X ( ropt_net_98 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_683 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_100 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_684 ( .A ( chanx_left_in[16] ) , - .X ( ropt_net_99 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_685 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_97 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_686 ( .A ( ropt_net_91 ) , - .X ( ropt_net_94 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_687 ( .A ( ropt_net_92 ) , - .X ( ropt_net_95 ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__60 ( .A ( mem_out[1] ) , - .X ( net_net_79 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_78 ( .A ( net_net_79 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__59 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__58 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__57 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__56 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__55 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__54 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__53 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__52 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__51 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__50 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_67 ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__49 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__48 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__47 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__46 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_65 ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( BUF_net_65 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_107 ( .A ( BUF_net_65 ) , - .X ( out[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size9_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__45 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , p0 ) ; -input [0:8] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_106 ( - .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__44 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__43 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__42 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__41 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__40 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__39 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__38 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__37 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__36 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__35 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size14_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__34 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size14_mem ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__33 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size14_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:13] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size14 ( in , sram , sram_inv , out , p0 ) ; -input [0:13] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__32 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__31 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__30 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__29 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__28 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module sb_2__1_ ( prog_clk , chany_top_in , top_left_grid_pin_42_ , - top_left_grid_pin_43_ , top_left_grid_pin_44_ , top_left_grid_pin_45_ , - top_left_grid_pin_46_ , top_left_grid_pin_47_ , top_left_grid_pin_48_ , - top_left_grid_pin_49_ , top_right_grid_pin_1_ , chany_bottom_in , - bottom_right_grid_pin_1_ , bottom_left_grid_pin_42_ , - bottom_left_grid_pin_43_ , bottom_left_grid_pin_44_ , - bottom_left_grid_pin_45_ , bottom_left_grid_pin_46_ , - bottom_left_grid_pin_47_ , bottom_left_grid_pin_48_ , - bottom_left_grid_pin_49_ , chanx_left_in , left_bottom_grid_pin_34_ , - left_bottom_grid_pin_35_ , left_bottom_grid_pin_36_ , - left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , - left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , - left_bottom_grid_pin_41_ , ccff_head , chany_top_out , chany_bottom_out , - chanx_left_out , ccff_tail , Test_en__FEEDTHRU_0 , Test_en__FEEDTHRU_1 , - clk__FEEDTHRU_0 , clk__FEEDTHRU_1 ) ; -input [0:0] prog_clk ; -input [0:19] chany_top_in ; -input [0:0] top_left_grid_pin_42_ ; -input [0:0] top_left_grid_pin_43_ ; -input [0:0] top_left_grid_pin_44_ ; -input [0:0] top_left_grid_pin_45_ ; -input [0:0] top_left_grid_pin_46_ ; -input [0:0] top_left_grid_pin_47_ ; -input [0:0] top_left_grid_pin_48_ ; -input [0:0] top_left_grid_pin_49_ ; -input [0:0] top_right_grid_pin_1_ ; -input [0:19] chany_bottom_in ; -input [0:0] bottom_right_grid_pin_1_ ; -input [0:0] bottom_left_grid_pin_42_ ; -input [0:0] bottom_left_grid_pin_43_ ; -input [0:0] bottom_left_grid_pin_44_ ; -input [0:0] bottom_left_grid_pin_45_ ; -input [0:0] bottom_left_grid_pin_46_ ; -input [0:0] bottom_left_grid_pin_47_ ; -input [0:0] bottom_left_grid_pin_48_ ; -input [0:0] bottom_left_grid_pin_49_ ; -input [0:19] chanx_left_in ; -input [0:0] left_bottom_grid_pin_34_ ; -input [0:0] left_bottom_grid_pin_35_ ; -input [0:0] left_bottom_grid_pin_36_ ; -input [0:0] left_bottom_grid_pin_37_ ; -input [0:0] left_bottom_grid_pin_38_ ; -input [0:0] left_bottom_grid_pin_39_ ; -input [0:0] left_bottom_grid_pin_40_ ; -input [0:0] left_bottom_grid_pin_41_ ; -input [0:0] ccff_head ; -output [0:19] chany_top_out ; -output [0:19] chany_bottom_out ; -output [0:19] chanx_left_out ; -output [0:0] ccff_tail ; -input [0:0] Test_en__FEEDTHRU_0 ; -output [0:0] Test_en__FEEDTHRU_1 ; -input [0:0] clk__FEEDTHRU_0 ; -output [0:0] clk__FEEDTHRU_1 ; - -wire [0:2] mux_bottom_track_17_undriven_sram_inv ; -wire [0:3] mux_bottom_track_1_undriven_sram_inv ; -wire [0:2] mux_bottom_track_25_undriven_sram_inv ; -wire [0:2] mux_bottom_track_33_undriven_sram_inv ; -wire [0:3] mux_bottom_track_3_undriven_sram_inv ; -wire [0:3] mux_bottom_track_5_undriven_sram_inv ; -wire [0:3] mux_bottom_track_9_undriven_sram_inv ; -wire [0:2] mux_left_track_11_undriven_sram_inv ; -wire [0:2] mux_left_track_13_undriven_sram_inv ; -wire [0:2] mux_left_track_15_undriven_sram_inv ; -wire [0:1] mux_left_track_17_undriven_sram_inv ; -wire [0:1] mux_left_track_19_undriven_sram_inv ; -wire [0:2] mux_left_track_1_undriven_sram_inv ; -wire [0:1] mux_left_track_21_undriven_sram_inv ; -wire [0:1] mux_left_track_23_undriven_sram_inv ; -wire [0:1] mux_left_track_25_undriven_sram_inv ; -wire [0:1] mux_left_track_29_undriven_sram_inv ; -wire [0:1] mux_left_track_31_undriven_sram_inv ; -wire [0:1] mux_left_track_33_undriven_sram_inv ; -wire [0:1] mux_left_track_35_undriven_sram_inv ; -wire [0:1] mux_left_track_37_undriven_sram_inv ; -wire [0:1] mux_left_track_39_undriven_sram_inv ; -wire [0:2] mux_left_track_3_undriven_sram_inv ; -wire [0:2] mux_left_track_5_undriven_sram_inv ; -wire [0:2] mux_left_track_7_undriven_sram_inv ; -wire [0:2] mux_left_track_9_undriven_sram_inv ; -wire [0:3] mux_top_track_0_undriven_sram_inv ; -wire [0:2] mux_top_track_16_undriven_sram_inv ; -wire [0:2] mux_top_track_24_undriven_sram_inv ; -wire [0:3] mux_top_track_2_undriven_sram_inv ; -wire [0:2] mux_top_track_32_undriven_sram_inv ; -wire [0:3] mux_top_track_4_undriven_sram_inv ; -wire [0:3] mux_top_track_8_undriven_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size14_0_sram ; -wire [0:3] mux_tree_tapbuf_size14_1_sram ; -wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail ; -wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_5_sram ; -wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; -wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:1] mux_tree_tapbuf_size3_2_sram ; -wire [0:1] mux_tree_tapbuf_size3_3_sram ; -wire [0:1] mux_tree_tapbuf_size3_4_sram ; -wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size4_0_sram ; -wire [0:2] mux_tree_tapbuf_size4_1_sram ; -wire [0:2] mux_tree_tapbuf_size4_2_sram ; -wire [0:2] mux_tree_tapbuf_size4_3_sram ; -wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size6_1_sram ; -wire [0:2] mux_tree_tapbuf_size6_2_sram ; -wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size7_0_sram ; -wire [0:2] mux_tree_tapbuf_size7_1_sram ; -wire [0:2] mux_tree_tapbuf_size7_2_sram ; -wire [0:2] mux_tree_tapbuf_size7_3_sram ; -wire [0:2] mux_tree_tapbuf_size7_4_sram ; -wire [0:2] mux_tree_tapbuf_size7_5_sram ; -wire [0:2] mux_tree_tapbuf_size7_6_sram ; -wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:3] mux_tree_tapbuf_size8_2_sram ; -wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size9_0_sram ; -wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ; - -assign clk__FEEDTHRU_1[0] = clk__FEEDTHRU_0[0] ; - -sb_2__1__mux_tree_tapbuf_size10 mux_top_track_0 ( - .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , - top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , - top_right_grid_pin_1_[0] , chany_bottom_in[2] , chany_bottom_in[12] , - chanx_left_in[0] , chanx_left_in[7] , chanx_left_in[14] } ) , - .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_top_track_0_undriven_sram_inv ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_126 ) ) ; -sb_2__1__mux_tree_tapbuf_size10_0 mux_bottom_track_1 ( - .in ( { chany_top_in[2] , chany_top_in[12] , bottom_right_grid_pin_1_[0] , - bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , - bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , - chanx_left_in[1] , chanx_left_in[8] , chanx_left_in[15] } ) , - .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_bottom_track_1_undriven_sram_inv ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_126 ) ) ; -sb_2__1__mux_tree_tapbuf_size10_mem mem_top_track_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size10_mem_0 mem_bottom_track_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size8_1 mux_top_track_2 ( - .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , - top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , - chany_bottom_in[4] , chany_bottom_in[13] , chanx_left_in[6] , - chanx_left_in[13] } ) , - .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_top_track_2_undriven_sram_inv ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_127 ) ) ; -sb_2__1__mux_tree_tapbuf_size8 mux_top_track_8 ( - .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_46_[0] , - top_right_grid_pin_1_[0] , chany_bottom_in[6] , chany_bottom_in[16] , - chanx_left_in[4] , chanx_left_in[11] , chanx_left_in[18] } ) , - .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_top_track_8_undriven_sram_inv ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_127 ) ) ; -sb_2__1__mux_tree_tapbuf_size8_0 mux_bottom_track_9 ( - .in ( { chany_top_in[6] , chany_top_in[16] , bottom_right_grid_pin_1_[0] , - bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_49_[0] , - chanx_left_in[4] , chanx_left_in[11] , chanx_left_in[18] } ) , - .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_bottom_track_9_undriven_sram_inv ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_125 ) ) ; -sb_2__1__mux_tree_tapbuf_size8_mem_1 mem_top_track_2 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size8_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size8_mem_0 mem_bottom_track_9 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size14 mux_top_track_4 ( - .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_43_[0] , - top_left_grid_pin_44_[0] , top_left_grid_pin_45_[0] , - top_left_grid_pin_46_[0] , top_left_grid_pin_47_[0] , - top_left_grid_pin_48_[0] , top_left_grid_pin_49_[0] , - top_right_grid_pin_1_[0] , chany_bottom_in[5] , chany_bottom_in[14] , - chanx_left_in[5] , chanx_left_in[12] , chanx_left_in[19] } ) , - .sram ( mux_tree_tapbuf_size14_0_sram ) , - .sram_inv ( mux_top_track_4_undriven_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_127 ) ) ; -sb_2__1__mux_tree_tapbuf_size14_0 mux_bottom_track_5 ( - .in ( { chany_top_in[5] , chany_top_in[14] , bottom_right_grid_pin_1_[0] , - bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_43_[0] , - bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_45_[0] , - bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_47_[0] , - bottom_left_grid_pin_48_[0] , bottom_left_grid_pin_49_[0] , - chanx_left_in[3] , chanx_left_in[10] , chanx_left_in[17] } ) , - .sram ( mux_tree_tapbuf_size14_1_sram ) , - .sram_inv ( mux_bottom_track_5_undriven_sram_inv ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_125 ) ) ; -sb_2__1__mux_tree_tapbuf_size14_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size14_0_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size14_mem_0 mem_bottom_track_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size14_1_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size7_5 mux_top_track_16 ( - .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_47_[0] , - chany_bottom_in[8] , chany_bottom_in[17] , chanx_left_in[3] , - chanx_left_in[10] , chanx_left_in[17] } ) , - .sram ( mux_tree_tapbuf_size7_0_sram ) , - .sram_inv ( mux_top_track_16_undriven_sram_inv ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_126 ) ) ; -sb_2__1__mux_tree_tapbuf_size7 mux_top_track_24 ( - .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_48_[0] , - chany_bottom_in[9] , chany_bottom_in[18] , chanx_left_in[2] , - chanx_left_in[9] , chanx_left_in[16] } ) , - .sram ( mux_tree_tapbuf_size7_1_sram ) , - .sram_inv ( mux_top_track_24_undriven_sram_inv ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_126 ) ) ; -sb_2__1__mux_tree_tapbuf_size7_0 mux_bottom_track_17 ( - .in ( { chany_top_in[8] , chany_top_in[17] , bottom_left_grid_pin_42_[0] , - bottom_left_grid_pin_46_[0] , chanx_left_in[5] , chanx_left_in[12] , - chanx_left_in[19] } ) , - .sram ( mux_tree_tapbuf_size7_2_sram ) , - .sram_inv ( mux_bottom_track_17_undriven_sram_inv ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_126 ) ) ; -sb_2__1__mux_tree_tapbuf_size7_1 mux_left_track_1 ( - .in ( { chany_top_in[0] , chany_top_in[2] , chany_bottom_in[2] , - left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , - left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , - .sram ( mux_tree_tapbuf_size7_3_sram ) , - .sram_inv ( mux_left_track_1_undriven_sram_inv ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_128 ) ) ; -sb_2__1__mux_tree_tapbuf_size7_2 mux_left_track_3 ( - .in ( { chany_top_in[4] , chany_bottom_in[0] , chany_bottom_in[4] , - left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , - left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , - .sram ( mux_tree_tapbuf_size7_4_sram ) , - .sram_inv ( mux_left_track_3_undriven_sram_inv ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_128 ) ) ; -sb_2__1__mux_tree_tapbuf_size7_3 mux_left_track_5 ( - .in ( { chany_top_in[5] , chany_bottom_in[1] , chany_bottom_in[5] , - left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , - left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , - .sram ( mux_tree_tapbuf_size7_5_sram ) , - .sram_inv ( mux_left_track_5_undriven_sram_inv ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_128 ) ) ; -sb_2__1__mux_tree_tapbuf_size7_4 mux_left_track_7 ( - .in ( { chany_top_in[6] , chany_bottom_in[3] , chany_bottom_in[6] , - left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , - left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , - .sram ( mux_tree_tapbuf_size7_6_sram ) , - .sram_inv ( mux_left_track_7_undriven_sram_inv ) , - .out ( chanx_left_out[3] ) , .p0 ( optlc_net_128 ) ) ; -sb_2__1__mux_tree_tapbuf_size7_mem_5 mem_top_track_16 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size7_mem mem_top_track_24 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size7_mem_0 mem_bottom_track_17 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size7_mem_1 mem_left_track_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_3_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size7_mem_2 mem_left_track_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_4_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size7_mem_3 mem_left_track_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_5_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size7_mem_4 mem_left_track_7 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_6_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size6 mux_top_track_32 ( - .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_49_[0] , - chany_bottom_in[10] , chanx_left_in[1] , chanx_left_in[8] , - chanx_left_in[15] } ) , - .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_top_track_32_undriven_sram_inv ) , - .out ( chany_top_out[16] ) , .p0 ( optlc_net_126 ) ) ; -sb_2__1__mux_tree_tapbuf_size6_0 mux_bottom_track_25 ( - .in ( { chany_top_in[9] , chany_top_in[18] , bottom_left_grid_pin_43_[0] , - bottom_left_grid_pin_47_[0] , chanx_left_in[6] , chanx_left_in[13] } ) , - .sram ( mux_tree_tapbuf_size6_1_sram ) , - .sram_inv ( mux_bottom_track_25_undriven_sram_inv ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_125 ) ) ; -sb_2__1__mux_tree_tapbuf_size6_1 mux_bottom_track_33 ( - .in ( { chany_top_in[10] , bottom_left_grid_pin_44_[0] , - bottom_left_grid_pin_48_[0] , chanx_left_in[0] , chanx_left_in[7] , - chanx_left_in[14] } ) , - .sram ( mux_tree_tapbuf_size6_2_sram ) , - .sram_inv ( mux_bottom_track_33_undriven_sram_inv ) , - .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_126 ) ) ; -sb_2__1__mux_tree_tapbuf_size6_mem mem_top_track_32 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_25 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size6_mem_1 mem_bottom_track_33 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_2_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size9 mux_bottom_track_3 ( - .in ( { chany_top_in[4] , chany_top_in[13] , bottom_left_grid_pin_42_[0] , - bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , - bottom_left_grid_pin_48_[0] , chanx_left_in[2] , chanx_left_in[9] , - chanx_left_in[16] } ) , - .sram ( mux_tree_tapbuf_size9_0_sram ) , - .sram_inv ( mux_bottom_track_3_undriven_sram_inv ) , - .out ( { ropt_net_132 } ) , - .p0 ( optlc_net_125 ) ) ; -sb_2__1__mux_tree_tapbuf_size9_mem mem_bottom_track_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size9_0_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size4 mux_left_track_9 ( - .in ( { chany_top_in[8] , chany_bottom_in[7] , chany_bottom_in[8] , - left_bottom_grid_pin_34_[0] } ) , - .sram ( mux_tree_tapbuf_size4_0_sram ) , - .sram_inv ( mux_left_track_9_undriven_sram_inv ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_128 ) ) ; -sb_2__1__mux_tree_tapbuf_size4_0 mux_left_track_11 ( - .in ( { chany_top_in[9] , chany_bottom_in[9] , chany_bottom_in[11] , - left_bottom_grid_pin_35_[0] } ) , - .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_left_track_11_undriven_sram_inv ) , - .out ( chanx_left_out[5] ) , .p0 ( optlc_net_128 ) ) ; -sb_2__1__mux_tree_tapbuf_size4_1 mux_left_track_13 ( - .in ( { chany_top_in[10] , chany_bottom_in[10] , chany_bottom_in[15] , - left_bottom_grid_pin_36_[0] } ) , - .sram ( mux_tree_tapbuf_size4_2_sram ) , - .sram_inv ( mux_left_track_13_undriven_sram_inv ) , - .out ( { ropt_net_130 } ) , - .p0 ( optlc_net_125 ) ) ; -sb_2__1__mux_tree_tapbuf_size4_2 mux_left_track_15 ( - .in ( { chany_top_in[12] , chany_bottom_in[12] , chany_bottom_in[19] , - left_bottom_grid_pin_37_[0] } ) , - .sram ( mux_tree_tapbuf_size4_3_sram ) , - .sram_inv ( mux_left_track_15_undriven_sram_inv ) , - .out ( chanx_left_out[7] ) , .p0 ( optlc_net_125 ) ) ; -sb_2__1__mux_tree_tapbuf_size4_mem mem_left_track_9 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size4_mem_0 mem_left_track_11 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size4_mem_1 mem_left_track_13 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size4_mem_2 mem_left_track_15 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size3_0 mux_left_track_17 ( - .in ( { chany_top_in[13] , chany_bottom_in[13] , - left_bottom_grid_pin_38_[0] } ) , - .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_left_track_17_undriven_sram_inv ) , - .out ( { ropt_net_131 } ) , - .p0 ( optlc_net_125 ) ) ; -sb_2__1__mux_tree_tapbuf_size3_1 mux_left_track_19 ( - .in ( { chany_top_in[14] , chany_bottom_in[14] , - left_bottom_grid_pin_39_[0] } ) , - .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_left_track_19_undriven_sram_inv ) , - .out ( chanx_left_out[9] ) , .p0 ( optlc_net_127 ) ) ; -sb_2__1__mux_tree_tapbuf_size3_2 mux_left_track_21 ( - .in ( { chany_top_in[16] , chany_bottom_in[16] , - left_bottom_grid_pin_40_[0] } ) , - .sram ( mux_tree_tapbuf_size3_2_sram ) , - .sram_inv ( mux_left_track_21_undriven_sram_inv ) , - .out ( chanx_left_out[10] ) , .p0 ( optlc_net_128 ) ) ; -sb_2__1__mux_tree_tapbuf_size3_3 mux_left_track_23 ( - .in ( { chany_top_in[17] , chany_bottom_in[17] , - left_bottom_grid_pin_41_[0] } ) , - .sram ( mux_tree_tapbuf_size3_3_sram ) , - .sram_inv ( mux_left_track_23_undriven_sram_inv ) , - .out ( chanx_left_out[11] ) , .p0 ( optlc_net_127 ) ) ; -sb_2__1__mux_tree_tapbuf_size3 mux_left_track_25 ( - .in ( { chany_top_in[18] , chany_bottom_in[18] , - left_bottom_grid_pin_34_[0] } ) , - .sram ( mux_tree_tapbuf_size3_4_sram ) , - .sram_inv ( mux_left_track_25_undriven_sram_inv ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_128 ) ) ; -sb_2__1__mux_tree_tapbuf_size3_mem_0 mem_left_track_17 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size3_mem_1 mem_left_track_19 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size3_mem_2 mem_left_track_21 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size3_mem_3 mem_left_track_23 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size3_mem mem_left_track_25 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_4_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size2_0 mux_left_track_29 ( - .in ( { chany_top_in[19] , left_bottom_grid_pin_36_[0] } ) , - .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_left_track_29_undriven_sram_inv ) , - .out ( chanx_left_out[14] ) , .p0 ( optlc_net_128 ) ) ; -sb_2__1__mux_tree_tapbuf_size2_1 mux_left_track_31 ( - .in ( { chany_top_in[15] , left_bottom_grid_pin_37_[0] } ) , - .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_left_track_31_undriven_sram_inv ) , - .out ( chanx_left_out[15] ) , .p0 ( optlc_net_127 ) ) ; -sb_2__1__mux_tree_tapbuf_size2_2 mux_left_track_33 ( - .in ( { chany_top_in[11] , left_bottom_grid_pin_38_[0] } ) , - .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_left_track_33_undriven_sram_inv ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_127 ) ) ; -sb_2__1__mux_tree_tapbuf_size2_3 mux_left_track_35 ( - .in ( { chany_top_in[7] , left_bottom_grid_pin_39_[0] } ) , - .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_left_track_35_undriven_sram_inv ) , - .out ( chanx_left_out[17] ) , .p0 ( optlc_net_127 ) ) ; -sb_2__1__mux_tree_tapbuf_size2_4 mux_left_track_37 ( - .in ( { chany_top_in[3] , left_bottom_grid_pin_40_[0] } ) , - .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_left_track_37_undriven_sram_inv ) , - .out ( chanx_left_out[18] ) , .p0 ( optlc_net_127 ) ) ; -sb_2__1__mux_tree_tapbuf_size2 mux_left_track_39 ( - .in ( { chany_top_in[1] , left_bottom_grid_pin_41_[0] } ) , - .sram ( mux_tree_tapbuf_size2_5_sram ) , - .sram_inv ( mux_left_track_39_undriven_sram_inv ) , - .out ( chanx_left_out[19] ) , .p0 ( optlc_net_127 ) ) ; -sb_2__1__mux_tree_tapbuf_size2_mem_0 mem_left_track_29 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size2_mem_1 mem_left_track_31 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size2_mem_2 mem_left_track_33 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size2_mem_3 mem_left_track_35 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size2_mem_4 mem_left_track_37 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size2_mem mem_left_track_39 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .ccff_tail ( { ropt_net_134 } ) , - .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; -sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_125 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_126 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_154 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__3 ( .A ( chany_top_in[6] ) , - .X ( ropt_net_145 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_120 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_127 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chany_top_in[9] ) , - .X ( ropt_net_156 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__6 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_153 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__7 ( .A ( chany_top_in[12] ) , - .X ( ropt_net_151 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_122 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_128 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chany_top_in[14] ) , - .X ( ropt_net_150 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chany_top_in[16] ) , - .X ( ropt_net_149 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( chany_top_in[17] ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__12 ( .A ( chany_top_in[18] ) , - .X ( ropt_net_148 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chany_bottom_in[2] ) , - .X ( ropt_net_146 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__14 ( .A ( chany_bottom_in[4] ) , - .X ( ropt_net_142 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__15 ( .A ( chany_bottom_in[5] ) , - .X ( ropt_net_144 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__16 ( .A ( chany_bottom_in[6] ) , - .X ( aps_rename_1_ ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_130 ) , - .X ( ropt_net_168 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( ropt_net_131 ) , - .X ( chanx_left_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_132 ) , - .X ( ropt_net_169 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__20 ( .A ( chany_bottom_in[12] ) , - .X ( ropt_net_158 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_161 ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_23__22 ( .A ( chany_bottom_in[14] ) , - .X ( ropt_net_139 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_162 ) , - .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_25__24 ( .A ( chany_bottom_in[17] ) , - .X ( ropt_net_143 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_26__25 ( .A ( chany_bottom_in[18] ) , - .X ( ropt_net_155 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_163 ) , - .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_133 ) , - .X ( ropt_net_173 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_759 ( .A ( ropt_net_164 ) , - .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_165 ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_166 ) , - .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( ropt_net_134 ) , - .X ( ropt_net_180 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( - .A ( chany_bottom_in[16] ) , .X ( ropt_net_182 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( - .A ( chany_bottom_in[13] ) , .X ( ropt_net_181 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( chany_top_in[13] ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_167 ) , - .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_763 ( .A ( ropt_net_168 ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_77 ( - .A ( left_bottom_grid_pin_35_[0] ) , .X ( ropt_net_133 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_81 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_157 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( chany_top_in[8] ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_766 ( .A ( ropt_net_169 ) , - .X ( chany_bottom_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_139 ) , - .X ( ropt_net_161 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_140 ) , - .X ( ropt_net_164 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( chany_bottom_in[8] ) , - .X ( ropt_net_166 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( ropt_net_170 ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_98 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_183 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_99 ( .A ( chany_top_in[4] ) , - .X ( ropt_net_140 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_100 ( .A ( Test_en__FEEDTHRU_0[0] ) , - .X ( ropt_net_152 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( ropt_net_142 ) , - .X ( ropt_net_167 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_103 ( .A ( aps_rename_1_ ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_769 ( .A ( ropt_net_171 ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_143 ) , - .X ( ropt_net_177 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_144 ) , - .X ( ropt_net_176 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_145 ) , - .X ( ropt_net_163 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_742 ( .A ( ropt_net_146 ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_172 ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_113 ( .A ( chany_bottom_in[10] ) , - .X ( ropt_net_147 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_147 ) , - .X ( ropt_net_162 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_148 ) , - .X ( ropt_net_174 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_149 ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_150 ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( ropt_net_151 ) , - .X ( ropt_net_171 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_152 ) , - .X ( ropt_net_178 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( .A ( ropt_net_153 ) , - .X ( ropt_net_179 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_154 ) , - .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_155 ) , - .X ( ropt_net_175 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_156 ) , - .X ( ropt_net_165 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_157 ) , - .X ( ropt_net_170 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_158 ) , - .X ( ropt_net_172 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_771 ( .A ( ropt_net_173 ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_772 ( .A ( ropt_net_174 ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_773 ( .A ( ropt_net_175 ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_774 ( .A ( ropt_net_176 ) , - .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( ropt_net_177 ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( ropt_net_178 ) , - .X ( Test_en__FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( ropt_net_179 ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_180 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_181 ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_182 ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_183 ) , - .X ( chany_bottom_out[3] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__39 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__38 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__37 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__36 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__35 ( .A ( mem_out[1] ) , - .X ( net_net_64 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_64 ( .A ( net_net_64 ) , - .X ( net_net_63 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_92 ( .A ( net_net_63 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__34 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__33 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__32 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__31 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__30 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__29 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__28 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__27 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__26 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__25 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__24 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__23 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_18 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__22 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_17 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__21 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__20 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__19 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__18 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__17 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__16 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_51 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__15 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__14 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__13 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__12 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__11 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__10 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module sb_2__0_ ( prog_clk , chany_top_in , top_left_grid_pin_42_ , - top_left_grid_pin_43_ , top_left_grid_pin_44_ , top_left_grid_pin_45_ , - top_left_grid_pin_46_ , top_left_grid_pin_47_ , top_left_grid_pin_48_ , - top_left_grid_pin_49_ , top_right_grid_pin_1_ , chanx_left_in , - left_bottom_grid_pin_1_ , left_bottom_grid_pin_3_ , - left_bottom_grid_pin_5_ , left_bottom_grid_pin_7_ , - left_bottom_grid_pin_9_ , left_bottom_grid_pin_11_ , ccff_head , - chany_top_out , chanx_left_out , ccff_tail ) ; -input [0:0] prog_clk ; -input [0:19] chany_top_in ; -input [0:0] top_left_grid_pin_42_ ; -input [0:0] top_left_grid_pin_43_ ; -input [0:0] top_left_grid_pin_44_ ; -input [0:0] top_left_grid_pin_45_ ; -input [0:0] top_left_grid_pin_46_ ; -input [0:0] top_left_grid_pin_47_ ; -input [0:0] top_left_grid_pin_48_ ; -input [0:0] top_left_grid_pin_49_ ; -input [0:0] top_right_grid_pin_1_ ; -input [0:19] chanx_left_in ; -input [0:0] left_bottom_grid_pin_1_ ; -input [0:0] left_bottom_grid_pin_3_ ; -input [0:0] left_bottom_grid_pin_5_ ; -input [0:0] left_bottom_grid_pin_7_ ; -input [0:0] left_bottom_grid_pin_9_ ; -input [0:0] left_bottom_grid_pin_11_ ; -input [0:0] ccff_head ; -output [0:19] chany_top_out ; -output [0:19] chanx_left_out ; -output [0:0] ccff_tail ; - -wire [0:1] mux_left_track_11_undriven_sram_inv ; -wire [0:1] mux_left_track_13_undriven_sram_inv ; -wire [0:1] mux_left_track_15_undriven_sram_inv ; -wire [0:1] mux_left_track_17_undriven_sram_inv ; -wire [0:1] mux_left_track_19_undriven_sram_inv ; -wire [0:2] mux_left_track_1_undriven_sram_inv ; -wire [0:1] mux_left_track_25_undriven_sram_inv ; -wire [0:1] mux_left_track_27_undriven_sram_inv ; -wire [0:1] mux_left_track_29_undriven_sram_inv ; -wire [0:1] mux_left_track_31_undriven_sram_inv ; -wire [0:1] mux_left_track_33_undriven_sram_inv ; -wire [0:1] mux_left_track_35_undriven_sram_inv ; -wire [0:2] mux_left_track_3_undriven_sram_inv ; -wire [0:2] mux_left_track_5_undriven_sram_inv ; -wire [0:2] mux_left_track_7_undriven_sram_inv ; -wire [0:1] mux_left_track_9_undriven_sram_inv ; -wire [0:2] mux_top_track_0_undriven_sram_inv ; -wire [0:1] mux_top_track_10_undriven_sram_inv ; -wire [0:1] mux_top_track_12_undriven_sram_inv ; -wire [0:1] mux_top_track_14_undriven_sram_inv ; -wire [0:1] mux_top_track_16_undriven_sram_inv ; -wire [0:1] mux_top_track_18_undriven_sram_inv ; -wire [0:1] mux_top_track_20_undriven_sram_inv ; -wire [0:1] mux_top_track_22_undriven_sram_inv ; -wire [0:1] mux_top_track_24_undriven_sram_inv ; -wire [0:1] mux_top_track_26_undriven_sram_inv ; -wire [0:2] mux_top_track_2_undriven_sram_inv ; -wire [0:2] mux_top_track_4_undriven_sram_inv ; -wire [0:2] mux_top_track_6_undriven_sram_inv ; -wire [0:1] mux_top_track_8_undriven_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_10_sram ; -wire [0:1] mux_tree_tapbuf_size2_11_sram ; -wire [0:1] mux_tree_tapbuf_size2_12_sram ; -wire [0:1] mux_tree_tapbuf_size2_13_sram ; -wire [0:1] mux_tree_tapbuf_size2_14_sram ; -wire [0:1] mux_tree_tapbuf_size2_15_sram ; -wire [0:1] mux_tree_tapbuf_size2_16_sram ; -wire [0:1] mux_tree_tapbuf_size2_17_sram ; -wire [0:1] mux_tree_tapbuf_size2_18_sram ; -wire [0:1] mux_tree_tapbuf_size2_19_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_5_sram ; -wire [0:1] mux_tree_tapbuf_size2_6_sram ; -wire [0:1] mux_tree_tapbuf_size2_7_sram ; -wire [0:1] mux_tree_tapbuf_size2_8_sram ; -wire [0:1] mux_tree_tapbuf_size2_9_sram ; -wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; -wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size4_0_sram ; -wire [0:2] mux_tree_tapbuf_size4_1_sram ; -wire [0:2] mux_tree_tapbuf_size4_2_sram ; -wire [0:2] mux_tree_tapbuf_size4_3_sram ; -wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size5_0_sram ; -wire [0:2] mux_tree_tapbuf_size5_1_sram ; -wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size6_1_sram ; -wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; - -sb_2__0__mux_tree_tapbuf_size6_0 mux_top_track_0 ( - .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , - top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , - top_right_grid_pin_1_[0] , chanx_left_in[0] } ) , - .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_top_track_0_undriven_sram_inv ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_120 ) ) ; -sb_2__0__mux_tree_tapbuf_size6 mux_top_track_4 ( - .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , - top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , - top_right_grid_pin_1_[0] , chanx_left_in[18] } ) , - .sram ( mux_tree_tapbuf_size6_1_sram ) , - .sram_inv ( mux_top_track_4_undriven_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_119 ) ) ; -sb_2__0__mux_tree_tapbuf_size6_mem_0 mem_top_track_0 ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size6_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size5_0 mux_top_track_2 ( - .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , - top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , - chanx_left_in[19] } ) , - .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_top_track_2_undriven_sram_inv ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_120 ) ) ; -sb_2__0__mux_tree_tapbuf_size5 mux_top_track_6 ( - .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , - top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , - chanx_left_in[17] } ) , - .sram ( mux_tree_tapbuf_size5_1_sram ) , - .sram_inv ( mux_top_track_6_undriven_sram_inv ) , - .out ( chany_top_out[3] ) , .p0 ( optlc_net_121 ) ) ; -sb_2__0__mux_tree_tapbuf_size5_mem_0 mem_top_track_2 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size5_mem mem_top_track_6 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size3 mux_top_track_8 ( - .in ( { top_left_grid_pin_42_[0] , top_right_grid_pin_1_[0] , - chanx_left_in[16] } ) , - .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_top_track_8_undriven_sram_inv ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_121 ) ) ; -sb_2__0__mux_tree_tapbuf_size3_0 mux_top_track_24 ( - .in ( { top_left_grid_pin_42_[0] , top_right_grid_pin_1_[0] , - chanx_left_in[8] } ) , - .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_top_track_24_undriven_sram_inv ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_119 ) ) ; -sb_2__0__mux_tree_tapbuf_size3_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size3_mem_0 mem_top_track_24 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size2_12 mux_top_track_10 ( - .in ( { top_left_grid_pin_43_[0] , chanx_left_in[15] } ) , - .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_top_track_10_undriven_sram_inv ) , - .out ( chany_top_out[5] ) , .p0 ( optlc_net_119 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_13 mux_top_track_12 ( - .in ( { top_left_grid_pin_44_[0] , chanx_left_in[14] } ) , - .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_top_track_12_undriven_sram_inv ) , - .out ( chany_top_out[6] ) , .p0 ( optlc_net_120 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_14 mux_top_track_14 ( - .in ( { top_left_grid_pin_45_[0] , chanx_left_in[13] } ) , - .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_top_track_14_undriven_sram_inv ) , - .out ( chany_top_out[7] ) , .p0 ( optlc_net_120 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_15 mux_top_track_16 ( - .in ( { top_left_grid_pin_46_[0] , chanx_left_in[12] } ) , - .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_top_track_16_undriven_sram_inv ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_120 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_16 mux_top_track_18 ( - .in ( { top_left_grid_pin_47_[0] , chanx_left_in[11] } ) , - .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_top_track_18_undriven_sram_inv ) , - .out ( chany_top_out[9] ) , .p0 ( optlc_net_121 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_17 mux_top_track_20 ( - .in ( { top_left_grid_pin_48_[0] , chanx_left_in[10] } ) , - .sram ( mux_tree_tapbuf_size2_5_sram ) , - .sram_inv ( mux_top_track_20_undriven_sram_inv ) , - .out ( chany_top_out[10] ) , .p0 ( optlc_net_119 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_18 mux_top_track_22 ( - .in ( { top_left_grid_pin_49_[0] , chanx_left_in[9] } ) , - .sram ( mux_tree_tapbuf_size2_6_sram ) , - .sram_inv ( mux_top_track_22_undriven_sram_inv ) , - .out ( chany_top_out[11] ) , .p0 ( optlc_net_119 ) ) ; -sb_2__0__mux_tree_tapbuf_size2 mux_top_track_26 ( - .in ( { top_left_grid_pin_43_[0] , chanx_left_in[7] } ) , - .sram ( mux_tree_tapbuf_size2_7_sram ) , - .sram_inv ( mux_top_track_26_undriven_sram_inv ) , - .out ( chany_top_out[13] ) , .p0 ( optlc_net_120 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_11 mux_left_track_9 ( - .in ( { chany_top_in[16] , left_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size2_8_sram ) , - .sram_inv ( mux_left_track_9_undriven_sram_inv ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_122 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_0 mux_left_track_11 ( - .in ( { chany_top_in[15] , left_bottom_grid_pin_3_[0] } ) , - .sram ( mux_tree_tapbuf_size2_9_sram ) , - .sram_inv ( mux_left_track_11_undriven_sram_inv ) , - .out ( chanx_left_out[5] ) , .p0 ( optlc_net_120 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_1 mux_left_track_13 ( - .in ( { chany_top_in[14] , left_bottom_grid_pin_5_[0] } ) , - .sram ( mux_tree_tapbuf_size2_10_sram ) , - .sram_inv ( mux_left_track_13_undriven_sram_inv ) , - .out ( chanx_left_out[6] ) , .p0 ( optlc_net_120 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_2 mux_left_track_15 ( - .in ( { chany_top_in[13] , left_bottom_grid_pin_7_[0] } ) , - .sram ( mux_tree_tapbuf_size2_11_sram ) , - .sram_inv ( mux_left_track_15_undriven_sram_inv ) , - .out ( chanx_left_out[7] ) , .p0 ( optlc_net_119 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_3 mux_left_track_17 ( - .in ( { chany_top_in[12] , left_bottom_grid_pin_9_[0] } ) , - .sram ( mux_tree_tapbuf_size2_12_sram ) , - .sram_inv ( mux_left_track_17_undriven_sram_inv ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_121 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_4 mux_left_track_19 ( - .in ( { chany_top_in[11] , left_bottom_grid_pin_11_[0] } ) , - .sram ( mux_tree_tapbuf_size2_13_sram ) , - .sram_inv ( mux_left_track_19_undriven_sram_inv ) , - .out ( chanx_left_out[9] ) , .p0 ( optlc_net_119 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_5 mux_left_track_25 ( - .in ( { chany_top_in[8] , left_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size2_14_sram ) , - .sram_inv ( mux_left_track_25_undriven_sram_inv ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_120 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_6 mux_left_track_27 ( - .in ( { chany_top_in[7] , left_bottom_grid_pin_3_[0] } ) , - .sram ( mux_tree_tapbuf_size2_15_sram ) , - .sram_inv ( mux_left_track_27_undriven_sram_inv ) , - .out ( chanx_left_out[13] ) , .p0 ( optlc_net_122 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_7 mux_left_track_29 ( - .in ( { chany_top_in[6] , left_bottom_grid_pin_5_[0] } ) , - .sram ( mux_tree_tapbuf_size2_16_sram ) , - .sram_inv ( mux_left_track_29_undriven_sram_inv ) , - .out ( { ropt_net_126 } ) , - .p0 ( optlc_net_119 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_8 mux_left_track_31 ( - .in ( { chany_top_in[5] , left_bottom_grid_pin_7_[0] } ) , - .sram ( mux_tree_tapbuf_size2_17_sram ) , - .sram_inv ( mux_left_track_31_undriven_sram_inv ) , - .out ( chanx_left_out[15] ) , .p0 ( optlc_net_122 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_9 mux_left_track_33 ( - .in ( { chany_top_in[4] , left_bottom_grid_pin_9_[0] } ) , - .sram ( mux_tree_tapbuf_size2_18_sram ) , - .sram_inv ( mux_left_track_33_undriven_sram_inv ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_119 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_10 mux_left_track_35 ( - .in ( { chany_top_in[3] , left_bottom_grid_pin_11_[0] } ) , - .sram ( mux_tree_tapbuf_size2_19_sram ) , - .sram_inv ( mux_left_track_35_undriven_sram_inv ) , - .out ( chanx_left_out[17] ) , .p0 ( optlc_net_121 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_12 mem_top_track_10 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_13 mem_top_track_12 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_14 mem_top_track_14 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_15 mem_top_track_16 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_16 mem_top_track_18 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_17 mem_top_track_20 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_18 mem_top_track_22 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem mem_top_track_26 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_11 mem_left_track_9 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_0 mem_left_track_11 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_1 mem_left_track_13 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_2 mem_left_track_15 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_11_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_3 mem_left_track_17 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_12_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_4 mem_left_track_19 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_13_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_5 mem_left_track_25 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_14_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_6 mem_left_track_27 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_15_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_7 mem_left_track_29 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_16_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_8 mem_left_track_31 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_17_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_9 mem_left_track_33 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_18_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_10 mem_left_track_35 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , - .ccff_tail ( { ropt_net_130 } ) , - .mem_out ( mux_tree_tapbuf_size2_19_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size4_0 mux_left_track_1 ( - .in ( { chany_top_in[0] , left_bottom_grid_pin_1_[0] , - left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] } ) , - .sram ( mux_tree_tapbuf_size4_0_sram ) , - .sram_inv ( mux_left_track_1_undriven_sram_inv ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_122 ) ) ; -sb_2__0__mux_tree_tapbuf_size4_1 mux_left_track_3 ( - .in ( { chany_top_in[19] , left_bottom_grid_pin_3_[0] , - left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] } ) , - .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_left_track_3_undriven_sram_inv ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_122 ) ) ; -sb_2__0__mux_tree_tapbuf_size4_2 mux_left_track_5 ( - .in ( { chany_top_in[18] , left_bottom_grid_pin_1_[0] , - left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] } ) , - .sram ( mux_tree_tapbuf_size4_2_sram ) , - .sram_inv ( mux_left_track_5_undriven_sram_inv ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_122 ) ) ; -sb_2__0__mux_tree_tapbuf_size4 mux_left_track_7 ( - .in ( { chany_top_in[17] , left_bottom_grid_pin_3_[0] , - left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] } ) , - .sram ( mux_tree_tapbuf_size4_3_sram ) , - .sram_inv ( mux_left_track_7_undriven_sram_inv ) , - .out ( chanx_left_out[3] ) , .p0 ( optlc_net_122 ) ) ; -sb_2__0__mux_tree_tapbuf_size4_mem_0 mem_left_track_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size4_mem_1 mem_left_track_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size4_mem_2 mem_left_track_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size4_mem mem_left_track_7 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_139 ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_708 ( .A ( ropt_net_126 ) , - .X ( ropt_net_139 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_721 ( .A ( ropt_net_140 ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_141 ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__4 ( .A ( chanx_left_in[1] ) , - .X ( ropt_net_133 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_119 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_120 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_121 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__8 ( .A ( chanx_left_in[5] ) , - .X ( ropt_net_134 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__9 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_137 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_723 ( .A ( ropt_net_142 ) , - .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_122 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( ropt_net_143 ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( ropt_net_144 ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( ropt_net_145 ) , - .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_78 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_132 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( ropt_net_146 ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_728 ( .A ( ropt_net_147 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_86 ( .A ( chanx_left_in[2] ) , - .X ( ropt_net_136 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_87 ( .A ( chanx_left_in[3] ) , - .X ( ropt_net_131 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_88 ( .A ( chanx_left_in[4] ) , - .X ( ropt_net_135 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_709 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_148 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_710 ( .A ( chany_top_in[9] ) , - .X ( ropt_net_149 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_711 ( .A ( chany_top_in[1] ) , - .X ( ropt_net_150 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_712 ( .A ( ropt_net_130 ) , - .X ( ropt_net_147 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_713 ( .A ( ropt_net_131 ) , - .X ( ropt_net_141 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_714 ( .A ( ropt_net_132 ) , - .X ( ropt_net_142 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_715 ( .A ( ropt_net_133 ) , - .X ( ropt_net_144 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_716 ( .A ( ropt_net_134 ) , - .X ( ropt_net_140 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_717 ( .A ( ropt_net_135 ) , - .X ( ropt_net_145 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_718 ( .A ( ropt_net_136 ) , - .X ( ropt_net_146 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_137 ) , - .X ( ropt_net_143 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_148 ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_730 ( .A ( ropt_net_149 ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_150 ) , - .X ( chanx_left_out[19] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_28__62 ( .A ( mem_out[2] ) , - .X ( net_net_120 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_120 ( .A ( net_net_120 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__61 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__60 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size3_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__59 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__58 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__57 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__56 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__55 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size3_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__54 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__53 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__52 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_126 ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__51 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__50 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__49 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__48 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__47 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__46 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__45 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__44 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__43 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_125 ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__42 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__41 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size14_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__40 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size14_mem ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__39 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size14_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:13] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size14 ( in , sram , sram_inv , out , p0 ) ; -input [0:13] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size9_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__38 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size9_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__37 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size9_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__36 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size9_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:8] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size9_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:8] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , p0 ) ; -input [0:8] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__35 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module sb_1__2_ ( prog_clk , chanx_right_in , right_top_grid_pin_1_ , - right_bottom_grid_pin_34_ , right_bottom_grid_pin_35_ , - right_bottom_grid_pin_36_ , right_bottom_grid_pin_37_ , - right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ , - right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ , chany_bottom_in , - bottom_left_grid_pin_42_ , bottom_left_grid_pin_43_ , - bottom_left_grid_pin_44_ , bottom_left_grid_pin_45_ , - bottom_left_grid_pin_46_ , bottom_left_grid_pin_47_ , - bottom_left_grid_pin_48_ , bottom_left_grid_pin_49_ , chanx_left_in , - left_top_grid_pin_1_ , left_bottom_grid_pin_34_ , - left_bottom_grid_pin_35_ , left_bottom_grid_pin_36_ , - left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , - left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , - left_bottom_grid_pin_41_ , ccff_head , chanx_right_out , - chany_bottom_out , chanx_left_out , ccff_tail , SC_IN_TOP , SC_IN_BOT , - SC_OUT_TOP , SC_OUT_BOT , Test_en__FEEDTHRU_0 , Test_en__FEEDTHRU_1 , - Test_en__FEEDTHRU_2 , clk__FEEDTHRU_0 , clk__FEEDTHRU_1 , - clk__FEEDTHRU_2 ) ; -input [0:0] prog_clk ; -input [0:19] chanx_right_in ; -input [0:0] right_top_grid_pin_1_ ; -input [0:0] right_bottom_grid_pin_34_ ; -input [0:0] right_bottom_grid_pin_35_ ; -input [0:0] right_bottom_grid_pin_36_ ; -input [0:0] right_bottom_grid_pin_37_ ; -input [0:0] right_bottom_grid_pin_38_ ; -input [0:0] right_bottom_grid_pin_39_ ; -input [0:0] right_bottom_grid_pin_40_ ; -input [0:0] right_bottom_grid_pin_41_ ; -input [0:19] chany_bottom_in ; -input [0:0] bottom_left_grid_pin_42_ ; -input [0:0] bottom_left_grid_pin_43_ ; -input [0:0] bottom_left_grid_pin_44_ ; -input [0:0] bottom_left_grid_pin_45_ ; -input [0:0] bottom_left_grid_pin_46_ ; -input [0:0] bottom_left_grid_pin_47_ ; -input [0:0] bottom_left_grid_pin_48_ ; -input [0:0] bottom_left_grid_pin_49_ ; -input [0:19] chanx_left_in ; -input [0:0] left_top_grid_pin_1_ ; -input [0:0] left_bottom_grid_pin_34_ ; -input [0:0] left_bottom_grid_pin_35_ ; -input [0:0] left_bottom_grid_pin_36_ ; -input [0:0] left_bottom_grid_pin_37_ ; -input [0:0] left_bottom_grid_pin_38_ ; -input [0:0] left_bottom_grid_pin_39_ ; -input [0:0] left_bottom_grid_pin_40_ ; -input [0:0] left_bottom_grid_pin_41_ ; -input [0:0] ccff_head ; -output [0:19] chanx_right_out ; -output [0:19] chany_bottom_out ; -output [0:19] chanx_left_out ; -output [0:0] ccff_tail ; -input SC_IN_TOP ; -input SC_IN_BOT ; -output SC_OUT_TOP ; -output SC_OUT_BOT ; -input [0:0] Test_en__FEEDTHRU_0 ; -output [0:0] Test_en__FEEDTHRU_1 ; -output [0:0] Test_en__FEEDTHRU_2 ; -input [0:0] clk__FEEDTHRU_0 ; -output [0:0] clk__FEEDTHRU_1 ; -output [0:0] clk__FEEDTHRU_2 ; - -wire [0:2] mux_bottom_track_11_undriven_sram_inv ; -wire [0:1] mux_bottom_track_13_undriven_sram_inv ; -wire [0:1] mux_bottom_track_15_undriven_sram_inv ; -wire [0:1] mux_bottom_track_17_undriven_sram_inv ; -wire [0:1] mux_bottom_track_19_undriven_sram_inv ; -wire [0:2] mux_bottom_track_1_undriven_sram_inv ; -wire [0:1] mux_bottom_track_21_undriven_sram_inv ; -wire [0:1] mux_bottom_track_23_undriven_sram_inv ; -wire [0:2] mux_bottom_track_25_undriven_sram_inv ; -wire [0:1] mux_bottom_track_27_undriven_sram_inv ; -wire [0:2] mux_bottom_track_3_undriven_sram_inv ; -wire [0:2] mux_bottom_track_5_undriven_sram_inv ; -wire [0:2] mux_bottom_track_7_undriven_sram_inv ; -wire [0:2] mux_bottom_track_9_undriven_sram_inv ; -wire [0:2] mux_left_track_17_undriven_sram_inv ; -wire [0:3] mux_left_track_1_undriven_sram_inv ; -wire [0:2] mux_left_track_25_undriven_sram_inv ; -wire [0:2] mux_left_track_33_undriven_sram_inv ; -wire [0:3] mux_left_track_3_undriven_sram_inv ; -wire [0:3] mux_left_track_5_undriven_sram_inv ; -wire [0:3] mux_left_track_9_undriven_sram_inv ; -wire [0:3] mux_right_track_0_undriven_sram_inv ; -wire [0:2] mux_right_track_16_undriven_sram_inv ; -wire [0:2] mux_right_track_24_undriven_sram_inv ; -wire [0:3] mux_right_track_2_undriven_sram_inv ; -wire [0:2] mux_right_track_32_undriven_sram_inv ; -wire [0:3] mux_right_track_4_undriven_sram_inv ; -wire [0:3] mux_right_track_8_undriven_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size14_0_sram ; -wire [0:3] mux_tree_tapbuf_size14_1_sram ; -wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail ; -wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; -wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:1] mux_tree_tapbuf_size3_2_sram ; -wire [0:1] mux_tree_tapbuf_size3_3_sram ; -wire [0:1] mux_tree_tapbuf_size3_4_sram ; -wire [0:1] mux_tree_tapbuf_size3_5_sram ; -wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size4_0_sram ; -wire [0:2] mux_tree_tapbuf_size4_1_sram ; -wire [0:2] mux_tree_tapbuf_size4_2_sram ; -wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size5_0_sram ; -wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size7_0_sram ; -wire [0:2] mux_tree_tapbuf_size7_1_sram ; -wire [0:2] mux_tree_tapbuf_size7_2_sram ; -wire [0:2] mux_tree_tapbuf_size7_3_sram ; -wire [0:2] mux_tree_tapbuf_size7_4_sram ; -wire [0:2] mux_tree_tapbuf_size7_5_sram ; -wire [0:2] mux_tree_tapbuf_size7_6_sram ; -wire [0:2] mux_tree_tapbuf_size7_7_sram ; -wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_7_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size9_0_sram ; -wire [0:3] mux_tree_tapbuf_size9_1_sram ; -wire [0:3] mux_tree_tapbuf_size9_2_sram ; -wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size9_mem_2_ccff_tail ; - -assign SC_IN_TOP = SC_IN_BOT ; -assign clk__FEEDTHRU_2[0] = clk__FEEDTHRU_0[0] ; -assign clk__FEEDTHRU_1[0] = clk__FEEDTHRU_2[0] ; - -sb_1__2__mux_tree_tapbuf_size10 mux_right_track_0 ( - .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] , - right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , - right_bottom_grid_pin_41_[0] , chany_bottom_in[5] , - chany_bottom_in[12] , chany_bottom_in[19] , chanx_left_in[2] , - chanx_left_in[12] } ) , - .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_right_track_0_undriven_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_157 ) ) ; -sb_1__2__mux_tree_tapbuf_size10_mem mem_right_track_0 ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size9 mux_right_track_2 ( - .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , - right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , - chany_bottom_in[4] , chany_bottom_in[11] , chany_bottom_in[18] , - chanx_left_in[4] , chanx_left_in[13] } ) , - .sram ( mux_tree_tapbuf_size9_0_sram ) , - .sram_inv ( mux_right_track_2_undriven_sram_inv ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_157 ) ) ; -sb_1__2__mux_tree_tapbuf_size9_0 mux_left_track_1 ( - .in ( { chanx_right_in[2] , chanx_right_in[12] , chany_bottom_in[6] , - chany_bottom_in[13] , left_top_grid_pin_1_[0] , - left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , - left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , - .sram ( mux_tree_tapbuf_size9_1_sram ) , - .sram_inv ( mux_left_track_1_undriven_sram_inv ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_155 ) ) ; -sb_1__2__mux_tree_tapbuf_size9_1 mux_left_track_3 ( - .in ( { chanx_right_in[4] , chanx_right_in[13] , chany_bottom_in[0] , - chany_bottom_in[7] , chany_bottom_in[14] , - left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , - left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , - .sram ( mux_tree_tapbuf_size9_2_sram ) , - .sram_inv ( mux_left_track_3_undriven_sram_inv ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_154 ) ) ; -sb_1__2__mux_tree_tapbuf_size9_mem mem_right_track_2 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size9_0_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size9_mem_0 mem_left_track_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size9_1_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size9_mem_1 mem_left_track_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size9_2_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size14 mux_right_track_4 ( - .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_34_[0] , - right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_36_[0] , - right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_38_[0] , - right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_40_[0] , - right_bottom_grid_pin_41_[0] , chany_bottom_in[3] , - chany_bottom_in[10] , chany_bottom_in[17] , chanx_left_in[5] , - chanx_left_in[14] } ) , - .sram ( mux_tree_tapbuf_size14_0_sram ) , - .sram_inv ( mux_right_track_4_undriven_sram_inv ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_157 ) ) ; -sb_1__2__mux_tree_tapbuf_size14_0 mux_left_track_5 ( - .in ( { chanx_right_in[5] , chanx_right_in[14] , chany_bottom_in[1] , - chany_bottom_in[8] , chany_bottom_in[15] , left_top_grid_pin_1_[0] , - left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_35_[0] , - left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_37_[0] , - left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_39_[0] , - left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_41_[0] } ) , - .sram ( mux_tree_tapbuf_size14_1_sram ) , - .sram_inv ( mux_left_track_5_undriven_sram_inv ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_154 ) ) ; -sb_1__2__mux_tree_tapbuf_size14_mem mem_right_track_4 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size14_0_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size14_mem_0 mem_left_track_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size14_1_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size8 mux_right_track_8 ( - .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_37_[0] , - right_bottom_grid_pin_41_[0] , chany_bottom_in[2] , - chany_bottom_in[9] , chany_bottom_in[16] , chanx_left_in[6] , - chanx_left_in[16] } ) , - .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_right_track_8_undriven_sram_inv ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_153 ) ) ; -sb_1__2__mux_tree_tapbuf_size8_0 mux_left_track_9 ( - .in ( { chanx_right_in[6] , chanx_right_in[16] , chany_bottom_in[2] , - chany_bottom_in[9] , chany_bottom_in[16] , left_top_grid_pin_1_[0] , - left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_41_[0] } ) , - .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_left_track_9_undriven_sram_inv ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_155 ) ) ; -sb_1__2__mux_tree_tapbuf_size8_mem mem_right_track_8 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size8_mem_0 mem_left_track_9 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size7_6 mux_right_track_16 ( - .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_38_[0] , - chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[15] , - chanx_left_in[8] , chanx_left_in[17] } ) , - .sram ( mux_tree_tapbuf_size7_0_sram ) , - .sram_inv ( mux_right_track_16_undriven_sram_inv ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_153 ) ) ; -sb_1__2__mux_tree_tapbuf_size7 mux_right_track_24 ( - .in ( { right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_39_[0] , - chany_bottom_in[0] , chany_bottom_in[7] , chany_bottom_in[14] , - chanx_left_in[9] , chanx_left_in[18] } ) , - .sram ( mux_tree_tapbuf_size7_1_sram ) , - .sram_inv ( mux_right_track_24_undriven_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_153 ) ) ; -sb_1__2__mux_tree_tapbuf_size7_0 mux_bottom_track_1 ( - .in ( { chanx_right_in[2] , bottom_left_grid_pin_42_[0] , - bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , - bottom_left_grid_pin_48_[0] , chanx_left_in[1] , chanx_left_in[2] } ) , - .sram ( mux_tree_tapbuf_size7_2_sram ) , - .sram_inv ( mux_bottom_track_1_undriven_sram_inv ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_155 ) ) ; -sb_1__2__mux_tree_tapbuf_size7_1 mux_bottom_track_3 ( - .in ( { chanx_right_in[4] , bottom_left_grid_pin_43_[0] , - bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , - bottom_left_grid_pin_49_[0] , chanx_left_in[3] , chanx_left_in[4] } ) , - .sram ( mux_tree_tapbuf_size7_3_sram ) , - .sram_inv ( mux_bottom_track_3_undriven_sram_inv ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_156 ) ) ; -sb_1__2__mux_tree_tapbuf_size7_2 mux_bottom_track_5 ( - .in ( { chanx_right_in[5] , bottom_left_grid_pin_42_[0] , - bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , - bottom_left_grid_pin_48_[0] , chanx_left_in[5] , chanx_left_in[7] } ) , - .sram ( mux_tree_tapbuf_size7_4_sram ) , - .sram_inv ( mux_bottom_track_5_undriven_sram_inv ) , - .out ( { ropt_net_169 } ) , - .p0 ( optlc_net_154 ) ) ; -sb_1__2__mux_tree_tapbuf_size7_3 mux_bottom_track_7 ( - .in ( { chanx_right_in[6] , bottom_left_grid_pin_43_[0] , - bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , - bottom_left_grid_pin_49_[0] , chanx_left_in[6] , chanx_left_in[11] } ) , - .sram ( mux_tree_tapbuf_size7_5_sram ) , - .sram_inv ( mux_bottom_track_7_undriven_sram_inv ) , - .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_154 ) ) ; -sb_1__2__mux_tree_tapbuf_size7_4 mux_left_track_17 ( - .in ( { chanx_right_in[8] , chanx_right_in[17] , chany_bottom_in[3] , - chany_bottom_in[10] , chany_bottom_in[17] , - left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_38_[0] } ) , - .sram ( mux_tree_tapbuf_size7_6_sram ) , - .sram_inv ( mux_left_track_17_undriven_sram_inv ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_155 ) ) ; -sb_1__2__mux_tree_tapbuf_size7_5 mux_left_track_25 ( - .in ( { chanx_right_in[9] , chanx_right_in[18] , chany_bottom_in[4] , - chany_bottom_in[11] , chany_bottom_in[18] , - left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_39_[0] } ) , - .sram ( mux_tree_tapbuf_size7_7_sram ) , - .sram_inv ( mux_left_track_25_undriven_sram_inv ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_156 ) ) ; -sb_1__2__mux_tree_tapbuf_size7_mem_6 mem_right_track_16 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size7_mem mem_right_track_24 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size7_mem_0 mem_bottom_track_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size7_mem_1 mem_bottom_track_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_3_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size7_mem_2 mem_bottom_track_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_4_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size7_mem_3 mem_bottom_track_7 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_5_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size7_mem_4 mem_left_track_17 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_6_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size7_mem_5 mem_left_track_25 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_7_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size5 mux_right_track_32 ( - .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_40_[0] , - chany_bottom_in[6] , chany_bottom_in[13] , chanx_left_in[10] } ) , - .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_right_track_32_undriven_sram_inv ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_153 ) ) ; -sb_1__2__mux_tree_tapbuf_size5_mem mem_right_track_32 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size4 mux_bottom_track_9 ( - .in ( { chanx_right_in[8] , bottom_left_grid_pin_42_[0] , - chanx_left_in[8] , chanx_left_in[15] } ) , - .sram ( mux_tree_tapbuf_size4_0_sram ) , - .sram_inv ( mux_bottom_track_9_undriven_sram_inv ) , - .out ( { ropt_net_168 } ) , - .p0 ( optlc_net_154 ) ) ; -sb_1__2__mux_tree_tapbuf_size4_0 mux_bottom_track_11 ( - .in ( { chanx_right_in[9] , bottom_left_grid_pin_43_[0] , - chanx_left_in[9] , chanx_left_in[19] } ) , - .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_bottom_track_11_undriven_sram_inv ) , - .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_154 ) ) ; -sb_1__2__mux_tree_tapbuf_size4_1 mux_bottom_track_25 ( - .in ( { chanx_right_in[18] , chanx_right_in[19] , - bottom_left_grid_pin_42_[0] , chanx_left_in[18] } ) , - .sram ( mux_tree_tapbuf_size4_2_sram ) , - .sram_inv ( mux_bottom_track_25_undriven_sram_inv ) , - .out ( { ropt_net_162 } ) , - .p0 ( optlc_net_153 ) ) ; -sb_1__2__mux_tree_tapbuf_size4_mem mem_bottom_track_9 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size4_mem_0 mem_bottom_track_11 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size4_mem_1 mem_bottom_track_25 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size3_0 mux_bottom_track_13 ( - .in ( { chanx_right_in[10] , bottom_left_grid_pin_44_[0] , - chanx_left_in[10] } ) , - .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_bottom_track_13_undriven_sram_inv ) , - .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_156 ) ) ; -sb_1__2__mux_tree_tapbuf_size3_1 mux_bottom_track_15 ( - .in ( { chanx_right_in[12] , bottom_left_grid_pin_45_[0] , - chanx_left_in[12] } ) , - .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_bottom_track_15_undriven_sram_inv ) , - .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_156 ) ) ; -sb_1__2__mux_tree_tapbuf_size3_2 mux_bottom_track_17 ( - .in ( { chanx_right_in[13] , bottom_left_grid_pin_46_[0] , - chanx_left_in[13] } ) , - .sram ( mux_tree_tapbuf_size3_2_sram ) , - .sram_inv ( mux_bottom_track_17_undriven_sram_inv ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_156 ) ) ; -sb_1__2__mux_tree_tapbuf_size3_3 mux_bottom_track_19 ( - .in ( { chanx_right_in[14] , bottom_left_grid_pin_47_[0] , - chanx_left_in[14] } ) , - .sram ( mux_tree_tapbuf_size3_3_sram ) , - .sram_inv ( mux_bottom_track_19_undriven_sram_inv ) , - .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_156 ) ) ; -sb_1__2__mux_tree_tapbuf_size3_4 mux_bottom_track_21 ( - .in ( { chanx_right_in[16] , bottom_left_grid_pin_48_[0] , - chanx_left_in[16] } ) , - .sram ( mux_tree_tapbuf_size3_4_sram ) , - .sram_inv ( mux_bottom_track_21_undriven_sram_inv ) , - .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_156 ) ) ; -sb_1__2__mux_tree_tapbuf_size3 mux_bottom_track_23 ( - .in ( { chanx_right_in[17] , bottom_left_grid_pin_49_[0] , - chanx_left_in[17] } ) , - .sram ( mux_tree_tapbuf_size3_5_sram ) , - .sram_inv ( mux_bottom_track_23_undriven_sram_inv ) , - .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_153 ) ) ; -sb_1__2__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_13 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size3_mem_1 mem_bottom_track_15 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size3_mem_2 mem_bottom_track_17 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size3_mem_3 mem_bottom_track_19 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size3_mem_4 mem_bottom_track_21 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_4_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size3_mem mem_bottom_track_23 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_5_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size2 mux_bottom_track_27 ( - .in ( { chanx_right_in[15] , bottom_left_grid_pin_43_[0] } ) , - .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_bottom_track_27_undriven_sram_inv ) , - .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_153 ) ) ; -sb_1__2__mux_tree_tapbuf_size2_mem mem_bottom_track_27 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size6 mux_left_track_33 ( - .in ( { chanx_right_in[10] , chany_bottom_in[5] , chany_bottom_in[12] , - chany_bottom_in[19] , left_bottom_grid_pin_36_[0] , - left_bottom_grid_pin_40_[0] } ) , - .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_left_track_33_undriven_sram_inv ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_154 ) ) ; -sb_1__2__mux_tree_tapbuf_size6_mem mem_left_track_33 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , - .ccff_tail ( { ropt_net_164 } ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_811 ( .A ( ropt_net_193 ) , - .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_153 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_150 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_154 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_152 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_155 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__4 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_179 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chanx_right_in[5] ) , - .X ( ropt_net_188 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__6 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_177 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_154 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_156 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_191 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_187 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_156 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , - .HI ( optlc_net_157 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( chanx_right_in[2] ) , - .X ( ropt_net_194 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_159 ) , - .X ( ropt_net_205 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( .A ( ropt_net_160 ) , - .X ( ropt_net_209 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chanx_right_in[14] ) , - .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_194 ) , - .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__16 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_184 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( chanx_right_in[18] ) , - .X ( ropt_net_211 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_162 ) , - .X ( ropt_net_204 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_163 ) , - .X ( ropt_net_197 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__20 ( .A ( chanx_left_in[4] ) , - .X ( ropt_net_189 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( ropt_net_195 ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( ropt_net_164 ) , - .X ( ropt_net_208 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_165 ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_25__24 ( .A ( chanx_left_in[9] ) , - .X ( ropt_net_182 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_26__25 ( .A ( chanx_left_in[10] ) , - .X ( ropt_net_186 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( - .A ( Test_en__FEEDTHRU_0[0] ) , .X ( ropt_net_215 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_782 ( - .A ( Test_en__FEEDTHRU_0[0] ) , .X ( ropt_net_216 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_783 ( .A ( ropt_net_168 ) , - .X ( ropt_net_210 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_784 ( .A ( ropt_net_169 ) , - .X ( ropt_net_214 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_31__30 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_180 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_785 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_213 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_160 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_196 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_814 ( .A ( ropt_net_196 ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_816 ( .A ( ropt_net_197 ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_787 ( .A ( chanx_left_in[5] ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_173 ) , - .X ( ropt_net_199 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_75 ( .A ( chanx_right_in[3] ) , - .X ( BUF_net_75 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( chanx_left_in[18] ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_818 ( .A ( ropt_net_198 ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_78 ( .A ( chanx_right_in[11] ) , - .X ( BUF_net_78 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_819 ( .A ( ropt_net_199 ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( chanx_left_in[6] ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_822 ( .A ( ropt_net_200 ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_212 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_823 ( .A ( ropt_net_201 ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_84 ( .A ( chanx_left_in[2] ) , - .X ( BUF_net_84 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_792 ( .A ( ropt_net_177 ) , - .X ( ropt_net_193 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_86 ( .A ( chanx_left_in[8] ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_178 ) , - .X ( ropt_net_202 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_179 ) , - .X ( ropt_net_198 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_180 ) , - .X ( ropt_net_201 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_90 ( .A ( chanx_left_in[16] ) , - .X ( ropt_net_183 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_181 ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_824 ( .A ( ropt_net_202 ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_826 ( .A ( ropt_net_203 ) , - .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_100 ( .A ( chanx_right_in[0] ) , - .X ( ropt_net_163 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( ropt_net_182 ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_183 ) , - .X ( ropt_net_195 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_184 ) , - .X ( ropt_net_206 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_185 ) , - .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_186 ) , - .X ( ropt_net_200 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_187 ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_188 ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_189 ) , - .X ( ropt_net_203 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_190 ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_191 ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_827 ( .A ( ropt_net_204 ) , - .X ( chany_bottom_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_828 ( .A ( ropt_net_205 ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_113 ( .A ( chanx_left_in[12] ) , - .X ( ropt_net_185 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_829 ( .A ( ropt_net_206 ) , - .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_830 ( .A ( ropt_net_207 ) , - .X ( chany_bottom_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_208 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_832 ( .A ( ropt_net_209 ) , - .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_122 ( .A ( chanx_right_in[16] ) , - .X ( ropt_net_159 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_834 ( .A ( ropt_net_210 ) , - .X ( chany_bottom_out[4] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_129 ( .A ( chanx_right_in[1] ) , - .X ( ropt_net_173 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_835 ( .A ( ropt_net_211 ) , - .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_131 ( .A ( BUF_net_75 ) , - .X ( ropt_net_207 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_132 ( .A ( chanx_right_in[7] ) , - .X ( ropt_net_190 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_836 ( .A ( ropt_net_212 ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_134 ( .A ( BUF_net_78 ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_837 ( .A ( ropt_net_213 ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_839 ( .A ( ropt_net_214 ) , - .X ( chany_bottom_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_840 ( .A ( ropt_net_215 ) , - .X ( Test_en__FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_138 ( .A ( chanx_left_in[0] ) , - .X ( ropt_net_165 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_139 ( .A ( BUF_net_84 ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_841 ( .A ( ropt_net_216 ) , - .X ( Test_en__FEEDTHRU_2[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_141 ( .A ( chanx_left_in[13] ) , - .X ( ropt_net_181 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_142 ( .A ( chanx_left_in[14] ) , - .X ( ropt_net_178 ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_28__81 ( .A ( mem_out[2] ) , - .X ( net_net_100 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_100 ( .A ( net_net_100 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__80 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__79 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__78 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__77 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__76 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__75 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__74 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__73 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__72 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__71 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__70 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_mem_8 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__69 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_mem_10 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__68 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_mem_9 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__67 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__66 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_8 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_10 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_9 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size16_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:4] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__65 ( .A ( mem_out[4] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size16_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:4] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__64 ( .A ( mem_out[4] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size16_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:4] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__63 ( .A ( mem_out[4] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size16_mem ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:4] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__62 ( .A ( mem_out[4] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size16_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:15] in ; -input [0:4] sram ; -input [0:4] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l5_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size16_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:15] in ; -input [0:4] sram ; -input [0:4] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_15_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , - .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_83 ( - .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( BUF_net_83 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_128 ( .A ( BUF_net_83 ) , - .X ( out[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size16_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:15] in ; -input [0:4] sram ; -input [0:4] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_15_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , - .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size16 ( in , sram , sram_inv , out , p0 ) ; -input [0:15] in ; -input [0:4] sram ; -input [0:4] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_15_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , - .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__61 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__60 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__59 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__58 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__57 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__56 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_mem ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__55 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__54 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:11] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:11] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_127 ( - .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:11] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:11] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:11] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:11] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12 ( in , sram , sram_inv , out , p0 ) ; -input [0:11] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:11] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -endmodule - - -module sb_1__1_ ( prog_clk , chany_top_in , top_left_grid_pin_42_ , - top_left_grid_pin_43_ , top_left_grid_pin_44_ , top_left_grid_pin_45_ , - top_left_grid_pin_46_ , top_left_grid_pin_47_ , top_left_grid_pin_48_ , - top_left_grid_pin_49_ , chanx_right_in , right_bottom_grid_pin_34_ , - right_bottom_grid_pin_35_ , right_bottom_grid_pin_36_ , - right_bottom_grid_pin_37_ , right_bottom_grid_pin_38_ , - right_bottom_grid_pin_39_ , right_bottom_grid_pin_40_ , - right_bottom_grid_pin_41_ , chany_bottom_in , bottom_left_grid_pin_42_ , - bottom_left_grid_pin_43_ , bottom_left_grid_pin_44_ , - bottom_left_grid_pin_45_ , bottom_left_grid_pin_46_ , - bottom_left_grid_pin_47_ , bottom_left_grid_pin_48_ , - bottom_left_grid_pin_49_ , chanx_left_in , left_bottom_grid_pin_34_ , - left_bottom_grid_pin_35_ , left_bottom_grid_pin_36_ , - left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , - left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , - left_bottom_grid_pin_41_ , ccff_head , chany_top_out , chanx_right_out , - chany_bottom_out , chanx_left_out , ccff_tail , prog_clk__FEEDTHRU_1 , - Test_en__FEEDTHRU_0 , Test_en__FEEDTHRU_1 , clk__FEEDTHRU_0 , - clk__FEEDTHRU_1 , - grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 , - grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) ; -input [0:0] prog_clk ; -input [0:19] chany_top_in ; -input [0:0] top_left_grid_pin_42_ ; -input [0:0] top_left_grid_pin_43_ ; -input [0:0] top_left_grid_pin_44_ ; -input [0:0] top_left_grid_pin_45_ ; -input [0:0] top_left_grid_pin_46_ ; -input [0:0] top_left_grid_pin_47_ ; -input [0:0] top_left_grid_pin_48_ ; -input [0:0] top_left_grid_pin_49_ ; -input [0:19] chanx_right_in ; -input [0:0] right_bottom_grid_pin_34_ ; -input [0:0] right_bottom_grid_pin_35_ ; -input [0:0] right_bottom_grid_pin_36_ ; -input [0:0] right_bottom_grid_pin_37_ ; -input [0:0] right_bottom_grid_pin_38_ ; -input [0:0] right_bottom_grid_pin_39_ ; -input [0:0] right_bottom_grid_pin_40_ ; -input [0:0] right_bottom_grid_pin_41_ ; -input [0:19] chany_bottom_in ; -input [0:0] bottom_left_grid_pin_42_ ; -input [0:0] bottom_left_grid_pin_43_ ; -input [0:0] bottom_left_grid_pin_44_ ; -input [0:0] bottom_left_grid_pin_45_ ; -input [0:0] bottom_left_grid_pin_46_ ; -input [0:0] bottom_left_grid_pin_47_ ; -input [0:0] bottom_left_grid_pin_48_ ; -input [0:0] bottom_left_grid_pin_49_ ; -input [0:19] chanx_left_in ; -input [0:0] left_bottom_grid_pin_34_ ; -input [0:0] left_bottom_grid_pin_35_ ; -input [0:0] left_bottom_grid_pin_36_ ; -input [0:0] left_bottom_grid_pin_37_ ; -input [0:0] left_bottom_grid_pin_38_ ; -input [0:0] left_bottom_grid_pin_39_ ; -input [0:0] left_bottom_grid_pin_40_ ; -input [0:0] left_bottom_grid_pin_41_ ; -input [0:0] ccff_head ; -output [0:19] chany_top_out ; -output [0:19] chanx_right_out ; -output [0:19] chany_bottom_out ; -output [0:19] chanx_left_out ; -output [0:0] ccff_tail ; -output [0:0] prog_clk__FEEDTHRU_1 ; -input [0:0] Test_en__FEEDTHRU_0 ; -output [0:0] Test_en__FEEDTHRU_1 ; -input [0:0] clk__FEEDTHRU_0 ; -output [0:0] clk__FEEDTHRU_1 ; -input [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ; -output [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ; - -wire [0:3] mux_bottom_track_17_undriven_sram_inv ; -wire [0:3] mux_bottom_track_1_undriven_sram_inv ; -wire [0:3] mux_bottom_track_25_undriven_sram_inv ; -wire [0:2] mux_bottom_track_33_undriven_sram_inv ; -wire [0:3] mux_bottom_track_3_undriven_sram_inv ; -wire [0:4] mux_bottom_track_5_undriven_sram_inv ; -wire [0:3] mux_bottom_track_9_undriven_sram_inv ; -wire [0:3] mux_left_track_17_undriven_sram_inv ; -wire [0:3] mux_left_track_1_undriven_sram_inv ; -wire [0:3] mux_left_track_25_undriven_sram_inv ; -wire [0:2] mux_left_track_33_undriven_sram_inv ; -wire [0:3] mux_left_track_3_undriven_sram_inv ; -wire [0:4] mux_left_track_5_undriven_sram_inv ; -wire [0:3] mux_left_track_9_undriven_sram_inv ; -wire [0:3] mux_right_track_0_undriven_sram_inv ; -wire [0:3] mux_right_track_16_undriven_sram_inv ; -wire [0:3] mux_right_track_24_undriven_sram_inv ; -wire [0:3] mux_right_track_2_undriven_sram_inv ; -wire [0:2] mux_right_track_32_undriven_sram_inv ; -wire [0:4] mux_right_track_4_undriven_sram_inv ; -wire [0:3] mux_right_track_8_undriven_sram_inv ; -wire [0:3] mux_top_track_0_undriven_sram_inv ; -wire [0:3] mux_top_track_16_undriven_sram_inv ; -wire [0:3] mux_top_track_24_undriven_sram_inv ; -wire [0:3] mux_top_track_2_undriven_sram_inv ; -wire [0:2] mux_top_track_32_undriven_sram_inv ; -wire [0:4] mux_top_track_4_undriven_sram_inv ; -wire [0:3] mux_top_track_8_undriven_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_10_sram ; -wire [0:3] mux_tree_tapbuf_size10_11_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:3] mux_tree_tapbuf_size10_2_sram ; -wire [0:3] mux_tree_tapbuf_size10_3_sram ; -wire [0:3] mux_tree_tapbuf_size10_4_sram ; -wire [0:3] mux_tree_tapbuf_size10_5_sram ; -wire [0:3] mux_tree_tapbuf_size10_6_sram ; -wire [0:3] mux_tree_tapbuf_size10_7_sram ; -wire [0:3] mux_tree_tapbuf_size10_8_sram ; -wire [0:3] mux_tree_tapbuf_size10_9_sram ; -wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_10_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_11_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_8_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_9_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size12_0_sram ; -wire [0:3] mux_tree_tapbuf_size12_1_sram ; -wire [0:3] mux_tree_tapbuf_size12_2_sram ; -wire [0:3] mux_tree_tapbuf_size12_3_sram ; -wire [0:3] mux_tree_tapbuf_size12_4_sram ; -wire [0:3] mux_tree_tapbuf_size12_5_sram ; -wire [0:3] mux_tree_tapbuf_size12_6_sram ; -wire [0:3] mux_tree_tapbuf_size12_7_sram ; -wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size12_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size12_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail ; -wire [0:4] mux_tree_tapbuf_size16_0_sram ; -wire [0:4] mux_tree_tapbuf_size16_1_sram ; -wire [0:4] mux_tree_tapbuf_size16_2_sram ; -wire [0:4] mux_tree_tapbuf_size16_3_sram ; -wire [0:0] mux_tree_tapbuf_size16_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size16_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size16_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size16_mem_3_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size7_0_sram ; -wire [0:2] mux_tree_tapbuf_size7_1_sram ; -wire [0:2] mux_tree_tapbuf_size7_2_sram ; -wire [0:2] mux_tree_tapbuf_size7_3_sram ; -wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; - -assign clk__FEEDTHRU_1[0] = clk__FEEDTHRU_0[0] ; - -sb_1__1__mux_tree_tapbuf_size12_6 mux_top_track_0 ( - .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , - top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , - chanx_right_in[1] , chanx_right_in[2] , chanx_right_in[12] , - chany_bottom_in[2] , chany_bottom_in[12] , chanx_left_in[0] , - chanx_left_in[2] , chanx_left_in[12] } ) , - .sram ( mux_tree_tapbuf_size12_0_sram ) , - .sram_inv ( mux_top_track_0_undriven_sram_inv ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_145 ) ) ; -sb_1__1__mux_tree_tapbuf_size12 mux_top_track_2 ( - .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , - top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , - chanx_right_in[3] , chanx_right_in[4] , chanx_right_in[13] , - chany_bottom_in[4] , chany_bottom_in[13] , chanx_left_in[4] , - chanx_left_in[13] , chanx_left_in[19] } ) , - .sram ( mux_tree_tapbuf_size12_1_sram ) , - .sram_inv ( mux_top_track_2_undriven_sram_inv ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_149 ) ) ; -sb_1__1__mux_tree_tapbuf_size12_4 mux_right_track_0 ( - .in ( { chany_top_in[2] , chany_top_in[12] , chany_top_in[19] , - right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , - right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , - chany_bottom_in[2] , chany_bottom_in[12] , chany_bottom_in[15] , - chanx_left_in[2] , chanx_left_in[12] } ) , - .sram ( mux_tree_tapbuf_size12_2_sram ) , - .sram_inv ( mux_right_track_0_undriven_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_145 ) ) ; -sb_1__1__mux_tree_tapbuf_size12_5 mux_right_track_2 ( - .in ( { chany_top_in[0] , chany_top_in[4] , chany_top_in[13] , - right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , - right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] , - chany_bottom_in[4] , chany_bottom_in[11] , chany_bottom_in[13] , - chanx_left_in[4] , chanx_left_in[13] } ) , - .sram ( mux_tree_tapbuf_size12_3_sram ) , - .sram_inv ( mux_right_track_2_undriven_sram_inv ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_146 ) ) ; -sb_1__1__mux_tree_tapbuf_size12_0 mux_bottom_track_1 ( - .in ( { chany_top_in[2] , chany_top_in[12] , chanx_right_in[2] , - chanx_right_in[12] , chanx_right_in[15] , - bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , - bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , - chanx_left_in[1] , chanx_left_in[2] , chanx_left_in[12] } ) , - .sram ( mux_tree_tapbuf_size12_4_sram ) , - .sram_inv ( mux_bottom_track_1_undriven_sram_inv ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_147 ) ) ; -sb_1__1__mux_tree_tapbuf_size12_1 mux_bottom_track_3 ( - .in ( { chany_top_in[4] , chany_top_in[13] , chanx_right_in[4] , - chanx_right_in[11] , chanx_right_in[13] , - bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , - bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , - chanx_left_in[3] , chanx_left_in[4] , chanx_left_in[13] } ) , - .sram ( mux_tree_tapbuf_size12_5_sram ) , - .sram_inv ( mux_bottom_track_3_undriven_sram_inv ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_147 ) ) ; -sb_1__1__mux_tree_tapbuf_size12_2 mux_left_track_1 ( - .in ( { chany_top_in[0] , chany_top_in[2] , chany_top_in[12] , - chanx_right_in[2] , chanx_right_in[12] , chany_bottom_in[2] , - chany_bottom_in[12] , chany_bottom_in[19] , - left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , - left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , - .sram ( mux_tree_tapbuf_size12_6_sram ) , - .sram_inv ( mux_left_track_1_undriven_sram_inv ) , - .out ( { ropt_net_158 } ) , - .p0 ( optlc_net_147 ) ) ; -sb_1__1__mux_tree_tapbuf_size12_3 mux_left_track_3 ( - .in ( { chany_top_in[4] , chany_top_in[13] , chany_top_in[19] , - chanx_right_in[4] , chanx_right_in[13] , chany_bottom_in[0] , - chany_bottom_in[4] , chany_bottom_in[13] , - left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , - left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , - .sram ( mux_tree_tapbuf_size12_7_sram ) , - .sram_inv ( mux_left_track_3_undriven_sram_inv ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_148 ) ) ; -sb_1__1__mux_tree_tapbuf_size12_mem_6 mem_top_track_0 ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_0_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size12_mem mem_top_track_2 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_1_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size12_mem_4 mem_right_track_0 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_2_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size12_mem_5 mem_right_track_2 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_3_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size12_mem_0 mem_bottom_track_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_4_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size12_mem_1 mem_bottom_track_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_5_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size12_mem_2 mem_left_track_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_6_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size12_mem_3 mem_left_track_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_7_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size16 mux_top_track_4 ( - .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_43_[0] , - top_left_grid_pin_44_[0] , top_left_grid_pin_45_[0] , - top_left_grid_pin_46_[0] , top_left_grid_pin_47_[0] , - top_left_grid_pin_48_[0] , top_left_grid_pin_49_[0] , - chanx_right_in[5] , chanx_right_in[7] , chanx_right_in[14] , - chany_bottom_in[5] , chany_bottom_in[14] , chanx_left_in[5] , - chanx_left_in[14] , chanx_left_in[15] } ) , - .sram ( mux_tree_tapbuf_size16_0_sram ) , - .sram_inv ( mux_top_track_4_undriven_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_149 ) ) ; -sb_1__1__mux_tree_tapbuf_size16_2 mux_right_track_4 ( - .in ( { chany_top_in[1] , chany_top_in[5] , chany_top_in[14] , - right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_35_[0] , - right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_37_[0] , - right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_39_[0] , - right_bottom_grid_pin_40_[0] , right_bottom_grid_pin_41_[0] , - chany_bottom_in[5] , chany_bottom_in[7] , chany_bottom_in[14] , - chanx_left_in[5] , chanx_left_in[14] } ) , - .sram ( mux_tree_tapbuf_size16_1_sram ) , - .sram_inv ( mux_right_track_4_undriven_sram_inv ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_146 ) ) ; -sb_1__1__mux_tree_tapbuf_size16_0 mux_bottom_track_5 ( - .in ( { chany_top_in[5] , chany_top_in[14] , chanx_right_in[5] , - chanx_right_in[7] , chanx_right_in[14] , bottom_left_grid_pin_42_[0] , - bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_44_[0] , - bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_46_[0] , - bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_48_[0] , - bottom_left_grid_pin_49_[0] , chanx_left_in[5] , chanx_left_in[7] , - chanx_left_in[14] } ) , - .sram ( mux_tree_tapbuf_size16_2_sram ) , - .sram_inv ( mux_bottom_track_5_undriven_sram_inv ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_148 ) ) ; -sb_1__1__mux_tree_tapbuf_size16_1 mux_left_track_5 ( - .in ( { chany_top_in[5] , chany_top_in[14] , chany_top_in[15] , - chanx_right_in[5] , chanx_right_in[14] , chany_bottom_in[1] , - chany_bottom_in[5] , chany_bottom_in[14] , - left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_35_[0] , - left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_37_[0] , - left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_39_[0] , - left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_41_[0] } ) , - .sram ( mux_tree_tapbuf_size16_3_sram ) , - .sram_inv ( mux_left_track_5_undriven_sram_inv ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_148 ) ) ; -sb_1__1__mux_tree_tapbuf_size16_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size16_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size16_0_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size16_mem_2 mem_right_track_4 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size16_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size16_1_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size16_mem_0 mem_bottom_track_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size16_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size16_2_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size16_mem_1 mem_left_track_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size16_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size16_3_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size10 mux_top_track_8 ( - .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_46_[0] , - chanx_right_in[6] , chanx_right_in[11] , chanx_right_in[16] , - chany_bottom_in[6] , chany_bottom_in[16] , chanx_left_in[6] , - chanx_left_in[11] , chanx_left_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_top_track_8_undriven_sram_inv ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_145 ) ) ; -sb_1__1__mux_tree_tapbuf_size10_9 mux_top_track_16 ( - .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_47_[0] , - chanx_right_in[8] , chanx_right_in[15] , chanx_right_in[17] , - chany_bottom_in[8] , chany_bottom_in[17] , chanx_left_in[7] , - chanx_left_in[8] , chanx_left_in[17] } ) , - .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_top_track_16_undriven_sram_inv ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_148 ) ) ; -sb_1__1__mux_tree_tapbuf_size10_10 mux_top_track_24 ( - .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_48_[0] , - chanx_right_in[9] , chanx_right_in[18] , chanx_right_in[19] , - chany_bottom_in[9] , chany_bottom_in[18] , chanx_left_in[3] , - chanx_left_in[9] , chanx_left_in[18] } ) , - .sram ( mux_tree_tapbuf_size10_2_sram ) , - .sram_inv ( mux_top_track_24_undriven_sram_inv ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_145 ) ) ; -sb_1__1__mux_tree_tapbuf_size10_8 mux_right_track_8 ( - .in ( { chany_top_in[3] , chany_top_in[6] , chany_top_in[16] , - right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_38_[0] , - chany_bottom_in[3] , chany_bottom_in[6] , chany_bottom_in[16] , - chanx_left_in[6] , chanx_left_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_3_sram ) , - .sram_inv ( mux_right_track_8_undriven_sram_inv ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_146 ) ) ; -sb_1__1__mux_tree_tapbuf_size10_6 mux_right_track_16 ( - .in ( { chany_top_in[7] , chany_top_in[8] , chany_top_in[17] , - right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_39_[0] , - chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[17] , - chanx_left_in[8] , chanx_left_in[17] } ) , - .sram ( mux_tree_tapbuf_size10_4_sram ) , - .sram_inv ( mux_right_track_16_undriven_sram_inv ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_146 ) ) ; -sb_1__1__mux_tree_tapbuf_size10_7 mux_right_track_24 ( - .in ( { chany_top_in[9] , chany_top_in[11] , chany_top_in[18] , - right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_40_[0] , - chany_bottom_in[0] , chany_bottom_in[9] , chany_bottom_in[18] , - chanx_left_in[9] , chanx_left_in[18] } ) , - .sram ( mux_tree_tapbuf_size10_5_sram ) , - .sram_inv ( mux_right_track_24_undriven_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_145 ) ) ; -sb_1__1__mux_tree_tapbuf_size10_2 mux_bottom_track_9 ( - .in ( { chany_top_in[6] , chany_top_in[16] , chanx_right_in[3] , - chanx_right_in[6] , chanx_right_in[16] , bottom_left_grid_pin_42_[0] , - bottom_left_grid_pin_46_[0] , chanx_left_in[6] , chanx_left_in[11] , - chanx_left_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_6_sram ) , - .sram_inv ( mux_bottom_track_9_undriven_sram_inv ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_147 ) ) ; -sb_1__1__mux_tree_tapbuf_size10_0 mux_bottom_track_17 ( - .in ( { chany_top_in[8] , chany_top_in[17] , chanx_right_in[1] , - chanx_right_in[8] , chanx_right_in[17] , bottom_left_grid_pin_43_[0] , - bottom_left_grid_pin_47_[0] , chanx_left_in[8] , chanx_left_in[15] , - chanx_left_in[17] } ) , - .sram ( mux_tree_tapbuf_size10_7_sram ) , - .sram_inv ( mux_bottom_track_17_undriven_sram_inv ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_146 ) ) ; -sb_1__1__mux_tree_tapbuf_size10_1 mux_bottom_track_25 ( - .in ( { chany_top_in[9] , chany_top_in[18] , chanx_right_in[0] , - chanx_right_in[9] , chanx_right_in[18] , bottom_left_grid_pin_44_[0] , - bottom_left_grid_pin_48_[0] , chanx_left_in[9] , chanx_left_in[18] , - chanx_left_in[19] } ) , - .sram ( mux_tree_tapbuf_size10_8_sram ) , - .sram_inv ( mux_bottom_track_25_undriven_sram_inv ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_145 ) ) ; -sb_1__1__mux_tree_tapbuf_size10_5 mux_left_track_9 ( - .in ( { chany_top_in[6] , chany_top_in[11] , chany_top_in[16] , - chanx_right_in[6] , chanx_right_in[16] , chany_bottom_in[3] , - chany_bottom_in[6] , chany_bottom_in[16] , - left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_38_[0] } ) , - .sram ( mux_tree_tapbuf_size10_9_sram ) , - .sram_inv ( mux_left_track_9_undriven_sram_inv ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_147 ) ) ; -sb_1__1__mux_tree_tapbuf_size10_3 mux_left_track_17 ( - .in ( { chany_top_in[7] , chany_top_in[8] , chany_top_in[17] , - chanx_right_in[8] , chanx_right_in[17] , chany_bottom_in[7] , - chany_bottom_in[8] , chany_bottom_in[17] , - left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_39_[0] } ) , - .sram ( mux_tree_tapbuf_size10_10_sram ) , - .sram_inv ( mux_left_track_17_undriven_sram_inv ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_148 ) ) ; -sb_1__1__mux_tree_tapbuf_size10_4 mux_left_track_25 ( - .in ( { chany_top_in[3] , chany_top_in[9] , chany_top_in[18] , - chanx_right_in[9] , chanx_right_in[18] , chany_bottom_in[9] , - chany_bottom_in[11] , chany_bottom_in[18] , - left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_40_[0] } ) , - .sram ( mux_tree_tapbuf_size10_11_sram ) , - .sram_inv ( mux_left_track_25_undriven_sram_inv ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_147 ) ) ; -sb_1__1__mux_tree_tapbuf_size10_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size16_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size10_mem_9 mem_top_track_16 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size10_mem_10 mem_top_track_24 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size10_mem_8 mem_right_track_8 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size16_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size10_mem_6 mem_right_track_16 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size10_mem_7 mem_right_track_24 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size10_mem_2 mem_bottom_track_9 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size16_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size10_mem_0 mem_bottom_track_17 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size10_mem_1 mem_bottom_track_25 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_8_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size10_mem_5 mem_left_track_9 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size16_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_9_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_9_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size10_mem_3 mem_left_track_17 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_9_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_10_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_10_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size10_mem_4 mem_left_track_25 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_10_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_11_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size7 mux_top_track_32 ( - .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_49_[0] , - chanx_right_in[0] , chanx_right_in[10] , chany_bottom_in[10] , - chanx_left_in[1] , chanx_left_in[10] } ) , - .sram ( mux_tree_tapbuf_size7_0_sram ) , - .sram_inv ( mux_top_track_32_undriven_sram_inv ) , - .out ( chany_top_out[16] ) , .p0 ( optlc_net_145 ) ) ; -sb_1__1__mux_tree_tapbuf_size7_2 mux_right_track_32 ( - .in ( { chany_top_in[10] , chany_top_in[15] , - right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_41_[0] , - chany_bottom_in[10] , chany_bottom_in[19] , chanx_left_in[10] } ) , - .sram ( mux_tree_tapbuf_size7_1_sram ) , - .sram_inv ( mux_right_track_32_undriven_sram_inv ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_146 ) ) ; -sb_1__1__mux_tree_tapbuf_size7_0 mux_bottom_track_33 ( - .in ( { chany_top_in[10] , chanx_right_in[10] , chanx_right_in[19] , - bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_49_[0] , - chanx_left_in[0] , chanx_left_in[10] } ) , - .sram ( mux_tree_tapbuf_size7_2_sram ) , - .sram_inv ( mux_bottom_track_33_undriven_sram_inv ) , - .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_147 ) ) ; -sb_1__1__mux_tree_tapbuf_size7_1 mux_left_track_33 ( - .in ( { chany_top_in[1] , chany_top_in[10] , chanx_right_in[10] , - chany_bottom_in[10] , chany_bottom_in[15] , - left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_41_[0] } ) , - .sram ( mux_tree_tapbuf_size7_3_sram ) , - .sram_inv ( mux_left_track_33_undriven_sram_inv ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_148 ) ) ; -sb_1__1__mux_tree_tapbuf_size7_mem mem_top_track_32 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size7_mem_2 mem_right_track_32 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size7_mem_0 mem_bottom_track_33 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size7_mem_1 mem_left_track_33 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , - .ccff_tail ( { ropt_net_155 } ) , - .mem_out ( mux_tree_tapbuf_size7_3_sram ) ) ; -sky130_fd_sc_hd__conb_1 optlc_140 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_145 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_142 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_146 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__2 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_179 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_top_in[6] ) , - .X ( ropt_net_194 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chany_top_in[8] ) , - .X ( ropt_net_178 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chany_top_in[9] ) , - .X ( ropt_net_170 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_top_in[10] ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chany_top_in[12] ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__8 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_174 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chany_top_in[14] ) , - .X ( ropt_net_196 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__10 ( .A ( chany_top_in[16] ) , - .X ( ropt_net_166 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__11 ( .A ( chany_top_in[17] ) , - .X ( ropt_net_197 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__12 ( .A ( chany_top_in[18] ) , - .X ( ropt_net_189 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_855 ( .A ( ropt_net_200 ) , - .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_144 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_147 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_146 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_148 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , - .HI ( optlc_net_149 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_198 ) ) ; -sky130_fd_sc_hd__clkbuf_1 \prog_clk[0]_bip415 ( .A ( prog_clk[0] ) , - .X ( ctsbuf_net_1151 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_20__19 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_192 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_right_in[12] ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( chanx_left_in[14] ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_23__22 ( .A ( chanx_right_in[14] ) , - .X ( ropt_net_173 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chanx_right_in[16] ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_25__24 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_184 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_26__25 ( .A ( chanx_right_in[18] ) , - .X ( ropt_net_165 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chany_bottom_in[2] ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_28__27 ( .A ( chany_bottom_in[4] ) , - .X ( ropt_net_171 ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_359774 ( .A ( ctsbuf_net_1151 ) , - .X ( prog_clk__FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_802 ( .A ( chanx_left_in[5] ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_856 ( .A ( ropt_net_201 ) , - .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_32__31 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_187 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_33__32 ( .A ( chany_bottom_in[10] ) , - .X ( ropt_net_193 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_154 ) , - .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_35__34 ( .A ( chany_bottom_in[13] ) , - .X ( ropt_net_199 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_804 ( .A ( ropt_net_155 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_37__36 ( .A ( chany_bottom_in[16] ) , - .X ( ropt_net_186 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_858 ( .A ( ropt_net_202 ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_39__38 ( .A ( chany_bottom_in[18] ) , - .X ( ropt_net_182 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( - .A ( Test_en__FEEDTHRU_0[0] ) , .X ( ropt_net_225 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( chanx_right_in[4] ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_807 ( .A ( ropt_net_158 ) , - .X ( ropt_net_224 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_808 ( .A ( chanx_right_in[5] ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( chanx_right_in[2] ) , - .X ( ropt_net_201 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_810 ( .A ( chany_bottom_in[6] ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_46__45 ( .A ( chanx_left_in[10] ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_47__46 ( .A ( chanx_left_in[12] ) , - .X ( ropt_net_185 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_48__47 ( .A ( chanx_left_in[13] ) , - .X ( ropt_net_169 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_811 ( .A ( chany_bottom_in[5] ) , - .X ( ropt_net_227 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_50__49 ( .A ( chanx_left_in[16] ) , - .X ( ropt_net_181 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_51__50 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_183 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_52__51 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_172 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_860 ( .A ( ropt_net_203 ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_812 ( - .A ( chany_bottom_in[17] ) , .X ( ropt_net_226 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_85 ( .A ( chany_top_in[4] ) , - .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_861 ( .A ( ropt_net_204 ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_862 ( .A ( ropt_net_205 ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_88 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_176 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( chanx_left_in[2] ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_165 ) , - .X ( ropt_net_210 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_91 ( .A ( chany_bottom_in[8] ) , - .X ( ropt_net_154 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_863 ( .A ( ropt_net_206 ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_166 ) , - .X ( ropt_net_223 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_167 ) , - .X ( ropt_net_206 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_95 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_180 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_96 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_177 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_97 ( .A ( chanx_left_in[9] ) , - .X ( ropt_net_168 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_864 ( .A ( ropt_net_207 ) , - .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_817 ( .A ( ropt_net_168 ) , - .X ( ropt_net_220 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_169 ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_170 ) , - .X ( ropt_net_208 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_171 ) , - .X ( ropt_net_200 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_172 ) , - .X ( ropt_net_215 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_108 ( .A ( chanx_left_in[4] ) , - .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_173 ) , - .X ( ropt_net_207 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_174 ) , - .X ( ropt_net_216 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_175 ) , - .X ( ropt_net_204 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_119 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_195 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_120 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_191 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_121 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_167 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_122 ( .A ( chany_bottom_in[12] ) , - .X ( ropt_net_188 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_123 ( .A ( chany_bottom_in[14] ) , - .X ( ropt_net_175 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_865 ( .A ( ropt_net_208 ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( ropt_net_176 ) , - .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_867 ( .A ( ropt_net_209 ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_868 ( .A ( ropt_net_210 ) , - .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_826 ( .A ( ropt_net_177 ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_871 ( .A ( ropt_net_211 ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_875 ( .A ( ropt_net_212 ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_876 ( .A ( ropt_net_213 ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_827 ( .A ( ropt_net_178 ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_136 ( - .A ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] ) , - .X ( ropt_net_190 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_179 ) , - .X ( ropt_net_219 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_829 ( .A ( ropt_net_180 ) , - .X ( ropt_net_209 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_181 ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_182 ) , - .X ( ropt_net_214 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_832 ( .A ( ropt_net_183 ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_833 ( .A ( ropt_net_184 ) , - .X ( ropt_net_222 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_834 ( .A ( ropt_net_185 ) , - .X ( ropt_net_218 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_835 ( .A ( ropt_net_186 ) , - .X ( ropt_net_205 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_836 ( .A ( ropt_net_187 ) , - .X ( ropt_net_211 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_837 ( .A ( ropt_net_188 ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_838 ( .A ( ropt_net_189 ) , - .X ( ropt_net_203 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_839 ( .A ( ropt_net_190 ) , - .X ( ropt_net_221 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_840 ( .A ( ropt_net_191 ) , - .X ( ropt_net_212 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_841 ( .A ( ropt_net_192 ) , - .X ( ropt_net_213 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_842 ( .A ( ropt_net_193 ) , - .X ( ropt_net_217 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_843 ( .A ( ropt_net_194 ) , - .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_844 ( .A ( ropt_net_195 ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_845 ( .A ( ropt_net_196 ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_846 ( .A ( ropt_net_197 ) , - .X ( ropt_net_202 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_849 ( .A ( ropt_net_198 ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_851 ( .A ( ropt_net_199 ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_878 ( .A ( ropt_net_214 ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_880 ( .A ( ropt_net_215 ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_881 ( .A ( ropt_net_216 ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_882 ( .A ( ropt_net_217 ) , - .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_883 ( .A ( ropt_net_218 ) , - .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_885 ( .A ( ropt_net_219 ) , - .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_886 ( .A ( ropt_net_220 ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_887 ( .A ( ropt_net_221 ) , - .X ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_888 ( .A ( ropt_net_222 ) , - .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_890 ( .A ( ropt_net_223 ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_893 ( .A ( ropt_net_224 ) , - .X ( chanx_left_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_897 ( .A ( ropt_net_225 ) , - .X ( Test_en__FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_898 ( .A ( ropt_net_226 ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_899 ( .A ( ropt_net_227 ) , - .X ( chany_top_out[6] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__60 ( .A ( mem_out[2] ) , - .X ( net_net_84 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_84 ( .A ( net_net_84 ) , - .X ( net_net_83 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_103 ( .A ( net_net_83 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__59 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__58 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__57 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size11_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__56 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size11_mem ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__55 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size11_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:10] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[10] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size11 ( in , sram , sram_inv , out , p0 ) ; -input [0:10] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[10] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__54 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__53 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size3_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__52 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size3_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__51 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__50 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__49 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__48 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__47 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size3_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size3_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__46 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__45 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__44 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__43 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__42 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__41 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__40 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__39 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__38 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__37 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__36 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_7 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__35 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__34 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__33 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module sb_1__0_ ( prog_clk , chany_top_in , top_left_grid_pin_42_ , - top_left_grid_pin_43_ , top_left_grid_pin_44_ , top_left_grid_pin_45_ , - top_left_grid_pin_46_ , top_left_grid_pin_47_ , top_left_grid_pin_48_ , - top_left_grid_pin_49_ , chanx_right_in , right_bottom_grid_pin_1_ , - right_bottom_grid_pin_3_ , right_bottom_grid_pin_5_ , - right_bottom_grid_pin_7_ , right_bottom_grid_pin_9_ , - right_bottom_grid_pin_11_ , chanx_left_in , left_bottom_grid_pin_1_ , - left_bottom_grid_pin_3_ , left_bottom_grid_pin_5_ , - left_bottom_grid_pin_7_ , left_bottom_grid_pin_9_ , - left_bottom_grid_pin_11_ , ccff_head , chany_top_out , chanx_right_out , - chanx_left_out , ccff_tail , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , - SC_OUT_BOT , prog_clk__FEEDTHRU_1 , prog_clk__FEEDTHRU_2 ) ; -input [0:0] prog_clk ; -input [0:19] chany_top_in ; -input [0:0] top_left_grid_pin_42_ ; -input [0:0] top_left_grid_pin_43_ ; -input [0:0] top_left_grid_pin_44_ ; -input [0:0] top_left_grid_pin_45_ ; -input [0:0] top_left_grid_pin_46_ ; -input [0:0] top_left_grid_pin_47_ ; -input [0:0] top_left_grid_pin_48_ ; -input [0:0] top_left_grid_pin_49_ ; -input [0:19] chanx_right_in ; -input [0:0] right_bottom_grid_pin_1_ ; -input [0:0] right_bottom_grid_pin_3_ ; -input [0:0] right_bottom_grid_pin_5_ ; -input [0:0] right_bottom_grid_pin_7_ ; -input [0:0] right_bottom_grid_pin_9_ ; -input [0:0] right_bottom_grid_pin_11_ ; -input [0:19] chanx_left_in ; -input [0:0] left_bottom_grid_pin_1_ ; -input [0:0] left_bottom_grid_pin_3_ ; -input [0:0] left_bottom_grid_pin_5_ ; -input [0:0] left_bottom_grid_pin_7_ ; -input [0:0] left_bottom_grid_pin_9_ ; -input [0:0] left_bottom_grid_pin_11_ ; -input [0:0] ccff_head ; -output [0:19] chany_top_out ; -output [0:19] chanx_right_out ; -output [0:19] chanx_left_out ; -output [0:0] ccff_tail ; -input SC_IN_TOP ; -input SC_IN_BOT ; -output SC_OUT_TOP ; -output SC_OUT_BOT ; -output [0:0] prog_clk__FEEDTHRU_1 ; -output [0:0] prog_clk__FEEDTHRU_2 ; - -wire [0:2] mux_left_track_17_undriven_sram_inv ; -wire [0:3] mux_left_track_1_undriven_sram_inv ; -wire [0:2] mux_left_track_25_undriven_sram_inv ; -wire [0:2] mux_left_track_33_undriven_sram_inv ; -wire [0:2] mux_left_track_3_undriven_sram_inv ; -wire [0:3] mux_left_track_5_undriven_sram_inv ; -wire [0:2] mux_left_track_9_undriven_sram_inv ; -wire [0:2] mux_right_track_0_undriven_sram_inv ; -wire [0:2] mux_right_track_16_undriven_sram_inv ; -wire [0:2] mux_right_track_24_undriven_sram_inv ; -wire [0:3] mux_right_track_2_undriven_sram_inv ; -wire [0:2] mux_right_track_32_undriven_sram_inv ; -wire [0:3] mux_right_track_4_undriven_sram_inv ; -wire [0:2] mux_right_track_8_undriven_sram_inv ; -wire [0:3] mux_top_track_0_undriven_sram_inv ; -wire [0:2] mux_top_track_10_undriven_sram_inv ; -wire [0:1] mux_top_track_12_undriven_sram_inv ; -wire [0:1] mux_top_track_14_undriven_sram_inv ; -wire [0:1] mux_top_track_16_undriven_sram_inv ; -wire [0:1] mux_top_track_18_undriven_sram_inv ; -wire [0:1] mux_top_track_20_undriven_sram_inv ; -wire [0:1] mux_top_track_22_undriven_sram_inv ; -wire [0:1] mux_top_track_24_undriven_sram_inv ; -wire [0:2] mux_top_track_2_undriven_sram_inv ; -wire [0:1] mux_top_track_38_undriven_sram_inv ; -wire [0:2] mux_top_track_4_undriven_sram_inv ; -wire [0:2] mux_top_track_6_undriven_sram_inv ; -wire [0:2] mux_top_track_8_undriven_sram_inv ; -wire [0:3] mux_tree_tapbuf_size11_0_sram ; -wire [0:3] mux_tree_tapbuf_size11_1_sram ; -wire [0:0] mux_tree_tapbuf_size11_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size11_mem_1_ccff_tail ; -wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; -wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:1] mux_tree_tapbuf_size3_2_sram ; -wire [0:1] mux_tree_tapbuf_size3_3_sram ; -wire [0:1] mux_tree_tapbuf_size3_4_sram ; -wire [0:1] mux_tree_tapbuf_size3_5_sram ; -wire [0:1] mux_tree_tapbuf_size3_6_sram ; -wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size4_0_sram ; -wire [0:2] mux_tree_tapbuf_size4_1_sram ; -wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size5_0_sram ; -wire [0:2] mux_tree_tapbuf_size5_1_sram ; -wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size6_1_sram ; -wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size7_0_sram ; -wire [0:2] mux_tree_tapbuf_size7_1_sram ; -wire [0:2] mux_tree_tapbuf_size7_2_sram ; -wire [0:2] mux_tree_tapbuf_size7_3_sram ; -wire [0:2] mux_tree_tapbuf_size7_4_sram ; -wire [0:2] mux_tree_tapbuf_size7_5_sram ; -wire [0:2] mux_tree_tapbuf_size7_6_sram ; -wire [0:2] mux_tree_tapbuf_size7_7_sram ; -wire [0:2] mux_tree_tapbuf_size7_8_sram ; -wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_7_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_8_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:3] mux_tree_tapbuf_size8_2_sram ; -wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; - -assign SC_IN_TOP = SC_IN_BOT ; -assign prog_clk__FEEDTHRU_1[0] = prog_clk__FEEDTHRU_2[0] ; - -sb_1__0__mux_tree_tapbuf_size8 mux_top_track_0 ( - .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , - top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , - chanx_right_in[1] , chanx_right_in[2] , chanx_left_in[0] , - chanx_left_in[2] } ) , - .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_top_track_0_undriven_sram_inv ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_120 ) ) ; -sb_1__0__mux_tree_tapbuf_size8_1 mux_right_track_2 ( - .in ( { chany_top_in[0] , chany_top_in[7] , chany_top_in[14] , - right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_7_[0] , - right_bottom_grid_pin_11_[0] , chanx_left_in[4] , chanx_left_in[13] } ) , - .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_right_track_2_undriven_sram_inv ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_123 ) ) ; -sb_1__0__mux_tree_tapbuf_size8_0 mux_left_track_1 ( - .in ( { chany_top_in[0] , chany_top_in[7] , chany_top_in[14] , - chanx_right_in[2] , chanx_right_in[12] , left_bottom_grid_pin_1_[0] , - left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] } ) , - .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_left_track_1_undriven_sram_inv ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_120 ) ) ; -sb_1__0__mux_tree_tapbuf_size8_mem mem_top_track_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size8_mem_1 mem_right_track_2 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size8_mem_0 mem_left_track_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size7_6 mux_top_track_2 ( - .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , - top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , - chanx_right_in[3] , chanx_right_in[4] , chanx_left_in[4] } ) , - .sram ( mux_tree_tapbuf_size7_0_sram ) , - .sram_inv ( mux_top_track_2_undriven_sram_inv ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_121 ) ) ; -sb_1__0__mux_tree_tapbuf_size7_7 mux_top_track_4 ( - .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , - top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , - chanx_right_in[5] , chanx_right_in[7] , chanx_left_in[5] } ) , - .sram ( mux_tree_tapbuf_size7_1_sram ) , - .sram_inv ( mux_top_track_4_undriven_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_122 ) ) ; -sb_1__0__mux_tree_tapbuf_size7 mux_top_track_6 ( - .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , - top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , - chanx_right_in[6] , chanx_right_in[11] , chanx_left_in[6] } ) , - .sram ( mux_tree_tapbuf_size7_2_sram ) , - .sram_inv ( mux_top_track_6_undriven_sram_inv ) , - .out ( chany_top_out[3] ) , .p0 ( optlc_net_122 ) ) ; -sb_1__0__mux_tree_tapbuf_size7_3 mux_right_track_0 ( - .in ( { chany_top_in[6] , chany_top_in[13] , right_bottom_grid_pin_1_[0] , - right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] , - chanx_left_in[2] , chanx_left_in[12] } ) , - .sram ( mux_tree_tapbuf_size7_3_sram ) , - .sram_inv ( mux_right_track_0_undriven_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_121 ) ) ; -sb_1__0__mux_tree_tapbuf_size7_5 mux_right_track_8 ( - .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , - right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_9_[0] , - chanx_left_in[6] , chanx_left_in[16] } ) , - .sram ( mux_tree_tapbuf_size7_4_sram ) , - .sram_inv ( mux_right_track_8_undriven_sram_inv ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_124 ) ) ; -sb_1__0__mux_tree_tapbuf_size7_4 mux_right_track_16 ( - .in ( { chany_top_in[3] , chany_top_in[10] , chany_top_in[17] , - right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_11_[0] , - chanx_left_in[8] , chanx_left_in[17] } ) , - .sram ( mux_tree_tapbuf_size7_5_sram ) , - .sram_inv ( mux_right_track_16_undriven_sram_inv ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_124 ) ) ; -sb_1__0__mux_tree_tapbuf_size7_1 mux_left_track_3 ( - .in ( { chany_top_in[6] , chany_top_in[13] , chanx_right_in[4] , - chanx_right_in[13] , left_bottom_grid_pin_3_[0] , - left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] } ) , - .sram ( mux_tree_tapbuf_size7_6_sram ) , - .sram_inv ( mux_left_track_3_undriven_sram_inv ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_120 ) ) ; -sb_1__0__mux_tree_tapbuf_size7_2 mux_left_track_9 ( - .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , - chanx_right_in[6] , chanx_right_in[16] , left_bottom_grid_pin_1_[0] , - left_bottom_grid_pin_9_[0] } ) , - .sram ( mux_tree_tapbuf_size7_7_sram ) , - .sram_inv ( mux_left_track_9_undriven_sram_inv ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_120 ) ) ; -sb_1__0__mux_tree_tapbuf_size7_0 mux_left_track_17 ( - .in ( { chany_top_in[3] , chany_top_in[10] , chany_top_in[17] , - chanx_right_in[8] , chanx_right_in[17] , left_bottom_grid_pin_3_[0] , - left_bottom_grid_pin_11_[0] } ) , - .sram ( mux_tree_tapbuf_size7_8_sram ) , - .sram_inv ( mux_left_track_17_undriven_sram_inv ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_120 ) ) ; -sb_1__0__mux_tree_tapbuf_size7_mem_6 mem_top_track_2 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size7_mem_7 mem_top_track_4 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size7_mem mem_top_track_6 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size7_mem_3 mem_right_track_0 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_3_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size7_mem_5 mem_right_track_8 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size11_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_4_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size7_mem_4 mem_right_track_16 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_5_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size7_mem_1 mem_left_track_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_6_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size7_mem_2 mem_left_track_9 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size11_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_7_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size7_mem_0 mem_left_track_17 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_8_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_8_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size4 mux_top_track_8 ( - .in ( { top_left_grid_pin_42_[0] , chanx_right_in[8] , - chanx_right_in[15] , chanx_left_in[8] } ) , - .sram ( mux_tree_tapbuf_size4_0_sram ) , - .sram_inv ( mux_top_track_8_undriven_sram_inv ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_122 ) ) ; -sb_1__0__mux_tree_tapbuf_size4_0 mux_top_track_10 ( - .in ( { top_left_grid_pin_43_[0] , chanx_right_in[9] , - chanx_right_in[19] , chanx_left_in[9] } ) , - .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_top_track_10_undriven_sram_inv ) , - .out ( chany_top_out[5] ) , .p0 ( optlc_net_124 ) ) ; -sb_1__0__mux_tree_tapbuf_size4_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size4_mem_0 mem_top_track_10 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size3_0 mux_top_track_12 ( - .in ( { top_left_grid_pin_44_[0] , chanx_right_in[10] , - chanx_left_in[10] } ) , - .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_top_track_12_undriven_sram_inv ) , - .out ( chany_top_out[6] ) , .p0 ( optlc_net_121 ) ) ; -sb_1__0__mux_tree_tapbuf_size3_1 mux_top_track_14 ( - .in ( { top_left_grid_pin_45_[0] , chanx_right_in[12] , - chanx_left_in[12] } ) , - .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_top_track_14_undriven_sram_inv ) , - .out ( chany_top_out[7] ) , .p0 ( optlc_net_121 ) ) ; -sb_1__0__mux_tree_tapbuf_size3_2 mux_top_track_16 ( - .in ( { top_left_grid_pin_46_[0] , chanx_right_in[13] , - chanx_left_in[13] } ) , - .sram ( mux_tree_tapbuf_size3_2_sram ) , - .sram_inv ( mux_top_track_16_undriven_sram_inv ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_120 ) ) ; -sb_1__0__mux_tree_tapbuf_size3_3 mux_top_track_18 ( - .in ( { top_left_grid_pin_47_[0] , chanx_right_in[14] , - chanx_left_in[14] } ) , - .sram ( mux_tree_tapbuf_size3_3_sram ) , - .sram_inv ( mux_top_track_18_undriven_sram_inv ) , - .out ( chany_top_out[9] ) , .p0 ( optlc_net_121 ) ) ; -sb_1__0__mux_tree_tapbuf_size3_4 mux_top_track_20 ( - .in ( { top_left_grid_pin_48_[0] , chanx_right_in[16] , - chanx_left_in[16] } ) , - .sram ( mux_tree_tapbuf_size3_4_sram ) , - .sram_inv ( mux_top_track_20_undriven_sram_inv ) , - .out ( chany_top_out[10] ) , .p0 ( optlc_net_122 ) ) ; -sb_1__0__mux_tree_tapbuf_size3_5 mux_top_track_22 ( - .in ( { top_left_grid_pin_49_[0] , chanx_right_in[17] , - chanx_left_in[17] } ) , - .sram ( mux_tree_tapbuf_size3_5_sram ) , - .sram_inv ( mux_top_track_22_undriven_sram_inv ) , - .out ( chany_top_out[11] ) , .p0 ( optlc_net_122 ) ) ; -sb_1__0__mux_tree_tapbuf_size3 mux_top_track_24 ( - .in ( { top_left_grid_pin_42_[0] , chanx_right_in[18] , - chanx_left_in[18] } ) , - .sram ( mux_tree_tapbuf_size3_6_sram ) , - .sram_inv ( mux_top_track_24_undriven_sram_inv ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_121 ) ) ; -sb_1__0__mux_tree_tapbuf_size3_mem_0 mem_top_track_12 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size3_mem_1 mem_top_track_14 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size3_mem_2 mem_top_track_16 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size3_mem_3 mem_top_track_18 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size3_mem_4 mem_top_track_20 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_4_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size3_mem_5 mem_top_track_22 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_5_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size3_mem mem_top_track_24 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_6_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size2 mux_top_track_38 ( - .in ( { chanx_right_in[0] , chanx_left_in[1] } ) , - .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_top_track_38_undriven_sram_inv ) , - .out ( chany_top_out[19] ) , .p0 ( optlc_net_121 ) ) ; -sb_1__0__mux_tree_tapbuf_size2_mem mem_top_track_38 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size11 mux_right_track_4 ( - .in ( { chany_top_in[1] , chany_top_in[8] , chany_top_in[15] , - right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_3_[0] , - right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_7_[0] , - right_bottom_grid_pin_9_[0] , right_bottom_grid_pin_11_[0] , - chanx_left_in[5] , chanx_left_in[14] } ) , - .sram ( mux_tree_tapbuf_size11_0_sram ) , - .sram_inv ( mux_right_track_4_undriven_sram_inv ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_123 ) ) ; -sb_1__0__mux_tree_tapbuf_size11_0 mux_left_track_5 ( - .in ( { chany_top_in[5] , chany_top_in[12] , chany_top_in[19] , - chanx_right_in[5] , chanx_right_in[14] , left_bottom_grid_pin_1_[0] , - left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_5_[0] , - left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_9_[0] , - left_bottom_grid_pin_11_[0] } ) , - .sram ( mux_tree_tapbuf_size11_1_sram ) , - .sram_inv ( mux_left_track_5_undriven_sram_inv ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_120 ) ) ; -sb_1__0__mux_tree_tapbuf_size11_mem mem_right_track_4 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size11_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size11_0_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size11_mem_0 mem_left_track_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size11_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size11_1_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size6 mux_right_track_24 ( - .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , - right_bottom_grid_pin_5_[0] , chanx_left_in[9] , chanx_left_in[18] } ) , - .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_right_track_24_undriven_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_124 ) ) ; -sb_1__0__mux_tree_tapbuf_size6_0 mux_left_track_25 ( - .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , - chanx_right_in[9] , chanx_right_in[18] , left_bottom_grid_pin_5_[0] } ) , - .sram ( mux_tree_tapbuf_size6_1_sram ) , - .sram_inv ( mux_left_track_25_undriven_sram_inv ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_122 ) ) ; -sb_1__0__mux_tree_tapbuf_size6_mem mem_right_track_24 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size6_mem_0 mem_left_track_25 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_8_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size5 mux_right_track_32 ( - .in ( { chany_top_in[5] , chany_top_in[12] , chany_top_in[19] , - right_bottom_grid_pin_7_[0] , chanx_left_in[10] } ) , - .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_right_track_32_undriven_sram_inv ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_121 ) ) ; -sb_1__0__mux_tree_tapbuf_size5_0 mux_left_track_33 ( - .in ( { chany_top_in[1] , chany_top_in[8] , chany_top_in[15] , - chanx_right_in[10] , left_bottom_grid_pin_7_[0] } ) , - .sram ( mux_tree_tapbuf_size5_1_sram ) , - .sram_inv ( mux_left_track_33_undriven_sram_inv ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_120 ) ) ; -sb_1__0__mux_tree_tapbuf_size5_mem mem_right_track_32 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size5_mem_0 mem_left_track_33 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .ccff_tail ( { ropt_net_147 } ) , - .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ; -sky130_fd_sc_hd__conb_1 optlc_114 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_120 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chanx_right_in[2] ) , - .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_145 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__3 ( .A ( chanx_right_in[5] ) , - .X ( ropt_net_154 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_121 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_161 ) , - .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_122 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_121 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_123 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__8 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_158 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_162 ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__10 ( .A ( chanx_right_in[14] ) , - .X ( ropt_net_151 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_123 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , - .HI ( optlc_net_124 ) ) ; -sky130_fd_sc_hd__clkbuf_1 \prog_clk[0]_bip390 ( .A ( prog_clk[0] ) , - .X ( \prog_clk__FEEDTHRU_2[0]0 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( .A ( ropt_net_129 ) , - .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chanx_left_in[2] ) , - .X ( ropt_net_152 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_165 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( chanx_left_in[19] ) , - .X ( ropt_net_169 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chanx_left_in[5] ) , - .X ( ropt_net_150 ) ) ; -sky130_fd_sc_hd__buf_8 cts_buf_368758 ( .A ( \prog_clk__FEEDTHRU_2[0]0 ) , - .X ( prog_clk__FEEDTHRU_2[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_784 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_179 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_785 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_175 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__21 ( .A ( chanx_left_in[9] ) , - .X ( ropt_net_148 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chanx_left_in[10] ) , - .X ( ropt_net_155 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_134 ) , - .X ( ropt_net_171 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_787 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_176 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_788 ( .A ( chanx_left_in[12] ) , - .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_137 ) , - .X ( ropt_net_163 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( chanx_right_in[18] ) , - .X ( ropt_net_174 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_821 ( .A ( ropt_net_163 ) , - .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_822 ( .A ( ropt_net_164 ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( chanx_left_in[13] ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( chanx_left_in[16] ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_129 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( chanx_right_in[6] ) , - .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_178 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_823 ( .A ( ropt_net_165 ) , - .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_166 ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_825 ( .A ( ropt_net_167 ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_826 ( .A ( ropt_net_168 ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_70 ( .A ( chanx_left_in[3] ) , - .X ( ropt_net_143 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_71 ( .A ( chanx_left_in[4] ) , - .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_72 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_157 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_73 ( .A ( chanx_left_in[7] ) , - .X ( ropt_net_160 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_74 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_156 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_75 ( .A ( chanx_left_in[11] ) , - .X ( ropt_net_137 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_827 ( .A ( ropt_net_169 ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_170 ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_78 ( .A ( chanx_left_in[14] ) , - .X ( ropt_net_159 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_79 ( .A ( chanx_left_in[15] ) , - .X ( ropt_net_146 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_143 ) , - .X ( ropt_net_164 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_830 ( .A ( ropt_net_171 ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_832 ( .A ( ropt_net_172 ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_177 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( ropt_net_145 ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_146 ) , - .X ( ropt_net_167 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_147 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_148 ) , - .X ( ropt_net_172 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_149 ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_150 ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_833 ( .A ( ropt_net_173 ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_99 ( .A ( top_left_grid_pin_43_[0] ) , - .X ( ropt_net_149 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_837 ( .A ( ropt_net_174 ) , - .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_151 ) , - .X ( ropt_net_161 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_105 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_153 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_152 ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_107 ( .A ( chanx_right_in[16] ) , - .X ( ropt_net_134 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_153 ) , - .X ( ropt_net_162 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_154 ) , - .X ( ropt_net_166 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_155 ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_156 ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_157 ) , - .X ( ropt_net_173 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_810 ( .A ( ropt_net_158 ) , - .X ( ropt_net_170 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_159 ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_160 ) , - .X ( ropt_net_168 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_838 ( .A ( ropt_net_175 ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_839 ( .A ( ropt_net_176 ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_840 ( .A ( ropt_net_177 ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_841 ( .A ( ropt_net_178 ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_842 ( .A ( ropt_net_179 ) , - .X ( chanx_right_out[19] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_24__40 ( .A ( mem_out[1] ) , - .X ( net_net_64 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_89 ( .A ( net_net_64 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__39 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__38 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__37 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__36 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__35 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__34 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__33 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__32 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__31 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__30 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__29 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__28 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__27 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__26 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__25 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__24 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__23 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_43 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__22 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__21 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__20 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__19 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__18 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__17 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module sb_0__2_ ( prog_clk , chanx_right_in , right_top_grid_pin_1_ , - right_bottom_grid_pin_34_ , right_bottom_grid_pin_35_ , - right_bottom_grid_pin_36_ , right_bottom_grid_pin_37_ , - right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ , - right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ , chany_bottom_in , - bottom_left_grid_pin_1_ , ccff_head , chanx_right_out , chany_bottom_out , - ccff_tail , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , SC_OUT_BOT ) ; -input [0:0] prog_clk ; -input [0:19] chanx_right_in ; -input [0:0] right_top_grid_pin_1_ ; -input [0:0] right_bottom_grid_pin_34_ ; -input [0:0] right_bottom_grid_pin_35_ ; -input [0:0] right_bottom_grid_pin_36_ ; -input [0:0] right_bottom_grid_pin_37_ ; -input [0:0] right_bottom_grid_pin_38_ ; -input [0:0] right_bottom_grid_pin_39_ ; -input [0:0] right_bottom_grid_pin_40_ ; -input [0:0] right_bottom_grid_pin_41_ ; -input [0:19] chany_bottom_in ; -input [0:0] bottom_left_grid_pin_1_ ; -input [0:0] ccff_head ; -output [0:19] chanx_right_out ; -output [0:19] chany_bottom_out ; -output [0:0] ccff_tail ; -input SC_IN_TOP ; -input SC_IN_BOT ; -output SC_OUT_TOP ; -output SC_OUT_BOT ; - -wire [0:1] mux_bottom_track_1_undriven_sram_inv ; -wire [0:1] mux_bottom_track_25_undriven_sram_inv ; -wire [0:1] mux_bottom_track_5_undriven_sram_inv ; -wire [0:1] mux_bottom_track_9_undriven_sram_inv ; -wire [0:2] mux_right_track_0_undriven_sram_inv ; -wire [0:1] mux_right_track_10_undriven_sram_inv ; -wire [0:1] mux_right_track_12_undriven_sram_inv ; -wire [0:1] mux_right_track_14_undriven_sram_inv ; -wire [0:1] mux_right_track_16_undriven_sram_inv ; -wire [0:1] mux_right_track_18_undriven_sram_inv ; -wire [0:1] mux_right_track_20_undriven_sram_inv ; -wire [0:1] mux_right_track_22_undriven_sram_inv ; -wire [0:1] mux_right_track_24_undriven_sram_inv ; -wire [0:1] mux_right_track_26_undriven_sram_inv ; -wire [0:1] mux_right_track_28_undriven_sram_inv ; -wire [0:2] mux_right_track_2_undriven_sram_inv ; -wire [0:1] mux_right_track_30_undriven_sram_inv ; -wire [0:1] mux_right_track_32_undriven_sram_inv ; -wire [0:1] mux_right_track_34_undriven_sram_inv ; -wire [0:1] mux_right_track_36_undriven_sram_inv ; -wire [0:1] mux_right_track_38_undriven_sram_inv ; -wire [0:2] mux_right_track_4_undriven_sram_inv ; -wire [0:2] mux_right_track_6_undriven_sram_inv ; -wire [0:1] mux_right_track_8_undriven_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_10_sram ; -wire [0:1] mux_tree_tapbuf_size2_11_sram ; -wire [0:1] mux_tree_tapbuf_size2_12_sram ; -wire [0:1] mux_tree_tapbuf_size2_13_sram ; -wire [0:1] mux_tree_tapbuf_size2_14_sram ; -wire [0:1] mux_tree_tapbuf_size2_15_sram ; -wire [0:1] mux_tree_tapbuf_size2_16_sram ; -wire [0:1] mux_tree_tapbuf_size2_17_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_5_sram ; -wire [0:1] mux_tree_tapbuf_size2_6_sram ; -wire [0:1] mux_tree_tapbuf_size2_7_sram ; -wire [0:1] mux_tree_tapbuf_size2_8_sram ; -wire [0:1] mux_tree_tapbuf_size2_9_sram ; -wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; -wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size5_0_sram ; -wire [0:2] mux_tree_tapbuf_size5_1_sram ; -wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size6_1_sram ; -wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; - -assign SC_IN_TOP = SC_IN_BOT ; - -sb_0__2__mux_tree_tapbuf_size6_0 mux_right_track_0 ( - .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] , - right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , - right_bottom_grid_pin_41_[0] , chany_bottom_in[18] } ) , - .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_right_track_0_undriven_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_114 ) ) ; -sb_0__2__mux_tree_tapbuf_size6 mux_right_track_4 ( - .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] , - right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , - right_bottom_grid_pin_41_[0] , chany_bottom_in[16] } ) , - .sram ( mux_tree_tapbuf_size6_1_sram ) , - .sram_inv ( mux_right_track_4_undriven_sram_inv ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_115 ) ) ; -sb_0__2__mux_tree_tapbuf_size6_mem_0 mem_right_track_0 ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size6_mem mem_right_track_4 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size5_0 mux_right_track_2 ( - .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , - right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , - chany_bottom_in[17] } ) , - .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_right_track_2_undriven_sram_inv ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_116 ) ) ; -sb_0__2__mux_tree_tapbuf_size5 mux_right_track_6 ( - .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , - right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , - chany_bottom_in[15] } ) , - .sram ( mux_tree_tapbuf_size5_1_sram ) , - .sram_inv ( mux_right_track_6_undriven_sram_inv ) , - .out ( chanx_right_out[3] ) , .p0 ( optlc_net_116 ) ) ; -sb_0__2__mux_tree_tapbuf_size5_mem_0 mem_right_track_2 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size5_mem mem_right_track_6 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size3 mux_right_track_8 ( - .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_41_[0] , - chany_bottom_in[14] } ) , - .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_right_track_8_undriven_sram_inv ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_116 ) ) ; -sb_0__2__mux_tree_tapbuf_size3_0 mux_right_track_24 ( - .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_41_[0] , - chany_bottom_in[6] } ) , - .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_right_track_24_undriven_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_116 ) ) ; -sb_0__2__mux_tree_tapbuf_size3_mem mem_right_track_8 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size3_mem_0 mem_right_track_24 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size2_4 mux_right_track_10 ( - .in ( { right_bottom_grid_pin_34_[0] , chany_bottom_in[13] } ) , - .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_right_track_10_undriven_sram_inv ) , - .out ( chanx_right_out[5] ) , .p0 ( optlc_net_116 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_5 mux_right_track_12 ( - .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[12] } ) , - .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_right_track_12_undriven_sram_inv ) , - .out ( chanx_right_out[6] ) , .p0 ( optlc_net_114 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_6 mux_right_track_14 ( - .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[11] } ) , - .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_right_track_14_undriven_sram_inv ) , - .out ( chanx_right_out[7] ) , .p0 ( optlc_net_115 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_7 mux_right_track_16 ( - .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[10] } ) , - .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_right_track_16_undriven_sram_inv ) , - .out ( { ropt_net_125 } ) , - .p0 ( optlc_net_117 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_8 mux_right_track_18 ( - .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[9] } ) , - .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_right_track_18_undriven_sram_inv ) , - .out ( chanx_right_out[9] ) , .p0 ( optlc_net_117 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_9 mux_right_track_20 ( - .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[8] } ) , - .sram ( mux_tree_tapbuf_size2_5_sram ) , - .sram_inv ( mux_right_track_20_undriven_sram_inv ) , - .out ( chanx_right_out[10] ) , .p0 ( optlc_net_114 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_10 mux_right_track_22 ( - .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[7] } ) , - .sram ( mux_tree_tapbuf_size2_6_sram ) , - .sram_inv ( mux_right_track_22_undriven_sram_inv ) , - .out ( chanx_right_out[11] ) , .p0 ( optlc_net_114 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_11 mux_right_track_26 ( - .in ( { right_bottom_grid_pin_34_[0] , chany_bottom_in[5] } ) , - .sram ( mux_tree_tapbuf_size2_7_sram ) , - .sram_inv ( mux_right_track_26_undriven_sram_inv ) , - .out ( chanx_right_out[13] ) , .p0 ( optlc_net_115 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_12 mux_right_track_28 ( - .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[4] } ) , - .sram ( mux_tree_tapbuf_size2_8_sram ) , - .sram_inv ( mux_right_track_28_undriven_sram_inv ) , - .out ( { ropt_net_122 } ) , - .p0 ( optlc_net_117 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_13 mux_right_track_30 ( - .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[3] } ) , - .sram ( mux_tree_tapbuf_size2_9_sram ) , - .sram_inv ( mux_right_track_30_undriven_sram_inv ) , - .out ( chanx_right_out[15] ) , .p0 ( optlc_net_117 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_14 mux_right_track_32 ( - .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[2] } ) , - .sram ( mux_tree_tapbuf_size2_10_sram ) , - .sram_inv ( mux_right_track_32_undriven_sram_inv ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_117 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_15 mux_right_track_34 ( - .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[1] } ) , - .sram ( mux_tree_tapbuf_size2_11_sram ) , - .sram_inv ( mux_right_track_34_undriven_sram_inv ) , - .out ( chanx_right_out[17] ) , .p0 ( optlc_net_117 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_16 mux_right_track_36 ( - .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[0] } ) , - .sram ( mux_tree_tapbuf_size2_12_sram ) , - .sram_inv ( mux_right_track_36_undriven_sram_inv ) , - .out ( chanx_right_out[18] ) , .p0 ( optlc_net_114 ) ) ; -sb_0__2__mux_tree_tapbuf_size2 mux_right_track_38 ( - .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[19] } ) , - .sram ( mux_tree_tapbuf_size2_13_sram ) , - .sram_inv ( mux_right_track_38_undriven_sram_inv ) , - .out ( chanx_right_out[19] ) , .p0 ( optlc_net_114 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_0 mux_bottom_track_1 ( - .in ( { chanx_right_in[18] , bottom_left_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size2_14_sram ) , - .sram_inv ( mux_bottom_track_1_undriven_sram_inv ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_114 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_2 mux_bottom_track_5 ( - .in ( { chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size2_15_sram ) , - .sram_inv ( mux_bottom_track_5_undriven_sram_inv ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_114 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_3 mux_bottom_track_9 ( - .in ( { chanx_right_in[14] , bottom_left_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size2_16_sram ) , - .sram_inv ( mux_bottom_track_9_undriven_sram_inv ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_114 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_1 mux_bottom_track_25 ( - .in ( { chanx_right_in[6] , bottom_left_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size2_17_sram ) , - .sram_inv ( mux_bottom_track_25_undriven_sram_inv ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_116 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_4 mem_right_track_10 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_5 mem_right_track_12 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_6 mem_right_track_14 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_7 mem_right_track_16 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_8 mem_right_track_18 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_9 mem_right_track_20 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_10 mem_right_track_22 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_11 mem_right_track_26 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_12 mem_right_track_28 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_13 mem_right_track_30 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_14 mem_right_track_32 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_15 mem_right_track_34 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_11_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_16 mem_right_track_36 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_12_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem mem_right_track_38 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_13_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_0 mem_bottom_track_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_14_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_2 mem_bottom_track_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_15_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_3 mem_bottom_track_9 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_16_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_1 mem_bottom_track_25 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_17_sram ) ) ; -sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_114 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_115 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_116 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_113 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_117 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_716 ( .A ( chanx_right_in[3] ) , - .X ( ropt_net_138 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_717 ( .A ( ropt_net_120 ) , - .X ( ropt_net_145 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_718 ( .A ( chanx_right_in[12] ) , - .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_122 ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_123 ) , - .X ( ropt_net_144 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( ropt_net_136 ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_137 ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_721 ( .A ( chanx_right_in[2] ) , - .X ( chany_bottom_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_138 ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_125 ) , - .X ( ropt_net_142 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_723 ( .A ( chanx_right_in[17] ) , - .X ( chany_bottom_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_724 ( .A ( ropt_net_127 ) , - .X ( ropt_net_140 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_17__16 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_120 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( chanx_right_in[19] ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( chanx_right_in[11] ) , - .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_741 ( .A ( ropt_net_139 ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_140 ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_744 ( .A ( ropt_net_141 ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_52 ( .A ( chanx_right_in[5] ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_746 ( .A ( ropt_net_142 ) , - .X ( chanx_right_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_747 ( .A ( ropt_net_143 ) , - .X ( chany_bottom_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_748 ( .A ( ropt_net_144 ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( .A ( ropt_net_145 ) , - .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_59 ( .A ( chanx_right_in[13] ) , - .X ( BUF_net_59 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_60 ( .A ( chanx_right_in[15] ) , - .X ( BUF_net_60 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( ropt_net_130 ) , - .X ( ropt_net_136 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( .A ( ropt_net_131 ) , - .X ( ropt_net_137 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( chanx_right_in[7] ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_133 ) , - .X ( ropt_net_141 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_86 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_143 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_88 ( .A ( BUF_net_59 ) , - .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_92 ( .A ( chanx_right_in[0] ) , - .X ( ropt_net_133 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_93 ( .A ( chanx_right_in[1] ) , - .X ( ropt_net_131 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_96 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_127 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_99 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_123 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_100 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_130 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_102 ( .A ( BUF_net_60 ) , - .X ( ropt_net_139 ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__59 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__58 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__57 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__56 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__55 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__54 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_127 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_27__53 ( .A ( mem_out[1] ) , - .X ( net_net_86 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_85 ( .A ( net_net_86 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__52 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__51 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__50 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__49 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__48 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__47 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__46 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size4_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__45 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__44 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__43 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__42 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size4_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__41 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__40 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size4_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__39 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_126 ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_65 ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size4_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_124 ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size5_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__38 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__37 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size5_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__36 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size5_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__35 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__34 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size5_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_63 ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( BUF_net_63 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_123 ( .A ( BUF_net_63 ) , - .X ( out[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__33 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__32 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__31 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__30 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__29 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__28 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__27 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_62 ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( BUF_net_62 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_122 ( .A ( BUF_net_62 ) , - .X ( out[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module sb_0__1_ ( prog_clk , chany_top_in , top_left_grid_pin_1_ , - chanx_right_in , right_bottom_grid_pin_34_ , right_bottom_grid_pin_35_ , - right_bottom_grid_pin_36_ , right_bottom_grid_pin_37_ , - right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ , - right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ , chany_bottom_in , - bottom_left_grid_pin_1_ , ccff_head , chany_top_out , chanx_right_out , - chany_bottom_out , ccff_tail , prog_clk__FEEDTHRU_1 ) ; -input [0:0] prog_clk ; -input [0:19] chany_top_in ; -input [0:0] top_left_grid_pin_1_ ; -input [0:19] chanx_right_in ; -input [0:0] right_bottom_grid_pin_34_ ; -input [0:0] right_bottom_grid_pin_35_ ; -input [0:0] right_bottom_grid_pin_36_ ; -input [0:0] right_bottom_grid_pin_37_ ; -input [0:0] right_bottom_grid_pin_38_ ; -input [0:0] right_bottom_grid_pin_39_ ; -input [0:0] right_bottom_grid_pin_40_ ; -input [0:0] right_bottom_grid_pin_41_ ; -input [0:19] chany_bottom_in ; -input [0:0] bottom_left_grid_pin_1_ ; -input [0:0] ccff_head ; -output [0:19] chany_top_out ; -output [0:19] chanx_right_out ; -output [0:19] chany_bottom_out ; -output [0:0] ccff_tail ; -output [0:0] prog_clk__FEEDTHRU_1 ; - -wire [0:2] mux_bottom_track_17_undriven_sram_inv ; -wire [0:2] mux_bottom_track_1_undriven_sram_inv ; -wire [0:2] mux_bottom_track_25_undriven_sram_inv ; -wire [0:1] mux_bottom_track_33_undriven_sram_inv ; -wire [0:2] mux_bottom_track_3_undriven_sram_inv ; -wire [0:2] mux_bottom_track_5_undriven_sram_inv ; -wire [0:2] mux_bottom_track_9_undriven_sram_inv ; -wire [0:2] mux_right_track_0_undriven_sram_inv ; -wire [0:2] mux_right_track_10_undriven_sram_inv ; -wire [0:2] mux_right_track_12_undriven_sram_inv ; -wire [0:2] mux_right_track_14_undriven_sram_inv ; -wire [0:1] mux_right_track_16_undriven_sram_inv ; -wire [0:1] mux_right_track_18_undriven_sram_inv ; -wire [0:1] mux_right_track_20_undriven_sram_inv ; -wire [0:1] mux_right_track_22_undriven_sram_inv ; -wire [0:2] mux_right_track_24_undriven_sram_inv ; -wire [0:1] mux_right_track_26_undriven_sram_inv ; -wire [0:1] mux_right_track_28_undriven_sram_inv ; -wire [0:2] mux_right_track_2_undriven_sram_inv ; -wire [0:1] mux_right_track_30_undriven_sram_inv ; -wire [0:1] mux_right_track_32_undriven_sram_inv ; -wire [0:1] mux_right_track_34_undriven_sram_inv ; -wire [0:1] mux_right_track_36_undriven_sram_inv ; -wire [0:2] mux_right_track_4_undriven_sram_inv ; -wire [0:2] mux_right_track_6_undriven_sram_inv ; -wire [0:2] mux_right_track_8_undriven_sram_inv ; -wire [0:2] mux_top_track_0_undriven_sram_inv ; -wire [0:2] mux_top_track_16_undriven_sram_inv ; -wire [0:2] mux_top_track_24_undriven_sram_inv ; -wire [0:2] mux_top_track_2_undriven_sram_inv ; -wire [0:2] mux_top_track_32_undriven_sram_inv ; -wire [0:2] mux_top_track_4_undriven_sram_inv ; -wire [0:2] mux_top_track_8_undriven_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_5_sram ; -wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; -wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:1] mux_tree_tapbuf_size3_2_sram ; -wire [0:1] mux_tree_tapbuf_size3_3_sram ; -wire [0:1] mux_tree_tapbuf_size3_4_sram ; -wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size4_0_sram ; -wire [0:2] mux_tree_tapbuf_size4_1_sram ; -wire [0:2] mux_tree_tapbuf_size4_2_sram ; -wire [0:2] mux_tree_tapbuf_size4_3_sram ; -wire [0:2] mux_tree_tapbuf_size4_4_sram ; -wire [0:2] mux_tree_tapbuf_size4_5_sram ; -wire [0:2] mux_tree_tapbuf_size4_6_sram ; -wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_6_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size5_0_sram ; -wire [0:2] mux_tree_tapbuf_size5_1_sram ; -wire [0:2] mux_tree_tapbuf_size5_2_sram ; -wire [0:2] mux_tree_tapbuf_size5_3_sram ; -wire [0:2] mux_tree_tapbuf_size5_4_sram ; -wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size6_1_sram ; -wire [0:2] mux_tree_tapbuf_size6_2_sram ; -wire [0:2] mux_tree_tapbuf_size6_3_sram ; -wire [0:2] mux_tree_tapbuf_size6_4_sram ; -wire [0:2] mux_tree_tapbuf_size6_5_sram ; -wire [0:2] mux_tree_tapbuf_size6_6_sram ; -wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_6_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size7_0_sram ; -wire [0:2] mux_tree_tapbuf_size7_1_sram ; -wire [0:2] mux_tree_tapbuf_size7_2_sram ; -wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; - -sb_0__1__mux_tree_tapbuf_size6_4 mux_top_track_0 ( - .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] , chanx_right_in[8] , - chanx_right_in[15] , chany_bottom_in[2] , chany_bottom_in[12] } ) , - .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_top_track_0_undriven_sram_inv ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_156 ) ) ; -sb_0__1__mux_tree_tapbuf_size6_5 mux_top_track_4 ( - .in ( { top_left_grid_pin_1_[0] , chanx_right_in[3] , chanx_right_in[10] , - chanx_right_in[17] , chany_bottom_in[5] , chany_bottom_in[14] } ) , - .sram ( mux_tree_tapbuf_size6_1_sram ) , - .sram_inv ( mux_top_track_4_undriven_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_156 ) ) ; -sb_0__1__mux_tree_tapbuf_size6 mux_top_track_8 ( - .in ( { top_left_grid_pin_1_[0] , chanx_right_in[4] , chanx_right_in[11] , - chanx_right_in[18] , chany_bottom_in[6] , chany_bottom_in[16] } ) , - .sram ( mux_tree_tapbuf_size6_2_sram ) , - .sram_inv ( mux_top_track_8_undriven_sram_inv ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_157 ) ) ; -sb_0__1__mux_tree_tapbuf_size6_3 mux_right_track_0 ( - .in ( { chany_top_in[2] , right_bottom_grid_pin_34_[0] , - right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , - right_bottom_grid_pin_40_[0] , chany_bottom_in[2] } ) , - .sram ( mux_tree_tapbuf_size6_3_sram ) , - .sram_inv ( mux_right_track_0_undriven_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_152 ) ) ; -sb_0__1__mux_tree_tapbuf_size6_0 mux_bottom_track_1 ( - .in ( { chany_top_in[2] , chany_top_in[12] , chanx_right_in[5] , - chanx_right_in[12] , chanx_right_in[19] , bottom_left_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size6_4_sram ) , - .sram_inv ( mux_bottom_track_1_undriven_sram_inv ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_155 ) ) ; -sb_0__1__mux_tree_tapbuf_size6_1 mux_bottom_track_5 ( - .in ( { chany_top_in[5] , chany_top_in[14] , chanx_right_in[3] , - chanx_right_in[10] , chanx_right_in[17] , bottom_left_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size6_5_sram ) , - .sram_inv ( mux_bottom_track_5_undriven_sram_inv ) , - .out ( { ropt_net_167 } ) , - .p0 ( optlc_net_151 ) ) ; -sb_0__1__mux_tree_tapbuf_size6_2 mux_bottom_track_9 ( - .in ( { chany_top_in[6] , chany_top_in[16] , chanx_right_in[2] , - chanx_right_in[9] , chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size6_6_sram ) , - .sram_inv ( mux_bottom_track_9_undriven_sram_inv ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_151 ) ) ; -sb_0__1__mux_tree_tapbuf_size6_mem_4 mem_top_track_0 ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size6_mem_5 mem_top_track_4 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size6_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_2_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size6_mem_3 mem_right_track_0 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_3_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_4_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size6_mem_1 mem_bottom_track_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_5_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size6_mem_2 mem_bottom_track_9 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_6_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size5 mux_top_track_2 ( - .in ( { chanx_right_in[2] , chanx_right_in[9] , chanx_right_in[16] , - chany_bottom_in[4] , chany_bottom_in[13] } ) , - .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_top_track_2_undriven_sram_inv ) , - .out ( { ropt_net_168 } ) , - .p0 ( optlc_net_156 ) ) ; -sb_0__1__mux_tree_tapbuf_size5_3 mux_top_track_16 ( - .in ( { chanx_right_in[5] , chanx_right_in[12] , chanx_right_in[19] , - chany_bottom_in[8] , chany_bottom_in[17] } ) , - .sram ( mux_tree_tapbuf_size5_1_sram ) , - .sram_inv ( mux_top_track_16_undriven_sram_inv ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_157 ) ) ; -sb_0__1__mux_tree_tapbuf_size5_2 mux_bottom_track_3 ( - .in ( { chany_top_in[4] , chany_top_in[13] , chanx_right_in[4] , - chanx_right_in[11] , chanx_right_in[18] } ) , - .sram ( mux_tree_tapbuf_size5_2_sram ) , - .sram_inv ( mux_bottom_track_3_undriven_sram_inv ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_155 ) ) ; -sb_0__1__mux_tree_tapbuf_size5_0 mux_bottom_track_17 ( - .in ( { chany_top_in[8] , chany_top_in[17] , chanx_right_in[1] , - chanx_right_in[8] , chanx_right_in[15] } ) , - .sram ( mux_tree_tapbuf_size5_3_sram ) , - .sram_inv ( mux_bottom_track_17_undriven_sram_inv ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_151 ) ) ; -sb_0__1__mux_tree_tapbuf_size5_1 mux_bottom_track_25 ( - .in ( { chany_top_in[9] , chany_top_in[18] , chanx_right_in[0] , - chanx_right_in[7] , chanx_right_in[14] } ) , - .sram ( mux_tree_tapbuf_size5_4_sram ) , - .sram_inv ( mux_bottom_track_25_undriven_sram_inv ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_154 ) ) ; -sb_0__1__mux_tree_tapbuf_size5_mem mem_top_track_2 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size5_mem_3 mem_top_track_16 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size5_mem_2 mem_bottom_track_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_2_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size5_mem_0 mem_bottom_track_17 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_3_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size5_mem_1 mem_bottom_track_25 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_4_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size4_5 mux_top_track_24 ( - .in ( { chanx_right_in[6] , chanx_right_in[13] , chany_bottom_in[9] , - chany_bottom_in[18] } ) , - .sram ( mux_tree_tapbuf_size4_0_sram ) , - .sram_inv ( mux_top_track_24_undriven_sram_inv ) , - .out ( { ropt_net_160 } ) , - .p0 ( optlc_net_153 ) ) ; -sb_0__1__mux_tree_tapbuf_size4 mux_top_track_32 ( - .in ( { chanx_right_in[0] , chanx_right_in[7] , chanx_right_in[14] , - chany_bottom_in[10] } ) , - .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_top_track_32_undriven_sram_inv ) , - .out ( chany_top_out[16] ) , .p0 ( optlc_net_153 ) ) ; -sb_0__1__mux_tree_tapbuf_size4_4 mux_right_track_8 ( - .in ( { chany_top_in[7] , chany_top_in[8] , right_bottom_grid_pin_34_[0] , - chany_bottom_in[8] } ) , - .sram ( mux_tree_tapbuf_size4_2_sram ) , - .sram_inv ( mux_right_track_8_undriven_sram_inv ) , - .out ( { ropt_net_163 } ) , - .p0 ( optlc_net_153 ) ) ; -sb_0__1__mux_tree_tapbuf_size4_0 mux_right_track_10 ( - .in ( { chany_top_in[9] , chany_top_in[11] , - right_bottom_grid_pin_35_[0] , chany_bottom_in[9] } ) , - .sram ( mux_tree_tapbuf_size4_3_sram ) , - .sram_inv ( mux_right_track_10_undriven_sram_inv ) , - .out ( chanx_right_out[5] ) , .p0 ( optlc_net_155 ) ) ; -sb_0__1__mux_tree_tapbuf_size4_1 mux_right_track_12 ( - .in ( { chany_top_in[10] , chany_top_in[15] , - right_bottom_grid_pin_36_[0] , chany_bottom_in[10] } ) , - .sram ( mux_tree_tapbuf_size4_4_sram ) , - .sram_inv ( mux_right_track_12_undriven_sram_inv ) , - .out ( chanx_right_out[6] ) , .p0 ( optlc_net_153 ) ) ; -sb_0__1__mux_tree_tapbuf_size4_2 mux_right_track_14 ( - .in ( { chany_top_in[12] , chany_top_in[19] , - right_bottom_grid_pin_37_[0] , chany_bottom_in[12] } ) , - .sram ( mux_tree_tapbuf_size4_5_sram ) , - .sram_inv ( mux_right_track_14_undriven_sram_inv ) , - .out ( { ropt_net_166 } ) , - .p0 ( optlc_net_155 ) ) ; -sb_0__1__mux_tree_tapbuf_size4_3 mux_right_track_24 ( - .in ( { chany_top_in[18] , right_bottom_grid_pin_34_[0] , - chany_bottom_in[18] , chany_bottom_in[19] } ) , - .sram ( mux_tree_tapbuf_size4_6_sram ) , - .sram_inv ( mux_right_track_24_undriven_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_154 ) ) ; -sb_0__1__mux_tree_tapbuf_size4_mem_5 mem_top_track_24 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size4_mem mem_top_track_32 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size4_mem_4 mem_right_track_8 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size4_mem_0 mem_right_track_10 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size4_mem_1 mem_right_track_12 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_4_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size4_mem_2 mem_right_track_14 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_5_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size4_mem_3 mem_right_track_24 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_6_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size7_0 mux_right_track_2 ( - .in ( { chany_top_in[0] , chany_top_in[4] , right_bottom_grid_pin_35_[0] , - right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , - right_bottom_grid_pin_41_[0] , chany_bottom_in[4] } ) , - .sram ( mux_tree_tapbuf_size7_0_sram ) , - .sram_inv ( mux_right_track_2_undriven_sram_inv ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_151 ) ) ; -sb_0__1__mux_tree_tapbuf_size7_1 mux_right_track_4 ( - .in ( { chany_top_in[1] , chany_top_in[5] , right_bottom_grid_pin_34_[0] , - right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , - right_bottom_grid_pin_40_[0] , chany_bottom_in[5] } ) , - .sram ( mux_tree_tapbuf_size7_1_sram ) , - .sram_inv ( mux_right_track_4_undriven_sram_inv ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_152 ) ) ; -sb_0__1__mux_tree_tapbuf_size7 mux_right_track_6 ( - .in ( { chany_top_in[3] , chany_top_in[6] , right_bottom_grid_pin_35_[0] , - right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , - right_bottom_grid_pin_41_[0] , chany_bottom_in[6] } ) , - .sram ( mux_tree_tapbuf_size7_2_sram ) , - .sram_inv ( mux_right_track_6_undriven_sram_inv ) , - .out ( chanx_right_out[3] ) , .p0 ( optlc_net_153 ) ) ; -sb_0__1__mux_tree_tapbuf_size7_mem_0 mem_right_track_2 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size7_mem_1 mem_right_track_4 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size7_mem mem_right_track_6 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size3_1 mux_right_track_16 ( - .in ( { chany_top_in[13] , right_bottom_grid_pin_38_[0] , - chany_bottom_in[13] } ) , - .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_right_track_16_undriven_sram_inv ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_151 ) ) ; -sb_0__1__mux_tree_tapbuf_size3_2 mux_right_track_18 ( - .in ( { chany_top_in[14] , right_bottom_grid_pin_39_[0] , - chany_bottom_in[14] } ) , - .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_right_track_18_undriven_sram_inv ) , - .out ( chanx_right_out[9] ) , .p0 ( optlc_net_152 ) ) ; -sb_0__1__mux_tree_tapbuf_size3_3 mux_right_track_20 ( - .in ( { chany_top_in[16] , right_bottom_grid_pin_40_[0] , - chany_bottom_in[16] } ) , - .sram ( mux_tree_tapbuf_size3_2_sram ) , - .sram_inv ( mux_right_track_20_undriven_sram_inv ) , - .out ( chanx_right_out[10] ) , .p0 ( optlc_net_152 ) ) ; -sb_0__1__mux_tree_tapbuf_size3 mux_right_track_22 ( - .in ( { chany_top_in[17] , right_bottom_grid_pin_41_[0] , - chany_bottom_in[17] } ) , - .sram ( mux_tree_tapbuf_size3_3_sram ) , - .sram_inv ( mux_right_track_22_undriven_sram_inv ) , - .out ( chanx_right_out[11] ) , .p0 ( optlc_net_154 ) ) ; -sb_0__1__mux_tree_tapbuf_size3_0 mux_bottom_track_33 ( - .in ( { chany_top_in[10] , chanx_right_in[6] , chanx_right_in[13] } ) , - .sram ( mux_tree_tapbuf_size3_4_sram ) , - .sram_inv ( mux_bottom_track_33_undriven_sram_inv ) , - .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_152 ) ) ; -sb_0__1__mux_tree_tapbuf_size3_mem_1 mem_right_track_16 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size3_mem_2 mem_right_track_18 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size3_mem_3 mem_right_track_20 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size3_mem mem_right_track_22 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_33 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , - .ccff_tail ( { ropt_net_179 } ) , - .mem_out ( mux_tree_tapbuf_size3_4_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size2_0 mux_right_track_26 ( - .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[15] } ) , - .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_right_track_26_undriven_sram_inv ) , - .out ( { ropt_net_173 } ) , - .p0 ( optlc_net_152 ) ) ; -sb_0__1__mux_tree_tapbuf_size2_1 mux_right_track_28 ( - .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[11] } ) , - .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_right_track_28_undriven_sram_inv ) , - .out ( chanx_right_out[14] ) , .p0 ( optlc_net_152 ) ) ; -sb_0__1__mux_tree_tapbuf_size2_2 mux_right_track_30 ( - .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[7] } ) , - .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_right_track_30_undriven_sram_inv ) , - .out ( chanx_right_out[15] ) , .p0 ( optlc_net_152 ) ) ; -sb_0__1__mux_tree_tapbuf_size2_3 mux_right_track_32 ( - .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[3] } ) , - .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_right_track_32_undriven_sram_inv ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_152 ) ) ; -sb_0__1__mux_tree_tapbuf_size2_4 mux_right_track_34 ( - .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[1] } ) , - .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_right_track_34_undriven_sram_inv ) , - .out ( chanx_right_out[17] ) , .p0 ( optlc_net_151 ) ) ; -sb_0__1__mux_tree_tapbuf_size2 mux_right_track_36 ( - .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[0] } ) , - .sram ( mux_tree_tapbuf_size2_5_sram ) , - .sram_inv ( mux_right_track_36_undriven_sram_inv ) , - .out ( chanx_right_out[18] ) , .p0 ( optlc_net_151 ) ) ; -sb_0__1__mux_tree_tapbuf_size2_mem_0 mem_right_track_26 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size2_mem_1 mem_right_track_28 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size2_mem_2 mem_right_track_30 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size2_mem_3 mem_right_track_32 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size2_mem_4 mem_right_track_34 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size2_mem mem_right_track_36 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_top_in[2] ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( ropt_net_182 ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_137 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_151 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_top_in[6] ) , - .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_141 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_152 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_144 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_153 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_top_in[10] ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_146 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_154 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , - .HI ( optlc_net_155 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chany_top_in[14] ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chany_top_in[16] ) , - .X ( ropt_net_180 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_151 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , - .HI ( optlc_net_156 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_153 ( .LO ( SYNOPSYS_UNCONNECTED_7 ) , - .HI ( optlc_net_157 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_814 ( .A ( ropt_net_183 ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__clkbuf_1 \prog_clk[0]_bip420 ( .A ( prog_clk[0] ) , - .X ( ctsbuf_net_1159 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_792 ( .A ( ropt_net_160 ) , - .X ( ropt_net_184 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chany_bottom_in[5] ) , - .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chany_bottom_in[6] ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chany_bottom_in[8] ) , - .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_184 ) , - .X ( chany_top_out[12] ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_345765 ( .A ( ctsbuf_net_1159 ) , - .X ( prog_clk__FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_816 ( .A ( ropt_net_185 ) , - .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( chany_top_in[18] ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chany_bottom_in[14] ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_25__24 ( .A ( chany_bottom_in[16] ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_817 ( .A ( ropt_net_186 ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_162 ) , - .X ( ropt_net_185 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_73 ( .A ( chany_top_in[4] ) , - .X ( BUF_net_73 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_818 ( .A ( ropt_net_187 ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_163 ) , - .X ( ropt_net_188 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_820 ( .A ( ropt_net_188 ) , - .X ( chanx_right_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_826 ( .A ( ropt_net_189 ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_827 ( .A ( ropt_net_190 ) , - .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_164 ) , - .X ( ropt_net_182 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( - .A ( right_bottom_grid_pin_41_[0] ) , .X ( ropt_net_191 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_166 ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_82 ( .A ( chany_bottom_in[10] ) , - .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_829 ( .A ( ropt_net_191 ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_192 ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_167 ) , - .X ( chany_bottom_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_168 ) , - .X ( chany_top_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_169 ) , - .X ( ropt_net_183 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_170 ) , - .X ( ropt_net_187 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_803 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_192 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_193 ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_804 ( .A ( chany_top_in[17] ) , - .X ( ropt_net_193 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( .A ( ropt_net_173 ) , - .X ( ropt_net_190 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_113 ( .A ( chany_top_in[8] ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_117 ( .A ( BUF_net_73 ) , - .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_118 ( .A ( chany_bottom_in[2] ) , - .X ( ropt_net_189 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_128 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_162 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( chany_top_in[9] ) , - .X ( ropt_net_186 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_131 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_164 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_133 ( .A ( chany_bottom_in[13] ) , - .X ( ropt_net_170 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_134 ( .A ( chany_bottom_in[18] ) , - .X ( ropt_net_169 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_807 ( .A ( chany_top_in[12] ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_808 ( - .A ( chany_bottom_in[17] ) , .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_809 ( .A ( chany_bottom_in[4] ) , - .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_810 ( - .A ( chany_bottom_in[12] ) , .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_179 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_180 ) , - .X ( chany_bottom_out[17] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__39 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__38 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__37 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__36 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__35 ( .A ( mem_out[1] ) , - .X ( net_aps_35 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_62 ( .A ( net_aps_35 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__34 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__33 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__32 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__31 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__30 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__29 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__28 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__27 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__26 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__25 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__24 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__23 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__22 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__21 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__20 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_41 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_40 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__0_ ( prog_clk , chany_top_in , top_left_grid_pin_1_ , - chanx_right_in , right_bottom_grid_pin_1_ , right_bottom_grid_pin_3_ , - right_bottom_grid_pin_5_ , right_bottom_grid_pin_7_ , - right_bottom_grid_pin_9_ , right_bottom_grid_pin_11_ , ccff_head , - chany_top_out , chanx_right_out , ccff_tail ) ; -input [0:0] prog_clk ; -input [0:19] chany_top_in ; -input [0:0] top_left_grid_pin_1_ ; -input [0:19] chanx_right_in ; -input [0:0] right_bottom_grid_pin_1_ ; -input [0:0] right_bottom_grid_pin_3_ ; -input [0:0] right_bottom_grid_pin_5_ ; -input [0:0] right_bottom_grid_pin_7_ ; -input [0:0] right_bottom_grid_pin_9_ ; -input [0:0] right_bottom_grid_pin_11_ ; -input [0:0] ccff_head ; -output [0:19] chany_top_out ; -output [0:19] chanx_right_out ; -output [0:0] ccff_tail ; - -wire [0:2] mux_right_track_0_undriven_sram_inv ; -wire [0:1] mux_right_track_10_undriven_sram_inv ; -wire [0:1] mux_right_track_12_undriven_sram_inv ; -wire [0:1] mux_right_track_14_undriven_sram_inv ; -wire [0:1] mux_right_track_16_undriven_sram_inv ; -wire [0:1] mux_right_track_18_undriven_sram_inv ; -wire [0:1] mux_right_track_24_undriven_sram_inv ; -wire [0:1] mux_right_track_26_undriven_sram_inv ; -wire [0:1] mux_right_track_28_undriven_sram_inv ; -wire [0:2] mux_right_track_2_undriven_sram_inv ; -wire [0:1] mux_right_track_30_undriven_sram_inv ; -wire [0:1] mux_right_track_32_undriven_sram_inv ; -wire [0:1] mux_right_track_34_undriven_sram_inv ; -wire [0:2] mux_right_track_4_undriven_sram_inv ; -wire [0:2] mux_right_track_6_undriven_sram_inv ; -wire [0:1] mux_right_track_8_undriven_sram_inv ; -wire [0:1] mux_top_track_0_undriven_sram_inv ; -wire [0:1] mux_top_track_24_undriven_sram_inv ; -wire [0:1] mux_top_track_4_undriven_sram_inv ; -wire [0:1] mux_top_track_8_undriven_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_10_sram ; -wire [0:1] mux_tree_tapbuf_size2_11_sram ; -wire [0:1] mux_tree_tapbuf_size2_12_sram ; -wire [0:1] mux_tree_tapbuf_size2_13_sram ; -wire [0:1] mux_tree_tapbuf_size2_14_sram ; -wire [0:1] mux_tree_tapbuf_size2_15_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_5_sram ; -wire [0:1] mux_tree_tapbuf_size2_6_sram ; -wire [0:1] mux_tree_tapbuf_size2_7_sram ; -wire [0:1] mux_tree_tapbuf_size2_8_sram ; -wire [0:1] mux_tree_tapbuf_size2_9_sram ; -wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size4_0_sram ; -wire [0:2] mux_tree_tapbuf_size4_1_sram ; -wire [0:2] mux_tree_tapbuf_size4_2_sram ; -wire [0:2] mux_tree_tapbuf_size4_3_sram ; -wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; - -sb_0__0__mux_tree_tapbuf_size2_12 mux_top_track_0 ( - .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] } ) , - .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_top_track_0_undriven_sram_inv ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_80 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_14 mux_top_track_4 ( - .in ( { top_left_grid_pin_1_[0] , chanx_right_in[3] } ) , - .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_top_track_4_undriven_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_80 ) ) ; -sb_0__0__mux_tree_tapbuf_size2 mux_top_track_8 ( - .in ( { top_left_grid_pin_1_[0] , chanx_right_in[5] } ) , - .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_top_track_8_undriven_sram_inv ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_80 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_13 mux_top_track_24 ( - .in ( { top_left_grid_pin_1_[0] , chanx_right_in[13] } ) , - .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_top_track_24_undriven_sram_inv ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_81 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_11 mux_right_track_8 ( - .in ( { chany_top_in[3] , right_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_right_track_8_undriven_sram_inv ) , - .out ( { ropt_net_83 } ) , - .p0 ( optlc_net_81 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_0 mux_right_track_10 ( - .in ( { chany_top_in[4] , right_bottom_grid_pin_3_[0] } ) , - .sram ( mux_tree_tapbuf_size2_5_sram ) , - .sram_inv ( mux_right_track_10_undriven_sram_inv ) , - .out ( chanx_right_out[5] ) , .p0 ( optlc_net_81 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_1 mux_right_track_12 ( - .in ( { chany_top_in[5] , right_bottom_grid_pin_5_[0] } ) , - .sram ( mux_tree_tapbuf_size2_6_sram ) , - .sram_inv ( mux_right_track_12_undriven_sram_inv ) , - .out ( { ropt_net_84 } ) , - .p0 ( optlc_net_78 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_2 mux_right_track_14 ( - .in ( { chany_top_in[6] , right_bottom_grid_pin_7_[0] } ) , - .sram ( mux_tree_tapbuf_size2_7_sram ) , - .sram_inv ( mux_right_track_14_undriven_sram_inv ) , - .out ( chanx_right_out[7] ) , .p0 ( optlc_net_78 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_3 mux_right_track_16 ( - .in ( { chany_top_in[7] , right_bottom_grid_pin_9_[0] } ) , - .sram ( mux_tree_tapbuf_size2_8_sram ) , - .sram_inv ( mux_right_track_16_undriven_sram_inv ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_78 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_4 mux_right_track_18 ( - .in ( { chany_top_in[8] , right_bottom_grid_pin_11_[0] } ) , - .sram ( mux_tree_tapbuf_size2_9_sram ) , - .sram_inv ( mux_right_track_18_undriven_sram_inv ) , - .out ( chanx_right_out[9] ) , .p0 ( optlc_net_81 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_5 mux_right_track_24 ( - .in ( { chany_top_in[11] , right_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size2_10_sram ) , - .sram_inv ( mux_right_track_24_undriven_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_79 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_6 mux_right_track_26 ( - .in ( { chany_top_in[12] , right_bottom_grid_pin_3_[0] } ) , - .sram ( mux_tree_tapbuf_size2_11_sram ) , - .sram_inv ( mux_right_track_26_undriven_sram_inv ) , - .out ( chanx_right_out[13] ) , .p0 ( optlc_net_79 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_7 mux_right_track_28 ( - .in ( { chany_top_in[13] , right_bottom_grid_pin_5_[0] } ) , - .sram ( mux_tree_tapbuf_size2_12_sram ) , - .sram_inv ( mux_right_track_28_undriven_sram_inv ) , - .out ( chanx_right_out[14] ) , .p0 ( optlc_net_79 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_8 mux_right_track_30 ( - .in ( { chany_top_in[14] , right_bottom_grid_pin_7_[0] } ) , - .sram ( mux_tree_tapbuf_size2_13_sram ) , - .sram_inv ( mux_right_track_30_undriven_sram_inv ) , - .out ( chanx_right_out[15] ) , .p0 ( optlc_net_78 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_9 mux_right_track_32 ( - .in ( { chany_top_in[15] , right_bottom_grid_pin_9_[0] } ) , - .sram ( mux_tree_tapbuf_size2_14_sram ) , - .sram_inv ( mux_right_track_32_undriven_sram_inv ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_78 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_10 mux_right_track_34 ( - .in ( { chany_top_in[16] , right_bottom_grid_pin_11_[0] } ) , - .sram ( mux_tree_tapbuf_size2_15_sram ) , - .sram_inv ( mux_right_track_34_undriven_sram_inv ) , - .out ( chanx_right_out[17] ) , .p0 ( optlc_net_78 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_12 mem_top_track_0 ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_14 mem_top_track_4 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_13 mem_top_track_24 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_11 mem_right_track_8 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_0 mem_right_track_10 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_1 mem_right_track_12 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_2 mem_right_track_14 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_3 mem_right_track_16 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_4 mem_right_track_18 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_5 mem_right_track_24 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_6 mem_right_track_26 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_11_sram ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_7 mem_right_track_28 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_12_sram ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_8 mem_right_track_30 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_13_sram ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_9 mem_right_track_32 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_14_sram ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_10 mem_right_track_34 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .ccff_tail ( { ropt_net_85 } ) , - .mem_out ( mux_tree_tapbuf_size2_15_sram ) ) ; -sb_0__0__mux_tree_tapbuf_size4_0 mux_right_track_0 ( - .in ( { chany_top_in[19] , right_bottom_grid_pin_1_[0] , - right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] } ) , - .sram ( mux_tree_tapbuf_size4_0_sram ) , - .sram_inv ( mux_right_track_0_undriven_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_78 ) ) ; -sb_0__0__mux_tree_tapbuf_size4_1 mux_right_track_2 ( - .in ( { chany_top_in[0] , right_bottom_grid_pin_3_[0] , - right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_11_[0] } ) , - .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_right_track_2_undriven_sram_inv ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_79 ) ) ; -sb_0__0__mux_tree_tapbuf_size4_2 mux_right_track_4 ( - .in ( { chany_top_in[1] , right_bottom_grid_pin_1_[0] , - right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] } ) , - .sram ( mux_tree_tapbuf_size4_2_sram ) , - .sram_inv ( mux_right_track_4_undriven_sram_inv ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_79 ) ) ; -sb_0__0__mux_tree_tapbuf_size4 mux_right_track_6 ( - .in ( { chany_top_in[2] , right_bottom_grid_pin_3_[0] , - right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_11_[0] } ) , - .sram ( mux_tree_tapbuf_size4_3_sram ) , - .sram_inv ( mux_right_track_6_undriven_sram_inv ) , - .out ( chanx_right_out[3] ) , .p0 ( optlc_net_79 ) ) ; -sb_0__0__mux_tree_tapbuf_size4_mem_0 mem_right_track_0 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ; -sb_0__0__mux_tree_tapbuf_size4_mem_1 mem_right_track_2 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ; -sb_0__0__mux_tree_tapbuf_size4_mem_2 mem_right_track_4 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ; -sb_0__0__mux_tree_tapbuf_size4_mem mem_right_track_6 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__0 ( .A ( chany_top_in[9] ) , - .X ( ropt_net_94 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_76 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_78 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_78 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_79 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_80 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_80 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chanx_right_in[0] ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_82 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_81 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_685 ( .A ( ropt_net_83 ) , - .X ( chanx_right_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_686 ( .A ( ropt_net_84 ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_687 ( .A ( ropt_net_85 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_688 ( .A ( chany_top_in[18] ) , - .X ( ropt_net_103 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_689 ( .A ( chanx_right_in[6] ) , - .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_690 ( .A ( chanx_right_in[15] ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_691 ( .A ( chanx_right_in[18] ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_692 ( .A ( ropt_net_90 ) , - .X ( ropt_net_99 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chanx_right_in[14] ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_693 ( .A ( ropt_net_91 ) , - .X ( ropt_net_98 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_694 ( .A ( ropt_net_92 ) , - .X ( ropt_net_100 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_695 ( .A ( ropt_net_93 ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_696 ( .A ( ropt_net_94 ) , - .X ( ropt_net_101 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_697 ( .A ( ropt_net_98 ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_46 ( .A ( chany_top_in[17] ) , - .X ( ropt_net_91 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_698 ( .A ( ropt_net_99 ) , - .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_48 ( .A ( chanx_right_in[2] ) , - .X ( chany_top_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_49 ( .A ( chanx_right_in[4] ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_699 ( .A ( ropt_net_100 ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_51 ( .A ( chanx_right_in[7] ) , - .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_52 ( .A ( chanx_right_in[8] ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_53 ( .A ( chanx_right_in[9] ) , - .X ( chany_top_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_54 ( .A ( chanx_right_in[10] ) , - .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_55 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_92 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_56 ( .A ( chanx_right_in[12] ) , - .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_700 ( .A ( ropt_net_101 ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_58 ( .A ( chanx_right_in[16] ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_59 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_90 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_701 ( .A ( ropt_net_102 ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_61 ( .A ( chanx_right_in[19] ) , - .X ( ropt_net_102 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_702 ( .A ( ropt_net_103 ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_67 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_93 ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_mem_23 ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_40__57 ( .A ( mem_out[1] ) , - .X ( net_net_110 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_110 ( .A ( net_net_110 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_mem_22 ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_39__56 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_mem_21 ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_38__55 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_23 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_22 ( in , sram , sram_inv , out , p_abuf0 , - p_abuf1 , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -output p_abuf0 ; -output p_abuf1 ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf1 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_92 ( .A ( p_abuf1 ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_93 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_21 ( in , sram , sram_inv , out , p_abuf0 , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -output p_abuf0 ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_91 ( .A ( out[0] ) , .X ( p_abuf0 ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff ( - Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk , p_abuf0 , p_abuf1 , - p_abuf2 ) ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:0] ff_D ; -input [0:0] ff_DI ; -output [0:0] ff_Q ; -input [0:0] ff_clk ; -output p_abuf0 ; -output p_abuf1 ; -output p_abuf2 ; - -sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , - .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( p_abuf2 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_58 ( .A ( p_abuf2 ) , .X ( ff_Q[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_60 ( .A ( p_abuf2 ) , .X ( p_abuf1 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_130 ( .A ( p_abuf2 ) , .X ( p_abuf0 ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_14 ( - Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:0] ff_D ; -input [0:0] ff_DI ; -output [0:0] ff_Q ; -input [0:0] ff_clk ; - -sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , - .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_37__54 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module grid_clb_mux_tree_size2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem ( prog_clk , - ccff_head , ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:16] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_5_ ( .D ( mem_out[4] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_6_ ( .D ( mem_out[5] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_7_ ( .D ( mem_out[6] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_8_ ( .D ( mem_out[7] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_9_ ( .D ( mem_out[8] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_10_ ( .D ( mem_out[9] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_11_ ( .D ( mem_out[10] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_12_ ( .D ( mem_out[11] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_13_ ( .D ( mem_out[12] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_14_ ( .D ( mem_out[13] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_15_ ( .D ( mem_out[14] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_16_ ( .D ( mem_out[15] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_36__53 ( .A ( mem_out[16] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module grid_clb_frac_lut4_mux ( in , sram , sram_inv , lut3_out , lut4_out ) ; -input [0:15] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:1] lut3_out ; -output [0:0] lut4_out ; - -wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_4_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_5_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( - .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( - .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( - .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( - .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_5_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_6_ ( - .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__buf_2_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__buf_2_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__buf_2_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ; -endmodule - - -module grid_clb_frac_lut4 ( in , sram , sram_inv , mode , mode_inv , - lut3_out , lut4_out ) ; -input [0:3] in ; -input [0:15] sram ; -input [0:15] sram_inv ; -input [0:0] mode ; -input [0:0] mode_inv ; -output [0:1] lut3_out ; -output [0:0] lut4_out ; - -wire [0:0] sky130_fd_sc_hd__buf_2_0_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_1_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_2_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; -wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ; -wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ; -wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ; -wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ; -wire [0:0] sky130_fd_sc_hd__or2_1_0_X ; - -sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , - .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , - .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , - .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , - .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( - .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , - .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , - .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , - .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , - .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( - .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; -grid_clb_frac_lut4_mux frac_lut4_mux_0_ ( .in ( sram ) , - .sram ( { sky130_fd_sc_hd__buf_2_0_X[0] , sky130_fd_sc_hd__buf_2_1_X[0] , - sky130_fd_sc_hd__buf_2_2_X[0] , sky130_fd_sc_hd__buf_2_3_X[0] } ) , - .sram_inv ( { sky130_fd_sc_hd__inv_1_0_Y[0] , - sky130_fd_sc_hd__inv_1_1_Y[0] , sky130_fd_sc_hd__inv_1_2_Y[0] , - sky130_fd_sc_hd__inv_1_3_Y[0] } ) , - .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4 ( - prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out , - frac_lut4_lut4_out , ccff_tail ) ; -input [0:0] prog_clk ; -input [0:3] frac_lut4_in ; -input [0:0] ccff_head ; -output [0:1] frac_lut4_lut3_out ; -output [0:0] frac_lut4_lut4_out ; -output [0:0] ccff_tail ; - -wire [0:15] frac_lut4_0__undriven_sram_inv ; -wire [0:0] frac_lut4_0_mode ; -wire [0:15] frac_lut4_0_sram ; - -grid_clb_frac_lut4 frac_lut4_0_ ( .in ( frac_lut4_in ) , - .sram ( frac_lut4_0_sram ) , - .sram_inv ( frac_lut4_0__undriven_sram_inv ) , - .mode ( frac_lut4_0_mode ) , - .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , - .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) ) ; -grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , - .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , - frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] , - frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , - frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , - frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , - frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic ( - prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p0 ) ; -input [0:0] prog_clk ; -input [0:3] frac_logic_in ; -input [0:0] ccff_head ; -output [0:1] frac_logic_out ; -output [0:0] ccff_tail ; -input p0 ; - -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; -wire [0:1] mux_frac_logic_out_0_undriven_sram_inv ; -wire [0:1] mux_tree_size2_0_sram ; - -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( - .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , - .ccff_head ( ccff_head ) , - .frac_lut4_lut3_out ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] , - frac_logic_out[1] } ) , - - .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , - .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ; -grid_clb_mux_tree_size2 mux_frac_logic_out_0 ( - .in ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] - } ) , - .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_frac_logic_out_0_undriven_sram_inv ) , - .out ( frac_logic_out[0] ) , .p0 ( p0 ) ) ; -grid_clb_mux_tree_size2_mem mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) ) ; -grid_clb_direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( frac_logic_out[1] ) ) ; -grid_clb_direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( frac_logic_in[0] ) ) ; -grid_clb_direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( frac_logic_in[1] ) ) ; -grid_clb_direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( frac_logic_in[2] ) ) ; -grid_clb_direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( frac_logic_in[3] ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric ( - prog_clk , Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , - fabric_clk , ccff_head , fabric_out , fabric_regout , fabric_sc_out , - ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p_abuf3 , p_abuf5 , p_abuf6 , - p0 ) ; -input [0:0] prog_clk ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:3] fabric_in ; -input [0:0] fabric_regin ; -input [0:0] fabric_sc_in ; -input [0:0] fabric_clk ; -input [0:0] ccff_head ; -output [0:1] fabric_out ; -output [0:0] fabric_regout ; -output [0:0] fabric_sc_out ; -output [0:0] ccff_tail ; -output p_abuf0 ; -output p_abuf1 ; -output p_abuf2 ; -output p_abuf3 ; -output p_abuf5 ; -output p_abuf6 ; -input p0 ; - -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; -wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; -wire [0:1] mux_fabric_out_0_undriven_sram_inv ; -wire [0:1] mux_fabric_out_1_undriven_sram_inv ; -wire [0:1] mux_ff_0_D_0_undriven_sram_inv ; -wire [0:1] mux_tree_size2_0_sram ; -wire [0:1] mux_tree_size2_1_sram ; -wire [0:0] mux_tree_size2_2_out ; -wire [0:1] mux_tree_size2_2_sram ; -wire [0:0] mux_tree_size2_mem_0_ccff_tail ; -wire [0:0] mux_tree_size2_mem_1_ccff_tail ; - -assign p_abuf1 = p_abuf2 ; - -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( - .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , - .ccff_head ( ccff_head ) , - .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , - .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .p0 ( p0 ) ) ; -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_14 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( - .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , - .ff_DI ( fabric_sc_in ) , - .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , - .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( - .Test_en ( Test_en ) , .clk ( clk ) , - .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , - .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , - .ff_Q ( fabric_sc_out ) , - .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) , - .p_abuf0 ( fabric_regout[0] ) , .p_abuf1 ( p_abuf0 ) , - .p_abuf2 ( p_abuf2 ) ) ; -grid_clb_mux_tree_size2_21 mux_fabric_out_0 ( - .in ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] - } ) , - .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_fabric_out_0_undriven_sram_inv ) , - .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf3 ) , .p0 ( p0 ) ) ; -grid_clb_mux_tree_size2_22 mux_fabric_out_1 ( - .in ( { fabric_sc_out[0] , - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] - } ) , - .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( mux_fabric_out_1_undriven_sram_inv ) , - .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf5 ) , .p_abuf1 ( p_abuf6 ) , - .p0 ( p0 ) ) ; -grid_clb_mux_tree_size2_23 mux_ff_0_D_0 ( - .in ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , - fabric_regin[0] } ) , - .sram ( mux_tree_size2_2_sram ) , - .sram_inv ( mux_ff_0_D_0_undriven_sram_inv ) , - .out ( mux_tree_size2_2_out ) , .p0 ( p0 ) ) ; -grid_clb_mux_tree_size2_mem_21 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_size2_0_sram ) ) ; -grid_clb_mux_tree_size2_mem_22 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_size2_1_sram ) ) ; -grid_clb_mux_tree_size2_mem_23 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , - .mem_out ( mux_tree_size2_2_sram ) ) ; -grid_clb_direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( { p_abuf2 } ) ) ; -grid_clb_direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( { p_abuf2 } ) ) ; -grid_clb_direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( fabric_in[0] ) ) ; -grid_clb_direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_6 } ) , - .out ( fabric_in[1] ) ) ; -grid_clb_direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_7 } ) , - .out ( fabric_in[2] ) ) ; -grid_clb_direct_interc direct_interc_5_ ( - .in ( { SYNOPSYS_UNCONNECTED_8 } ) , - .out ( fabric_in[3] ) ) ; -grid_clb_direct_interc direct_interc_6_ ( - .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( fabric_sc_in ) ) ; -grid_clb_direct_interc direct_interc_7_ ( - .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( fabric_clk ) ) ; -grid_clb_direct_interc direct_interc_8_ ( - .in ( { SYNOPSYS_UNCONNECTED_11 } ) , - - .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) ) ; -grid_clb_direct_interc direct_interc_9_ ( - .in ( { SYNOPSYS_UNCONNECTED_12 } ) , - - .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ) ; -grid_clb_direct_interc direct_interc_10_ ( - .in ( { SYNOPSYS_UNCONNECTED_13 } ) , - .out ( fabric_clk ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle ( prog_clk , Test_en , - clk , fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , - fle_regout , fle_sc_out , ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , - p_abuf3 , p_abuf5 , p_abuf6 , p0 ) ; -input [0:0] prog_clk ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:3] fle_in ; -input [0:0] fle_regin ; -input [0:0] fle_sc_in ; -input [0:0] fle_clk ; -input [0:0] ccff_head ; -output [0:1] fle_out ; -output [0:0] fle_regout ; -output [0:0] fle_sc_out ; -output [0:0] ccff_tail ; -output p_abuf0 ; -output p_abuf1 ; -output p_abuf2 ; -output p_abuf3 ; -output p_abuf5 ; -output p_abuf6 ; -input p0 ; - -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( - .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , - .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , - .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , - .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , - .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , - .p_abuf2 ( p_abuf2 ) , .p_abuf3 ( p_abuf3 ) , .p_abuf5 ( p_abuf5 ) , - .p_abuf6 ( p_abuf6 ) , .p0 ( p0 ) ) ; -grid_clb_direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( { p_abuf6 } ) ) ; -grid_clb_direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( { p_abuf1 } ) ) ; -grid_clb_direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( { p_abuf2 } ) ) ; -grid_clb_direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fle_in[0] ) ) ; -grid_clb_direct_interc direct_interc_5_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( fle_in[1] ) ) ; -grid_clb_direct_interc direct_interc_6_ ( - .in ( { SYNOPSYS_UNCONNECTED_6 } ) , - .out ( fle_in[2] ) ) ; -grid_clb_direct_interc direct_interc_7_ ( - .in ( { SYNOPSYS_UNCONNECTED_7 } ) , - .out ( fle_in[3] ) ) ; -grid_clb_direct_interc direct_interc_8_ ( - .in ( { SYNOPSYS_UNCONNECTED_8 } ) , - .out ( fle_regin ) ) ; -grid_clb_direct_interc direct_interc_9_ ( - .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( fle_sc_in ) ) ; -grid_clb_direct_interc direct_interc_10_ ( - .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( fle_clk ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_mem_20 ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_35__52 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_mem_19 ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_34__51 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_mem_18 ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__50 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_20 ( in , sram , sram_inv , out , p3 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p3 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_19 ( in , sram , sram_inv , out , p_abuf0 , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -output p_abuf0 ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_124 ( .A ( BUF_net_89 ) , - .X ( p_abuf0 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_89 ( .A ( out[0] ) , - .X ( BUF_net_89 ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_18 ( in , sram , sram_inv , out , p_abuf0 , - p_abuf1 , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -output p_abuf0 ; -output p_abuf1 ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf1 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_86 ( .A ( p_abuf1 ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_87 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_13 ( - Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:0] ff_D ; -input [0:0] ff_DI ; -output [0:0] ff_Q ; -input [0:0] ff_clk ; - -sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , - .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_12 ( - Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:0] ff_D ; -input [0:0] ff_DI ; -output [0:0] ff_Q ; -input [0:0] ff_clk ; - -sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , - .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_mem_30 ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_32__49 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_30 ( in , sram , sram_inv , out , p3 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p3 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_6 ( prog_clk , - ccff_head , ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:16] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_5_ ( .D ( mem_out[4] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_6_ ( .D ( mem_out[5] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_7_ ( .D ( mem_out[6] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_8_ ( .D ( mem_out[7] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_9_ ( .D ( mem_out[8] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_10_ ( .D ( mem_out[9] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_11_ ( .D ( mem_out[10] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_12_ ( .D ( mem_out[11] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_13_ ( .D ( mem_out[12] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_14_ ( .D ( mem_out[13] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_15_ ( .D ( mem_out[14] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_16_ ( .D ( mem_out[15] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__48 ( .A ( mem_out[16] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module grid_clb_frac_lut4_mux_6 ( in , sram , sram_inv , lut3_out , lut4_out ) ; -input [0:15] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:1] lut3_out ; -output [0:0] lut4_out ; - -wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_4_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_5_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( - .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( - .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( - .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( - .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_5_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_6_ ( - .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__buf_2_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__buf_2_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__buf_2_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ; -endmodule - - -module grid_clb_frac_lut4_6 ( in , sram , sram_inv , mode , mode_inv , - lut3_out , lut4_out ) ; -input [0:3] in ; -input [0:15] sram ; -input [0:15] sram_inv ; -input [0:0] mode ; -input [0:0] mode_inv ; -output [0:1] lut3_out ; -output [0:0] lut4_out ; - -wire [0:0] sky130_fd_sc_hd__buf_2_0_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_1_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_2_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; -wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ; -wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ; -wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ; -wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ; -wire [0:0] sky130_fd_sc_hd__or2_1_0_X ; - -sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , - .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , - .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , - .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , - .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( - .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , - .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , - .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , - .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , - .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( - .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; -grid_clb_frac_lut4_mux_6 frac_lut4_mux_0_ ( .in ( sram ) , - .sram ( { sky130_fd_sc_hd__buf_2_0_X[0] , sky130_fd_sc_hd__buf_2_1_X[0] , - sky130_fd_sc_hd__buf_2_2_X[0] , sky130_fd_sc_hd__buf_2_3_X[0] } ) , - .sram_inv ( { sky130_fd_sc_hd__inv_1_0_Y[0] , - sky130_fd_sc_hd__inv_1_1_Y[0] , sky130_fd_sc_hd__inv_1_2_Y[0] , - sky130_fd_sc_hd__inv_1_3_Y[0] } ) , - .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_6 ( - prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out , - frac_lut4_lut4_out , ccff_tail ) ; -input [0:0] prog_clk ; -input [0:3] frac_lut4_in ; -input [0:0] ccff_head ; -output [0:1] frac_lut4_lut3_out ; -output [0:0] frac_lut4_lut4_out ; -output [0:0] ccff_tail ; - -wire [0:15] frac_lut4_0__undriven_sram_inv ; -wire [0:0] frac_lut4_0_mode ; -wire [0:15] frac_lut4_0_sram ; - -grid_clb_frac_lut4_6 frac_lut4_0_ ( .in ( frac_lut4_in ) , - .sram ( frac_lut4_0_sram ) , - .sram_inv ( frac_lut4_0__undriven_sram_inv ) , - .mode ( frac_lut4_0_mode ) , - .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , - .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) ) ; -grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_6 frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , - .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , - frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] , - frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , - frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , - frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , - frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_6 ( - prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p3 ) ; -input [0:0] prog_clk ; -input [0:3] frac_logic_in ; -input [0:0] ccff_head ; -output [0:1] frac_logic_out ; -output [0:0] ccff_tail ; -input p3 ; - -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; -wire [0:1] mux_frac_logic_out_0_undriven_sram_inv ; -wire [0:1] mux_tree_size2_0_sram ; - -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( - .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , - .ccff_head ( ccff_head ) , - .frac_lut4_lut3_out ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] , - frac_logic_out[1] } ) , - - .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , - .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ; -grid_clb_mux_tree_size2_30 mux_frac_logic_out_0 ( - .in ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] - } ) , - .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_frac_logic_out_0_undriven_sram_inv ) , - .out ( frac_logic_out[0] ) , .p3 ( p3 ) ) ; -grid_clb_mux_tree_size2_mem_30 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) ) ; -grid_clb_direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( frac_logic_out[1] ) ) ; -grid_clb_direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( frac_logic_in[0] ) ) ; -grid_clb_direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( frac_logic_in[1] ) ) ; -grid_clb_direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( frac_logic_in[2] ) ) ; -grid_clb_direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( frac_logic_in[3] ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_6 ( - prog_clk , Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , - fabric_clk , ccff_head , fabric_out , fabric_regout , fabric_sc_out , - ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p0 , p3 ) ; -input [0:0] prog_clk ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:3] fabric_in ; -input [0:0] fabric_regin ; -input [0:0] fabric_sc_in ; -input [0:0] fabric_clk ; -input [0:0] ccff_head ; -output [0:1] fabric_out ; -output [0:0] fabric_regout ; -output [0:0] fabric_sc_out ; -output [0:0] ccff_tail ; -output p_abuf0 ; -output p_abuf1 ; -output p_abuf2 ; -input p0 ; -input p3 ; - -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; -wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; -wire [0:1] mux_fabric_out_0_undriven_sram_inv ; -wire [0:1] mux_fabric_out_1_undriven_sram_inv ; -wire [0:1] mux_ff_0_D_0_undriven_sram_inv ; -wire [0:1] mux_tree_size2_0_sram ; -wire [0:1] mux_tree_size2_1_sram ; -wire [0:0] mux_tree_size2_2_out ; -wire [0:1] mux_tree_size2_2_sram ; -wire [0:0] mux_tree_size2_mem_0_ccff_tail ; -wire [0:0] mux_tree_size2_mem_1_ccff_tail ; - -assign fabric_regout[0] = fabric_sc_out[0] ; - -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( - .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , - .ccff_head ( ccff_head ) , - .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , - .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .p3 ( p3 ) ) ; -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_12 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( - .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , - .ff_DI ( fabric_sc_in ) , - .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , - .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_13 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( - .Test_en ( Test_en ) , .clk ( clk ) , - .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , - .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , - .ff_Q ( fabric_sc_out ) , - .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; -grid_clb_mux_tree_size2_18 mux_fabric_out_0 ( - .in ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] - } ) , - .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_fabric_out_0_undriven_sram_inv ) , - .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , - .p0 ( p0 ) ) ; -grid_clb_mux_tree_size2_19 mux_fabric_out_1 ( - .in ( { fabric_sc_out[0] , - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] - } ) , - .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( mux_fabric_out_1_undriven_sram_inv ) , - .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf2 ) , .p0 ( p0 ) ) ; -grid_clb_mux_tree_size2_20 mux_ff_0_D_0 ( - .in ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , - fabric_regin[0] } ) , - .sram ( mux_tree_size2_2_sram ) , - .sram_inv ( mux_ff_0_D_0_undriven_sram_inv ) , - .out ( mux_tree_size2_2_out ) , .p3 ( p3 ) ) ; -grid_clb_mux_tree_size2_mem_18 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_size2_0_sram ) ) ; -grid_clb_mux_tree_size2_mem_19 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_size2_1_sram ) ) ; -grid_clb_mux_tree_size2_mem_20 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , - .mem_out ( mux_tree_size2_2_sram ) ) ; -grid_clb_direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fabric_sc_out ) ) ; -grid_clb_direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fabric_sc_out ) ) ; -grid_clb_direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( fabric_in[0] ) ) ; -grid_clb_direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_6 } ) , - .out ( fabric_in[1] ) ) ; -grid_clb_direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_7 } ) , - .out ( fabric_in[2] ) ) ; -grid_clb_direct_interc direct_interc_5_ ( - .in ( { SYNOPSYS_UNCONNECTED_8 } ) , - .out ( fabric_in[3] ) ) ; -grid_clb_direct_interc direct_interc_6_ ( - .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( fabric_sc_in ) ) ; -grid_clb_direct_interc direct_interc_7_ ( - .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( fabric_clk ) ) ; -grid_clb_direct_interc direct_interc_8_ ( - .in ( { SYNOPSYS_UNCONNECTED_11 } ) , - - .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) ) ; -grid_clb_direct_interc direct_interc_9_ ( - .in ( { SYNOPSYS_UNCONNECTED_12 } ) , - - .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ) ; -grid_clb_direct_interc direct_interc_10_ ( - .in ( { SYNOPSYS_UNCONNECTED_13 } ) , - .out ( fabric_clk ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_6 ( prog_clk , Test_en , - clk , fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , - fle_regout , fle_sc_out , ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p0 , - p3 ) ; -input [0:0] prog_clk ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:3] fle_in ; -input [0:0] fle_regin ; -input [0:0] fle_sc_in ; -input [0:0] fle_clk ; -input [0:0] ccff_head ; -output [0:1] fle_out ; -output [0:0] fle_regout ; -output [0:0] fle_sc_out ; -output [0:0] ccff_tail ; -output p_abuf0 ; -output p_abuf1 ; -output p_abuf2 ; -input p0 ; -input p3 ; - -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( - .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , - .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , - .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , - .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , - .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , - .p_abuf2 ( p_abuf2 ) , .p0 ( p0 ) , .p3 ( p3 ) ) ; -grid_clb_direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( { p_abuf1 } ) ) ; -grid_clb_direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( fle_regout ) ) ; -grid_clb_direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fle_sc_out ) ) ; -grid_clb_direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fle_in[0] ) ) ; -grid_clb_direct_interc direct_interc_5_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( fle_in[1] ) ) ; -grid_clb_direct_interc direct_interc_6_ ( - .in ( { SYNOPSYS_UNCONNECTED_6 } ) , - .out ( fle_in[2] ) ) ; -grid_clb_direct_interc direct_interc_7_ ( - .in ( { SYNOPSYS_UNCONNECTED_7 } ) , - .out ( fle_in[3] ) ) ; -grid_clb_direct_interc direct_interc_8_ ( - .in ( { SYNOPSYS_UNCONNECTED_8 } ) , - .out ( fle_regin ) ) ; -grid_clb_direct_interc direct_interc_9_ ( - .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( fle_sc_in ) ) ; -grid_clb_direct_interc direct_interc_10_ ( - .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( fle_clk ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_mem_17 ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__47 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_mem_16 ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__46 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_mem_15 ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_28__45 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_17 ( in , sram , sram_inv , out , p3 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p3 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_16 ( in , sram , sram_inv , out , p_abuf0 , - p3 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -output p_abuf0 ; -input p3 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_123 ( .A ( out[0] ) , .X ( p_abuf0 ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_15 ( in , sram , sram_inv , out , p_abuf0 , - p_abuf1 , p3 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -output p_abuf0 ; -output p_abuf1 ; -input p3 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf1 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_82 ( .A ( p_abuf1 ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_83 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_11 ( - Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:0] ff_D ; -input [0:0] ff_DI ; -output [0:0] ff_Q ; -input [0:0] ff_clk ; - -sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , - .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_10 ( - Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:0] ff_D ; -input [0:0] ff_DI ; -output [0:0] ff_Q ; -input [0:0] ff_clk ; - -sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , - .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_mem_29 ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_27__44 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_29 ( in , sram , sram_inv , out , p3 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p3 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_5 ( prog_clk , - ccff_head , ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:16] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_5_ ( .D ( mem_out[4] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_6_ ( .D ( mem_out[5] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_7_ ( .D ( mem_out[6] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_8_ ( .D ( mem_out[7] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_9_ ( .D ( mem_out[8] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_10_ ( .D ( mem_out[9] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_11_ ( .D ( mem_out[10] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_12_ ( .D ( mem_out[11] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_13_ ( .D ( mem_out[12] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_14_ ( .D ( mem_out[13] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_15_ ( .D ( mem_out[14] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_16_ ( .D ( mem_out[15] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_26__43 ( .A ( mem_out[16] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module grid_clb_frac_lut4_mux_5 ( in , sram , sram_inv , lut3_out , lut4_out ) ; -input [0:15] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:1] lut3_out ; -output [0:0] lut4_out ; - -wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_4_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_5_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( - .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( - .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( - .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( - .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_5_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_6_ ( - .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__buf_2_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__buf_2_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__buf_2_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ; -endmodule - - -module grid_clb_frac_lut4_5 ( in , sram , sram_inv , mode , mode_inv , - lut3_out , lut4_out ) ; -input [0:3] in ; -input [0:15] sram ; -input [0:15] sram_inv ; -input [0:0] mode ; -input [0:0] mode_inv ; -output [0:1] lut3_out ; -output [0:0] lut4_out ; - -wire [0:0] sky130_fd_sc_hd__buf_2_0_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_1_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_2_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; -wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ; -wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ; -wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ; -wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ; -wire [0:0] sky130_fd_sc_hd__or2_1_0_X ; - -sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , - .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , - .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , - .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , - .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( - .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , - .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , - .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , - .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , - .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( - .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; -grid_clb_frac_lut4_mux_5 frac_lut4_mux_0_ ( .in ( sram ) , - .sram ( { sky130_fd_sc_hd__buf_2_0_X[0] , sky130_fd_sc_hd__buf_2_1_X[0] , - sky130_fd_sc_hd__buf_2_2_X[0] , sky130_fd_sc_hd__buf_2_3_X[0] } ) , - .sram_inv ( { sky130_fd_sc_hd__inv_1_0_Y[0] , - sky130_fd_sc_hd__inv_1_1_Y[0] , sky130_fd_sc_hd__inv_1_2_Y[0] , - sky130_fd_sc_hd__inv_1_3_Y[0] } ) , - .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_5 ( - prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out , - frac_lut4_lut4_out , ccff_tail ) ; -input [0:0] prog_clk ; -input [0:3] frac_lut4_in ; -input [0:0] ccff_head ; -output [0:1] frac_lut4_lut3_out ; -output [0:0] frac_lut4_lut4_out ; -output [0:0] ccff_tail ; - -wire [0:15] frac_lut4_0__undriven_sram_inv ; -wire [0:0] frac_lut4_0_mode ; -wire [0:15] frac_lut4_0_sram ; - -grid_clb_frac_lut4_5 frac_lut4_0_ ( .in ( frac_lut4_in ) , - .sram ( frac_lut4_0_sram ) , - .sram_inv ( frac_lut4_0__undriven_sram_inv ) , - .mode ( frac_lut4_0_mode ) , - .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , - .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) ) ; -grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_5 frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , - .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , - frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] , - frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , - frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , - frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , - frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_5 ( - prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p3 ) ; -input [0:0] prog_clk ; -input [0:3] frac_logic_in ; -input [0:0] ccff_head ; -output [0:1] frac_logic_out ; -output [0:0] ccff_tail ; -input p3 ; - -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; -wire [0:1] mux_frac_logic_out_0_undriven_sram_inv ; -wire [0:1] mux_tree_size2_0_sram ; - -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( - .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , - .ccff_head ( ccff_head ) , - .frac_lut4_lut3_out ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] , - frac_logic_out[1] } ) , - - .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , - .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ; -grid_clb_mux_tree_size2_29 mux_frac_logic_out_0 ( - .in ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] - } ) , - .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_frac_logic_out_0_undriven_sram_inv ) , - .out ( frac_logic_out[0] ) , .p3 ( p3 ) ) ; -grid_clb_mux_tree_size2_mem_29 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) ) ; -grid_clb_direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( frac_logic_out[1] ) ) ; -grid_clb_direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( frac_logic_in[0] ) ) ; -grid_clb_direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( frac_logic_in[1] ) ) ; -grid_clb_direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( frac_logic_in[2] ) ) ; -grid_clb_direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( frac_logic_in[3] ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_5 ( - prog_clk , Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , - fabric_clk , ccff_head , fabric_out , fabric_regout , fabric_sc_out , - ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p3 ) ; -input [0:0] prog_clk ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:3] fabric_in ; -input [0:0] fabric_regin ; -input [0:0] fabric_sc_in ; -input [0:0] fabric_clk ; -input [0:0] ccff_head ; -output [0:1] fabric_out ; -output [0:0] fabric_regout ; -output [0:0] fabric_sc_out ; -output [0:0] ccff_tail ; -output p_abuf0 ; -output p_abuf1 ; -output p_abuf2 ; -input p3 ; - -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; -wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; -wire [0:1] mux_fabric_out_0_undriven_sram_inv ; -wire [0:1] mux_fabric_out_1_undriven_sram_inv ; -wire [0:1] mux_ff_0_D_0_undriven_sram_inv ; -wire [0:1] mux_tree_size2_0_sram ; -wire [0:1] mux_tree_size2_1_sram ; -wire [0:0] mux_tree_size2_2_out ; -wire [0:1] mux_tree_size2_2_sram ; -wire [0:0] mux_tree_size2_mem_0_ccff_tail ; -wire [0:0] mux_tree_size2_mem_1_ccff_tail ; - -assign fabric_regout[0] = fabric_sc_out[0] ; - -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( - .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , - .ccff_head ( ccff_head ) , - .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , - .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .p3 ( p3 ) ) ; -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_10 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( - .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , - .ff_DI ( fabric_sc_in ) , - .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , - .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_11 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( - .Test_en ( Test_en ) , .clk ( clk ) , - .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , - .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , - .ff_Q ( fabric_sc_out ) , - .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; -grid_clb_mux_tree_size2_15 mux_fabric_out_0 ( - .in ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] - } ) , - .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_fabric_out_0_undriven_sram_inv ) , - .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , - .p3 ( p3 ) ) ; -grid_clb_mux_tree_size2_16 mux_fabric_out_1 ( - .in ( { fabric_sc_out[0] , - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] - } ) , - .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( mux_fabric_out_1_undriven_sram_inv ) , - .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf2 ) , .p3 ( p3 ) ) ; -grid_clb_mux_tree_size2_17 mux_ff_0_D_0 ( - .in ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , - fabric_regin[0] } ) , - .sram ( mux_tree_size2_2_sram ) , - .sram_inv ( mux_ff_0_D_0_undriven_sram_inv ) , - .out ( mux_tree_size2_2_out ) , .p3 ( p3 ) ) ; -grid_clb_mux_tree_size2_mem_15 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_size2_0_sram ) ) ; -grid_clb_mux_tree_size2_mem_16 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_size2_1_sram ) ) ; -grid_clb_mux_tree_size2_mem_17 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , - .mem_out ( mux_tree_size2_2_sram ) ) ; -grid_clb_direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fabric_sc_out ) ) ; -grid_clb_direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fabric_sc_out ) ) ; -grid_clb_direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( fabric_in[0] ) ) ; -grid_clb_direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_6 } ) , - .out ( fabric_in[1] ) ) ; -grid_clb_direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_7 } ) , - .out ( fabric_in[2] ) ) ; -grid_clb_direct_interc direct_interc_5_ ( - .in ( { SYNOPSYS_UNCONNECTED_8 } ) , - .out ( fabric_in[3] ) ) ; -grid_clb_direct_interc direct_interc_6_ ( - .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( fabric_sc_in ) ) ; -grid_clb_direct_interc direct_interc_7_ ( - .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( fabric_clk ) ) ; -grid_clb_direct_interc direct_interc_8_ ( - .in ( { SYNOPSYS_UNCONNECTED_11 } ) , - - .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) ) ; -grid_clb_direct_interc direct_interc_9_ ( - .in ( { SYNOPSYS_UNCONNECTED_12 } ) , - - .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ) ; -grid_clb_direct_interc direct_interc_10_ ( - .in ( { SYNOPSYS_UNCONNECTED_13 } ) , - .out ( fabric_clk ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_5 ( prog_clk , Test_en , - clk , fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , - fle_regout , fle_sc_out , ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p3 ) ; -input [0:0] prog_clk ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:3] fle_in ; -input [0:0] fle_regin ; -input [0:0] fle_sc_in ; -input [0:0] fle_clk ; -input [0:0] ccff_head ; -output [0:1] fle_out ; -output [0:0] fle_regout ; -output [0:0] fle_sc_out ; -output [0:0] ccff_tail ; -output p_abuf0 ; -output p_abuf1 ; -output p_abuf2 ; -input p3 ; - -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( - .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , - .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , - .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , - .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , - .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , - .p_abuf2 ( p_abuf2 ) , .p3 ( p3 ) ) ; -grid_clb_direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( { p_abuf1 } ) ) ; -grid_clb_direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( fle_regout ) ) ; -grid_clb_direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fle_sc_out ) ) ; -grid_clb_direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fle_in[0] ) ) ; -grid_clb_direct_interc direct_interc_5_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( fle_in[1] ) ) ; -grid_clb_direct_interc direct_interc_6_ ( - .in ( { SYNOPSYS_UNCONNECTED_6 } ) , - .out ( fle_in[2] ) ) ; -grid_clb_direct_interc direct_interc_7_ ( - .in ( { SYNOPSYS_UNCONNECTED_7 } ) , - .out ( fle_in[3] ) ) ; -grid_clb_direct_interc direct_interc_8_ ( - .in ( { SYNOPSYS_UNCONNECTED_8 } ) , - .out ( fle_regin ) ) ; -grid_clb_direct_interc direct_interc_9_ ( - .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( fle_sc_in ) ) ; -grid_clb_direct_interc direct_interc_10_ ( - .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( fle_clk ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_mem_14 ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__42 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_mem_13 ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__41 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_mem_12 ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__40 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_14 ( in , sram , sram_inv , out , p2 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p2 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_13 ( in , sram , sram_inv , out , p_abuf0 , - p_abuf1 , p3 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -output p_abuf0 ; -output p_abuf1 ; -input p3 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf1 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_80 ( .A ( p_abuf1 ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_81 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_12 ( in , sram , sram_inv , out , p_abuf0 , - p3 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -output p_abuf0 ; -input p3 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_79 ( .A ( out[0] ) , .X ( p_abuf0 ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_9 ( - Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:0] ff_D ; -input [0:0] ff_DI ; -output [0:0] ff_Q ; -input [0:0] ff_clk ; - -sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , - .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_8 ( - Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:0] ff_D ; -input [0:0] ff_DI ; -output [0:0] ff_Q ; -input [0:0] ff_clk ; - -sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , - .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_mem_28 ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_22__39 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_28 ( in , sram , sram_inv , out , p2 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p2 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_4 ( prog_clk , - ccff_head , ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:16] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_5_ ( .D ( mem_out[4] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_6_ ( .D ( mem_out[5] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_7_ ( .D ( mem_out[6] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_8_ ( .D ( mem_out[7] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_9_ ( .D ( mem_out[8] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_10_ ( .D ( mem_out[9] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_11_ ( .D ( mem_out[10] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_12_ ( .D ( mem_out[11] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_13_ ( .D ( mem_out[12] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_14_ ( .D ( mem_out[13] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_15_ ( .D ( mem_out[14] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_16_ ( .D ( mem_out[15] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__38 ( .A ( mem_out[16] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module grid_clb_frac_lut4_mux_4 ( in , sram , sram_inv , lut3_out , lut4_out ) ; -input [0:15] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:1] lut3_out ; -output [0:0] lut4_out ; - -wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_4_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_5_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( - .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( - .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( - .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( - .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_5_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_6_ ( - .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__buf_2_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__buf_2_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__buf_2_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ; -endmodule - - -module grid_clb_frac_lut4_4 ( in , sram , sram_inv , mode , mode_inv , - lut3_out , lut4_out ) ; -input [0:3] in ; -input [0:15] sram ; -input [0:15] sram_inv ; -input [0:0] mode ; -input [0:0] mode_inv ; -output [0:1] lut3_out ; -output [0:0] lut4_out ; - -wire [0:0] sky130_fd_sc_hd__buf_2_0_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_1_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_2_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; -wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ; -wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ; -wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ; -wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ; -wire [0:0] sky130_fd_sc_hd__or2_1_0_X ; - -sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , - .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , - .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , - .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , - .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( - .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , - .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , - .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , - .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , - .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( - .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; -grid_clb_frac_lut4_mux_4 frac_lut4_mux_0_ ( .in ( sram ) , - .sram ( { sky130_fd_sc_hd__buf_2_0_X[0] , sky130_fd_sc_hd__buf_2_1_X[0] , - sky130_fd_sc_hd__buf_2_2_X[0] , sky130_fd_sc_hd__buf_2_3_X[0] } ) , - .sram_inv ( { sky130_fd_sc_hd__inv_1_0_Y[0] , - sky130_fd_sc_hd__inv_1_1_Y[0] , sky130_fd_sc_hd__inv_1_2_Y[0] , - sky130_fd_sc_hd__inv_1_3_Y[0] } ) , - .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_4 ( - prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out , - frac_lut4_lut4_out , ccff_tail ) ; -input [0:0] prog_clk ; -input [0:3] frac_lut4_in ; -input [0:0] ccff_head ; -output [0:1] frac_lut4_lut3_out ; -output [0:0] frac_lut4_lut4_out ; -output [0:0] ccff_tail ; - -wire [0:15] frac_lut4_0__undriven_sram_inv ; -wire [0:0] frac_lut4_0_mode ; -wire [0:15] frac_lut4_0_sram ; - -grid_clb_frac_lut4_4 frac_lut4_0_ ( .in ( frac_lut4_in ) , - .sram ( frac_lut4_0_sram ) , - .sram_inv ( frac_lut4_0__undriven_sram_inv ) , - .mode ( frac_lut4_0_mode ) , - .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , - .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) ) ; -grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_4 frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , - .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , - frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] , - frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , - frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , - frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , - frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_4 ( - prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p2 ) ; -input [0:0] prog_clk ; -input [0:3] frac_logic_in ; -input [0:0] ccff_head ; -output [0:1] frac_logic_out ; -output [0:0] ccff_tail ; -input p2 ; - -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; -wire [0:1] mux_frac_logic_out_0_undriven_sram_inv ; -wire [0:1] mux_tree_size2_0_sram ; - -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( - .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , - .ccff_head ( ccff_head ) , - .frac_lut4_lut3_out ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] , - frac_logic_out[1] } ) , - - .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , - .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ; -grid_clb_mux_tree_size2_28 mux_frac_logic_out_0 ( - .in ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] - } ) , - .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_frac_logic_out_0_undriven_sram_inv ) , - .out ( frac_logic_out[0] ) , .p2 ( p2 ) ) ; -grid_clb_mux_tree_size2_mem_28 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) ) ; -grid_clb_direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( frac_logic_out[1] ) ) ; -grid_clb_direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( frac_logic_in[0] ) ) ; -grid_clb_direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( frac_logic_in[1] ) ) ; -grid_clb_direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( frac_logic_in[2] ) ) ; -grid_clb_direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( frac_logic_in[3] ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_4 ( - prog_clk , Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , - fabric_clk , ccff_head , fabric_out , fabric_regout , fabric_sc_out , - ccff_tail , p_abuf0 , p_abuf2 , p_abuf3 , p2 , p3 ) ; -input [0:0] prog_clk ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:3] fabric_in ; -input [0:0] fabric_regin ; -input [0:0] fabric_sc_in ; -input [0:0] fabric_clk ; -input [0:0] ccff_head ; -output [0:1] fabric_out ; -output [0:0] fabric_regout ; -output [0:0] fabric_sc_out ; -output [0:0] ccff_tail ; -output p_abuf0 ; -output p_abuf2 ; -output p_abuf3 ; -input p2 ; -input p3 ; - -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; -wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; -wire [0:1] mux_fabric_out_0_undriven_sram_inv ; -wire [0:1] mux_fabric_out_1_undriven_sram_inv ; -wire [0:1] mux_ff_0_D_0_undriven_sram_inv ; -wire [0:1] mux_tree_size2_0_sram ; -wire [0:1] mux_tree_size2_1_sram ; -wire [0:0] mux_tree_size2_2_out ; -wire [0:1] mux_tree_size2_2_sram ; -wire [0:0] mux_tree_size2_mem_0_ccff_tail ; -wire [0:0] mux_tree_size2_mem_1_ccff_tail ; - -assign fabric_regout[0] = fabric_sc_out[0] ; - -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( - .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , - .ccff_head ( ccff_head ) , - .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , - .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .p2 ( p2 ) ) ; -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_8 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( - .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , - .ff_DI ( fabric_sc_in ) , - .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , - .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_9 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( - .Test_en ( Test_en ) , .clk ( clk ) , - .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , - .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , - .ff_Q ( fabric_sc_out ) , - .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; -grid_clb_mux_tree_size2_12 mux_fabric_out_0 ( - .in ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] - } ) , - .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_fabric_out_0_undriven_sram_inv ) , - .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p3 ( p3 ) ) ; -grid_clb_mux_tree_size2_13 mux_fabric_out_1 ( - .in ( { fabric_sc_out[0] , - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] - } ) , - .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( mux_fabric_out_1_undriven_sram_inv ) , - .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf2 ) , .p_abuf1 ( p_abuf3 ) , - .p3 ( p3 ) ) ; -grid_clb_mux_tree_size2_14 mux_ff_0_D_0 ( - .in ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , - fabric_regin[0] } ) , - .sram ( mux_tree_size2_2_sram ) , - .sram_inv ( mux_ff_0_D_0_undriven_sram_inv ) , - .out ( mux_tree_size2_2_out ) , .p2 ( p2 ) ) ; -grid_clb_mux_tree_size2_mem_12 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_size2_0_sram ) ) ; -grid_clb_mux_tree_size2_mem_13 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_size2_1_sram ) ) ; -grid_clb_mux_tree_size2_mem_14 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , - .mem_out ( mux_tree_size2_2_sram ) ) ; -grid_clb_direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fabric_sc_out ) ) ; -grid_clb_direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fabric_sc_out ) ) ; -grid_clb_direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( fabric_in[0] ) ) ; -grid_clb_direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_6 } ) , - .out ( fabric_in[1] ) ) ; -grid_clb_direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_7 } ) , - .out ( fabric_in[2] ) ) ; -grid_clb_direct_interc direct_interc_5_ ( - .in ( { SYNOPSYS_UNCONNECTED_8 } ) , - .out ( fabric_in[3] ) ) ; -grid_clb_direct_interc direct_interc_6_ ( - .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( fabric_sc_in ) ) ; -grid_clb_direct_interc direct_interc_7_ ( - .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( fabric_clk ) ) ; -grid_clb_direct_interc direct_interc_8_ ( - .in ( { SYNOPSYS_UNCONNECTED_11 } ) , - - .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) ) ; -grid_clb_direct_interc direct_interc_9_ ( - .in ( { SYNOPSYS_UNCONNECTED_12 } ) , - - .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ) ; -grid_clb_direct_interc direct_interc_10_ ( - .in ( { SYNOPSYS_UNCONNECTED_13 } ) , - .out ( fabric_clk ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_4 ( prog_clk , Test_en , - clk , fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , - fle_regout , fle_sc_out , ccff_tail , p_abuf0 , p_abuf2 , p_abuf3 , p2 , - p3 ) ; -input [0:0] prog_clk ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:3] fle_in ; -input [0:0] fle_regin ; -input [0:0] fle_sc_in ; -input [0:0] fle_clk ; -input [0:0] ccff_head ; -output [0:1] fle_out ; -output [0:0] fle_regout ; -output [0:0] fle_sc_out ; -output [0:0] ccff_tail ; -output p_abuf0 ; -output p_abuf2 ; -output p_abuf3 ; -input p2 ; -input p3 ; - -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( - .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , - .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , - .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , - .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , - .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf2 ( p_abuf2 ) , - .p_abuf3 ( p_abuf3 ) , .p2 ( p2 ) , .p3 ( p3 ) ) ; -grid_clb_direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( { p_abuf3 } ) ) ; -grid_clb_direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( fle_regout ) ) ; -grid_clb_direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fle_sc_out ) ) ; -grid_clb_direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fle_in[0] ) ) ; -grid_clb_direct_interc direct_interc_5_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( fle_in[1] ) ) ; -grid_clb_direct_interc direct_interc_6_ ( - .in ( { SYNOPSYS_UNCONNECTED_6 } ) , - .out ( fle_in[2] ) ) ; -grid_clb_direct_interc direct_interc_7_ ( - .in ( { SYNOPSYS_UNCONNECTED_7 } ) , - .out ( fle_in[3] ) ) ; -grid_clb_direct_interc direct_interc_8_ ( - .in ( { SYNOPSYS_UNCONNECTED_8 } ) , - .out ( fle_regin ) ) ; -grid_clb_direct_interc direct_interc_9_ ( - .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( fle_sc_in ) ) ; -grid_clb_direct_interc direct_interc_10_ ( - .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( fle_clk ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_mem_11 ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__37 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_mem_10 ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__36 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_mem_9 ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__35 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_11 ( in , sram , sram_inv , out , p2 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p2 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_10 ( in , sram , sram_inv , out , p_abuf0 , - p_abuf1 , p2 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -output p_abuf0 ; -output p_abuf1 ; -input p2 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf1 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_76 ( .A ( p_abuf1 ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_77 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_9 ( in , sram , sram_inv , out , p_abuf0 , p2 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -output p_abuf0 ; -input p2 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p2 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_75 ( .A ( out[0] ) , .X ( p_abuf0 ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_7 ( - Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:0] ff_D ; -input [0:0] ff_DI ; -output [0:0] ff_Q ; -input [0:0] ff_clk ; - -sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , - .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_6 ( - Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:0] ff_D ; -input [0:0] ff_DI ; -output [0:0] ff_Q ; -input [0:0] ff_clk ; - -sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , - .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_mem_27 ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__34 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_27 ( in , sram , sram_inv , out , p2 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p2 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_3 ( prog_clk , - ccff_head , ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:16] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_5_ ( .D ( mem_out[4] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_6_ ( .D ( mem_out[5] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_7_ ( .D ( mem_out[6] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_8_ ( .D ( mem_out[7] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_9_ ( .D ( mem_out[8] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_10_ ( .D ( mem_out[9] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_11_ ( .D ( mem_out[10] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_12_ ( .D ( mem_out[11] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_13_ ( .D ( mem_out[12] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_14_ ( .D ( mem_out[13] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_15_ ( .D ( mem_out[14] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_16_ ( .D ( mem_out[15] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__33 ( .A ( mem_out[16] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module grid_clb_frac_lut4_mux_3 ( in , sram , sram_inv , lut3_out , lut4_out ) ; -input [0:15] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:1] lut3_out ; -output [0:0] lut4_out ; - -wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_4_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_5_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( - .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( - .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( - .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_5_ ( - .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_5_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_6_ ( - .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__buf_2_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__buf_2_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__buf_2_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ; -endmodule - - -module grid_clb_frac_lut4_3 ( in , sram , sram_inv , mode , mode_inv , - lut3_out , lut4_out ) ; -input [0:3] in ; -input [0:15] sram ; -input [0:15] sram_inv ; -input [0:0] mode ; -input [0:0] mode_inv ; -output [0:1] lut3_out ; -output [0:0] lut4_out ; - -wire [0:0] sky130_fd_sc_hd__buf_2_0_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_1_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_2_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; -wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ; -wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ; -wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ; -wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ; -wire [0:0] sky130_fd_sc_hd__or2_1_0_X ; - -sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , - .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , - .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , - .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , - .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( - .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , - .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , - .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , - .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , - .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( - .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; -grid_clb_frac_lut4_mux_3 frac_lut4_mux_0_ ( .in ( sram ) , - .sram ( { sky130_fd_sc_hd__buf_2_0_X[0] , sky130_fd_sc_hd__buf_2_1_X[0] , - sky130_fd_sc_hd__buf_2_2_X[0] , sky130_fd_sc_hd__buf_2_3_X[0] } ) , - .sram_inv ( { sky130_fd_sc_hd__inv_1_0_Y[0] , - sky130_fd_sc_hd__inv_1_1_Y[0] , sky130_fd_sc_hd__inv_1_2_Y[0] , - sky130_fd_sc_hd__inv_1_3_Y[0] } ) , - .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_3 ( - prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out , - frac_lut4_lut4_out , ccff_tail ) ; -input [0:0] prog_clk ; -input [0:3] frac_lut4_in ; -input [0:0] ccff_head ; -output [0:1] frac_lut4_lut3_out ; -output [0:0] frac_lut4_lut4_out ; -output [0:0] ccff_tail ; - -wire [0:15] frac_lut4_0__undriven_sram_inv ; -wire [0:0] frac_lut4_0_mode ; -wire [0:15] frac_lut4_0_sram ; - -grid_clb_frac_lut4_3 frac_lut4_0_ ( .in ( frac_lut4_in ) , - .sram ( frac_lut4_0_sram ) , - .sram_inv ( frac_lut4_0__undriven_sram_inv ) , - .mode ( frac_lut4_0_mode ) , - .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , - .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) ) ; -grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_3 frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , - .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , - frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] , - frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , - frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , - frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , - frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_3 ( - prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p2 ) ; -input [0:0] prog_clk ; -input [0:3] frac_logic_in ; -input [0:0] ccff_head ; -output [0:1] frac_logic_out ; -output [0:0] ccff_tail ; -input p2 ; - -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; -wire [0:1] mux_frac_logic_out_0_undriven_sram_inv ; -wire [0:1] mux_tree_size2_0_sram ; - -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( - .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , - .ccff_head ( ccff_head ) , - .frac_lut4_lut3_out ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] , - frac_logic_out[1] } ) , - - .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , - .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ; -grid_clb_mux_tree_size2_27 mux_frac_logic_out_0 ( - .in ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] - } ) , - .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_frac_logic_out_0_undriven_sram_inv ) , - .out ( frac_logic_out[0] ) , .p2 ( p2 ) ) ; -grid_clb_mux_tree_size2_mem_27 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) ) ; -grid_clb_direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( frac_logic_out[1] ) ) ; -grid_clb_direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( frac_logic_in[0] ) ) ; -grid_clb_direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( frac_logic_in[1] ) ) ; -grid_clb_direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( frac_logic_in[2] ) ) ; -grid_clb_direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( frac_logic_in[3] ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_3 ( - prog_clk , Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , - fabric_clk , ccff_head , fabric_out , fabric_regout , fabric_sc_out , - ccff_tail , p_abuf0 , p_abuf2 , p_abuf3 , p2 ) ; -input [0:0] prog_clk ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:3] fabric_in ; -input [0:0] fabric_regin ; -input [0:0] fabric_sc_in ; -input [0:0] fabric_clk ; -input [0:0] ccff_head ; -output [0:1] fabric_out ; -output [0:0] fabric_regout ; -output [0:0] fabric_sc_out ; -output [0:0] ccff_tail ; -output p_abuf0 ; -output p_abuf2 ; -output p_abuf3 ; -input p2 ; - -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; -wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; -wire [0:1] mux_fabric_out_0_undriven_sram_inv ; -wire [0:1] mux_fabric_out_1_undriven_sram_inv ; -wire [0:1] mux_ff_0_D_0_undriven_sram_inv ; -wire [0:1] mux_tree_size2_0_sram ; -wire [0:1] mux_tree_size2_1_sram ; -wire [0:0] mux_tree_size2_2_out ; -wire [0:1] mux_tree_size2_2_sram ; -wire [0:0] mux_tree_size2_mem_0_ccff_tail ; -wire [0:0] mux_tree_size2_mem_1_ccff_tail ; - -assign fabric_regout[0] = fabric_sc_out[0] ; - -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( - .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , - .ccff_head ( ccff_head ) , - .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , - .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .p2 ( p2 ) ) ; -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( - .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , - .ff_DI ( fabric_sc_in ) , - .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , - .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_7 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( - .Test_en ( Test_en ) , .clk ( clk ) , - .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , - .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , - .ff_Q ( fabric_sc_out ) , - .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; -grid_clb_mux_tree_size2_9 mux_fabric_out_0 ( - .in ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] - } ) , - .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_fabric_out_0_undriven_sram_inv ) , - .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p2 ( p2 ) ) ; -grid_clb_mux_tree_size2_10 mux_fabric_out_1 ( - .in ( { fabric_sc_out[0] , - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] - } ) , - .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( mux_fabric_out_1_undriven_sram_inv ) , - .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf2 ) , .p_abuf1 ( p_abuf3 ) , - .p2 ( p2 ) ) ; -grid_clb_mux_tree_size2_11 mux_ff_0_D_0 ( - .in ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , - fabric_regin[0] } ) , - .sram ( mux_tree_size2_2_sram ) , - .sram_inv ( mux_ff_0_D_0_undriven_sram_inv ) , - .out ( mux_tree_size2_2_out ) , .p2 ( p2 ) ) ; -grid_clb_mux_tree_size2_mem_9 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_size2_0_sram ) ) ; -grid_clb_mux_tree_size2_mem_10 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_size2_1_sram ) ) ; -grid_clb_mux_tree_size2_mem_11 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , - .mem_out ( mux_tree_size2_2_sram ) ) ; -grid_clb_direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fabric_sc_out ) ) ; -grid_clb_direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fabric_sc_out ) ) ; -grid_clb_direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( fabric_in[0] ) ) ; -grid_clb_direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_6 } ) , - .out ( fabric_in[1] ) ) ; -grid_clb_direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_7 } ) , - .out ( fabric_in[2] ) ) ; -grid_clb_direct_interc direct_interc_5_ ( - .in ( { SYNOPSYS_UNCONNECTED_8 } ) , - .out ( fabric_in[3] ) ) ; -grid_clb_direct_interc direct_interc_6_ ( - .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( fabric_sc_in ) ) ; -grid_clb_direct_interc direct_interc_7_ ( - .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( fabric_clk ) ) ; -grid_clb_direct_interc direct_interc_8_ ( - .in ( { SYNOPSYS_UNCONNECTED_11 } ) , - - .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) ) ; -grid_clb_direct_interc direct_interc_9_ ( - .in ( { SYNOPSYS_UNCONNECTED_12 } ) , - - .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ) ; -grid_clb_direct_interc direct_interc_10_ ( - .in ( { SYNOPSYS_UNCONNECTED_13 } ) , - .out ( fabric_clk ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_3 ( prog_clk , Test_en , - clk , fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , - fle_regout , fle_sc_out , ccff_tail , p_abuf0 , p_abuf2 , p_abuf3 , p2 ) ; -input [0:0] prog_clk ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:3] fle_in ; -input [0:0] fle_regin ; -input [0:0] fle_sc_in ; -input [0:0] fle_clk ; -input [0:0] ccff_head ; -output [0:1] fle_out ; -output [0:0] fle_regout ; -output [0:0] fle_sc_out ; -output [0:0] ccff_tail ; -output p_abuf0 ; -output p_abuf2 ; -output p_abuf3 ; -input p2 ; - -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( - .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , - .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , - .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , - .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , - .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf2 ( p_abuf2 ) , - .p_abuf3 ( p_abuf3 ) , .p2 ( p2 ) ) ; -grid_clb_direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( { p_abuf3 } ) ) ; -grid_clb_direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( fle_regout ) ) ; -grid_clb_direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fle_sc_out ) ) ; -grid_clb_direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fle_in[0] ) ) ; -grid_clb_direct_interc direct_interc_5_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( fle_in[1] ) ) ; -grid_clb_direct_interc direct_interc_6_ ( - .in ( { SYNOPSYS_UNCONNECTED_6 } ) , - .out ( fle_in[2] ) ) ; -grid_clb_direct_interc direct_interc_7_ ( - .in ( { SYNOPSYS_UNCONNECTED_7 } ) , - .out ( fle_in[3] ) ) ; -grid_clb_direct_interc direct_interc_8_ ( - .in ( { SYNOPSYS_UNCONNECTED_8 } ) , - .out ( fle_regin ) ) ; -grid_clb_direct_interc direct_interc_9_ ( - .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( fle_sc_in ) ) ; -grid_clb_direct_interc direct_interc_10_ ( - .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( fle_clk ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_mem_8 ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__32 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_mem_7 ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__31 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__30 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_8 ( in , sram , sram_inv , out , p2 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p2 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_7 ( in , sram , sram_inv , out , p_abuf0 , - p_abuf1 , p2 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -output p_abuf0 ; -output p_abuf1 ; -input p2 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf1 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_72 ( .A ( p_abuf1 ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_73 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_6 ( in , sram , sram_inv , out , p_abuf0 , - p_abuf1 , p2 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -output p_abuf0 ; -output p_abuf1 ; -input p2 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf1 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_70 ( .A ( p_abuf1 ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_71 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_5 ( - Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:0] ff_D ; -input [0:0] ff_DI ; -output [0:0] ff_Q ; -input [0:0] ff_clk ; - -sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , - .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_4 ( - Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:0] ff_D ; -input [0:0] ff_DI ; -output [0:0] ff_Q ; -input [0:0] ff_clk ; - -sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , - .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_mem_26 ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__29 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_26 ( in , sram , sram_inv , out , p2 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p2 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_2 ( prog_clk , - ccff_head , ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:16] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_5_ ( .D ( mem_out[4] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_6_ ( .D ( mem_out[5] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_7_ ( .D ( mem_out[6] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_8_ ( .D ( mem_out[7] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_9_ ( .D ( mem_out[8] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_10_ ( .D ( mem_out[9] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_11_ ( .D ( mem_out[10] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_12_ ( .D ( mem_out[11] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_13_ ( .D ( mem_out[12] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_14_ ( .D ( mem_out[13] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_15_ ( .D ( mem_out[14] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_16_ ( .D ( mem_out[15] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__28 ( .A ( mem_out[16] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module grid_clb_frac_lut4_mux_2 ( in , sram , sram_inv , lut3_out , lut4_out ) ; -input [0:15] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:1] lut3_out ; -output [0:0] lut4_out ; - -wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_4_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_5_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( - .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( - .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( - .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( - .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_5_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_6_ ( - .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__buf_2_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__buf_2_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__buf_2_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ; -endmodule - - -module grid_clb_frac_lut4_2 ( in , sram , sram_inv , mode , mode_inv , - lut3_out , lut4_out ) ; -input [0:3] in ; -input [0:15] sram ; -input [0:15] sram_inv ; -input [0:0] mode ; -input [0:0] mode_inv ; -output [0:1] lut3_out ; -output [0:0] lut4_out ; - -wire [0:0] sky130_fd_sc_hd__buf_2_0_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_1_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_2_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; -wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ; -wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ; -wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ; -wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ; -wire [0:0] sky130_fd_sc_hd__or2_1_0_X ; - -sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , - .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , - .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , - .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , - .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( - .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , - .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , - .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , - .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , - .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( - .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; -grid_clb_frac_lut4_mux_2 frac_lut4_mux_0_ ( .in ( sram ) , - .sram ( { sky130_fd_sc_hd__buf_2_0_X[0] , sky130_fd_sc_hd__buf_2_1_X[0] , - sky130_fd_sc_hd__buf_2_2_X[0] , sky130_fd_sc_hd__buf_2_3_X[0] } ) , - .sram_inv ( { sky130_fd_sc_hd__inv_1_0_Y[0] , - sky130_fd_sc_hd__inv_1_1_Y[0] , sky130_fd_sc_hd__inv_1_2_Y[0] , - sky130_fd_sc_hd__inv_1_3_Y[0] } ) , - .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_2 ( - prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out , - frac_lut4_lut4_out , ccff_tail ) ; -input [0:0] prog_clk ; -input [0:3] frac_lut4_in ; -input [0:0] ccff_head ; -output [0:1] frac_lut4_lut3_out ; -output [0:0] frac_lut4_lut4_out ; -output [0:0] ccff_tail ; - -wire [0:15] frac_lut4_0__undriven_sram_inv ; -wire [0:0] frac_lut4_0_mode ; -wire [0:15] frac_lut4_0_sram ; - -grid_clb_frac_lut4_2 frac_lut4_0_ ( .in ( frac_lut4_in ) , - .sram ( frac_lut4_0_sram ) , - .sram_inv ( frac_lut4_0__undriven_sram_inv ) , - .mode ( frac_lut4_0_mode ) , - .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , - .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) ) ; -grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_2 frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , - .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , - frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] , - frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , - frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , - frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , - frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_2 ( - prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p2 ) ; -input [0:0] prog_clk ; -input [0:3] frac_logic_in ; -input [0:0] ccff_head ; -output [0:1] frac_logic_out ; -output [0:0] ccff_tail ; -input p2 ; - -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; -wire [0:1] mux_frac_logic_out_0_undriven_sram_inv ; -wire [0:1] mux_tree_size2_0_sram ; - -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( - .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , - .ccff_head ( ccff_head ) , - .frac_lut4_lut3_out ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] , - frac_logic_out[1] } ) , - - .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , - .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ; -grid_clb_mux_tree_size2_26 mux_frac_logic_out_0 ( - .in ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] - } ) , - .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_frac_logic_out_0_undriven_sram_inv ) , - .out ( frac_logic_out[0] ) , .p2 ( p2 ) ) ; -grid_clb_mux_tree_size2_mem_26 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) ) ; -grid_clb_direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( frac_logic_out[1] ) ) ; -grid_clb_direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( frac_logic_in[0] ) ) ; -grid_clb_direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( frac_logic_in[1] ) ) ; -grid_clb_direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( frac_logic_in[2] ) ) ; -grid_clb_direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( frac_logic_in[3] ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_2 ( - prog_clk , Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , - fabric_clk , ccff_head , fabric_out , fabric_regout , fabric_sc_out , - ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p_abuf3 , p2 ) ; -input [0:0] prog_clk ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:3] fabric_in ; -input [0:0] fabric_regin ; -input [0:0] fabric_sc_in ; -input [0:0] fabric_clk ; -input [0:0] ccff_head ; -output [0:1] fabric_out ; -output [0:0] fabric_regout ; -output [0:0] fabric_sc_out ; -output [0:0] ccff_tail ; -output p_abuf0 ; -output p_abuf1 ; -output p_abuf2 ; -output p_abuf3 ; -input p2 ; - -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; -wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; -wire [0:1] mux_fabric_out_0_undriven_sram_inv ; -wire [0:1] mux_fabric_out_1_undriven_sram_inv ; -wire [0:1] mux_ff_0_D_0_undriven_sram_inv ; -wire [0:1] mux_tree_size2_0_sram ; -wire [0:1] mux_tree_size2_1_sram ; -wire [0:0] mux_tree_size2_2_out ; -wire [0:1] mux_tree_size2_2_sram ; -wire [0:0] mux_tree_size2_mem_0_ccff_tail ; -wire [0:0] mux_tree_size2_mem_1_ccff_tail ; - -assign fabric_regout[0] = fabric_sc_out[0] ; - -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( - .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , - .ccff_head ( ccff_head ) , - .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , - .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .p2 ( p2 ) ) ; -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( - .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , - .ff_DI ( fabric_sc_in ) , - .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , - .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( - .Test_en ( Test_en ) , .clk ( clk ) , - .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , - .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , - .ff_Q ( fabric_sc_out ) , - .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; -grid_clb_mux_tree_size2_6 mux_fabric_out_0 ( - .in ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] - } ) , - .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_fabric_out_0_undriven_sram_inv ) , - .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , - .p2 ( p2 ) ) ; -grid_clb_mux_tree_size2_7 mux_fabric_out_1 ( - .in ( { fabric_sc_out[0] , - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] - } ) , - .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( mux_fabric_out_1_undriven_sram_inv ) , - .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf2 ) , .p_abuf1 ( p_abuf3 ) , - .p2 ( p2 ) ) ; -grid_clb_mux_tree_size2_8 mux_ff_0_D_0 ( - .in ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , - fabric_regin[0] } ) , - .sram ( mux_tree_size2_2_sram ) , - .sram_inv ( mux_ff_0_D_0_undriven_sram_inv ) , - .out ( mux_tree_size2_2_out ) , .p2 ( p2 ) ) ; -grid_clb_mux_tree_size2_mem_6 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_size2_0_sram ) ) ; -grid_clb_mux_tree_size2_mem_7 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_size2_1_sram ) ) ; -grid_clb_mux_tree_size2_mem_8 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , - .mem_out ( mux_tree_size2_2_sram ) ) ; -grid_clb_direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fabric_sc_out ) ) ; -grid_clb_direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fabric_sc_out ) ) ; -grid_clb_direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( fabric_in[0] ) ) ; -grid_clb_direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_6 } ) , - .out ( fabric_in[1] ) ) ; -grid_clb_direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_7 } ) , - .out ( fabric_in[2] ) ) ; -grid_clb_direct_interc direct_interc_5_ ( - .in ( { SYNOPSYS_UNCONNECTED_8 } ) , - .out ( fabric_in[3] ) ) ; -grid_clb_direct_interc direct_interc_6_ ( - .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( fabric_sc_in ) ) ; -grid_clb_direct_interc direct_interc_7_ ( - .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( fabric_clk ) ) ; -grid_clb_direct_interc direct_interc_8_ ( - .in ( { SYNOPSYS_UNCONNECTED_11 } ) , - - .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) ) ; -grid_clb_direct_interc direct_interc_9_ ( - .in ( { SYNOPSYS_UNCONNECTED_12 } ) , - - .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ) ; -grid_clb_direct_interc direct_interc_10_ ( - .in ( { SYNOPSYS_UNCONNECTED_13 } ) , - .out ( fabric_clk ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_2 ( prog_clk , Test_en , - clk , fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , - fle_regout , fle_sc_out , ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , - p_abuf3 , p2 ) ; -input [0:0] prog_clk ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:3] fle_in ; -input [0:0] fle_regin ; -input [0:0] fle_sc_in ; -input [0:0] fle_clk ; -input [0:0] ccff_head ; -output [0:1] fle_out ; -output [0:0] fle_regout ; -output [0:0] fle_sc_out ; -output [0:0] ccff_tail ; -output p_abuf0 ; -output p_abuf1 ; -output p_abuf2 ; -output p_abuf3 ; -input p2 ; - -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( - .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , - .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , - .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , - .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , - .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , - .p_abuf2 ( p_abuf2 ) , .p_abuf3 ( p_abuf3 ) , .p2 ( p2 ) ) ; -grid_clb_direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( { p_abuf1 } ) ) ; -grid_clb_direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( { p_abuf3 } ) ) ; -grid_clb_direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fle_regout ) ) ; -grid_clb_direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fle_sc_out ) ) ; -grid_clb_direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( fle_in[0] ) ) ; -grid_clb_direct_interc direct_interc_5_ ( - .in ( { SYNOPSYS_UNCONNECTED_6 } ) , - .out ( fle_in[1] ) ) ; -grid_clb_direct_interc direct_interc_6_ ( - .in ( { SYNOPSYS_UNCONNECTED_7 } ) , - .out ( fle_in[2] ) ) ; -grid_clb_direct_interc direct_interc_7_ ( - .in ( { SYNOPSYS_UNCONNECTED_8 } ) , - .out ( fle_in[3] ) ) ; -grid_clb_direct_interc direct_interc_8_ ( - .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( fle_regin ) ) ; -grid_clb_direct_interc direct_interc_9_ ( - .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( fle_sc_in ) ) ; -grid_clb_direct_interc direct_interc_10_ ( - .in ( { SYNOPSYS_UNCONNECTED_11 } ) , - .out ( fle_clk ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__27 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__26 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__25 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_4 ( in , sram , sram_inv , out , p_abuf0 , p1 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -output p_abuf0 ; -input p1 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p1 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_69 ( .A ( out[0] ) , .X ( p_abuf0 ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_3 ( in , sram , sram_inv , out , p_abuf0 , - p_abuf1 , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -output p_abuf0 ; -output p_abuf1 ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf1 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_66 ( .A ( p_abuf1 ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_67 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_3 ( - Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:0] ff_D ; -input [0:0] ff_DI ; -output [0:0] ff_Q ; -input [0:0] ff_clk ; - -sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , - .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_2 ( - Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:0] ff_D ; -input [0:0] ff_DI ; -output [0:0] ff_Q ; -input [0:0] ff_clk ; - -sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , - .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_mem_25 ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__24 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_25 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_1 ( prog_clk , - ccff_head , ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:16] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_5_ ( .D ( mem_out[4] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_6_ ( .D ( mem_out[5] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_7_ ( .D ( mem_out[6] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_8_ ( .D ( mem_out[7] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_9_ ( .D ( mem_out[8] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_10_ ( .D ( mem_out[9] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_11_ ( .D ( mem_out[10] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_12_ ( .D ( mem_out[11] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_13_ ( .D ( mem_out[12] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_14_ ( .D ( mem_out[13] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_15_ ( .D ( mem_out[14] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_16_ ( .D ( mem_out[15] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__23 ( .A ( mem_out[16] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module grid_clb_frac_lut4_mux_1 ( in , sram , sram_inv , lut3_out , lut4_out ) ; -input [0:15] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:1] lut3_out ; -output [0:0] lut4_out ; - -wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_4_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_5_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( - .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( - .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( - .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( - .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_5_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_6_ ( - .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__buf_2_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__buf_2_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__buf_2_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ; -endmodule - - -module grid_clb_frac_lut4_1 ( in , sram , sram_inv , mode , mode_inv , - lut3_out , lut4_out ) ; -input [0:3] in ; -input [0:15] sram ; -input [0:15] sram_inv ; -input [0:0] mode ; -input [0:0] mode_inv ; -output [0:1] lut3_out ; -output [0:0] lut4_out ; - -wire [0:0] sky130_fd_sc_hd__buf_2_0_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_1_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_2_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; -wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ; -wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ; -wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ; -wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ; -wire [0:0] sky130_fd_sc_hd__or2_1_0_X ; - -sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , - .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , - .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , - .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , - .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( - .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , - .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , - .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , - .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , - .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( - .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; -grid_clb_frac_lut4_mux_1 frac_lut4_mux_0_ ( .in ( sram ) , - .sram ( { sky130_fd_sc_hd__buf_2_0_X[0] , sky130_fd_sc_hd__buf_2_1_X[0] , - sky130_fd_sc_hd__buf_2_2_X[0] , sky130_fd_sc_hd__buf_2_3_X[0] } ) , - .sram_inv ( { sky130_fd_sc_hd__inv_1_0_Y[0] , - sky130_fd_sc_hd__inv_1_1_Y[0] , sky130_fd_sc_hd__inv_1_2_Y[0] , - sky130_fd_sc_hd__inv_1_3_Y[0] } ) , - .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_1 ( - prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out , - frac_lut4_lut4_out , ccff_tail ) ; -input [0:0] prog_clk ; -input [0:3] frac_lut4_in ; -input [0:0] ccff_head ; -output [0:1] frac_lut4_lut3_out ; -output [0:0] frac_lut4_lut4_out ; -output [0:0] ccff_tail ; - -wire [0:15] frac_lut4_0__undriven_sram_inv ; -wire [0:0] frac_lut4_0_mode ; -wire [0:15] frac_lut4_0_sram ; - -grid_clb_frac_lut4_1 frac_lut4_0_ ( .in ( frac_lut4_in ) , - .sram ( frac_lut4_0_sram ) , - .sram_inv ( frac_lut4_0__undriven_sram_inv ) , - .mode ( frac_lut4_0_mode ) , - .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , - .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) ) ; -grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_1 frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , - .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , - frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] , - frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , - frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , - frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , - frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_1 ( - prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p0 ) ; -input [0:0] prog_clk ; -input [0:3] frac_logic_in ; -input [0:0] ccff_head ; -output [0:1] frac_logic_out ; -output [0:0] ccff_tail ; -input p0 ; - -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; -wire [0:1] mux_frac_logic_out_0_undriven_sram_inv ; -wire [0:1] mux_tree_size2_0_sram ; - -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( - .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , - .ccff_head ( ccff_head ) , - .frac_lut4_lut3_out ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] , - frac_logic_out[1] } ) , - - .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , - .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ; -grid_clb_mux_tree_size2_25 mux_frac_logic_out_0 ( - .in ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] - } ) , - .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_frac_logic_out_0_undriven_sram_inv ) , - .out ( frac_logic_out[0] ) , .p0 ( p0 ) ) ; -grid_clb_mux_tree_size2_mem_25 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) ) ; -grid_clb_direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( frac_logic_out[1] ) ) ; -grid_clb_direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( frac_logic_in[0] ) ) ; -grid_clb_direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( frac_logic_in[1] ) ) ; -grid_clb_direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( frac_logic_in[2] ) ) ; -grid_clb_direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( frac_logic_in[3] ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_1 ( - prog_clk , Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , - fabric_clk , ccff_head , fabric_out , fabric_regout , fabric_sc_out , - ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p0 , p1 ) ; -input [0:0] prog_clk ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:3] fabric_in ; -input [0:0] fabric_regin ; -input [0:0] fabric_sc_in ; -input [0:0] fabric_clk ; -input [0:0] ccff_head ; -output [0:1] fabric_out ; -output [0:0] fabric_regout ; -output [0:0] fabric_sc_out ; -output [0:0] ccff_tail ; -output p_abuf0 ; -output p_abuf1 ; -output p_abuf2 ; -input p0 ; -input p1 ; - -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; -wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; -wire [0:1] mux_fabric_out_0_undriven_sram_inv ; -wire [0:1] mux_fabric_out_1_undriven_sram_inv ; -wire [0:1] mux_ff_0_D_0_undriven_sram_inv ; -wire [0:1] mux_tree_size2_0_sram ; -wire [0:1] mux_tree_size2_1_sram ; -wire [0:0] mux_tree_size2_2_out ; -wire [0:1] mux_tree_size2_2_sram ; -wire [0:0] mux_tree_size2_mem_0_ccff_tail ; -wire [0:0] mux_tree_size2_mem_1_ccff_tail ; - -assign fabric_regout[0] = fabric_sc_out[0] ; - -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( - .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , - .ccff_head ( ccff_head ) , - .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , - .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .p0 ( p0 ) ) ; -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( - .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , - .ff_DI ( fabric_sc_in ) , - .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , - .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( - .Test_en ( Test_en ) , .clk ( clk ) , - .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , - .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , - .ff_Q ( fabric_sc_out ) , - .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; -grid_clb_mux_tree_size2_3 mux_fabric_out_0 ( - .in ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] - } ) , - .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_fabric_out_0_undriven_sram_inv ) , - .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , - .p0 ( p0 ) ) ; -grid_clb_mux_tree_size2_4 mux_fabric_out_1 ( - .in ( { fabric_sc_out[0] , - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] - } ) , - .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( mux_fabric_out_1_undriven_sram_inv ) , - .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf2 ) , .p1 ( p1 ) ) ; -grid_clb_mux_tree_size2_5 mux_ff_0_D_0 ( - .in ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , - fabric_regin[0] } ) , - .sram ( mux_tree_size2_2_sram ) , - .sram_inv ( mux_ff_0_D_0_undriven_sram_inv ) , - .out ( mux_tree_size2_2_out ) , .p0 ( p0 ) ) ; -grid_clb_mux_tree_size2_mem_3 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_size2_0_sram ) ) ; -grid_clb_mux_tree_size2_mem_4 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_size2_1_sram ) ) ; -grid_clb_mux_tree_size2_mem_5 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , - .mem_out ( mux_tree_size2_2_sram ) ) ; -grid_clb_direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fabric_sc_out ) ) ; -grid_clb_direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fabric_sc_out ) ) ; -grid_clb_direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( fabric_in[0] ) ) ; -grid_clb_direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_6 } ) , - .out ( fabric_in[1] ) ) ; -grid_clb_direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_7 } ) , - .out ( fabric_in[2] ) ) ; -grid_clb_direct_interc direct_interc_5_ ( - .in ( { SYNOPSYS_UNCONNECTED_8 } ) , - .out ( fabric_in[3] ) ) ; -grid_clb_direct_interc direct_interc_6_ ( - .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( fabric_sc_in ) ) ; -grid_clb_direct_interc direct_interc_7_ ( - .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( fabric_clk ) ) ; -grid_clb_direct_interc direct_interc_8_ ( - .in ( { SYNOPSYS_UNCONNECTED_11 } ) , - - .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) ) ; -grid_clb_direct_interc direct_interc_9_ ( - .in ( { SYNOPSYS_UNCONNECTED_12 } ) , - - .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ) ; -grid_clb_direct_interc direct_interc_10_ ( - .in ( { SYNOPSYS_UNCONNECTED_13 } ) , - .out ( fabric_clk ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_1 ( prog_clk , Test_en , - clk , fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , - fle_regout , fle_sc_out , ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p0 , - p1 ) ; -input [0:0] prog_clk ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:3] fle_in ; -input [0:0] fle_regin ; -input [0:0] fle_sc_in ; -input [0:0] fle_clk ; -input [0:0] ccff_head ; -output [0:1] fle_out ; -output [0:0] fle_regout ; -output [0:0] fle_sc_out ; -output [0:0] ccff_tail ; -output p_abuf0 ; -output p_abuf1 ; -output p_abuf2 ; -input p0 ; -input p1 ; - -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( - .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , - .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , - .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , - .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , - .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , - .p_abuf2 ( p_abuf2 ) , .p0 ( p0 ) , .p1 ( p1 ) ) ; -grid_clb_direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( { p_abuf1 } ) ) ; -grid_clb_direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( fle_regout ) ) ; -grid_clb_direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fle_sc_out ) ) ; -grid_clb_direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fle_in[0] ) ) ; -grid_clb_direct_interc direct_interc_5_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( fle_in[1] ) ) ; -grid_clb_direct_interc direct_interc_6_ ( - .in ( { SYNOPSYS_UNCONNECTED_6 } ) , - .out ( fle_in[2] ) ) ; -grid_clb_direct_interc direct_interc_7_ ( - .in ( { SYNOPSYS_UNCONNECTED_7 } ) , - .out ( fle_in[3] ) ) ; -grid_clb_direct_interc direct_interc_8_ ( - .in ( { SYNOPSYS_UNCONNECTED_8 } ) , - .out ( fle_regin ) ) ; -grid_clb_direct_interc direct_interc_9_ ( - .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( fle_sc_in ) ) ; -grid_clb_direct_interc direct_interc_10_ ( - .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( fle_clk ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__22 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__21 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__20 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_1 ( in , sram , sram_inv , out , p_abuf0 , - p_abuf1 , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -output p_abuf0 ; -output p_abuf1 ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf1 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_64 ( .A ( p_abuf1 ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_65 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_0 ( in , sram , sram_inv , out , p_abuf0 , - p_abuf1 , p1 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -output p_abuf0 ; -output p_abuf1 ; -input p1 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf1 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_62 ( .A ( p_abuf1 ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_63 ( .A ( p_abuf1 ) , - .X ( BUF_net_63 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_131 ( .A ( BUF_net_63 ) , - .X ( p_abuf0 ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( - Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:0] ff_D ; -input [0:0] ff_DI ; -output [0:0] ff_Q ; -input [0:0] ff_clk ; - -sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , - .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( - Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:0] ff_D ; -input [0:0] ff_DI ; -output [0:0] ff_Q ; -input [0:0] ff_clk ; - -sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , - .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) ) ; -endmodule - - -module grid_clb_direct_interc ( in , out ) ; -input [0:0] in ; -output [0:0] out ; - -assign out[0] = in[0] ; -endmodule - - -module grid_clb_mux_tree_size2_mem_24 ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__19 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module grid_clb_mux_tree_size2_24 ( in , sram , sram_inv , out , p1 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p1 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_0 ( prog_clk , - ccff_head , ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:16] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_5_ ( .D ( mem_out[4] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_6_ ( .D ( mem_out[5] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_7_ ( .D ( mem_out[6] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_8_ ( .D ( mem_out[7] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_9_ ( .D ( mem_out[8] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_10_ ( .D ( mem_out[9] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_11_ ( .D ( mem_out[10] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_12_ ( .D ( mem_out[11] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_13_ ( .D ( mem_out[12] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_14_ ( .D ( mem_out[13] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_15_ ( .D ( mem_out[14] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_16_ ( .D ( mem_out[15] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__18 ( .A ( mem_out[16] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module grid_clb_frac_lut4_mux_0 ( in , sram , sram_inv , lut3_out , lut4_out ) ; -input [0:15] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:1] lut3_out ; -output [0:0] lut4_out ; - -wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_4_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_5_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( - .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( - .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( - .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( - .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_5_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_6_ ( - .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__buf_2_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__buf_2_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__buf_2_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ; -endmodule - - -module grid_clb_frac_lut4_0 ( in , sram , sram_inv , mode , mode_inv , - lut3_out , lut4_out ) ; -input [0:3] in ; -input [0:15] sram ; -input [0:15] sram_inv ; -input [0:0] mode ; -input [0:0] mode_inv ; -output [0:1] lut3_out ; -output [0:0] lut4_out ; - -wire [0:0] sky130_fd_sc_hd__buf_2_0_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_1_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_2_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; -wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ; -wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ; -wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ; -wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ; -wire [0:0] sky130_fd_sc_hd__or2_1_0_X ; - -sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , - .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , - .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , - .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , - .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( - .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , - .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , - .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , - .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , - .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( - .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; -grid_clb_frac_lut4_mux_0 frac_lut4_mux_0_ ( .in ( sram ) , - .sram ( { sky130_fd_sc_hd__buf_2_0_X[0] , sky130_fd_sc_hd__buf_2_1_X[0] , - sky130_fd_sc_hd__buf_2_2_X[0] , sky130_fd_sc_hd__buf_2_3_X[0] } ) , - .sram_inv ( { sky130_fd_sc_hd__inv_1_0_Y[0] , - sky130_fd_sc_hd__inv_1_1_Y[0] , sky130_fd_sc_hd__inv_1_2_Y[0] , - sky130_fd_sc_hd__inv_1_3_Y[0] } ) , - .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( - prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out , - frac_lut4_lut4_out , ccff_tail ) ; -input [0:0] prog_clk ; -input [0:3] frac_lut4_in ; -input [0:0] ccff_head ; -output [0:1] frac_lut4_lut3_out ; -output [0:0] frac_lut4_lut4_out ; -output [0:0] ccff_tail ; - -wire [0:15] frac_lut4_0__undriven_sram_inv ; -wire [0:0] frac_lut4_0_mode ; -wire [0:15] frac_lut4_0_sram ; - -grid_clb_frac_lut4_0 frac_lut4_0_ ( .in ( frac_lut4_in ) , - .sram ( frac_lut4_0_sram ) , - .sram_inv ( frac_lut4_0__undriven_sram_inv ) , - .mode ( frac_lut4_0_mode ) , - .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , - .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) ) ; -grid_clb_frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem_0 frac_lut4_sky130_fd_sc_hd__dfxtp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , - .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , - frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] , - frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , - frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , - frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , - frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( - prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p1 ) ; -input [0:0] prog_clk ; -input [0:3] frac_logic_in ; -input [0:0] ccff_head ; -output [0:1] frac_logic_out ; -output [0:0] ccff_tail ; -input p1 ; - -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; -wire [0:1] mux_frac_logic_out_0_undriven_sram_inv ; -wire [0:1] mux_tree_size2_0_sram ; - -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( - .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , - .ccff_head ( ccff_head ) , - .frac_lut4_lut3_out ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] , - frac_logic_out[1] } ) , - - .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , - .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ; -grid_clb_mux_tree_size2_24 mux_frac_logic_out_0 ( - .in ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] - } ) , - .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_frac_logic_out_0_undriven_sram_inv ) , - .out ( frac_logic_out[0] ) , .p1 ( p1 ) ) ; -grid_clb_mux_tree_size2_mem_24 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) ) ; -grid_clb_direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( frac_logic_out[1] ) ) ; -grid_clb_direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( frac_logic_in[0] ) ) ; -grid_clb_direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( frac_logic_in[1] ) ) ; -grid_clb_direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( frac_logic_in[2] ) ) ; -grid_clb_direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( frac_logic_in[3] ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( - prog_clk , Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , - fabric_clk , ccff_head , fabric_out , fabric_regout , fabric_sc_out , - ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p_abuf3 , p0 , p1 ) ; -input [0:0] prog_clk ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:3] fabric_in ; -input [0:0] fabric_regin ; -input [0:0] fabric_sc_in ; -input [0:0] fabric_clk ; -input [0:0] ccff_head ; -output [0:1] fabric_out ; -output [0:0] fabric_regout ; -output [0:0] fabric_sc_out ; -output [0:0] ccff_tail ; -output p_abuf0 ; -output p_abuf1 ; -output p_abuf2 ; -output p_abuf3 ; -input p0 ; -input p1 ; - -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; -wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; -wire [0:1] mux_fabric_out_0_undriven_sram_inv ; -wire [0:1] mux_fabric_out_1_undriven_sram_inv ; -wire [0:1] mux_ff_0_D_0_undriven_sram_inv ; -wire [0:1] mux_tree_size2_0_sram ; -wire [0:1] mux_tree_size2_1_sram ; -wire [0:0] mux_tree_size2_2_out ; -wire [0:1] mux_tree_size2_2_sram ; -wire [0:0] mux_tree_size2_mem_0_ccff_tail ; -wire [0:0] mux_tree_size2_mem_1_ccff_tail ; - -assign fabric_regout[0] = fabric_sc_out[0] ; - -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( - .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , - .ccff_head ( ccff_head ) , - .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , - .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .p1 ( p1 ) ) ; -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( - .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , - .ff_DI ( fabric_sc_in ) , - .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , - .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( - .Test_en ( Test_en ) , .clk ( clk ) , - .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , - .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , - .ff_Q ( fabric_sc_out ) , - .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; -grid_clb_mux_tree_size2_0 mux_fabric_out_0 ( - .in ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] - } ) , - .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_fabric_out_0_undriven_sram_inv ) , - .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , - .p1 ( p1 ) ) ; -grid_clb_mux_tree_size2_1 mux_fabric_out_1 ( - .in ( { fabric_sc_out[0] , - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] - } ) , - .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( mux_fabric_out_1_undriven_sram_inv ) , - .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf2 ) , .p_abuf1 ( p_abuf3 ) , - .p0 ( p0 ) ) ; -grid_clb_mux_tree_size2_2 mux_ff_0_D_0 ( - .in ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , - fabric_regin[0] } ) , - .sram ( mux_tree_size2_2_sram ) , - .sram_inv ( mux_ff_0_D_0_undriven_sram_inv ) , - .out ( mux_tree_size2_2_out ) , .p0 ( p0 ) ) ; -grid_clb_mux_tree_size2_mem_0 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_size2_0_sram ) ) ; -grid_clb_mux_tree_size2_mem_1 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_size2_1_sram ) ) ; -grid_clb_mux_tree_size2_mem_2 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , - .mem_out ( mux_tree_size2_2_sram ) ) ; -grid_clb_direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fabric_sc_out ) ) ; -grid_clb_direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fabric_sc_out ) ) ; -grid_clb_direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( fabric_in[0] ) ) ; -grid_clb_direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_6 } ) , - .out ( fabric_in[1] ) ) ; -grid_clb_direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_7 } ) , - .out ( fabric_in[2] ) ) ; -grid_clb_direct_interc direct_interc_5_ ( - .in ( { SYNOPSYS_UNCONNECTED_8 } ) , - .out ( fabric_in[3] ) ) ; -grid_clb_direct_interc direct_interc_6_ ( - .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( fabric_sc_in ) ) ; -grid_clb_direct_interc direct_interc_7_ ( - .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( fabric_clk ) ) ; -grid_clb_direct_interc direct_interc_8_ ( - .in ( { SYNOPSYS_UNCONNECTED_11 } ) , - - .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) ) ; -grid_clb_direct_interc direct_interc_9_ ( - .in ( { SYNOPSYS_UNCONNECTED_12 } ) , - - .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ) ; -grid_clb_direct_interc direct_interc_10_ ( - .in ( { SYNOPSYS_UNCONNECTED_13 } ) , - .out ( fabric_clk ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_default__fle_0 ( prog_clk , Test_en , - clk , fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , - fle_regout , fle_sc_out , ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , - p_abuf3 , p0 , p1 ) ; -input [0:0] prog_clk ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:3] fle_in ; -input [0:0] fle_regin ; -input [0:0] fle_sc_in ; -input [0:0] fle_clk ; -input [0:0] ccff_head ; -output [0:1] fle_out ; -output [0:0] fle_regout ; -output [0:0] fle_sc_out ; -output [0:0] ccff_tail ; -output p_abuf0 ; -output p_abuf1 ; -output p_abuf2 ; -output p_abuf3 ; -input p0 ; -input p1 ; - -grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( - .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , - .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , - .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , - .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , - .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , - .p_abuf2 ( p_abuf2 ) , .p_abuf3 ( p_abuf3 ) , .p0 ( p0 ) , .p1 ( p1 ) ) ; -grid_clb_direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( { p_abuf1 } ) ) ; -grid_clb_direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( { p_abuf3 } ) ) ; -grid_clb_direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fle_regout ) ) ; -grid_clb_direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fle_sc_out ) ) ; -grid_clb_direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( fle_in[0] ) ) ; -grid_clb_direct_interc direct_interc_5_ ( - .in ( { SYNOPSYS_UNCONNECTED_6 } ) , - .out ( fle_in[1] ) ) ; -grid_clb_direct_interc direct_interc_6_ ( - .in ( { SYNOPSYS_UNCONNECTED_7 } ) , - .out ( fle_in[2] ) ) ; -grid_clb_direct_interc direct_interc_7_ ( - .in ( { SYNOPSYS_UNCONNECTED_8 } ) , - .out ( fle_in[3] ) ) ; -grid_clb_direct_interc direct_interc_8_ ( - .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( fle_regin ) ) ; -grid_clb_direct_interc direct_interc_9_ ( - .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( fle_sc_in ) ) ; -grid_clb_direct_interc direct_interc_10_ ( - .in ( { SYNOPSYS_UNCONNECTED_11 } ) , - .out ( fle_clk ) ) ; -endmodule - - -module grid_clb_logical_tile_clb_mode_clb_ ( prog_clk , Test_en , clk , - clb_I0 , clb_I0i , clb_I1 , clb_I1i , clb_I2 , clb_I2i , clb_I3 , - clb_I3i , clb_I4 , clb_I4i , clb_I5 , clb_I5i , clb_I6 , clb_I6i , - clb_I7 , clb_I7i , clb_regin , clb_sc_in , clb_clk , ccff_head , clb_O , - clb_regout , clb_sc_out , ccff_tail , p_abuf0 , p_abuf3 , p_abuf5 , - p_abuf7 , p_abuf9 , p_abuf11 , p_abuf13 , p_abuf15 , p_abuf17 , p_abuf19 , - p_abuf21 , p_abuf23 , p_abuf25 , p_abuf27 , p_abuf29 , p_abuf31 , - p_abuf33 , p0 , p1 , p2 , p3 , p4 ) ; -input [0:0] prog_clk ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:2] clb_I0 ; -input [0:0] clb_I0i ; -input [0:2] clb_I1 ; -input [0:0] clb_I1i ; -input [0:2] clb_I2 ; -input [0:0] clb_I2i ; -input [0:2] clb_I3 ; -input [0:0] clb_I3i ; -input [0:2] clb_I4 ; -input [0:0] clb_I4i ; -input [0:2] clb_I5 ; -input [0:0] clb_I5i ; -input [0:2] clb_I6 ; -input [0:0] clb_I6i ; -input [0:2] clb_I7 ; -input [0:0] clb_I7i ; -input [0:0] clb_regin ; -input [0:0] clb_sc_in ; -input [0:0] clb_clk ; -input [0:0] ccff_head ; -output [0:15] clb_O ; -output [0:0] clb_regout ; -output [0:0] clb_sc_out ; -output [0:0] ccff_tail ; -output p_abuf0 ; -output p_abuf3 ; -output p_abuf5 ; -output p_abuf7 ; -output p_abuf9 ; -output p_abuf11 ; -output p_abuf13 ; -output p_abuf15 ; -output p_abuf17 ; -output p_abuf19 ; -output p_abuf21 ; -output p_abuf23 ; -output p_abuf25 ; -output p_abuf27 ; -output p_abuf29 ; -output p_abuf31 ; -output p_abuf33 ; -input p0 ; -input p1 ; -input p2 ; -input p3 ; -input p4 ; - -wire [0:0] logical_tile_clb_mode_default__fle_0_ccff_tail ; -wire [0:0] logical_tile_clb_mode_default__fle_0_fle_regout ; -wire [0:0] logical_tile_clb_mode_default__fle_0_fle_sc_out ; -wire [0:0] logical_tile_clb_mode_default__fle_1_ccff_tail ; -wire [0:0] logical_tile_clb_mode_default__fle_1_fle_regout ; -wire [0:0] logical_tile_clb_mode_default__fle_1_fle_sc_out ; -wire [0:0] logical_tile_clb_mode_default__fle_2_ccff_tail ; -wire [0:0] logical_tile_clb_mode_default__fle_2_fle_regout ; -wire [0:0] logical_tile_clb_mode_default__fle_2_fle_sc_out ; -wire [0:0] logical_tile_clb_mode_default__fle_3_ccff_tail ; -wire [0:0] logical_tile_clb_mode_default__fle_3_fle_regout ; -wire [0:0] logical_tile_clb_mode_default__fle_3_fle_sc_out ; -wire [0:0] logical_tile_clb_mode_default__fle_4_ccff_tail ; -wire [0:0] logical_tile_clb_mode_default__fle_4_fle_regout ; -wire [0:0] logical_tile_clb_mode_default__fle_4_fle_sc_out ; -wire [0:0] logical_tile_clb_mode_default__fle_5_ccff_tail ; -wire [0:0] logical_tile_clb_mode_default__fle_5_fle_regout ; -wire [0:0] logical_tile_clb_mode_default__fle_5_fle_sc_out ; -wire [0:0] logical_tile_clb_mode_default__fle_6_ccff_tail ; -wire [0:0] logical_tile_clb_mode_default__fle_6_fle_regout ; -wire [0:0] logical_tile_clb_mode_default__fle_6_fle_sc_out ; - -grid_clb_logical_tile_clb_mode_default__fle_0 logical_tile_clb_mode_default__fle_0 ( - .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fle_in ( { clb_I0[0] , clb_I0[1] , clb_I0[2] , clb_I0i[0] } ) , - .fle_regin ( clb_regin ) , .fle_sc_in ( clb_sc_in ) , - .fle_clk ( clb_clk ) , .ccff_head ( ccff_head ) , - .fle_out ( { clb_O[1] , clb_O[0] } ) , - .fle_regout ( logical_tile_clb_mode_default__fle_0_fle_regout ) , - .fle_sc_out ( logical_tile_clb_mode_default__fle_0_fle_sc_out ) , - .ccff_tail ( logical_tile_clb_mode_default__fle_0_ccff_tail ) , - .p_abuf0 ( p_abuf3 ) , .p_abuf1 ( p_abuf4 ) , .p_abuf2 ( p_abuf5 ) , - .p_abuf3 ( p_abuf6 ) , .p0 ( p0 ) , .p1 ( p2 ) ) ; -grid_clb_logical_tile_clb_mode_default__fle_1 logical_tile_clb_mode_default__fle_1 ( - .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fle_in ( { clb_I1[0] , clb_I1[1] , clb_I1[2] , clb_I1i[0] } ) , - .fle_regin ( logical_tile_clb_mode_default__fle_0_fle_regout ) , - .fle_sc_in ( logical_tile_clb_mode_default__fle_0_fle_sc_out ) , - .fle_clk ( clb_clk ) , - .ccff_head ( logical_tile_clb_mode_default__fle_0_ccff_tail ) , - .fle_out ( { clb_O[3] , clb_O[2] } ) , - .fle_regout ( logical_tile_clb_mode_default__fle_1_fle_regout ) , - .fle_sc_out ( logical_tile_clb_mode_default__fle_1_fle_sc_out ) , - .ccff_tail ( logical_tile_clb_mode_default__fle_1_ccff_tail ) , - .p_abuf0 ( p_abuf7 ) , .p_abuf1 ( p_abuf8 ) , .p_abuf2 ( p_abuf9 ) , - .p0 ( p0 ) , .p1 ( p2 ) ) ; -grid_clb_logical_tile_clb_mode_default__fle_2 logical_tile_clb_mode_default__fle_2 ( - .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fle_in ( { clb_I2[0] , clb_I2[1] , clb_I2[2] , clb_I2i[0] } ) , - .fle_regin ( logical_tile_clb_mode_default__fle_1_fle_regout ) , - .fle_sc_in ( logical_tile_clb_mode_default__fle_1_fle_sc_out ) , - .fle_clk ( clb_clk ) , - .ccff_head ( logical_tile_clb_mode_default__fle_1_ccff_tail ) , - .fle_out ( { clb_O[5] , clb_O[4] } ) , - .fle_regout ( logical_tile_clb_mode_default__fle_2_fle_regout ) , - .fle_sc_out ( logical_tile_clb_mode_default__fle_2_fle_sc_out ) , - .ccff_tail ( logical_tile_clb_mode_default__fle_2_ccff_tail ) , - .p_abuf0 ( p_abuf11 ) , .p_abuf1 ( p_abuf12 ) , .p_abuf2 ( p_abuf13 ) , - .p_abuf3 ( p_abuf14 ) , .p2 ( p3 ) ) ; -grid_clb_logical_tile_clb_mode_default__fle_3 logical_tile_clb_mode_default__fle_3 ( - .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fle_in ( { clb_I3[0] , clb_I3[1] , clb_I3[2] , clb_I3i[0] } ) , - .fle_regin ( logical_tile_clb_mode_default__fle_2_fle_regout ) , - .fle_sc_in ( logical_tile_clb_mode_default__fle_2_fle_sc_out ) , - .fle_clk ( clb_clk ) , - .ccff_head ( logical_tile_clb_mode_default__fle_2_ccff_tail ) , - .fle_out ( { clb_O[7] , clb_O[6] } ) , - .fle_regout ( logical_tile_clb_mode_default__fle_3_fle_regout ) , - .fle_sc_out ( logical_tile_clb_mode_default__fle_3_fle_sc_out ) , - .ccff_tail ( logical_tile_clb_mode_default__fle_3_ccff_tail ) , - .p_abuf0 ( p_abuf15 ) , .p_abuf2 ( p_abuf17 ) , .p_abuf3 ( p_abuf18 ) , - .p2 ( p3 ) ) ; -grid_clb_logical_tile_clb_mode_default__fle_4 logical_tile_clb_mode_default__fle_4 ( - .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fle_in ( { clb_I4[0] , clb_I4[1] , clb_I4[2] , clb_I4i[0] } ) , - .fle_regin ( logical_tile_clb_mode_default__fle_3_fle_regout ) , - .fle_sc_in ( logical_tile_clb_mode_default__fle_3_fle_sc_out ) , - .fle_clk ( clb_clk ) , - .ccff_head ( logical_tile_clb_mode_default__fle_3_ccff_tail ) , - .fle_out ( { clb_O[9] , clb_O[8] } ) , - .fle_regout ( logical_tile_clb_mode_default__fle_4_fle_regout ) , - .fle_sc_out ( logical_tile_clb_mode_default__fle_4_fle_sc_out ) , - .ccff_tail ( logical_tile_clb_mode_default__fle_4_ccff_tail ) , - .p_abuf0 ( p_abuf19 ) , .p_abuf2 ( p_abuf21 ) , .p_abuf3 ( p_abuf22 ) , - .p2 ( p3 ) , .p3 ( p4 ) ) ; -grid_clb_logical_tile_clb_mode_default__fle_5 logical_tile_clb_mode_default__fle_5 ( - .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fle_in ( { clb_I5[0] , clb_I5[1] , clb_I5[2] , clb_I5i[0] } ) , - .fle_regin ( logical_tile_clb_mode_default__fle_4_fle_regout ) , - .fle_sc_in ( logical_tile_clb_mode_default__fle_4_fle_sc_out ) , - .fle_clk ( clb_clk ) , - .ccff_head ( logical_tile_clb_mode_default__fle_4_ccff_tail ) , - .fle_out ( { clb_O[11] , clb_O[10] } ) , - .fle_regout ( logical_tile_clb_mode_default__fle_5_fle_regout ) , - .fle_sc_out ( logical_tile_clb_mode_default__fle_5_fle_sc_out ) , - .ccff_tail ( logical_tile_clb_mode_default__fle_5_ccff_tail ) , - .p_abuf0 ( p_abuf23 ) , .p_abuf1 ( p_abuf24 ) , .p_abuf2 ( p_abuf25 ) , - .p3 ( p4 ) ) ; -grid_clb_logical_tile_clb_mode_default__fle_6 logical_tile_clb_mode_default__fle_6 ( - .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fle_in ( { clb_I6[0] , clb_I6[1] , clb_I6[2] , clb_I6i[0] } ) , - .fle_regin ( logical_tile_clb_mode_default__fle_5_fle_regout ) , - .fle_sc_in ( logical_tile_clb_mode_default__fle_5_fle_sc_out ) , - .fle_clk ( clb_clk ) , - .ccff_head ( logical_tile_clb_mode_default__fle_5_ccff_tail ) , - .fle_out ( { clb_O[13] , clb_O[12] } ) , - .fle_regout ( logical_tile_clb_mode_default__fle_6_fle_regout ) , - .fle_sc_out ( logical_tile_clb_mode_default__fle_6_fle_sc_out ) , - .ccff_tail ( logical_tile_clb_mode_default__fle_6_ccff_tail ) , - .p_abuf0 ( p_abuf27 ) , .p_abuf1 ( p_abuf28 ) , .p_abuf2 ( p_abuf29 ) , - .p0 ( p1 ) , .p3 ( p4 ) ) ; -grid_clb_logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_7 ( - .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fle_in ( { clb_I7[0] , clb_I7[1] , clb_I7[2] , clb_I7i[0] } ) , - .fle_regin ( logical_tile_clb_mode_default__fle_6_fle_regout ) , - .fle_sc_in ( logical_tile_clb_mode_default__fle_6_fle_sc_out ) , - .fle_clk ( clb_clk ) , - .ccff_head ( logical_tile_clb_mode_default__fle_6_ccff_tail ) , - .fle_out ( { clb_O[15] , clb_O[14] } ) , - .fle_regout ( clb_regout ) , .fle_sc_out ( clb_sc_out ) , - .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , - .p_abuf2 ( p_abuf2 ) , .p_abuf3 ( p_abuf31 ) , .p_abuf5 ( p_abuf33 ) , - .p_abuf6 ( p_abuf34 ) , .p0 ( p1 ) ) ; -grid_clb_direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( { p_abuf6 } ) ) ; -grid_clb_direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( { p_abuf4 } ) ) ; -grid_clb_direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( { p_abuf8 } ) ) ; -grid_clb_direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( { p_abuf14 } ) ) ; -grid_clb_direct_interc direct_interc_5_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( { p_abuf12 } ) ) ; -grid_clb_direct_interc direct_interc_6_ ( - .in ( { SYNOPSYS_UNCONNECTED_6 } ) , - .out ( { p_abuf18 } ) ) ; -grid_clb_direct_interc direct_interc_8_ ( - .in ( { SYNOPSYS_UNCONNECTED_7 } ) , - .out ( { p_abuf22 } ) ) ; -grid_clb_direct_interc direct_interc_11_ ( - .in ( { SYNOPSYS_UNCONNECTED_8 } ) , - .out ( { p_abuf24 } ) ) ; -grid_clb_direct_interc direct_interc_13_ ( - .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( { p_abuf28 } ) ) ; -grid_clb_direct_interc direct_interc_14_ ( - .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( { p_abuf34 } ) ) ; -grid_clb_direct_interc direct_interc_16_ ( - .in ( { SYNOPSYS_UNCONNECTED_11 } ) , - .out ( { p_abuf1 } ) ) ; -grid_clb_direct_interc direct_interc_17_ ( - .in ( { SYNOPSYS_UNCONNECTED_12 } ) , - .out ( { p_abuf2 } ) ) ; -grid_clb_direct_interc direct_interc_18_ ( - .in ( { SYNOPSYS_UNCONNECTED_13 } ) , - .out ( clb_I0[0] ) ) ; -grid_clb_direct_interc direct_interc_19_ ( - .in ( { SYNOPSYS_UNCONNECTED_14 } ) , - .out ( clb_I0[1] ) ) ; -grid_clb_direct_interc direct_interc_20_ ( - .in ( { SYNOPSYS_UNCONNECTED_15 } ) , - .out ( clb_I0[2] ) ) ; -grid_clb_direct_interc direct_interc_21_ ( - .in ( { SYNOPSYS_UNCONNECTED_16 } ) , - .out ( clb_I0i ) ) ; -grid_clb_direct_interc direct_interc_22_ ( - .in ( { SYNOPSYS_UNCONNECTED_17 } ) , - .out ( clb_regin ) ) ; -grid_clb_direct_interc direct_interc_23_ ( - .in ( { SYNOPSYS_UNCONNECTED_18 } ) , - .out ( clb_sc_in ) ) ; -grid_clb_direct_interc direct_interc_24_ ( - .in ( { SYNOPSYS_UNCONNECTED_19 } ) , - .out ( clb_clk ) ) ; -grid_clb_direct_interc direct_interc_25_ ( - .in ( { SYNOPSYS_UNCONNECTED_20 } ) , - .out ( clb_I1[0] ) ) ; -grid_clb_direct_interc direct_interc_26_ ( - .in ( { SYNOPSYS_UNCONNECTED_21 } ) , - .out ( clb_I1[1] ) ) ; -grid_clb_direct_interc direct_interc_27_ ( - .in ( { SYNOPSYS_UNCONNECTED_22 } ) , - .out ( clb_I1[2] ) ) ; -grid_clb_direct_interc direct_interc_28_ ( - .in ( { SYNOPSYS_UNCONNECTED_23 } ) , - .out ( clb_I1i ) ) ; -grid_clb_direct_interc direct_interc_29_ ( - .in ( { SYNOPSYS_UNCONNECTED_24 } ) , - .out ( logical_tile_clb_mode_default__fle_0_fle_regout ) ) ; -grid_clb_direct_interc direct_interc_30_ ( - .in ( { SYNOPSYS_UNCONNECTED_25 } ) , - .out ( logical_tile_clb_mode_default__fle_0_fle_sc_out ) ) ; -grid_clb_direct_interc direct_interc_31_ ( - .in ( { SYNOPSYS_UNCONNECTED_26 } ) , - .out ( clb_clk ) ) ; -grid_clb_direct_interc direct_interc_32_ ( - .in ( { SYNOPSYS_UNCONNECTED_27 } ) , - .out ( clb_I2[0] ) ) ; -grid_clb_direct_interc direct_interc_33_ ( - .in ( { SYNOPSYS_UNCONNECTED_28 } ) , - .out ( clb_I2[1] ) ) ; -grid_clb_direct_interc direct_interc_34_ ( - .in ( { SYNOPSYS_UNCONNECTED_29 } ) , - .out ( clb_I2[2] ) ) ; -grid_clb_direct_interc direct_interc_35_ ( - .in ( { SYNOPSYS_UNCONNECTED_30 } ) , - .out ( clb_I2i ) ) ; -grid_clb_direct_interc direct_interc_36_ ( - .in ( { SYNOPSYS_UNCONNECTED_31 } ) , - .out ( logical_tile_clb_mode_default__fle_1_fle_regout ) ) ; -grid_clb_direct_interc direct_interc_37_ ( - .in ( { SYNOPSYS_UNCONNECTED_32 } ) , - .out ( logical_tile_clb_mode_default__fle_1_fle_sc_out ) ) ; -grid_clb_direct_interc direct_interc_38_ ( - .in ( { SYNOPSYS_UNCONNECTED_33 } ) , - .out ( clb_clk ) ) ; -grid_clb_direct_interc direct_interc_39_ ( - .in ( { SYNOPSYS_UNCONNECTED_34 } ) , - .out ( clb_I3[0] ) ) ; -grid_clb_direct_interc direct_interc_40_ ( - .in ( { SYNOPSYS_UNCONNECTED_35 } ) , - .out ( clb_I3[1] ) ) ; -grid_clb_direct_interc direct_interc_41_ ( - .in ( { SYNOPSYS_UNCONNECTED_36 } ) , - .out ( clb_I3[2] ) ) ; -grid_clb_direct_interc direct_interc_42_ ( - .in ( { SYNOPSYS_UNCONNECTED_37 } ) , - .out ( clb_I3i ) ) ; -grid_clb_direct_interc direct_interc_43_ ( - .in ( { SYNOPSYS_UNCONNECTED_38 } ) , - .out ( logical_tile_clb_mode_default__fle_2_fle_regout ) ) ; -grid_clb_direct_interc direct_interc_44_ ( - .in ( { SYNOPSYS_UNCONNECTED_39 } ) , - .out ( logical_tile_clb_mode_default__fle_2_fle_sc_out ) ) ; -grid_clb_direct_interc direct_interc_45_ ( - .in ( { SYNOPSYS_UNCONNECTED_40 } ) , - .out ( clb_clk ) ) ; -grid_clb_direct_interc direct_interc_46_ ( - .in ( { SYNOPSYS_UNCONNECTED_41 } ) , - .out ( clb_I4[0] ) ) ; -grid_clb_direct_interc direct_interc_47_ ( - .in ( { SYNOPSYS_UNCONNECTED_42 } ) , - .out ( clb_I4[1] ) ) ; -grid_clb_direct_interc direct_interc_48_ ( - .in ( { SYNOPSYS_UNCONNECTED_43 } ) , - .out ( clb_I4[2] ) ) ; -grid_clb_direct_interc direct_interc_49_ ( - .in ( { SYNOPSYS_UNCONNECTED_44 } ) , - .out ( clb_I4i ) ) ; -grid_clb_direct_interc direct_interc_50_ ( - .in ( { SYNOPSYS_UNCONNECTED_45 } ) , - .out ( logical_tile_clb_mode_default__fle_3_fle_regout ) ) ; -grid_clb_direct_interc direct_interc_51_ ( - .in ( { SYNOPSYS_UNCONNECTED_46 } ) , - .out ( logical_tile_clb_mode_default__fle_3_fle_sc_out ) ) ; -grid_clb_direct_interc direct_interc_52_ ( - .in ( { SYNOPSYS_UNCONNECTED_47 } ) , - .out ( clb_clk ) ) ; -grid_clb_direct_interc direct_interc_53_ ( - .in ( { SYNOPSYS_UNCONNECTED_48 } ) , - .out ( clb_I5[0] ) ) ; -grid_clb_direct_interc direct_interc_54_ ( - .in ( { SYNOPSYS_UNCONNECTED_49 } ) , - .out ( clb_I5[1] ) ) ; -grid_clb_direct_interc direct_interc_55_ ( - .in ( { SYNOPSYS_UNCONNECTED_50 } ) , - .out ( clb_I5[2] ) ) ; -grid_clb_direct_interc direct_interc_56_ ( - .in ( { SYNOPSYS_UNCONNECTED_51 } ) , - .out ( clb_I5i ) ) ; -grid_clb_direct_interc direct_interc_57_ ( - .in ( { SYNOPSYS_UNCONNECTED_52 } ) , - .out ( logical_tile_clb_mode_default__fle_4_fle_regout ) ) ; -grid_clb_direct_interc direct_interc_58_ ( - .in ( { SYNOPSYS_UNCONNECTED_53 } ) , - .out ( logical_tile_clb_mode_default__fle_4_fle_sc_out ) ) ; -grid_clb_direct_interc direct_interc_59_ ( - .in ( { SYNOPSYS_UNCONNECTED_54 } ) , - .out ( clb_clk ) ) ; -grid_clb_direct_interc direct_interc_60_ ( - .in ( { SYNOPSYS_UNCONNECTED_55 } ) , - .out ( clb_I6[0] ) ) ; -grid_clb_direct_interc direct_interc_61_ ( - .in ( { SYNOPSYS_UNCONNECTED_56 } ) , - .out ( clb_I6[1] ) ) ; -grid_clb_direct_interc direct_interc_62_ ( - .in ( { SYNOPSYS_UNCONNECTED_57 } ) , - .out ( clb_I6[2] ) ) ; -grid_clb_direct_interc direct_interc_63_ ( - .in ( { SYNOPSYS_UNCONNECTED_58 } ) , - .out ( clb_I6i ) ) ; -grid_clb_direct_interc direct_interc_64_ ( - .in ( { SYNOPSYS_UNCONNECTED_59 } ) , - .out ( logical_tile_clb_mode_default__fle_5_fle_regout ) ) ; -grid_clb_direct_interc direct_interc_65_ ( - .in ( { SYNOPSYS_UNCONNECTED_60 } ) , - .out ( logical_tile_clb_mode_default__fle_5_fle_sc_out ) ) ; -grid_clb_direct_interc direct_interc_66_ ( - .in ( { SYNOPSYS_UNCONNECTED_61 } ) , - .out ( clb_clk ) ) ; -grid_clb_direct_interc direct_interc_67_ ( - .in ( { SYNOPSYS_UNCONNECTED_62 } ) , - .out ( clb_I7[0] ) ) ; -grid_clb_direct_interc direct_interc_68_ ( - .in ( { SYNOPSYS_UNCONNECTED_63 } ) , - .out ( clb_I7[1] ) ) ; -grid_clb_direct_interc direct_interc_69_ ( - .in ( { SYNOPSYS_UNCONNECTED_64 } ) , - .out ( clb_I7[2] ) ) ; -grid_clb_direct_interc direct_interc_70_ ( - .in ( { SYNOPSYS_UNCONNECTED_65 } ) , - .out ( clb_I7i ) ) ; -grid_clb_direct_interc direct_interc_71_ ( - .in ( { SYNOPSYS_UNCONNECTED_66 } ) , - .out ( logical_tile_clb_mode_default__fle_6_fle_regout ) ) ; -grid_clb_direct_interc direct_interc_72_ ( - .in ( { SYNOPSYS_UNCONNECTED_67 } ) , - .out ( logical_tile_clb_mode_default__fle_6_fle_sc_out ) ) ; -grid_clb_direct_interc direct_interc_73_ ( - .in ( { SYNOPSYS_UNCONNECTED_68 } ) , - .out ( clb_clk ) ) ; -endmodule - - -module grid_clb ( prog_clk , Test_en , clk , top_width_0_height_0__pin_0_ , - top_width_0_height_0__pin_1_ , top_width_0_height_0__pin_2_ , - top_width_0_height_0__pin_3_ , top_width_0_height_0__pin_4_ , - top_width_0_height_0__pin_5_ , top_width_0_height_0__pin_6_ , - top_width_0_height_0__pin_7_ , top_width_0_height_0__pin_8_ , - top_width_0_height_0__pin_9_ , top_width_0_height_0__pin_10_ , - top_width_0_height_0__pin_11_ , top_width_0_height_0__pin_12_ , - top_width_0_height_0__pin_13_ , top_width_0_height_0__pin_14_ , - top_width_0_height_0__pin_15_ , top_width_0_height_0__pin_32_ , - top_width_0_height_0__pin_33_ , right_width_0_height_0__pin_16_ , - right_width_0_height_0__pin_17_ , right_width_0_height_0__pin_18_ , - right_width_0_height_0__pin_19_ , right_width_0_height_0__pin_20_ , - right_width_0_height_0__pin_21_ , right_width_0_height_0__pin_22_ , - right_width_0_height_0__pin_23_ , right_width_0_height_0__pin_24_ , - right_width_0_height_0__pin_25_ , right_width_0_height_0__pin_26_ , - right_width_0_height_0__pin_27_ , right_width_0_height_0__pin_28_ , - right_width_0_height_0__pin_29_ , right_width_0_height_0__pin_30_ , - right_width_0_height_0__pin_31_ , left_width_0_height_0__pin_52_ , - ccff_head , top_width_0_height_0__pin_34_upper , - top_width_0_height_0__pin_34_lower , top_width_0_height_0__pin_35_upper , - top_width_0_height_0__pin_35_lower , top_width_0_height_0__pin_36_upper , - top_width_0_height_0__pin_36_lower , top_width_0_height_0__pin_37_upper , - top_width_0_height_0__pin_37_lower , top_width_0_height_0__pin_38_upper , - top_width_0_height_0__pin_38_lower , top_width_0_height_0__pin_39_upper , - top_width_0_height_0__pin_39_lower , top_width_0_height_0__pin_40_upper , - top_width_0_height_0__pin_40_lower , top_width_0_height_0__pin_41_upper , - top_width_0_height_0__pin_41_lower , - right_width_0_height_0__pin_42_upper , - right_width_0_height_0__pin_42_lower , - right_width_0_height_0__pin_43_upper , - right_width_0_height_0__pin_43_lower , - right_width_0_height_0__pin_44_upper , - right_width_0_height_0__pin_44_lower , - right_width_0_height_0__pin_45_upper , - right_width_0_height_0__pin_45_lower , - right_width_0_height_0__pin_46_upper , - right_width_0_height_0__pin_46_lower , - right_width_0_height_0__pin_47_upper , - right_width_0_height_0__pin_47_lower , - right_width_0_height_0__pin_48_upper , - right_width_0_height_0__pin_48_lower , - right_width_0_height_0__pin_49_upper , - right_width_0_height_0__pin_49_lower , bottom_width_0_height_0__pin_50_ , - bottom_width_0_height_0__pin_51_ , ccff_tail , SC_IN_TOP , SC_IN_BOT , - SC_OUT_TOP , SC_OUT_BOT , prog_clk__FEEDTHRU_1 , prog_clk__FEEDTHRU_2 , - prog_clk__FEEDTHRU_3 , prog_clk__FEEDTHRU_4 , Test_en__FEEDTHRU_1 , - clk__FEEDTHRU_1 ) ; -input [0:0] prog_clk ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:0] top_width_0_height_0__pin_0_ ; -input [0:0] top_width_0_height_0__pin_1_ ; -input [0:0] top_width_0_height_0__pin_2_ ; -input [0:0] top_width_0_height_0__pin_3_ ; -input [0:0] top_width_0_height_0__pin_4_ ; -input [0:0] top_width_0_height_0__pin_5_ ; -input [0:0] top_width_0_height_0__pin_6_ ; -input [0:0] top_width_0_height_0__pin_7_ ; -input [0:0] top_width_0_height_0__pin_8_ ; -input [0:0] top_width_0_height_0__pin_9_ ; -input [0:0] top_width_0_height_0__pin_10_ ; -input [0:0] top_width_0_height_0__pin_11_ ; -input [0:0] top_width_0_height_0__pin_12_ ; -input [0:0] top_width_0_height_0__pin_13_ ; -input [0:0] top_width_0_height_0__pin_14_ ; -input [0:0] top_width_0_height_0__pin_15_ ; -input [0:0] top_width_0_height_0__pin_32_ ; -input [0:0] top_width_0_height_0__pin_33_ ; -input [0:0] right_width_0_height_0__pin_16_ ; -input [0:0] right_width_0_height_0__pin_17_ ; -input [0:0] right_width_0_height_0__pin_18_ ; -input [0:0] right_width_0_height_0__pin_19_ ; -input [0:0] right_width_0_height_0__pin_20_ ; -input [0:0] right_width_0_height_0__pin_21_ ; -input [0:0] right_width_0_height_0__pin_22_ ; -input [0:0] right_width_0_height_0__pin_23_ ; -input [0:0] right_width_0_height_0__pin_24_ ; -input [0:0] right_width_0_height_0__pin_25_ ; -input [0:0] right_width_0_height_0__pin_26_ ; -input [0:0] right_width_0_height_0__pin_27_ ; -input [0:0] right_width_0_height_0__pin_28_ ; -input [0:0] right_width_0_height_0__pin_29_ ; -input [0:0] right_width_0_height_0__pin_30_ ; -input [0:0] right_width_0_height_0__pin_31_ ; -input [0:0] left_width_0_height_0__pin_52_ ; -input [0:0] ccff_head ; -output [0:0] top_width_0_height_0__pin_34_upper ; -output [0:0] top_width_0_height_0__pin_34_lower ; -output [0:0] top_width_0_height_0__pin_35_upper ; -output [0:0] top_width_0_height_0__pin_35_lower ; -output [0:0] top_width_0_height_0__pin_36_upper ; -output [0:0] top_width_0_height_0__pin_36_lower ; -output [0:0] top_width_0_height_0__pin_37_upper ; -output [0:0] top_width_0_height_0__pin_37_lower ; -output [0:0] top_width_0_height_0__pin_38_upper ; -output [0:0] top_width_0_height_0__pin_38_lower ; -output [0:0] top_width_0_height_0__pin_39_upper ; -output [0:0] top_width_0_height_0__pin_39_lower ; -output [0:0] top_width_0_height_0__pin_40_upper ; -output [0:0] top_width_0_height_0__pin_40_lower ; -output [0:0] top_width_0_height_0__pin_41_upper ; -output [0:0] top_width_0_height_0__pin_41_lower ; -output [0:0] right_width_0_height_0__pin_42_upper ; -output [0:0] right_width_0_height_0__pin_42_lower ; -output [0:0] right_width_0_height_0__pin_43_upper ; -output [0:0] right_width_0_height_0__pin_43_lower ; -output [0:0] right_width_0_height_0__pin_44_upper ; -output [0:0] right_width_0_height_0__pin_44_lower ; -output [0:0] right_width_0_height_0__pin_45_upper ; -output [0:0] right_width_0_height_0__pin_45_lower ; -output [0:0] right_width_0_height_0__pin_46_upper ; -output [0:0] right_width_0_height_0__pin_46_lower ; -output [0:0] right_width_0_height_0__pin_47_upper ; -output [0:0] right_width_0_height_0__pin_47_lower ; -output [0:0] right_width_0_height_0__pin_48_upper ; -output [0:0] right_width_0_height_0__pin_48_lower ; -output [0:0] right_width_0_height_0__pin_49_upper ; -output [0:0] right_width_0_height_0__pin_49_lower ; -output [0:0] bottom_width_0_height_0__pin_50_ ; -output [0:0] bottom_width_0_height_0__pin_51_ ; -output [0:0] ccff_tail ; -input SC_IN_TOP ; -input SC_IN_BOT ; -output SC_OUT_TOP ; -output SC_OUT_BOT ; -output [0:0] prog_clk__FEEDTHRU_1 ; -output [0:0] prog_clk__FEEDTHRU_2 ; -output [0:0] prog_clk__FEEDTHRU_3 ; -output [0:0] prog_clk__FEEDTHRU_4 ; -output [0:0] Test_en__FEEDTHRU_1 ; -output [0:0] clk__FEEDTHRU_1 ; - -wire ropt_net_156 ; -wire ropt_net_153 ; -wire ropt_net_151 ; -wire ropt_net_150 ; -wire ropt_net_167 ; -wire ropt_net_154 ; -wire ropt_net_168 ; -wire ropt_net_152 ; -wire ropt_net_163 ; -wire ropt_net_162 ; - -assign SC_IN_TOP = SC_IN_BOT ; -assign prog_clk__FEEDTHRU_2[0] = prog_clk__FEEDTHRU_4[0] ; -assign prog_clk__FEEDTHRU_3[0] = prog_clk__FEEDTHRU_4[0] ; - -grid_clb_logical_tile_clb_mode_clb_ logical_tile_clb_mode_clb__0 ( - .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .clb_I0 ( { top_width_0_height_0__pin_0_[0] , - top_width_0_height_0__pin_1_[0] , top_width_0_height_0__pin_2_[0] } ) , - .clb_I0i ( top_width_0_height_0__pin_3_ ) , - .clb_I1 ( { top_width_0_height_0__pin_4_[0] , - top_width_0_height_0__pin_5_[0] , top_width_0_height_0__pin_6_[0] } ) , - .clb_I1i ( top_width_0_height_0__pin_7_ ) , - .clb_I2 ( { top_width_0_height_0__pin_8_[0] , - top_width_0_height_0__pin_9_[0] , top_width_0_height_0__pin_10_[0] } ) , - .clb_I2i ( top_width_0_height_0__pin_11_ ) , - .clb_I3 ( { top_width_0_height_0__pin_12_[0] , - top_width_0_height_0__pin_13_[0] , top_width_0_height_0__pin_14_[0] } ) , - .clb_I3i ( top_width_0_height_0__pin_15_ ) , - .clb_I4 ( { right_width_0_height_0__pin_16_[0] , - right_width_0_height_0__pin_17_[0] , - right_width_0_height_0__pin_18_[0] } ) , - .clb_I4i ( right_width_0_height_0__pin_19_ ) , - .clb_I5 ( { right_width_0_height_0__pin_20_[0] , - right_width_0_height_0__pin_21_[0] , - right_width_0_height_0__pin_22_[0] } ) , - .clb_I5i ( right_width_0_height_0__pin_23_ ) , - .clb_I6 ( { right_width_0_height_0__pin_24_[0] , - right_width_0_height_0__pin_25_[0] , - right_width_0_height_0__pin_26_[0] } ) , - .clb_I6i ( right_width_0_height_0__pin_27_ ) , - .clb_I7 ( { right_width_0_height_0__pin_28_[0] , - right_width_0_height_0__pin_29_[0] , - right_width_0_height_0__pin_30_[0] } ) , - .clb_I7i ( right_width_0_height_0__pin_31_ ) , - .clb_regin ( top_width_0_height_0__pin_32_ ) , - .clb_sc_in ( { SC_IN_BOT } ) , - .clb_clk ( left_width_0_height_0__pin_52_ ) , .ccff_head ( ccff_head ) , - .clb_O ( { aps_rename_138_ , aps_rename_139_ , - top_width_0_height_0__pin_36_lower[0] , aps_rename_142_ , - aps_rename_144_ , aps_rename_145_ , aps_rename_146_ , - top_width_0_height_0__pin_41_lower[0] , aps_rename_148_ , - aps_rename_150_ , aps_rename_151_ , aps_rename_153_ , - aps_rename_154_ , aps_rename_156_ , aps_rename_157_ , - aps_rename_158_ } ) , - .clb_regout ( { ropt_net_161 } ) , - .clb_sc_out ( { aps_rename_160_ } ) , - .ccff_tail ( ccff_tail ) , .p_abuf0 ( ropt_net_162 ) , - .p_abuf3 ( top_width_0_height_0__pin_35_upper[0] ) , - .p_abuf5 ( top_width_0_height_0__pin_34_upper[0] ) , - .p_abuf7 ( ropt_net_156 ) , - .p_abuf9 ( top_width_0_height_0__pin_36_upper[0] ) , - .p_abuf11 ( ropt_net_151 ) , .p_abuf13 ( ropt_net_153 ) , - .p_abuf15 ( top_width_0_height_0__pin_41_upper[0] ) , - .p_abuf17 ( top_width_0_height_0__pin_40_upper[0] ) , - .p_abuf19 ( ropt_net_167 ) , .p_abuf21 ( ropt_net_150 ) , - .p_abuf23 ( ropt_net_168 ) , .p_abuf25 ( ropt_net_154 ) , - .p_abuf27 ( ropt_net_152 ) , - .p_abuf29 ( right_width_0_height_0__pin_46_upper[0] ) , - .p_abuf31 ( right_width_0_height_0__pin_49_upper[0] ) , - .p_abuf33 ( ropt_net_163 ) , .p0 ( optlc_net_137 ) , - .p1 ( optlc_net_138 ) , .p2 ( optlc_net_139 ) , .p3 ( optlc_net_140 ) , - .p4 ( optlc_net_141 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( Test_en[0] ) , - .X ( ropt_net_166 ) ) ; -sky130_fd_sc_hd__buf_2 \clk[0]_bip538 ( .A ( clk[0] ) , - .X ( ctsbuf_net_1142 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_989 ( .A ( ropt_net_167 ) , - .X ( right_width_0_height_0__pin_43_upper[0] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_137 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_137 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__4 ( .A ( aps_rename_142_ ) , - .X ( aps_rename_143_ ) ) ; -sky130_fd_sc_hd__conb_1 optlc_139 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_138 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_141 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_139 ) ) ; -sky130_fd_sc_hd__clkbuf_1 \prog_clk[0]_bip539 ( .A ( prog_clk[0] ) , - .X ( ctsbuf_net_6147 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_143 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_140 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_990 ( .A ( ropt_net_168 ) , - .X ( right_width_0_height_0__pin_45_upper[0] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_145 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , - .HI ( optlc_net_141 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__11 ( .A ( aps_rename_151_ ) , - .X ( aps_rename_152_ ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_955 ( .A ( ropt_net_148 ) , - .X ( top_width_0_height_0__pin_38_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__13 ( .A ( aps_rename_154_ ) , - .X ( aps_rename_155_ ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_364903 ( .A ( ctsbuf_net_1142 ) , - .X ( clk__FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_956 ( .A ( ropt_net_149 ) , - .X ( top_width_0_height_0__pin_39_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__16 ( .A ( aps_rename_158_ ) , - .X ( aps_rename_159_ ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__17 ( .A ( aps_rename_160_ ) , - .X ( ropt_net_157 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_94 ( .A ( aps_rename_138_ ) , - .X ( BUF_net_94 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_95 ( .A ( aps_rename_139_ ) , - .X ( BUF_net_95 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_957 ( .A ( ropt_net_150 ) , - .X ( right_width_0_height_0__pin_42_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_97 ( .A ( aps_rename_143_ ) , - .X ( top_width_0_height_0__pin_37_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_98 ( .A ( aps_rename_144_ ) , - .X ( ropt_net_148 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_99 ( .A ( aps_rename_145_ ) , - .X ( ropt_net_149 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_100 ( .A ( aps_rename_146_ ) , - .X ( BUF_net_100 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_958 ( .A ( ropt_net_151 ) , - .X ( top_width_0_height_0__pin_39_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_959 ( .A ( ropt_net_152 ) , - .X ( right_width_0_height_0__pin_47_upper[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_103 ( .A ( aps_rename_150_ ) , - .X ( BUF_net_103 ) ) ; -sky130_fd_sc_hd__buf_8 cts_buf_389928 ( .A ( prog_clk__FEEDTHRU_4[0] ) , - .X ( prog_clk__FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__buf_12 cts_buf_393932 ( .A ( ctsbuf_net_6147 ) , - .X ( prog_clk__FEEDTHRU_4[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_960 ( .A ( ropt_net_153 ) , - .X ( top_width_0_height_0__pin_38_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_964 ( .A ( ropt_net_154 ) , - .X ( right_width_0_height_0__pin_44_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_994 ( .A ( ropt_net_169 ) , - .X ( right_width_0_height_0__pin_49_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_965 ( .A ( aps_rename_156_ ) , - .X ( right_width_0_height_0__pin_47_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_966 ( .A ( ropt_net_156 ) , - .X ( top_width_0_height_0__pin_37_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_968 ( .A ( ropt_net_157 ) , - .X ( ropt_net_172 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_116 ( .A ( aps_rename_152_ ) , - .X ( right_width_0_height_0__pin_44_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_998 ( .A ( ropt_net_170 ) , - .X ( right_width_0_height_0__pin_48_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_118 ( .A ( aps_rename_155_ ) , - .X ( right_width_0_height_0__pin_46_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_999 ( .A ( ropt_net_171 ) , - .X ( right_width_0_height_0__pin_48_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_120 ( .A ( aps_rename_157_ ) , - .X ( ropt_net_165 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_121 ( .A ( aps_rename_159_ ) , - .X ( ropt_net_164 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_126 ( .A ( BUF_net_94 ) , - .X ( top_width_0_height_0__pin_34_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_127 ( .A ( BUF_net_95 ) , - .X ( top_width_0_height_0__pin_35_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_128 ( .A ( BUF_net_100 ) , - .X ( ropt_net_174 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_969 ( .A ( aps_rename_153_ ) , - .X ( right_width_0_height_0__pin_45_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_132 ( .A ( aps_rename_148_ ) , - .X ( ropt_net_159 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_1004 ( .A ( ropt_net_172 ) , - .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_972 ( .A ( ropt_net_159 ) , - .X ( right_width_0_height_0__pin_42_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_974 ( .A ( BUF_net_103 ) , - .X ( right_width_0_height_0__pin_43_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_978 ( .A ( ropt_net_161 ) , - .X ( ropt_net_173 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_984 ( .A ( ropt_net_162 ) , - .X ( SC_OUT_TOP ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_985 ( .A ( ropt_net_163 ) , - .X ( ropt_net_170 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_986 ( .A ( ropt_net_164 ) , - .X ( ropt_net_169 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_987 ( .A ( ropt_net_165 ) , - .X ( ropt_net_171 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_988 ( .A ( ropt_net_166 ) , - .X ( Test_en__FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_1005 ( .A ( ropt_net_173 ) , - .X ( bottom_width_0_height_0__pin_50_[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_1007 ( .A ( ropt_net_174 ) , - .X ( top_width_0_height_0__pin_40_lower[0] ) ) ; -endmodule - - -module fpga_core ( prog_clk , Test_en , clk , gfpga_pad_EMBEDDED_IO_SOC_IN , - gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , - ccff_head , ccff_tail , sc_head , sc_tail ) ; -input [0:0] prog_clk ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:17] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:17] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:17] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -input sc_head ; -output sc_tail ; - -wire [0:0] cbx_1__0__0_bottom_grid_pin_0_ ; -wire [0:0] cbx_1__0__0_bottom_grid_pin_10_ ; -wire [0:0] cbx_1__0__0_bottom_grid_pin_2_ ; -wire [0:0] cbx_1__0__0_bottom_grid_pin_4_ ; -wire [0:0] cbx_1__0__0_bottom_grid_pin_6_ ; -wire [0:0] cbx_1__0__0_bottom_grid_pin_8_ ; -wire [0:19] cbx_1__0__0_chanx_left_out ; -wire [0:19] cbx_1__0__0_chanx_right_out ; -wire [0:0] cbx_1__0__1_bottom_grid_pin_0_ ; -wire [0:0] cbx_1__0__1_bottom_grid_pin_10_ ; -wire [0:0] cbx_1__0__1_bottom_grid_pin_2_ ; -wire [0:0] cbx_1__0__1_bottom_grid_pin_4_ ; -wire [0:0] cbx_1__0__1_bottom_grid_pin_6_ ; -wire [0:0] cbx_1__0__1_bottom_grid_pin_8_ ; -wire [0:19] cbx_1__0__1_chanx_left_out ; -wire [0:19] cbx_1__0__1_chanx_right_out ; -wire [0:0] cbx_1__1__0_bottom_grid_pin_0_ ; -wire [0:0] cbx_1__1__0_bottom_grid_pin_10_ ; -wire [0:0] cbx_1__1__0_bottom_grid_pin_11_ ; -wire [0:0] cbx_1__1__0_bottom_grid_pin_12_ ; -wire [0:0] cbx_1__1__0_bottom_grid_pin_13_ ; -wire [0:0] cbx_1__1__0_bottom_grid_pin_14_ ; -wire [0:0] cbx_1__1__0_bottom_grid_pin_15_ ; -wire [0:0] cbx_1__1__0_bottom_grid_pin_1_ ; -wire [0:0] cbx_1__1__0_bottom_grid_pin_2_ ; -wire [0:0] cbx_1__1__0_bottom_grid_pin_3_ ; -wire [0:0] cbx_1__1__0_bottom_grid_pin_4_ ; -wire [0:0] cbx_1__1__0_bottom_grid_pin_5_ ; -wire [0:0] cbx_1__1__0_bottom_grid_pin_6_ ; -wire [0:0] cbx_1__1__0_bottom_grid_pin_7_ ; -wire [0:0] cbx_1__1__0_bottom_grid_pin_8_ ; -wire [0:0] cbx_1__1__0_bottom_grid_pin_9_ ; -wire [0:0] cbx_1__1__0_ccff_tail ; -wire [0:19] cbx_1__1__0_chanx_left_out ; -wire [0:19] cbx_1__1__0_chanx_right_out ; -wire [0:0] cbx_1__1__1_bottom_grid_pin_0_ ; -wire [0:0] cbx_1__1__1_bottom_grid_pin_10_ ; -wire [0:0] cbx_1__1__1_bottom_grid_pin_11_ ; -wire [0:0] cbx_1__1__1_bottom_grid_pin_12_ ; -wire [0:0] cbx_1__1__1_bottom_grid_pin_13_ ; -wire [0:0] cbx_1__1__1_bottom_grid_pin_14_ ; -wire [0:0] cbx_1__1__1_bottom_grid_pin_15_ ; -wire [0:0] cbx_1__1__1_bottom_grid_pin_1_ ; -wire [0:0] cbx_1__1__1_bottom_grid_pin_2_ ; -wire [0:0] cbx_1__1__1_bottom_grid_pin_3_ ; -wire [0:0] cbx_1__1__1_bottom_grid_pin_4_ ; -wire [0:0] cbx_1__1__1_bottom_grid_pin_5_ ; -wire [0:0] cbx_1__1__1_bottom_grid_pin_6_ ; -wire [0:0] cbx_1__1__1_bottom_grid_pin_7_ ; -wire [0:0] cbx_1__1__1_bottom_grid_pin_8_ ; -wire [0:0] cbx_1__1__1_bottom_grid_pin_9_ ; -wire [0:0] cbx_1__1__1_ccff_tail ; -wire [0:19] cbx_1__1__1_chanx_left_out ; -wire [0:19] cbx_1__1__1_chanx_right_out ; -wire [0:0] cbx_1__2__0_bottom_grid_pin_0_ ; -wire [0:0] cbx_1__2__0_bottom_grid_pin_10_ ; -wire [0:0] cbx_1__2__0_bottom_grid_pin_11_ ; -wire [0:0] cbx_1__2__0_bottom_grid_pin_12_ ; -wire [0:0] cbx_1__2__0_bottom_grid_pin_13_ ; -wire [0:0] cbx_1__2__0_bottom_grid_pin_14_ ; -wire [0:0] cbx_1__2__0_bottom_grid_pin_15_ ; -wire [0:0] cbx_1__2__0_bottom_grid_pin_1_ ; -wire [0:0] cbx_1__2__0_bottom_grid_pin_2_ ; -wire [0:0] cbx_1__2__0_bottom_grid_pin_3_ ; -wire [0:0] cbx_1__2__0_bottom_grid_pin_4_ ; -wire [0:0] cbx_1__2__0_bottom_grid_pin_5_ ; -wire [0:0] cbx_1__2__0_bottom_grid_pin_6_ ; -wire [0:0] cbx_1__2__0_bottom_grid_pin_7_ ; -wire [0:0] cbx_1__2__0_bottom_grid_pin_8_ ; -wire [0:0] cbx_1__2__0_bottom_grid_pin_9_ ; -wire [0:19] cbx_1__2__0_chanx_left_out ; -wire [0:19] cbx_1__2__0_chanx_right_out ; -wire [0:0] cbx_1__2__0_top_grid_pin_0_ ; -wire [0:0] cbx_1__2__1_bottom_grid_pin_0_ ; -wire [0:0] cbx_1__2__1_bottom_grid_pin_10_ ; -wire [0:0] cbx_1__2__1_bottom_grid_pin_11_ ; -wire [0:0] cbx_1__2__1_bottom_grid_pin_12_ ; -wire [0:0] cbx_1__2__1_bottom_grid_pin_13_ ; -wire [0:0] cbx_1__2__1_bottom_grid_pin_14_ ; -wire [0:0] cbx_1__2__1_bottom_grid_pin_15_ ; -wire [0:0] cbx_1__2__1_bottom_grid_pin_1_ ; -wire [0:0] cbx_1__2__1_bottom_grid_pin_2_ ; -wire [0:0] cbx_1__2__1_bottom_grid_pin_3_ ; -wire [0:0] cbx_1__2__1_bottom_grid_pin_4_ ; -wire [0:0] cbx_1__2__1_bottom_grid_pin_5_ ; -wire [0:0] cbx_1__2__1_bottom_grid_pin_6_ ; -wire [0:0] cbx_1__2__1_bottom_grid_pin_7_ ; -wire [0:0] cbx_1__2__1_bottom_grid_pin_8_ ; -wire [0:0] cbx_1__2__1_bottom_grid_pin_9_ ; -wire [0:19] cbx_1__2__1_chanx_left_out ; -wire [0:19] cbx_1__2__1_chanx_right_out ; -wire [0:0] cbx_1__2__1_top_grid_pin_0_ ; -wire [0:19] cby_0__1__0_chany_bottom_out ; -wire [0:19] cby_0__1__0_chany_top_out ; -wire [0:0] cby_0__1__0_left_grid_pin_0_ ; -wire [0:19] cby_0__1__1_chany_bottom_out ; -wire [0:19] cby_0__1__1_chany_top_out ; -wire [0:0] cby_0__1__1_left_grid_pin_0_ ; -wire [0:0] cby_1__1__0_ccff_tail ; -wire [0:19] cby_1__1__0_chany_bottom_out ; -wire [0:19] cby_1__1__0_chany_top_out ; -wire [0:0] cby_1__1__0_left_grid_pin_16_ ; -wire [0:0] cby_1__1__0_left_grid_pin_17_ ; -wire [0:0] cby_1__1__0_left_grid_pin_18_ ; -wire [0:0] cby_1__1__0_left_grid_pin_19_ ; -wire [0:0] cby_1__1__0_left_grid_pin_20_ ; -wire [0:0] cby_1__1__0_left_grid_pin_21_ ; -wire [0:0] cby_1__1__0_left_grid_pin_22_ ; -wire [0:0] cby_1__1__0_left_grid_pin_23_ ; -wire [0:0] cby_1__1__0_left_grid_pin_24_ ; -wire [0:0] cby_1__1__0_left_grid_pin_25_ ; -wire [0:0] cby_1__1__0_left_grid_pin_26_ ; -wire [0:0] cby_1__1__0_left_grid_pin_27_ ; -wire [0:0] cby_1__1__0_left_grid_pin_28_ ; -wire [0:0] cby_1__1__0_left_grid_pin_29_ ; -wire [0:0] cby_1__1__0_left_grid_pin_30_ ; -wire [0:0] cby_1__1__0_left_grid_pin_31_ ; -wire [0:0] cby_1__1__1_ccff_tail ; -wire [0:19] cby_1__1__1_chany_bottom_out ; -wire [0:19] cby_1__1__1_chany_top_out ; -wire [0:0] cby_1__1__1_left_grid_pin_16_ ; -wire [0:0] cby_1__1__1_left_grid_pin_17_ ; -wire [0:0] cby_1__1__1_left_grid_pin_18_ ; -wire [0:0] cby_1__1__1_left_grid_pin_19_ ; -wire [0:0] cby_1__1__1_left_grid_pin_20_ ; -wire [0:0] cby_1__1__1_left_grid_pin_21_ ; -wire [0:0] cby_1__1__1_left_grid_pin_22_ ; -wire [0:0] cby_1__1__1_left_grid_pin_23_ ; -wire [0:0] cby_1__1__1_left_grid_pin_24_ ; -wire [0:0] cby_1__1__1_left_grid_pin_25_ ; -wire [0:0] cby_1__1__1_left_grid_pin_26_ ; -wire [0:0] cby_1__1__1_left_grid_pin_27_ ; -wire [0:0] cby_1__1__1_left_grid_pin_28_ ; -wire [0:0] cby_1__1__1_left_grid_pin_29_ ; -wire [0:0] cby_1__1__1_left_grid_pin_30_ ; -wire [0:0] cby_1__1__1_left_grid_pin_31_ ; -wire [0:19] cby_2__1__0_chany_bottom_out ; -wire [0:19] cby_2__1__0_chany_top_out ; -wire [0:0] cby_2__1__0_left_grid_pin_16_ ; -wire [0:0] cby_2__1__0_left_grid_pin_17_ ; -wire [0:0] cby_2__1__0_left_grid_pin_18_ ; -wire [0:0] cby_2__1__0_left_grid_pin_19_ ; -wire [0:0] cby_2__1__0_left_grid_pin_20_ ; -wire [0:0] cby_2__1__0_left_grid_pin_21_ ; -wire [0:0] cby_2__1__0_left_grid_pin_22_ ; -wire [0:0] cby_2__1__0_left_grid_pin_23_ ; -wire [0:0] cby_2__1__0_left_grid_pin_24_ ; -wire [0:0] cby_2__1__0_left_grid_pin_25_ ; -wire [0:0] cby_2__1__0_left_grid_pin_26_ ; -wire [0:0] cby_2__1__0_left_grid_pin_27_ ; -wire [0:0] cby_2__1__0_left_grid_pin_28_ ; -wire [0:0] cby_2__1__0_left_grid_pin_29_ ; -wire [0:0] cby_2__1__0_left_grid_pin_30_ ; -wire [0:0] cby_2__1__0_left_grid_pin_31_ ; -wire [0:0] cby_2__1__0_right_grid_pin_0_ ; -wire [0:19] cby_2__1__1_chany_bottom_out ; -wire [0:19] cby_2__1__1_chany_top_out ; -wire [0:0] cby_2__1__1_left_grid_pin_16_ ; -wire [0:0] cby_2__1__1_left_grid_pin_17_ ; -wire [0:0] cby_2__1__1_left_grid_pin_18_ ; -wire [0:0] cby_2__1__1_left_grid_pin_19_ ; -wire [0:0] cby_2__1__1_left_grid_pin_20_ ; -wire [0:0] cby_2__1__1_left_grid_pin_21_ ; -wire [0:0] cby_2__1__1_left_grid_pin_22_ ; -wire [0:0] cby_2__1__1_left_grid_pin_23_ ; -wire [0:0] cby_2__1__1_left_grid_pin_24_ ; -wire [0:0] cby_2__1__1_left_grid_pin_25_ ; -wire [0:0] cby_2__1__1_left_grid_pin_26_ ; -wire [0:0] cby_2__1__1_left_grid_pin_27_ ; -wire [0:0] cby_2__1__1_left_grid_pin_28_ ; -wire [0:0] cby_2__1__1_left_grid_pin_29_ ; -wire [0:0] cby_2__1__1_left_grid_pin_30_ ; -wire [0:0] cby_2__1__1_left_grid_pin_31_ ; -wire [0:0] cby_2__1__1_right_grid_pin_0_ ; -wire [0:0] direct_interc_0_out ; -wire [0:0] direct_interc_1_out ; -wire [0:0] direct_interc_2_out ; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_50_ ; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_51_ ; -wire [0:0] grid_clb_0_ccff_tail ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_42_lower ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_42_upper ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_43_lower ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_43_upper ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_44_lower ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_44_upper ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_45_lower ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_45_upper ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_46_lower ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_46_upper ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_47_lower ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_47_upper ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_48_lower ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_48_upper ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_49_lower ; -wire [0:0] grid_clb_0_right_width_0_height_0__pin_49_upper ; -wire [0:0] grid_clb_0_top_width_0_height_0__pin_34_lower ; -wire [0:0] grid_clb_0_top_width_0_height_0__pin_34_upper ; -wire [0:0] grid_clb_0_top_width_0_height_0__pin_35_lower ; -wire [0:0] grid_clb_0_top_width_0_height_0__pin_35_upper ; -wire [0:0] grid_clb_0_top_width_0_height_0__pin_36_lower ; -wire [0:0] grid_clb_0_top_width_0_height_0__pin_36_upper ; -wire [0:0] grid_clb_0_top_width_0_height_0__pin_37_lower ; -wire [0:0] grid_clb_0_top_width_0_height_0__pin_37_upper ; -wire [0:0] grid_clb_0_top_width_0_height_0__pin_38_lower ; -wire [0:0] grid_clb_0_top_width_0_height_0__pin_38_upper ; -wire [0:0] grid_clb_0_top_width_0_height_0__pin_39_lower ; -wire [0:0] grid_clb_0_top_width_0_height_0__pin_39_upper ; -wire [0:0] grid_clb_0_top_width_0_height_0__pin_40_lower ; -wire [0:0] grid_clb_0_top_width_0_height_0__pin_40_upper ; -wire [0:0] grid_clb_0_top_width_0_height_0__pin_41_lower ; -wire [0:0] grid_clb_0_top_width_0_height_0__pin_41_upper ; -wire [0:0] grid_clb_1__1__undriven_left_width_0_height_0__pin_52_ ; -wire [0:0] grid_clb_1__2__undriven_left_width_0_height_0__pin_52_ ; -wire [0:0] grid_clb_1__2__undriven_top_width_0_height_0__pin_32_ ; -wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_50_ ; -wire [0:0] grid_clb_1_ccff_tail ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_42_lower ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_42_upper ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_43_lower ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_43_upper ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_44_lower ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_44_upper ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_45_lower ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_45_upper ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_46_lower ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_46_upper ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_47_lower ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_47_upper ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_48_lower ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_48_upper ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_49_lower ; -wire [0:0] grid_clb_1_right_width_0_height_0__pin_49_upper ; -wire [0:0] grid_clb_1_top_width_0_height_0__pin_34_lower ; -wire [0:0] grid_clb_1_top_width_0_height_0__pin_34_upper ; -wire [0:0] grid_clb_1_top_width_0_height_0__pin_35_lower ; -wire [0:0] grid_clb_1_top_width_0_height_0__pin_35_upper ; -wire [0:0] grid_clb_1_top_width_0_height_0__pin_36_lower ; -wire [0:0] grid_clb_1_top_width_0_height_0__pin_36_upper ; -wire [0:0] grid_clb_1_top_width_0_height_0__pin_37_lower ; -wire [0:0] grid_clb_1_top_width_0_height_0__pin_37_upper ; -wire [0:0] grid_clb_1_top_width_0_height_0__pin_38_lower ; -wire [0:0] grid_clb_1_top_width_0_height_0__pin_38_upper ; -wire [0:0] grid_clb_1_top_width_0_height_0__pin_39_lower ; -wire [0:0] grid_clb_1_top_width_0_height_0__pin_39_upper ; -wire [0:0] grid_clb_1_top_width_0_height_0__pin_40_lower ; -wire [0:0] grid_clb_1_top_width_0_height_0__pin_40_upper ; -wire [0:0] grid_clb_1_top_width_0_height_0__pin_41_lower ; -wire [0:0] grid_clb_1_top_width_0_height_0__pin_41_upper ; -wire [0:0] grid_clb_2__1__undriven_bottom_width_0_height_0__pin_50_ ; -wire [0:0] grid_clb_2__1__undriven_left_width_0_height_0__pin_52_ ; -wire [0:0] grid_clb_2__2__undriven_left_width_0_height_0__pin_52_ ; -wire [0:0] grid_clb_2_ccff_tail ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_42_lower ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_42_upper ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_43_lower ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_43_upper ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_44_lower ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_44_upper ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_45_lower ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_45_upper ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_46_lower ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_46_upper ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_47_lower ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_47_upper ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_48_lower ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_48_upper ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_49_lower ; -wire [0:0] grid_clb_2_right_width_0_height_0__pin_49_upper ; -wire [0:0] grid_clb_2_top_width_0_height_0__pin_34_lower ; -wire [0:0] grid_clb_2_top_width_0_height_0__pin_34_upper ; -wire [0:0] grid_clb_2_top_width_0_height_0__pin_35_lower ; -wire [0:0] grid_clb_2_top_width_0_height_0__pin_35_upper ; -wire [0:0] grid_clb_2_top_width_0_height_0__pin_36_lower ; -wire [0:0] grid_clb_2_top_width_0_height_0__pin_36_upper ; -wire [0:0] grid_clb_2_top_width_0_height_0__pin_37_lower ; -wire [0:0] grid_clb_2_top_width_0_height_0__pin_37_upper ; -wire [0:0] grid_clb_2_top_width_0_height_0__pin_38_lower ; -wire [0:0] grid_clb_2_top_width_0_height_0__pin_38_upper ; -wire [0:0] grid_clb_2_top_width_0_height_0__pin_39_lower ; -wire [0:0] grid_clb_2_top_width_0_height_0__pin_39_upper ; -wire [0:0] grid_clb_2_top_width_0_height_0__pin_40_lower ; -wire [0:0] grid_clb_2_top_width_0_height_0__pin_40_upper ; -wire [0:0] grid_clb_2_top_width_0_height_0__pin_41_lower ; -wire [0:0] grid_clb_2_top_width_0_height_0__pin_41_upper ; -wire [0:0] grid_clb_3_bottom_width_0_height_0__pin_50_ ; -wire [0:0] grid_clb_3_ccff_tail ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_42_lower ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_42_upper ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_43_lower ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_43_upper ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_44_lower ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_44_upper ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_45_lower ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_45_upper ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_46_lower ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_46_upper ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_47_lower ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_47_upper ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_48_lower ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_48_upper ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_49_lower ; -wire [0:0] grid_clb_3_right_width_0_height_0__pin_49_upper ; -wire [0:0] grid_clb_3_top_width_0_height_0__pin_34_lower ; -wire [0:0] grid_clb_3_top_width_0_height_0__pin_34_upper ; -wire [0:0] grid_clb_3_top_width_0_height_0__pin_35_lower ; -wire [0:0] grid_clb_3_top_width_0_height_0__pin_35_upper ; -wire [0:0] grid_clb_3_top_width_0_height_0__pin_36_lower ; -wire [0:0] grid_clb_3_top_width_0_height_0__pin_36_upper ; -wire [0:0] grid_clb_3_top_width_0_height_0__pin_37_lower ; -wire [0:0] grid_clb_3_top_width_0_height_0__pin_37_upper ; -wire [0:0] grid_clb_3_top_width_0_height_0__pin_38_lower ; -wire [0:0] grid_clb_3_top_width_0_height_0__pin_38_upper ; -wire [0:0] grid_clb_3_top_width_0_height_0__pin_39_lower ; -wire [0:0] grid_clb_3_top_width_0_height_0__pin_39_upper ; -wire [0:0] grid_clb_3_top_width_0_height_0__pin_40_lower ; -wire [0:0] grid_clb_3_top_width_0_height_0__pin_40_upper ; -wire [0:0] grid_clb_3_top_width_0_height_0__pin_41_lower ; -wire [0:0] grid_clb_3_top_width_0_height_0__pin_41_upper ; -wire [0:0] grid_io_bottom_0_ccff_tail ; -wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_11_lower ; -wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_11_upper ; -wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_1_lower ; -wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_1_upper ; -wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_3_lower ; -wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_3_upper ; -wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_5_lower ; -wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_5_upper ; -wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_7_lower ; -wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_7_upper ; -wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_9_lower ; -wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_9_upper ; -wire [0:0] grid_io_bottom_1_ccff_tail ; -wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_11_lower ; -wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_11_upper ; -wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_1_lower ; -wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_1_upper ; -wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_3_lower ; -wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_3_upper ; -wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_5_lower ; -wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_5_upper ; -wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_7_lower ; -wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_7_upper ; -wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_9_lower ; -wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_9_upper ; -wire [0:0] grid_io_left_0_ccff_tail ; -wire [0:0] grid_io_left_0_right_width_0_height_0__pin_1_lower ; -wire [0:0] grid_io_left_0_right_width_0_height_0__pin_1_upper ; -wire [0:0] grid_io_left_1_ccff_tail ; -wire [0:0] grid_io_left_1_right_width_0_height_0__pin_1_lower ; -wire [0:0] grid_io_left_1_right_width_0_height_0__pin_1_upper ; -wire [0:0] grid_io_right_0_ccff_tail ; -wire [0:0] grid_io_right_0_left_width_0_height_0__pin_1_lower ; -wire [0:0] grid_io_right_0_left_width_0_height_0__pin_1_upper ; -wire [0:0] grid_io_right_1_ccff_tail ; -wire [0:0] grid_io_right_1_left_width_0_height_0__pin_1_lower ; -wire [0:0] grid_io_right_1_left_width_0_height_0__pin_1_upper ; -wire [0:0] grid_io_top_0_bottom_width_0_height_0__pin_1_lower ; -wire [0:0] grid_io_top_0_bottom_width_0_height_0__pin_1_upper ; -wire [0:0] grid_io_top_0_ccff_tail ; -wire [0:0] grid_io_top_1_bottom_width_0_height_0__pin_1_lower ; -wire [0:0] grid_io_top_1_bottom_width_0_height_0__pin_1_upper ; -wire [0:0] grid_io_top_1_ccff_tail ; -wire [0:19] sb_0__0__0_chanx_right_out ; -wire [0:19] sb_0__0__0_chany_top_out ; -wire [0:0] sb_0__1__0_ccff_tail ; -wire [0:19] sb_0__1__0_chanx_right_out ; -wire [0:19] sb_0__1__0_chany_bottom_out ; -wire [0:19] sb_0__1__0_chany_top_out ; -wire [0:0] sb_0__2__0_ccff_tail ; -wire [0:19] sb_0__2__0_chanx_right_out ; -wire [0:19] sb_0__2__0_chany_bottom_out ; -wire [0:0] sb_1__0__0_ccff_tail ; -wire [0:19] sb_1__0__0_chanx_left_out ; -wire [0:19] sb_1__0__0_chanx_right_out ; -wire [0:19] sb_1__0__0_chany_top_out ; -wire [0:0] sb_1__1__0_ccff_tail ; -wire [0:19] sb_1__1__0_chanx_left_out ; -wire [0:19] sb_1__1__0_chanx_right_out ; -wire [0:19] sb_1__1__0_chany_bottom_out ; -wire [0:19] sb_1__1__0_chany_top_out ; -wire [0:0] sb_1__2__0_ccff_tail ; -wire [0:19] sb_1__2__0_chanx_left_out ; -wire [0:19] sb_1__2__0_chanx_right_out ; -wire [0:19] sb_1__2__0_chany_bottom_out ; -wire [0:0] sb_2__0__0_ccff_tail ; -wire [0:19] sb_2__0__0_chanx_left_out ; -wire [0:19] sb_2__0__0_chany_top_out ; -wire [0:0] sb_2__1__0_ccff_tail ; -wire [0:19] sb_2__1__0_chanx_left_out ; -wire [0:19] sb_2__1__0_chany_bottom_out ; -wire [0:19] sb_2__1__0_chany_top_out ; -wire [0:0] sb_2__2__0_ccff_tail ; -wire [0:19] sb_2__2__0_chanx_left_out ; -wire [0:19] sb_2__2__0_chany_bottom_out ; -wire [0:0] prog_clk__FEEDTHRU_1 ; -wire [0:0] prog_clk__FEEDTHRU_2 ; -wire [0:0] prog_clk__FEEDTHRU_3 ; -wire [0:0] prog_clk__FEEDTHRU_4 ; -wire [0:0] prog_clk__FEEDTHRU_5 ; -wire [0:0] prog_clk__FEEDTHRU_6 ; -wire [0:0] prog_clk__FEEDTHRU_7 ; -wire [0:0] prog_clk__FEEDTHRU_8 ; -wire [0:0] prog_clk__FEEDTHRU_9 ; -wire [0:0] prog_clk__FEEDTHRU_10 ; -wire [0:0] prog_clk__FEEDTHRU_11 ; -wire [0:0] prog_clk__FEEDTHRU_12 ; -wire [0:0] prog_clk__FEEDTHRU_13 ; -wire [0:0] prog_clk__FEEDTHRU_14 ; -wire [0:0] prog_clk__FEEDTHRU_15 ; -wire [0:0] prog_clk__FEEDTHRU_16 ; -wire [0:0] prog_clk__FEEDTHRU_17 ; -wire [0:0] prog_clk__FEEDTHRU_18 ; -wire [0:0] prog_clk__FEEDTHRU_19 ; -wire [0:0] Test_en__FEEDTHRU_1 ; -wire [0:0] Test_en__FEEDTHRU_2 ; -wire [0:0] Test_en__FEEDTHRU_3 ; -wire [0:0] Test_en__FEEDTHRU_4 ; -wire [0:0] Test_en__FEEDTHRU_5 ; -wire [0:0] Test_en__FEEDTHRU_6 ; -wire [0:0] clk__FEEDTHRU_1 ; -wire [0:0] clk__FEEDTHRU_2 ; -wire [0:0] clk__FEEDTHRU_3 ; -wire [0:0] clk__FEEDTHRU_4 ; -wire [0:0] clk__FEEDTHRU_5 ; -wire [0:0] clk__FEEDTHRU_6 ; -wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ; -// - -grid_clb grid_clb_1__1_ ( - .prog_clk ( { ctsbuf_net_1921 } ) , - .Test_en ( Test_en__FEEDTHRU_6 ) , .clk ( clk__FEEDTHRU_6 ) , - .top_width_0_height_0__pin_0_ ( cbx_1__1__0_bottom_grid_pin_0_ ) , - .top_width_0_height_0__pin_1_ ( cbx_1__1__0_bottom_grid_pin_1_ ) , - .top_width_0_height_0__pin_2_ ( cbx_1__1__0_bottom_grid_pin_2_ ) , - .top_width_0_height_0__pin_3_ ( cbx_1__1__0_bottom_grid_pin_3_ ) , - .top_width_0_height_0__pin_4_ ( cbx_1__1__0_bottom_grid_pin_4_ ) , - .top_width_0_height_0__pin_5_ ( cbx_1__1__0_bottom_grid_pin_5_ ) , - .top_width_0_height_0__pin_6_ ( cbx_1__1__0_bottom_grid_pin_6_ ) , - .top_width_0_height_0__pin_7_ ( cbx_1__1__0_bottom_grid_pin_7_ ) , - .top_width_0_height_0__pin_8_ ( cbx_1__1__0_bottom_grid_pin_8_ ) , - .top_width_0_height_0__pin_9_ ( cbx_1__1__0_bottom_grid_pin_9_ ) , - .top_width_0_height_0__pin_10_ ( cbx_1__1__0_bottom_grid_pin_10_ ) , - .top_width_0_height_0__pin_11_ ( cbx_1__1__0_bottom_grid_pin_11_ ) , - .top_width_0_height_0__pin_12_ ( cbx_1__1__0_bottom_grid_pin_12_ ) , - .top_width_0_height_0__pin_13_ ( cbx_1__1__0_bottom_grid_pin_13_ ) , - .top_width_0_height_0__pin_14_ ( cbx_1__1__0_bottom_grid_pin_14_ ) , - .top_width_0_height_0__pin_15_ ( cbx_1__1__0_bottom_grid_pin_15_ ) , - .top_width_0_height_0__pin_32_ ( direct_interc_0_out ) , - .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1 } ) , - .right_width_0_height_0__pin_16_ ( cby_1__1__0_left_grid_pin_16_ ) , - .right_width_0_height_0__pin_17_ ( cby_1__1__0_left_grid_pin_17_ ) , - .right_width_0_height_0__pin_18_ ( cby_1__1__0_left_grid_pin_18_ ) , - .right_width_0_height_0__pin_19_ ( cby_1__1__0_left_grid_pin_19_ ) , - .right_width_0_height_0__pin_20_ ( cby_1__1__0_left_grid_pin_20_ ) , - .right_width_0_height_0__pin_21_ ( cby_1__1__0_left_grid_pin_21_ ) , - .right_width_0_height_0__pin_22_ ( cby_1__1__0_left_grid_pin_22_ ) , - .right_width_0_height_0__pin_23_ ( cby_1__1__0_left_grid_pin_23_ ) , - .right_width_0_height_0__pin_24_ ( cby_1__1__0_left_grid_pin_24_ ) , - .right_width_0_height_0__pin_25_ ( cby_1__1__0_left_grid_pin_25_ ) , - .right_width_0_height_0__pin_26_ ( cby_1__1__0_left_grid_pin_26_ ) , - .right_width_0_height_0__pin_27_ ( cby_1__1__0_left_grid_pin_27_ ) , - .right_width_0_height_0__pin_28_ ( cby_1__1__0_left_grid_pin_28_ ) , - .right_width_0_height_0__pin_29_ ( cby_1__1__0_left_grid_pin_29_ ) , - .right_width_0_height_0__pin_30_ ( cby_1__1__0_left_grid_pin_30_ ) , - .right_width_0_height_0__pin_31_ ( cby_1__1__0_left_grid_pin_31_ ) , - .left_width_0_height_0__pin_52_ ( grid_clb_1__1__undriven_left_width_0_height_0__pin_52_ ) , - .ccff_head ( grid_io_left_0_ccff_tail ) , - .top_width_0_height_0__pin_34_upper ( grid_clb_0_top_width_0_height_0__pin_34_upper ) , - .top_width_0_height_0__pin_34_lower ( grid_clb_0_top_width_0_height_0__pin_34_lower ) , - .top_width_0_height_0__pin_35_upper ( grid_clb_0_top_width_0_height_0__pin_35_upper ) , - .top_width_0_height_0__pin_35_lower ( grid_clb_0_top_width_0_height_0__pin_35_lower ) , - .top_width_0_height_0__pin_36_upper ( grid_clb_0_top_width_0_height_0__pin_36_upper ) , - .top_width_0_height_0__pin_36_lower ( grid_clb_0_top_width_0_height_0__pin_36_lower ) , - .top_width_0_height_0__pin_37_upper ( grid_clb_0_top_width_0_height_0__pin_37_upper ) , - .top_width_0_height_0__pin_37_lower ( grid_clb_0_top_width_0_height_0__pin_37_lower ) , - .top_width_0_height_0__pin_38_upper ( grid_clb_0_top_width_0_height_0__pin_38_upper ) , - .top_width_0_height_0__pin_38_lower ( grid_clb_0_top_width_0_height_0__pin_38_lower ) , - .top_width_0_height_0__pin_39_upper ( grid_clb_0_top_width_0_height_0__pin_39_upper ) , - .top_width_0_height_0__pin_39_lower ( grid_clb_0_top_width_0_height_0__pin_39_lower ) , - .top_width_0_height_0__pin_40_upper ( grid_clb_0_top_width_0_height_0__pin_40_upper ) , - .top_width_0_height_0__pin_40_lower ( grid_clb_0_top_width_0_height_0__pin_40_lower ) , - .top_width_0_height_0__pin_41_upper ( grid_clb_0_top_width_0_height_0__pin_41_upper ) , - .top_width_0_height_0__pin_41_lower ( grid_clb_0_top_width_0_height_0__pin_41_lower ) , - .right_width_0_height_0__pin_42_upper ( grid_clb_0_right_width_0_height_0__pin_42_upper ) , - .right_width_0_height_0__pin_42_lower ( grid_clb_0_right_width_0_height_0__pin_42_lower ) , - .right_width_0_height_0__pin_43_upper ( grid_clb_0_right_width_0_height_0__pin_43_upper ) , - .right_width_0_height_0__pin_43_lower ( grid_clb_0_right_width_0_height_0__pin_43_lower ) , - .right_width_0_height_0__pin_44_upper ( grid_clb_0_right_width_0_height_0__pin_44_upper ) , - .right_width_0_height_0__pin_44_lower ( grid_clb_0_right_width_0_height_0__pin_44_lower ) , - .right_width_0_height_0__pin_45_upper ( grid_clb_0_right_width_0_height_0__pin_45_upper ) , - .right_width_0_height_0__pin_45_lower ( grid_clb_0_right_width_0_height_0__pin_45_lower ) , - .right_width_0_height_0__pin_46_upper ( grid_clb_0_right_width_0_height_0__pin_46_upper ) , - .right_width_0_height_0__pin_46_lower ( grid_clb_0_right_width_0_height_0__pin_46_lower ) , - .right_width_0_height_0__pin_47_upper ( grid_clb_0_right_width_0_height_0__pin_47_upper ) , - .right_width_0_height_0__pin_47_lower ( grid_clb_0_right_width_0_height_0__pin_47_lower ) , - .right_width_0_height_0__pin_48_upper ( grid_clb_0_right_width_0_height_0__pin_48_upper ) , - .right_width_0_height_0__pin_48_lower ( grid_clb_0_right_width_0_height_0__pin_48_lower ) , - .right_width_0_height_0__pin_49_upper ( grid_clb_0_right_width_0_height_0__pin_49_upper ) , - .right_width_0_height_0__pin_49_lower ( grid_clb_0_right_width_0_height_0__pin_49_lower ) , - .bottom_width_0_height_0__pin_50_ ( grid_clb_0_bottom_width_0_height_0__pin_50_ ) , - .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_2 } ) , - .ccff_tail ( grid_clb_0_ccff_tail ) , .SC_IN_TOP ( scff_Wires_3_ ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_3 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4 ) , .SC_OUT_BOT ( scff_Wires_5_ ) , - .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_3 ) , - .prog_clk__FEEDTHRU_2 ( prog_clk__FEEDTHRU_4 ) , - .prog_clk__FEEDTHRU_3 ( { SYNOPSYS_UNCONNECTED_5 } ) , - .prog_clk__FEEDTHRU_4 ( { SYNOPSYS_UNCONNECTED_6 } ) , - .Test_en__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_7 } ) , - .clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_8 } ) ) ; -grid_clb grid_clb_1__2_ ( - .prog_clk ( { ctsbuf_net_1113 } ) , - .Test_en ( Test_en__FEEDTHRU_4 ) , .clk ( clk__FEEDTHRU_4 ) , - .top_width_0_height_0__pin_0_ ( cbx_1__2__0_bottom_grid_pin_0_ ) , - .top_width_0_height_0__pin_1_ ( cbx_1__2__0_bottom_grid_pin_1_ ) , - .top_width_0_height_0__pin_2_ ( cbx_1__2__0_bottom_grid_pin_2_ ) , - .top_width_0_height_0__pin_3_ ( cbx_1__2__0_bottom_grid_pin_3_ ) , - .top_width_0_height_0__pin_4_ ( cbx_1__2__0_bottom_grid_pin_4_ ) , - .top_width_0_height_0__pin_5_ ( cbx_1__2__0_bottom_grid_pin_5_ ) , - .top_width_0_height_0__pin_6_ ( cbx_1__2__0_bottom_grid_pin_6_ ) , - .top_width_0_height_0__pin_7_ ( cbx_1__2__0_bottom_grid_pin_7_ ) , - .top_width_0_height_0__pin_8_ ( cbx_1__2__0_bottom_grid_pin_8_ ) , - .top_width_0_height_0__pin_9_ ( cbx_1__2__0_bottom_grid_pin_9_ ) , - .top_width_0_height_0__pin_10_ ( cbx_1__2__0_bottom_grid_pin_10_ ) , - .top_width_0_height_0__pin_11_ ( cbx_1__2__0_bottom_grid_pin_11_ ) , - .top_width_0_height_0__pin_12_ ( cbx_1__2__0_bottom_grid_pin_12_ ) , - .top_width_0_height_0__pin_13_ ( cbx_1__2__0_bottom_grid_pin_13_ ) , - .top_width_0_height_0__pin_14_ ( cbx_1__2__0_bottom_grid_pin_14_ ) , - .top_width_0_height_0__pin_15_ ( cbx_1__2__0_bottom_grid_pin_15_ ) , - .top_width_0_height_0__pin_32_ ( grid_clb_1__2__undriven_top_width_0_height_0__pin_32_ ) , - .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_9 } ) , - .right_width_0_height_0__pin_16_ ( cby_1__1__1_left_grid_pin_16_ ) , - .right_width_0_height_0__pin_17_ ( cby_1__1__1_left_grid_pin_17_ ) , - .right_width_0_height_0__pin_18_ ( cby_1__1__1_left_grid_pin_18_ ) , - .right_width_0_height_0__pin_19_ ( cby_1__1__1_left_grid_pin_19_ ) , - .right_width_0_height_0__pin_20_ ( cby_1__1__1_left_grid_pin_20_ ) , - .right_width_0_height_0__pin_21_ ( cby_1__1__1_left_grid_pin_21_ ) , - .right_width_0_height_0__pin_22_ ( cby_1__1__1_left_grid_pin_22_ ) , - .right_width_0_height_0__pin_23_ ( cby_1__1__1_left_grid_pin_23_ ) , - .right_width_0_height_0__pin_24_ ( cby_1__1__1_left_grid_pin_24_ ) , - .right_width_0_height_0__pin_25_ ( cby_1__1__1_left_grid_pin_25_ ) , - .right_width_0_height_0__pin_26_ ( cby_1__1__1_left_grid_pin_26_ ) , - .right_width_0_height_0__pin_27_ ( cby_1__1__1_left_grid_pin_27_ ) , - .right_width_0_height_0__pin_28_ ( cby_1__1__1_left_grid_pin_28_ ) , - .right_width_0_height_0__pin_29_ ( cby_1__1__1_left_grid_pin_29_ ) , - .right_width_0_height_0__pin_30_ ( cby_1__1__1_left_grid_pin_30_ ) , - .right_width_0_height_0__pin_31_ ( cby_1__1__1_left_grid_pin_31_ ) , - .left_width_0_height_0__pin_52_ ( grid_clb_1__2__undriven_left_width_0_height_0__pin_52_ ) , - .ccff_head ( grid_io_left_1_ccff_tail ) , - .top_width_0_height_0__pin_34_upper ( grid_clb_1_top_width_0_height_0__pin_34_upper ) , - .top_width_0_height_0__pin_34_lower ( grid_clb_1_top_width_0_height_0__pin_34_lower ) , - .top_width_0_height_0__pin_35_upper ( grid_clb_1_top_width_0_height_0__pin_35_upper ) , - .top_width_0_height_0__pin_35_lower ( grid_clb_1_top_width_0_height_0__pin_35_lower ) , - .top_width_0_height_0__pin_36_upper ( grid_clb_1_top_width_0_height_0__pin_36_upper ) , - .top_width_0_height_0__pin_36_lower ( grid_clb_1_top_width_0_height_0__pin_36_lower ) , - .top_width_0_height_0__pin_37_upper ( grid_clb_1_top_width_0_height_0__pin_37_upper ) , - .top_width_0_height_0__pin_37_lower ( grid_clb_1_top_width_0_height_0__pin_37_lower ) , - .top_width_0_height_0__pin_38_upper ( grid_clb_1_top_width_0_height_0__pin_38_upper ) , - .top_width_0_height_0__pin_38_lower ( grid_clb_1_top_width_0_height_0__pin_38_lower ) , - .top_width_0_height_0__pin_39_upper ( grid_clb_1_top_width_0_height_0__pin_39_upper ) , - .top_width_0_height_0__pin_39_lower ( grid_clb_1_top_width_0_height_0__pin_39_lower ) , - .top_width_0_height_0__pin_40_upper ( grid_clb_1_top_width_0_height_0__pin_40_upper ) , - .top_width_0_height_0__pin_40_lower ( grid_clb_1_top_width_0_height_0__pin_40_lower ) , - .top_width_0_height_0__pin_41_upper ( grid_clb_1_top_width_0_height_0__pin_41_upper ) , - .top_width_0_height_0__pin_41_lower ( grid_clb_1_top_width_0_height_0__pin_41_lower ) , - .right_width_0_height_0__pin_42_upper ( grid_clb_1_right_width_0_height_0__pin_42_upper ) , - .right_width_0_height_0__pin_42_lower ( grid_clb_1_right_width_0_height_0__pin_42_lower ) , - .right_width_0_height_0__pin_43_upper ( grid_clb_1_right_width_0_height_0__pin_43_upper ) , - .right_width_0_height_0__pin_43_lower ( grid_clb_1_right_width_0_height_0__pin_43_lower ) , - .right_width_0_height_0__pin_44_upper ( grid_clb_1_right_width_0_height_0__pin_44_upper ) , - .right_width_0_height_0__pin_44_lower ( grid_clb_1_right_width_0_height_0__pin_44_lower ) , - .right_width_0_height_0__pin_45_upper ( grid_clb_1_right_width_0_height_0__pin_45_upper ) , - .right_width_0_height_0__pin_45_lower ( grid_clb_1_right_width_0_height_0__pin_45_lower ) , - .right_width_0_height_0__pin_46_upper ( grid_clb_1_right_width_0_height_0__pin_46_upper ) , - .right_width_0_height_0__pin_46_lower ( grid_clb_1_right_width_0_height_0__pin_46_lower ) , - .right_width_0_height_0__pin_47_upper ( grid_clb_1_right_width_0_height_0__pin_47_upper ) , - .right_width_0_height_0__pin_47_lower ( grid_clb_1_right_width_0_height_0__pin_47_lower ) , - .right_width_0_height_0__pin_48_upper ( grid_clb_1_right_width_0_height_0__pin_48_upper ) , - .right_width_0_height_0__pin_48_lower ( grid_clb_1_right_width_0_height_0__pin_48_lower ) , - .right_width_0_height_0__pin_49_upper ( grid_clb_1_right_width_0_height_0__pin_49_upper ) , - .right_width_0_height_0__pin_49_lower ( grid_clb_1_right_width_0_height_0__pin_49_lower ) , - .bottom_width_0_height_0__pin_50_ ( grid_clb_1_bottom_width_0_height_0__pin_50_ ) , - .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_10 } ) , - .ccff_tail ( grid_clb_1_ccff_tail ) , .SC_IN_TOP ( scff_Wires_1_ ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_11 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_12 ) , .SC_OUT_BOT ( scff_Wires_2_ ) , - .prog_clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_13 } ) , - .prog_clk__FEEDTHRU_2 ( { SYNOPSYS_UNCONNECTED_14 } ) , - .prog_clk__FEEDTHRU_3 ( prog_clk__FEEDTHRU_6 ) , - .prog_clk__FEEDTHRU_4 ( { SYNOPSYS_UNCONNECTED_15 } ) , - .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_5 ) , - .clk__FEEDTHRU_1 ( clk__FEEDTHRU_5 ) ) ; -grid_clb grid_clb_2__1_ ( .prog_clk ( prog_clk__FEEDTHRU_16 ) , - .Test_en ( Test_en__FEEDTHRU_3 ) , .clk ( clk__FEEDTHRU_3 ) , - .top_width_0_height_0__pin_0_ ( cbx_1__1__1_bottom_grid_pin_0_ ) , - .top_width_0_height_0__pin_1_ ( cbx_1__1__1_bottom_grid_pin_1_ ) , - .top_width_0_height_0__pin_2_ ( cbx_1__1__1_bottom_grid_pin_2_ ) , - .top_width_0_height_0__pin_3_ ( cbx_1__1__1_bottom_grid_pin_3_ ) , - .top_width_0_height_0__pin_4_ ( cbx_1__1__1_bottom_grid_pin_4_ ) , - .top_width_0_height_0__pin_5_ ( cbx_1__1__1_bottom_grid_pin_5_ ) , - .top_width_0_height_0__pin_6_ ( cbx_1__1__1_bottom_grid_pin_6_ ) , - .top_width_0_height_0__pin_7_ ( cbx_1__1__1_bottom_grid_pin_7_ ) , - .top_width_0_height_0__pin_8_ ( cbx_1__1__1_bottom_grid_pin_8_ ) , - .top_width_0_height_0__pin_9_ ( cbx_1__1__1_bottom_grid_pin_9_ ) , - .top_width_0_height_0__pin_10_ ( cbx_1__1__1_bottom_grid_pin_10_ ) , - .top_width_0_height_0__pin_11_ ( cbx_1__1__1_bottom_grid_pin_11_ ) , - .top_width_0_height_0__pin_12_ ( cbx_1__1__1_bottom_grid_pin_12_ ) , - .top_width_0_height_0__pin_13_ ( cbx_1__1__1_bottom_grid_pin_13_ ) , - .top_width_0_height_0__pin_14_ ( cbx_1__1__1_bottom_grid_pin_14_ ) , - .top_width_0_height_0__pin_15_ ( cbx_1__1__1_bottom_grid_pin_15_ ) , - .top_width_0_height_0__pin_32_ ( direct_interc_1_out ) , - .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_16 } ) , - .right_width_0_height_0__pin_16_ ( cby_2__1__0_left_grid_pin_16_ ) , - .right_width_0_height_0__pin_17_ ( cby_2__1__0_left_grid_pin_17_ ) , - .right_width_0_height_0__pin_18_ ( cby_2__1__0_left_grid_pin_18_ ) , - .right_width_0_height_0__pin_19_ ( cby_2__1__0_left_grid_pin_19_ ) , - .right_width_0_height_0__pin_20_ ( cby_2__1__0_left_grid_pin_20_ ) , - .right_width_0_height_0__pin_21_ ( cby_2__1__0_left_grid_pin_21_ ) , - .right_width_0_height_0__pin_22_ ( cby_2__1__0_left_grid_pin_22_ ) , - .right_width_0_height_0__pin_23_ ( cby_2__1__0_left_grid_pin_23_ ) , - .right_width_0_height_0__pin_24_ ( cby_2__1__0_left_grid_pin_24_ ) , - .right_width_0_height_0__pin_25_ ( cby_2__1__0_left_grid_pin_25_ ) , - .right_width_0_height_0__pin_26_ ( cby_2__1__0_left_grid_pin_26_ ) , - .right_width_0_height_0__pin_27_ ( cby_2__1__0_left_grid_pin_27_ ) , - .right_width_0_height_0__pin_28_ ( cby_2__1__0_left_grid_pin_28_ ) , - .right_width_0_height_0__pin_29_ ( cby_2__1__0_left_grid_pin_29_ ) , - .right_width_0_height_0__pin_30_ ( cby_2__1__0_left_grid_pin_30_ ) , - .right_width_0_height_0__pin_31_ ( cby_2__1__0_left_grid_pin_31_ ) , - .left_width_0_height_0__pin_52_ ( grid_clb_2__1__undriven_left_width_0_height_0__pin_52_ ) , - .ccff_head ( cby_1__1__0_ccff_tail ) , - .top_width_0_height_0__pin_34_upper ( grid_clb_2_top_width_0_height_0__pin_34_upper ) , - .top_width_0_height_0__pin_34_lower ( grid_clb_2_top_width_0_height_0__pin_34_lower ) , - .top_width_0_height_0__pin_35_upper ( grid_clb_2_top_width_0_height_0__pin_35_upper ) , - .top_width_0_height_0__pin_35_lower ( grid_clb_2_top_width_0_height_0__pin_35_lower ) , - .top_width_0_height_0__pin_36_upper ( grid_clb_2_top_width_0_height_0__pin_36_upper ) , - .top_width_0_height_0__pin_36_lower ( grid_clb_2_top_width_0_height_0__pin_36_lower ) , - .top_width_0_height_0__pin_37_upper ( grid_clb_2_top_width_0_height_0__pin_37_upper ) , - .top_width_0_height_0__pin_37_lower ( grid_clb_2_top_width_0_height_0__pin_37_lower ) , - .top_width_0_height_0__pin_38_upper ( grid_clb_2_top_width_0_height_0__pin_38_upper ) , - .top_width_0_height_0__pin_38_lower ( grid_clb_2_top_width_0_height_0__pin_38_lower ) , - .top_width_0_height_0__pin_39_upper ( grid_clb_2_top_width_0_height_0__pin_39_upper ) , - .top_width_0_height_0__pin_39_lower ( grid_clb_2_top_width_0_height_0__pin_39_lower ) , - .top_width_0_height_0__pin_40_upper ( grid_clb_2_top_width_0_height_0__pin_40_upper ) , - .top_width_0_height_0__pin_40_lower ( grid_clb_2_top_width_0_height_0__pin_40_lower ) , - .top_width_0_height_0__pin_41_upper ( grid_clb_2_top_width_0_height_0__pin_41_upper ) , - .top_width_0_height_0__pin_41_lower ( grid_clb_2_top_width_0_height_0__pin_41_lower ) , - .right_width_0_height_0__pin_42_upper ( grid_clb_2_right_width_0_height_0__pin_42_upper ) , - .right_width_0_height_0__pin_42_lower ( grid_clb_2_right_width_0_height_0__pin_42_lower ) , - .right_width_0_height_0__pin_43_upper ( grid_clb_2_right_width_0_height_0__pin_43_upper ) , - .right_width_0_height_0__pin_43_lower ( grid_clb_2_right_width_0_height_0__pin_43_lower ) , - .right_width_0_height_0__pin_44_upper ( grid_clb_2_right_width_0_height_0__pin_44_upper ) , - .right_width_0_height_0__pin_44_lower ( grid_clb_2_right_width_0_height_0__pin_44_lower ) , - .right_width_0_height_0__pin_45_upper ( grid_clb_2_right_width_0_height_0__pin_45_upper ) , - .right_width_0_height_0__pin_45_lower ( grid_clb_2_right_width_0_height_0__pin_45_lower ) , - .right_width_0_height_0__pin_46_upper ( grid_clb_2_right_width_0_height_0__pin_46_upper ) , - .right_width_0_height_0__pin_46_lower ( grid_clb_2_right_width_0_height_0__pin_46_lower ) , - .right_width_0_height_0__pin_47_upper ( grid_clb_2_right_width_0_height_0__pin_47_upper ) , - .right_width_0_height_0__pin_47_lower ( grid_clb_2_right_width_0_height_0__pin_47_lower ) , - .right_width_0_height_0__pin_48_upper ( grid_clb_2_right_width_0_height_0__pin_48_upper ) , - .right_width_0_height_0__pin_48_lower ( grid_clb_2_right_width_0_height_0__pin_48_lower ) , - .right_width_0_height_0__pin_49_upper ( grid_clb_2_right_width_0_height_0__pin_49_upper ) , - .right_width_0_height_0__pin_49_lower ( grid_clb_2_right_width_0_height_0__pin_49_lower ) , - .bottom_width_0_height_0__pin_50_ ( grid_clb_2__1__undriven_bottom_width_0_height_0__pin_50_ ) , - .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_17 } ) , - .ccff_tail ( grid_clb_2_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_18 ) , .SC_IN_BOT ( scff_Wires_8_ ) , - .SC_OUT_TOP ( scff_Wires_9_ ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_19 ) , - .prog_clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_20 } ) , - .prog_clk__FEEDTHRU_2 ( prog_clk__FEEDTHRU_17 ) , - .prog_clk__FEEDTHRU_3 ( { SYNOPSYS_UNCONNECTED_21 } ) , - .prog_clk__FEEDTHRU_4 ( prog_clk__FEEDTHRU_19 ) , - .Test_en__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_22 } ) , - .clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_23 } ) ) ; -grid_clb grid_clb_2__2_ ( - .prog_clk ( { ctsbuf_net_1315 } ) , - .Test_en ( Test_en__FEEDTHRU_1 ) , .clk ( clk__FEEDTHRU_1 ) , - .top_width_0_height_0__pin_0_ ( cbx_1__2__1_bottom_grid_pin_0_ ) , - .top_width_0_height_0__pin_1_ ( cbx_1__2__1_bottom_grid_pin_1_ ) , - .top_width_0_height_0__pin_2_ ( cbx_1__2__1_bottom_grid_pin_2_ ) , - .top_width_0_height_0__pin_3_ ( cbx_1__2__1_bottom_grid_pin_3_ ) , - .top_width_0_height_0__pin_4_ ( cbx_1__2__1_bottom_grid_pin_4_ ) , - .top_width_0_height_0__pin_5_ ( cbx_1__2__1_bottom_grid_pin_5_ ) , - .top_width_0_height_0__pin_6_ ( cbx_1__2__1_bottom_grid_pin_6_ ) , - .top_width_0_height_0__pin_7_ ( cbx_1__2__1_bottom_grid_pin_7_ ) , - .top_width_0_height_0__pin_8_ ( cbx_1__2__1_bottom_grid_pin_8_ ) , - .top_width_0_height_0__pin_9_ ( cbx_1__2__1_bottom_grid_pin_9_ ) , - .top_width_0_height_0__pin_10_ ( cbx_1__2__1_bottom_grid_pin_10_ ) , - .top_width_0_height_0__pin_11_ ( cbx_1__2__1_bottom_grid_pin_11_ ) , - .top_width_0_height_0__pin_12_ ( cbx_1__2__1_bottom_grid_pin_12_ ) , - .top_width_0_height_0__pin_13_ ( cbx_1__2__1_bottom_grid_pin_13_ ) , - .top_width_0_height_0__pin_14_ ( cbx_1__2__1_bottom_grid_pin_14_ ) , - .top_width_0_height_0__pin_15_ ( cbx_1__2__1_bottom_grid_pin_15_ ) , - .top_width_0_height_0__pin_32_ ( direct_interc_2_out ) , - .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_24 } ) , - .right_width_0_height_0__pin_16_ ( cby_2__1__1_left_grid_pin_16_ ) , - .right_width_0_height_0__pin_17_ ( cby_2__1__1_left_grid_pin_17_ ) , - .right_width_0_height_0__pin_18_ ( cby_2__1__1_left_grid_pin_18_ ) , - .right_width_0_height_0__pin_19_ ( cby_2__1__1_left_grid_pin_19_ ) , - .right_width_0_height_0__pin_20_ ( cby_2__1__1_left_grid_pin_20_ ) , - .right_width_0_height_0__pin_21_ ( cby_2__1__1_left_grid_pin_21_ ) , - .right_width_0_height_0__pin_22_ ( cby_2__1__1_left_grid_pin_22_ ) , - .right_width_0_height_0__pin_23_ ( cby_2__1__1_left_grid_pin_23_ ) , - .right_width_0_height_0__pin_24_ ( cby_2__1__1_left_grid_pin_24_ ) , - .right_width_0_height_0__pin_25_ ( cby_2__1__1_left_grid_pin_25_ ) , - .right_width_0_height_0__pin_26_ ( cby_2__1__1_left_grid_pin_26_ ) , - .right_width_0_height_0__pin_27_ ( cby_2__1__1_left_grid_pin_27_ ) , - .right_width_0_height_0__pin_28_ ( cby_2__1__1_left_grid_pin_28_ ) , - .right_width_0_height_0__pin_29_ ( cby_2__1__1_left_grid_pin_29_ ) , - .right_width_0_height_0__pin_30_ ( cby_2__1__1_left_grid_pin_30_ ) , - .right_width_0_height_0__pin_31_ ( cby_2__1__1_left_grid_pin_31_ ) , - .left_width_0_height_0__pin_52_ ( grid_clb_2__2__undriven_left_width_0_height_0__pin_52_ ) , - .ccff_head ( cby_1__1__1_ccff_tail ) , - .top_width_0_height_0__pin_34_upper ( grid_clb_3_top_width_0_height_0__pin_34_upper ) , - .top_width_0_height_0__pin_34_lower ( grid_clb_3_top_width_0_height_0__pin_34_lower ) , - .top_width_0_height_0__pin_35_upper ( grid_clb_3_top_width_0_height_0__pin_35_upper ) , - .top_width_0_height_0__pin_35_lower ( grid_clb_3_top_width_0_height_0__pin_35_lower ) , - .top_width_0_height_0__pin_36_upper ( grid_clb_3_top_width_0_height_0__pin_36_upper ) , - .top_width_0_height_0__pin_36_lower ( grid_clb_3_top_width_0_height_0__pin_36_lower ) , - .top_width_0_height_0__pin_37_upper ( grid_clb_3_top_width_0_height_0__pin_37_upper ) , - .top_width_0_height_0__pin_37_lower ( grid_clb_3_top_width_0_height_0__pin_37_lower ) , - .top_width_0_height_0__pin_38_upper ( grid_clb_3_top_width_0_height_0__pin_38_upper ) , - .top_width_0_height_0__pin_38_lower ( grid_clb_3_top_width_0_height_0__pin_38_lower ) , - .top_width_0_height_0__pin_39_upper ( grid_clb_3_top_width_0_height_0__pin_39_upper ) , - .top_width_0_height_0__pin_39_lower ( grid_clb_3_top_width_0_height_0__pin_39_lower ) , - .top_width_0_height_0__pin_40_upper ( grid_clb_3_top_width_0_height_0__pin_40_upper ) , - .top_width_0_height_0__pin_40_lower ( grid_clb_3_top_width_0_height_0__pin_40_lower ) , - .top_width_0_height_0__pin_41_upper ( grid_clb_3_top_width_0_height_0__pin_41_upper ) , - .top_width_0_height_0__pin_41_lower ( grid_clb_3_top_width_0_height_0__pin_41_lower ) , - .right_width_0_height_0__pin_42_upper ( grid_clb_3_right_width_0_height_0__pin_42_upper ) , - .right_width_0_height_0__pin_42_lower ( grid_clb_3_right_width_0_height_0__pin_42_lower ) , - .right_width_0_height_0__pin_43_upper ( grid_clb_3_right_width_0_height_0__pin_43_upper ) , - .right_width_0_height_0__pin_43_lower ( grid_clb_3_right_width_0_height_0__pin_43_lower ) , - .right_width_0_height_0__pin_44_upper ( grid_clb_3_right_width_0_height_0__pin_44_upper ) , - .right_width_0_height_0__pin_44_lower ( grid_clb_3_right_width_0_height_0__pin_44_lower ) , - .right_width_0_height_0__pin_45_upper ( grid_clb_3_right_width_0_height_0__pin_45_upper ) , - .right_width_0_height_0__pin_45_lower ( grid_clb_3_right_width_0_height_0__pin_45_lower ) , - .right_width_0_height_0__pin_46_upper ( grid_clb_3_right_width_0_height_0__pin_46_upper ) , - .right_width_0_height_0__pin_46_lower ( grid_clb_3_right_width_0_height_0__pin_46_lower ) , - .right_width_0_height_0__pin_47_upper ( grid_clb_3_right_width_0_height_0__pin_47_upper ) , - .right_width_0_height_0__pin_47_lower ( grid_clb_3_right_width_0_height_0__pin_47_lower ) , - .right_width_0_height_0__pin_48_upper ( grid_clb_3_right_width_0_height_0__pin_48_upper ) , - .right_width_0_height_0__pin_48_lower ( grid_clb_3_right_width_0_height_0__pin_48_lower ) , - .right_width_0_height_0__pin_49_upper ( grid_clb_3_right_width_0_height_0__pin_49_upper ) , - .right_width_0_height_0__pin_49_lower ( grid_clb_3_right_width_0_height_0__pin_49_lower ) , - .bottom_width_0_height_0__pin_50_ ( grid_clb_3_bottom_width_0_height_0__pin_50_ ) , - .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_25 } ) , - .ccff_tail ( grid_clb_3_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_26 ) , .SC_IN_BOT ( scff_Wires_10_ ) , - .SC_OUT_TOP ( scff_Wires_11_ ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_27 ) , - .prog_clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_28 } ) , - .prog_clk__FEEDTHRU_2 ( { SYNOPSYS_UNCONNECTED_29 } ) , - .prog_clk__FEEDTHRU_3 ( prog_clk__FEEDTHRU_13 ) , - .prog_clk__FEEDTHRU_4 ( prog_clk__FEEDTHRU_15 ) , - .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_2 ) , - .clk__FEEDTHRU_1 ( clk__FEEDTHRU_2 ) ) ; -sb_0__0_ sb_0__0_ ( - .prog_clk ( { ctsbuf_net_1719 } ) , - .chany_top_in ( cby_0__1__0_chany_bottom_out ) , - .top_left_grid_pin_1_ ( grid_io_left_0_right_width_0_height_0__pin_1_lower ) , - .chanx_right_in ( cbx_1__0__0_chanx_left_out ) , - .right_bottom_grid_pin_1_ ( grid_io_bottom_0_top_width_0_height_0__pin_1_upper ) , - .right_bottom_grid_pin_3_ ( grid_io_bottom_0_top_width_0_height_0__pin_3_upper ) , - .right_bottom_grid_pin_5_ ( grid_io_bottom_0_top_width_0_height_0__pin_5_upper ) , - .right_bottom_grid_pin_7_ ( grid_io_bottom_0_top_width_0_height_0__pin_7_upper ) , - .right_bottom_grid_pin_9_ ( grid_io_bottom_0_top_width_0_height_0__pin_9_upper ) , - .right_bottom_grid_pin_11_ ( grid_io_bottom_0_top_width_0_height_0__pin_11_upper ) , - .ccff_head ( grid_io_bottom_0_ccff_tail ) , - .chany_top_out ( sb_0__0__0_chany_top_out ) , - .chanx_right_out ( sb_0__0__0_chanx_right_out ) , - .ccff_tail ( ccff_tail ) ) ; -sb_0__1_ sb_0__1_ ( .prog_clk ( prog_clk__FEEDTHRU_4 ) , - .chany_top_in ( cby_0__1__1_chany_bottom_out ) , - .top_left_grid_pin_1_ ( grid_io_left_1_right_width_0_height_0__pin_1_lower ) , - .chanx_right_in ( cbx_1__1__0_chanx_left_out ) , - .right_bottom_grid_pin_34_ ( grid_clb_0_top_width_0_height_0__pin_34_upper ) , - .right_bottom_grid_pin_35_ ( grid_clb_0_top_width_0_height_0__pin_35_upper ) , - .right_bottom_grid_pin_36_ ( grid_clb_0_top_width_0_height_0__pin_36_upper ) , - .right_bottom_grid_pin_37_ ( grid_clb_0_top_width_0_height_0__pin_37_upper ) , - .right_bottom_grid_pin_38_ ( grid_clb_0_top_width_0_height_0__pin_38_upper ) , - .right_bottom_grid_pin_39_ ( grid_clb_0_top_width_0_height_0__pin_39_upper ) , - .right_bottom_grid_pin_40_ ( grid_clb_0_top_width_0_height_0__pin_40_upper ) , - .right_bottom_grid_pin_41_ ( grid_clb_0_top_width_0_height_0__pin_41_upper ) , - .chany_bottom_in ( cby_0__1__0_chany_top_out ) , - .bottom_left_grid_pin_1_ ( grid_io_left_0_right_width_0_height_0__pin_1_upper ) , - .ccff_head ( cbx_1__1__0_ccff_tail ) , - .chany_top_out ( sb_0__1__0_chany_top_out ) , - .chanx_right_out ( sb_0__1__0_chanx_right_out ) , - .chany_bottom_out ( sb_0__1__0_chany_bottom_out ) , - .ccff_tail ( sb_0__1__0_ccff_tail ) , - .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_5 ) ) ; -sb_0__2_ sb_0__2_ ( .prog_clk ( prog_clk__FEEDTHRU_7 ) , - .chanx_right_in ( cbx_1__2__0_chanx_left_out ) , - .right_top_grid_pin_1_ ( grid_io_top_0_bottom_width_0_height_0__pin_1_upper ) , - .right_bottom_grid_pin_34_ ( grid_clb_1_top_width_0_height_0__pin_34_upper ) , - .right_bottom_grid_pin_35_ ( grid_clb_1_top_width_0_height_0__pin_35_upper ) , - .right_bottom_grid_pin_36_ ( grid_clb_1_top_width_0_height_0__pin_36_upper ) , - .right_bottom_grid_pin_37_ ( grid_clb_1_top_width_0_height_0__pin_37_upper ) , - .right_bottom_grid_pin_38_ ( grid_clb_1_top_width_0_height_0__pin_38_upper ) , - .right_bottom_grid_pin_39_ ( grid_clb_1_top_width_0_height_0__pin_39_upper ) , - .right_bottom_grid_pin_40_ ( grid_clb_1_top_width_0_height_0__pin_40_upper ) , - .right_bottom_grid_pin_41_ ( grid_clb_1_top_width_0_height_0__pin_41_upper ) , - .chany_bottom_in ( cby_0__1__1_chany_top_out ) , - .bottom_left_grid_pin_1_ ( grid_io_left_1_right_width_0_height_0__pin_1_upper ) , - .ccff_head ( grid_io_top_0_ccff_tail ) , - .chanx_right_out ( sb_0__2__0_chanx_right_out ) , - .chany_bottom_out ( sb_0__2__0_chany_bottom_out ) , - .ccff_tail ( sb_0__2__0_ccff_tail ) , .SC_IN_TOP ( sc_head ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_30 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_31 ) , .SC_OUT_BOT ( scff_Wires_0_ ) ) ; -sb_1__0_ sb_1__0_ ( .prog_clk ( prog_clk ) , - .chany_top_in ( cby_1__1__0_chany_bottom_out ) , - .top_left_grid_pin_42_ ( grid_clb_0_right_width_0_height_0__pin_42_lower ) , - .top_left_grid_pin_43_ ( grid_clb_0_right_width_0_height_0__pin_43_lower ) , - .top_left_grid_pin_44_ ( grid_clb_0_right_width_0_height_0__pin_44_lower ) , - .top_left_grid_pin_45_ ( grid_clb_0_right_width_0_height_0__pin_45_lower ) , - .top_left_grid_pin_46_ ( grid_clb_0_right_width_0_height_0__pin_46_lower ) , - .top_left_grid_pin_47_ ( grid_clb_0_right_width_0_height_0__pin_47_lower ) , - .top_left_grid_pin_48_ ( grid_clb_0_right_width_0_height_0__pin_48_lower ) , - .top_left_grid_pin_49_ ( grid_clb_0_right_width_0_height_0__pin_49_lower ) , - .chanx_right_in ( cbx_1__0__1_chanx_left_out ) , - .right_bottom_grid_pin_1_ ( grid_io_bottom_1_top_width_0_height_0__pin_1_upper ) , - .right_bottom_grid_pin_3_ ( grid_io_bottom_1_top_width_0_height_0__pin_3_upper ) , - .right_bottom_grid_pin_5_ ( grid_io_bottom_1_top_width_0_height_0__pin_5_upper ) , - .right_bottom_grid_pin_7_ ( grid_io_bottom_1_top_width_0_height_0__pin_7_upper ) , - .right_bottom_grid_pin_9_ ( grid_io_bottom_1_top_width_0_height_0__pin_9_upper ) , - .right_bottom_grid_pin_11_ ( grid_io_bottom_1_top_width_0_height_0__pin_11_upper ) , - .chanx_left_in ( cbx_1__0__0_chanx_right_out ) , - .left_bottom_grid_pin_1_ ( grid_io_bottom_0_top_width_0_height_0__pin_1_lower ) , - .left_bottom_grid_pin_3_ ( grid_io_bottom_0_top_width_0_height_0__pin_3_lower ) , - .left_bottom_grid_pin_5_ ( grid_io_bottom_0_top_width_0_height_0__pin_5_lower ) , - .left_bottom_grid_pin_7_ ( grid_io_bottom_0_top_width_0_height_0__pin_7_lower ) , - .left_bottom_grid_pin_9_ ( grid_io_bottom_0_top_width_0_height_0__pin_9_lower ) , - .left_bottom_grid_pin_11_ ( grid_io_bottom_0_top_width_0_height_0__pin_11_lower ) , - .ccff_head ( grid_io_bottom_1_ccff_tail ) , - .chany_top_out ( sb_1__0__0_chany_top_out ) , - .chanx_right_out ( sb_1__0__0_chanx_right_out ) , - .chanx_left_out ( sb_1__0__0_chanx_left_out ) , - .ccff_tail ( sb_1__0__0_ccff_tail ) , .SC_IN_TOP ( scff_Wires_6_ ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_32 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_33 ) , .SC_OUT_BOT ( scff_Wires_7_ ) , - .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_1 ) , - .prog_clk__FEEDTHRU_2 ( prog_clk__FEEDTHRU_8 ) ) ; -sb_1__1_ sb_1__1_ ( - .prog_clk ( { ctsbuf_net_2123 } ) , - .chany_top_in ( cby_1__1__1_chany_bottom_out ) , - .top_left_grid_pin_42_ ( grid_clb_1_right_width_0_height_0__pin_42_lower ) , - .top_left_grid_pin_43_ ( grid_clb_1_right_width_0_height_0__pin_43_lower ) , - .top_left_grid_pin_44_ ( grid_clb_1_right_width_0_height_0__pin_44_lower ) , - .top_left_grid_pin_45_ ( grid_clb_1_right_width_0_height_0__pin_45_lower ) , - .top_left_grid_pin_46_ ( grid_clb_1_right_width_0_height_0__pin_46_lower ) , - .top_left_grid_pin_47_ ( grid_clb_1_right_width_0_height_0__pin_47_lower ) , - .top_left_grid_pin_48_ ( grid_clb_1_right_width_0_height_0__pin_48_lower ) , - .top_left_grid_pin_49_ ( grid_clb_1_right_width_0_height_0__pin_49_lower ) , - .chanx_right_in ( cbx_1__1__1_chanx_left_out ) , - .right_bottom_grid_pin_34_ ( grid_clb_2_top_width_0_height_0__pin_34_upper ) , - .right_bottom_grid_pin_35_ ( grid_clb_2_top_width_0_height_0__pin_35_upper ) , - .right_bottom_grid_pin_36_ ( grid_clb_2_top_width_0_height_0__pin_36_upper ) , - .right_bottom_grid_pin_37_ ( grid_clb_2_top_width_0_height_0__pin_37_upper ) , - .right_bottom_grid_pin_38_ ( grid_clb_2_top_width_0_height_0__pin_38_upper ) , - .right_bottom_grid_pin_39_ ( grid_clb_2_top_width_0_height_0__pin_39_upper ) , - .right_bottom_grid_pin_40_ ( grid_clb_2_top_width_0_height_0__pin_40_upper ) , - .right_bottom_grid_pin_41_ ( grid_clb_2_top_width_0_height_0__pin_41_upper ) , - .chany_bottom_in ( cby_1__1__0_chany_top_out ) , - .bottom_left_grid_pin_42_ ( grid_clb_0_right_width_0_height_0__pin_42_upper ) , - .bottom_left_grid_pin_43_ ( grid_clb_0_right_width_0_height_0__pin_43_upper ) , - .bottom_left_grid_pin_44_ ( grid_clb_0_right_width_0_height_0__pin_44_upper ) , - .bottom_left_grid_pin_45_ ( grid_clb_0_right_width_0_height_0__pin_45_upper ) , - .bottom_left_grid_pin_46_ ( grid_clb_0_right_width_0_height_0__pin_46_upper ) , - .bottom_left_grid_pin_47_ ( grid_clb_0_right_width_0_height_0__pin_47_upper ) , - .bottom_left_grid_pin_48_ ( grid_clb_0_right_width_0_height_0__pin_48_upper ) , - .bottom_left_grid_pin_49_ ( grid_clb_0_right_width_0_height_0__pin_49_upper ) , - .chanx_left_in ( cbx_1__1__0_chanx_right_out ) , - .left_bottom_grid_pin_34_ ( grid_clb_0_top_width_0_height_0__pin_34_lower ) , - .left_bottom_grid_pin_35_ ( grid_clb_0_top_width_0_height_0__pin_35_lower ) , - .left_bottom_grid_pin_36_ ( grid_clb_0_top_width_0_height_0__pin_36_lower ) , - .left_bottom_grid_pin_37_ ( grid_clb_0_top_width_0_height_0__pin_37_lower ) , - .left_bottom_grid_pin_38_ ( grid_clb_0_top_width_0_height_0__pin_38_lower ) , - .left_bottom_grid_pin_39_ ( grid_clb_0_top_width_0_height_0__pin_39_lower ) , - .left_bottom_grid_pin_40_ ( grid_clb_0_top_width_0_height_0__pin_40_lower ) , - .left_bottom_grid_pin_41_ ( grid_clb_0_top_width_0_height_0__pin_41_lower ) , - .ccff_head ( cbx_1__1__1_ccff_tail ) , - .chany_top_out ( sb_1__1__0_chany_top_out ) , - .chanx_right_out ( sb_1__1__0_chanx_right_out ) , - .chany_bottom_out ( sb_1__1__0_chany_bottom_out ) , - .chanx_left_out ( sb_1__1__0_chanx_left_out ) , - .ccff_tail ( sb_1__1__0_ccff_tail ) , - .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_10 ) , - .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_5 ) , - .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_6 ) , - .clk__FEEDTHRU_0 ( clk__FEEDTHRU_5 ) , - .clk__FEEDTHRU_1 ( clk__FEEDTHRU_6 ) , - .grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_0_bottom_width_0_height_0__pin_50_ ) , - .grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) ) ; -sb_1__2_ sb_1__2_ ( .prog_clk ( prog_clk__FEEDTHRU_11 ) , - .chanx_right_in ( cbx_1__2__1_chanx_left_out ) , - .right_top_grid_pin_1_ ( grid_io_top_1_bottom_width_0_height_0__pin_1_upper ) , - .right_bottom_grid_pin_34_ ( grid_clb_3_top_width_0_height_0__pin_34_upper ) , - .right_bottom_grid_pin_35_ ( grid_clb_3_top_width_0_height_0__pin_35_upper ) , - .right_bottom_grid_pin_36_ ( grid_clb_3_top_width_0_height_0__pin_36_upper ) , - .right_bottom_grid_pin_37_ ( grid_clb_3_top_width_0_height_0__pin_37_upper ) , - .right_bottom_grid_pin_38_ ( grid_clb_3_top_width_0_height_0__pin_38_upper ) , - .right_bottom_grid_pin_39_ ( grid_clb_3_top_width_0_height_0__pin_39_upper ) , - .right_bottom_grid_pin_40_ ( grid_clb_3_top_width_0_height_0__pin_40_upper ) , - .right_bottom_grid_pin_41_ ( grid_clb_3_top_width_0_height_0__pin_41_upper ) , - .chany_bottom_in ( cby_1__1__1_chany_top_out ) , - .bottom_left_grid_pin_42_ ( grid_clb_1_right_width_0_height_0__pin_42_upper ) , - .bottom_left_grid_pin_43_ ( grid_clb_1_right_width_0_height_0__pin_43_upper ) , - .bottom_left_grid_pin_44_ ( grid_clb_1_right_width_0_height_0__pin_44_upper ) , - .bottom_left_grid_pin_45_ ( grid_clb_1_right_width_0_height_0__pin_45_upper ) , - .bottom_left_grid_pin_46_ ( grid_clb_1_right_width_0_height_0__pin_46_upper ) , - .bottom_left_grid_pin_47_ ( grid_clb_1_right_width_0_height_0__pin_47_upper ) , - .bottom_left_grid_pin_48_ ( grid_clb_1_right_width_0_height_0__pin_48_upper ) , - .bottom_left_grid_pin_49_ ( grid_clb_1_right_width_0_height_0__pin_49_upper ) , - .chanx_left_in ( cbx_1__2__0_chanx_right_out ) , - .left_top_grid_pin_1_ ( grid_io_top_0_bottom_width_0_height_0__pin_1_lower ) , - .left_bottom_grid_pin_34_ ( grid_clb_1_top_width_0_height_0__pin_34_lower ) , - .left_bottom_grid_pin_35_ ( grid_clb_1_top_width_0_height_0__pin_35_lower ) , - .left_bottom_grid_pin_36_ ( grid_clb_1_top_width_0_height_0__pin_36_lower ) , - .left_bottom_grid_pin_37_ ( grid_clb_1_top_width_0_height_0__pin_37_lower ) , - .left_bottom_grid_pin_38_ ( grid_clb_1_top_width_0_height_0__pin_38_lower ) , - .left_bottom_grid_pin_39_ ( grid_clb_1_top_width_0_height_0__pin_39_lower ) , - .left_bottom_grid_pin_40_ ( grid_clb_1_top_width_0_height_0__pin_40_lower ) , - .left_bottom_grid_pin_41_ ( grid_clb_1_top_width_0_height_0__pin_41_lower ) , - .ccff_head ( grid_io_top_1_ccff_tail ) , - .chanx_right_out ( sb_1__2__0_chanx_right_out ) , - .chany_bottom_out ( sb_1__2__0_chany_bottom_out ) , - .chanx_left_out ( sb_1__2__0_chanx_left_out ) , - .ccff_tail ( sb_1__2__0_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_34 ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_35 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_36 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_37 ) , - .Test_en__FEEDTHRU_0 ( Test_en ) , - .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_4 ) , - .Test_en__FEEDTHRU_2 ( Test_en__FEEDTHRU_1 ) , .clk__FEEDTHRU_0 ( clk ) , - .clk__FEEDTHRU_1 ( clk__FEEDTHRU_4 ) , - .clk__FEEDTHRU_2 ( clk__FEEDTHRU_1 ) ) ; -sb_2__0_ sb_2__0_ ( - .prog_clk ( { ctsbuf_net_2729 } ) , - .chany_top_in ( cby_2__1__0_chany_bottom_out ) , - .top_left_grid_pin_42_ ( grid_clb_2_right_width_0_height_0__pin_42_lower ) , - .top_left_grid_pin_43_ ( grid_clb_2_right_width_0_height_0__pin_43_lower ) , - .top_left_grid_pin_44_ ( grid_clb_2_right_width_0_height_0__pin_44_lower ) , - .top_left_grid_pin_45_ ( grid_clb_2_right_width_0_height_0__pin_45_lower ) , - .top_left_grid_pin_46_ ( grid_clb_2_right_width_0_height_0__pin_46_lower ) , - .top_left_grid_pin_47_ ( grid_clb_2_right_width_0_height_0__pin_47_lower ) , - .top_left_grid_pin_48_ ( grid_clb_2_right_width_0_height_0__pin_48_lower ) , - .top_left_grid_pin_49_ ( grid_clb_2_right_width_0_height_0__pin_49_lower ) , - .top_right_grid_pin_1_ ( grid_io_right_0_left_width_0_height_0__pin_1_lower ) , - .chanx_left_in ( cbx_1__0__1_chanx_right_out ) , - .left_bottom_grid_pin_1_ ( grid_io_bottom_1_top_width_0_height_0__pin_1_lower ) , - .left_bottom_grid_pin_3_ ( grid_io_bottom_1_top_width_0_height_0__pin_3_lower ) , - .left_bottom_grid_pin_5_ ( grid_io_bottom_1_top_width_0_height_0__pin_5_lower ) , - .left_bottom_grid_pin_7_ ( grid_io_bottom_1_top_width_0_height_0__pin_7_lower ) , - .left_bottom_grid_pin_9_ ( grid_io_bottom_1_top_width_0_height_0__pin_9_lower ) , - .left_bottom_grid_pin_11_ ( grid_io_bottom_1_top_width_0_height_0__pin_11_lower ) , - .ccff_head ( grid_io_right_0_ccff_tail ) , - .chany_top_out ( sb_2__0__0_chany_top_out ) , - .chanx_left_out ( sb_2__0__0_chanx_left_out ) , - .ccff_tail ( sb_2__0__0_ccff_tail ) ) ; -sb_2__1_ sb_2__1_ ( .prog_clk ( prog_clk__FEEDTHRU_18 ) , - .chany_top_in ( cby_2__1__1_chany_bottom_out ) , - .top_left_grid_pin_42_ ( grid_clb_3_right_width_0_height_0__pin_42_lower ) , - .top_left_grid_pin_43_ ( grid_clb_3_right_width_0_height_0__pin_43_lower ) , - .top_left_grid_pin_44_ ( grid_clb_3_right_width_0_height_0__pin_44_lower ) , - .top_left_grid_pin_45_ ( grid_clb_3_right_width_0_height_0__pin_45_lower ) , - .top_left_grid_pin_46_ ( grid_clb_3_right_width_0_height_0__pin_46_lower ) , - .top_left_grid_pin_47_ ( grid_clb_3_right_width_0_height_0__pin_47_lower ) , - .top_left_grid_pin_48_ ( grid_clb_3_right_width_0_height_0__pin_48_lower ) , - .top_left_grid_pin_49_ ( grid_clb_3_right_width_0_height_0__pin_49_lower ) , - .top_right_grid_pin_1_ ( grid_io_right_1_left_width_0_height_0__pin_1_lower ) , - .chany_bottom_in ( cby_2__1__0_chany_top_out ) , - .bottom_right_grid_pin_1_ ( grid_io_right_0_left_width_0_height_0__pin_1_upper ) , - .bottom_left_grid_pin_42_ ( grid_clb_2_right_width_0_height_0__pin_42_upper ) , - .bottom_left_grid_pin_43_ ( grid_clb_2_right_width_0_height_0__pin_43_upper ) , - .bottom_left_grid_pin_44_ ( grid_clb_2_right_width_0_height_0__pin_44_upper ) , - .bottom_left_grid_pin_45_ ( grid_clb_2_right_width_0_height_0__pin_45_upper ) , - .bottom_left_grid_pin_46_ ( grid_clb_2_right_width_0_height_0__pin_46_upper ) , - .bottom_left_grid_pin_47_ ( grid_clb_2_right_width_0_height_0__pin_47_upper ) , - .bottom_left_grid_pin_48_ ( grid_clb_2_right_width_0_height_0__pin_48_upper ) , - .bottom_left_grid_pin_49_ ( grid_clb_2_right_width_0_height_0__pin_49_upper ) , - .chanx_left_in ( cbx_1__1__1_chanx_right_out ) , - .left_bottom_grid_pin_34_ ( grid_clb_2_top_width_0_height_0__pin_34_lower ) , - .left_bottom_grid_pin_35_ ( grid_clb_2_top_width_0_height_0__pin_35_lower ) , - .left_bottom_grid_pin_36_ ( grid_clb_2_top_width_0_height_0__pin_36_lower ) , - .left_bottom_grid_pin_37_ ( grid_clb_2_top_width_0_height_0__pin_37_lower ) , - .left_bottom_grid_pin_38_ ( grid_clb_2_top_width_0_height_0__pin_38_lower ) , - .left_bottom_grid_pin_39_ ( grid_clb_2_top_width_0_height_0__pin_39_lower ) , - .left_bottom_grid_pin_40_ ( grid_clb_2_top_width_0_height_0__pin_40_lower ) , - .left_bottom_grid_pin_41_ ( grid_clb_2_top_width_0_height_0__pin_41_lower ) , - .ccff_head ( grid_io_right_1_ccff_tail ) , - .chany_top_out ( sb_2__1__0_chany_top_out ) , - .chany_bottom_out ( sb_2__1__0_chany_bottom_out ) , - .chanx_left_out ( sb_2__1__0_chanx_left_out ) , - .ccff_tail ( sb_2__1__0_ccff_tail ) , - .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_2 ) , - .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_3 ) , - .clk__FEEDTHRU_0 ( clk__FEEDTHRU_2 ) , - .clk__FEEDTHRU_1 ( clk__FEEDTHRU_3 ) ) ; -sb_2__2_ sb_2__2_ ( .prog_clk ( prog_clk__FEEDTHRU_14 ) , - .chany_bottom_in ( cby_2__1__1_chany_top_out ) , - .bottom_right_grid_pin_1_ ( grid_io_right_1_left_width_0_height_0__pin_1_upper ) , - .bottom_left_grid_pin_42_ ( grid_clb_3_right_width_0_height_0__pin_42_upper ) , - .bottom_left_grid_pin_43_ ( grid_clb_3_right_width_0_height_0__pin_43_upper ) , - .bottom_left_grid_pin_44_ ( grid_clb_3_right_width_0_height_0__pin_44_upper ) , - .bottom_left_grid_pin_45_ ( grid_clb_3_right_width_0_height_0__pin_45_upper ) , - .bottom_left_grid_pin_46_ ( grid_clb_3_right_width_0_height_0__pin_46_upper ) , - .bottom_left_grid_pin_47_ ( grid_clb_3_right_width_0_height_0__pin_47_upper ) , - .bottom_left_grid_pin_48_ ( grid_clb_3_right_width_0_height_0__pin_48_upper ) , - .bottom_left_grid_pin_49_ ( grid_clb_3_right_width_0_height_0__pin_49_upper ) , - .chanx_left_in ( cbx_1__2__1_chanx_right_out ) , - .left_top_grid_pin_1_ ( grid_io_top_1_bottom_width_0_height_0__pin_1_lower ) , - .left_bottom_grid_pin_34_ ( grid_clb_3_top_width_0_height_0__pin_34_lower ) , - .left_bottom_grid_pin_35_ ( grid_clb_3_top_width_0_height_0__pin_35_lower ) , - .left_bottom_grid_pin_36_ ( grid_clb_3_top_width_0_height_0__pin_36_lower ) , - .left_bottom_grid_pin_37_ ( grid_clb_3_top_width_0_height_0__pin_37_lower ) , - .left_bottom_grid_pin_38_ ( grid_clb_3_top_width_0_height_0__pin_38_lower ) , - .left_bottom_grid_pin_39_ ( grid_clb_3_top_width_0_height_0__pin_39_lower ) , - .left_bottom_grid_pin_40_ ( grid_clb_3_top_width_0_height_0__pin_40_lower ) , - .left_bottom_grid_pin_41_ ( grid_clb_3_top_width_0_height_0__pin_41_lower ) , - .ccff_head ( ccff_head ) , - .chany_bottom_out ( sb_2__2__0_chany_bottom_out ) , - .chanx_left_out ( sb_2__2__0_chanx_left_out ) , - .ccff_tail ( sb_2__2__0_ccff_tail ) , .SC_IN_TOP ( scff_Wires_12_ ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_38 ) , .SC_OUT_TOP ( sc_tail ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_39 ) ) ; -cbx_1__0_ cbx_1__0_ ( - .prog_clk ( { ctsbuf_net_2426 } ) , - .chanx_left_in ( sb_0__0__0_chanx_right_out ) , - .chanx_right_in ( sb_1__0__0_chanx_left_out ) , - .ccff_head ( sb_1__0__0_ccff_tail ) , - .chanx_left_out ( cbx_1__0__0_chanx_left_out ) , - .chanx_right_out ( cbx_1__0__0_chanx_right_out ) , - .bottom_grid_pin_0_ ( cbx_1__0__0_bottom_grid_pin_0_ ) , - .bottom_grid_pin_2_ ( cbx_1__0__0_bottom_grid_pin_2_ ) , - .bottom_grid_pin_4_ ( cbx_1__0__0_bottom_grid_pin_4_ ) , - .bottom_grid_pin_6_ ( cbx_1__0__0_bottom_grid_pin_6_ ) , - .bottom_grid_pin_8_ ( cbx_1__0__0_bottom_grid_pin_8_ ) , - .bottom_grid_pin_10_ ( cbx_1__0__0_bottom_grid_pin_10_ ) , - .ccff_tail ( grid_io_bottom_0_ccff_tail ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[4:9] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[4:9] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[4:9] ) , - .top_width_0_height_0__pin_0_ ( cbx_1__0__0_bottom_grid_pin_0_ ) , - .top_width_0_height_0__pin_2_ ( cbx_1__0__0_bottom_grid_pin_2_ ) , - .top_width_0_height_0__pin_4_ ( cbx_1__0__0_bottom_grid_pin_4_ ) , - .top_width_0_height_0__pin_6_ ( cbx_1__0__0_bottom_grid_pin_6_ ) , - .top_width_0_height_0__pin_8_ ( cbx_1__0__0_bottom_grid_pin_8_ ) , - .top_width_0_height_0__pin_10_ ( cbx_1__0__0_bottom_grid_pin_10_ ) , - .top_width_0_height_0__pin_1_upper ( grid_io_bottom_0_top_width_0_height_0__pin_1_upper ) , - .top_width_0_height_0__pin_1_lower ( grid_io_bottom_0_top_width_0_height_0__pin_1_lower ) , - .top_width_0_height_0__pin_3_upper ( grid_io_bottom_0_top_width_0_height_0__pin_3_upper ) , - .top_width_0_height_0__pin_3_lower ( grid_io_bottom_0_top_width_0_height_0__pin_3_lower ) , - .top_width_0_height_0__pin_5_upper ( grid_io_bottom_0_top_width_0_height_0__pin_5_upper ) , - .top_width_0_height_0__pin_5_lower ( grid_io_bottom_0_top_width_0_height_0__pin_5_lower ) , - .top_width_0_height_0__pin_7_upper ( grid_io_bottom_0_top_width_0_height_0__pin_7_upper ) , - .top_width_0_height_0__pin_7_lower ( grid_io_bottom_0_top_width_0_height_0__pin_7_lower ) , - .top_width_0_height_0__pin_9_upper ( grid_io_bottom_0_top_width_0_height_0__pin_9_upper ) , - .top_width_0_height_0__pin_9_lower ( grid_io_bottom_0_top_width_0_height_0__pin_9_lower ) , - .top_width_0_height_0__pin_11_upper ( grid_io_bottom_0_top_width_0_height_0__pin_11_upper ) , - .top_width_0_height_0__pin_11_lower ( grid_io_bottom_0_top_width_0_height_0__pin_11_lower ) , - .SC_IN_TOP ( scff_Wires_5_ ) , .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_40 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_41 ) , .SC_OUT_BOT ( scff_Wires_6_ ) , - .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_2 ) ) ; -cbx_1__0_ cbx_2__0_ ( - .prog_clk ( { ctsbuf_net_2729 } ) , - .chanx_left_in ( sb_1__0__0_chanx_right_out ) , - .chanx_right_in ( sb_2__0__0_chanx_left_out ) , - .ccff_head ( sb_2__0__0_ccff_tail ) , - .chanx_left_out ( cbx_1__0__1_chanx_left_out ) , - .chanx_right_out ( cbx_1__0__1_chanx_right_out ) , - .bottom_grid_pin_0_ ( cbx_1__0__1_bottom_grid_pin_0_ ) , - .bottom_grid_pin_2_ ( cbx_1__0__1_bottom_grid_pin_2_ ) , - .bottom_grid_pin_4_ ( cbx_1__0__1_bottom_grid_pin_4_ ) , - .bottom_grid_pin_6_ ( cbx_1__0__1_bottom_grid_pin_6_ ) , - .bottom_grid_pin_8_ ( cbx_1__0__1_bottom_grid_pin_8_ ) , - .bottom_grid_pin_10_ ( cbx_1__0__1_bottom_grid_pin_10_ ) , - .ccff_tail ( grid_io_bottom_1_ccff_tail ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[10:15] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[10:15] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[10:15] ) , - .top_width_0_height_0__pin_0_ ( cbx_1__0__1_bottom_grid_pin_0_ ) , - .top_width_0_height_0__pin_2_ ( cbx_1__0__1_bottom_grid_pin_2_ ) , - .top_width_0_height_0__pin_4_ ( cbx_1__0__1_bottom_grid_pin_4_ ) , - .top_width_0_height_0__pin_6_ ( cbx_1__0__1_bottom_grid_pin_6_ ) , - .top_width_0_height_0__pin_8_ ( cbx_1__0__1_bottom_grid_pin_8_ ) , - .top_width_0_height_0__pin_10_ ( cbx_1__0__1_bottom_grid_pin_10_ ) , - .top_width_0_height_0__pin_1_upper ( grid_io_bottom_1_top_width_0_height_0__pin_1_upper ) , - .top_width_0_height_0__pin_1_lower ( grid_io_bottom_1_top_width_0_height_0__pin_1_lower ) , - .top_width_0_height_0__pin_3_upper ( grid_io_bottom_1_top_width_0_height_0__pin_3_upper ) , - .top_width_0_height_0__pin_3_lower ( grid_io_bottom_1_top_width_0_height_0__pin_3_lower ) , - .top_width_0_height_0__pin_5_upper ( grid_io_bottom_1_top_width_0_height_0__pin_5_upper ) , - .top_width_0_height_0__pin_5_lower ( grid_io_bottom_1_top_width_0_height_0__pin_5_lower ) , - .top_width_0_height_0__pin_7_upper ( grid_io_bottom_1_top_width_0_height_0__pin_7_upper ) , - .top_width_0_height_0__pin_7_lower ( grid_io_bottom_1_top_width_0_height_0__pin_7_lower ) , - .top_width_0_height_0__pin_9_upper ( grid_io_bottom_1_top_width_0_height_0__pin_9_upper ) , - .top_width_0_height_0__pin_9_lower ( grid_io_bottom_1_top_width_0_height_0__pin_9_lower ) , - .top_width_0_height_0__pin_11_upper ( grid_io_bottom_1_top_width_0_height_0__pin_11_upper ) , - .top_width_0_height_0__pin_11_lower ( grid_io_bottom_1_top_width_0_height_0__pin_11_lower ) , - .SC_IN_TOP ( scff_Wires_7_ ) , .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_42 ) , - .SC_OUT_TOP ( scff_Wires_8_ ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_43 ) , - .prog_clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_44 } ) ) ; -cbx_1__1_ cbx_1__1_ ( .prog_clk ( prog_clk__FEEDTHRU_3 ) , - .chanx_left_in ( sb_0__1__0_chanx_right_out ) , - .chanx_right_in ( sb_1__1__0_chanx_left_out ) , - .ccff_head ( sb_1__1__0_ccff_tail ) , - .chanx_left_out ( cbx_1__1__0_chanx_left_out ) , - .chanx_right_out ( cbx_1__1__0_chanx_right_out ) , - .bottom_grid_pin_0_ ( cbx_1__1__0_bottom_grid_pin_0_ ) , - .bottom_grid_pin_1_ ( cbx_1__1__0_bottom_grid_pin_1_ ) , - .bottom_grid_pin_2_ ( cbx_1__1__0_bottom_grid_pin_2_ ) , - .bottom_grid_pin_3_ ( cbx_1__1__0_bottom_grid_pin_3_ ) , - .bottom_grid_pin_4_ ( cbx_1__1__0_bottom_grid_pin_4_ ) , - .bottom_grid_pin_5_ ( cbx_1__1__0_bottom_grid_pin_5_ ) , - .bottom_grid_pin_6_ ( cbx_1__1__0_bottom_grid_pin_6_ ) , - .bottom_grid_pin_7_ ( cbx_1__1__0_bottom_grid_pin_7_ ) , - .bottom_grid_pin_8_ ( cbx_1__1__0_bottom_grid_pin_8_ ) , - .bottom_grid_pin_9_ ( cbx_1__1__0_bottom_grid_pin_9_ ) , - .bottom_grid_pin_10_ ( cbx_1__1__0_bottom_grid_pin_10_ ) , - .bottom_grid_pin_11_ ( cbx_1__1__0_bottom_grid_pin_11_ ) , - .bottom_grid_pin_12_ ( cbx_1__1__0_bottom_grid_pin_12_ ) , - .bottom_grid_pin_13_ ( cbx_1__1__0_bottom_grid_pin_13_ ) , - .bottom_grid_pin_14_ ( cbx_1__1__0_bottom_grid_pin_14_ ) , - .bottom_grid_pin_15_ ( cbx_1__1__0_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__0_ccff_tail ) , .SC_IN_TOP ( scff_Wires_2_ ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_45 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_46 ) , .SC_OUT_BOT ( scff_Wires_3_ ) , - .prog_clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_47 } ) ) ; -cbx_1__1_ cbx_2__1_ ( .prog_clk ( prog_clk__FEEDTHRU_17 ) , - .chanx_left_in ( sb_1__1__0_chanx_right_out ) , - .chanx_right_in ( sb_2__1__0_chanx_left_out ) , - .ccff_head ( sb_2__1__0_ccff_tail ) , - .chanx_left_out ( cbx_1__1__1_chanx_left_out ) , - .chanx_right_out ( cbx_1__1__1_chanx_right_out ) , - .bottom_grid_pin_0_ ( cbx_1__1__1_bottom_grid_pin_0_ ) , - .bottom_grid_pin_1_ ( cbx_1__1__1_bottom_grid_pin_1_ ) , - .bottom_grid_pin_2_ ( cbx_1__1__1_bottom_grid_pin_2_ ) , - .bottom_grid_pin_3_ ( cbx_1__1__1_bottom_grid_pin_3_ ) , - .bottom_grid_pin_4_ ( cbx_1__1__1_bottom_grid_pin_4_ ) , - .bottom_grid_pin_5_ ( cbx_1__1__1_bottom_grid_pin_5_ ) , - .bottom_grid_pin_6_ ( cbx_1__1__1_bottom_grid_pin_6_ ) , - .bottom_grid_pin_7_ ( cbx_1__1__1_bottom_grid_pin_7_ ) , - .bottom_grid_pin_8_ ( cbx_1__1__1_bottom_grid_pin_8_ ) , - .bottom_grid_pin_9_ ( cbx_1__1__1_bottom_grid_pin_9_ ) , - .bottom_grid_pin_10_ ( cbx_1__1__1_bottom_grid_pin_10_ ) , - .bottom_grid_pin_11_ ( cbx_1__1__1_bottom_grid_pin_11_ ) , - .bottom_grid_pin_12_ ( cbx_1__1__1_bottom_grid_pin_12_ ) , - .bottom_grid_pin_13_ ( cbx_1__1__1_bottom_grid_pin_13_ ) , - .bottom_grid_pin_14_ ( cbx_1__1__1_bottom_grid_pin_14_ ) , - .bottom_grid_pin_15_ ( cbx_1__1__1_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__1_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_48 ) , .SC_IN_BOT ( scff_Wires_9_ ) , - .SC_OUT_TOP ( scff_Wires_10_ ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_49 ) , - .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_18 ) ) ; -cbx_1__2_ cbx_1__2_ ( .prog_clk ( prog_clk__FEEDTHRU_6 ) , - .chanx_left_in ( sb_0__2__0_chanx_right_out ) , - .chanx_right_in ( sb_1__2__0_chanx_left_out ) , - .ccff_head ( sb_1__2__0_ccff_tail ) , - .chanx_left_out ( cbx_1__2__0_chanx_left_out ) , - .chanx_right_out ( cbx_1__2__0_chanx_right_out ) , - .top_grid_pin_0_ ( cbx_1__2__0_top_grid_pin_0_ ) , - .bottom_grid_pin_0_ ( cbx_1__2__0_bottom_grid_pin_0_ ) , - .bottom_grid_pin_1_ ( cbx_1__2__0_bottom_grid_pin_1_ ) , - .bottom_grid_pin_2_ ( cbx_1__2__0_bottom_grid_pin_2_ ) , - .bottom_grid_pin_3_ ( cbx_1__2__0_bottom_grid_pin_3_ ) , - .bottom_grid_pin_4_ ( cbx_1__2__0_bottom_grid_pin_4_ ) , - .bottom_grid_pin_5_ ( cbx_1__2__0_bottom_grid_pin_5_ ) , - .bottom_grid_pin_6_ ( cbx_1__2__0_bottom_grid_pin_6_ ) , - .bottom_grid_pin_7_ ( cbx_1__2__0_bottom_grid_pin_7_ ) , - .bottom_grid_pin_8_ ( cbx_1__2__0_bottom_grid_pin_8_ ) , - .bottom_grid_pin_9_ ( cbx_1__2__0_bottom_grid_pin_9_ ) , - .bottom_grid_pin_10_ ( cbx_1__2__0_bottom_grid_pin_10_ ) , - .bottom_grid_pin_11_ ( cbx_1__2__0_bottom_grid_pin_11_ ) , - .bottom_grid_pin_12_ ( cbx_1__2__0_bottom_grid_pin_12_ ) , - .bottom_grid_pin_13_ ( cbx_1__2__0_bottom_grid_pin_13_ ) , - .bottom_grid_pin_14_ ( cbx_1__2__0_bottom_grid_pin_14_ ) , - .bottom_grid_pin_15_ ( cbx_1__2__0_bottom_grid_pin_15_ ) , - .ccff_tail ( grid_io_top_0_ccff_tail ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , - .bottom_width_0_height_0__pin_0_ ( cbx_1__2__0_top_grid_pin_0_ ) , - .bottom_width_0_height_0__pin_1_upper ( grid_io_top_0_bottom_width_0_height_0__pin_1_upper ) , - .bottom_width_0_height_0__pin_1_lower ( grid_io_top_0_bottom_width_0_height_0__pin_1_lower ) , - .SC_IN_TOP ( scff_Wires_0_ ) , .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_50 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_51 ) , .SC_OUT_BOT ( scff_Wires_1_ ) , - .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_7 ) , - .prog_clk__FEEDTHRU_2 ( { SYNOPSYS_UNCONNECTED_52 } ) ) ; -cbx_1__2_ cbx_2__2_ ( .prog_clk ( prog_clk__FEEDTHRU_13 ) , - .chanx_left_in ( sb_1__2__0_chanx_right_out ) , - .chanx_right_in ( sb_2__2__0_chanx_left_out ) , - .ccff_head ( sb_2__2__0_ccff_tail ) , - .chanx_left_out ( cbx_1__2__1_chanx_left_out ) , - .chanx_right_out ( cbx_1__2__1_chanx_right_out ) , - .top_grid_pin_0_ ( cbx_1__2__1_top_grid_pin_0_ ) , - .bottom_grid_pin_0_ ( cbx_1__2__1_bottom_grid_pin_0_ ) , - .bottom_grid_pin_1_ ( cbx_1__2__1_bottom_grid_pin_1_ ) , - .bottom_grid_pin_2_ ( cbx_1__2__1_bottom_grid_pin_2_ ) , - .bottom_grid_pin_3_ ( cbx_1__2__1_bottom_grid_pin_3_ ) , - .bottom_grid_pin_4_ ( cbx_1__2__1_bottom_grid_pin_4_ ) , - .bottom_grid_pin_5_ ( cbx_1__2__1_bottom_grid_pin_5_ ) , - .bottom_grid_pin_6_ ( cbx_1__2__1_bottom_grid_pin_6_ ) , - .bottom_grid_pin_7_ ( cbx_1__2__1_bottom_grid_pin_7_ ) , - .bottom_grid_pin_8_ ( cbx_1__2__1_bottom_grid_pin_8_ ) , - .bottom_grid_pin_9_ ( cbx_1__2__1_bottom_grid_pin_9_ ) , - .bottom_grid_pin_10_ ( cbx_1__2__1_bottom_grid_pin_10_ ) , - .bottom_grid_pin_11_ ( cbx_1__2__1_bottom_grid_pin_11_ ) , - .bottom_grid_pin_12_ ( cbx_1__2__1_bottom_grid_pin_12_ ) , - .bottom_grid_pin_13_ ( cbx_1__2__1_bottom_grid_pin_13_ ) , - .bottom_grid_pin_14_ ( cbx_1__2__1_bottom_grid_pin_14_ ) , - .bottom_grid_pin_15_ ( cbx_1__2__1_bottom_grid_pin_15_ ) , - .ccff_tail ( grid_io_top_1_ccff_tail ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[1] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[1] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[1] ) , - .bottom_width_0_height_0__pin_0_ ( cbx_1__2__1_top_grid_pin_0_ ) , - .bottom_width_0_height_0__pin_1_upper ( grid_io_top_1_bottom_width_0_height_0__pin_1_upper ) , - .bottom_width_0_height_0__pin_1_lower ( grid_io_top_1_bottom_width_0_height_0__pin_1_lower ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_53 ) , .SC_IN_BOT ( scff_Wires_11_ ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_54 ) , .SC_OUT_BOT ( scff_Wires_12_ ) , - .prog_clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_55 } ) , - .prog_clk__FEEDTHRU_2 ( prog_clk__FEEDTHRU_14 ) ) ; -cby_0__1_ cby_0__1_ ( - .prog_clk ( { ctsbuf_net_1719 } ) , - .chany_bottom_in ( sb_0__0__0_chany_top_out ) , - .chany_top_in ( sb_0__1__0_chany_bottom_out ) , - .ccff_head ( sb_0__1__0_ccff_tail ) , - .chany_bottom_out ( cby_0__1__0_chany_bottom_out ) , - .chany_top_out ( cby_0__1__0_chany_top_out ) , - .left_grid_pin_0_ ( cby_0__1__0_left_grid_pin_0_ ) , - .ccff_tail ( grid_io_left_0_ccff_tail ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[16] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[16] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[16] ) , - .right_width_0_height_0__pin_0_ ( cby_0__1__0_left_grid_pin_0_ ) , - .right_width_0_height_0__pin_1_upper ( grid_io_left_0_right_width_0_height_0__pin_1_upper ) , - .right_width_0_height_0__pin_1_lower ( grid_io_left_0_right_width_0_height_0__pin_1_lower ) ) ; -cby_0__1_ cby_0__2_ ( .prog_clk ( prog_clk__FEEDTHRU_5 ) , - .chany_bottom_in ( sb_0__1__0_chany_top_out ) , - .chany_top_in ( sb_0__2__0_chany_bottom_out ) , - .ccff_head ( sb_0__2__0_ccff_tail ) , - .chany_bottom_out ( cby_0__1__1_chany_bottom_out ) , - .chany_top_out ( cby_0__1__1_chany_top_out ) , - .left_grid_pin_0_ ( cby_0__1__1_left_grid_pin_0_ ) , - .ccff_tail ( grid_io_left_1_ccff_tail ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[17] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[17] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[17] ) , - .right_width_0_height_0__pin_0_ ( cby_0__1__1_left_grid_pin_0_ ) , - .right_width_0_height_0__pin_1_upper ( grid_io_left_1_right_width_0_height_0__pin_1_upper ) , - .right_width_0_height_0__pin_1_lower ( grid_io_left_1_right_width_0_height_0__pin_1_lower ) ) ; -cby_1__1_ cby_1__1_ ( - .prog_clk ( { ctsbuf_net_2325 } ) , - .chany_bottom_in ( sb_1__0__0_chany_top_out ) , - .chany_top_in ( sb_1__1__0_chany_bottom_out ) , - .ccff_head ( grid_clb_0_ccff_tail ) , - .chany_bottom_out ( cby_1__1__0_chany_bottom_out ) , - .chany_top_out ( cby_1__1__0_chany_top_out ) , - .left_grid_pin_16_ ( cby_1__1__0_left_grid_pin_16_ ) , - .left_grid_pin_17_ ( cby_1__1__0_left_grid_pin_17_ ) , - .left_grid_pin_18_ ( cby_1__1__0_left_grid_pin_18_ ) , - .left_grid_pin_19_ ( cby_1__1__0_left_grid_pin_19_ ) , - .left_grid_pin_20_ ( cby_1__1__0_left_grid_pin_20_ ) , - .left_grid_pin_21_ ( cby_1__1__0_left_grid_pin_21_ ) , - .left_grid_pin_22_ ( cby_1__1__0_left_grid_pin_22_ ) , - .left_grid_pin_23_ ( cby_1__1__0_left_grid_pin_23_ ) , - .left_grid_pin_24_ ( cby_1__1__0_left_grid_pin_24_ ) , - .left_grid_pin_25_ ( cby_1__1__0_left_grid_pin_25_ ) , - .left_grid_pin_26_ ( cby_1__1__0_left_grid_pin_26_ ) , - .left_grid_pin_27_ ( cby_1__1__0_left_grid_pin_27_ ) , - .left_grid_pin_28_ ( cby_1__1__0_left_grid_pin_28_ ) , - .left_grid_pin_29_ ( cby_1__1__0_left_grid_pin_29_ ) , - .left_grid_pin_30_ ( cby_1__1__0_left_grid_pin_30_ ) , - .left_grid_pin_31_ ( cby_1__1__0_left_grid_pin_31_ ) , - .ccff_tail ( cby_1__1__0_ccff_tail ) , - .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_16 ) , - .prog_clk__FEEDTHRU_2 ( prog_clk__FEEDTHRU_9 ) ) ; -cby_1__1_ cby_1__2_ ( .prog_clk ( prog_clk__FEEDTHRU_10 ) , - .chany_bottom_in ( sb_1__1__0_chany_top_out ) , - .chany_top_in ( sb_1__2__0_chany_bottom_out ) , - .ccff_head ( grid_clb_1_ccff_tail ) , - .chany_bottom_out ( cby_1__1__1_chany_bottom_out ) , - .chany_top_out ( cby_1__1__1_chany_top_out ) , - .left_grid_pin_16_ ( cby_1__1__1_left_grid_pin_16_ ) , - .left_grid_pin_17_ ( cby_1__1__1_left_grid_pin_17_ ) , - .left_grid_pin_18_ ( cby_1__1__1_left_grid_pin_18_ ) , - .left_grid_pin_19_ ( cby_1__1__1_left_grid_pin_19_ ) , - .left_grid_pin_20_ ( cby_1__1__1_left_grid_pin_20_ ) , - .left_grid_pin_21_ ( cby_1__1__1_left_grid_pin_21_ ) , - .left_grid_pin_22_ ( cby_1__1__1_left_grid_pin_22_ ) , - .left_grid_pin_23_ ( cby_1__1__1_left_grid_pin_23_ ) , - .left_grid_pin_24_ ( cby_1__1__1_left_grid_pin_24_ ) , - .left_grid_pin_25_ ( cby_1__1__1_left_grid_pin_25_ ) , - .left_grid_pin_26_ ( cby_1__1__1_left_grid_pin_26_ ) , - .left_grid_pin_27_ ( cby_1__1__1_left_grid_pin_27_ ) , - .left_grid_pin_28_ ( cby_1__1__1_left_grid_pin_28_ ) , - .left_grid_pin_29_ ( cby_1__1__1_left_grid_pin_29_ ) , - .left_grid_pin_30_ ( cby_1__1__1_left_grid_pin_30_ ) , - .left_grid_pin_31_ ( cby_1__1__1_left_grid_pin_31_ ) , - .ccff_tail ( cby_1__1__1_ccff_tail ) , - .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_12 ) , - .prog_clk__FEEDTHRU_2 ( prog_clk__FEEDTHRU_11 ) ) ; -cby_2__1_ cby_2__1_ ( .prog_clk ( prog_clk__FEEDTHRU_19 ) , - .chany_bottom_in ( sb_2__0__0_chany_top_out ) , - .chany_top_in ( sb_2__1__0_chany_bottom_out ) , - .ccff_head ( grid_clb_2_ccff_tail ) , - .chany_bottom_out ( cby_2__1__0_chany_bottom_out ) , - .chany_top_out ( cby_2__1__0_chany_top_out ) , - .right_grid_pin_0_ ( cby_2__1__0_right_grid_pin_0_ ) , - .left_grid_pin_16_ ( cby_2__1__0_left_grid_pin_16_ ) , - .left_grid_pin_17_ ( cby_2__1__0_left_grid_pin_17_ ) , - .left_grid_pin_18_ ( cby_2__1__0_left_grid_pin_18_ ) , - .left_grid_pin_19_ ( cby_2__1__0_left_grid_pin_19_ ) , - .left_grid_pin_20_ ( cby_2__1__0_left_grid_pin_20_ ) , - .left_grid_pin_21_ ( cby_2__1__0_left_grid_pin_21_ ) , - .left_grid_pin_22_ ( cby_2__1__0_left_grid_pin_22_ ) , - .left_grid_pin_23_ ( cby_2__1__0_left_grid_pin_23_ ) , - .left_grid_pin_24_ ( cby_2__1__0_left_grid_pin_24_ ) , - .left_grid_pin_25_ ( cby_2__1__0_left_grid_pin_25_ ) , - .left_grid_pin_26_ ( cby_2__1__0_left_grid_pin_26_ ) , - .left_grid_pin_27_ ( cby_2__1__0_left_grid_pin_27_ ) , - .left_grid_pin_28_ ( cby_2__1__0_left_grid_pin_28_ ) , - .left_grid_pin_29_ ( cby_2__1__0_left_grid_pin_29_ ) , - .left_grid_pin_30_ ( cby_2__1__0_left_grid_pin_30_ ) , - .left_grid_pin_31_ ( cby_2__1__0_left_grid_pin_31_ ) , - .ccff_tail ( grid_io_right_0_ccff_tail ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[2] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[2] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[2] ) , - .left_width_0_height_0__pin_0_ ( cby_2__1__0_right_grid_pin_0_ ) , - .left_width_0_height_0__pin_1_upper ( grid_io_right_0_left_width_0_height_0__pin_1_upper ) , - .left_width_0_height_0__pin_1_lower ( grid_io_right_0_left_width_0_height_0__pin_1_lower ) ) ; -cby_2__1_ cby_2__2_ ( - .prog_clk ( { ctsbuf_net_24 } ) , - .chany_bottom_in ( sb_2__1__0_chany_top_out ) , - .chany_top_in ( sb_2__2__0_chany_bottom_out ) , - .ccff_head ( grid_clb_3_ccff_tail ) , - .chany_bottom_out ( cby_2__1__1_chany_bottom_out ) , - .chany_top_out ( cby_2__1__1_chany_top_out ) , - .right_grid_pin_0_ ( cby_2__1__1_right_grid_pin_0_ ) , - .left_grid_pin_16_ ( cby_2__1__1_left_grid_pin_16_ ) , - .left_grid_pin_17_ ( cby_2__1__1_left_grid_pin_17_ ) , - .left_grid_pin_18_ ( cby_2__1__1_left_grid_pin_18_ ) , - .left_grid_pin_19_ ( cby_2__1__1_left_grid_pin_19_ ) , - .left_grid_pin_20_ ( cby_2__1__1_left_grid_pin_20_ ) , - .left_grid_pin_21_ ( cby_2__1__1_left_grid_pin_21_ ) , - .left_grid_pin_22_ ( cby_2__1__1_left_grid_pin_22_ ) , - .left_grid_pin_23_ ( cby_2__1__1_left_grid_pin_23_ ) , - .left_grid_pin_24_ ( cby_2__1__1_left_grid_pin_24_ ) , - .left_grid_pin_25_ ( cby_2__1__1_left_grid_pin_25_ ) , - .left_grid_pin_26_ ( cby_2__1__1_left_grid_pin_26_ ) , - .left_grid_pin_27_ ( cby_2__1__1_left_grid_pin_27_ ) , - .left_grid_pin_28_ ( cby_2__1__1_left_grid_pin_28_ ) , - .left_grid_pin_29_ ( cby_2__1__1_left_grid_pin_29_ ) , - .left_grid_pin_30_ ( cby_2__1__1_left_grid_pin_30_ ) , - .left_grid_pin_31_ ( cby_2__1__1_left_grid_pin_31_ ) , - .ccff_tail ( grid_io_right_1_ccff_tail ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[3] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[3] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[3] ) , - .left_width_0_height_0__pin_0_ ( cby_2__1__1_right_grid_pin_0_ ) , - .left_width_0_height_0__pin_1_upper ( grid_io_right_1_left_width_0_height_0__pin_1_upper ) , - .left_width_0_height_0__pin_1_lower ( grid_io_right_1_left_width_0_height_0__pin_1_lower ) ) ; -direct_interc_0 direct_interc_0_ ( - .in ( grid_clb_1_bottom_width_0_height_0__pin_50_ ) , - .out ( direct_interc_0_out ) ) ; -direct_interc_1 direct_interc_1_ ( - .in ( grid_clb_3_bottom_width_0_height_0__pin_50_ ) , - .out ( direct_interc_1_out ) ) ; -direct_interc_2 direct_interc_2_ ( - .in ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) , - .out ( direct_interc_2_out ) ) ; -sky130_fd_sc_hd__clkinv_2 cts_inv_80028275 ( .A ( ctsbuf_net_46 ) , - .Y ( ctsbuf_net_24 ) ) ; -sky130_fd_sc_hd__inv_1 cts_inv_80108283 ( .A ( prog_clk__FEEDTHRU_15[0] ) , - .Y ( ctsbuf_net_46 ) ) ; -sky130_fd_sc_hd__inv_6 cts_inv_80408313 ( .A ( ctsbuf_net_1214 ) , - .Y ( ctsbuf_net_1113 ) ) ; -sky130_fd_sc_hd__inv_1 cts_inv_80448317 ( .A ( prog_clk__FEEDTHRU_5[0] ) , - .Y ( ctsbuf_net_1214 ) ) ; -sky130_fd_sc_hd__clkinv_16 cts_inv_80538326 ( .A ( ctsbuf_net_1416 ) , - .Y ( ctsbuf_net_1315 ) ) ; -sky130_fd_sc_hd__inv_2 cts_inv_80578330 ( .A ( prog_clk__FEEDTHRU_12[0] ) , - .Y ( ctsbuf_net_1416 ) ) ; -sky130_fd_sc_hd__clkinv_2 cts_inv_80898362 ( .A ( ctsbuf_net_1820 ) , - .Y ( ctsbuf_net_1719 ) ) ; -sky130_fd_sc_hd__inv_1 cts_inv_80938366 ( .A ( prog_clk__FEEDTHRU_2[0] ) , - .Y ( ctsbuf_net_1820 ) ) ; -sky130_fd_sc_hd__clkinv_16 cts_inv_80978370 ( .A ( ctsbuf_net_2022 ) , - .Y ( ctsbuf_net_1921 ) ) ; -sky130_fd_sc_hd__inv_2 cts_inv_81018374 ( .A ( prog_clk__FEEDTHRU_2[0] ) , - .Y ( ctsbuf_net_2022 ) ) ; -sky130_fd_sc_hd__clkinv_16 cts_inv_81108383 ( .A ( ctsbuf_net_2224 ) , - .Y ( ctsbuf_net_2123 ) ) ; -sky130_fd_sc_hd__inv_2 cts_inv_81148387 ( .A ( prog_clk__FEEDTHRU_9[0] ) , - .Y ( ctsbuf_net_2224 ) ) ; -sky130_fd_sc_hd__clkinv_8 cts_inv_81198392 ( .A ( ctsbuf_net_2527 ) , - .Y ( ctsbuf_net_2325 ) ) ; -sky130_fd_sc_hd__inv_4 cts_inv_81238396 ( .A ( ctsbuf_net_2628 ) , - .Y ( ctsbuf_net_2426 ) ) ; -sky130_fd_sc_hd__inv_2 cts_inv_81278400 ( .A ( prog_clk__FEEDTHRU_8[0] ) , - .Y ( ctsbuf_net_2527 ) ) ; -sky130_fd_sc_hd__inv_1 cts_inv_81318404 ( .A ( prog_clk__FEEDTHRU_1[0] ) , - .Y ( ctsbuf_net_2628 ) ) ; -sky130_fd_sc_hd__inv_4 cts_inv_81368409 ( .A ( ctsbuf_net_2830 ) , - .Y ( ctsbuf_net_2729 ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_81408413 ( .A ( prog_clk[0] ) , - .Y ( ctsbuf_net_2830 ) ) ; -endmodule - - diff --git a/FPGA22_HIER_SKY_PNR/fpga_core/rpts_icc2/module_utilization.tsv b/FPGA22_HIER_SKY_PNR/fpga_core/rpts_icc2/module_utilization.tsv deleted file mode 100644 index 5a12b1a..0000000 --- a/FPGA22_HIER_SKY_PNR/fpga_core/rpts_icc2/module_utilization.tsv +++ /dev/null @@ -1,18 +0,0 @@ -| Module | Util| Area| Sites| Insts| Std_Cells -|--------------------|----------|-----------------|-------|-------|------- -| sb_0__0_ | 24.99 | 8728.371200 | 6976 | 1 | 78 -| sb_0__1_ | 48.87 | 9449.062400 | 7552 | 1 | 127 -| sb_0__2_ | 29.93 | 8728.371200 | 6976 | 1 | 88 -| sb_1__0_ | 44.23 | 10970.521600 | 8768 | 1 | 135 -| sb_1__1_ | 65.73 | 11691.212800 | 9344 | 1 | 181 -| sb_1__2_ | 47.88 | 10970.521600 | 8768 | 1 | 145 -| sb_2__0_ | 36.31 | 8728.371200 | 6976 | 1 | 95 -| sb_2__1_ | 58.37 | 9449.062400 | 7552 | 1 | 146 -| sb_2__2_ | 39.94 | 8728.371200 | 6976 | 1 | 89 -| cbx_1__0_ | 56.73 | 5765.529600 | 4608 | 2 | 151 -| cbx_1__1_ | 71.12 | 5765.529600 | 4608 | 2 | 110 -| cbx_1__2_ | 74.91 | 5765.529600 | 4608 | 2 | 111 -| cby_0__1_ | 29.89 | 5044.838400 | 4032 | 2 | 103 -| cby_1__1_ | 78.17 | 5044.838400 | 4032 | 2 | 96 -| cby_2__1_ | 80.56 | 5044.838400 | 4032 | 2 | 88 -| grid_clb_1__1_ | 75.92 | 11531.059200 | 9216 | 4 | 58 diff --git a/FPGA22_HIER_SKY_PNR/fpga_core/rpts_icc2/std_cell_utilization.tsv b/FPGA22_HIER_SKY_PNR/fpga_core/rpts_icc2/std_cell_utilization.tsv deleted file mode 100644 index 69a5c64..0000000 --- a/FPGA22_HIER_SKY_PNR/fpga_core/rpts_icc2/std_cell_utilization.tsv +++ /dev/null @@ -1,32 +0,0 @@ - Ref Name Total Area Utilization_% Instance Count - ---------------------------------------------------------------------------------------------------- - sky130_fd_sc_hd__mux2_1 32960.361600 6.77 2927 - sky130_fd_sc_hd__dfxtp_1 25584.537600 5.25 1278 - sky130_fd_sc_hd__dlymetal6s2s_1 9484.096000 1.95 758 - sky130_fd_sc_hd__dlymetal6s6s_1 8896.032000 1.83 711 - sky130_fd_sc_hd__dlygate4sd3_1 6205.952000 1.27 620 - sky130_fd_sc_hd__buf_4 2695.084800 0.55 359 - sky130_fd_sc_hd__dlygate4sd2_1 1891.814400 0.39 216 - sky130_fd_sc_hd__sdfxtp_1 1681.612800 0.35 64 - sky130_fd_sc_hd__mux2_8 814.531200 0.17 31 - sky130_fd_sc_hd__inv_1 390.374400 0.08 104 - sky130_fd_sc_hd__conb_1 330.316800 0.07 88 - sky130_fd_sc_hd__dlygate4sd1_1 289.027200 0.06 33 - sky130_fd_sc_hd__buf_6 202.694400 0.04 18 - sky130_fd_sc_hd__or2_0 200.192000 0.04 32 - sky130_fd_sc_hd__buf_2 180.172800 0.04 36 - sky130_fd_sc_hd__clkinv_16 90.086400 0.02 3 - sky130_fd_sc_hd__buf_12 80.076800 0.02 4 - sky130_fd_sc_hd__buf_8 75.072000 0.02 5 - sky130_fd_sc_hd__clkbuf_1 41.289600 0.01 11 - sky130_fd_sc_hd__mux2_4 30.028800 0.01 2 - sky130_fd_sc_hd__clkinv_8 16.265600 0.00 1 - sky130_fd_sc_hd__inv_2 15.014400 0.00 4 - sky130_fd_sc_hd__inv_4 12.512000 0.00 2 - sky130_fd_sc_hd__mux2_2 11.260800 0.00 1 - sky130_fd_sc_hd__clkinv_2 10.009600 0.00 2 - sky130_fd_sc_hd__inv_6 8.758400 0.00 1 - sky130_fd_sc_hd__clkinvlp_2 5.004800 0.00 1 -FPGA_BBOX_AREA 221972.8896 -CORE_BBOX_AREA 486866.944 -FPGA_BBOX_UTIL 45.5921052632 diff --git a/FPGA22_HIER_SKY_PNR/fpga_core/rpts_icc2/timing_reports.txt b/FPGA22_HIER_SKY_PNR/fpga_core/rpts_icc2/timing_reports.txt deleted file mode 100644 index ba5fec4..0000000 --- a/FPGA22_HIER_SKY_PNR/fpga_core/rpts_icc2/timing_reports.txt +++ /dev/null @@ -1,81 +0,0 @@ -**************************************** -Report : clock timing - -type latency - -launch - -nworst 1 - -setup -Design : fpga_core -Version: P-2019.03-SP4 -Date : Mon Nov 9 18:55:42 2020 -**************************************** -Information: Timer using 'PrimeTime Delay Calculation, SI, Timing Window Analysis, AWP, CRPR'. (TIM-050) - - Mode: full_chip - Clock: CLK - - --- Latency --- - Clock Pin Trans Source Offset Network Total Corner ---------------------------------------------------------------------------------------------------- - grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/sky130_fd_sc_hd__sdfxtp_1_0_/CLK 0.175 0.000 -- 0.370 0.370 rp-+ nominal ---------------------------------------------------------------------------------------------------- - - Mode: full_chip - Clock: PROG_CLK - - --- Latency --- - Clock Pin Trans Source Offset Network Total Corner ---------------------------------------------------------------------------------------------------- - sb_0__2_/mem_right_track_20/sky130_fd_sc_hd__dfxtp_1_0_/CLK 0.352 0.000 -- 4.373 4.373 rp-+ nominal ---------------------------------------------------------------------------------------------------- -**************************************** -Report : clock timing - -type skew - -nworst 1 - -setup -Design : fpga_core -Version: P-2019.03-SP4 -Date : Mon Nov 9 18:55:42 2020 -**************************************** -Information: Timer using 'PrimeTime Delay Calculation, SI, Timing Window Analysis, AWP, CRPR'. (TIM-050) - - Mode: full_chip - Clock: CLK - - Clock Pin Latency CRP Skew Corner ---------------------------------------------------------------------------------------------------- - grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/sky130_fd_sc_hd__sdfxtp_1_0_/CLK 0.365 rp-+ nominal - grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/sky130_fd_sc_hd__sdfxtp_1_0_/CLK 0.026 0.000 0.338 rp-+ nominal - ---------------------------------------------------------------------------------------------------- - - Mode: full_chip - Clock: PROG_CLK - - Clock Pin Latency CRP Skew Corner ---------------------------------------------------------------------------------------------------- - sb_0__2_/mem_bottom_track_25/sky130_fd_sc_hd__dfxtp_1_1_/CLK 4.370 rp-+ nominal - cby_0__2_/mem_right_ipin_0/sky130_fd_sc_hd__dfxtp_1_0_/CLK 2.387 0.000 1.983 rp-+ nominal - ---------------------------------------------------------------------------------------------------- -Information: Timer using 'PrimeTime Delay Calculation, SI, Timing Window Analysis, AWP, CRPR'. (TIM-050) -**************************************** -Report : global timing - -format { narrow } -Design : fpga_core -Version: P-2019.03-SP4 -Date : Mon Nov 9 18:55:42 2020 -**************************************** - -No setup violations found. - - -Hold violations --------------------------------------------------------------- - Total reg->reg in->reg reg->out in->out --------------------------------------------------------------- -WNS -0.238 -0.238 0.000 0.000 0.000 -TNS -0.598 -0.598 0.000 0.000 0.000 -NUM 3 3 0 0 0 --------------------------------------------------------------- - -1 diff --git a/FPGA22_HIER_SKY_PNR/modules/gds/cbx_1__0__icv_in_design.gds.gz b/FPGA22_HIER_SKY_PNR/modules/gds/cbx_1__0__icv_in_design.gds.gz deleted file mode 100644 index e35cab5..0000000 Binary files a/FPGA22_HIER_SKY_PNR/modules/gds/cbx_1__0__icv_in_design.gds.gz and /dev/null differ diff --git a/FPGA22_HIER_SKY_PNR/modules/gds/cbx_1__1__icv_in_design.gds.gz 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a/FPGA22_HIER_SKY_PNR/modules/lef/cbx_1__0__icv_in_design.lef b/FPGA22_HIER_SKY_PNR/modules/lef/cbx_1__0__icv_in_design.lef deleted file mode 100644 index e8b224c..0000000 --- a/FPGA22_HIER_SKY_PNR/modules/lef/cbx_1__0__icv_in_design.lef +++ /dev/null @@ -1,2032 +0,0 @@ -VERSION 5.7 ; -BUSBITCHARS "[]" ; - -UNITS - DATABASE MICRONS 1000 ; -END UNITS - -MANUFACTURINGGRID 0.005 ; - -LAYER li1 - TYPE ROUTING ; - DIRECTION VERTICAL ; - PITCH 0.46 ; - WIDTH 0.17 ; -END li1 - -LAYER mcon - TYPE CUT ; -END mcon - -LAYER met1 - TYPE ROUTING ; - DIRECTION HORIZONTAL ; - PITCH 0.34 ; - WIDTH 0.14 ; -END met1 - -LAYER via - TYPE CUT ; -END via - -LAYER met2 - TYPE ROUTING ; - DIRECTION VERTICAL ; - PITCH 0.46 ; - WIDTH 0.14 ; -END met2 - -LAYER via2 - TYPE CUT ; -END via2 - -LAYER met3 - TYPE ROUTING ; - DIRECTION HORIZONTAL ; - PITCH 0.68 ; - WIDTH 0.3 ; -END met3 - -LAYER via3 - TYPE CUT ; -END via3 - -LAYER met4 - TYPE ROUTING ; - DIRECTION VERTICAL ; - PITCH 0.92 ; - WIDTH 0.3 ; -END met4 - -LAYER via4 - TYPE CUT ; -END via4 - -LAYER met5 - TYPE ROUTING ; - DIRECTION HORIZONTAL ; - PITCH 3.4 ; - WIDTH 1.6 ; -END met5 - -LAYER nwell - TYPE MASTERSLICE ; -END nwell - -LAYER pwell - TYPE MASTERSLICE ; -END pwell - -LAYER OVERLAP - TYPE OVERLAP ; -END OVERLAP - -VIA L1M1_PR - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.145 -0.115 0.145 0.115 ; -END L1M1_PR - -VIA L1M1_PR_R - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.115 -0.145 0.115 0.145 ; -END L1M1_PR_R - -VIA L1M1_PR_M - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.115 -0.145 0.115 0.145 ; -END L1M1_PR_M - -VIA L1M1_PR_MR - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.145 -0.115 0.145 0.115 ; -END L1M1_PR_MR - -VIA L1M1_PR_C - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.145 -0.145 0.145 0.145 ; -END L1M1_PR_C - -VIA M1M2_PR - LAYER met1 ; - RECT -0.16 -0.13 0.16 0.13 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.13 -0.16 0.13 0.16 ; -END M1M2_PR - -VIA M1M2_PR_Enc - LAYER met1 ; - RECT -0.16 -0.13 0.16 0.13 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.16 -0.13 0.16 0.13 ; -END M1M2_PR_Enc - -VIA M1M2_PR_R - LAYER met1 ; - RECT -0.13 -0.16 0.13 0.16 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.16 -0.13 0.16 0.13 ; -END M1M2_PR_R - -VIA M1M2_PR_R_Enc - LAYER met1 ; - RECT -0.13 -0.16 0.13 0.16 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.13 -0.16 0.13 0.16 ; -END M1M2_PR_R_Enc - -VIA M1M2_PR_M - LAYER met1 ; - RECT -0.16 -0.13 0.16 0.13 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.16 -0.13 0.16 0.13 ; -END M1M2_PR_M - -VIA M1M2_PR_M_Enc - LAYER met1 ; - RECT -0.16 -0.13 0.16 0.13 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.13 -0.16 0.13 0.16 ; -END M1M2_PR_M_Enc - -VIA M1M2_PR_MR - LAYER met1 ; - RECT -0.13 -0.16 0.13 0.16 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.13 -0.16 0.13 0.16 ; -END M1M2_PR_MR - -VIA M1M2_PR_MR_Enc - LAYER met1 ; - RECT -0.13 -0.16 0.13 0.16 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.16 -0.13 0.16 0.13 ; -END M1M2_PR_MR_Enc - -VIA M1M2_PR_C - LAYER met1 ; - RECT -0.16 -0.16 0.16 0.16 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.16 -0.16 0.16 0.16 ; -END M1M2_PR_C - -VIA M2M3_PR - LAYER met2 ; - RECT -0.14 -0.185 0.14 0.185 ; - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met3 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M2M3_PR - -VIA M2M3_PR_R - LAYER met2 ; - RECT -0.185 -0.14 0.185 0.14 ; - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met3 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M2M3_PR_R - -VIA M2M3_PR_M - LAYER met2 ; - RECT -0.14 -0.185 0.14 0.185 ; - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met3 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M2M3_PR_M - -VIA M2M3_PR_MR - LAYER met2 ; - RECT -0.185 -0.14 0.185 0.14 ; - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met3 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M2M3_PR_MR - -VIA M2M3_PR_C - LAYER met2 ; - RECT -0.185 -0.185 0.185 0.185 ; - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met3 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M2M3_PR_C - -VIA M3M4_PR - LAYER met3 ; - RECT -0.19 -0.16 0.19 0.16 ; - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR - -VIA M3M4_PR_R - LAYER met3 ; - RECT -0.16 -0.19 0.16 0.19 ; - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR_R - -VIA M3M4_PR_M - LAYER met3 ; - RECT -0.19 -0.16 0.19 0.16 ; - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR_M - -VIA M3M4_PR_MR - LAYER met3 ; - RECT -0.16 -0.19 0.16 0.19 ; - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR_MR - -VIA M3M4_PR_C - LAYER met3 ; - RECT -0.19 -0.19 0.19 0.19 ; - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR_C - -VIA M4M5_PR - LAYER met4 ; - RECT -0.59 -0.59 0.59 0.59 ; - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - LAYER met5 ; - RECT -0.71 -0.71 0.71 0.71 ; -END M4M5_PR - -VIA M4M5_PR_R - LAYER met4 ; - RECT -0.59 -0.59 0.59 0.59 ; - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - LAYER met5 ; - RECT -0.71 -0.71 0.71 0.71 ; -END M4M5_PR_R - -VIA M4M5_PR_M - LAYER met4 ; - RECT -0.59 -0.59 0.59 0.59 ; - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - LAYER met5 ; - RECT -0.71 -0.71 0.71 0.71 ; -END M4M5_PR_M - -VIA M4M5_PR_MR - LAYER met4 ; - RECT -0.59 -0.59 0.59 0.59 ; - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - LAYER met5 ; - RECT -0.71 -0.71 0.71 0.71 ; -END M4M5_PR_MR - -VIA M4M5_PR_C - LAYER met4 ; - RECT -0.59 -0.59 0.59 0.59 ; - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - LAYER met5 ; - RECT -0.71 -0.71 0.71 0.71 ; -END M4M5_PR_C - -SITE unit - CLASS CORE ; - SYMMETRY Y ; - SIZE 0.46 BY 2.72 ; -END unit - -SITE unithddbl - CLASS CORE ; - SIZE 0.46 BY 5.44 ; -END unithddbl - -MACRO cbx_1__0_ - CLASS BLOCK ; - ORIGIN 0 0 ; - SIZE 66.24 BY 87.04 ; - SYMMETRY X Y ; - PIN prog_clk[0] - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER met3 ; - RECT 64.86 13.45 66.24 13.75 ; - END - END prog_clk[0] - PIN chanx_left_in[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 56.97 1.38 57.27 ; - END - END chanx_left_in[0] - PIN chanx_left_in[1] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 67.85 1.38 68.15 ; - END - END chanx_left_in[1] - PIN chanx_left_in[2] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 43.37 1.38 43.67 ; - END - END chanx_left_in[2] - PIN chanx_left_in[3] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 80.09 1.38 80.39 ; - END - END chanx_left_in[3] - PIN chanx_left_in[4] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 33.85 1.38 34.15 ; - END - END chanx_left_in[4] - PIN chanx_left_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 82.13 1.38 82.43 ; - END - END chanx_left_in[5] - PIN chanx_left_in[6] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 39.29 1.38 39.59 ; - END - END chanx_left_in[6] - PIN chanx_left_in[7] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 53.57 1.38 53.87 ; - END - END chanx_left_in[7] - PIN chanx_left_in[8] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 47.45 1.38 47.75 ; - END - END chanx_left_in[8] - PIN chanx_left_in[9] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 78.73 1.38 79.03 ; - END - END chanx_left_in[9] - PIN chanx_left_in[10] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 46.09 1.38 46.39 ; - END - END chanx_left_in[10] - PIN chanx_left_in[11] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 69.21 1.38 69.51 ; - END - END chanx_left_in[11] - PIN chanx_left_in[12] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 40.65 1.38 40.95 ; - END - END chanx_left_in[12] - PIN chanx_left_in[13] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 37.93 1.38 38.23 ; - END - END chanx_left_in[13] - PIN chanx_left_in[14] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 29.77 1.38 30.07 ; - END - END chanx_left_in[14] - PIN chanx_left_in[15] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 52.21 1.38 52.51 ; - END - END chanx_left_in[15] - PIN chanx_left_in[16] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 58.33 1.38 58.63 ; - END - END chanx_left_in[16] - PIN chanx_left_in[17] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 63.09 1.38 63.39 ; - END - END chanx_left_in[17] - PIN chanx_left_in[18] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 70.57 1.38 70.87 ; - END - END chanx_left_in[18] - PIN chanx_left_in[19] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 65.13 1.38 65.43 ; - END - END chanx_left_in[19] - PIN chanx_right_in[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 59.69 66.24 59.99 ; - END - END chanx_right_in[0] - PIN chanx_right_in[1] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 56.29 66.24 56.59 ; - END - END chanx_right_in[1] - PIN chanx_right_in[2] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 77.37 66.24 77.67 ; - END - END chanx_right_in[2] - PIN chanx_right_in[3] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 80.09 66.24 80.39 ; - END - END chanx_right_in[3] - PIN chanx_right_in[4] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 48.13 66.24 48.43 ; - END - END chanx_right_in[4] - PIN chanx_right_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 82.13 66.24 82.43 ; - END - END chanx_right_in[5] - PIN chanx_right_in[6] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 73.29 66.24 73.59 ; - END - END chanx_right_in[6] - PIN chanx_right_in[7] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 58.33 66.24 58.63 ; - END - END chanx_right_in[7] - PIN chanx_right_in[8] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 19.57 66.24 19.87 ; - END - END chanx_right_in[8] - PIN chanx_right_in[9] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 44.73 66.24 45.03 ; - END - END chanx_right_in[9] - PIN chanx_right_in[10] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 71.93 66.24 72.23 ; - END - END chanx_right_in[10] - PIN chanx_right_in[11] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 70.57 66.24 70.87 ; - END - END chanx_right_in[11] - PIN chanx_right_in[12] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 74.65 66.24 74.95 ; - END - END chanx_right_in[12] - PIN chanx_right_in[13] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 65.13 66.24 65.43 ; - END - END chanx_right_in[13] - PIN chanx_right_in[14] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 27.73 66.24 28.03 ; - END - END chanx_right_in[14] - PIN chanx_right_in[15] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 49.49 66.24 49.79 ; - END - END chanx_right_in[15] - PIN chanx_right_in[16] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 40.65 66.24 40.95 ; - END - END chanx_right_in[16] - PIN chanx_right_in[17] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 8.69 66.24 8.99 ; - END - END chanx_right_in[17] - PIN chanx_right_in[18] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 50.85 66.24 51.15 ; - END - END chanx_right_in[18] - PIN chanx_right_in[19] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 52.21 66.24 52.51 ; - END - END chanx_right_in[19] - PIN ccff_head[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 16.85 66.24 17.15 ; - END - END ccff_head[0] - PIN chanx_left_out[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 73.29 1.38 73.59 ; - END - END chanx_left_out[0] - PIN chanx_left_out[1] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 71.93 1.38 72.23 ; - END - END chanx_left_out[1] - PIN chanx_left_out[2] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 9.37 1.38 9.67 ; - END - END chanx_left_out[2] - PIN chanx_left_out[3] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 21.61 1.38 21.91 ; - END - END chanx_left_out[3] - PIN chanx_left_out[4] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 76.01 1.38 76.31 ; - END - END chanx_left_out[4] - PIN chanx_left_out[5] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 22.97 1.38 23.27 ; - END - END chanx_left_out[5] - PIN chanx_left_out[6] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 42.01 1.38 42.31 ; - END - END chanx_left_out[6] - PIN chanx_left_out[7] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 36.57 1.38 36.87 ; - END - END chanx_left_out[7] - PIN chanx_left_out[8] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 24.33 1.38 24.63 ; - END - END chanx_left_out[8] - PIN chanx_left_out[9] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 44.73 1.38 45.03 ; - END - END chanx_left_out[9] - PIN chanx_left_out[10] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 54.93 1.38 55.23 ; - END - END chanx_left_out[10] - PIN chanx_left_out[11] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 31.13 1.38 31.43 ; - END - END chanx_left_out[11] - PIN chanx_left_out[12] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 12.09 1.38 12.39 ; - END - END chanx_left_out[12] - PIN chanx_left_out[13] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 83.49 1.38 83.79 ; - END - END chanx_left_out[13] - PIN chanx_left_out[14] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 77.37 1.38 77.67 ; - END - END chanx_left_out[14] - PIN chanx_left_out[15] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 26.37 1.38 26.67 ; - END - END chanx_left_out[15] - PIN chanx_left_out[16] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 32.49 1.38 32.79 ; - END - END chanx_left_out[16] - PIN chanx_left_out[17] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 10.73 1.38 11.03 ; - END - END chanx_left_out[17] - PIN chanx_left_out[18] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 35.21 1.38 35.51 ; - END - END chanx_left_out[18] - PIN chanx_left_out[19] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 28.41 1.38 28.71 ; - END - END chanx_left_out[19] - PIN chanx_right_out[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 11.41 66.24 11.71 ; - END - END chanx_right_out[0] - PIN chanx_right_out[1] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 66.49 66.24 66.79 ; - END - END chanx_right_out[1] - PIN chanx_right_out[2] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 10.05 66.24 10.35 ; - END - END chanx_right_out[2] - PIN chanx_right_out[3] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 21.61 66.24 21.91 ; - END - END chanx_right_out[3] - PIN chanx_right_out[4] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 78.73 66.24 79.03 ; - END - END chanx_right_out[4] - PIN chanx_right_out[5] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 15.49 66.24 15.79 ; - END - END chanx_right_out[5] - PIN chanx_right_out[6] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 33.17 66.24 33.47 ; - END - END chanx_right_out[6] - PIN chanx_right_out[7] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 83.49 66.24 83.79 ; - END - END chanx_right_out[7] - PIN chanx_right_out[8] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 25.69 66.24 25.99 ; - END - END chanx_right_out[8] - PIN chanx_right_out[9] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 34.53 66.24 34.83 ; - END - END chanx_right_out[9] - PIN chanx_right_out[10] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 39.29 66.24 39.59 ; - END - END chanx_right_out[10] - PIN chanx_right_out[11] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 18.21 66.24 18.51 ; - END - END chanx_right_out[11] - PIN chanx_right_out[12] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 76.01 66.24 76.31 ; - END - END chanx_right_out[12] - PIN chanx_right_out[13] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 69.21 66.24 69.51 ; - END - END chanx_right_out[13] - PIN chanx_right_out[14] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 42.01 66.24 42.31 ; - END - END chanx_right_out[14] - PIN chanx_right_out[15] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 46.09 66.24 46.39 ; - END - END chanx_right_out[15] - PIN chanx_right_out[16] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 29.77 66.24 30.07 ; - END - END chanx_right_out[16] - PIN chanx_right_out[17] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 24.33 66.24 24.63 ; - END - END chanx_right_out[17] - PIN chanx_right_out[18] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 22.97 66.24 23.27 ; - END - END chanx_right_out[18] - PIN chanx_right_out[19] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 67.85 66.24 68.15 ; - END - END chanx_right_out[19] - PIN bottom_grid_pin_0_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 16.17 1.38 16.47 ; - END - END bottom_grid_pin_0_[0] - PIN bottom_grid_pin_2_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 11.43 85.68 11.57 87.04 ; - END - END bottom_grid_pin_2_[0] - PIN bottom_grid_pin_4_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 18.89 1.38 19.19 ; - END - END bottom_grid_pin_4_[0] - PIN bottom_grid_pin_6_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 5.97 66.24 6.27 ; - END - END bottom_grid_pin_6_[0] - PIN bottom_grid_pin_8_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 44.09 0 44.23 1.36 ; - END - END bottom_grid_pin_8_[0] - PIN bottom_grid_pin_10_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 28.91 0 29.05 1.36 ; - END - END bottom_grid_pin_10_[0] - PIN ccff_tail[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 13.45 1.38 13.75 ; - END - END ccff_tail[0] - PIN gfpga_pad_EMBEDDED_IO_SOC_IN[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 39.49 0 39.63 1.36 ; - END - END gfpga_pad_EMBEDDED_IO_SOC_IN[0] - PIN gfpga_pad_EMBEDDED_IO_SOC_IN[1] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 20.63 0 20.77 1.36 ; - END - END gfpga_pad_EMBEDDED_IO_SOC_IN[1] - PIN gfpga_pad_EMBEDDED_IO_SOC_IN[2] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 40.87 0 41.01 1.36 ; - END - END gfpga_pad_EMBEDDED_IO_SOC_IN[2] - PIN gfpga_pad_EMBEDDED_IO_SOC_IN[3] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 33.51 0 33.65 1.36 ; - END - END gfpga_pad_EMBEDDED_IO_SOC_IN[3] - PIN gfpga_pad_EMBEDDED_IO_SOC_IN[4] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 26.61 0 26.75 1.36 ; - END - END gfpga_pad_EMBEDDED_IO_SOC_IN[4] - PIN gfpga_pad_EMBEDDED_IO_SOC_IN[5] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 61.11 0 61.25 1.36 ; - END - END gfpga_pad_EMBEDDED_IO_SOC_IN[5] - PIN gfpga_pad_EMBEDDED_IO_SOC_OUT[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 34.43 0 34.57 1.36 ; - END - END gfpga_pad_EMBEDDED_IO_SOC_OUT[0] - PIN gfpga_pad_EMBEDDED_IO_SOC_OUT[1] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 4.07 0 4.21 1.36 ; - END - END gfpga_pad_EMBEDDED_IO_SOC_OUT[1] - PIN gfpga_pad_EMBEDDED_IO_SOC_OUT[2] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 14.19 0 14.33 1.36 ; - END - END gfpga_pad_EMBEDDED_IO_SOC_OUT[2] - PIN gfpga_pad_EMBEDDED_IO_SOC_OUT[3] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 42.25 0 42.39 1.36 ; - END - END gfpga_pad_EMBEDDED_IO_SOC_OUT[3] - PIN gfpga_pad_EMBEDDED_IO_SOC_OUT[4] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 56.05 0 56.19 1.36 ; - END - END gfpga_pad_EMBEDDED_IO_SOC_OUT[4] - PIN gfpga_pad_EMBEDDED_IO_SOC_OUT[5] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 23.85 0 23.99 1.36 ; - END - END gfpga_pad_EMBEDDED_IO_SOC_OUT[5] - PIN gfpga_pad_EMBEDDED_IO_SOC_DIR[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 31.21 0 31.35 1.36 ; - END - END gfpga_pad_EMBEDDED_IO_SOC_DIR[0] - PIN gfpga_pad_EMBEDDED_IO_SOC_DIR[1] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 27.99 0 28.13 1.36 ; - END - END gfpga_pad_EMBEDDED_IO_SOC_DIR[1] - PIN gfpga_pad_EMBEDDED_IO_SOC_DIR[2] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 24.77 0 24.91 1.36 ; - END - END gfpga_pad_EMBEDDED_IO_SOC_DIR[2] - PIN gfpga_pad_EMBEDDED_IO_SOC_DIR[3] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 12.81 0 12.95 1.36 ; - END - END gfpga_pad_EMBEDDED_IO_SOC_DIR[3] - PIN gfpga_pad_EMBEDDED_IO_SOC_DIR[4] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 8.67 0 8.81 1.36 ; - END - END gfpga_pad_EMBEDDED_IO_SOC_DIR[4] - PIN gfpga_pad_EMBEDDED_IO_SOC_DIR[5] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 7.75 0 7.89 1.36 ; - END - END gfpga_pad_EMBEDDED_IO_SOC_DIR[5] - PIN top_width_0_height_0__pin_0_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 17.53 1.38 17.83 ; - END - END top_width_0_height_0__pin_0_[0] - PIN top_width_0_height_0__pin_2_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 12.35 85.68 12.49 87.04 ; - END - END top_width_0_height_0__pin_2_[0] - PIN top_width_0_height_0__pin_4_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 20.25 1.38 20.55 ; - END - END top_width_0_height_0__pin_4_[0] - PIN top_width_0_height_0__pin_6_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 7.33 66.24 7.63 ; - END - END top_width_0_height_0__pin_6_[0] - PIN top_width_0_height_0__pin_8_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 43.17 0 43.31 1.36 ; - END - END top_width_0_height_0__pin_8_[0] - PIN top_width_0_height_0__pin_10_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 29.83 0 29.97 1.36 ; - END - END top_width_0_height_0__pin_10_[0] - PIN top_width_0_height_0__pin_1_upper[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 74.65 1.38 74.95 ; - END - END top_width_0_height_0__pin_1_upper[0] - PIN top_width_0_height_0__pin_1_lower[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 63.77 66.24 64.07 ; - END - END top_width_0_height_0__pin_1_lower[0] - PIN top_width_0_height_0__pin_3_upper[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 59.69 1.38 59.99 ; - END - END top_width_0_height_0__pin_3_upper[0] - PIN top_width_0_height_0__pin_3_lower[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 31.13 66.24 31.43 ; - END - END top_width_0_height_0__pin_3_lower[0] - PIN top_width_0_height_0__pin_5_upper[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 66.49 1.38 66.79 ; - END - END top_width_0_height_0__pin_5_upper[0] - PIN top_width_0_height_0__pin_5_lower[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 43.37 66.24 43.67 ; - END - END top_width_0_height_0__pin_5_lower[0] - PIN top_width_0_height_0__pin_7_upper[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 50.17 1.38 50.47 ; - END - END top_width_0_height_0__pin_7_upper[0] - PIN top_width_0_height_0__pin_7_lower[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 54.25 66.24 54.55 ; - END - END top_width_0_height_0__pin_7_lower[0] - PIN top_width_0_height_0__pin_9_upper[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 61.73 1.38 62.03 ; - END - END top_width_0_height_0__pin_9_upper[0] - PIN top_width_0_height_0__pin_9_lower[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 61.73 66.24 62.03 ; - END - END top_width_0_height_0__pin_9_lower[0] - PIN top_width_0_height_0__pin_11_upper[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 48.81 1.38 49.11 ; - END - END top_width_0_height_0__pin_11_upper[0] - PIN top_width_0_height_0__pin_11_lower[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 37.25 66.24 37.55 ; - END - END top_width_0_height_0__pin_11_lower[0] - PIN SC_IN_TOP - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 63.87 85.68 64.01 87.04 ; - END - END SC_IN_TOP - PIN SC_IN_BOT - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 14.81 1.38 15.11 ; - END - END SC_IN_BOT - PIN SC_OUT_TOP - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 14.19 85.68 14.33 87.04 ; - END - END SC_OUT_TOP - PIN SC_OUT_BOT - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 35.89 66.24 36.19 ; - END - END SC_OUT_BOT - PIN VDD - DIRECTION INPUT ; - USE POWER ; - PORT - LAYER met5 ; - RECT 0 11.32 3.2 14.52 ; - RECT 63.04 11.32 66.24 14.52 ; - RECT 0 52.12 3.2 55.32 ; - RECT 63.04 52.12 66.24 55.32 ; - LAYER met4 ; - RECT 10.74 0 11.34 0.6 ; - RECT 40.18 0 40.78 0.6 ; - RECT 10.74 86.44 11.34 87.04 ; - RECT 40.18 86.44 40.78 87.04 ; - LAYER met1 ; - RECT 0 2.48 0.48 2.96 ; - RECT 65.76 2.48 66.24 2.96 ; - RECT 0 7.92 0.48 8.4 ; - RECT 65.76 7.92 66.24 8.4 ; - RECT 0 13.36 0.48 13.84 ; - RECT 65.76 13.36 66.24 13.84 ; - RECT 0 18.8 0.48 19.28 ; - RECT 65.76 18.8 66.24 19.28 ; - RECT 0 24.24 0.48 24.72 ; - RECT 65.76 24.24 66.24 24.72 ; - RECT 0 29.68 0.48 30.16 ; - RECT 65.76 29.68 66.24 30.16 ; - RECT 0 35.12 0.48 35.6 ; - RECT 65.76 35.12 66.24 35.6 ; - RECT 0 40.56 0.48 41.04 ; - RECT 65.76 40.56 66.24 41.04 ; - RECT 0 46 0.48 46.48 ; - RECT 65.76 46 66.24 46.48 ; - RECT 0 51.44 0.48 51.92 ; - RECT 65.76 51.44 66.24 51.92 ; - RECT 0 56.88 0.48 57.36 ; - RECT 65.76 56.88 66.24 57.36 ; - RECT 0 62.32 0.48 62.8 ; - RECT 65.76 62.32 66.24 62.8 ; - RECT 0 67.76 0.48 68.24 ; - RECT 65.76 67.76 66.24 68.24 ; - RECT 0 73.2 0.48 73.68 ; - RECT 65.76 73.2 66.24 73.68 ; - RECT 0 78.64 0.48 79.12 ; - RECT 65.76 78.64 66.24 79.12 ; - RECT 0 84.08 0.48 84.56 ; - RECT 65.76 84.08 66.24 84.56 ; - END - END VDD - PIN VSS - DIRECTION INPUT ; - USE GROUND ; - PORT - LAYER met5 ; - RECT 0 31.72 3.2 34.92 ; - RECT 63.04 31.72 66.24 34.92 ; - RECT 0 72.52 3.2 75.72 ; - RECT 63.04 72.52 66.24 75.72 ; - LAYER met4 ; - RECT 25.46 0 26.06 0.6 ; - RECT 54.9 0 55.5 0.6 ; - RECT 25.46 86.44 26.06 87.04 ; - RECT 54.9 86.44 55.5 87.04 ; - LAYER met1 ; - RECT 0 0 66.24 0.24 ; - RECT 0 5.2 0.48 5.68 ; - RECT 65.76 5.2 66.24 5.68 ; - RECT 0 10.64 0.48 11.12 ; - RECT 65.76 10.64 66.24 11.12 ; - RECT 0 16.08 0.48 16.56 ; - RECT 65.76 16.08 66.24 16.56 ; - RECT 0 21.52 0.48 22 ; - RECT 65.76 21.52 66.24 22 ; - RECT 0 26.96 0.48 27.44 ; - RECT 65.76 26.96 66.24 27.44 ; - RECT 0 32.4 0.48 32.88 ; - RECT 65.76 32.4 66.24 32.88 ; - RECT 0 37.84 0.48 38.32 ; - RECT 65.76 37.84 66.24 38.32 ; - RECT 0 43.28 0.48 43.76 ; - RECT 65.76 43.28 66.24 43.76 ; - RECT 0 48.72 0.48 49.2 ; - RECT 65.76 48.72 66.24 49.2 ; - RECT 0 54.16 0.48 54.64 ; - RECT 65.76 54.16 66.24 54.64 ; - RECT 0 59.6 0.48 60.08 ; - RECT 65.76 59.6 66.24 60.08 ; - RECT 0 65.04 0.48 65.52 ; - RECT 65.76 65.04 66.24 65.52 ; - RECT 0 70.48 0.48 70.96 ; - RECT 65.76 70.48 66.24 70.96 ; - RECT 0 75.92 0.48 76.4 ; - RECT 65.76 75.92 66.24 76.4 ; - RECT 0 81.36 0.48 81.84 ; - RECT 65.76 81.36 66.24 81.84 ; - RECT 0 86.8 66.24 87.04 ; - END - END VSS - PIN prog_clk__FEEDTHRU_1[0] - DIRECTION OUTPUT ; - USE CLOCK ; - PORT - LAYER met2 ; - RECT 6.37 85.68 6.51 87.04 ; - END - END prog_clk__FEEDTHRU_1[0] - OBS - LAYER li1 ; - RECT 0 86.955 66.24 87.125 ; - RECT 65.32 84.235 66.24 84.405 ; - RECT 0 84.235 3.68 84.405 ; - RECT 65.32 81.515 66.24 81.685 ; - RECT 0 81.515 1.84 81.685 ; - RECT 65.32 78.795 66.24 78.965 ; - RECT 0 78.795 1.84 78.965 ; - RECT 65.32 76.075 66.24 76.245 ; - RECT 0 76.075 1.84 76.245 ; - RECT 65.32 73.355 66.24 73.525 ; - RECT 0 73.355 1.84 73.525 ; - RECT 65.32 70.635 66.24 70.805 ; - RECT 0 70.635 1.84 70.805 ; - RECT 65.32 67.915 66.24 68.085 ; - RECT 0 67.915 1.84 68.085 ; - RECT 65.32 65.195 66.24 65.365 ; - RECT 0 65.195 1.84 65.365 ; - RECT 65.32 62.475 66.24 62.645 ; - RECT 0 62.475 3.68 62.645 ; - RECT 65.32 59.755 66.24 59.925 ; - RECT 0 59.755 3.68 59.925 ; - RECT 65.32 57.035 66.24 57.205 ; - RECT 0 57.035 1.84 57.205 ; - RECT 65.32 54.315 66.24 54.485 ; - RECT 0 54.315 1.84 54.485 ; - RECT 65.32 51.595 66.24 51.765 ; - RECT 0 51.595 1.84 51.765 ; - RECT 65.32 48.875 66.24 49.045 ; - RECT 0 48.875 1.84 49.045 ; - RECT 65.32 46.155 66.24 46.325 ; - RECT 0 46.155 1.84 46.325 ; - RECT 65.32 43.435 66.24 43.605 ; - RECT 0 43.435 1.84 43.605 ; - RECT 65.32 40.715 66.24 40.885 ; - RECT 0 40.715 1.84 40.885 ; - RECT 62.56 37.995 66.24 38.165 ; - RECT 0 37.995 1.84 38.165 ; - RECT 62.56 35.275 66.24 35.445 ; - RECT 0 35.275 1.84 35.445 ; - RECT 65.32 32.555 66.24 32.725 ; - RECT 0 32.555 1.84 32.725 ; - RECT 65.32 29.835 66.24 30.005 ; - RECT 0 29.835 1.84 30.005 ; - RECT 65.32 27.115 66.24 27.285 ; - RECT 0 27.115 1.84 27.285 ; - RECT 65.32 24.395 66.24 24.565 ; - RECT 0 24.395 1.84 24.565 ; - RECT 65.32 21.675 66.24 21.845 ; - RECT 0 21.675 1.84 21.845 ; - RECT 65.32 18.955 66.24 19.125 ; - RECT 0 18.955 1.84 19.125 ; - RECT 64.4 16.235 66.24 16.405 ; - RECT 0 16.235 1.84 16.405 ; - RECT 64.4 13.515 66.24 13.685 ; - RECT 0 13.515 1.84 13.685 ; - RECT 65.32 10.795 66.24 10.965 ; - RECT 0 10.795 1.84 10.965 ; - RECT 65.32 8.075 66.24 8.245 ; - RECT 0 8.075 1.84 8.245 ; - RECT 65.78 5.355 66.24 5.525 ; - RECT 0 5.355 3.68 5.525 ; - RECT 65.78 2.635 66.24 2.805 ; - RECT 0 2.635 3.68 2.805 ; - RECT 0 -0.085 66.24 0.085 ; - LAYER met3 ; - POLYGON 55.365 87.205 55.365 87.2 55.58 87.2 55.58 86.88 55.365 86.88 55.365 86.875 55.035 86.875 55.035 86.88 54.82 86.88 54.82 87.2 55.035 87.2 55.035 87.205 ; - POLYGON 25.925 87.205 25.925 87.2 26.14 87.2 26.14 86.88 25.925 86.88 25.925 86.875 25.595 86.875 25.595 86.88 25.38 86.88 25.38 87.2 25.595 87.2 25.595 87.205 ; - POLYGON 14.41 71.55 14.41 71.25 1.23 71.25 1.23 71.53 1.78 71.53 1.78 71.55 ; - POLYGON 1.99 45.03 1.99 44.35 4.29 44.35 4.29 44.05 1.69 44.05 1.69 44.33 1.78 44.33 1.78 45.03 ; - POLYGON 6.59 37.55 6.59 37.25 1.99 37.25 1.99 36.57 1.78 36.57 1.78 37.27 1.69 37.27 1.69 37.55 ; - POLYGON 55.365 0.165 55.365 0.16 55.58 0.16 55.58 -0.16 55.365 -0.16 55.365 -0.165 55.035 -0.165 55.035 -0.16 54.82 -0.16 54.82 0.16 55.035 0.16 55.035 0.165 ; - POLYGON 25.925 0.165 25.925 0.16 26.14 0.16 26.14 -0.16 25.925 -0.16 25.925 -0.165 25.595 -0.165 25.595 -0.16 25.38 -0.16 25.38 0.16 25.595 0.16 25.595 0.165 ; - POLYGON 65.84 86.64 65.84 84.19 64.46 84.19 64.46 83.09 65.84 83.09 65.84 82.83 64.46 82.83 64.46 81.73 65.84 81.73 65.84 80.79 64.46 80.79 64.46 79.69 65.84 79.69 65.84 79.43 64.46 79.43 64.46 78.33 65.84 78.33 65.84 78.07 64.46 78.07 64.46 76.97 65.84 76.97 65.84 76.71 64.46 76.71 64.46 75.61 65.84 75.61 65.84 75.35 64.46 75.35 64.46 74.25 65.84 74.25 65.84 73.99 64.46 73.99 64.46 72.89 65.84 72.89 65.84 72.63 64.46 72.63 64.46 71.53 65.84 71.53 65.84 71.27 64.46 71.27 64.46 70.17 65.84 70.17 65.84 69.91 64.46 69.91 64.46 68.81 65.84 68.81 65.84 68.55 64.46 68.55 64.46 67.45 65.84 67.45 65.84 67.19 64.46 67.19 64.46 66.09 65.84 66.09 65.84 65.83 64.46 65.83 64.46 64.73 65.84 64.73 65.84 64.47 64.46 64.47 64.46 63.37 65.84 63.37 65.84 62.43 64.46 62.43 64.46 61.33 65.84 61.33 65.84 60.39 64.46 60.39 64.46 59.29 65.84 59.29 65.84 59.03 64.46 59.03 64.46 57.93 65.84 57.93 65.84 56.99 64.46 56.99 64.46 55.89 65.84 55.89 65.84 54.95 64.46 54.95 64.46 53.85 65.84 53.85 65.84 52.91 64.46 52.91 64.46 51.81 65.84 51.81 65.84 51.55 64.46 51.55 64.46 50.45 65.84 50.45 65.84 50.19 64.46 50.19 64.46 49.09 65.84 49.09 65.84 48.83 64.46 48.83 64.46 47.73 65.84 47.73 65.84 46.79 64.46 46.79 64.46 45.69 65.84 45.69 65.84 45.43 64.46 45.43 64.46 44.33 65.84 44.33 65.84 44.07 64.46 44.07 64.46 42.97 65.84 42.97 65.84 42.71 64.46 42.71 64.46 41.61 65.84 41.61 65.84 41.35 64.46 41.35 64.46 40.25 65.84 40.25 65.84 39.99 64.46 39.99 64.46 38.89 65.84 38.89 65.84 37.95 64.46 37.95 64.46 36.85 65.84 36.85 65.84 36.59 64.46 36.59 64.46 35.49 65.84 35.49 65.84 35.23 64.46 35.23 64.46 34.13 65.84 34.13 65.84 33.87 64.46 33.87 64.46 32.77 65.84 32.77 65.84 31.83 64.46 31.83 64.46 30.73 65.84 30.73 65.84 30.47 64.46 30.47 64.46 29.37 65.84 29.37 65.84 28.43 64.46 28.43 64.46 27.33 65.84 27.33 65.84 26.39 64.46 26.39 64.46 25.29 65.84 25.29 65.84 25.03 64.46 25.03 64.46 23.93 65.84 23.93 65.84 23.67 64.46 23.67 64.46 22.57 65.84 22.57 65.84 22.31 64.46 22.31 64.46 21.21 65.84 21.21 65.84 20.27 64.46 20.27 64.46 19.17 65.84 19.17 65.84 18.91 64.46 18.91 64.46 17.81 65.84 17.81 65.84 17.55 64.46 17.55 64.46 16.45 65.84 16.45 65.84 16.19 64.46 16.19 64.46 15.09 65.84 15.09 65.84 14.15 64.46 14.15 64.46 13.05 65.84 13.05 65.84 12.11 64.46 12.11 64.46 11.01 65.84 11.01 65.84 10.75 64.46 10.75 64.46 9.65 65.84 9.65 65.84 9.39 64.46 9.39 64.46 8.29 65.84 8.29 65.84 8.03 64.46 8.03 64.46 6.93 65.84 6.93 65.84 6.67 64.46 6.67 64.46 5.57 65.84 5.57 65.84 0.4 0.4 0.4 0.4 8.97 1.78 8.97 1.78 10.07 0.4 10.07 0.4 10.33 1.78 10.33 1.78 11.43 0.4 11.43 0.4 11.69 1.78 11.69 1.78 12.79 0.4 12.79 0.4 13.05 1.78 13.05 1.78 14.15 0.4 14.15 0.4 14.41 1.78 14.41 1.78 15.51 0.4 15.51 0.4 15.77 1.78 15.77 1.78 16.87 0.4 16.87 0.4 17.13 1.78 17.13 1.78 18.23 0.4 18.23 0.4 18.49 1.78 18.49 1.78 19.59 0.4 19.59 0.4 19.85 1.78 19.85 1.78 20.95 0.4 20.95 0.4 21.21 1.78 21.21 1.78 22.31 0.4 22.31 0.4 22.57 1.78 22.57 1.78 23.67 0.4 23.67 0.4 23.93 1.78 23.93 1.78 25.03 0.4 25.03 0.4 25.97 1.78 25.97 1.78 27.07 0.4 27.07 0.4 28.01 1.78 28.01 1.78 29.11 0.4 29.11 0.4 29.37 1.78 29.37 1.78 30.47 0.4 30.47 0.4 30.73 1.78 30.73 1.78 31.83 0.4 31.83 0.4 32.09 1.78 32.09 1.78 33.19 0.4 33.19 0.4 33.45 1.78 33.45 1.78 34.55 0.4 34.55 0.4 34.81 1.78 34.81 1.78 35.91 0.4 35.91 0.4 36.17 1.78 36.17 1.78 37.27 0.4 37.27 0.4 37.53 1.78 37.53 1.78 38.63 0.4 38.63 0.4 38.89 1.78 38.89 1.78 39.99 0.4 39.99 0.4 40.25 1.78 40.25 1.78 41.35 0.4 41.35 0.4 41.61 1.78 41.61 1.78 42.71 0.4 42.71 0.4 42.97 1.78 42.97 1.78 44.07 0.4 44.07 0.4 44.33 1.78 44.33 1.78 45.43 0.4 45.43 0.4 45.69 1.78 45.69 1.78 46.79 0.4 46.79 0.4 47.05 1.78 47.05 1.78 48.15 0.4 48.15 0.4 48.41 1.78 48.41 1.78 49.51 0.4 49.51 0.4 49.77 1.78 49.77 1.78 50.87 0.4 50.87 0.4 51.81 1.78 51.81 1.78 52.91 0.4 52.91 0.4 53.17 1.78 53.17 1.78 54.27 0.4 54.27 0.4 54.53 1.78 54.53 1.78 55.63 0.4 55.63 0.4 56.57 1.78 56.57 1.78 57.67 0.4 57.67 0.4 57.93 1.78 57.93 1.78 59.03 0.4 59.03 0.4 59.29 1.78 59.29 1.78 60.39 0.4 60.39 0.4 61.33 1.78 61.33 1.78 62.43 0.4 62.43 0.4 62.69 1.78 62.69 1.78 63.79 0.4 63.79 0.4 64.73 1.78 64.73 1.78 65.83 0.4 65.83 0.4 66.09 1.78 66.09 1.78 67.19 0.4 67.19 0.4 67.45 1.78 67.45 1.78 68.55 0.4 68.55 0.4 68.81 1.78 68.81 1.78 69.91 0.4 69.91 0.4 70.17 1.78 70.17 1.78 71.27 0.4 71.27 0.4 71.53 1.78 71.53 1.78 72.63 0.4 72.63 0.4 72.89 1.78 72.89 1.78 73.99 0.4 73.99 0.4 74.25 1.78 74.25 1.78 75.35 0.4 75.35 0.4 75.61 1.78 75.61 1.78 76.71 0.4 76.71 0.4 76.97 1.78 76.97 1.78 78.07 0.4 78.07 0.4 78.33 1.78 78.33 1.78 79.43 0.4 79.43 0.4 79.69 1.78 79.69 1.78 80.79 0.4 80.79 0.4 81.73 1.78 81.73 1.78 82.83 0.4 82.83 0.4 83.09 1.78 83.09 1.78 84.19 0.4 84.19 0.4 86.64 ; - LAYER met2 ; - RECT 55.06 86.855 55.34 87.225 ; - RECT 25.62 86.855 25.9 87.225 ; - RECT 55.06 -0.185 55.34 0.185 ; - RECT 25.62 -0.185 25.9 0.185 ; - POLYGON 65.96 86.76 65.96 0.28 61.53 0.28 61.53 1.64 60.83 1.64 60.83 0.28 56.47 0.28 56.47 1.64 55.77 1.64 55.77 0.28 44.51 0.28 44.51 1.64 43.81 1.64 43.81 0.28 43.59 0.28 43.59 1.64 42.89 1.64 42.89 0.28 42.67 0.28 42.67 1.64 41.97 1.64 41.97 0.28 41.29 0.28 41.29 1.64 40.59 1.64 40.59 0.28 39.91 0.28 39.91 1.64 39.21 1.64 39.21 0.28 34.85 0.28 34.85 1.64 34.15 1.64 34.15 0.28 33.93 0.28 33.93 1.64 33.23 1.64 33.23 0.28 31.63 0.28 31.63 1.64 30.93 1.64 30.93 0.28 30.25 0.28 30.25 1.64 29.55 1.64 29.55 0.28 29.33 0.28 29.33 1.64 28.63 1.64 28.63 0.28 28.41 0.28 28.41 1.64 27.71 1.64 27.71 0.28 27.03 0.28 27.03 1.64 26.33 1.64 26.33 0.28 25.19 0.28 25.19 1.64 24.49 1.64 24.49 0.28 24.27 0.28 24.27 1.64 23.57 1.64 23.57 0.28 21.05 0.28 21.05 1.64 20.35 1.64 20.35 0.28 14.61 0.28 14.61 1.64 13.91 1.64 13.91 0.28 13.23 0.28 13.23 1.64 12.53 1.64 12.53 0.28 9.09 0.28 9.09 1.64 8.39 1.64 8.39 0.28 8.17 0.28 8.17 1.64 7.47 1.64 7.47 0.28 4.49 0.28 4.49 1.64 3.79 1.64 3.79 0.28 0.28 0.28 0.28 86.76 6.09 86.76 6.09 85.4 6.79 85.4 6.79 86.76 11.15 86.76 11.15 85.4 11.85 85.4 11.85 86.76 12.07 86.76 12.07 85.4 12.77 85.4 12.77 86.76 13.91 86.76 13.91 85.4 14.61 85.4 14.61 86.76 63.59 86.76 63.59 85.4 64.29 85.4 64.29 86.76 ; - LAYER met1 ; - POLYGON 65.96 86.52 65.96 84.84 65.48 84.84 65.48 83.8 65.96 83.8 65.96 82.12 65.48 82.12 65.48 81.08 65.96 81.08 65.96 79.4 65.48 79.4 65.48 78.36 65.96 78.36 65.96 76.68 65.48 76.68 65.48 75.64 65.96 75.64 65.96 73.96 65.48 73.96 65.48 72.92 65.96 72.92 65.96 71.24 65.48 71.24 65.48 70.2 65.96 70.2 65.96 68.52 65.48 68.52 65.48 67.48 65.96 67.48 65.96 65.8 65.48 65.8 65.48 64.76 65.96 64.76 65.96 63.08 65.48 63.08 65.48 62.04 65.96 62.04 65.96 60.36 65.48 60.36 65.48 59.32 65.96 59.32 65.96 57.64 65.48 57.64 65.48 56.6 65.96 56.6 65.96 54.92 65.48 54.92 65.48 53.88 65.96 53.88 65.96 52.2 65.48 52.2 65.48 51.16 65.96 51.16 65.96 49.48 65.48 49.48 65.48 48.44 65.96 48.44 65.96 46.76 65.48 46.76 65.48 45.72 65.96 45.72 65.96 44.04 65.48 44.04 65.48 43 65.96 43 65.96 41.32 65.48 41.32 65.48 40.28 65.96 40.28 65.96 38.6 65.48 38.6 65.48 37.56 65.96 37.56 65.96 35.88 65.48 35.88 65.48 34.84 65.96 34.84 65.96 33.16 65.48 33.16 65.48 32.12 65.96 32.12 65.96 30.44 65.48 30.44 65.48 29.4 65.96 29.4 65.96 27.72 65.48 27.72 65.48 26.68 65.96 26.68 65.96 25 65.48 25 65.48 23.96 65.96 23.96 65.96 22.28 65.48 22.28 65.48 21.24 65.96 21.24 65.96 19.56 65.48 19.56 65.48 18.52 65.96 18.52 65.96 16.84 65.48 16.84 65.48 15.8 65.96 15.8 65.96 14.12 65.48 14.12 65.48 13.08 65.96 13.08 65.96 11.4 65.48 11.4 65.48 10.36 65.96 10.36 65.96 8.68 65.48 8.68 65.48 7.64 65.96 7.64 65.96 5.96 65.48 5.96 65.48 4.92 65.96 4.92 65.96 3.24 65.48 3.24 65.48 2.2 65.96 2.2 65.96 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 0.76 10.36 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 0.76 81.08 0.76 82.12 0.28 82.12 0.28 83.8 0.76 83.8 0.76 84.84 0.28 84.84 0.28 86.52 ; - LAYER met4 ; - POLYGON 65.84 86.64 65.84 0.4 55.9 0.4 55.9 1 54.5 1 54.5 0.4 41.18 0.4 41.18 1 39.78 1 39.78 0.4 26.46 0.4 26.46 1 25.06 1 25.06 0.4 11.74 0.4 11.74 1 10.34 1 10.34 0.4 0.4 0.4 0.4 86.64 10.34 86.64 10.34 86.04 11.74 86.04 11.74 86.64 25.06 86.64 25.06 86.04 26.46 86.04 26.46 86.64 39.78 86.64 39.78 86.04 41.18 86.04 41.18 86.64 54.5 86.64 54.5 86.04 55.9 86.04 55.9 86.64 ; - LAYER met5 ; - POLYGON 64.64 85.44 64.64 77.32 61.44 77.32 61.44 70.92 64.64 70.92 64.64 56.92 61.44 56.92 61.44 50.52 64.64 50.52 64.64 36.52 61.44 36.52 61.44 30.12 64.64 30.12 64.64 16.12 61.44 16.12 61.44 9.72 64.64 9.72 64.64 1.6 1.6 1.6 1.6 9.72 4.8 9.72 4.8 16.12 1.6 16.12 1.6 30.12 4.8 30.12 4.8 36.52 1.6 36.52 1.6 50.52 4.8 50.52 4.8 56.92 1.6 56.92 1.6 70.92 4.8 70.92 4.8 77.32 1.6 77.32 1.6 85.44 ; - LAYER li1 ; - RECT 0.17 0.17 66.07 86.87 ; - LAYER mcon ; - RECT 65.925 86.955 66.095 87.125 ; - RECT 65.465 86.955 65.635 87.125 ; - RECT 65.005 86.955 65.175 87.125 ; - RECT 64.545 86.955 64.715 87.125 ; - RECT 64.085 86.955 64.255 87.125 ; - RECT 63.625 86.955 63.795 87.125 ; - RECT 63.165 86.955 63.335 87.125 ; - RECT 62.705 86.955 62.875 87.125 ; - RECT 62.245 86.955 62.415 87.125 ; - RECT 61.785 86.955 61.955 87.125 ; - RECT 61.325 86.955 61.495 87.125 ; - RECT 60.865 86.955 61.035 87.125 ; - RECT 60.405 86.955 60.575 87.125 ; - RECT 59.945 86.955 60.115 87.125 ; - RECT 59.485 86.955 59.655 87.125 ; - RECT 59.025 86.955 59.195 87.125 ; - RECT 58.565 86.955 58.735 87.125 ; - RECT 58.105 86.955 58.275 87.125 ; - RECT 57.645 86.955 57.815 87.125 ; - RECT 57.185 86.955 57.355 87.125 ; - RECT 56.725 86.955 56.895 87.125 ; - RECT 56.265 86.955 56.435 87.125 ; - RECT 55.805 86.955 55.975 87.125 ; - RECT 55.345 86.955 55.515 87.125 ; - RECT 54.885 86.955 55.055 87.125 ; - RECT 54.425 86.955 54.595 87.125 ; - RECT 53.965 86.955 54.135 87.125 ; - RECT 53.505 86.955 53.675 87.125 ; - RECT 53.045 86.955 53.215 87.125 ; - RECT 52.585 86.955 52.755 87.125 ; - RECT 52.125 86.955 52.295 87.125 ; - RECT 51.665 86.955 51.835 87.125 ; - RECT 51.205 86.955 51.375 87.125 ; - RECT 50.745 86.955 50.915 87.125 ; - RECT 50.285 86.955 50.455 87.125 ; - RECT 49.825 86.955 49.995 87.125 ; - RECT 49.365 86.955 49.535 87.125 ; - RECT 48.905 86.955 49.075 87.125 ; - RECT 48.445 86.955 48.615 87.125 ; - RECT 47.985 86.955 48.155 87.125 ; - RECT 47.525 86.955 47.695 87.125 ; - RECT 47.065 86.955 47.235 87.125 ; - RECT 46.605 86.955 46.775 87.125 ; - RECT 46.145 86.955 46.315 87.125 ; - RECT 45.685 86.955 45.855 87.125 ; - RECT 45.225 86.955 45.395 87.125 ; - RECT 44.765 86.955 44.935 87.125 ; - RECT 44.305 86.955 44.475 87.125 ; - RECT 43.845 86.955 44.015 87.125 ; - RECT 43.385 86.955 43.555 87.125 ; - RECT 42.925 86.955 43.095 87.125 ; - RECT 42.465 86.955 42.635 87.125 ; - RECT 42.005 86.955 42.175 87.125 ; - RECT 41.545 86.955 41.715 87.125 ; - RECT 41.085 86.955 41.255 87.125 ; - RECT 40.625 86.955 40.795 87.125 ; - RECT 40.165 86.955 40.335 87.125 ; - RECT 39.705 86.955 39.875 87.125 ; - RECT 39.245 86.955 39.415 87.125 ; - RECT 38.785 86.955 38.955 87.125 ; - RECT 38.325 86.955 38.495 87.125 ; - RECT 37.865 86.955 38.035 87.125 ; - RECT 37.405 86.955 37.575 87.125 ; - RECT 36.945 86.955 37.115 87.125 ; - RECT 36.485 86.955 36.655 87.125 ; - RECT 36.025 86.955 36.195 87.125 ; - RECT 35.565 86.955 35.735 87.125 ; - RECT 35.105 86.955 35.275 87.125 ; - RECT 34.645 86.955 34.815 87.125 ; - RECT 34.185 86.955 34.355 87.125 ; - RECT 33.725 86.955 33.895 87.125 ; - RECT 33.265 86.955 33.435 87.125 ; - RECT 32.805 86.955 32.975 87.125 ; - RECT 32.345 86.955 32.515 87.125 ; - RECT 31.885 86.955 32.055 87.125 ; - RECT 31.425 86.955 31.595 87.125 ; - RECT 30.965 86.955 31.135 87.125 ; - RECT 30.505 86.955 30.675 87.125 ; - RECT 30.045 86.955 30.215 87.125 ; - RECT 29.585 86.955 29.755 87.125 ; - RECT 29.125 86.955 29.295 87.125 ; - RECT 28.665 86.955 28.835 87.125 ; - RECT 28.205 86.955 28.375 87.125 ; - RECT 27.745 86.955 27.915 87.125 ; - RECT 27.285 86.955 27.455 87.125 ; - RECT 26.825 86.955 26.995 87.125 ; - RECT 26.365 86.955 26.535 87.125 ; - RECT 25.905 86.955 26.075 87.125 ; - RECT 25.445 86.955 25.615 87.125 ; - RECT 24.985 86.955 25.155 87.125 ; - RECT 24.525 86.955 24.695 87.125 ; - RECT 24.065 86.955 24.235 87.125 ; - RECT 23.605 86.955 23.775 87.125 ; - RECT 23.145 86.955 23.315 87.125 ; - RECT 22.685 86.955 22.855 87.125 ; - RECT 22.225 86.955 22.395 87.125 ; - RECT 21.765 86.955 21.935 87.125 ; - RECT 21.305 86.955 21.475 87.125 ; - RECT 20.845 86.955 21.015 87.125 ; - RECT 20.385 86.955 20.555 87.125 ; - RECT 19.925 86.955 20.095 87.125 ; - RECT 19.465 86.955 19.635 87.125 ; - RECT 19.005 86.955 19.175 87.125 ; - RECT 18.545 86.955 18.715 87.125 ; - RECT 18.085 86.955 18.255 87.125 ; - RECT 17.625 86.955 17.795 87.125 ; - RECT 17.165 86.955 17.335 87.125 ; - RECT 16.705 86.955 16.875 87.125 ; - RECT 16.245 86.955 16.415 87.125 ; - RECT 15.785 86.955 15.955 87.125 ; - RECT 15.325 86.955 15.495 87.125 ; - RECT 14.865 86.955 15.035 87.125 ; - RECT 14.405 86.955 14.575 87.125 ; - RECT 13.945 86.955 14.115 87.125 ; - RECT 13.485 86.955 13.655 87.125 ; - RECT 13.025 86.955 13.195 87.125 ; - RECT 12.565 86.955 12.735 87.125 ; - RECT 12.105 86.955 12.275 87.125 ; - RECT 11.645 86.955 11.815 87.125 ; - RECT 11.185 86.955 11.355 87.125 ; - RECT 10.725 86.955 10.895 87.125 ; - RECT 10.265 86.955 10.435 87.125 ; - RECT 9.805 86.955 9.975 87.125 ; - RECT 9.345 86.955 9.515 87.125 ; - RECT 8.885 86.955 9.055 87.125 ; - RECT 8.425 86.955 8.595 87.125 ; - RECT 7.965 86.955 8.135 87.125 ; - RECT 7.505 86.955 7.675 87.125 ; - RECT 7.045 86.955 7.215 87.125 ; - RECT 6.585 86.955 6.755 87.125 ; - RECT 6.125 86.955 6.295 87.125 ; - RECT 5.665 86.955 5.835 87.125 ; - RECT 5.205 86.955 5.375 87.125 ; - RECT 4.745 86.955 4.915 87.125 ; - RECT 4.285 86.955 4.455 87.125 ; - RECT 3.825 86.955 3.995 87.125 ; - RECT 3.365 86.955 3.535 87.125 ; - RECT 2.905 86.955 3.075 87.125 ; - RECT 2.445 86.955 2.615 87.125 ; - RECT 1.985 86.955 2.155 87.125 ; - RECT 1.525 86.955 1.695 87.125 ; - RECT 1.065 86.955 1.235 87.125 ; - RECT 0.605 86.955 0.775 87.125 ; - RECT 0.145 86.955 0.315 87.125 ; - RECT 65.925 84.235 66.095 84.405 ; - RECT 65.465 84.235 65.635 84.405 ; - RECT 0.605 84.235 0.775 84.405 ; - RECT 0.145 84.235 0.315 84.405 ; - RECT 65.925 81.515 66.095 81.685 ; - RECT 65.465 81.515 65.635 81.685 ; - RECT 0.605 81.515 0.775 81.685 ; - RECT 0.145 81.515 0.315 81.685 ; - RECT 65.925 78.795 66.095 78.965 ; - RECT 65.465 78.795 65.635 78.965 ; - RECT 0.605 78.795 0.775 78.965 ; - RECT 0.145 78.795 0.315 78.965 ; - RECT 65.925 76.075 66.095 76.245 ; - RECT 65.465 76.075 65.635 76.245 ; - RECT 0.605 76.075 0.775 76.245 ; - RECT 0.145 76.075 0.315 76.245 ; - RECT 65.925 73.355 66.095 73.525 ; - RECT 65.465 73.355 65.635 73.525 ; - RECT 0.605 73.355 0.775 73.525 ; - RECT 0.145 73.355 0.315 73.525 ; - RECT 65.925 70.635 66.095 70.805 ; - RECT 65.465 70.635 65.635 70.805 ; - RECT 0.605 70.635 0.775 70.805 ; - RECT 0.145 70.635 0.315 70.805 ; - RECT 65.925 67.915 66.095 68.085 ; - RECT 65.465 67.915 65.635 68.085 ; - RECT 0.605 67.915 0.775 68.085 ; - RECT 0.145 67.915 0.315 68.085 ; - RECT 65.925 65.195 66.095 65.365 ; - RECT 65.465 65.195 65.635 65.365 ; - RECT 0.605 65.195 0.775 65.365 ; - RECT 0.145 65.195 0.315 65.365 ; - RECT 65.925 62.475 66.095 62.645 ; - RECT 65.465 62.475 65.635 62.645 ; - RECT 0.605 62.475 0.775 62.645 ; - RECT 0.145 62.475 0.315 62.645 ; - RECT 65.925 59.755 66.095 59.925 ; - RECT 65.465 59.755 65.635 59.925 ; - RECT 0.605 59.755 0.775 59.925 ; - RECT 0.145 59.755 0.315 59.925 ; - RECT 65.925 57.035 66.095 57.205 ; - RECT 65.465 57.035 65.635 57.205 ; - RECT 0.605 57.035 0.775 57.205 ; - RECT 0.145 57.035 0.315 57.205 ; - RECT 65.925 54.315 66.095 54.485 ; - RECT 65.465 54.315 65.635 54.485 ; - RECT 0.605 54.315 0.775 54.485 ; - RECT 0.145 54.315 0.315 54.485 ; - RECT 65.925 51.595 66.095 51.765 ; - RECT 65.465 51.595 65.635 51.765 ; - RECT 0.605 51.595 0.775 51.765 ; - RECT 0.145 51.595 0.315 51.765 ; - RECT 65.925 48.875 66.095 49.045 ; - RECT 65.465 48.875 65.635 49.045 ; - RECT 0.605 48.875 0.775 49.045 ; - RECT 0.145 48.875 0.315 49.045 ; - RECT 65.925 46.155 66.095 46.325 ; - RECT 65.465 46.155 65.635 46.325 ; - RECT 0.605 46.155 0.775 46.325 ; - RECT 0.145 46.155 0.315 46.325 ; - RECT 65.925 43.435 66.095 43.605 ; - RECT 65.465 43.435 65.635 43.605 ; - RECT 0.605 43.435 0.775 43.605 ; - RECT 0.145 43.435 0.315 43.605 ; - RECT 65.925 40.715 66.095 40.885 ; - RECT 65.465 40.715 65.635 40.885 ; - RECT 0.605 40.715 0.775 40.885 ; - RECT 0.145 40.715 0.315 40.885 ; - RECT 65.925 37.995 66.095 38.165 ; - RECT 65.465 37.995 65.635 38.165 ; - RECT 0.605 37.995 0.775 38.165 ; - RECT 0.145 37.995 0.315 38.165 ; - RECT 65.925 35.275 66.095 35.445 ; - RECT 65.465 35.275 65.635 35.445 ; - RECT 0.605 35.275 0.775 35.445 ; - RECT 0.145 35.275 0.315 35.445 ; - RECT 65.925 32.555 66.095 32.725 ; - RECT 65.465 32.555 65.635 32.725 ; - RECT 0.605 32.555 0.775 32.725 ; - RECT 0.145 32.555 0.315 32.725 ; - RECT 65.925 29.835 66.095 30.005 ; - RECT 65.465 29.835 65.635 30.005 ; - RECT 0.605 29.835 0.775 30.005 ; - RECT 0.145 29.835 0.315 30.005 ; - RECT 65.925 27.115 66.095 27.285 ; - RECT 65.465 27.115 65.635 27.285 ; - RECT 0.605 27.115 0.775 27.285 ; - RECT 0.145 27.115 0.315 27.285 ; - RECT 65.925 24.395 66.095 24.565 ; - RECT 65.465 24.395 65.635 24.565 ; - RECT 0.605 24.395 0.775 24.565 ; - RECT 0.145 24.395 0.315 24.565 ; - RECT 65.925 21.675 66.095 21.845 ; - RECT 65.465 21.675 65.635 21.845 ; - RECT 0.605 21.675 0.775 21.845 ; - RECT 0.145 21.675 0.315 21.845 ; - RECT 65.925 18.955 66.095 19.125 ; - RECT 65.465 18.955 65.635 19.125 ; - RECT 0.605 18.955 0.775 19.125 ; - RECT 0.145 18.955 0.315 19.125 ; - RECT 65.925 16.235 66.095 16.405 ; - RECT 65.465 16.235 65.635 16.405 ; - RECT 0.605 16.235 0.775 16.405 ; - RECT 0.145 16.235 0.315 16.405 ; - RECT 65.925 13.515 66.095 13.685 ; - RECT 65.465 13.515 65.635 13.685 ; - RECT 0.605 13.515 0.775 13.685 ; - RECT 0.145 13.515 0.315 13.685 ; - RECT 65.925 10.795 66.095 10.965 ; - RECT 65.465 10.795 65.635 10.965 ; - RECT 0.605 10.795 0.775 10.965 ; - RECT 0.145 10.795 0.315 10.965 ; - RECT 65.925 8.075 66.095 8.245 ; - RECT 65.465 8.075 65.635 8.245 ; - RECT 0.605 8.075 0.775 8.245 ; - RECT 0.145 8.075 0.315 8.245 ; - RECT 65.925 5.355 66.095 5.525 ; - RECT 65.465 5.355 65.635 5.525 ; - RECT 0.605 5.355 0.775 5.525 ; - RECT 0.145 5.355 0.315 5.525 ; - RECT 65.925 2.635 66.095 2.805 ; - RECT 65.465 2.635 65.635 2.805 ; - RECT 0.605 2.635 0.775 2.805 ; - RECT 0.145 2.635 0.315 2.805 ; - RECT 65.925 -0.085 66.095 0.085 ; - RECT 65.465 -0.085 65.635 0.085 ; - RECT 65.005 -0.085 65.175 0.085 ; - RECT 64.545 -0.085 64.715 0.085 ; - RECT 64.085 -0.085 64.255 0.085 ; - RECT 63.625 -0.085 63.795 0.085 ; - RECT 63.165 -0.085 63.335 0.085 ; - RECT 62.705 -0.085 62.875 0.085 ; - RECT 62.245 -0.085 62.415 0.085 ; - RECT 61.785 -0.085 61.955 0.085 ; - RECT 61.325 -0.085 61.495 0.085 ; - RECT 60.865 -0.085 61.035 0.085 ; - RECT 60.405 -0.085 60.575 0.085 ; - RECT 59.945 -0.085 60.115 0.085 ; - RECT 59.485 -0.085 59.655 0.085 ; - RECT 59.025 -0.085 59.195 0.085 ; - RECT 58.565 -0.085 58.735 0.085 ; - RECT 58.105 -0.085 58.275 0.085 ; - RECT 57.645 -0.085 57.815 0.085 ; - RECT 57.185 -0.085 57.355 0.085 ; - RECT 56.725 -0.085 56.895 0.085 ; - RECT 56.265 -0.085 56.435 0.085 ; - RECT 55.805 -0.085 55.975 0.085 ; - RECT 55.345 -0.085 55.515 0.085 ; - RECT 54.885 -0.085 55.055 0.085 ; - RECT 54.425 -0.085 54.595 0.085 ; - RECT 53.965 -0.085 54.135 0.085 ; - RECT 53.505 -0.085 53.675 0.085 ; - RECT 53.045 -0.085 53.215 0.085 ; - RECT 52.585 -0.085 52.755 0.085 ; - RECT 52.125 -0.085 52.295 0.085 ; - RECT 51.665 -0.085 51.835 0.085 ; - RECT 51.205 -0.085 51.375 0.085 ; - RECT 50.745 -0.085 50.915 0.085 ; - RECT 50.285 -0.085 50.455 0.085 ; - RECT 49.825 -0.085 49.995 0.085 ; - RECT 49.365 -0.085 49.535 0.085 ; - RECT 48.905 -0.085 49.075 0.085 ; - RECT 48.445 -0.085 48.615 0.085 ; - RECT 47.985 -0.085 48.155 0.085 ; - RECT 47.525 -0.085 47.695 0.085 ; - RECT 47.065 -0.085 47.235 0.085 ; - RECT 46.605 -0.085 46.775 0.085 ; - RECT 46.145 -0.085 46.315 0.085 ; - RECT 45.685 -0.085 45.855 0.085 ; - RECT 45.225 -0.085 45.395 0.085 ; - RECT 44.765 -0.085 44.935 0.085 ; - RECT 44.305 -0.085 44.475 0.085 ; - RECT 43.845 -0.085 44.015 0.085 ; - RECT 43.385 -0.085 43.555 0.085 ; - RECT 42.925 -0.085 43.095 0.085 ; - RECT 42.465 -0.085 42.635 0.085 ; - RECT 42.005 -0.085 42.175 0.085 ; - RECT 41.545 -0.085 41.715 0.085 ; - RECT 41.085 -0.085 41.255 0.085 ; - RECT 40.625 -0.085 40.795 0.085 ; - RECT 40.165 -0.085 40.335 0.085 ; - RECT 39.705 -0.085 39.875 0.085 ; - RECT 39.245 -0.085 39.415 0.085 ; - RECT 38.785 -0.085 38.955 0.085 ; - RECT 38.325 -0.085 38.495 0.085 ; - RECT 37.865 -0.085 38.035 0.085 ; - RECT 37.405 -0.085 37.575 0.085 ; - RECT 36.945 -0.085 37.115 0.085 ; - RECT 36.485 -0.085 36.655 0.085 ; - RECT 36.025 -0.085 36.195 0.085 ; - RECT 35.565 -0.085 35.735 0.085 ; - RECT 35.105 -0.085 35.275 0.085 ; - RECT 34.645 -0.085 34.815 0.085 ; - RECT 34.185 -0.085 34.355 0.085 ; - RECT 33.725 -0.085 33.895 0.085 ; - RECT 33.265 -0.085 33.435 0.085 ; - RECT 32.805 -0.085 32.975 0.085 ; - RECT 32.345 -0.085 32.515 0.085 ; - RECT 31.885 -0.085 32.055 0.085 ; - RECT 31.425 -0.085 31.595 0.085 ; - RECT 30.965 -0.085 31.135 0.085 ; - RECT 30.505 -0.085 30.675 0.085 ; - RECT 30.045 -0.085 30.215 0.085 ; - RECT 29.585 -0.085 29.755 0.085 ; - RECT 29.125 -0.085 29.295 0.085 ; - RECT 28.665 -0.085 28.835 0.085 ; - RECT 28.205 -0.085 28.375 0.085 ; - RECT 27.745 -0.085 27.915 0.085 ; - RECT 27.285 -0.085 27.455 0.085 ; - RECT 26.825 -0.085 26.995 0.085 ; - RECT 26.365 -0.085 26.535 0.085 ; - RECT 25.905 -0.085 26.075 0.085 ; - RECT 25.445 -0.085 25.615 0.085 ; - RECT 24.985 -0.085 25.155 0.085 ; - RECT 24.525 -0.085 24.695 0.085 ; - RECT 24.065 -0.085 24.235 0.085 ; - RECT 23.605 -0.085 23.775 0.085 ; - RECT 23.145 -0.085 23.315 0.085 ; - RECT 22.685 -0.085 22.855 0.085 ; - RECT 22.225 -0.085 22.395 0.085 ; - RECT 21.765 -0.085 21.935 0.085 ; - RECT 21.305 -0.085 21.475 0.085 ; - RECT 20.845 -0.085 21.015 0.085 ; - RECT 20.385 -0.085 20.555 0.085 ; - RECT 19.925 -0.085 20.095 0.085 ; - RECT 19.465 -0.085 19.635 0.085 ; - RECT 19.005 -0.085 19.175 0.085 ; - RECT 18.545 -0.085 18.715 0.085 ; - RECT 18.085 -0.085 18.255 0.085 ; - RECT 17.625 -0.085 17.795 0.085 ; - RECT 17.165 -0.085 17.335 0.085 ; - RECT 16.705 -0.085 16.875 0.085 ; - RECT 16.245 -0.085 16.415 0.085 ; - RECT 15.785 -0.085 15.955 0.085 ; - RECT 15.325 -0.085 15.495 0.085 ; - RECT 14.865 -0.085 15.035 0.085 ; - RECT 14.405 -0.085 14.575 0.085 ; - RECT 13.945 -0.085 14.115 0.085 ; - RECT 13.485 -0.085 13.655 0.085 ; - RECT 13.025 -0.085 13.195 0.085 ; - RECT 12.565 -0.085 12.735 0.085 ; - RECT 12.105 -0.085 12.275 0.085 ; - RECT 11.645 -0.085 11.815 0.085 ; - RECT 11.185 -0.085 11.355 0.085 ; - RECT 10.725 -0.085 10.895 0.085 ; - RECT 10.265 -0.085 10.435 0.085 ; - RECT 9.805 -0.085 9.975 0.085 ; - RECT 9.345 -0.085 9.515 0.085 ; - RECT 8.885 -0.085 9.055 0.085 ; - RECT 8.425 -0.085 8.595 0.085 ; - RECT 7.965 -0.085 8.135 0.085 ; - RECT 7.505 -0.085 7.675 0.085 ; - RECT 7.045 -0.085 7.215 0.085 ; - RECT 6.585 -0.085 6.755 0.085 ; - RECT 6.125 -0.085 6.295 0.085 ; - RECT 5.665 -0.085 5.835 0.085 ; - RECT 5.205 -0.085 5.375 0.085 ; - RECT 4.745 -0.085 4.915 0.085 ; - RECT 4.285 -0.085 4.455 0.085 ; - RECT 3.825 -0.085 3.995 0.085 ; - RECT 3.365 -0.085 3.535 0.085 ; - RECT 2.905 -0.085 3.075 0.085 ; - RECT 2.445 -0.085 2.615 0.085 ; - RECT 1.985 -0.085 2.155 0.085 ; - RECT 1.525 -0.085 1.695 0.085 ; - RECT 1.065 -0.085 1.235 0.085 ; - RECT 0.605 -0.085 0.775 0.085 ; - RECT 0.145 -0.085 0.315 0.085 ; - LAYER via ; - RECT 55.125 86.965 55.275 87.115 ; - RECT 25.685 86.965 25.835 87.115 ; - RECT 56.045 1.625 56.195 1.775 ; - RECT 43.165 1.625 43.315 1.775 ; - RECT 29.825 1.625 29.975 1.775 ; - RECT 23.845 1.625 23.995 1.775 ; - RECT 55.125 -0.075 55.275 0.075 ; - RECT 25.685 -0.075 25.835 0.075 ; - LAYER via2 ; - RECT 55.1 86.94 55.3 87.14 ; - RECT 25.66 86.94 25.86 87.14 ; - RECT 64.76 67.9 64.96 68.1 ; - RECT 1.74 66.54 1.94 66.74 ; - RECT 64.76 63.82 64.96 64.02 ; - RECT 1.28 61.78 1.48 61.98 ; - RECT 1.74 23.02 1.94 23.22 ; - RECT 64.76 15.54 64.96 15.74 ; - RECT 1.74 13.5 1.94 13.7 ; - RECT 55.1 -0.1 55.3 0.1 ; - RECT 25.66 -0.1 25.86 0.1 ; - LAYER via3 ; - RECT 55.1 86.94 55.3 87.14 ; - RECT 25.66 86.94 25.86 87.14 ; - RECT 55.1 -0.1 55.3 0.1 ; - RECT 25.66 -0.1 25.86 0.1 ; - LAYER OVERLAP ; - POLYGON 0 0 0 87.04 66.24 87.04 66.24 0 ; - END -END cbx_1__0_ - -END LIBRARY diff --git a/FPGA22_HIER_SKY_PNR/modules/lef/cbx_1__1__icv_in_design.lef b/FPGA22_HIER_SKY_PNR/modules/lef/cbx_1__1__icv_in_design.lef deleted file mode 100644 index 61270a5..0000000 --- a/FPGA22_HIER_SKY_PNR/modules/lef/cbx_1__1__icv_in_design.lef +++ /dev/null @@ -1,1839 +0,0 @@ -VERSION 5.7 ; -BUSBITCHARS "[]" ; - -UNITS - DATABASE MICRONS 1000 ; -END UNITS - -MANUFACTURINGGRID 0.005 ; - -LAYER li1 - TYPE ROUTING ; - DIRECTION VERTICAL ; - PITCH 0.46 ; - WIDTH 0.17 ; -END li1 - -LAYER mcon - TYPE CUT ; -END mcon - -LAYER met1 - TYPE ROUTING ; - DIRECTION HORIZONTAL ; - PITCH 0.34 ; - WIDTH 0.14 ; -END met1 - -LAYER via - TYPE CUT ; -END via - -LAYER met2 - TYPE ROUTING ; - DIRECTION VERTICAL ; - PITCH 0.46 ; - WIDTH 0.14 ; -END met2 - -LAYER via2 - TYPE CUT ; -END via2 - -LAYER met3 - TYPE ROUTING ; - DIRECTION HORIZONTAL ; - PITCH 0.68 ; - WIDTH 0.3 ; -END met3 - -LAYER via3 - TYPE CUT ; -END via3 - -LAYER met4 - TYPE ROUTING ; - DIRECTION VERTICAL ; - PITCH 0.92 ; - WIDTH 0.3 ; -END met4 - -LAYER via4 - TYPE CUT ; -END via4 - -LAYER met5 - TYPE ROUTING ; - DIRECTION HORIZONTAL ; - PITCH 3.4 ; - WIDTH 1.6 ; -END met5 - -LAYER nwell - TYPE MASTERSLICE ; -END nwell - -LAYER pwell - TYPE MASTERSLICE ; -END pwell - -LAYER OVERLAP - TYPE OVERLAP ; -END OVERLAP - -VIA L1M1_PR - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.145 -0.115 0.145 0.115 ; -END L1M1_PR - -VIA L1M1_PR_R - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.115 -0.145 0.115 0.145 ; -END L1M1_PR_R - -VIA L1M1_PR_M - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.115 -0.145 0.115 0.145 ; -END L1M1_PR_M - -VIA L1M1_PR_MR - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.145 -0.115 0.145 0.115 ; -END L1M1_PR_MR - -VIA L1M1_PR_C - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.145 -0.145 0.145 0.145 ; -END L1M1_PR_C - -VIA M1M2_PR - LAYER met1 ; - RECT -0.16 -0.13 0.16 0.13 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.13 -0.16 0.13 0.16 ; -END M1M2_PR - -VIA M1M2_PR_Enc - LAYER met1 ; - RECT -0.16 -0.13 0.16 0.13 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.16 -0.13 0.16 0.13 ; -END M1M2_PR_Enc - -VIA M1M2_PR_R - LAYER met1 ; - RECT -0.13 -0.16 0.13 0.16 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.16 -0.13 0.16 0.13 ; -END M1M2_PR_R - -VIA M1M2_PR_R_Enc - LAYER met1 ; - RECT -0.13 -0.16 0.13 0.16 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.13 -0.16 0.13 0.16 ; -END M1M2_PR_R_Enc - -VIA M1M2_PR_M - LAYER met1 ; - RECT -0.16 -0.13 0.16 0.13 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.16 -0.13 0.16 0.13 ; -END M1M2_PR_M - -VIA M1M2_PR_M_Enc - LAYER met1 ; - RECT -0.16 -0.13 0.16 0.13 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.13 -0.16 0.13 0.16 ; -END M1M2_PR_M_Enc - -VIA M1M2_PR_MR - LAYER met1 ; - RECT -0.13 -0.16 0.13 0.16 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.13 -0.16 0.13 0.16 ; -END M1M2_PR_MR - -VIA M1M2_PR_MR_Enc - LAYER met1 ; - RECT -0.13 -0.16 0.13 0.16 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.16 -0.13 0.16 0.13 ; -END M1M2_PR_MR_Enc - -VIA M1M2_PR_C - LAYER met1 ; - RECT -0.16 -0.16 0.16 0.16 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.16 -0.16 0.16 0.16 ; -END M1M2_PR_C - -VIA M2M3_PR - LAYER met2 ; - RECT -0.14 -0.185 0.14 0.185 ; - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met3 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M2M3_PR - -VIA M2M3_PR_R - LAYER met2 ; - RECT -0.185 -0.14 0.185 0.14 ; - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met3 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M2M3_PR_R - -VIA M2M3_PR_M - LAYER met2 ; - RECT -0.14 -0.185 0.14 0.185 ; - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met3 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M2M3_PR_M - -VIA M2M3_PR_MR - LAYER met2 ; - RECT -0.185 -0.14 0.185 0.14 ; - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met3 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M2M3_PR_MR - -VIA M2M3_PR_C - LAYER met2 ; - RECT -0.185 -0.185 0.185 0.185 ; - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met3 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M2M3_PR_C - -VIA M3M4_PR - LAYER met3 ; - RECT -0.19 -0.16 0.19 0.16 ; - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR - -VIA M3M4_PR_R - LAYER met3 ; - RECT -0.16 -0.19 0.16 0.19 ; - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR_R - -VIA M3M4_PR_M - LAYER met3 ; - RECT -0.19 -0.16 0.19 0.16 ; - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR_M - -VIA M3M4_PR_MR - LAYER met3 ; - RECT -0.16 -0.19 0.16 0.19 ; - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR_MR - -VIA M3M4_PR_C - LAYER met3 ; - RECT -0.19 -0.19 0.19 0.19 ; - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR_C - -VIA M4M5_PR - LAYER met4 ; - RECT -0.59 -0.59 0.59 0.59 ; - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - LAYER met5 ; - RECT -0.71 -0.71 0.71 0.71 ; -END M4M5_PR - -VIA M4M5_PR_R - LAYER met4 ; - RECT -0.59 -0.59 0.59 0.59 ; - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - LAYER met5 ; - RECT -0.71 -0.71 0.71 0.71 ; -END M4M5_PR_R - -VIA M4M5_PR_M - LAYER met4 ; - RECT -0.59 -0.59 0.59 0.59 ; - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - LAYER met5 ; - RECT -0.71 -0.71 0.71 0.71 ; -END M4M5_PR_M - -VIA M4M5_PR_MR - LAYER met4 ; - RECT -0.59 -0.59 0.59 0.59 ; - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - LAYER met5 ; - RECT -0.71 -0.71 0.71 0.71 ; -END M4M5_PR_MR - -VIA M4M5_PR_C - LAYER met4 ; - RECT -0.59 -0.59 0.59 0.59 ; - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - LAYER met5 ; - RECT -0.71 -0.71 0.71 0.71 ; -END M4M5_PR_C - -SITE unit - CLASS CORE ; - SYMMETRY Y ; - SIZE 0.46 BY 2.72 ; -END unit - -SITE unithddbl - CLASS CORE ; - SIZE 0.46 BY 5.44 ; -END unithddbl - -MACRO cbx_1__1_ - CLASS BLOCK ; - ORIGIN 0 0 ; - SIZE 66.24 BY 87.04 ; - SYMMETRY X Y ; - PIN prog_clk[0] - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER met2 ; - RECT 14.19 0 14.33 1.36 ; - END - END prog_clk[0] - PIN chanx_left_in[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 59.69 1.38 59.99 ; - END - END chanx_left_in[0] - PIN chanx_left_in[1] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 44.73 1.38 45.03 ; - END - END chanx_left_in[1] - PIN chanx_left_in[2] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 61.05 1.38 61.35 ; - END - END chanx_left_in[2] - PIN chanx_left_in[3] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 43.37 1.38 43.67 ; - END - END chanx_left_in[3] - PIN chanx_left_in[4] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 27.05 1.38 27.35 ; - END - END chanx_left_in[4] - PIN chanx_left_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 69.21 1.38 69.51 ; - END - END chanx_left_in[5] - PIN chanx_left_in[6] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 39.29 1.38 39.59 ; - END - END chanx_left_in[6] - PIN chanx_left_in[7] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 52.89 1.38 53.19 ; - END - END chanx_left_in[7] - PIN chanx_left_in[8] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 31.13 1.38 31.43 ; - END - END chanx_left_in[8] - PIN chanx_left_in[9] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 40.65 1.38 40.95 ; - END - END chanx_left_in[9] - PIN chanx_left_in[10] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 42.01 1.38 42.31 ; - END - END chanx_left_in[10] - PIN chanx_left_in[11] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 28.41 1.38 28.71 ; - END - END chanx_left_in[11] - PIN chanx_left_in[12] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 67.85 1.38 68.15 ; - END - END chanx_left_in[12] - PIN chanx_left_in[13] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 56.97 1.38 57.27 ; - END - END chanx_left_in[13] - PIN chanx_left_in[14] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 24.33 1.38 24.63 ; - END - END chanx_left_in[14] - PIN chanx_left_in[15] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 29.77 1.38 30.07 ; - END - END chanx_left_in[15] - PIN chanx_left_in[16] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 47.45 1.38 47.75 ; - END - END chanx_left_in[16] - PIN chanx_left_in[17] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 36.57 1.38 36.87 ; - END - END chanx_left_in[17] - PIN chanx_left_in[18] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 48.81 1.38 49.11 ; - END - END chanx_left_in[18] - PIN chanx_left_in[19] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 65.13 1.38 65.43 ; - END - END chanx_left_in[19] - PIN chanx_right_in[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 71.93 66.24 72.23 ; - END - END chanx_right_in[0] - PIN chanx_right_in[1] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 52.89 66.24 53.19 ; - END - END chanx_right_in[1] - PIN chanx_right_in[2] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 48.13 66.24 48.43 ; - END - END chanx_right_in[2] - PIN chanx_right_in[3] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 37.25 66.24 37.55 ; - END - END chanx_right_in[3] - PIN chanx_right_in[4] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 51.53 66.24 51.83 ; - END - END chanx_right_in[4] - PIN chanx_right_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 77.37 66.24 77.67 ; - END - END chanx_right_in[5] - PIN chanx_right_in[6] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 35.89 66.24 36.19 ; - END - END chanx_right_in[6] - PIN chanx_right_in[7] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 39.97 66.24 40.27 ; - END - END chanx_right_in[7] - PIN chanx_right_in[8] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 44.05 66.24 44.35 ; - END - END chanx_right_in[8] - PIN chanx_right_in[9] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 41.33 66.24 41.63 ; - END - END chanx_right_in[9] - PIN chanx_right_in[10] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 50.17 66.24 50.47 ; - END - END chanx_right_in[10] - PIN chanx_right_in[11] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 57.65 66.24 57.95 ; - END - END chanx_right_in[11] - PIN chanx_right_in[12] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 31.81 66.24 32.11 ; - END - END chanx_right_in[12] - PIN chanx_right_in[13] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 80.09 66.24 80.39 ; - END - END chanx_right_in[13] - PIN chanx_right_in[14] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 22.29 66.24 22.59 ; - END - END chanx_right_in[14] - PIN chanx_right_in[15] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 67.85 66.24 68.15 ; - END - END chanx_right_in[15] - PIN chanx_right_in[16] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 59.01 66.24 59.31 ; - END - END chanx_right_in[16] - PIN chanx_right_in[17] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 29.09 66.24 29.39 ; - END - END chanx_right_in[17] - PIN chanx_right_in[18] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 42.69 66.24 42.99 ; - END - END chanx_right_in[18] - PIN chanx_right_in[19] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 69.21 66.24 69.51 ; - END - END chanx_right_in[19] - PIN ccff_head[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 65.81 66.24 66.11 ; - END - END ccff_head[0] - PIN chanx_left_out[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 55.61 1.38 55.91 ; - END - END chanx_left_out[0] - PIN chanx_left_out[1] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 71.93 1.38 72.23 ; - END - END chanx_left_out[1] - PIN chanx_left_out[2] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 81.45 1.38 81.75 ; - END - END chanx_left_out[2] - PIN chanx_left_out[3] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 25.69 1.38 25.99 ; - END - END chanx_left_out[3] - PIN chanx_left_out[4] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 63.77 1.38 64.07 ; - END - END chanx_left_out[4] - PIN chanx_left_out[5] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 66.49 1.38 66.79 ; - END - END chanx_left_out[5] - PIN chanx_left_out[6] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 22.97 1.38 23.27 ; - END - END chanx_left_out[6] - PIN chanx_left_out[7] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 35.21 1.38 35.51 ; - END - END chanx_left_out[7] - PIN chanx_left_out[8] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 46.09 1.38 46.39 ; - END - END chanx_left_out[8] - PIN chanx_left_out[9] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 62.41 1.38 62.71 ; - END - END chanx_left_out[9] - PIN chanx_left_out[10] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 73.29 1.38 73.59 ; - END - END chanx_left_out[10] - PIN chanx_left_out[11] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 80.09 1.38 80.39 ; - END - END chanx_left_out[11] - PIN chanx_left_out[12] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 70.57 1.38 70.87 ; - END - END chanx_left_out[12] - PIN chanx_left_out[13] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 33.85 1.38 34.15 ; - END - END chanx_left_out[13] - PIN chanx_left_out[14] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 20.93 1.38 21.23 ; - END - END chanx_left_out[14] - PIN chanx_left_out[15] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 50.85 1.38 51.15 ; - END - END chanx_left_out[15] - PIN chanx_left_out[16] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 54.25 1.38 54.55 ; - END - END chanx_left_out[16] - PIN chanx_left_out[17] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 37.93 1.38 38.23 ; - END - END chanx_left_out[17] - PIN chanx_left_out[18] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 58.33 1.38 58.63 ; - END - END chanx_left_out[18] - PIN chanx_left_out[19] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 78.73 1.38 79.03 ; - END - END chanx_left_out[19] - PIN chanx_right_out[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 55.61 66.24 55.91 ; - END - END chanx_right_out[0] - PIN chanx_right_out[1] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 73.29 66.24 73.59 ; - END - END chanx_right_out[1] - PIN chanx_right_out[2] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 74.65 66.24 74.95 ; - END - END chanx_right_out[2] - PIN chanx_right_out[3] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 26.37 66.24 26.67 ; - END - END chanx_right_out[3] - PIN chanx_right_out[4] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 33.17 66.24 33.47 ; - END - END chanx_right_out[4] - PIN chanx_right_out[5] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 20.93 66.24 21.23 ; - END - END chanx_right_out[5] - PIN chanx_right_out[6] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 78.73 66.24 79.03 ; - END - END chanx_right_out[6] - PIN chanx_right_out[7] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 54.25 66.24 54.55 ; - END - END chanx_right_out[7] - PIN chanx_right_out[8] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 46.09 66.24 46.39 ; - END - END chanx_right_out[8] - PIN chanx_right_out[9] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 70.57 66.24 70.87 ; - END - END chanx_right_out[9] - PIN chanx_right_out[10] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 38.61 66.24 38.91 ; - END - END chanx_right_out[10] - PIN chanx_right_out[11] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 64.45 66.24 64.75 ; - END - END chanx_right_out[11] - PIN chanx_right_out[12] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 81.45 66.24 81.75 ; - END - END chanx_right_out[12] - PIN chanx_right_out[13] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 34.53 66.24 34.83 ; - END - END chanx_right_out[13] - PIN chanx_right_out[14] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 76.01 66.24 76.31 ; - END - END chanx_right_out[14] - PIN chanx_right_out[15] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 60.37 66.24 60.67 ; - END - END chanx_right_out[15] - PIN chanx_right_out[16] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 30.45 66.24 30.75 ; - END - END chanx_right_out[16] - PIN chanx_right_out[17] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 27.73 66.24 28.03 ; - END - END chanx_right_out[17] - PIN chanx_right_out[18] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 63.09 66.24 63.39 ; - END - END chanx_right_out[18] - PIN chanx_right_out[19] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 61.73 66.24 62.03 ; - END - END chanx_right_out[19] - PIN bottom_grid_pin_0_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 36.73 0 36.87 1.36 ; - END - END bottom_grid_pin_0_[0] - PIN bottom_grid_pin_1_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 17.87 0 18.01 1.36 ; - END - END bottom_grid_pin_1_[0] - PIN bottom_grid_pin_2_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 12.81 0 12.95 1.36 ; - END - END bottom_grid_pin_2_[0] - PIN bottom_grid_pin_3_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 11.89 0 12.03 1.36 ; - END - END bottom_grid_pin_3_[0] - PIN bottom_grid_pin_4_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 37.65 0 37.79 1.36 ; - END - END bottom_grid_pin_4_[0] - PIN bottom_grid_pin_5_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 40.41 0 40.55 1.36 ; - END - END bottom_grid_pin_5_[0] - PIN bottom_grid_pin_6_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 38.57 0 38.71 1.36 ; - END - END bottom_grid_pin_6_[0] - PIN bottom_grid_pin_7_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 39.49 0 39.63 1.36 ; - END - END bottom_grid_pin_7_[0] - PIN bottom_grid_pin_8_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 2.23 0 2.37 1.36 ; - END - END bottom_grid_pin_8_[0] - PIN bottom_grid_pin_9_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 10.05 0 10.19 1.36 ; - END - END bottom_grid_pin_9_[0] - PIN bottom_grid_pin_10_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 10.97 0 11.11 1.36 ; - END - END bottom_grid_pin_10_[0] - PIN bottom_grid_pin_11_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 19.71 0 19.85 1.36 ; - END - END bottom_grid_pin_11_[0] - PIN bottom_grid_pin_12_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 34.89 0 35.03 1.36 ; - END - END bottom_grid_pin_12_[0] - PIN bottom_grid_pin_13_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 18.79 0 18.93 1.36 ; - END - END bottom_grid_pin_13_[0] - PIN bottom_grid_pin_14_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 16.03 0 16.17 1.36 ; - END - END bottom_grid_pin_14_[0] - PIN bottom_grid_pin_15_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 35.81 0 35.95 1.36 ; - END - END bottom_grid_pin_15_[0] - PIN ccff_tail[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 32.49 1.38 32.79 ; - END - END ccff_tail[0] - PIN SC_IN_TOP - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 63.87 85.68 64.01 87.04 ; - END - END SC_IN_TOP - PIN SC_IN_BOT - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 62.95 0 63.09 1.36 ; - END - END SC_IN_BOT - PIN SC_OUT_TOP - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 14.19 85.68 14.33 87.04 ; - END - END SC_OUT_TOP - PIN SC_OUT_BOT - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 16.95 0 17.09 1.36 ; - END - END SC_OUT_BOT - PIN VDD - DIRECTION INPUT ; - USE POWER ; - PORT - LAYER met4 ; - RECT 10.74 0 11.34 0.6 ; - RECT 40.18 0 40.78 0.6 ; - RECT 10.74 86.44 11.34 87.04 ; - RECT 40.18 86.44 40.78 87.04 ; - LAYER met5 ; - RECT 0 11.32 3.2 14.52 ; - RECT 63.04 11.32 66.24 14.52 ; - RECT 0 52.12 3.2 55.32 ; - RECT 63.04 52.12 66.24 55.32 ; - LAYER met1 ; - RECT 0 2.48 0.48 2.96 ; - RECT 65.76 2.48 66.24 2.96 ; - RECT 0 7.92 0.48 8.4 ; - RECT 65.76 7.92 66.24 8.4 ; - RECT 0 13.36 0.48 13.84 ; - RECT 65.76 13.36 66.24 13.84 ; - RECT 0 18.8 0.48 19.28 ; - RECT 65.76 18.8 66.24 19.28 ; - RECT 0 24.24 0.48 24.72 ; - RECT 65.76 24.24 66.24 24.72 ; - RECT 0 29.68 0.48 30.16 ; - RECT 65.76 29.68 66.24 30.16 ; - RECT 0 35.12 0.48 35.6 ; - RECT 65.76 35.12 66.24 35.6 ; - RECT 0 40.56 0.48 41.04 ; - RECT 65.76 40.56 66.24 41.04 ; - RECT 0 46 0.48 46.48 ; - RECT 65.76 46 66.24 46.48 ; - RECT 0 51.44 0.48 51.92 ; - RECT 65.76 51.44 66.24 51.92 ; - RECT 0 56.88 0.48 57.36 ; - RECT 65.76 56.88 66.24 57.36 ; - RECT 0 62.32 0.48 62.8 ; - RECT 65.76 62.32 66.24 62.8 ; - RECT 0 67.76 0.48 68.24 ; - RECT 65.76 67.76 66.24 68.24 ; - RECT 0 73.2 0.48 73.68 ; - RECT 65.76 73.2 66.24 73.68 ; - RECT 0 78.64 0.48 79.12 ; - RECT 65.76 78.64 66.24 79.12 ; - RECT 0 84.08 0.48 84.56 ; - RECT 65.76 84.08 66.24 84.56 ; - END - END VDD - PIN VSS - DIRECTION INPUT ; - USE GROUND ; - PORT - LAYER met4 ; - RECT 25.46 0 26.06 0.6 ; - RECT 54.9 0 55.5 0.6 ; - RECT 25.46 86.44 26.06 87.04 ; - RECT 54.9 86.44 55.5 87.04 ; - LAYER met5 ; - RECT 0 31.72 3.2 34.92 ; - RECT 63.04 31.72 66.24 34.92 ; - RECT 0 72.52 3.2 75.72 ; - RECT 63.04 72.52 66.24 75.72 ; - LAYER met1 ; - RECT 0 0 66.24 0.24 ; - RECT 0 5.2 0.48 5.68 ; - RECT 65.76 5.2 66.24 5.68 ; - RECT 0 10.64 0.48 11.12 ; - RECT 65.76 10.64 66.24 11.12 ; - RECT 0 16.08 0.48 16.56 ; - RECT 65.76 16.08 66.24 16.56 ; - RECT 0 21.52 0.48 22 ; - RECT 65.76 21.52 66.24 22 ; - RECT 0 26.96 0.48 27.44 ; - RECT 65.76 26.96 66.24 27.44 ; - RECT 0 32.4 0.48 32.88 ; - RECT 65.76 32.4 66.24 32.88 ; - RECT 0 37.84 0.48 38.32 ; - RECT 65.76 37.84 66.24 38.32 ; - RECT 0 43.28 0.48 43.76 ; - RECT 65.76 43.28 66.24 43.76 ; - RECT 0 48.72 0.48 49.2 ; - RECT 65.76 48.72 66.24 49.2 ; - RECT 0 54.16 0.48 54.64 ; - RECT 65.76 54.16 66.24 54.64 ; - RECT 0 59.6 0.48 60.08 ; - RECT 65.76 59.6 66.24 60.08 ; - RECT 0 65.04 0.48 65.52 ; - RECT 65.76 65.04 66.24 65.52 ; - RECT 0 70.48 0.48 70.96 ; - RECT 65.76 70.48 66.24 70.96 ; - RECT 0 75.92 0.48 76.4 ; - RECT 65.76 75.92 66.24 76.4 ; - RECT 0 81.36 0.48 81.84 ; - RECT 65.76 81.36 66.24 81.84 ; - RECT 0 86.8 66.24 87.04 ; - END - END VSS - PIN prog_clk__FEEDTHRU_1[0] - DIRECTION OUTPUT ; - USE CLOCK ; - PORT - LAYER met3 ; - RECT 64.86 24.33 66.24 24.63 ; - END - END prog_clk__FEEDTHRU_1[0] - OBS - LAYER li1 ; - RECT 0 86.955 66.24 87.125 ; - RECT 65.32 84.235 66.24 84.405 ; - RECT 0 84.235 3.68 84.405 ; - RECT 65.32 81.515 66.24 81.685 ; - RECT 0 81.515 1.84 81.685 ; - RECT 65.32 78.795 66.24 78.965 ; - RECT 0 78.795 1.84 78.965 ; - RECT 65.32 76.075 66.24 76.245 ; - RECT 0 76.075 1.84 76.245 ; - RECT 65.32 73.355 66.24 73.525 ; - RECT 0 73.355 1.84 73.525 ; - RECT 65.32 70.635 66.24 70.805 ; - RECT 0 70.635 1.84 70.805 ; - RECT 65.32 67.915 66.24 68.085 ; - RECT 0 67.915 1.84 68.085 ; - RECT 65.32 65.195 66.24 65.365 ; - RECT 0 65.195 1.84 65.365 ; - RECT 65.32 62.475 66.24 62.645 ; - RECT 0 62.475 1.84 62.645 ; - RECT 65.32 59.755 66.24 59.925 ; - RECT 0 59.755 1.84 59.925 ; - RECT 65.32 57.035 66.24 57.205 ; - RECT 0 57.035 1.84 57.205 ; - RECT 65.32 54.315 66.24 54.485 ; - RECT 0 54.315 1.84 54.485 ; - RECT 65.32 51.595 66.24 51.765 ; - RECT 0 51.595 1.84 51.765 ; - RECT 65.32 48.875 66.24 49.045 ; - RECT 0 48.875 1.84 49.045 ; - RECT 62.56 46.155 66.24 46.325 ; - RECT 0 46.155 1.84 46.325 ; - RECT 62.56 43.435 66.24 43.605 ; - RECT 0 43.435 1.84 43.605 ; - RECT 65.32 40.715 66.24 40.885 ; - RECT 0 40.715 1.84 40.885 ; - RECT 65.32 37.995 66.24 38.165 ; - RECT 0 37.995 1.84 38.165 ; - RECT 65.32 35.275 66.24 35.445 ; - RECT 0 35.275 1.84 35.445 ; - RECT 65.32 32.555 66.24 32.725 ; - RECT 0 32.555 1.84 32.725 ; - RECT 65.32 29.835 66.24 30.005 ; - RECT 0 29.835 1.84 30.005 ; - RECT 65.32 27.115 66.24 27.285 ; - RECT 0 27.115 1.84 27.285 ; - RECT 65.32 24.395 66.24 24.565 ; - RECT 0 24.395 1.84 24.565 ; - RECT 65.32 21.675 66.24 21.845 ; - RECT 0 21.675 1.84 21.845 ; - RECT 65.32 18.955 66.24 19.125 ; - RECT 0 18.955 3.68 19.125 ; - RECT 65.32 16.235 66.24 16.405 ; - RECT 0 16.235 3.68 16.405 ; - RECT 65.32 13.515 66.24 13.685 ; - RECT 0 13.515 3.68 13.685 ; - RECT 65.32 10.795 66.24 10.965 ; - RECT 0 10.795 1.84 10.965 ; - RECT 65.32 8.075 66.24 8.245 ; - RECT 0 8.075 3.68 8.245 ; - RECT 65.32 5.355 66.24 5.525 ; - RECT 0 5.355 3.68 5.525 ; - RECT 65.78 2.635 66.24 2.805 ; - RECT 0 2.635 3.68 2.805 ; - RECT 0 -0.085 66.24 0.085 ; - LAYER met2 ; - RECT 55.06 86.855 55.34 87.225 ; - RECT 25.62 86.855 25.9 87.225 ; - RECT 55.06 -0.185 55.34 0.185 ; - RECT 25.62 -0.185 25.9 0.185 ; - POLYGON 65.96 86.76 65.96 0.28 63.37 0.28 63.37 1.64 62.67 1.64 62.67 0.28 40.83 0.28 40.83 1.64 40.13 1.64 40.13 0.28 39.91 0.28 39.91 1.64 39.21 1.64 39.21 0.28 38.99 0.28 38.99 1.64 38.29 1.64 38.29 0.28 38.07 0.28 38.07 1.64 37.37 1.64 37.37 0.28 37.15 0.28 37.15 1.64 36.45 1.64 36.45 0.28 36.23 0.28 36.23 1.64 35.53 1.64 35.53 0.28 35.31 0.28 35.31 1.64 34.61 1.64 34.61 0.28 20.13 0.28 20.13 1.64 19.43 1.64 19.43 0.28 19.21 0.28 19.21 1.64 18.51 1.64 18.51 0.28 18.29 0.28 18.29 1.64 17.59 1.64 17.59 0.28 17.37 0.28 17.37 1.64 16.67 1.64 16.67 0.28 16.45 0.28 16.45 1.64 15.75 1.64 15.75 0.28 14.61 0.28 14.61 1.64 13.91 1.64 13.91 0.28 13.23 0.28 13.23 1.64 12.53 1.64 12.53 0.28 12.31 0.28 12.31 1.64 11.61 1.64 11.61 0.28 11.39 0.28 11.39 1.64 10.69 1.64 10.69 0.28 10.47 0.28 10.47 1.64 9.77 1.64 9.77 0.28 2.65 0.28 2.65 1.64 1.95 1.64 1.95 0.28 0.28 0.28 0.28 86.76 13.91 86.76 13.91 85.4 14.61 85.4 14.61 86.76 63.59 86.76 63.59 85.4 64.29 85.4 64.29 86.76 ; - LAYER met3 ; - POLYGON 55.365 87.205 55.365 87.2 55.58 87.2 55.58 86.88 55.365 86.88 55.365 86.875 55.035 86.875 55.035 86.88 54.82 86.88 54.82 87.2 55.035 87.2 55.035 87.205 ; - POLYGON 25.925 87.205 25.925 87.2 26.14 87.2 26.14 86.88 25.925 86.88 25.925 86.875 25.595 86.875 25.595 86.88 25.38 86.88 25.38 87.2 25.595 87.2 25.595 87.205 ; - POLYGON 2.03 78.36 2.03 78.35 4.29 78.35 4.29 78.05 2.03 78.05 2.03 78.04 1.65 78.04 1.65 78.36 ; - POLYGON 7.51 71.55 7.51 71.25 1.78 71.25 1.78 71.27 1.23 71.27 1.23 71.55 ; - POLYGON 24.07 68.83 24.07 68.53 1.78 68.53 1.78 68.55 1.23 68.55 1.23 68.83 ; - POLYGON 65.01 64.07 65.01 63.79 64.46 63.79 64.46 63.77 61.95 63.77 61.95 64.07 ; - POLYGON 11.65 55.23 11.65 54.93 1.78 54.93 1.78 54.95 1.08 54.95 1.08 55.23 ; - POLYGON 3.37 48.43 3.37 48.13 1.99 48.13 1.99 47.45 1.78 47.45 1.78 48.15 1.69 48.15 1.69 48.43 ; - POLYGON 2.03 40.28 2.03 40.27 11.65 40.27 11.65 39.97 2.03 39.97 2.03 39.96 1.65 39.96 1.65 40.28 ; - POLYGON 1.99 39.59 1.99 38.91 18.09 38.91 18.09 38.61 1.69 38.61 1.69 38.89 1.78 38.89 1.78 39.59 ; - POLYGON 1.545 36.205 1.545 36.19 50.75 36.19 50.75 35.89 1.545 35.89 1.545 35.875 1.215 35.875 1.215 36.205 ; - POLYGON 23.15 30.75 23.15 30.45 1.23 30.45 1.23 30.73 1.78 30.73 1.78 30.75 ; - POLYGON 10.73 23.95 10.73 23.65 1.99 23.65 1.99 23.27 2.91 23.27 2.91 22.97 1.78 22.97 1.78 23.67 1.69 23.67 1.69 23.95 ; - POLYGON 55.365 0.165 55.365 0.16 55.58 0.16 55.58 -0.16 55.365 -0.16 55.365 -0.165 55.035 -0.165 55.035 -0.16 54.82 -0.16 54.82 0.16 55.035 0.16 55.035 0.165 ; - POLYGON 25.925 0.165 25.925 0.16 26.14 0.16 26.14 -0.16 25.925 -0.16 25.925 -0.165 25.595 -0.165 25.595 -0.16 25.38 -0.16 25.38 0.16 25.595 0.16 25.595 0.165 ; - POLYGON 65.84 86.64 65.84 82.15 64.46 82.15 64.46 81.05 65.84 81.05 65.84 80.79 64.46 80.79 64.46 79.69 65.84 79.69 65.84 79.43 64.46 79.43 64.46 78.33 65.84 78.33 65.84 78.07 64.46 78.07 64.46 76.97 65.84 76.97 65.84 76.71 64.46 76.71 64.46 75.61 65.84 75.61 65.84 75.35 64.46 75.35 64.46 74.25 65.84 74.25 65.84 73.99 64.46 73.99 64.46 72.89 65.84 72.89 65.84 72.63 64.46 72.63 64.46 71.53 65.84 71.53 65.84 71.27 64.46 71.27 64.46 70.17 65.84 70.17 65.84 69.91 64.46 69.91 64.46 68.81 65.84 68.81 65.84 68.55 64.46 68.55 64.46 67.45 65.84 67.45 65.84 66.51 64.46 66.51 64.46 65.41 65.84 65.41 65.84 65.15 64.46 65.15 64.46 64.05 65.84 64.05 65.84 63.79 64.46 63.79 64.46 62.69 65.84 62.69 65.84 62.43 64.46 62.43 64.46 61.33 65.84 61.33 65.84 61.07 64.46 61.07 64.46 59.97 65.84 59.97 65.84 59.71 64.46 59.71 64.46 58.61 65.84 58.61 65.84 58.35 64.46 58.35 64.46 57.25 65.84 57.25 65.84 56.31 64.46 56.31 64.46 55.21 65.84 55.21 65.84 54.95 64.46 54.95 64.46 53.85 65.84 53.85 65.84 53.59 64.46 53.59 64.46 52.49 65.84 52.49 65.84 52.23 64.46 52.23 64.46 51.13 65.84 51.13 65.84 50.87 64.46 50.87 64.46 49.77 65.84 49.77 65.84 48.83 64.46 48.83 64.46 47.73 65.84 47.73 65.84 46.79 64.46 46.79 64.46 45.69 65.84 45.69 65.84 44.75 64.46 44.75 64.46 43.65 65.84 43.65 65.84 43.39 64.46 43.39 64.46 42.29 65.84 42.29 65.84 42.03 64.46 42.03 64.46 40.93 65.84 40.93 65.84 40.67 64.46 40.67 64.46 39.57 65.84 39.57 65.84 39.31 64.46 39.31 64.46 38.21 65.84 38.21 65.84 37.95 64.46 37.95 64.46 36.85 65.84 36.85 65.84 36.59 64.46 36.59 64.46 35.49 65.84 35.49 65.84 35.23 64.46 35.23 64.46 34.13 65.84 34.13 65.84 33.87 64.46 33.87 64.46 32.77 65.84 32.77 65.84 32.51 64.46 32.51 64.46 31.41 65.84 31.41 65.84 31.15 64.46 31.15 64.46 30.05 65.84 30.05 65.84 29.79 64.46 29.79 64.46 28.69 65.84 28.69 65.84 28.43 64.46 28.43 64.46 27.33 65.84 27.33 65.84 27.07 64.46 27.07 64.46 25.97 65.84 25.97 65.84 25.03 64.46 25.03 64.46 23.93 65.84 23.93 65.84 22.99 64.46 22.99 64.46 21.89 65.84 21.89 65.84 21.63 64.46 21.63 64.46 20.53 65.84 20.53 65.84 0.4 0.4 0.4 0.4 20.53 1.78 20.53 1.78 21.63 0.4 21.63 0.4 22.57 1.78 22.57 1.78 23.67 0.4 23.67 0.4 23.93 1.78 23.93 1.78 25.03 0.4 25.03 0.4 25.29 1.78 25.29 1.78 26.39 0.4 26.39 0.4 26.65 1.78 26.65 1.78 27.75 0.4 27.75 0.4 28.01 1.78 28.01 1.78 29.11 0.4 29.11 0.4 29.37 1.78 29.37 1.78 30.47 0.4 30.47 0.4 30.73 1.78 30.73 1.78 31.83 0.4 31.83 0.4 32.09 1.78 32.09 1.78 33.19 0.4 33.19 0.4 33.45 1.78 33.45 1.78 34.55 0.4 34.55 0.4 34.81 1.78 34.81 1.78 35.91 0.4 35.91 0.4 36.17 1.78 36.17 1.78 37.27 0.4 37.27 0.4 37.53 1.78 37.53 1.78 38.63 0.4 38.63 0.4 38.89 1.78 38.89 1.78 39.99 0.4 39.99 0.4 40.25 1.78 40.25 1.78 41.35 0.4 41.35 0.4 41.61 1.78 41.61 1.78 42.71 0.4 42.71 0.4 42.97 1.78 42.97 1.78 44.07 0.4 44.07 0.4 44.33 1.78 44.33 1.78 45.43 0.4 45.43 0.4 45.69 1.78 45.69 1.78 46.79 0.4 46.79 0.4 47.05 1.78 47.05 1.78 48.15 0.4 48.15 0.4 48.41 1.78 48.41 1.78 49.51 0.4 49.51 0.4 50.45 1.78 50.45 1.78 51.55 0.4 51.55 0.4 52.49 1.78 52.49 1.78 53.59 0.4 53.59 0.4 53.85 1.78 53.85 1.78 54.95 0.4 54.95 0.4 55.21 1.78 55.21 1.78 56.31 0.4 56.31 0.4 56.57 1.78 56.57 1.78 57.67 0.4 57.67 0.4 57.93 1.78 57.93 1.78 59.03 0.4 59.03 0.4 59.29 1.78 59.29 1.78 60.39 0.4 60.39 0.4 60.65 1.78 60.65 1.78 61.75 0.4 61.75 0.4 62.01 1.78 62.01 1.78 63.11 0.4 63.11 0.4 63.37 1.78 63.37 1.78 64.47 0.4 64.47 0.4 64.73 1.78 64.73 1.78 65.83 0.4 65.83 0.4 66.09 1.78 66.09 1.78 67.19 0.4 67.19 0.4 67.45 1.78 67.45 1.78 68.55 0.4 68.55 0.4 68.81 1.78 68.81 1.78 69.91 0.4 69.91 0.4 70.17 1.78 70.17 1.78 71.27 0.4 71.27 0.4 71.53 1.78 71.53 1.78 72.63 0.4 72.63 0.4 72.89 1.78 72.89 1.78 73.99 0.4 73.99 0.4 78.33 1.78 78.33 1.78 79.43 0.4 79.43 0.4 79.69 1.78 79.69 1.78 80.79 0.4 80.79 0.4 81.05 1.78 81.05 1.78 82.15 0.4 82.15 0.4 86.64 ; - LAYER met1 ; - POLYGON 65.96 86.52 65.96 84.84 65.48 84.84 65.48 83.8 65.96 83.8 65.96 82.12 65.48 82.12 65.48 81.08 65.96 81.08 65.96 79.4 65.48 79.4 65.48 78.36 65.96 78.36 65.96 76.68 65.48 76.68 65.48 75.64 65.96 75.64 65.96 73.96 65.48 73.96 65.48 72.92 65.96 72.92 65.96 71.24 65.48 71.24 65.48 70.2 65.96 70.2 65.96 68.52 65.48 68.52 65.48 67.48 65.96 67.48 65.96 65.8 65.48 65.8 65.48 64.76 65.96 64.76 65.96 63.08 65.48 63.08 65.48 62.04 65.96 62.04 65.96 60.36 65.48 60.36 65.48 59.32 65.96 59.32 65.96 57.64 65.48 57.64 65.48 56.6 65.96 56.6 65.96 54.92 65.48 54.92 65.48 53.88 65.96 53.88 65.96 52.2 65.48 52.2 65.48 51.16 65.96 51.16 65.96 49.48 65.48 49.48 65.48 48.44 65.96 48.44 65.96 46.76 65.48 46.76 65.48 45.72 65.96 45.72 65.96 44.04 65.48 44.04 65.48 43 65.96 43 65.96 41.32 65.48 41.32 65.48 40.28 65.96 40.28 65.96 38.6 65.48 38.6 65.48 37.56 65.96 37.56 65.96 35.88 65.48 35.88 65.48 34.84 65.96 34.84 65.96 33.16 65.48 33.16 65.48 32.12 65.96 32.12 65.96 30.44 65.48 30.44 65.48 29.4 65.96 29.4 65.96 27.72 65.48 27.72 65.48 26.68 65.96 26.68 65.96 25 65.48 25 65.48 23.96 65.96 23.96 65.96 22.28 65.48 22.28 65.48 21.24 65.96 21.24 65.96 19.56 65.48 19.56 65.48 18.52 65.96 18.52 65.96 16.84 65.48 16.84 65.48 15.8 65.96 15.8 65.96 14.12 65.48 14.12 65.48 13.08 65.96 13.08 65.96 11.4 65.48 11.4 65.48 10.36 65.96 10.36 65.96 8.68 65.48 8.68 65.48 7.64 65.96 7.64 65.96 5.96 65.48 5.96 65.48 4.92 65.96 4.92 65.96 3.24 65.48 3.24 65.48 2.2 65.96 2.2 65.96 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 0.76 10.36 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 0.76 81.08 0.76 82.12 0.28 82.12 0.28 83.8 0.76 83.8 0.76 84.84 0.28 84.84 0.28 86.52 ; - LAYER met5 ; - POLYGON 64.64 85.44 64.64 77.32 61.44 77.32 61.44 70.92 64.64 70.92 64.64 56.92 61.44 56.92 61.44 50.52 64.64 50.52 64.64 36.52 61.44 36.52 61.44 30.12 64.64 30.12 64.64 16.12 61.44 16.12 61.44 9.72 64.64 9.72 64.64 1.6 1.6 1.6 1.6 9.72 4.8 9.72 4.8 16.12 1.6 16.12 1.6 30.12 4.8 30.12 4.8 36.52 1.6 36.52 1.6 50.52 4.8 50.52 4.8 56.92 1.6 56.92 1.6 70.92 4.8 70.92 4.8 77.32 1.6 77.32 1.6 85.44 ; - LAYER met4 ; - POLYGON 65.84 86.64 65.84 0.4 55.9 0.4 55.9 1 54.5 1 54.5 0.4 41.18 0.4 41.18 1 39.78 1 39.78 0.4 26.46 0.4 26.46 1 25.06 1 25.06 0.4 11.74 0.4 11.74 1 10.34 1 10.34 0.4 0.4 0.4 0.4 86.64 10.34 86.64 10.34 86.04 11.74 86.04 11.74 86.64 25.06 86.64 25.06 86.04 26.46 86.04 26.46 86.64 39.78 86.64 39.78 86.04 41.18 86.04 41.18 86.64 54.5 86.64 54.5 86.04 55.9 86.04 55.9 86.64 ; - LAYER li1 ; - RECT 0.17 0.17 66.07 86.87 ; - LAYER mcon ; - RECT 65.925 86.955 66.095 87.125 ; - RECT 65.465 86.955 65.635 87.125 ; - RECT 65.005 86.955 65.175 87.125 ; - RECT 64.545 86.955 64.715 87.125 ; - RECT 64.085 86.955 64.255 87.125 ; - RECT 63.625 86.955 63.795 87.125 ; - RECT 63.165 86.955 63.335 87.125 ; - RECT 62.705 86.955 62.875 87.125 ; - RECT 62.245 86.955 62.415 87.125 ; - RECT 61.785 86.955 61.955 87.125 ; - RECT 61.325 86.955 61.495 87.125 ; - RECT 60.865 86.955 61.035 87.125 ; - RECT 60.405 86.955 60.575 87.125 ; - RECT 59.945 86.955 60.115 87.125 ; - RECT 59.485 86.955 59.655 87.125 ; - RECT 59.025 86.955 59.195 87.125 ; - RECT 58.565 86.955 58.735 87.125 ; - RECT 58.105 86.955 58.275 87.125 ; - RECT 57.645 86.955 57.815 87.125 ; - RECT 57.185 86.955 57.355 87.125 ; - RECT 56.725 86.955 56.895 87.125 ; - RECT 56.265 86.955 56.435 87.125 ; - RECT 55.805 86.955 55.975 87.125 ; - RECT 55.345 86.955 55.515 87.125 ; - RECT 54.885 86.955 55.055 87.125 ; - RECT 54.425 86.955 54.595 87.125 ; - RECT 53.965 86.955 54.135 87.125 ; - RECT 53.505 86.955 53.675 87.125 ; - RECT 53.045 86.955 53.215 87.125 ; - RECT 52.585 86.955 52.755 87.125 ; - RECT 52.125 86.955 52.295 87.125 ; - RECT 51.665 86.955 51.835 87.125 ; - RECT 51.205 86.955 51.375 87.125 ; - RECT 50.745 86.955 50.915 87.125 ; - RECT 50.285 86.955 50.455 87.125 ; - RECT 49.825 86.955 49.995 87.125 ; - RECT 49.365 86.955 49.535 87.125 ; - RECT 48.905 86.955 49.075 87.125 ; - RECT 48.445 86.955 48.615 87.125 ; - RECT 47.985 86.955 48.155 87.125 ; - RECT 47.525 86.955 47.695 87.125 ; - RECT 47.065 86.955 47.235 87.125 ; - RECT 46.605 86.955 46.775 87.125 ; - RECT 46.145 86.955 46.315 87.125 ; - RECT 45.685 86.955 45.855 87.125 ; - RECT 45.225 86.955 45.395 87.125 ; - RECT 44.765 86.955 44.935 87.125 ; - RECT 44.305 86.955 44.475 87.125 ; - RECT 43.845 86.955 44.015 87.125 ; - RECT 43.385 86.955 43.555 87.125 ; - RECT 42.925 86.955 43.095 87.125 ; - RECT 42.465 86.955 42.635 87.125 ; - RECT 42.005 86.955 42.175 87.125 ; - RECT 41.545 86.955 41.715 87.125 ; - RECT 41.085 86.955 41.255 87.125 ; - RECT 40.625 86.955 40.795 87.125 ; - RECT 40.165 86.955 40.335 87.125 ; - RECT 39.705 86.955 39.875 87.125 ; - RECT 39.245 86.955 39.415 87.125 ; - RECT 38.785 86.955 38.955 87.125 ; - RECT 38.325 86.955 38.495 87.125 ; - RECT 37.865 86.955 38.035 87.125 ; - RECT 37.405 86.955 37.575 87.125 ; - RECT 36.945 86.955 37.115 87.125 ; - RECT 36.485 86.955 36.655 87.125 ; - RECT 36.025 86.955 36.195 87.125 ; - RECT 35.565 86.955 35.735 87.125 ; - RECT 35.105 86.955 35.275 87.125 ; - RECT 34.645 86.955 34.815 87.125 ; - RECT 34.185 86.955 34.355 87.125 ; - RECT 33.725 86.955 33.895 87.125 ; - RECT 33.265 86.955 33.435 87.125 ; - RECT 32.805 86.955 32.975 87.125 ; - RECT 32.345 86.955 32.515 87.125 ; - RECT 31.885 86.955 32.055 87.125 ; - RECT 31.425 86.955 31.595 87.125 ; - RECT 30.965 86.955 31.135 87.125 ; - RECT 30.505 86.955 30.675 87.125 ; - RECT 30.045 86.955 30.215 87.125 ; - RECT 29.585 86.955 29.755 87.125 ; - RECT 29.125 86.955 29.295 87.125 ; - RECT 28.665 86.955 28.835 87.125 ; - RECT 28.205 86.955 28.375 87.125 ; - RECT 27.745 86.955 27.915 87.125 ; - RECT 27.285 86.955 27.455 87.125 ; - RECT 26.825 86.955 26.995 87.125 ; - RECT 26.365 86.955 26.535 87.125 ; - RECT 25.905 86.955 26.075 87.125 ; - RECT 25.445 86.955 25.615 87.125 ; - RECT 24.985 86.955 25.155 87.125 ; - RECT 24.525 86.955 24.695 87.125 ; - RECT 24.065 86.955 24.235 87.125 ; - RECT 23.605 86.955 23.775 87.125 ; - RECT 23.145 86.955 23.315 87.125 ; - RECT 22.685 86.955 22.855 87.125 ; - RECT 22.225 86.955 22.395 87.125 ; - RECT 21.765 86.955 21.935 87.125 ; - RECT 21.305 86.955 21.475 87.125 ; - RECT 20.845 86.955 21.015 87.125 ; - RECT 20.385 86.955 20.555 87.125 ; - RECT 19.925 86.955 20.095 87.125 ; - RECT 19.465 86.955 19.635 87.125 ; - RECT 19.005 86.955 19.175 87.125 ; - RECT 18.545 86.955 18.715 87.125 ; - RECT 18.085 86.955 18.255 87.125 ; - RECT 17.625 86.955 17.795 87.125 ; - RECT 17.165 86.955 17.335 87.125 ; - RECT 16.705 86.955 16.875 87.125 ; - RECT 16.245 86.955 16.415 87.125 ; - RECT 15.785 86.955 15.955 87.125 ; - RECT 15.325 86.955 15.495 87.125 ; - RECT 14.865 86.955 15.035 87.125 ; - RECT 14.405 86.955 14.575 87.125 ; - RECT 13.945 86.955 14.115 87.125 ; - RECT 13.485 86.955 13.655 87.125 ; - RECT 13.025 86.955 13.195 87.125 ; - RECT 12.565 86.955 12.735 87.125 ; - RECT 12.105 86.955 12.275 87.125 ; - RECT 11.645 86.955 11.815 87.125 ; - RECT 11.185 86.955 11.355 87.125 ; - RECT 10.725 86.955 10.895 87.125 ; - RECT 10.265 86.955 10.435 87.125 ; - RECT 9.805 86.955 9.975 87.125 ; - RECT 9.345 86.955 9.515 87.125 ; - RECT 8.885 86.955 9.055 87.125 ; - RECT 8.425 86.955 8.595 87.125 ; - RECT 7.965 86.955 8.135 87.125 ; - RECT 7.505 86.955 7.675 87.125 ; - RECT 7.045 86.955 7.215 87.125 ; - RECT 6.585 86.955 6.755 87.125 ; - RECT 6.125 86.955 6.295 87.125 ; - RECT 5.665 86.955 5.835 87.125 ; - RECT 5.205 86.955 5.375 87.125 ; - RECT 4.745 86.955 4.915 87.125 ; - RECT 4.285 86.955 4.455 87.125 ; - RECT 3.825 86.955 3.995 87.125 ; - RECT 3.365 86.955 3.535 87.125 ; - RECT 2.905 86.955 3.075 87.125 ; - RECT 2.445 86.955 2.615 87.125 ; - RECT 1.985 86.955 2.155 87.125 ; - RECT 1.525 86.955 1.695 87.125 ; - RECT 1.065 86.955 1.235 87.125 ; - RECT 0.605 86.955 0.775 87.125 ; - RECT 0.145 86.955 0.315 87.125 ; - RECT 65.925 84.235 66.095 84.405 ; - RECT 65.465 84.235 65.635 84.405 ; - RECT 0.605 84.235 0.775 84.405 ; - RECT 0.145 84.235 0.315 84.405 ; - RECT 65.925 81.515 66.095 81.685 ; - RECT 65.465 81.515 65.635 81.685 ; - RECT 0.605 81.515 0.775 81.685 ; - RECT 0.145 81.515 0.315 81.685 ; - RECT 65.925 78.795 66.095 78.965 ; - RECT 65.465 78.795 65.635 78.965 ; - RECT 0.605 78.795 0.775 78.965 ; - RECT 0.145 78.795 0.315 78.965 ; - RECT 65.925 76.075 66.095 76.245 ; - RECT 65.465 76.075 65.635 76.245 ; - RECT 0.605 76.075 0.775 76.245 ; - RECT 0.145 76.075 0.315 76.245 ; - RECT 65.925 73.355 66.095 73.525 ; - RECT 65.465 73.355 65.635 73.525 ; - RECT 0.605 73.355 0.775 73.525 ; - RECT 0.145 73.355 0.315 73.525 ; - RECT 65.925 70.635 66.095 70.805 ; - RECT 65.465 70.635 65.635 70.805 ; - RECT 0.605 70.635 0.775 70.805 ; - RECT 0.145 70.635 0.315 70.805 ; - RECT 65.925 67.915 66.095 68.085 ; - RECT 65.465 67.915 65.635 68.085 ; - RECT 0.605 67.915 0.775 68.085 ; - RECT 0.145 67.915 0.315 68.085 ; - RECT 65.925 65.195 66.095 65.365 ; - RECT 65.465 65.195 65.635 65.365 ; - RECT 0.605 65.195 0.775 65.365 ; - RECT 0.145 65.195 0.315 65.365 ; - RECT 65.925 62.475 66.095 62.645 ; - RECT 65.465 62.475 65.635 62.645 ; - RECT 0.605 62.475 0.775 62.645 ; - RECT 0.145 62.475 0.315 62.645 ; - RECT 65.925 59.755 66.095 59.925 ; - RECT 65.465 59.755 65.635 59.925 ; - RECT 0.605 59.755 0.775 59.925 ; - RECT 0.145 59.755 0.315 59.925 ; - RECT 65.925 57.035 66.095 57.205 ; - RECT 65.465 57.035 65.635 57.205 ; - RECT 0.605 57.035 0.775 57.205 ; - RECT 0.145 57.035 0.315 57.205 ; - RECT 65.925 54.315 66.095 54.485 ; - RECT 65.465 54.315 65.635 54.485 ; - RECT 0.605 54.315 0.775 54.485 ; - RECT 0.145 54.315 0.315 54.485 ; - RECT 65.925 51.595 66.095 51.765 ; - RECT 65.465 51.595 65.635 51.765 ; - RECT 0.605 51.595 0.775 51.765 ; - RECT 0.145 51.595 0.315 51.765 ; - RECT 65.925 48.875 66.095 49.045 ; - RECT 65.465 48.875 65.635 49.045 ; - RECT 0.605 48.875 0.775 49.045 ; - RECT 0.145 48.875 0.315 49.045 ; - RECT 65.925 46.155 66.095 46.325 ; - RECT 65.465 46.155 65.635 46.325 ; - RECT 0.605 46.155 0.775 46.325 ; - RECT 0.145 46.155 0.315 46.325 ; - RECT 65.925 43.435 66.095 43.605 ; - RECT 65.465 43.435 65.635 43.605 ; - RECT 0.605 43.435 0.775 43.605 ; - RECT 0.145 43.435 0.315 43.605 ; - RECT 65.925 40.715 66.095 40.885 ; - RECT 65.465 40.715 65.635 40.885 ; - RECT 0.605 40.715 0.775 40.885 ; - RECT 0.145 40.715 0.315 40.885 ; - RECT 65.925 37.995 66.095 38.165 ; - RECT 65.465 37.995 65.635 38.165 ; - RECT 0.605 37.995 0.775 38.165 ; - RECT 0.145 37.995 0.315 38.165 ; - RECT 65.925 35.275 66.095 35.445 ; - RECT 65.465 35.275 65.635 35.445 ; - RECT 0.605 35.275 0.775 35.445 ; - RECT 0.145 35.275 0.315 35.445 ; - RECT 65.925 32.555 66.095 32.725 ; - RECT 65.465 32.555 65.635 32.725 ; - RECT 0.605 32.555 0.775 32.725 ; - RECT 0.145 32.555 0.315 32.725 ; - RECT 65.925 29.835 66.095 30.005 ; - RECT 65.465 29.835 65.635 30.005 ; - RECT 0.605 29.835 0.775 30.005 ; - RECT 0.145 29.835 0.315 30.005 ; - RECT 65.925 27.115 66.095 27.285 ; - RECT 65.465 27.115 65.635 27.285 ; - RECT 0.605 27.115 0.775 27.285 ; - RECT 0.145 27.115 0.315 27.285 ; - RECT 65.925 24.395 66.095 24.565 ; - RECT 65.465 24.395 65.635 24.565 ; - RECT 0.605 24.395 0.775 24.565 ; - RECT 0.145 24.395 0.315 24.565 ; - RECT 65.925 21.675 66.095 21.845 ; - RECT 65.465 21.675 65.635 21.845 ; - RECT 0.605 21.675 0.775 21.845 ; - RECT 0.145 21.675 0.315 21.845 ; - RECT 65.925 18.955 66.095 19.125 ; - RECT 65.465 18.955 65.635 19.125 ; - RECT 0.605 18.955 0.775 19.125 ; - RECT 0.145 18.955 0.315 19.125 ; - RECT 65.925 16.235 66.095 16.405 ; - RECT 65.465 16.235 65.635 16.405 ; - RECT 0.605 16.235 0.775 16.405 ; - RECT 0.145 16.235 0.315 16.405 ; - RECT 65.925 13.515 66.095 13.685 ; - RECT 65.465 13.515 65.635 13.685 ; - RECT 0.605 13.515 0.775 13.685 ; - RECT 0.145 13.515 0.315 13.685 ; - RECT 65.925 10.795 66.095 10.965 ; - RECT 65.465 10.795 65.635 10.965 ; - RECT 0.605 10.795 0.775 10.965 ; - RECT 0.145 10.795 0.315 10.965 ; - RECT 65.925 8.075 66.095 8.245 ; - RECT 65.465 8.075 65.635 8.245 ; - RECT 0.605 8.075 0.775 8.245 ; - RECT 0.145 8.075 0.315 8.245 ; - RECT 65.925 5.355 66.095 5.525 ; - RECT 65.465 5.355 65.635 5.525 ; - RECT 0.605 5.355 0.775 5.525 ; - RECT 0.145 5.355 0.315 5.525 ; - RECT 65.925 2.635 66.095 2.805 ; - RECT 65.465 2.635 65.635 2.805 ; - RECT 0.605 2.635 0.775 2.805 ; - RECT 0.145 2.635 0.315 2.805 ; - RECT 65.925 -0.085 66.095 0.085 ; - RECT 65.465 -0.085 65.635 0.085 ; - RECT 65.005 -0.085 65.175 0.085 ; - RECT 64.545 -0.085 64.715 0.085 ; - RECT 64.085 -0.085 64.255 0.085 ; - RECT 63.625 -0.085 63.795 0.085 ; - RECT 63.165 -0.085 63.335 0.085 ; - RECT 62.705 -0.085 62.875 0.085 ; - RECT 62.245 -0.085 62.415 0.085 ; - RECT 61.785 -0.085 61.955 0.085 ; - RECT 61.325 -0.085 61.495 0.085 ; - RECT 60.865 -0.085 61.035 0.085 ; - RECT 60.405 -0.085 60.575 0.085 ; - RECT 59.945 -0.085 60.115 0.085 ; - RECT 59.485 -0.085 59.655 0.085 ; - RECT 59.025 -0.085 59.195 0.085 ; - RECT 58.565 -0.085 58.735 0.085 ; - RECT 58.105 -0.085 58.275 0.085 ; - RECT 57.645 -0.085 57.815 0.085 ; - RECT 57.185 -0.085 57.355 0.085 ; - RECT 56.725 -0.085 56.895 0.085 ; - RECT 56.265 -0.085 56.435 0.085 ; - RECT 55.805 -0.085 55.975 0.085 ; - RECT 55.345 -0.085 55.515 0.085 ; - RECT 54.885 -0.085 55.055 0.085 ; - RECT 54.425 -0.085 54.595 0.085 ; - RECT 53.965 -0.085 54.135 0.085 ; - RECT 53.505 -0.085 53.675 0.085 ; - RECT 53.045 -0.085 53.215 0.085 ; - RECT 52.585 -0.085 52.755 0.085 ; - RECT 52.125 -0.085 52.295 0.085 ; - RECT 51.665 -0.085 51.835 0.085 ; - RECT 51.205 -0.085 51.375 0.085 ; - RECT 50.745 -0.085 50.915 0.085 ; - RECT 50.285 -0.085 50.455 0.085 ; - RECT 49.825 -0.085 49.995 0.085 ; - RECT 49.365 -0.085 49.535 0.085 ; - RECT 48.905 -0.085 49.075 0.085 ; - RECT 48.445 -0.085 48.615 0.085 ; - RECT 47.985 -0.085 48.155 0.085 ; - RECT 47.525 -0.085 47.695 0.085 ; - RECT 47.065 -0.085 47.235 0.085 ; - RECT 46.605 -0.085 46.775 0.085 ; - RECT 46.145 -0.085 46.315 0.085 ; - RECT 45.685 -0.085 45.855 0.085 ; - RECT 45.225 -0.085 45.395 0.085 ; - RECT 44.765 -0.085 44.935 0.085 ; - RECT 44.305 -0.085 44.475 0.085 ; - RECT 43.845 -0.085 44.015 0.085 ; - RECT 43.385 -0.085 43.555 0.085 ; - RECT 42.925 -0.085 43.095 0.085 ; - RECT 42.465 -0.085 42.635 0.085 ; - RECT 42.005 -0.085 42.175 0.085 ; - RECT 41.545 -0.085 41.715 0.085 ; - RECT 41.085 -0.085 41.255 0.085 ; - RECT 40.625 -0.085 40.795 0.085 ; - RECT 40.165 -0.085 40.335 0.085 ; - RECT 39.705 -0.085 39.875 0.085 ; - RECT 39.245 -0.085 39.415 0.085 ; - RECT 38.785 -0.085 38.955 0.085 ; - RECT 38.325 -0.085 38.495 0.085 ; - RECT 37.865 -0.085 38.035 0.085 ; - RECT 37.405 -0.085 37.575 0.085 ; - RECT 36.945 -0.085 37.115 0.085 ; - RECT 36.485 -0.085 36.655 0.085 ; - RECT 36.025 -0.085 36.195 0.085 ; - RECT 35.565 -0.085 35.735 0.085 ; - RECT 35.105 -0.085 35.275 0.085 ; - RECT 34.645 -0.085 34.815 0.085 ; - RECT 34.185 -0.085 34.355 0.085 ; - RECT 33.725 -0.085 33.895 0.085 ; - RECT 33.265 -0.085 33.435 0.085 ; - RECT 32.805 -0.085 32.975 0.085 ; - RECT 32.345 -0.085 32.515 0.085 ; - RECT 31.885 -0.085 32.055 0.085 ; - RECT 31.425 -0.085 31.595 0.085 ; - RECT 30.965 -0.085 31.135 0.085 ; - RECT 30.505 -0.085 30.675 0.085 ; - RECT 30.045 -0.085 30.215 0.085 ; - RECT 29.585 -0.085 29.755 0.085 ; - RECT 29.125 -0.085 29.295 0.085 ; - RECT 28.665 -0.085 28.835 0.085 ; - RECT 28.205 -0.085 28.375 0.085 ; - RECT 27.745 -0.085 27.915 0.085 ; - RECT 27.285 -0.085 27.455 0.085 ; - RECT 26.825 -0.085 26.995 0.085 ; - RECT 26.365 -0.085 26.535 0.085 ; - RECT 25.905 -0.085 26.075 0.085 ; - RECT 25.445 -0.085 25.615 0.085 ; - RECT 24.985 -0.085 25.155 0.085 ; - RECT 24.525 -0.085 24.695 0.085 ; - RECT 24.065 -0.085 24.235 0.085 ; - RECT 23.605 -0.085 23.775 0.085 ; - RECT 23.145 -0.085 23.315 0.085 ; - RECT 22.685 -0.085 22.855 0.085 ; - RECT 22.225 -0.085 22.395 0.085 ; - RECT 21.765 -0.085 21.935 0.085 ; - RECT 21.305 -0.085 21.475 0.085 ; - RECT 20.845 -0.085 21.015 0.085 ; - RECT 20.385 -0.085 20.555 0.085 ; - RECT 19.925 -0.085 20.095 0.085 ; - RECT 19.465 -0.085 19.635 0.085 ; - RECT 19.005 -0.085 19.175 0.085 ; - RECT 18.545 -0.085 18.715 0.085 ; - RECT 18.085 -0.085 18.255 0.085 ; - RECT 17.625 -0.085 17.795 0.085 ; - RECT 17.165 -0.085 17.335 0.085 ; - RECT 16.705 -0.085 16.875 0.085 ; - RECT 16.245 -0.085 16.415 0.085 ; - RECT 15.785 -0.085 15.955 0.085 ; - RECT 15.325 -0.085 15.495 0.085 ; - RECT 14.865 -0.085 15.035 0.085 ; - RECT 14.405 -0.085 14.575 0.085 ; - RECT 13.945 -0.085 14.115 0.085 ; - RECT 13.485 -0.085 13.655 0.085 ; - RECT 13.025 -0.085 13.195 0.085 ; - RECT 12.565 -0.085 12.735 0.085 ; - RECT 12.105 -0.085 12.275 0.085 ; - RECT 11.645 -0.085 11.815 0.085 ; - RECT 11.185 -0.085 11.355 0.085 ; - RECT 10.725 -0.085 10.895 0.085 ; - RECT 10.265 -0.085 10.435 0.085 ; - RECT 9.805 -0.085 9.975 0.085 ; - RECT 9.345 -0.085 9.515 0.085 ; - RECT 8.885 -0.085 9.055 0.085 ; - RECT 8.425 -0.085 8.595 0.085 ; - RECT 7.965 -0.085 8.135 0.085 ; - RECT 7.505 -0.085 7.675 0.085 ; - RECT 7.045 -0.085 7.215 0.085 ; - RECT 6.585 -0.085 6.755 0.085 ; - RECT 6.125 -0.085 6.295 0.085 ; - RECT 5.665 -0.085 5.835 0.085 ; - RECT 5.205 -0.085 5.375 0.085 ; - RECT 4.745 -0.085 4.915 0.085 ; - RECT 4.285 -0.085 4.455 0.085 ; - RECT 3.825 -0.085 3.995 0.085 ; - RECT 3.365 -0.085 3.535 0.085 ; - RECT 2.905 -0.085 3.075 0.085 ; - RECT 2.445 -0.085 2.615 0.085 ; - RECT 1.985 -0.085 2.155 0.085 ; - RECT 1.525 -0.085 1.695 0.085 ; - RECT 1.065 -0.085 1.235 0.085 ; - RECT 0.605 -0.085 0.775 0.085 ; - RECT 0.145 -0.085 0.315 0.085 ; - LAYER via ; - RECT 55.125 86.965 55.275 87.115 ; - RECT 25.685 86.965 25.835 87.115 ; - RECT 36.725 1.625 36.875 1.775 ; - RECT 16.945 1.625 17.095 1.775 ; - RECT 55.125 -0.075 55.275 0.075 ; - RECT 25.685 -0.075 25.835 0.075 ; - LAYER via2 ; - RECT 55.1 86.94 55.3 87.14 ; - RECT 25.66 86.94 25.86 87.14 ; - RECT 1.28 80.14 1.48 80.34 ; - RECT 64.76 73.34 64.96 73.54 ; - RECT 1.74 63.82 1.94 64.02 ; - RECT 64.76 60.42 64.96 60.62 ; - RECT 1.74 52.94 1.94 53.14 ; - RECT 64.76 46.14 64.96 46.34 ; - RECT 1.28 46.14 1.48 46.34 ; - RECT 64.76 40.02 64.96 40.22 ; - RECT 64.3 38.66 64.5 38.86 ; - RECT 64.3 34.58 64.5 34.78 ; - RECT 64.76 33.22 64.96 33.42 ; - RECT 1.28 32.54 1.48 32.74 ; - RECT 1.28 25.74 1.48 25.94 ; - RECT 64.76 20.98 64.96 21.18 ; - RECT 1.74 20.98 1.94 21.18 ; - RECT 55.1 -0.1 55.3 0.1 ; - RECT 25.66 -0.1 25.86 0.1 ; - LAYER via3 ; - RECT 55.1 86.94 55.3 87.14 ; - RECT 25.66 86.94 25.86 87.14 ; - RECT 1.74 57.02 1.94 57.22 ; - RECT 55.1 -0.1 55.3 0.1 ; - RECT 25.66 -0.1 25.86 0.1 ; - LAYER OVERLAP ; - POLYGON 0 0 0 87.04 66.24 87.04 66.24 0 ; - END -END cbx_1__1_ - -END LIBRARY diff --git a/FPGA22_HIER_SKY_PNR/modules/lef/cbx_1__2__icv_in_design.lef b/FPGA22_HIER_SKY_PNR/modules/lef/cbx_1__2__icv_in_design.lef deleted file mode 100644 index 6a93c37..0000000 --- a/FPGA22_HIER_SKY_PNR/modules/lef/cbx_1__2__icv_in_design.lef +++ /dev/null @@ -1,1894 +0,0 @@ -VERSION 5.7 ; -BUSBITCHARS "[]" ; - -UNITS - DATABASE MICRONS 1000 ; -END UNITS - -MANUFACTURINGGRID 0.005 ; - -LAYER li1 - TYPE ROUTING ; - DIRECTION VERTICAL ; - PITCH 0.46 ; - WIDTH 0.17 ; -END li1 - -LAYER mcon - TYPE CUT ; -END mcon - -LAYER met1 - TYPE ROUTING ; - DIRECTION HORIZONTAL ; - PITCH 0.34 ; - WIDTH 0.14 ; -END met1 - -LAYER via - TYPE CUT ; -END via - -LAYER met2 - TYPE ROUTING ; - DIRECTION VERTICAL ; - PITCH 0.46 ; - WIDTH 0.14 ; -END met2 - -LAYER via2 - TYPE CUT ; -END via2 - -LAYER met3 - TYPE ROUTING ; - DIRECTION HORIZONTAL ; - PITCH 0.68 ; - WIDTH 0.3 ; -END met3 - -LAYER via3 - TYPE CUT ; -END via3 - -LAYER met4 - TYPE ROUTING ; - DIRECTION VERTICAL ; - PITCH 0.92 ; - WIDTH 0.3 ; -END met4 - -LAYER via4 - TYPE CUT ; -END via4 - -LAYER met5 - TYPE ROUTING ; - DIRECTION HORIZONTAL ; - PITCH 3.4 ; - WIDTH 1.6 ; -END met5 - -LAYER nwell - TYPE MASTERSLICE ; -END nwell - -LAYER pwell - TYPE MASTERSLICE ; -END pwell - -LAYER OVERLAP - TYPE OVERLAP ; -END OVERLAP - -VIA L1M1_PR - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.145 -0.115 0.145 0.115 ; -END L1M1_PR - -VIA L1M1_PR_R - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.115 -0.145 0.115 0.145 ; -END L1M1_PR_R - -VIA L1M1_PR_M - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.115 -0.145 0.115 0.145 ; -END L1M1_PR_M - -VIA L1M1_PR_MR - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.145 -0.115 0.145 0.115 ; -END L1M1_PR_MR - -VIA L1M1_PR_C - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.145 -0.145 0.145 0.145 ; -END L1M1_PR_C - -VIA M1M2_PR - LAYER met1 ; - RECT -0.16 -0.13 0.16 0.13 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.13 -0.16 0.13 0.16 ; -END M1M2_PR - -VIA M1M2_PR_Enc - LAYER met1 ; - RECT -0.16 -0.13 0.16 0.13 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.16 -0.13 0.16 0.13 ; -END M1M2_PR_Enc - -VIA M1M2_PR_R - LAYER met1 ; - RECT -0.13 -0.16 0.13 0.16 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.16 -0.13 0.16 0.13 ; -END M1M2_PR_R - -VIA M1M2_PR_R_Enc - LAYER met1 ; - RECT -0.13 -0.16 0.13 0.16 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.13 -0.16 0.13 0.16 ; -END M1M2_PR_R_Enc - -VIA M1M2_PR_M - LAYER met1 ; - RECT -0.16 -0.13 0.16 0.13 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.16 -0.13 0.16 0.13 ; -END M1M2_PR_M - -VIA M1M2_PR_M_Enc - LAYER met1 ; - RECT -0.16 -0.13 0.16 0.13 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.13 -0.16 0.13 0.16 ; -END M1M2_PR_M_Enc - -VIA M1M2_PR_MR - LAYER met1 ; - RECT -0.13 -0.16 0.13 0.16 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.13 -0.16 0.13 0.16 ; -END M1M2_PR_MR - -VIA M1M2_PR_MR_Enc - LAYER met1 ; - RECT -0.13 -0.16 0.13 0.16 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.16 -0.13 0.16 0.13 ; -END M1M2_PR_MR_Enc - -VIA M1M2_PR_C - LAYER met1 ; - RECT -0.16 -0.16 0.16 0.16 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.16 -0.16 0.16 0.16 ; -END M1M2_PR_C - -VIA M2M3_PR - LAYER met2 ; - RECT -0.14 -0.185 0.14 0.185 ; - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met3 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M2M3_PR - -VIA M2M3_PR_R - LAYER met2 ; - RECT -0.185 -0.14 0.185 0.14 ; - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met3 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M2M3_PR_R - -VIA M2M3_PR_M - LAYER met2 ; - RECT -0.14 -0.185 0.14 0.185 ; - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met3 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M2M3_PR_M - -VIA M2M3_PR_MR - LAYER met2 ; - RECT -0.185 -0.14 0.185 0.14 ; - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met3 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M2M3_PR_MR - -VIA M2M3_PR_C - LAYER met2 ; - RECT -0.185 -0.185 0.185 0.185 ; - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met3 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M2M3_PR_C - -VIA M3M4_PR - LAYER met3 ; - RECT -0.19 -0.16 0.19 0.16 ; - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR - -VIA M3M4_PR_R - LAYER met3 ; - RECT -0.16 -0.19 0.16 0.19 ; - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR_R - -VIA M3M4_PR_M - LAYER met3 ; - RECT -0.19 -0.16 0.19 0.16 ; - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR_M - -VIA M3M4_PR_MR - LAYER met3 ; - RECT -0.16 -0.19 0.16 0.19 ; - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR_MR - -VIA M3M4_PR_C - LAYER met3 ; - RECT -0.19 -0.19 0.19 0.19 ; - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR_C - -VIA M4M5_PR - LAYER met4 ; - RECT -0.59 -0.59 0.59 0.59 ; - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - LAYER met5 ; - RECT -0.71 -0.71 0.71 0.71 ; -END M4M5_PR - -VIA M4M5_PR_R - LAYER met4 ; - RECT -0.59 -0.59 0.59 0.59 ; - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - LAYER met5 ; - RECT -0.71 -0.71 0.71 0.71 ; -END M4M5_PR_R - -VIA M4M5_PR_M - LAYER met4 ; - RECT -0.59 -0.59 0.59 0.59 ; - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - LAYER met5 ; - RECT -0.71 -0.71 0.71 0.71 ; -END M4M5_PR_M - -VIA M4M5_PR_MR - LAYER met4 ; - RECT -0.59 -0.59 0.59 0.59 ; - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - LAYER met5 ; - RECT -0.71 -0.71 0.71 0.71 ; -END M4M5_PR_MR - -VIA M4M5_PR_C - LAYER met4 ; - RECT -0.59 -0.59 0.59 0.59 ; - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - LAYER met5 ; - RECT -0.71 -0.71 0.71 0.71 ; -END M4M5_PR_C - -SITE unit - CLASS CORE ; - SYMMETRY Y ; - SIZE 0.46 BY 2.72 ; -END unit - -SITE unithddbl - CLASS CORE ; - SIZE 0.46 BY 5.44 ; -END unithddbl - -MACRO cbx_1__2_ - CLASS BLOCK ; - ORIGIN 0 0 ; - SIZE 66.24 BY 87.04 ; - SYMMETRY X Y ; - PIN prog_clk[0] - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER met2 ; - RECT 56.51 0 56.65 1.36 ; - END - END prog_clk[0] - PIN chanx_left_in[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 3.25 1.38 3.55 ; - END - END chanx_left_in[0] - PIN chanx_left_in[1] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 21.61 1.38 21.91 ; - END - END chanx_left_in[1] - PIN chanx_left_in[2] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 4.61 1.38 4.91 ; - END - END chanx_left_in[2] - PIN chanx_left_in[3] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 50.17 1.38 50.47 ; - END - END chanx_left_in[3] - PIN chanx_left_in[4] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 10.73 1.38 11.03 ; - END - END chanx_left_in[4] - PIN chanx_left_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 15.49 1.38 15.79 ; - END - END chanx_left_in[5] - PIN chanx_left_in[6] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 35.89 1.38 36.19 ; - END - END chanx_left_in[6] - PIN chanx_left_in[7] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 30.45 1.38 30.75 ; - END - END chanx_left_in[7] - PIN chanx_left_in[8] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 56.29 1.38 56.59 ; - END - END chanx_left_in[8] - PIN chanx_left_in[9] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 33.17 1.38 33.47 ; - END - END chanx_left_in[9] - PIN chanx_left_in[10] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 25.69 1.38 25.99 ; - END - END chanx_left_in[10] - PIN chanx_left_in[11] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 29.09 1.38 29.39 ; - END - END chanx_left_in[11] - PIN chanx_left_in[12] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 9.37 1.38 9.67 ; - END - END chanx_left_in[12] - PIN chanx_left_in[13] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 16.85 1.38 17.15 ; - END - END chanx_left_in[13] - PIN chanx_left_in[14] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 59.01 1.38 59.31 ; - END - END chanx_left_in[14] - PIN chanx_left_in[15] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 31.81 1.38 32.11 ; - END - END chanx_left_in[15] - PIN chanx_left_in[16] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 64.45 1.38 64.75 ; - END - END chanx_left_in[16] - PIN chanx_left_in[17] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 34.53 1.38 34.83 ; - END - END chanx_left_in[17] - PIN chanx_left_in[18] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 53.57 1.38 53.87 ; - END - END chanx_left_in[18] - PIN chanx_left_in[19] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 24.33 1.38 24.63 ; - END - END chanx_left_in[19] - PIN chanx_right_in[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 61.05 66.24 61.35 ; - END - END chanx_right_in[0] - PIN chanx_right_in[1] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 78.73 66.24 79.03 ; - END - END chanx_right_in[1] - PIN chanx_right_in[2] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 62.41 66.24 62.71 ; - END - END chanx_right_in[2] - PIN chanx_right_in[3] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 41.33 66.24 41.63 ; - END - END chanx_right_in[3] - PIN chanx_right_in[4] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 59.69 66.24 59.99 ; - END - END chanx_right_in[4] - PIN chanx_right_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 56.97 66.24 57.27 ; - END - END chanx_right_in[5] - PIN chanx_right_in[6] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 35.89 66.24 36.19 ; - END - END chanx_right_in[6] - PIN chanx_right_in[7] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 37.25 66.24 37.55 ; - END - END chanx_right_in[7] - PIN chanx_right_in[8] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 66.49 66.24 66.79 ; - END - END chanx_right_in[8] - PIN chanx_right_in[9] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 33.17 66.24 33.47 ; - END - END chanx_right_in[9] - PIN chanx_right_in[10] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 42.69 66.24 42.99 ; - END - END chanx_right_in[10] - PIN chanx_right_in[11] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 26.37 66.24 26.67 ; - END - END chanx_right_in[11] - PIN chanx_right_in[12] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 63.77 66.24 64.07 ; - END - END chanx_right_in[12] - PIN chanx_right_in[13] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 16.85 66.24 17.15 ; - END - END chanx_right_in[13] - PIN chanx_right_in[14] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 52.21 66.24 52.51 ; - END - END chanx_right_in[14] - PIN chanx_right_in[15] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 29.09 66.24 29.39 ; - END - END chanx_right_in[15] - PIN chanx_right_in[16] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 13.45 66.24 13.75 ; - END - END chanx_right_in[16] - PIN chanx_right_in[17] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 20.93 66.24 21.23 ; - END - END chanx_right_in[17] - PIN chanx_right_in[18] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 34.53 66.24 34.83 ; - END - END chanx_right_in[18] - PIN chanx_right_in[19] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 54.93 66.24 55.23 ; - END - END chanx_right_in[19] - PIN ccff_head[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 3.93 66.24 4.23 ; - END - END ccff_head[0] - PIN chanx_left_out[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 70.57 1.38 70.87 ; - END - END chanx_left_out[0] - PIN chanx_left_out[1] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 42.69 1.38 42.99 ; - END - END chanx_left_out[1] - PIN chanx_left_out[2] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 69.21 1.38 69.51 ; - END - END chanx_left_out[2] - PIN chanx_left_out[3] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 61.73 1.38 62.03 ; - END - END chanx_left_out[3] - PIN chanx_left_out[4] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 22.97 1.38 23.27 ; - END - END chanx_left_out[4] - PIN chanx_left_out[5] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 12.09 1.38 12.39 ; - END - END chanx_left_out[5] - PIN chanx_left_out[6] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 13.45 1.38 13.75 ; - END - END chanx_left_out[6] - PIN chanx_left_out[7] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 38.61 1.38 38.91 ; - END - END chanx_left_out[7] - PIN chanx_left_out[8] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 66.49 1.38 66.79 ; - END - END chanx_left_out[8] - PIN chanx_left_out[9] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 48.81 1.38 49.11 ; - END - END chanx_left_out[9] - PIN chanx_left_out[10] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 63.09 1.38 63.39 ; - END - END chanx_left_out[10] - PIN chanx_left_out[11] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 57.65 1.38 57.95 ; - END - END chanx_left_out[11] - PIN chanx_left_out[12] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 39.97 1.38 40.27 ; - END - END chanx_left_out[12] - PIN chanx_left_out[13] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 60.37 1.38 60.67 ; - END - END chanx_left_out[13] - PIN chanx_left_out[14] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 20.25 1.38 20.55 ; - END - END chanx_left_out[14] - PIN chanx_left_out[15] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 44.73 1.38 45.03 ; - END - END chanx_left_out[15] - PIN chanx_left_out[16] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 18.21 1.38 18.51 ; - END - END chanx_left_out[16] - PIN chanx_left_out[17] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 41.33 1.38 41.63 ; - END - END chanx_left_out[17] - PIN chanx_left_out[18] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 46.09 1.38 46.39 ; - END - END chanx_left_out[18] - PIN chanx_left_out[19] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 47.45 1.38 47.75 ; - END - END chanx_left_out[19] - PIN chanx_right_out[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 31.81 66.24 32.11 ; - END - END chanx_right_out[0] - PIN chanx_right_out[1] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 44.05 66.24 44.35 ; - END - END chanx_right_out[1] - PIN chanx_right_out[2] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 38.61 66.24 38.91 ; - END - END chanx_right_out[2] - PIN chanx_right_out[3] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 10.73 66.24 11.03 ; - END - END chanx_right_out[3] - PIN chanx_right_out[4] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 12.09 66.24 12.39 ; - END - END chanx_right_out[4] - PIN chanx_right_out[5] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 22.29 66.24 22.59 ; - END - END chanx_right_out[5] - PIN chanx_right_out[6] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 15.49 66.24 15.79 ; - END - END chanx_right_out[6] - PIN chanx_right_out[7] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 18.21 66.24 18.51 ; - END - END chanx_right_out[7] - PIN chanx_right_out[8] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 30.45 66.24 30.75 ; - END - END chanx_right_out[8] - PIN chanx_right_out[9] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 45.41 66.24 45.71 ; - END - END chanx_right_out[9] - PIN chanx_right_out[10] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 46.77 66.24 47.07 ; - END - END chanx_right_out[10] - PIN chanx_right_out[11] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 48.13 66.24 48.43 ; - END - END chanx_right_out[11] - PIN chanx_right_out[12] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 8.01 66.24 8.31 ; - END - END chanx_right_out[12] - PIN chanx_right_out[13] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 9.37 66.24 9.67 ; - END - END chanx_right_out[13] - PIN chanx_right_out[14] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 6.65 66.24 6.95 ; - END - END chanx_right_out[14] - PIN chanx_right_out[15] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 19.57 66.24 19.87 ; - END - END chanx_right_out[15] - PIN chanx_right_out[16] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 53.57 66.24 53.87 ; - END - END chanx_right_out[16] - PIN chanx_right_out[17] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 39.97 66.24 40.27 ; - END - END chanx_right_out[17] - PIN chanx_right_out[18] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 58.33 66.24 58.63 ; - END - END chanx_right_out[18] - PIN chanx_right_out[19] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 27.73 66.24 28.03 ; - END - END chanx_right_out[19] - PIN top_grid_pin_0_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 67.85 66.24 68.15 ; - END - END top_grid_pin_0_[0] - PIN bottom_grid_pin_0_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 36.73 0 36.87 1.36 ; - END - END bottom_grid_pin_0_[0] - PIN bottom_grid_pin_1_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 17.87 0 18.01 1.36 ; - END - END bottom_grid_pin_1_[0] - PIN bottom_grid_pin_2_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 12.81 0 12.95 1.36 ; - END - END bottom_grid_pin_2_[0] - PIN bottom_grid_pin_3_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 11.89 0 12.03 1.36 ; - END - END bottom_grid_pin_3_[0] - PIN bottom_grid_pin_4_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 37.65 0 37.79 1.36 ; - END - END bottom_grid_pin_4_[0] - PIN bottom_grid_pin_5_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 40.41 0 40.55 1.36 ; - END - END bottom_grid_pin_5_[0] - PIN bottom_grid_pin_6_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 38.57 0 38.71 1.36 ; - END - END bottom_grid_pin_6_[0] - PIN bottom_grid_pin_7_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 39.49 0 39.63 1.36 ; - END - END bottom_grid_pin_7_[0] - PIN bottom_grid_pin_8_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 2.23 0 2.37 1.36 ; - END - END bottom_grid_pin_8_[0] - PIN bottom_grid_pin_9_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 10.05 0 10.19 1.36 ; - END - END bottom_grid_pin_9_[0] - PIN bottom_grid_pin_10_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 10.97 0 11.11 1.36 ; - END - END bottom_grid_pin_10_[0] - PIN bottom_grid_pin_11_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 19.71 0 19.85 1.36 ; - END - END bottom_grid_pin_11_[0] - PIN bottom_grid_pin_12_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 34.89 0 35.03 1.36 ; - END - END bottom_grid_pin_12_[0] - PIN bottom_grid_pin_13_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 18.79 0 18.93 1.36 ; - END - END bottom_grid_pin_13_[0] - PIN bottom_grid_pin_14_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 16.03 0 16.17 1.36 ; - END - END bottom_grid_pin_14_[0] - PIN bottom_grid_pin_15_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 35.81 0 35.95 1.36 ; - END - END bottom_grid_pin_15_[0] - PIN ccff_tail[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 37.25 1.38 37.55 ; - END - END ccff_tail[0] - PIN gfpga_pad_EMBEDDED_IO_SOC_IN[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 62.49 85.68 62.63 87.04 ; - END - END gfpga_pad_EMBEDDED_IO_SOC_IN[0] - PIN gfpga_pad_EMBEDDED_IO_SOC_OUT[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 50.99 85.68 51.13 87.04 ; - END - END gfpga_pad_EMBEDDED_IO_SOC_OUT[0] - PIN gfpga_pad_EMBEDDED_IO_SOC_DIR[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 7.29 85.68 7.43 87.04 ; - END - END gfpga_pad_EMBEDDED_IO_SOC_DIR[0] - PIN bottom_width_0_height_0__pin_0_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 65.13 66.24 65.43 ; - END - END bottom_width_0_height_0__pin_0_[0] - PIN bottom_width_0_height_0__pin_1_upper[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 27.05 1.38 27.35 ; - END - END bottom_width_0_height_0__pin_1_upper[0] - PIN bottom_width_0_height_0__pin_1_lower[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 50.17 66.24 50.47 ; - END - END bottom_width_0_height_0__pin_1_lower[0] - PIN SC_IN_TOP - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 67.85 1.38 68.15 ; - END - END SC_IN_TOP - PIN SC_IN_BOT - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 62.95 0 63.09 1.36 ; - END - END SC_IN_BOT - PIN SC_OUT_TOP - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 51.53 1.38 51.83 ; - END - END SC_OUT_TOP - PIN SC_OUT_BOT - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 5.29 66.24 5.59 ; - END - END SC_OUT_BOT - PIN VDD - DIRECTION INPUT ; - USE POWER ; - PORT - LAYER met4 ; - RECT 10.74 0 11.34 0.6 ; - RECT 40.18 0 40.78 0.6 ; - RECT 10.74 86.44 11.34 87.04 ; - RECT 40.18 86.44 40.78 87.04 ; - LAYER met5 ; - RECT 0 11.32 3.2 14.52 ; - RECT 63.04 11.32 66.24 14.52 ; - RECT 0 52.12 3.2 55.32 ; - RECT 63.04 52.12 66.24 55.32 ; - LAYER met1 ; - RECT 0 2.48 0.48 2.96 ; - RECT 65.76 2.48 66.24 2.96 ; - RECT 0 7.92 0.48 8.4 ; - RECT 65.76 7.92 66.24 8.4 ; - RECT 0 13.36 0.48 13.84 ; - RECT 65.76 13.36 66.24 13.84 ; - RECT 0 18.8 0.48 19.28 ; - RECT 65.76 18.8 66.24 19.28 ; - RECT 0 24.24 0.48 24.72 ; - RECT 65.76 24.24 66.24 24.72 ; - RECT 0 29.68 0.48 30.16 ; - RECT 65.76 29.68 66.24 30.16 ; - RECT 0 35.12 0.48 35.6 ; - RECT 65.76 35.12 66.24 35.6 ; - RECT 0 40.56 0.48 41.04 ; - RECT 65.76 40.56 66.24 41.04 ; - RECT 0 46 0.48 46.48 ; - RECT 65.76 46 66.24 46.48 ; - RECT 0 51.44 0.48 51.92 ; - RECT 65.76 51.44 66.24 51.92 ; - RECT 0 56.88 0.48 57.36 ; - RECT 65.76 56.88 66.24 57.36 ; - RECT 0 62.32 0.48 62.8 ; - RECT 65.76 62.32 66.24 62.8 ; - RECT 0 67.76 0.48 68.24 ; - RECT 65.76 67.76 66.24 68.24 ; - RECT 0 73.2 0.48 73.68 ; - RECT 65.76 73.2 66.24 73.68 ; - RECT 0 78.64 0.48 79.12 ; - RECT 65.76 78.64 66.24 79.12 ; - RECT 0 84.08 0.48 84.56 ; - RECT 65.76 84.08 66.24 84.56 ; - END - END VDD - PIN VSS - DIRECTION INPUT ; - USE GROUND ; - PORT - LAYER met4 ; - RECT 25.46 0 26.06 0.6 ; - RECT 54.9 0 55.5 0.6 ; - RECT 25.46 86.44 26.06 87.04 ; - RECT 54.9 86.44 55.5 87.04 ; - LAYER met5 ; - RECT 0 31.72 3.2 34.92 ; - RECT 63.04 31.72 66.24 34.92 ; - RECT 0 72.52 3.2 75.72 ; - RECT 63.04 72.52 66.24 75.72 ; - LAYER met1 ; - RECT 0 0 66.24 0.24 ; - RECT 0 5.2 0.48 5.68 ; - RECT 65.76 5.2 66.24 5.68 ; - RECT 0 10.64 0.48 11.12 ; - RECT 65.76 10.64 66.24 11.12 ; - RECT 0 16.08 0.48 16.56 ; - RECT 65.76 16.08 66.24 16.56 ; - RECT 0 21.52 0.48 22 ; - RECT 65.76 21.52 66.24 22 ; - RECT 0 26.96 0.48 27.44 ; - RECT 65.76 26.96 66.24 27.44 ; - RECT 0 32.4 0.48 32.88 ; - RECT 65.76 32.4 66.24 32.88 ; - RECT 0 37.84 0.48 38.32 ; - RECT 65.76 37.84 66.24 38.32 ; - RECT 0 43.28 0.48 43.76 ; - RECT 65.76 43.28 66.24 43.76 ; - RECT 0 48.72 0.48 49.2 ; - RECT 65.76 48.72 66.24 49.2 ; - RECT 0 54.16 0.48 54.64 ; - RECT 65.76 54.16 66.24 54.64 ; - RECT 0 59.6 0.48 60.08 ; - RECT 65.76 59.6 66.24 60.08 ; - RECT 0 65.04 0.48 65.52 ; - RECT 65.76 65.04 66.24 65.52 ; - RECT 0 70.48 0.48 70.96 ; - RECT 65.76 70.48 66.24 70.96 ; - RECT 0 75.92 0.48 76.4 ; - RECT 65.76 75.92 66.24 76.4 ; - RECT 0 81.36 0.48 81.84 ; - RECT 65.76 81.36 66.24 81.84 ; - RECT 0 86.8 66.24 87.04 ; - END - END VSS - PIN prog_clk__FEEDTHRU_1[0] - DIRECTION OUTPUT ; - USE CLOCK ; - PORT - LAYER met3 ; - RECT 0 6.65 1.38 6.95 ; - END - END prog_clk__FEEDTHRU_1[0] - PIN prog_clk__FEEDTHRU_2[0] - DIRECTION OUTPUT ; - USE CLOCK ; - PORT - LAYER met3 ; - RECT 64.86 24.33 66.24 24.63 ; - END - END prog_clk__FEEDTHRU_2[0] - OBS - LAYER li1 ; - RECT 0 86.955 66.24 87.125 ; - RECT 65.32 84.235 66.24 84.405 ; - RECT 0 84.235 3.68 84.405 ; - RECT 65.32 81.515 66.24 81.685 ; - RECT 0 81.515 1.84 81.685 ; - RECT 65.32 78.795 66.24 78.965 ; - RECT 0 78.795 1.84 78.965 ; - RECT 65.32 76.075 66.24 76.245 ; - RECT 0 76.075 1.84 76.245 ; - RECT 65.32 73.355 66.24 73.525 ; - RECT 0 73.355 1.84 73.525 ; - RECT 64.4 70.635 66.24 70.805 ; - RECT 0 70.635 1.84 70.805 ; - RECT 64.4 67.915 66.24 68.085 ; - RECT 0 67.915 1.84 68.085 ; - RECT 65.32 65.195 66.24 65.365 ; - RECT 0 65.195 1.84 65.365 ; - RECT 65.32 62.475 66.24 62.645 ; - RECT 0 62.475 1.84 62.645 ; - RECT 65.32 59.755 66.24 59.925 ; - RECT 0 59.755 1.84 59.925 ; - RECT 65.32 57.035 66.24 57.205 ; - RECT 0 57.035 1.84 57.205 ; - RECT 65.32 54.315 66.24 54.485 ; - RECT 0 54.315 1.84 54.485 ; - RECT 65.32 51.595 66.24 51.765 ; - RECT 0 51.595 1.84 51.765 ; - RECT 65.32 48.875 66.24 49.045 ; - RECT 0 48.875 1.84 49.045 ; - RECT 65.32 46.155 66.24 46.325 ; - RECT 0 46.155 1.84 46.325 ; - RECT 65.32 43.435 66.24 43.605 ; - RECT 0 43.435 1.84 43.605 ; - RECT 65.32 40.715 66.24 40.885 ; - RECT 0 40.715 1.84 40.885 ; - RECT 65.32 37.995 66.24 38.165 ; - RECT 0 37.995 1.84 38.165 ; - RECT 65.32 35.275 66.24 35.445 ; - RECT 0 35.275 1.84 35.445 ; - RECT 65.32 32.555 66.24 32.725 ; - RECT 0 32.555 1.84 32.725 ; - RECT 65.32 29.835 66.24 30.005 ; - RECT 0 29.835 1.84 30.005 ; - RECT 65.32 27.115 66.24 27.285 ; - RECT 0 27.115 1.84 27.285 ; - RECT 65.32 24.395 66.24 24.565 ; - RECT 0 24.395 1.84 24.565 ; - RECT 65.32 21.675 66.24 21.845 ; - RECT 0 21.675 1.84 21.845 ; - RECT 65.32 18.955 66.24 19.125 ; - RECT 0 18.955 1.84 19.125 ; - RECT 65.32 16.235 66.24 16.405 ; - RECT 0 16.235 1.84 16.405 ; - RECT 65.32 13.515 66.24 13.685 ; - RECT 0 13.515 1.84 13.685 ; - RECT 65.32 10.795 66.24 10.965 ; - RECT 0 10.795 1.84 10.965 ; - RECT 65.32 8.075 66.24 8.245 ; - RECT 0 8.075 1.84 8.245 ; - RECT 65.32 5.355 66.24 5.525 ; - RECT 0 5.355 3.68 5.525 ; - RECT 65.32 2.635 66.24 2.805 ; - RECT 0 2.635 3.68 2.805 ; - RECT 0 -0.085 66.24 0.085 ; - LAYER met2 ; - RECT 55.06 86.855 55.34 87.225 ; - RECT 25.62 86.855 25.9 87.225 ; - RECT 55.06 -0.185 55.34 0.185 ; - RECT 25.62 -0.185 25.9 0.185 ; - POLYGON 65.96 86.76 65.96 0.28 63.37 0.28 63.37 1.64 62.67 1.64 62.67 0.28 56.93 0.28 56.93 1.64 56.23 1.64 56.23 0.28 40.83 0.28 40.83 1.64 40.13 1.64 40.13 0.28 39.91 0.28 39.91 1.64 39.21 1.64 39.21 0.28 38.99 0.28 38.99 1.64 38.29 1.64 38.29 0.28 38.07 0.28 38.07 1.64 37.37 1.64 37.37 0.28 37.15 0.28 37.15 1.64 36.45 1.64 36.45 0.28 36.23 0.28 36.23 1.64 35.53 1.64 35.53 0.28 35.31 0.28 35.31 1.64 34.61 1.64 34.61 0.28 20.13 0.28 20.13 1.64 19.43 1.64 19.43 0.28 19.21 0.28 19.21 1.64 18.51 1.64 18.51 0.28 18.29 0.28 18.29 1.64 17.59 1.64 17.59 0.28 16.45 0.28 16.45 1.64 15.75 1.64 15.75 0.28 13.23 0.28 13.23 1.64 12.53 1.64 12.53 0.28 12.31 0.28 12.31 1.64 11.61 1.64 11.61 0.28 11.39 0.28 11.39 1.64 10.69 1.64 10.69 0.28 10.47 0.28 10.47 1.64 9.77 1.64 9.77 0.28 2.65 0.28 2.65 1.64 1.95 1.64 1.95 0.28 0.28 0.28 0.28 86.76 7.01 86.76 7.01 85.4 7.71 85.4 7.71 86.76 50.71 86.76 50.71 85.4 51.41 85.4 51.41 86.76 62.21 86.76 62.21 85.4 62.91 85.4 62.91 86.76 ; - LAYER met3 ; - POLYGON 55.365 87.205 55.365 87.2 55.58 87.2 55.58 86.88 55.365 86.88 55.365 86.875 55.035 86.875 55.035 86.88 54.82 86.88 54.82 87.2 55.035 87.2 55.035 87.205 ; - POLYGON 25.925 87.205 25.925 87.2 26.14 87.2 26.14 86.88 25.925 86.88 25.925 86.875 25.595 86.875 25.595 86.88 25.38 86.88 25.38 87.2 25.595 87.2 25.595 87.205 ; - POLYGON 2.005 35.525 2.005 35.52 2.03 35.52 2.03 35.2 2.005 35.2 2.005 35.195 1.275 35.195 1.275 35.525 ; - POLYGON 1.545 30.085 1.545 30.07 7.05 30.07 7.05 29.77 1.545 29.77 1.545 29.755 1.215 29.755 1.215 30.085 ; - POLYGON 2.03 19.88 2.03 19.87 30.51 19.87 30.51 19.57 2.03 19.57 2.03 19.56 1.65 19.56 1.65 19.88 ; - POLYGON 55.365 0.165 55.365 0.16 55.58 0.16 55.58 -0.16 55.365 -0.16 55.365 -0.165 55.035 -0.165 55.035 -0.16 54.82 -0.16 54.82 0.16 55.035 0.16 55.035 0.165 ; - POLYGON 25.925 0.165 25.925 0.16 26.14 0.16 26.14 -0.16 25.925 -0.16 25.925 -0.165 25.595 -0.165 25.595 -0.16 25.38 -0.16 25.38 0.16 25.595 0.16 25.595 0.165 ; - POLYGON 65.84 86.64 65.84 79.43 64.46 79.43 64.46 78.33 65.84 78.33 65.84 68.55 64.46 68.55 64.46 67.45 65.84 67.45 65.84 67.19 64.46 67.19 64.46 66.09 65.84 66.09 65.84 65.83 64.46 65.83 64.46 64.73 65.84 64.73 65.84 64.47 64.46 64.47 64.46 63.37 65.84 63.37 65.84 63.11 64.46 63.11 64.46 62.01 65.84 62.01 65.84 61.75 64.46 61.75 64.46 60.65 65.84 60.65 65.84 60.39 64.46 60.39 64.46 59.29 65.84 59.29 65.84 59.03 64.46 59.03 64.46 57.93 65.84 57.93 65.84 57.67 64.46 57.67 64.46 56.57 65.84 56.57 65.84 55.63 64.46 55.63 64.46 54.53 65.84 54.53 65.84 54.27 64.46 54.27 64.46 53.17 65.84 53.17 65.84 52.91 64.46 52.91 64.46 51.81 65.84 51.81 65.84 50.87 64.46 50.87 64.46 49.77 65.84 49.77 65.84 48.83 64.46 48.83 64.46 47.73 65.84 47.73 65.84 47.47 64.46 47.47 64.46 46.37 65.84 46.37 65.84 46.11 64.46 46.11 64.46 45.01 65.84 45.01 65.84 44.75 64.46 44.75 64.46 43.65 65.84 43.65 65.84 43.39 64.46 43.39 64.46 42.29 65.84 42.29 65.84 42.03 64.46 42.03 64.46 40.93 65.84 40.93 65.84 40.67 64.46 40.67 64.46 39.57 65.84 39.57 65.84 39.31 64.46 39.31 64.46 38.21 65.84 38.21 65.84 37.95 64.46 37.95 64.46 36.85 65.84 36.85 65.84 36.59 64.46 36.59 64.46 35.49 65.84 35.49 65.84 35.23 64.46 35.23 64.46 34.13 65.84 34.13 65.84 33.87 64.46 33.87 64.46 32.77 65.84 32.77 65.84 32.51 64.46 32.51 64.46 31.41 65.84 31.41 65.84 31.15 64.46 31.15 64.46 30.05 65.84 30.05 65.84 29.79 64.46 29.79 64.46 28.69 65.84 28.69 65.84 28.43 64.46 28.43 64.46 27.33 65.84 27.33 65.84 27.07 64.46 27.07 64.46 25.97 65.84 25.97 65.84 25.03 64.46 25.03 64.46 23.93 65.84 23.93 65.84 22.99 64.46 22.99 64.46 21.89 65.84 21.89 65.84 21.63 64.46 21.63 64.46 20.53 65.84 20.53 65.84 20.27 64.46 20.27 64.46 19.17 65.84 19.17 65.84 18.91 64.46 18.91 64.46 17.81 65.84 17.81 65.84 17.55 64.46 17.55 64.46 16.45 65.84 16.45 65.84 16.19 64.46 16.19 64.46 15.09 65.84 15.09 65.84 14.15 64.46 14.15 64.46 13.05 65.84 13.05 65.84 12.79 64.46 12.79 64.46 11.69 65.84 11.69 65.84 11.43 64.46 11.43 64.46 10.33 65.84 10.33 65.84 10.07 64.46 10.07 64.46 8.97 65.84 8.97 65.84 8.71 64.46 8.71 64.46 7.61 65.84 7.61 65.84 7.35 64.46 7.35 64.46 6.25 65.84 6.25 65.84 5.99 64.46 5.99 64.46 4.89 65.84 4.89 65.84 4.63 64.46 4.63 64.46 3.53 65.84 3.53 65.84 0.4 0.4 0.4 0.4 2.85 1.78 2.85 1.78 3.95 0.4 3.95 0.4 4.21 1.78 4.21 1.78 5.31 0.4 5.31 0.4 6.25 1.78 6.25 1.78 7.35 0.4 7.35 0.4 8.97 1.78 8.97 1.78 10.07 0.4 10.07 0.4 10.33 1.78 10.33 1.78 11.43 0.4 11.43 0.4 11.69 1.78 11.69 1.78 12.79 0.4 12.79 0.4 13.05 1.78 13.05 1.78 14.15 0.4 14.15 0.4 15.09 1.78 15.09 1.78 16.19 0.4 16.19 0.4 16.45 1.78 16.45 1.78 17.55 0.4 17.55 0.4 17.81 1.78 17.81 1.78 18.91 0.4 18.91 0.4 19.85 1.78 19.85 1.78 20.95 0.4 20.95 0.4 21.21 1.78 21.21 1.78 22.31 0.4 22.31 0.4 22.57 1.78 22.57 1.78 23.67 0.4 23.67 0.4 23.93 1.78 23.93 1.78 25.03 0.4 25.03 0.4 25.29 1.78 25.29 1.78 26.39 0.4 26.39 0.4 26.65 1.78 26.65 1.78 27.75 0.4 27.75 0.4 28.69 1.78 28.69 1.78 29.79 0.4 29.79 0.4 30.05 1.78 30.05 1.78 31.15 0.4 31.15 0.4 31.41 1.78 31.41 1.78 32.51 0.4 32.51 0.4 32.77 1.78 32.77 1.78 33.87 0.4 33.87 0.4 34.13 1.78 34.13 1.78 35.23 0.4 35.23 0.4 35.49 1.78 35.49 1.78 36.59 0.4 36.59 0.4 36.85 1.78 36.85 1.78 37.95 0.4 37.95 0.4 38.21 1.78 38.21 1.78 39.31 0.4 39.31 0.4 39.57 1.78 39.57 1.78 40.67 0.4 40.67 0.4 40.93 1.78 40.93 1.78 42.03 0.4 42.03 0.4 42.29 1.78 42.29 1.78 43.39 0.4 43.39 0.4 44.33 1.78 44.33 1.78 45.43 0.4 45.43 0.4 45.69 1.78 45.69 1.78 46.79 0.4 46.79 0.4 47.05 1.78 47.05 1.78 48.15 0.4 48.15 0.4 48.41 1.78 48.41 1.78 49.51 0.4 49.51 0.4 49.77 1.78 49.77 1.78 50.87 0.4 50.87 0.4 51.13 1.78 51.13 1.78 52.23 0.4 52.23 0.4 53.17 1.78 53.17 1.78 54.27 0.4 54.27 0.4 55.89 1.78 55.89 1.78 56.99 0.4 56.99 0.4 57.25 1.78 57.25 1.78 58.35 0.4 58.35 0.4 58.61 1.78 58.61 1.78 59.71 0.4 59.71 0.4 59.97 1.78 59.97 1.78 61.07 0.4 61.07 0.4 61.33 1.78 61.33 1.78 62.43 0.4 62.43 0.4 62.69 1.78 62.69 1.78 63.79 0.4 63.79 0.4 64.05 1.78 64.05 1.78 65.15 0.4 65.15 0.4 66.09 1.78 66.09 1.78 67.19 0.4 67.19 0.4 67.45 1.78 67.45 1.78 68.55 0.4 68.55 0.4 68.81 1.78 68.81 1.78 69.91 0.4 69.91 0.4 70.17 1.78 70.17 1.78 71.27 0.4 71.27 0.4 86.64 ; - LAYER met1 ; - POLYGON 65.96 86.52 65.96 84.84 65.48 84.84 65.48 83.8 65.96 83.8 65.96 82.12 65.48 82.12 65.48 81.08 65.96 81.08 65.96 79.4 65.48 79.4 65.48 78.36 65.96 78.36 65.96 76.68 65.48 76.68 65.48 75.64 65.96 75.64 65.96 73.96 65.48 73.96 65.48 72.92 65.96 72.92 65.96 71.24 65.48 71.24 65.48 70.2 65.96 70.2 65.96 68.52 65.48 68.52 65.48 67.48 65.96 67.48 65.96 65.8 65.48 65.8 65.48 64.76 65.96 64.76 65.96 63.08 65.48 63.08 65.48 62.04 65.96 62.04 65.96 60.36 65.48 60.36 65.48 59.32 65.96 59.32 65.96 57.64 65.48 57.64 65.48 56.6 65.96 56.6 65.96 54.92 65.48 54.92 65.48 53.88 65.96 53.88 65.96 52.2 65.48 52.2 65.48 51.16 65.96 51.16 65.96 49.48 65.48 49.48 65.48 48.44 65.96 48.44 65.96 46.76 65.48 46.76 65.48 45.72 65.96 45.72 65.96 44.04 65.48 44.04 65.48 43 65.96 43 65.96 41.32 65.48 41.32 65.48 40.28 65.96 40.28 65.96 38.6 65.48 38.6 65.48 37.56 65.96 37.56 65.96 35.88 65.48 35.88 65.48 34.84 65.96 34.84 65.96 33.16 65.48 33.16 65.48 32.12 65.96 32.12 65.96 30.44 65.48 30.44 65.48 29.4 65.96 29.4 65.96 27.72 65.48 27.72 65.48 26.68 65.96 26.68 65.96 25 65.48 25 65.48 23.96 65.96 23.96 65.96 22.28 65.48 22.28 65.48 21.24 65.96 21.24 65.96 19.56 65.48 19.56 65.48 18.52 65.96 18.52 65.96 16.84 65.48 16.84 65.48 15.8 65.96 15.8 65.96 14.12 65.48 14.12 65.48 13.08 65.96 13.08 65.96 11.4 65.48 11.4 65.48 10.36 65.96 10.36 65.96 8.68 65.48 8.68 65.48 7.64 65.96 7.64 65.96 5.96 65.48 5.96 65.48 4.92 65.96 4.92 65.96 3.24 65.48 3.24 65.48 2.2 65.96 2.2 65.96 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 0.76 10.36 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 0.76 81.08 0.76 82.12 0.28 82.12 0.28 83.8 0.76 83.8 0.76 84.84 0.28 84.84 0.28 86.52 ; - LAYER met5 ; - POLYGON 64.64 85.44 64.64 77.32 61.44 77.32 61.44 70.92 64.64 70.92 64.64 56.92 61.44 56.92 61.44 50.52 64.64 50.52 64.64 36.52 61.44 36.52 61.44 30.12 64.64 30.12 64.64 16.12 61.44 16.12 61.44 9.72 64.64 9.72 64.64 1.6 1.6 1.6 1.6 9.72 4.8 9.72 4.8 16.12 1.6 16.12 1.6 30.12 4.8 30.12 4.8 36.52 1.6 36.52 1.6 50.52 4.8 50.52 4.8 56.92 1.6 56.92 1.6 70.92 4.8 70.92 4.8 77.32 1.6 77.32 1.6 85.44 ; - LAYER met4 ; - POLYGON 65.84 86.64 65.84 0.4 55.9 0.4 55.9 1 54.5 1 54.5 0.4 41.18 0.4 41.18 1 39.78 1 39.78 0.4 26.46 0.4 26.46 1 25.06 1 25.06 0.4 11.74 0.4 11.74 1 10.34 1 10.34 0.4 0.4 0.4 0.4 86.64 10.34 86.64 10.34 86.04 11.74 86.04 11.74 86.64 25.06 86.64 25.06 86.04 26.46 86.04 26.46 86.64 39.78 86.64 39.78 86.04 41.18 86.04 41.18 86.64 54.5 86.64 54.5 86.04 55.9 86.04 55.9 86.64 ; - LAYER li1 ; - RECT 0.17 0.17 66.07 86.87 ; - LAYER mcon ; - RECT 65.925 86.955 66.095 87.125 ; - RECT 65.465 86.955 65.635 87.125 ; - RECT 65.005 86.955 65.175 87.125 ; - RECT 64.545 86.955 64.715 87.125 ; - RECT 64.085 86.955 64.255 87.125 ; - RECT 63.625 86.955 63.795 87.125 ; - RECT 63.165 86.955 63.335 87.125 ; - RECT 62.705 86.955 62.875 87.125 ; - RECT 62.245 86.955 62.415 87.125 ; - RECT 61.785 86.955 61.955 87.125 ; - RECT 61.325 86.955 61.495 87.125 ; - RECT 60.865 86.955 61.035 87.125 ; - RECT 60.405 86.955 60.575 87.125 ; - RECT 59.945 86.955 60.115 87.125 ; - RECT 59.485 86.955 59.655 87.125 ; - RECT 59.025 86.955 59.195 87.125 ; - RECT 58.565 86.955 58.735 87.125 ; - RECT 58.105 86.955 58.275 87.125 ; - RECT 57.645 86.955 57.815 87.125 ; - RECT 57.185 86.955 57.355 87.125 ; - RECT 56.725 86.955 56.895 87.125 ; - RECT 56.265 86.955 56.435 87.125 ; - RECT 55.805 86.955 55.975 87.125 ; - RECT 55.345 86.955 55.515 87.125 ; - RECT 54.885 86.955 55.055 87.125 ; - RECT 54.425 86.955 54.595 87.125 ; - RECT 53.965 86.955 54.135 87.125 ; - RECT 53.505 86.955 53.675 87.125 ; - RECT 53.045 86.955 53.215 87.125 ; - RECT 52.585 86.955 52.755 87.125 ; - RECT 52.125 86.955 52.295 87.125 ; - RECT 51.665 86.955 51.835 87.125 ; - RECT 51.205 86.955 51.375 87.125 ; - RECT 50.745 86.955 50.915 87.125 ; - RECT 50.285 86.955 50.455 87.125 ; - RECT 49.825 86.955 49.995 87.125 ; - RECT 49.365 86.955 49.535 87.125 ; - RECT 48.905 86.955 49.075 87.125 ; - RECT 48.445 86.955 48.615 87.125 ; - RECT 47.985 86.955 48.155 87.125 ; - RECT 47.525 86.955 47.695 87.125 ; - RECT 47.065 86.955 47.235 87.125 ; - RECT 46.605 86.955 46.775 87.125 ; - RECT 46.145 86.955 46.315 87.125 ; - RECT 45.685 86.955 45.855 87.125 ; - RECT 45.225 86.955 45.395 87.125 ; - RECT 44.765 86.955 44.935 87.125 ; - RECT 44.305 86.955 44.475 87.125 ; - RECT 43.845 86.955 44.015 87.125 ; - RECT 43.385 86.955 43.555 87.125 ; - RECT 42.925 86.955 43.095 87.125 ; - RECT 42.465 86.955 42.635 87.125 ; - RECT 42.005 86.955 42.175 87.125 ; - RECT 41.545 86.955 41.715 87.125 ; - RECT 41.085 86.955 41.255 87.125 ; - RECT 40.625 86.955 40.795 87.125 ; - RECT 40.165 86.955 40.335 87.125 ; - RECT 39.705 86.955 39.875 87.125 ; - RECT 39.245 86.955 39.415 87.125 ; - RECT 38.785 86.955 38.955 87.125 ; - RECT 38.325 86.955 38.495 87.125 ; - RECT 37.865 86.955 38.035 87.125 ; - RECT 37.405 86.955 37.575 87.125 ; - RECT 36.945 86.955 37.115 87.125 ; - RECT 36.485 86.955 36.655 87.125 ; - RECT 36.025 86.955 36.195 87.125 ; - RECT 35.565 86.955 35.735 87.125 ; - RECT 35.105 86.955 35.275 87.125 ; - RECT 34.645 86.955 34.815 87.125 ; - RECT 34.185 86.955 34.355 87.125 ; - RECT 33.725 86.955 33.895 87.125 ; - RECT 33.265 86.955 33.435 87.125 ; - RECT 32.805 86.955 32.975 87.125 ; - RECT 32.345 86.955 32.515 87.125 ; - RECT 31.885 86.955 32.055 87.125 ; - RECT 31.425 86.955 31.595 87.125 ; - RECT 30.965 86.955 31.135 87.125 ; - RECT 30.505 86.955 30.675 87.125 ; - RECT 30.045 86.955 30.215 87.125 ; - RECT 29.585 86.955 29.755 87.125 ; - RECT 29.125 86.955 29.295 87.125 ; - RECT 28.665 86.955 28.835 87.125 ; - RECT 28.205 86.955 28.375 87.125 ; - RECT 27.745 86.955 27.915 87.125 ; - RECT 27.285 86.955 27.455 87.125 ; - RECT 26.825 86.955 26.995 87.125 ; - RECT 26.365 86.955 26.535 87.125 ; - RECT 25.905 86.955 26.075 87.125 ; - RECT 25.445 86.955 25.615 87.125 ; - RECT 24.985 86.955 25.155 87.125 ; - RECT 24.525 86.955 24.695 87.125 ; - RECT 24.065 86.955 24.235 87.125 ; - RECT 23.605 86.955 23.775 87.125 ; - RECT 23.145 86.955 23.315 87.125 ; - RECT 22.685 86.955 22.855 87.125 ; - RECT 22.225 86.955 22.395 87.125 ; - RECT 21.765 86.955 21.935 87.125 ; - RECT 21.305 86.955 21.475 87.125 ; - RECT 20.845 86.955 21.015 87.125 ; - RECT 20.385 86.955 20.555 87.125 ; - RECT 19.925 86.955 20.095 87.125 ; - RECT 19.465 86.955 19.635 87.125 ; - RECT 19.005 86.955 19.175 87.125 ; - RECT 18.545 86.955 18.715 87.125 ; - RECT 18.085 86.955 18.255 87.125 ; - RECT 17.625 86.955 17.795 87.125 ; - RECT 17.165 86.955 17.335 87.125 ; - RECT 16.705 86.955 16.875 87.125 ; - RECT 16.245 86.955 16.415 87.125 ; - RECT 15.785 86.955 15.955 87.125 ; - RECT 15.325 86.955 15.495 87.125 ; - RECT 14.865 86.955 15.035 87.125 ; - RECT 14.405 86.955 14.575 87.125 ; - RECT 13.945 86.955 14.115 87.125 ; - RECT 13.485 86.955 13.655 87.125 ; - RECT 13.025 86.955 13.195 87.125 ; - RECT 12.565 86.955 12.735 87.125 ; - RECT 12.105 86.955 12.275 87.125 ; - RECT 11.645 86.955 11.815 87.125 ; - RECT 11.185 86.955 11.355 87.125 ; - RECT 10.725 86.955 10.895 87.125 ; - RECT 10.265 86.955 10.435 87.125 ; - RECT 9.805 86.955 9.975 87.125 ; - RECT 9.345 86.955 9.515 87.125 ; - RECT 8.885 86.955 9.055 87.125 ; - RECT 8.425 86.955 8.595 87.125 ; - RECT 7.965 86.955 8.135 87.125 ; - RECT 7.505 86.955 7.675 87.125 ; - RECT 7.045 86.955 7.215 87.125 ; - RECT 6.585 86.955 6.755 87.125 ; - RECT 6.125 86.955 6.295 87.125 ; - RECT 5.665 86.955 5.835 87.125 ; - RECT 5.205 86.955 5.375 87.125 ; - RECT 4.745 86.955 4.915 87.125 ; - RECT 4.285 86.955 4.455 87.125 ; - RECT 3.825 86.955 3.995 87.125 ; - RECT 3.365 86.955 3.535 87.125 ; - RECT 2.905 86.955 3.075 87.125 ; - RECT 2.445 86.955 2.615 87.125 ; - RECT 1.985 86.955 2.155 87.125 ; - RECT 1.525 86.955 1.695 87.125 ; - RECT 1.065 86.955 1.235 87.125 ; - RECT 0.605 86.955 0.775 87.125 ; - RECT 0.145 86.955 0.315 87.125 ; - RECT 65.925 84.235 66.095 84.405 ; - RECT 65.465 84.235 65.635 84.405 ; - RECT 0.605 84.235 0.775 84.405 ; - RECT 0.145 84.235 0.315 84.405 ; - RECT 65.925 81.515 66.095 81.685 ; - RECT 65.465 81.515 65.635 81.685 ; - RECT 0.605 81.515 0.775 81.685 ; - RECT 0.145 81.515 0.315 81.685 ; - RECT 65.925 78.795 66.095 78.965 ; - RECT 65.465 78.795 65.635 78.965 ; - RECT 0.605 78.795 0.775 78.965 ; - RECT 0.145 78.795 0.315 78.965 ; - RECT 65.925 76.075 66.095 76.245 ; - RECT 65.465 76.075 65.635 76.245 ; - RECT 0.605 76.075 0.775 76.245 ; - RECT 0.145 76.075 0.315 76.245 ; - RECT 65.925 73.355 66.095 73.525 ; - RECT 65.465 73.355 65.635 73.525 ; - RECT 0.605 73.355 0.775 73.525 ; - RECT 0.145 73.355 0.315 73.525 ; - RECT 65.925 70.635 66.095 70.805 ; - RECT 65.465 70.635 65.635 70.805 ; - RECT 0.605 70.635 0.775 70.805 ; - RECT 0.145 70.635 0.315 70.805 ; - RECT 65.925 67.915 66.095 68.085 ; - RECT 65.465 67.915 65.635 68.085 ; - RECT 0.605 67.915 0.775 68.085 ; - RECT 0.145 67.915 0.315 68.085 ; - RECT 65.925 65.195 66.095 65.365 ; - RECT 65.465 65.195 65.635 65.365 ; - RECT 0.605 65.195 0.775 65.365 ; - RECT 0.145 65.195 0.315 65.365 ; - RECT 65.925 62.475 66.095 62.645 ; - RECT 65.465 62.475 65.635 62.645 ; - RECT 0.605 62.475 0.775 62.645 ; - RECT 0.145 62.475 0.315 62.645 ; - RECT 65.925 59.755 66.095 59.925 ; - RECT 65.465 59.755 65.635 59.925 ; - RECT 0.605 59.755 0.775 59.925 ; - RECT 0.145 59.755 0.315 59.925 ; - RECT 65.925 57.035 66.095 57.205 ; - RECT 65.465 57.035 65.635 57.205 ; - RECT 0.605 57.035 0.775 57.205 ; - RECT 0.145 57.035 0.315 57.205 ; - RECT 65.925 54.315 66.095 54.485 ; - RECT 65.465 54.315 65.635 54.485 ; - RECT 0.605 54.315 0.775 54.485 ; - RECT 0.145 54.315 0.315 54.485 ; - RECT 65.925 51.595 66.095 51.765 ; - RECT 65.465 51.595 65.635 51.765 ; - RECT 0.605 51.595 0.775 51.765 ; - RECT 0.145 51.595 0.315 51.765 ; - RECT 65.925 48.875 66.095 49.045 ; - RECT 65.465 48.875 65.635 49.045 ; - RECT 0.605 48.875 0.775 49.045 ; - RECT 0.145 48.875 0.315 49.045 ; - RECT 65.925 46.155 66.095 46.325 ; - RECT 65.465 46.155 65.635 46.325 ; - RECT 0.605 46.155 0.775 46.325 ; - RECT 0.145 46.155 0.315 46.325 ; - RECT 65.925 43.435 66.095 43.605 ; - RECT 65.465 43.435 65.635 43.605 ; - RECT 0.605 43.435 0.775 43.605 ; - RECT 0.145 43.435 0.315 43.605 ; - RECT 65.925 40.715 66.095 40.885 ; - RECT 65.465 40.715 65.635 40.885 ; - RECT 0.605 40.715 0.775 40.885 ; - RECT 0.145 40.715 0.315 40.885 ; - RECT 65.925 37.995 66.095 38.165 ; - RECT 65.465 37.995 65.635 38.165 ; - RECT 0.605 37.995 0.775 38.165 ; - RECT 0.145 37.995 0.315 38.165 ; - RECT 65.925 35.275 66.095 35.445 ; - RECT 65.465 35.275 65.635 35.445 ; - RECT 0.605 35.275 0.775 35.445 ; - RECT 0.145 35.275 0.315 35.445 ; - RECT 65.925 32.555 66.095 32.725 ; - RECT 65.465 32.555 65.635 32.725 ; - RECT 0.605 32.555 0.775 32.725 ; - RECT 0.145 32.555 0.315 32.725 ; - RECT 65.925 29.835 66.095 30.005 ; - RECT 65.465 29.835 65.635 30.005 ; - RECT 0.605 29.835 0.775 30.005 ; - RECT 0.145 29.835 0.315 30.005 ; - RECT 65.925 27.115 66.095 27.285 ; - RECT 65.465 27.115 65.635 27.285 ; - RECT 0.605 27.115 0.775 27.285 ; - RECT 0.145 27.115 0.315 27.285 ; - RECT 65.925 24.395 66.095 24.565 ; - RECT 65.465 24.395 65.635 24.565 ; - RECT 0.605 24.395 0.775 24.565 ; - RECT 0.145 24.395 0.315 24.565 ; - RECT 65.925 21.675 66.095 21.845 ; - RECT 65.465 21.675 65.635 21.845 ; - RECT 0.605 21.675 0.775 21.845 ; - RECT 0.145 21.675 0.315 21.845 ; - RECT 65.925 18.955 66.095 19.125 ; - RECT 65.465 18.955 65.635 19.125 ; - RECT 0.605 18.955 0.775 19.125 ; - RECT 0.145 18.955 0.315 19.125 ; - RECT 65.925 16.235 66.095 16.405 ; - RECT 65.465 16.235 65.635 16.405 ; - RECT 0.605 16.235 0.775 16.405 ; - RECT 0.145 16.235 0.315 16.405 ; - RECT 65.925 13.515 66.095 13.685 ; - RECT 65.465 13.515 65.635 13.685 ; - RECT 0.605 13.515 0.775 13.685 ; - RECT 0.145 13.515 0.315 13.685 ; - RECT 65.925 10.795 66.095 10.965 ; - RECT 65.465 10.795 65.635 10.965 ; - RECT 0.605 10.795 0.775 10.965 ; - RECT 0.145 10.795 0.315 10.965 ; - RECT 65.925 8.075 66.095 8.245 ; - RECT 65.465 8.075 65.635 8.245 ; - RECT 0.605 8.075 0.775 8.245 ; - RECT 0.145 8.075 0.315 8.245 ; - RECT 65.925 5.355 66.095 5.525 ; - RECT 65.465 5.355 65.635 5.525 ; - RECT 0.605 5.355 0.775 5.525 ; - RECT 0.145 5.355 0.315 5.525 ; - RECT 65.925 2.635 66.095 2.805 ; - RECT 65.465 2.635 65.635 2.805 ; - RECT 0.605 2.635 0.775 2.805 ; - RECT 0.145 2.635 0.315 2.805 ; - RECT 65.925 -0.085 66.095 0.085 ; - RECT 65.465 -0.085 65.635 0.085 ; - RECT 65.005 -0.085 65.175 0.085 ; - RECT 64.545 -0.085 64.715 0.085 ; - RECT 64.085 -0.085 64.255 0.085 ; - RECT 63.625 -0.085 63.795 0.085 ; - RECT 63.165 -0.085 63.335 0.085 ; - RECT 62.705 -0.085 62.875 0.085 ; - RECT 62.245 -0.085 62.415 0.085 ; - RECT 61.785 -0.085 61.955 0.085 ; - RECT 61.325 -0.085 61.495 0.085 ; - RECT 60.865 -0.085 61.035 0.085 ; - RECT 60.405 -0.085 60.575 0.085 ; - RECT 59.945 -0.085 60.115 0.085 ; - RECT 59.485 -0.085 59.655 0.085 ; - RECT 59.025 -0.085 59.195 0.085 ; - RECT 58.565 -0.085 58.735 0.085 ; - RECT 58.105 -0.085 58.275 0.085 ; - RECT 57.645 -0.085 57.815 0.085 ; - RECT 57.185 -0.085 57.355 0.085 ; - RECT 56.725 -0.085 56.895 0.085 ; - RECT 56.265 -0.085 56.435 0.085 ; - RECT 55.805 -0.085 55.975 0.085 ; - RECT 55.345 -0.085 55.515 0.085 ; - RECT 54.885 -0.085 55.055 0.085 ; - RECT 54.425 -0.085 54.595 0.085 ; - RECT 53.965 -0.085 54.135 0.085 ; - RECT 53.505 -0.085 53.675 0.085 ; - RECT 53.045 -0.085 53.215 0.085 ; - RECT 52.585 -0.085 52.755 0.085 ; - RECT 52.125 -0.085 52.295 0.085 ; - RECT 51.665 -0.085 51.835 0.085 ; - RECT 51.205 -0.085 51.375 0.085 ; - RECT 50.745 -0.085 50.915 0.085 ; - RECT 50.285 -0.085 50.455 0.085 ; - RECT 49.825 -0.085 49.995 0.085 ; - RECT 49.365 -0.085 49.535 0.085 ; - RECT 48.905 -0.085 49.075 0.085 ; - RECT 48.445 -0.085 48.615 0.085 ; - RECT 47.985 -0.085 48.155 0.085 ; - RECT 47.525 -0.085 47.695 0.085 ; - RECT 47.065 -0.085 47.235 0.085 ; - RECT 46.605 -0.085 46.775 0.085 ; - RECT 46.145 -0.085 46.315 0.085 ; - RECT 45.685 -0.085 45.855 0.085 ; - RECT 45.225 -0.085 45.395 0.085 ; - RECT 44.765 -0.085 44.935 0.085 ; - RECT 44.305 -0.085 44.475 0.085 ; - RECT 43.845 -0.085 44.015 0.085 ; - RECT 43.385 -0.085 43.555 0.085 ; - RECT 42.925 -0.085 43.095 0.085 ; - RECT 42.465 -0.085 42.635 0.085 ; - RECT 42.005 -0.085 42.175 0.085 ; - RECT 41.545 -0.085 41.715 0.085 ; - RECT 41.085 -0.085 41.255 0.085 ; - RECT 40.625 -0.085 40.795 0.085 ; - RECT 40.165 -0.085 40.335 0.085 ; - RECT 39.705 -0.085 39.875 0.085 ; - RECT 39.245 -0.085 39.415 0.085 ; - RECT 38.785 -0.085 38.955 0.085 ; - RECT 38.325 -0.085 38.495 0.085 ; - RECT 37.865 -0.085 38.035 0.085 ; - RECT 37.405 -0.085 37.575 0.085 ; - RECT 36.945 -0.085 37.115 0.085 ; - RECT 36.485 -0.085 36.655 0.085 ; - RECT 36.025 -0.085 36.195 0.085 ; - RECT 35.565 -0.085 35.735 0.085 ; - RECT 35.105 -0.085 35.275 0.085 ; - RECT 34.645 -0.085 34.815 0.085 ; - RECT 34.185 -0.085 34.355 0.085 ; - RECT 33.725 -0.085 33.895 0.085 ; - RECT 33.265 -0.085 33.435 0.085 ; - RECT 32.805 -0.085 32.975 0.085 ; - RECT 32.345 -0.085 32.515 0.085 ; - RECT 31.885 -0.085 32.055 0.085 ; - RECT 31.425 -0.085 31.595 0.085 ; - RECT 30.965 -0.085 31.135 0.085 ; - RECT 30.505 -0.085 30.675 0.085 ; - RECT 30.045 -0.085 30.215 0.085 ; - RECT 29.585 -0.085 29.755 0.085 ; - RECT 29.125 -0.085 29.295 0.085 ; - RECT 28.665 -0.085 28.835 0.085 ; - RECT 28.205 -0.085 28.375 0.085 ; - RECT 27.745 -0.085 27.915 0.085 ; - RECT 27.285 -0.085 27.455 0.085 ; - RECT 26.825 -0.085 26.995 0.085 ; - RECT 26.365 -0.085 26.535 0.085 ; - RECT 25.905 -0.085 26.075 0.085 ; - RECT 25.445 -0.085 25.615 0.085 ; - RECT 24.985 -0.085 25.155 0.085 ; - RECT 24.525 -0.085 24.695 0.085 ; - RECT 24.065 -0.085 24.235 0.085 ; - RECT 23.605 -0.085 23.775 0.085 ; - RECT 23.145 -0.085 23.315 0.085 ; - RECT 22.685 -0.085 22.855 0.085 ; - RECT 22.225 -0.085 22.395 0.085 ; - RECT 21.765 -0.085 21.935 0.085 ; - RECT 21.305 -0.085 21.475 0.085 ; - RECT 20.845 -0.085 21.015 0.085 ; - RECT 20.385 -0.085 20.555 0.085 ; - RECT 19.925 -0.085 20.095 0.085 ; - RECT 19.465 -0.085 19.635 0.085 ; - RECT 19.005 -0.085 19.175 0.085 ; - RECT 18.545 -0.085 18.715 0.085 ; - RECT 18.085 -0.085 18.255 0.085 ; - RECT 17.625 -0.085 17.795 0.085 ; - RECT 17.165 -0.085 17.335 0.085 ; - RECT 16.705 -0.085 16.875 0.085 ; - RECT 16.245 -0.085 16.415 0.085 ; - RECT 15.785 -0.085 15.955 0.085 ; - RECT 15.325 -0.085 15.495 0.085 ; - RECT 14.865 -0.085 15.035 0.085 ; - RECT 14.405 -0.085 14.575 0.085 ; - RECT 13.945 -0.085 14.115 0.085 ; - RECT 13.485 -0.085 13.655 0.085 ; - RECT 13.025 -0.085 13.195 0.085 ; - RECT 12.565 -0.085 12.735 0.085 ; - RECT 12.105 -0.085 12.275 0.085 ; - RECT 11.645 -0.085 11.815 0.085 ; - RECT 11.185 -0.085 11.355 0.085 ; - RECT 10.725 -0.085 10.895 0.085 ; - RECT 10.265 -0.085 10.435 0.085 ; - RECT 9.805 -0.085 9.975 0.085 ; - RECT 9.345 -0.085 9.515 0.085 ; - RECT 8.885 -0.085 9.055 0.085 ; - RECT 8.425 -0.085 8.595 0.085 ; - RECT 7.965 -0.085 8.135 0.085 ; - RECT 7.505 -0.085 7.675 0.085 ; - RECT 7.045 -0.085 7.215 0.085 ; - RECT 6.585 -0.085 6.755 0.085 ; - RECT 6.125 -0.085 6.295 0.085 ; - RECT 5.665 -0.085 5.835 0.085 ; - RECT 5.205 -0.085 5.375 0.085 ; - RECT 4.745 -0.085 4.915 0.085 ; - RECT 4.285 -0.085 4.455 0.085 ; - RECT 3.825 -0.085 3.995 0.085 ; - RECT 3.365 -0.085 3.535 0.085 ; - RECT 2.905 -0.085 3.075 0.085 ; - RECT 2.445 -0.085 2.615 0.085 ; - RECT 1.985 -0.085 2.155 0.085 ; - RECT 1.525 -0.085 1.695 0.085 ; - RECT 1.065 -0.085 1.235 0.085 ; - RECT 0.605 -0.085 0.775 0.085 ; - RECT 0.145 -0.085 0.315 0.085 ; - LAYER via ; - RECT 55.125 86.965 55.275 87.115 ; - RECT 25.685 86.965 25.835 87.115 ; - RECT 37.645 1.625 37.795 1.775 ; - RECT 55.125 -0.075 55.275 0.075 ; - RECT 25.685 -0.075 25.835 0.075 ; - LAYER via2 ; - RECT 55.1 86.94 55.3 87.14 ; - RECT 25.66 86.94 25.86 87.14 ; - RECT 64.76 78.78 64.96 78.98 ; - RECT 1.28 57.7 1.48 57.9 ; - RECT 1.28 47.5 1.48 47.7 ; - RECT 1.74 42.74 1.94 42.94 ; - RECT 1.74 41.38 1.94 41.58 ; - RECT 64.3 40.02 64.5 40.22 ; - RECT 1.28 40.02 1.48 40.22 ; - RECT 1.28 37.3 1.48 37.5 ; - RECT 1.28 27.1 1.48 27.3 ; - RECT 1.28 24.38 1.48 24.58 ; - RECT 64.76 18.26 64.96 18.46 ; - RECT 1.28 18.26 1.48 18.46 ; - RECT 1.28 12.14 1.48 12.34 ; - RECT 1.74 9.42 1.94 9.62 ; - RECT 55.1 -0.1 55.3 0.1 ; - RECT 25.66 -0.1 25.86 0.1 ; - LAYER via3 ; - RECT 55.1 86.94 55.3 87.14 ; - RECT 25.66 86.94 25.86 87.14 ; - RECT 1.74 38.66 1.94 38.86 ; - RECT 1.74 10.78 1.94 10.98 ; - RECT 55.1 -0.1 55.3 0.1 ; - RECT 25.66 -0.1 25.86 0.1 ; - LAYER OVERLAP ; - POLYGON 0 0 0 87.04 66.24 87.04 66.24 0 ; - END -END cbx_1__2_ - -END LIBRARY diff --git a/FPGA22_HIER_SKY_PNR/modules/lef/cby_0__1__icv_in_design.lef b/FPGA22_HIER_SKY_PNR/modules/lef/cby_0__1__icv_in_design.lef deleted file mode 100644 index 06d8f74..0000000 --- a/FPGA22_HIER_SKY_PNR/modules/lef/cby_0__1__icv_in_design.lef +++ /dev/null @@ -1,1673 +0,0 @@ -VERSION 5.7 ; -BUSBITCHARS "[]" ; - -UNITS - DATABASE MICRONS 1000 ; -END UNITS - -MANUFACTURINGGRID 0.005 ; - -LAYER li1 - TYPE ROUTING ; - DIRECTION VERTICAL ; - PITCH 0.46 ; - WIDTH 0.17 ; -END li1 - -LAYER mcon - TYPE CUT ; -END mcon - -LAYER met1 - TYPE ROUTING ; - DIRECTION HORIZONTAL ; - PITCH 0.34 ; - WIDTH 0.14 ; -END met1 - -LAYER via - TYPE CUT ; -END via - -LAYER met2 - TYPE ROUTING ; - DIRECTION VERTICAL ; - PITCH 0.46 ; - WIDTH 0.14 ; -END met2 - -LAYER via2 - TYPE CUT ; -END via2 - -LAYER met3 - TYPE ROUTING ; - DIRECTION HORIZONTAL ; - PITCH 0.68 ; - WIDTH 0.3 ; -END met3 - -LAYER via3 - TYPE CUT ; -END via3 - -LAYER met4 - TYPE ROUTING ; - DIRECTION VERTICAL ; - PITCH 0.92 ; - WIDTH 0.3 ; -END met4 - -LAYER via4 - TYPE CUT ; -END via4 - -LAYER met5 - TYPE ROUTING ; - DIRECTION HORIZONTAL ; - PITCH 3.4 ; - WIDTH 1.6 ; -END met5 - -LAYER nwell - TYPE MASTERSLICE ; -END nwell - -LAYER pwell - TYPE MASTERSLICE ; -END pwell - -LAYER OVERLAP - TYPE OVERLAP ; -END OVERLAP - -VIA L1M1_PR - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.145 -0.115 0.145 0.115 ; -END L1M1_PR - -VIA L1M1_PR_R - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.115 -0.145 0.115 0.145 ; -END L1M1_PR_R - -VIA L1M1_PR_M - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.115 -0.145 0.115 0.145 ; -END L1M1_PR_M - -VIA L1M1_PR_MR - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.145 -0.115 0.145 0.115 ; -END L1M1_PR_MR - -VIA L1M1_PR_C - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.145 -0.145 0.145 0.145 ; -END L1M1_PR_C - -VIA M1M2_PR - LAYER met1 ; - RECT -0.16 -0.13 0.16 0.13 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.13 -0.16 0.13 0.16 ; -END M1M2_PR - -VIA M1M2_PR_Enc - LAYER met1 ; - RECT -0.16 -0.13 0.16 0.13 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.16 -0.13 0.16 0.13 ; -END M1M2_PR_Enc - -VIA M1M2_PR_R - LAYER met1 ; - RECT -0.13 -0.16 0.13 0.16 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.16 -0.13 0.16 0.13 ; -END M1M2_PR_R - -VIA M1M2_PR_R_Enc - LAYER met1 ; - RECT -0.13 -0.16 0.13 0.16 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.13 -0.16 0.13 0.16 ; -END M1M2_PR_R_Enc - -VIA M1M2_PR_M - LAYER met1 ; - RECT -0.16 -0.13 0.16 0.13 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.16 -0.13 0.16 0.13 ; -END M1M2_PR_M - -VIA M1M2_PR_M_Enc - LAYER met1 ; - RECT -0.16 -0.13 0.16 0.13 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.13 -0.16 0.13 0.16 ; -END M1M2_PR_M_Enc - -VIA M1M2_PR_MR - LAYER met1 ; - RECT -0.13 -0.16 0.13 0.16 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.13 -0.16 0.13 0.16 ; -END M1M2_PR_MR - -VIA M1M2_PR_MR_Enc - LAYER met1 ; - RECT -0.13 -0.16 0.13 0.16 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.16 -0.13 0.16 0.13 ; -END M1M2_PR_MR_Enc - -VIA M1M2_PR_C - LAYER met1 ; - RECT -0.16 -0.16 0.16 0.16 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.16 -0.16 0.16 0.16 ; -END M1M2_PR_C - -VIA M2M3_PR - LAYER met2 ; - RECT -0.14 -0.185 0.14 0.185 ; - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met3 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M2M3_PR - -VIA M2M3_PR_R - LAYER met2 ; - RECT -0.185 -0.14 0.185 0.14 ; - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met3 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M2M3_PR_R - -VIA M2M3_PR_M - LAYER met2 ; - RECT -0.14 -0.185 0.14 0.185 ; - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met3 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M2M3_PR_M - -VIA M2M3_PR_MR - LAYER met2 ; - RECT -0.185 -0.14 0.185 0.14 ; - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met3 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M2M3_PR_MR - -VIA M2M3_PR_C - LAYER met2 ; - RECT -0.185 -0.185 0.185 0.185 ; - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met3 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M2M3_PR_C - -VIA M3M4_PR - LAYER met3 ; - RECT -0.19 -0.16 0.19 0.16 ; - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR - -VIA M3M4_PR_R - LAYER met3 ; - RECT -0.16 -0.19 0.16 0.19 ; - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR_R - -VIA M3M4_PR_M - LAYER met3 ; - RECT -0.19 -0.16 0.19 0.16 ; - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR_M - -VIA M3M4_PR_MR - LAYER met3 ; - RECT -0.16 -0.19 0.16 0.19 ; - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR_MR - -VIA M3M4_PR_C - LAYER met3 ; - RECT -0.19 -0.19 0.19 0.19 ; - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR_C - -VIA M4M5_PR - LAYER met4 ; - RECT -0.59 -0.59 0.59 0.59 ; - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - LAYER met5 ; - RECT -0.71 -0.71 0.71 0.71 ; -END M4M5_PR - -VIA M4M5_PR_R - LAYER met4 ; - RECT -0.59 -0.59 0.59 0.59 ; - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - LAYER met5 ; - RECT -0.71 -0.71 0.71 0.71 ; -END M4M5_PR_R - -VIA M4M5_PR_M - LAYER met4 ; - RECT -0.59 -0.59 0.59 0.59 ; - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - LAYER met5 ; - RECT -0.71 -0.71 0.71 0.71 ; -END M4M5_PR_M - -VIA M4M5_PR_MR - LAYER met4 ; - RECT -0.59 -0.59 0.59 0.59 ; - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - LAYER met5 ; - RECT -0.71 -0.71 0.71 0.71 ; -END M4M5_PR_MR - -VIA M4M5_PR_C - LAYER met4 ; - RECT -0.59 -0.59 0.59 0.59 ; - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - LAYER met5 ; - RECT -0.71 -0.71 0.71 0.71 ; -END M4M5_PR_C - -SITE unit - CLASS CORE ; - SYMMETRY Y ; - SIZE 0.46 BY 2.72 ; -END unit - -SITE unithddbl - CLASS CORE ; - SIZE 0.46 BY 5.44 ; -END unithddbl - -MACRO cby_0__1_ - CLASS BLOCK ; - ORIGIN 0 0 ; - SIZE 66.24 BY 76.16 ; - SYMMETRY X Y ; - PIN prog_clk[0] - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER met2 ; - RECT 61.57 0 61.71 1.36 ; - END - END prog_clk[0] - PIN chany_bottom_in[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 45.47 0 45.61 1.36 ; - END - END chany_bottom_in[0] - PIN chany_bottom_in[1] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 12.73 0 13.03 1.36 ; - END - END chany_bottom_in[1] - PIN chany_bottom_in[2] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 47.31 0 47.45 1.36 ; - END - END chany_bottom_in[2] - PIN chany_bottom_in[3] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 5.37 0 5.67 1.36 ; - END - END chany_bottom_in[3] - PIN chany_bottom_in[4] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 56.05 0 56.19 1.36 ; - END - END chany_bottom_in[4] - PIN chany_bottom_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 46.77 0 47.07 1.36 ; - END - END chany_bottom_in[5] - PIN chany_bottom_in[6] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 34.81 0 35.11 1.36 ; - END - END chany_bottom_in[6] - PIN chany_bottom_in[7] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 23.77 0 24.07 1.36 ; - END - END chany_bottom_in[7] - PIN chany_bottom_in[8] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 7.21 0 7.51 1.36 ; - END - END chany_bottom_in[8] - PIN chany_bottom_in[9] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 32.97 0 33.27 1.36 ; - END - END chany_bottom_in[9] - PIN chany_bottom_in[10] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 48.23 0 48.37 1.36 ; - END - END chany_bottom_in[10] - PIN chany_bottom_in[11] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 48.61 0 48.91 1.36 ; - END - END chany_bottom_in[11] - PIN chany_bottom_in[12] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 50.99 0 51.13 1.36 ; - END - END chany_bottom_in[12] - PIN chany_bottom_in[13] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 31.13 0 31.43 1.36 ; - END - END chany_bottom_in[13] - PIN chany_bottom_in[14] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 9.05 0 9.35 1.36 ; - END - END chany_bottom_in[14] - PIN chany_bottom_in[15] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 27.45 0 27.75 1.36 ; - END - END chany_bottom_in[15] - PIN chany_bottom_in[16] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 51.91 0 52.05 1.36 ; - END - END chany_bottom_in[16] - PIN chany_bottom_in[17] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 52.29 0 52.59 1.36 ; - END - END chany_bottom_in[17] - PIN chany_bottom_in[18] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 50.45 0 50.75 1.36 ; - END - END chany_bottom_in[18] - PIN chany_bottom_in[19] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 29.29 0 29.59 1.36 ; - END - END chany_bottom_in[19] - PIN chany_top_in[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 47.31 74.8 47.45 76.16 ; - END - END chany_top_in[0] - PIN chany_top_in[1] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 49.15 74.8 49.29 76.16 ; - END - END chany_top_in[1] - PIN chany_top_in[2] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 53.75 74.8 53.89 76.16 ; - END - END chany_top_in[2] - PIN chany_top_in[3] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 46.77 74.8 47.07 76.16 ; - END - END chany_top_in[3] - PIN chany_top_in[4] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 57.43 74.8 57.57 76.16 ; - END - END chany_top_in[4] - PIN chany_top_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 5.37 74.8 5.67 76.16 ; - END - END chany_top_in[5] - PIN chany_top_in[6] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 27.45 74.8 27.75 76.16 ; - END - END chany_top_in[6] - PIN chany_top_in[7] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 48.61 74.8 48.91 76.16 ; - END - END chany_top_in[7] - PIN chany_top_in[8] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 51.91 74.8 52.05 76.16 ; - END - END chany_top_in[8] - PIN chany_top_in[9] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 52.29 74.8 52.59 76.16 ; - END - END chany_top_in[9] - PIN chany_top_in[10] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 56.05 74.8 56.19 76.16 ; - END - END chany_top_in[10] - PIN chany_top_in[11] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 29.29 74.8 29.59 76.16 ; - END - END chany_top_in[11] - PIN chany_top_in[12] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 28.45 74.8 28.59 76.16 ; - END - END chany_top_in[12] - PIN chany_top_in[13] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 7.21 74.8 7.51 76.16 ; - END - END chany_top_in[13] - PIN chany_top_in[14] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 9.05 74.8 9.35 76.16 ; - END - END chany_top_in[14] - PIN chany_top_in[15] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 50.45 74.8 50.75 76.16 ; - END - END chany_top_in[15] - PIN chany_top_in[16] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 42.71 74.8 42.85 76.16 ; - END - END chany_top_in[16] - PIN chany_top_in[17] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 50.07 74.8 50.21 76.16 ; - END - END chany_top_in[17] - PIN chany_top_in[18] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 9.13 74.8 9.27 76.16 ; - END - END chany_top_in[18] - PIN chany_top_in[19] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 50.99 74.8 51.13 76.16 ; - END - END chany_top_in[19] - PIN ccff_head[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 40.87 74.8 41.01 76.16 ; - END - END ccff_head[0] - PIN chany_bottom_out[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 44.55 0 44.69 1.36 ; - END - END chany_bottom_out[0] - PIN chany_bottom_out[1] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 53.75 0 53.89 1.36 ; - END - END chany_bottom_out[1] - PIN chany_bottom_out[2] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 57.89 0 58.03 1.36 ; - END - END chany_bottom_out[2] - PIN chany_bottom_out[3] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 46.39 0 46.53 1.36 ; - END - END chany_bottom_out[3] - PIN chany_bottom_out[4] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 39.95 0 40.09 1.36 ; - END - END chany_bottom_out[4] - PIN chany_bottom_out[5] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 27.53 0 27.67 1.36 ; - END - END chany_bottom_out[5] - PIN chany_bottom_out[6] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 8.21 0 8.35 1.36 ; - END - END chany_bottom_out[6] - PIN chany_bottom_out[7] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 28.45 0 28.59 1.36 ; - END - END chany_bottom_out[7] - PIN chany_bottom_out[8] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 29.37 0 29.51 1.36 ; - END - END chany_bottom_out[8] - PIN chany_bottom_out[9] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 36.65 0 36.95 1.36 ; - END - END chany_bottom_out[9] - PIN chany_bottom_out[10] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 44.93 0 45.23 1.36 ; - END - END chany_bottom_out[10] - PIN chany_bottom_out[11] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 50.07 0 50.21 1.36 ; - END - END chany_bottom_out[11] - PIN chany_bottom_out[12] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 49.15 0 49.29 1.36 ; - END - END chany_bottom_out[12] - PIN chany_bottom_out[13] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 56.97 0 57.11 1.36 ; - END - END chany_bottom_out[13] - PIN chany_bottom_out[14] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 9.13 0 9.27 1.36 ; - END - END chany_bottom_out[14] - PIN chany_bottom_out[15] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 30.29 0 30.43 1.36 ; - END - END chany_bottom_out[15] - PIN chany_bottom_out[16] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 33.51 0 33.65 1.36 ; - END - END chany_bottom_out[16] - PIN chany_bottom_out[17] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 56.89 0 57.19 1.36 ; - END - END chany_bottom_out[17] - PIN chany_bottom_out[18] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 21.93 0 22.23 1.36 ; - END - END chany_bottom_out[18] - PIN chany_bottom_out[19] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 52.83 0 52.97 1.36 ; - END - END chany_bottom_out[19] - PIN chany_top_out[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 61.11 74.8 61.25 76.16 ; - END - END chany_top_out[0] - PIN chany_top_out[1] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 60.19 74.8 60.33 76.16 ; - END - END chany_top_out[1] - PIN chany_top_out[2] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 44.55 74.8 44.69 76.16 ; - END - END chany_top_out[2] - PIN chany_top_out[3] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 46.39 74.8 46.53 76.16 ; - END - END chany_top_out[3] - PIN chany_top_out[4] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 58.35 74.8 58.49 76.16 ; - END - END chany_top_out[4] - PIN chany_top_out[5] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 27.53 74.8 27.67 76.16 ; - END - END chany_top_out[5] - PIN chany_top_out[6] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 33.05 74.8 33.19 76.16 ; - END - END chany_top_out[6] - PIN chany_top_out[7] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 52.83 74.8 52.97 76.16 ; - END - END chany_top_out[7] - PIN chany_top_out[8] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 10.05 74.8 10.19 76.16 ; - END - END chany_top_out[8] - PIN chany_top_out[9] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 26.61 74.8 26.75 76.16 ; - END - END chany_top_out[9] - PIN chany_top_out[10] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 17.87 74.8 18.01 76.16 ; - END - END chany_top_out[10] - PIN chany_top_out[11] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 48.23 74.8 48.37 76.16 ; - END - END chany_top_out[11] - PIN chany_top_out[12] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 45.47 74.8 45.61 76.16 ; - END - END chany_top_out[12] - PIN chany_top_out[13] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 32.13 74.8 32.27 76.16 ; - END - END chany_top_out[13] - PIN chany_top_out[14] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 29.37 74.8 29.51 76.16 ; - END - END chany_top_out[14] - PIN chany_top_out[15] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 30.29 74.8 30.43 76.16 ; - END - END chany_top_out[15] - PIN chany_top_out[16] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 39.03 74.8 39.17 76.16 ; - END - END chany_top_out[16] - PIN chany_top_out[17] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 8.21 74.8 8.35 76.16 ; - END - END chany_top_out[17] - PIN chany_top_out[18] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 7.29 74.8 7.43 76.16 ; - END - END chany_top_out[18] - PIN chany_top_out[19] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 31.21 74.8 31.35 76.16 ; - END - END chany_top_out[19] - PIN left_grid_pin_0_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 19.25 0 19.39 1.36 ; - END - END left_grid_pin_0_[0] - PIN ccff_tail[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 51.53 66.24 51.83 ; - END - END ccff_tail[0] - PIN gfpga_pad_EMBEDDED_IO_SOC_IN[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 27.73 1.38 28.03 ; - END - END gfpga_pad_EMBEDDED_IO_SOC_IN[0] - PIN gfpga_pad_EMBEDDED_IO_SOC_OUT[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 64.45 1.38 64.75 ; - END - END gfpga_pad_EMBEDDED_IO_SOC_OUT[0] - PIN gfpga_pad_EMBEDDED_IO_SOC_DIR[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 65.81 1.38 66.11 ; - END - END gfpga_pad_EMBEDDED_IO_SOC_DIR[0] - PIN right_width_0_height_0__pin_0_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 20.17 0 20.31 1.36 ; - END - END right_width_0_height_0__pin_0_[0] - PIN right_width_0_height_0__pin_1_upper[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 59.27 74.8 59.41 76.16 ; - END - END right_width_0_height_0__pin_1_upper[0] - PIN right_width_0_height_0__pin_1_lower[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 60.19 0 60.33 1.36 ; - END - END right_width_0_height_0__pin_1_lower[0] - PIN VDD - DIRECTION INPUT ; - USE POWER ; - PORT - LAYER met5 ; - RECT 0 5.88 3.2 9.08 ; - RECT 63.04 5.88 66.24 9.08 ; - RECT 0 46.68 3.2 49.88 ; - RECT 63.04 46.68 66.24 49.88 ; - LAYER met4 ; - RECT 10.74 0 11.34 0.6 ; - RECT 40.18 0 40.78 0.6 ; - RECT 10.74 75.56 11.34 76.16 ; - RECT 40.18 75.56 40.78 76.16 ; - LAYER met1 ; - RECT 0 2.48 0.48 2.96 ; - RECT 65.76 2.48 66.24 2.96 ; - RECT 0 7.92 0.48 8.4 ; - RECT 65.76 7.92 66.24 8.4 ; - RECT 0 13.36 0.48 13.84 ; - RECT 65.76 13.36 66.24 13.84 ; - RECT 0 18.8 0.48 19.28 ; - RECT 65.76 18.8 66.24 19.28 ; - RECT 0 24.24 0.48 24.72 ; - RECT 65.76 24.24 66.24 24.72 ; - RECT 0 29.68 0.48 30.16 ; - RECT 65.76 29.68 66.24 30.16 ; - RECT 0 35.12 0.48 35.6 ; - RECT 65.76 35.12 66.24 35.6 ; - RECT 0 40.56 0.48 41.04 ; - RECT 65.76 40.56 66.24 41.04 ; - RECT 0 46 0.48 46.48 ; - RECT 65.76 46 66.24 46.48 ; - RECT 0 51.44 0.48 51.92 ; - RECT 65.76 51.44 66.24 51.92 ; - RECT 0 56.88 0.48 57.36 ; - RECT 65.76 56.88 66.24 57.36 ; - RECT 0 62.32 0.48 62.8 ; - RECT 65.76 62.32 66.24 62.8 ; - RECT 0 67.76 0.48 68.24 ; - RECT 65.76 67.76 66.24 68.24 ; - RECT 0 73.2 0.48 73.68 ; - RECT 65.76 73.2 66.24 73.68 ; - END - END VDD - PIN VSS - DIRECTION INPUT ; - USE GROUND ; - PORT - LAYER met5 ; - RECT 0 26.28 3.2 29.48 ; - RECT 63.04 26.28 66.24 29.48 ; - RECT 0 67.08 3.2 70.28 ; - RECT 63.04 67.08 66.24 70.28 ; - LAYER met4 ; - RECT 25.46 0 26.06 0.6 ; - RECT 54.9 0 55.5 0.6 ; - RECT 25.46 75.56 26.06 76.16 ; - RECT 54.9 75.56 55.5 76.16 ; - LAYER met1 ; - RECT 0 0 66.24 0.24 ; - RECT 0 5.2 0.48 5.68 ; - RECT 65.76 5.2 66.24 5.68 ; - RECT 0 10.64 0.48 11.12 ; - RECT 65.76 10.64 66.24 11.12 ; - RECT 0 16.08 0.48 16.56 ; - RECT 65.76 16.08 66.24 16.56 ; - RECT 0 21.52 0.48 22 ; - RECT 65.76 21.52 66.24 22 ; - RECT 0 26.96 0.48 27.44 ; - RECT 65.76 26.96 66.24 27.44 ; - RECT 0 32.4 0.48 32.88 ; - RECT 65.76 32.4 66.24 32.88 ; - RECT 0 37.84 0.48 38.32 ; - RECT 65.76 37.84 66.24 38.32 ; - RECT 0 43.28 0.48 43.76 ; - RECT 65.76 43.28 66.24 43.76 ; - RECT 0 48.72 0.48 49.2 ; - RECT 65.76 48.72 66.24 49.2 ; - RECT 0 54.16 0.48 54.64 ; - RECT 65.76 54.16 66.24 54.64 ; - RECT 0 59.6 0.48 60.08 ; - RECT 65.76 59.6 66.24 60.08 ; - RECT 0 65.04 0.48 65.52 ; - RECT 65.76 65.04 66.24 65.52 ; - RECT 0 70.48 0.48 70.96 ; - RECT 65.76 70.48 66.24 70.96 ; - RECT 0 75.92 66.24 76.16 ; - END - END VSS - OBS - LAYER li1 ; - RECT 0 76.075 66.24 76.245 ; - RECT 65.32 73.355 66.24 73.525 ; - RECT 0 73.355 3.68 73.525 ; - RECT 65.32 70.635 66.24 70.805 ; - RECT 0 70.635 3.68 70.805 ; - RECT 65.32 67.915 66.24 68.085 ; - RECT 0 67.915 3.68 68.085 ; - RECT 65.32 65.195 66.24 65.365 ; - RECT 0 65.195 1.84 65.365 ; - RECT 65.32 62.475 66.24 62.645 ; - RECT 0 62.475 3.68 62.645 ; - RECT 65.32 59.755 66.24 59.925 ; - RECT 0 59.755 3.68 59.925 ; - RECT 65.32 57.035 66.24 57.205 ; - RECT 0 57.035 3.68 57.205 ; - RECT 65.32 54.315 66.24 54.485 ; - RECT 0 54.315 3.68 54.485 ; - RECT 65.32 51.595 66.24 51.765 ; - RECT 0 51.595 3.68 51.765 ; - RECT 65.78 48.875 66.24 49.045 ; - RECT 0 48.875 3.68 49.045 ; - RECT 65.78 46.155 66.24 46.325 ; - RECT 0 46.155 3.68 46.325 ; - RECT 62.56 43.435 66.24 43.605 ; - RECT 0 43.435 3.68 43.605 ; - RECT 62.56 40.715 66.24 40.885 ; - RECT 0 40.715 3.68 40.885 ; - RECT 62.56 37.995 66.24 38.165 ; - RECT 0 37.995 3.68 38.165 ; - RECT 62.56 35.275 66.24 35.445 ; - RECT 0 35.275 3.68 35.445 ; - RECT 62.56 32.555 66.24 32.725 ; - RECT 0 32.555 3.68 32.725 ; - RECT 64.4 29.835 66.24 30.005 ; - RECT 0 29.835 3.68 30.005 ; - RECT 65.78 27.115 66.24 27.285 ; - RECT 0 27.115 3.68 27.285 ; - RECT 65.78 24.395 66.24 24.565 ; - RECT 0 24.395 3.68 24.565 ; - RECT 65.78 21.675 66.24 21.845 ; - RECT 0 21.675 3.68 21.845 ; - RECT 62.56 18.955 66.24 19.125 ; - RECT 0 18.955 3.68 19.125 ; - RECT 62.56 16.235 66.24 16.405 ; - RECT 0 16.235 3.68 16.405 ; - RECT 62.56 13.515 66.24 13.685 ; - RECT 0 13.515 3.68 13.685 ; - RECT 62.56 10.795 66.24 10.965 ; - RECT 0 10.795 3.68 10.965 ; - RECT 65.32 8.075 66.24 8.245 ; - RECT 0 8.075 3.68 8.245 ; - RECT 65.32 5.355 66.24 5.525 ; - RECT 0 5.355 3.68 5.525 ; - RECT 65.32 2.635 66.24 2.805 ; - RECT 0 2.635 3.68 2.805 ; - RECT 0 -0.085 66.24 0.085 ; - LAYER met2 ; - RECT 55.06 75.975 55.34 76.345 ; - RECT 25.62 75.975 25.9 76.345 ; - RECT 31.61 74.3 31.87 74.62 ; - RECT 57.37 1.54 57.63 1.86 ; - RECT 55.06 -0.185 55.34 0.185 ; - RECT 25.62 -0.185 25.9 0.185 ; - POLYGON 65.96 75.88 65.96 0.28 61.99 0.28 61.99 1.64 61.29 1.64 61.29 0.28 60.61 0.28 60.61 1.64 59.91 1.64 59.91 0.28 58.31 0.28 58.31 1.64 57.61 1.64 57.61 0.28 57.39 0.28 57.39 1.64 56.69 1.64 56.69 0.28 56.47 0.28 56.47 1.64 55.77 1.64 55.77 0.28 54.17 0.28 54.17 1.64 53.47 1.64 53.47 0.28 53.25 0.28 53.25 1.64 52.55 1.64 52.55 0.28 52.33 0.28 52.33 1.64 51.63 1.64 51.63 0.28 51.41 0.28 51.41 1.64 50.71 1.64 50.71 0.28 50.49 0.28 50.49 1.64 49.79 1.64 49.79 0.28 49.57 0.28 49.57 1.64 48.87 1.64 48.87 0.28 48.65 0.28 48.65 1.64 47.95 1.64 47.95 0.28 47.73 0.28 47.73 1.64 47.03 1.64 47.03 0.28 46.81 0.28 46.81 1.64 46.11 1.64 46.11 0.28 45.89 0.28 45.89 1.64 45.19 1.64 45.19 0.28 44.97 0.28 44.97 1.64 44.27 1.64 44.27 0.28 40.37 0.28 40.37 1.64 39.67 1.64 39.67 0.28 33.93 0.28 33.93 1.64 33.23 1.64 33.23 0.28 30.71 0.28 30.71 1.64 30.01 1.64 30.01 0.28 29.79 0.28 29.79 1.64 29.09 1.64 29.09 0.28 28.87 0.28 28.87 1.64 28.17 1.64 28.17 0.28 27.95 0.28 27.95 1.64 27.25 1.64 27.25 0.28 20.59 0.28 20.59 1.64 19.89 1.64 19.89 0.28 19.67 0.28 19.67 1.64 18.97 1.64 18.97 0.28 9.55 0.28 9.55 1.64 8.85 1.64 8.85 0.28 8.63 0.28 8.63 1.64 7.93 1.64 7.93 0.28 0.28 0.28 0.28 75.88 7.01 75.88 7.01 74.52 7.71 74.52 7.71 75.88 7.93 75.88 7.93 74.52 8.63 74.52 8.63 75.88 8.85 75.88 8.85 74.52 9.55 74.52 9.55 75.88 9.77 75.88 9.77 74.52 10.47 74.52 10.47 75.88 17.59 75.88 17.59 74.52 18.29 74.52 18.29 75.88 26.33 75.88 26.33 74.52 27.03 74.52 27.03 75.88 27.25 75.88 27.25 74.52 27.95 74.52 27.95 75.88 28.17 75.88 28.17 74.52 28.87 74.52 28.87 75.88 29.09 75.88 29.09 74.52 29.79 74.52 29.79 75.88 30.01 75.88 30.01 74.52 30.71 74.52 30.71 75.88 30.93 75.88 30.93 74.52 31.63 74.52 31.63 75.88 31.85 75.88 31.85 74.52 32.55 74.52 32.55 75.88 32.77 75.88 32.77 74.52 33.47 74.52 33.47 75.88 38.75 75.88 38.75 74.52 39.45 74.52 39.45 75.88 40.59 75.88 40.59 74.52 41.29 74.52 41.29 75.88 42.43 75.88 42.43 74.52 43.13 74.52 43.13 75.88 44.27 75.88 44.27 74.52 44.97 74.52 44.97 75.88 45.19 75.88 45.19 74.52 45.89 74.52 45.89 75.88 46.11 75.88 46.11 74.52 46.81 74.52 46.81 75.88 47.03 75.88 47.03 74.52 47.73 74.52 47.73 75.88 47.95 75.88 47.95 74.52 48.65 74.52 48.65 75.88 48.87 75.88 48.87 74.52 49.57 74.52 49.57 75.88 49.79 75.88 49.79 74.52 50.49 74.52 50.49 75.88 50.71 75.88 50.71 74.52 51.41 74.52 51.41 75.88 51.63 75.88 51.63 74.52 52.33 74.52 52.33 75.88 52.55 75.88 52.55 74.52 53.25 74.52 53.25 75.88 53.47 75.88 53.47 74.52 54.17 74.52 54.17 75.88 55.77 75.88 55.77 74.52 56.47 74.52 56.47 75.88 57.15 75.88 57.15 74.52 57.85 74.52 57.85 75.88 58.07 75.88 58.07 74.52 58.77 74.52 58.77 75.88 58.99 75.88 58.99 74.52 59.69 74.52 59.69 75.88 59.91 75.88 59.91 74.52 60.61 74.52 60.61 75.88 60.83 75.88 60.83 74.52 61.53 74.52 61.53 75.88 ; - LAYER met4 ; - POLYGON 65.84 75.76 65.84 0.4 57.59 0.4 57.59 1.76 56.49 1.76 56.49 0.4 55.9 0.4 55.9 1 54.5 1 54.5 0.4 52.99 0.4 52.99 1.76 51.89 1.76 51.89 0.4 51.15 0.4 51.15 1.76 50.05 1.76 50.05 0.4 49.31 0.4 49.31 1.76 48.21 1.76 48.21 0.4 47.47 0.4 47.47 1.76 46.37 1.76 46.37 0.4 45.63 0.4 45.63 1.76 44.53 1.76 44.53 0.4 41.18 0.4 41.18 1 39.78 1 39.78 0.4 37.35 0.4 37.35 1.76 36.25 1.76 36.25 0.4 35.51 0.4 35.51 1.76 34.41 1.76 34.41 0.4 33.67 0.4 33.67 1.76 32.57 1.76 32.57 0.4 31.83 0.4 31.83 1.76 30.73 1.76 30.73 0.4 29.99 0.4 29.99 1.76 28.89 1.76 28.89 0.4 28.15 0.4 28.15 1.76 27.05 1.76 27.05 0.4 26.46 0.4 26.46 1 25.06 1 25.06 0.4 24.47 0.4 24.47 1.76 23.37 1.76 23.37 0.4 22.63 0.4 22.63 1.76 21.53 1.76 21.53 0.4 13.43 0.4 13.43 1.76 12.33 1.76 12.33 0.4 11.74 0.4 11.74 1 10.34 1 10.34 0.4 9.75 0.4 9.75 1.76 8.65 1.76 8.65 0.4 7.91 0.4 7.91 1.76 6.81 1.76 6.81 0.4 6.07 0.4 6.07 1.76 4.97 1.76 4.97 0.4 0.4 0.4 0.4 75.76 4.97 75.76 4.97 74.4 6.07 74.4 6.07 75.76 6.81 75.76 6.81 74.4 7.91 74.4 7.91 75.76 8.65 75.76 8.65 74.4 9.75 74.4 9.75 75.76 10.34 75.76 10.34 75.16 11.74 75.16 11.74 75.76 25.06 75.76 25.06 75.16 26.46 75.16 26.46 75.76 27.05 75.76 27.05 74.4 28.15 74.4 28.15 75.76 28.89 75.76 28.89 74.4 29.99 74.4 29.99 75.76 39.78 75.76 39.78 75.16 41.18 75.16 41.18 75.76 46.37 75.76 46.37 74.4 47.47 74.4 47.47 75.76 48.21 75.76 48.21 74.4 49.31 74.4 49.31 75.76 50.05 75.76 50.05 74.4 51.15 74.4 51.15 75.76 51.89 75.76 51.89 74.4 52.99 74.4 52.99 75.76 54.5 75.76 54.5 75.16 55.9 75.16 55.9 75.76 ; - LAYER met3 ; - POLYGON 55.365 76.325 55.365 76.32 55.58 76.32 55.58 76 55.365 76 55.365 75.995 55.035 75.995 55.035 76 54.82 76 54.82 76.32 55.035 76.32 55.035 76.325 ; - POLYGON 25.925 76.325 25.925 76.32 26.14 76.32 26.14 76 25.925 76 25.925 75.995 25.595 75.995 25.595 76 25.38 76 25.38 76.32 25.595 76.32 25.595 76.325 ; - POLYGON 55.365 0.165 55.365 0.16 55.58 0.16 55.58 -0.16 55.365 -0.16 55.365 -0.165 55.035 -0.165 55.035 -0.16 54.82 -0.16 54.82 0.16 55.035 0.16 55.035 0.165 ; - POLYGON 25.925 0.165 25.925 0.16 26.14 0.16 26.14 -0.16 25.925 -0.16 25.925 -0.165 25.595 -0.165 25.595 -0.16 25.38 -0.16 25.38 0.16 25.595 0.16 25.595 0.165 ; - POLYGON 65.84 75.76 65.84 52.23 64.46 52.23 64.46 51.13 65.84 51.13 65.84 0.4 0.4 0.4 0.4 27.33 1.78 27.33 1.78 28.43 0.4 28.43 0.4 64.05 1.78 64.05 1.78 65.15 0.4 65.15 0.4 65.41 1.78 65.41 1.78 66.51 0.4 66.51 0.4 75.76 ; - LAYER met1 ; - POLYGON 65.96 75.64 65.96 73.96 65.48 73.96 65.48 72.92 65.96 72.92 65.96 71.24 65.48 71.24 65.48 70.2 65.96 70.2 65.96 68.52 65.48 68.52 65.48 67.48 65.96 67.48 65.96 65.8 65.48 65.8 65.48 64.76 65.96 64.76 65.96 63.08 65.48 63.08 65.48 62.04 65.96 62.04 65.96 60.36 65.48 60.36 65.48 59.32 65.96 59.32 65.96 57.64 65.48 57.64 65.48 56.6 65.96 56.6 65.96 54.92 65.48 54.92 65.48 53.88 65.96 53.88 65.96 52.2 65.48 52.2 65.48 51.16 65.96 51.16 65.96 49.48 65.48 49.48 65.48 48.44 65.96 48.44 65.96 46.76 65.48 46.76 65.48 45.72 65.96 45.72 65.96 44.04 65.48 44.04 65.48 43 65.96 43 65.96 41.32 65.48 41.32 65.48 40.28 65.96 40.28 65.96 38.6 65.48 38.6 65.48 37.56 65.96 37.56 65.96 35.88 65.48 35.88 65.48 34.84 65.96 34.84 65.96 33.16 65.48 33.16 65.48 32.12 65.96 32.12 65.96 30.44 65.48 30.44 65.48 29.4 65.96 29.4 65.96 27.72 65.48 27.72 65.48 26.68 65.96 26.68 65.96 25 65.48 25 65.48 23.96 65.96 23.96 65.96 22.28 65.48 22.28 65.48 21.24 65.96 21.24 65.96 19.56 65.48 19.56 65.48 18.52 65.96 18.52 65.96 16.84 65.48 16.84 65.48 15.8 65.96 15.8 65.96 14.12 65.48 14.12 65.48 13.08 65.96 13.08 65.96 11.4 65.48 11.4 65.48 10.36 65.96 10.36 65.96 8.68 65.48 8.68 65.48 7.64 65.96 7.64 65.96 5.96 65.48 5.96 65.48 4.92 65.96 4.92 65.96 3.24 65.48 3.24 65.48 2.2 65.96 2.2 65.96 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 0.76 10.36 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 ; - LAYER met5 ; - POLYGON 64.64 74.56 64.64 71.88 61.44 71.88 61.44 65.48 64.64 65.48 64.64 51.48 61.44 51.48 61.44 45.08 64.64 45.08 64.64 31.08 61.44 31.08 61.44 24.68 64.64 24.68 64.64 10.68 61.44 10.68 61.44 4.28 64.64 4.28 64.64 1.6 1.6 1.6 1.6 4.28 4.8 4.28 4.8 10.68 1.6 10.68 1.6 24.68 4.8 24.68 4.8 31.08 1.6 31.08 1.6 45.08 4.8 45.08 4.8 51.48 1.6 51.48 1.6 65.48 4.8 65.48 4.8 71.88 1.6 71.88 1.6 74.56 ; - LAYER li1 ; - RECT 0.17 0.17 66.07 75.99 ; - LAYER mcon ; - RECT 65.925 76.075 66.095 76.245 ; - RECT 65.465 76.075 65.635 76.245 ; - RECT 65.005 76.075 65.175 76.245 ; - RECT 64.545 76.075 64.715 76.245 ; - RECT 64.085 76.075 64.255 76.245 ; - RECT 63.625 76.075 63.795 76.245 ; - RECT 63.165 76.075 63.335 76.245 ; - RECT 62.705 76.075 62.875 76.245 ; - RECT 62.245 76.075 62.415 76.245 ; - RECT 61.785 76.075 61.955 76.245 ; - RECT 61.325 76.075 61.495 76.245 ; - RECT 60.865 76.075 61.035 76.245 ; - RECT 60.405 76.075 60.575 76.245 ; - RECT 59.945 76.075 60.115 76.245 ; - RECT 59.485 76.075 59.655 76.245 ; - RECT 59.025 76.075 59.195 76.245 ; - RECT 58.565 76.075 58.735 76.245 ; - RECT 58.105 76.075 58.275 76.245 ; - RECT 57.645 76.075 57.815 76.245 ; - RECT 57.185 76.075 57.355 76.245 ; - RECT 56.725 76.075 56.895 76.245 ; - RECT 56.265 76.075 56.435 76.245 ; - RECT 55.805 76.075 55.975 76.245 ; - RECT 55.345 76.075 55.515 76.245 ; - RECT 54.885 76.075 55.055 76.245 ; - RECT 54.425 76.075 54.595 76.245 ; - RECT 53.965 76.075 54.135 76.245 ; - RECT 53.505 76.075 53.675 76.245 ; - RECT 53.045 76.075 53.215 76.245 ; - RECT 52.585 76.075 52.755 76.245 ; - RECT 52.125 76.075 52.295 76.245 ; - RECT 51.665 76.075 51.835 76.245 ; - RECT 51.205 76.075 51.375 76.245 ; - RECT 50.745 76.075 50.915 76.245 ; - RECT 50.285 76.075 50.455 76.245 ; - RECT 49.825 76.075 49.995 76.245 ; - RECT 49.365 76.075 49.535 76.245 ; - RECT 48.905 76.075 49.075 76.245 ; - RECT 48.445 76.075 48.615 76.245 ; - RECT 47.985 76.075 48.155 76.245 ; - RECT 47.525 76.075 47.695 76.245 ; - RECT 47.065 76.075 47.235 76.245 ; - RECT 46.605 76.075 46.775 76.245 ; - RECT 46.145 76.075 46.315 76.245 ; - RECT 45.685 76.075 45.855 76.245 ; - RECT 45.225 76.075 45.395 76.245 ; - RECT 44.765 76.075 44.935 76.245 ; - RECT 44.305 76.075 44.475 76.245 ; - RECT 43.845 76.075 44.015 76.245 ; - RECT 43.385 76.075 43.555 76.245 ; - RECT 42.925 76.075 43.095 76.245 ; - RECT 42.465 76.075 42.635 76.245 ; - RECT 42.005 76.075 42.175 76.245 ; - RECT 41.545 76.075 41.715 76.245 ; - RECT 41.085 76.075 41.255 76.245 ; - RECT 40.625 76.075 40.795 76.245 ; - RECT 40.165 76.075 40.335 76.245 ; - RECT 39.705 76.075 39.875 76.245 ; - RECT 39.245 76.075 39.415 76.245 ; - RECT 38.785 76.075 38.955 76.245 ; - RECT 38.325 76.075 38.495 76.245 ; - RECT 37.865 76.075 38.035 76.245 ; - RECT 37.405 76.075 37.575 76.245 ; - RECT 36.945 76.075 37.115 76.245 ; - RECT 36.485 76.075 36.655 76.245 ; - RECT 36.025 76.075 36.195 76.245 ; - RECT 35.565 76.075 35.735 76.245 ; - RECT 35.105 76.075 35.275 76.245 ; - RECT 34.645 76.075 34.815 76.245 ; - RECT 34.185 76.075 34.355 76.245 ; - RECT 33.725 76.075 33.895 76.245 ; - RECT 33.265 76.075 33.435 76.245 ; - RECT 32.805 76.075 32.975 76.245 ; - RECT 32.345 76.075 32.515 76.245 ; - RECT 31.885 76.075 32.055 76.245 ; - RECT 31.425 76.075 31.595 76.245 ; - RECT 30.965 76.075 31.135 76.245 ; - RECT 30.505 76.075 30.675 76.245 ; - RECT 30.045 76.075 30.215 76.245 ; - RECT 29.585 76.075 29.755 76.245 ; - RECT 29.125 76.075 29.295 76.245 ; - RECT 28.665 76.075 28.835 76.245 ; - RECT 28.205 76.075 28.375 76.245 ; - RECT 27.745 76.075 27.915 76.245 ; - RECT 27.285 76.075 27.455 76.245 ; - RECT 26.825 76.075 26.995 76.245 ; - RECT 26.365 76.075 26.535 76.245 ; - RECT 25.905 76.075 26.075 76.245 ; - RECT 25.445 76.075 25.615 76.245 ; - RECT 24.985 76.075 25.155 76.245 ; - RECT 24.525 76.075 24.695 76.245 ; - RECT 24.065 76.075 24.235 76.245 ; - RECT 23.605 76.075 23.775 76.245 ; - RECT 23.145 76.075 23.315 76.245 ; - RECT 22.685 76.075 22.855 76.245 ; - RECT 22.225 76.075 22.395 76.245 ; - RECT 21.765 76.075 21.935 76.245 ; - RECT 21.305 76.075 21.475 76.245 ; - RECT 20.845 76.075 21.015 76.245 ; - RECT 20.385 76.075 20.555 76.245 ; - RECT 19.925 76.075 20.095 76.245 ; - RECT 19.465 76.075 19.635 76.245 ; - RECT 19.005 76.075 19.175 76.245 ; - RECT 18.545 76.075 18.715 76.245 ; - RECT 18.085 76.075 18.255 76.245 ; - RECT 17.625 76.075 17.795 76.245 ; - RECT 17.165 76.075 17.335 76.245 ; - RECT 16.705 76.075 16.875 76.245 ; - RECT 16.245 76.075 16.415 76.245 ; - RECT 15.785 76.075 15.955 76.245 ; - RECT 15.325 76.075 15.495 76.245 ; - RECT 14.865 76.075 15.035 76.245 ; - RECT 14.405 76.075 14.575 76.245 ; - RECT 13.945 76.075 14.115 76.245 ; - RECT 13.485 76.075 13.655 76.245 ; - RECT 13.025 76.075 13.195 76.245 ; - RECT 12.565 76.075 12.735 76.245 ; - RECT 12.105 76.075 12.275 76.245 ; - RECT 11.645 76.075 11.815 76.245 ; - RECT 11.185 76.075 11.355 76.245 ; - RECT 10.725 76.075 10.895 76.245 ; - RECT 10.265 76.075 10.435 76.245 ; - RECT 9.805 76.075 9.975 76.245 ; - RECT 9.345 76.075 9.515 76.245 ; - RECT 8.885 76.075 9.055 76.245 ; - RECT 8.425 76.075 8.595 76.245 ; - RECT 7.965 76.075 8.135 76.245 ; - RECT 7.505 76.075 7.675 76.245 ; - RECT 7.045 76.075 7.215 76.245 ; - RECT 6.585 76.075 6.755 76.245 ; - RECT 6.125 76.075 6.295 76.245 ; - RECT 5.665 76.075 5.835 76.245 ; - RECT 5.205 76.075 5.375 76.245 ; - RECT 4.745 76.075 4.915 76.245 ; - RECT 4.285 76.075 4.455 76.245 ; - RECT 3.825 76.075 3.995 76.245 ; - RECT 3.365 76.075 3.535 76.245 ; - RECT 2.905 76.075 3.075 76.245 ; - RECT 2.445 76.075 2.615 76.245 ; - RECT 1.985 76.075 2.155 76.245 ; - RECT 1.525 76.075 1.695 76.245 ; - RECT 1.065 76.075 1.235 76.245 ; - RECT 0.605 76.075 0.775 76.245 ; - RECT 0.145 76.075 0.315 76.245 ; - RECT 65.925 73.355 66.095 73.525 ; - RECT 65.465 73.355 65.635 73.525 ; - RECT 0.605 73.355 0.775 73.525 ; - RECT 0.145 73.355 0.315 73.525 ; - RECT 65.925 70.635 66.095 70.805 ; - RECT 65.465 70.635 65.635 70.805 ; - RECT 0.605 70.635 0.775 70.805 ; - RECT 0.145 70.635 0.315 70.805 ; - RECT 65.925 67.915 66.095 68.085 ; - RECT 65.465 67.915 65.635 68.085 ; - RECT 0.605 67.915 0.775 68.085 ; - RECT 0.145 67.915 0.315 68.085 ; - RECT 65.925 65.195 66.095 65.365 ; - RECT 65.465 65.195 65.635 65.365 ; - RECT 0.605 65.195 0.775 65.365 ; - RECT 0.145 65.195 0.315 65.365 ; - RECT 65.925 62.475 66.095 62.645 ; - RECT 65.465 62.475 65.635 62.645 ; - RECT 0.605 62.475 0.775 62.645 ; - RECT 0.145 62.475 0.315 62.645 ; - RECT 65.925 59.755 66.095 59.925 ; - RECT 65.465 59.755 65.635 59.925 ; - RECT 0.605 59.755 0.775 59.925 ; - RECT 0.145 59.755 0.315 59.925 ; - RECT 65.925 57.035 66.095 57.205 ; - RECT 65.465 57.035 65.635 57.205 ; - RECT 0.605 57.035 0.775 57.205 ; - RECT 0.145 57.035 0.315 57.205 ; - RECT 65.925 54.315 66.095 54.485 ; - RECT 65.465 54.315 65.635 54.485 ; - RECT 0.605 54.315 0.775 54.485 ; - RECT 0.145 54.315 0.315 54.485 ; - RECT 65.925 51.595 66.095 51.765 ; - RECT 65.465 51.595 65.635 51.765 ; - RECT 0.605 51.595 0.775 51.765 ; - RECT 0.145 51.595 0.315 51.765 ; - RECT 65.925 48.875 66.095 49.045 ; - RECT 65.465 48.875 65.635 49.045 ; - RECT 0.605 48.875 0.775 49.045 ; - RECT 0.145 48.875 0.315 49.045 ; - RECT 65.925 46.155 66.095 46.325 ; - RECT 65.465 46.155 65.635 46.325 ; - RECT 0.605 46.155 0.775 46.325 ; - RECT 0.145 46.155 0.315 46.325 ; - RECT 65.925 43.435 66.095 43.605 ; - RECT 65.465 43.435 65.635 43.605 ; - RECT 0.605 43.435 0.775 43.605 ; - RECT 0.145 43.435 0.315 43.605 ; - RECT 65.925 40.715 66.095 40.885 ; - RECT 65.465 40.715 65.635 40.885 ; - RECT 0.605 40.715 0.775 40.885 ; - RECT 0.145 40.715 0.315 40.885 ; - RECT 65.925 37.995 66.095 38.165 ; - RECT 65.465 37.995 65.635 38.165 ; - RECT 0.605 37.995 0.775 38.165 ; - RECT 0.145 37.995 0.315 38.165 ; - RECT 65.925 35.275 66.095 35.445 ; - RECT 65.465 35.275 65.635 35.445 ; - RECT 0.605 35.275 0.775 35.445 ; - RECT 0.145 35.275 0.315 35.445 ; - RECT 65.925 32.555 66.095 32.725 ; - RECT 65.465 32.555 65.635 32.725 ; - RECT 0.605 32.555 0.775 32.725 ; - RECT 0.145 32.555 0.315 32.725 ; - RECT 65.925 29.835 66.095 30.005 ; - RECT 65.465 29.835 65.635 30.005 ; - RECT 0.605 29.835 0.775 30.005 ; - RECT 0.145 29.835 0.315 30.005 ; - RECT 65.925 27.115 66.095 27.285 ; - RECT 65.465 27.115 65.635 27.285 ; - RECT 0.605 27.115 0.775 27.285 ; - RECT 0.145 27.115 0.315 27.285 ; - RECT 65.925 24.395 66.095 24.565 ; - RECT 65.465 24.395 65.635 24.565 ; - RECT 0.605 24.395 0.775 24.565 ; - RECT 0.145 24.395 0.315 24.565 ; - RECT 65.925 21.675 66.095 21.845 ; - RECT 65.465 21.675 65.635 21.845 ; - RECT 0.605 21.675 0.775 21.845 ; - RECT 0.145 21.675 0.315 21.845 ; - RECT 65.925 18.955 66.095 19.125 ; - RECT 65.465 18.955 65.635 19.125 ; - RECT 0.605 18.955 0.775 19.125 ; - RECT 0.145 18.955 0.315 19.125 ; - RECT 65.925 16.235 66.095 16.405 ; - RECT 65.465 16.235 65.635 16.405 ; - RECT 0.605 16.235 0.775 16.405 ; - RECT 0.145 16.235 0.315 16.405 ; - RECT 65.925 13.515 66.095 13.685 ; - RECT 65.465 13.515 65.635 13.685 ; - RECT 0.605 13.515 0.775 13.685 ; - RECT 0.145 13.515 0.315 13.685 ; - RECT 65.925 10.795 66.095 10.965 ; - RECT 65.465 10.795 65.635 10.965 ; - RECT 0.605 10.795 0.775 10.965 ; - RECT 0.145 10.795 0.315 10.965 ; - RECT 65.925 8.075 66.095 8.245 ; - RECT 65.465 8.075 65.635 8.245 ; - RECT 0.605 8.075 0.775 8.245 ; - RECT 0.145 8.075 0.315 8.245 ; - RECT 65.925 5.355 66.095 5.525 ; - RECT 65.465 5.355 65.635 5.525 ; - RECT 0.605 5.355 0.775 5.525 ; - RECT 0.145 5.355 0.315 5.525 ; - RECT 65.925 2.635 66.095 2.805 ; - RECT 65.465 2.635 65.635 2.805 ; - RECT 0.605 2.635 0.775 2.805 ; - RECT 0.145 2.635 0.315 2.805 ; - RECT 65.925 -0.085 66.095 0.085 ; - RECT 65.465 -0.085 65.635 0.085 ; - RECT 65.005 -0.085 65.175 0.085 ; - RECT 64.545 -0.085 64.715 0.085 ; - RECT 64.085 -0.085 64.255 0.085 ; - RECT 63.625 -0.085 63.795 0.085 ; - RECT 63.165 -0.085 63.335 0.085 ; - RECT 62.705 -0.085 62.875 0.085 ; - RECT 62.245 -0.085 62.415 0.085 ; - RECT 61.785 -0.085 61.955 0.085 ; - RECT 61.325 -0.085 61.495 0.085 ; - RECT 60.865 -0.085 61.035 0.085 ; - RECT 60.405 -0.085 60.575 0.085 ; - RECT 59.945 -0.085 60.115 0.085 ; - RECT 59.485 -0.085 59.655 0.085 ; - RECT 59.025 -0.085 59.195 0.085 ; - RECT 58.565 -0.085 58.735 0.085 ; - RECT 58.105 -0.085 58.275 0.085 ; - RECT 57.645 -0.085 57.815 0.085 ; - RECT 57.185 -0.085 57.355 0.085 ; - RECT 56.725 -0.085 56.895 0.085 ; - RECT 56.265 -0.085 56.435 0.085 ; - RECT 55.805 -0.085 55.975 0.085 ; - RECT 55.345 -0.085 55.515 0.085 ; - RECT 54.885 -0.085 55.055 0.085 ; - RECT 54.425 -0.085 54.595 0.085 ; - RECT 53.965 -0.085 54.135 0.085 ; - RECT 53.505 -0.085 53.675 0.085 ; - RECT 53.045 -0.085 53.215 0.085 ; - RECT 52.585 -0.085 52.755 0.085 ; - RECT 52.125 -0.085 52.295 0.085 ; - RECT 51.665 -0.085 51.835 0.085 ; - RECT 51.205 -0.085 51.375 0.085 ; - RECT 50.745 -0.085 50.915 0.085 ; - RECT 50.285 -0.085 50.455 0.085 ; - RECT 49.825 -0.085 49.995 0.085 ; - RECT 49.365 -0.085 49.535 0.085 ; - RECT 48.905 -0.085 49.075 0.085 ; - RECT 48.445 -0.085 48.615 0.085 ; - RECT 47.985 -0.085 48.155 0.085 ; - RECT 47.525 -0.085 47.695 0.085 ; - RECT 47.065 -0.085 47.235 0.085 ; - RECT 46.605 -0.085 46.775 0.085 ; - RECT 46.145 -0.085 46.315 0.085 ; - RECT 45.685 -0.085 45.855 0.085 ; - RECT 45.225 -0.085 45.395 0.085 ; - RECT 44.765 -0.085 44.935 0.085 ; - RECT 44.305 -0.085 44.475 0.085 ; - RECT 43.845 -0.085 44.015 0.085 ; - RECT 43.385 -0.085 43.555 0.085 ; - RECT 42.925 -0.085 43.095 0.085 ; - RECT 42.465 -0.085 42.635 0.085 ; - RECT 42.005 -0.085 42.175 0.085 ; - RECT 41.545 -0.085 41.715 0.085 ; - RECT 41.085 -0.085 41.255 0.085 ; - RECT 40.625 -0.085 40.795 0.085 ; - RECT 40.165 -0.085 40.335 0.085 ; - RECT 39.705 -0.085 39.875 0.085 ; - RECT 39.245 -0.085 39.415 0.085 ; - RECT 38.785 -0.085 38.955 0.085 ; - RECT 38.325 -0.085 38.495 0.085 ; - RECT 37.865 -0.085 38.035 0.085 ; - RECT 37.405 -0.085 37.575 0.085 ; - RECT 36.945 -0.085 37.115 0.085 ; - RECT 36.485 -0.085 36.655 0.085 ; - RECT 36.025 -0.085 36.195 0.085 ; - RECT 35.565 -0.085 35.735 0.085 ; - RECT 35.105 -0.085 35.275 0.085 ; - RECT 34.645 -0.085 34.815 0.085 ; - RECT 34.185 -0.085 34.355 0.085 ; - RECT 33.725 -0.085 33.895 0.085 ; - RECT 33.265 -0.085 33.435 0.085 ; - RECT 32.805 -0.085 32.975 0.085 ; - RECT 32.345 -0.085 32.515 0.085 ; - RECT 31.885 -0.085 32.055 0.085 ; - RECT 31.425 -0.085 31.595 0.085 ; - RECT 30.965 -0.085 31.135 0.085 ; - RECT 30.505 -0.085 30.675 0.085 ; - RECT 30.045 -0.085 30.215 0.085 ; - RECT 29.585 -0.085 29.755 0.085 ; - RECT 29.125 -0.085 29.295 0.085 ; - RECT 28.665 -0.085 28.835 0.085 ; - RECT 28.205 -0.085 28.375 0.085 ; - RECT 27.745 -0.085 27.915 0.085 ; - RECT 27.285 -0.085 27.455 0.085 ; - RECT 26.825 -0.085 26.995 0.085 ; - RECT 26.365 -0.085 26.535 0.085 ; - RECT 25.905 -0.085 26.075 0.085 ; - RECT 25.445 -0.085 25.615 0.085 ; - RECT 24.985 -0.085 25.155 0.085 ; - RECT 24.525 -0.085 24.695 0.085 ; - RECT 24.065 -0.085 24.235 0.085 ; - RECT 23.605 -0.085 23.775 0.085 ; - RECT 23.145 -0.085 23.315 0.085 ; - RECT 22.685 -0.085 22.855 0.085 ; - RECT 22.225 -0.085 22.395 0.085 ; - RECT 21.765 -0.085 21.935 0.085 ; - RECT 21.305 -0.085 21.475 0.085 ; - RECT 20.845 -0.085 21.015 0.085 ; - RECT 20.385 -0.085 20.555 0.085 ; - RECT 19.925 -0.085 20.095 0.085 ; - RECT 19.465 -0.085 19.635 0.085 ; - RECT 19.005 -0.085 19.175 0.085 ; - RECT 18.545 -0.085 18.715 0.085 ; - RECT 18.085 -0.085 18.255 0.085 ; - RECT 17.625 -0.085 17.795 0.085 ; - RECT 17.165 -0.085 17.335 0.085 ; - RECT 16.705 -0.085 16.875 0.085 ; - RECT 16.245 -0.085 16.415 0.085 ; - RECT 15.785 -0.085 15.955 0.085 ; - RECT 15.325 -0.085 15.495 0.085 ; - RECT 14.865 -0.085 15.035 0.085 ; - RECT 14.405 -0.085 14.575 0.085 ; - RECT 13.945 -0.085 14.115 0.085 ; - RECT 13.485 -0.085 13.655 0.085 ; - RECT 13.025 -0.085 13.195 0.085 ; - RECT 12.565 -0.085 12.735 0.085 ; - RECT 12.105 -0.085 12.275 0.085 ; - RECT 11.645 -0.085 11.815 0.085 ; - RECT 11.185 -0.085 11.355 0.085 ; - RECT 10.725 -0.085 10.895 0.085 ; - RECT 10.265 -0.085 10.435 0.085 ; - RECT 9.805 -0.085 9.975 0.085 ; - RECT 9.345 -0.085 9.515 0.085 ; - RECT 8.885 -0.085 9.055 0.085 ; - RECT 8.425 -0.085 8.595 0.085 ; - RECT 7.965 -0.085 8.135 0.085 ; - RECT 7.505 -0.085 7.675 0.085 ; - RECT 7.045 -0.085 7.215 0.085 ; - RECT 6.585 -0.085 6.755 0.085 ; - RECT 6.125 -0.085 6.295 0.085 ; - RECT 5.665 -0.085 5.835 0.085 ; - RECT 5.205 -0.085 5.375 0.085 ; - RECT 4.745 -0.085 4.915 0.085 ; - RECT 4.285 -0.085 4.455 0.085 ; - RECT 3.825 -0.085 3.995 0.085 ; - RECT 3.365 -0.085 3.535 0.085 ; - RECT 2.905 -0.085 3.075 0.085 ; - RECT 2.445 -0.085 2.615 0.085 ; - RECT 1.985 -0.085 2.155 0.085 ; - RECT 1.525 -0.085 1.695 0.085 ; - RECT 1.065 -0.085 1.235 0.085 ; - RECT 0.605 -0.085 0.775 0.085 ; - RECT 0.145 -0.085 0.315 0.085 ; - LAYER via ; - RECT 55.125 76.085 55.275 76.235 ; - RECT 25.685 76.085 25.835 76.235 ; - RECT 44.545 74.385 44.695 74.535 ; - RECT 30.285 74.385 30.435 74.535 ; - RECT 60.185 1.625 60.335 1.775 ; - RECT 9.125 1.625 9.275 1.775 ; - RECT 55.125 -0.075 55.275 0.075 ; - RECT 25.685 -0.075 25.835 0.075 ; - LAYER via2 ; - RECT 55.1 76.06 55.3 76.26 ; - RECT 25.66 76.06 25.86 76.26 ; - RECT 64.3 51.58 64.5 51.78 ; - RECT 55.1 -0.1 55.3 0.1 ; - RECT 25.66 -0.1 25.86 0.1 ; - LAYER via3 ; - RECT 55.1 76.06 55.3 76.26 ; - RECT 25.66 76.06 25.86 76.26 ; - RECT 55.1 -0.1 55.3 0.1 ; - RECT 25.66 -0.1 25.86 0.1 ; - LAYER OVERLAP ; - POLYGON 0 0 0 76.16 66.24 76.16 66.24 0 ; - END -END cby_0__1_ - -END LIBRARY diff --git a/FPGA22_HIER_SKY_PNR/modules/lef/cby_1__1__icv_in_design.lef b/FPGA22_HIER_SKY_PNR/modules/lef/cby_1__1__icv_in_design.lef deleted file mode 100644 index 034db54..0000000 --- a/FPGA22_HIER_SKY_PNR/modules/lef/cby_1__1__icv_in_design.lef +++ /dev/null @@ -1,1773 +0,0 @@ -VERSION 5.7 ; -BUSBITCHARS "[]" ; - -UNITS - DATABASE MICRONS 1000 ; -END UNITS - -MANUFACTURINGGRID 0.005 ; - -LAYER li1 - TYPE ROUTING ; - DIRECTION VERTICAL ; - PITCH 0.46 ; - WIDTH 0.17 ; -END li1 - -LAYER mcon - TYPE CUT ; -END mcon - -LAYER met1 - TYPE ROUTING ; - DIRECTION HORIZONTAL ; - PITCH 0.34 ; - WIDTH 0.14 ; -END met1 - -LAYER via - TYPE CUT ; -END via - -LAYER met2 - TYPE ROUTING ; - DIRECTION VERTICAL ; - PITCH 0.46 ; - WIDTH 0.14 ; -END met2 - -LAYER via2 - TYPE CUT ; -END via2 - -LAYER met3 - TYPE ROUTING ; - DIRECTION HORIZONTAL ; - PITCH 0.68 ; - WIDTH 0.3 ; -END met3 - -LAYER via3 - TYPE CUT ; -END via3 - -LAYER met4 - TYPE ROUTING ; - DIRECTION VERTICAL ; - PITCH 0.92 ; - WIDTH 0.3 ; -END met4 - -LAYER via4 - TYPE CUT ; -END via4 - -LAYER met5 - TYPE ROUTING ; - DIRECTION HORIZONTAL ; - PITCH 3.4 ; - WIDTH 1.6 ; -END met5 - -LAYER nwell - TYPE MASTERSLICE ; -END nwell - -LAYER pwell - TYPE MASTERSLICE ; -END pwell - -LAYER OVERLAP - TYPE OVERLAP ; -END OVERLAP - -VIA L1M1_PR - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.145 -0.115 0.145 0.115 ; -END L1M1_PR - -VIA L1M1_PR_R - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.115 -0.145 0.115 0.145 ; -END L1M1_PR_R - -VIA L1M1_PR_M - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.115 -0.145 0.115 0.145 ; -END L1M1_PR_M - -VIA L1M1_PR_MR - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.145 -0.115 0.145 0.115 ; -END L1M1_PR_MR - -VIA L1M1_PR_C - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.145 -0.145 0.145 0.145 ; -END L1M1_PR_C - -VIA M1M2_PR - LAYER met1 ; - RECT -0.16 -0.13 0.16 0.13 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.13 -0.16 0.13 0.16 ; -END M1M2_PR - -VIA M1M2_PR_Enc - LAYER met1 ; - RECT -0.16 -0.13 0.16 0.13 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.16 -0.13 0.16 0.13 ; -END M1M2_PR_Enc - -VIA M1M2_PR_R - LAYER met1 ; - RECT -0.13 -0.16 0.13 0.16 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.16 -0.13 0.16 0.13 ; -END M1M2_PR_R - -VIA M1M2_PR_R_Enc - LAYER met1 ; - RECT -0.13 -0.16 0.13 0.16 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.13 -0.16 0.13 0.16 ; -END M1M2_PR_R_Enc - -VIA M1M2_PR_M - LAYER met1 ; - RECT -0.16 -0.13 0.16 0.13 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.16 -0.13 0.16 0.13 ; -END M1M2_PR_M - -VIA M1M2_PR_M_Enc - LAYER met1 ; - RECT -0.16 -0.13 0.16 0.13 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.13 -0.16 0.13 0.16 ; -END M1M2_PR_M_Enc - -VIA M1M2_PR_MR - LAYER met1 ; - RECT -0.13 -0.16 0.13 0.16 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.13 -0.16 0.13 0.16 ; -END M1M2_PR_MR - -VIA M1M2_PR_MR_Enc - LAYER met1 ; - RECT -0.13 -0.16 0.13 0.16 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.16 -0.13 0.16 0.13 ; -END M1M2_PR_MR_Enc - -VIA M1M2_PR_C - LAYER met1 ; - RECT -0.16 -0.16 0.16 0.16 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.16 -0.16 0.16 0.16 ; -END M1M2_PR_C - -VIA M2M3_PR - LAYER met2 ; - RECT -0.14 -0.185 0.14 0.185 ; - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met3 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M2M3_PR - -VIA M2M3_PR_R - LAYER met2 ; - RECT -0.185 -0.14 0.185 0.14 ; - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met3 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M2M3_PR_R - -VIA M2M3_PR_M - LAYER met2 ; - RECT -0.14 -0.185 0.14 0.185 ; - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met3 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M2M3_PR_M - -VIA M2M3_PR_MR - LAYER met2 ; - RECT -0.185 -0.14 0.185 0.14 ; - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met3 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M2M3_PR_MR - -VIA M2M3_PR_C - LAYER met2 ; - RECT -0.185 -0.185 0.185 0.185 ; - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met3 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M2M3_PR_C - -VIA M3M4_PR - LAYER met3 ; - RECT -0.19 -0.16 0.19 0.16 ; - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR - -VIA M3M4_PR_R - LAYER met3 ; - RECT -0.16 -0.19 0.16 0.19 ; - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR_R - -VIA M3M4_PR_M - LAYER met3 ; - RECT -0.19 -0.16 0.19 0.16 ; - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR_M - -VIA M3M4_PR_MR - LAYER met3 ; - RECT -0.16 -0.19 0.16 0.19 ; - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR_MR - -VIA M3M4_PR_C - LAYER met3 ; - RECT -0.19 -0.19 0.19 0.19 ; - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR_C - -VIA M4M5_PR - LAYER met4 ; - RECT -0.59 -0.59 0.59 0.59 ; - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - LAYER met5 ; - RECT -0.71 -0.71 0.71 0.71 ; -END M4M5_PR - -VIA M4M5_PR_R - LAYER met4 ; - RECT -0.59 -0.59 0.59 0.59 ; - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - LAYER met5 ; - RECT -0.71 -0.71 0.71 0.71 ; -END M4M5_PR_R - -VIA M4M5_PR_M - LAYER met4 ; - RECT -0.59 -0.59 0.59 0.59 ; - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - LAYER met5 ; - RECT -0.71 -0.71 0.71 0.71 ; -END M4M5_PR_M - -VIA M4M5_PR_MR - LAYER met4 ; - RECT -0.59 -0.59 0.59 0.59 ; - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - LAYER met5 ; - RECT -0.71 -0.71 0.71 0.71 ; -END M4M5_PR_MR - -VIA M4M5_PR_C - LAYER met4 ; - RECT -0.59 -0.59 0.59 0.59 ; - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - LAYER met5 ; - RECT -0.71 -0.71 0.71 0.71 ; -END M4M5_PR_C - -SITE unit - CLASS CORE ; - SYMMETRY Y ; - SIZE 0.46 BY 2.72 ; -END unit - -SITE unithddbl - CLASS CORE ; - SIZE 0.46 BY 5.44 ; -END unithddbl - -MACRO cby_1__1_ - CLASS BLOCK ; - ORIGIN 0 0 ; - SIZE 66.24 BY 76.16 ; - SYMMETRY X Y ; - PIN prog_clk[0] - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER met2 ; - RECT 29.37 0 29.51 1.36 ; - END - END prog_clk[0] - PIN chany_bottom_in[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 54.21 0 54.35 1.36 ; - END - END chany_bottom_in[0] - PIN chany_bottom_in[1] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 36.73 0 36.87 1.36 ; - END - END chany_bottom_in[1] - PIN chany_bottom_in[2] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 21.55 0 21.69 1.36 ; - END - END chany_bottom_in[2] - PIN chany_bottom_in[3] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 49.61 0 49.75 1.36 ; - END - END chany_bottom_in[3] - PIN chany_bottom_in[4] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 26.61 0 26.75 1.36 ; - END - END chany_bottom_in[4] - PIN chany_bottom_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 50.53 0 50.67 1.36 ; - END - END chany_bottom_in[5] - PIN chany_bottom_in[6] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 31.67 0 31.81 1.36 ; - END - END chany_bottom_in[6] - PIN chany_bottom_in[7] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 44.09 0 44.23 1.36 ; - END - END chany_bottom_in[7] - PIN chany_bottom_in[8] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 22.47 0 22.61 1.36 ; - END - END chany_bottom_in[8] - PIN chany_bottom_in[9] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 45.47 0 45.61 1.36 ; - END - END chany_bottom_in[9] - PIN chany_bottom_in[10] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 35.81 0 35.95 1.36 ; - END - END chany_bottom_in[10] - PIN chany_bottom_in[11] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 39.03 0 39.17 1.36 ; - END - END chany_bottom_in[11] - PIN chany_bottom_in[12] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 58.35 0 58.49 1.36 ; - END - END chany_bottom_in[12] - PIN chany_bottom_in[13] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 42.25 0 42.39 1.36 ; - END - END chany_bottom_in[13] - PIN chany_bottom_in[14] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 8.67 0 8.81 1.36 ; - END - END chany_bottom_in[14] - PIN chany_bottom_in[15] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 46.85 0 46.99 1.36 ; - END - END chany_bottom_in[15] - PIN chany_bottom_in[16] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 24.77 0 24.91 1.36 ; - END - END chany_bottom_in[16] - PIN chany_bottom_in[17] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 48.69 0 48.83 1.36 ; - END - END chany_bottom_in[17] - PIN chany_bottom_in[18] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 27.53 0 27.67 1.36 ; - END - END chany_bottom_in[18] - PIN chany_bottom_in[19] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 56.51 0 56.65 1.36 ; - END - END chany_bottom_in[19] - PIN chany_top_in[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 38.11 74.8 38.25 76.16 ; - END - END chany_top_in[0] - PIN chany_top_in[1] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 19.25 74.8 19.39 76.16 ; - END - END chany_top_in[1] - PIN chany_top_in[2] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 29.37 74.8 29.51 76.16 ; - END - END chany_top_in[2] - PIN chany_top_in[3] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 40.41 74.8 40.55 76.16 ; - END - END chany_top_in[3] - PIN chany_top_in[4] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 32.59 74.8 32.73 76.16 ; - END - END chany_top_in[4] - PIN chany_top_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 49.61 74.8 49.75 76.16 ; - END - END chany_top_in[5] - PIN chany_top_in[6] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 24.77 74.8 24.91 76.16 ; - END - END chany_top_in[6] - PIN chany_top_in[7] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 47.77 74.8 47.91 76.16 ; - END - END chany_top_in[7] - PIN chany_top_in[8] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 56.97 74.8 57.11 76.16 ; - END - END chany_top_in[8] - PIN chany_top_in[9] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 48.69 74.8 48.83 76.16 ; - END - END chany_top_in[9] - PIN chany_top_in[10] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 30.29 74.8 30.43 76.16 ; - END - END chany_top_in[10] - PIN chany_top_in[11] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 45.93 74.8 46.07 76.16 ; - END - END chany_top_in[11] - PIN chany_top_in[12] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 54.21 74.8 54.35 76.16 ; - END - END chany_top_in[12] - PIN chany_top_in[13] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 50.53 74.8 50.67 76.16 ; - END - END chany_top_in[13] - PIN chany_top_in[14] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 8.67 74.8 8.81 76.16 ; - END - END chany_top_in[14] - PIN chany_top_in[15] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 62.49 74.8 62.63 76.16 ; - END - END chany_top_in[15] - PIN chany_top_in[16] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 56.05 74.8 56.19 76.16 ; - END - END chany_top_in[16] - PIN chany_top_in[17] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 61.57 74.8 61.71 76.16 ; - END - END chany_top_in[17] - PIN chany_top_in[18] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 28.45 74.8 28.59 76.16 ; - END - END chany_top_in[18] - PIN chany_top_in[19] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 63.41 74.8 63.55 76.16 ; - END - END chany_top_in[19] - PIN ccff_head[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 65.13 1.38 65.43 ; - END - END ccff_head[0] - PIN chany_bottom_out[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 38.11 0 38.25 1.36 ; - END - END chany_bottom_out[0] - PIN chany_bottom_out[1] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 33.51 0 33.65 1.36 ; - END - END chany_bottom_out[1] - PIN chany_bottom_out[2] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 42.17 0 42.47 1.36 ; - END - END chany_bottom_out[2] - PIN chany_bottom_out[3] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 52.37 0 52.51 1.36 ; - END - END chany_bottom_out[3] - PIN chany_bottom_out[4] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 32.59 0 32.73 1.36 ; - END - END chany_bottom_out[4] - PIN chany_bottom_out[5] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 43.17 0 43.31 1.36 ; - END - END chany_bottom_out[5] - PIN chany_bottom_out[6] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 20.63 0 20.77 1.36 ; - END - END chany_bottom_out[6] - PIN chany_bottom_out[7] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 47.77 0 47.91 1.36 ; - END - END chany_bottom_out[7] - PIN chany_bottom_out[8] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 30.75 0 30.89 1.36 ; - END - END chany_bottom_out[8] - PIN chany_bottom_out[9] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 51.45 0 51.59 1.36 ; - END - END chany_bottom_out[9] - PIN chany_bottom_out[10] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 40.41 0 40.55 1.36 ; - END - END chany_bottom_out[10] - PIN chany_bottom_out[11] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 17.87 0 18.01 1.36 ; - END - END chany_bottom_out[11] - PIN chany_bottom_out[12] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 37.57 0 37.87 1.36 ; - END - END chany_bottom_out[12] - PIN chany_bottom_out[13] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 23.85 0 23.99 1.36 ; - END - END chany_bottom_out[13] - PIN chany_bottom_out[14] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 57.43 0 57.57 1.36 ; - END - END chany_bottom_out[14] - PIN chany_bottom_out[15] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 19.71 0 19.85 1.36 ; - END - END chany_bottom_out[15] - PIN chany_bottom_out[16] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 53.29 0 53.43 1.36 ; - END - END chany_bottom_out[16] - PIN chany_bottom_out[17] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 41.33 0 41.47 1.36 ; - END - END chany_bottom_out[17] - PIN chany_bottom_out[18] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 18.79 0 18.93 1.36 ; - END - END chany_bottom_out[18] - PIN chany_bottom_out[19] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 34.89 0 35.03 1.36 ; - END - END chany_bottom_out[19] - PIN chany_top_out[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 51.45 74.8 51.59 76.16 ; - END - END chany_top_out[0] - PIN chany_top_out[1] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 43.17 74.8 43.31 76.16 ; - END - END chany_top_out[1] - PIN chany_top_out[2] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 53.29 74.8 53.43 76.16 ; - END - END chany_top_out[2] - PIN chany_top_out[3] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 44.09 74.8 44.23 76.16 ; - END - END chany_top_out[3] - PIN chany_top_out[4] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 39.49 74.8 39.63 76.16 ; - END - END chany_top_out[4] - PIN chany_top_out[5] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 33.51 74.8 33.65 76.16 ; - END - END chany_top_out[5] - PIN chany_top_out[6] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 21.09 74.8 21.23 76.16 ; - END - END chany_top_out[6] - PIN chany_top_out[7] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 34.43 74.8 34.57 76.16 ; - END - END chany_top_out[7] - PIN chany_top_out[8] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 22.01 74.8 22.15 76.16 ; - END - END chany_top_out[8] - PIN chany_top_out[9] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 41.33 74.8 41.47 76.16 ; - END - END chany_top_out[9] - PIN chany_top_out[10] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 42.25 74.8 42.39 76.16 ; - END - END chany_top_out[10] - PIN chany_top_out[11] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 45.01 74.8 45.15 76.16 ; - END - END chany_top_out[11] - PIN chany_top_out[12] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 36.73 74.8 36.87 76.16 ; - END - END chany_top_out[12] - PIN chany_top_out[13] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 35.35 74.8 35.49 76.16 ; - END - END chany_top_out[13] - PIN chany_top_out[14] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 22.93 74.8 23.07 76.16 ; - END - END chany_top_out[14] - PIN chany_top_out[15] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 31.21 74.8 31.35 76.16 ; - END - END chany_top_out[15] - PIN chany_top_out[16] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 52.37 74.8 52.51 76.16 ; - END - END chany_top_out[16] - PIN chany_top_out[17] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 20.17 74.8 20.31 76.16 ; - END - END chany_top_out[17] - PIN chany_top_out[18] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 23.85 74.8 23.99 76.16 ; - END - END chany_top_out[18] - PIN chany_top_out[19] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 46.85 74.8 46.99 76.16 ; - END - END chany_top_out[19] - PIN left_grid_pin_16_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 27.05 1.38 27.35 ; - END - END left_grid_pin_16_[0] - PIN left_grid_pin_17_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 32.49 1.38 32.79 ; - END - END left_grid_pin_17_[0] - PIN left_grid_pin_18_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 4.61 1.38 4.91 ; - END - END left_grid_pin_18_[0] - PIN left_grid_pin_19_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 31.13 1.38 31.43 ; - END - END left_grid_pin_19_[0] - PIN left_grid_pin_20_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 8.69 1.38 8.99 ; - END - END left_grid_pin_20_[0] - PIN left_grid_pin_21_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 5.97 1.38 6.27 ; - END - END left_grid_pin_21_[0] - PIN left_grid_pin_22_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 7.33 1.38 7.63 ; - END - END left_grid_pin_22_[0] - PIN left_grid_pin_23_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 12.77 1.38 13.07 ; - END - END left_grid_pin_23_[0] - PIN left_grid_pin_24_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 25.69 1.38 25.99 ; - END - END left_grid_pin_24_[0] - PIN left_grid_pin_25_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 24.33 1.38 24.63 ; - END - END left_grid_pin_25_[0] - PIN left_grid_pin_26_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 14.13 1.38 14.43 ; - END - END left_grid_pin_26_[0] - PIN left_grid_pin_27_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 52.89 1.38 53.19 ; - END - END left_grid_pin_27_[0] - PIN left_grid_pin_28_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 50.17 1.38 50.47 ; - END - END left_grid_pin_28_[0] - PIN left_grid_pin_29_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 29.77 1.38 30.07 ; - END - END left_grid_pin_29_[0] - PIN left_grid_pin_30_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 28.41 1.38 28.71 ; - END - END left_grid_pin_30_[0] - PIN left_grid_pin_31_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 51.53 1.38 51.83 ; - END - END left_grid_pin_31_[0] - PIN ccff_tail[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 51.53 66.24 51.83 ; - END - END ccff_tail[0] - PIN VDD - DIRECTION INPUT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0 2.48 0.48 2.96 ; - RECT 65.76 2.48 66.24 2.96 ; - RECT 0 7.92 0.48 8.4 ; - RECT 65.76 7.92 66.24 8.4 ; - RECT 0 13.36 0.48 13.84 ; - RECT 65.76 13.36 66.24 13.84 ; - RECT 0 18.8 0.48 19.28 ; - RECT 65.76 18.8 66.24 19.28 ; - RECT 0 24.24 0.48 24.72 ; - RECT 65.76 24.24 66.24 24.72 ; - RECT 0 29.68 0.48 30.16 ; - RECT 65.76 29.68 66.24 30.16 ; - RECT 0 35.12 0.48 35.6 ; - RECT 65.76 35.12 66.24 35.6 ; - RECT 0 40.56 0.48 41.04 ; - RECT 65.76 40.56 66.24 41.04 ; - RECT 0 46 0.48 46.48 ; - RECT 65.76 46 66.24 46.48 ; - RECT 0 51.44 0.48 51.92 ; - RECT 65.76 51.44 66.24 51.92 ; - RECT 0 56.88 0.48 57.36 ; - RECT 65.76 56.88 66.24 57.36 ; - RECT 0 62.32 0.48 62.8 ; - RECT 65.76 62.32 66.24 62.8 ; - RECT 0 67.76 0.48 68.24 ; - RECT 65.76 67.76 66.24 68.24 ; - RECT 0 73.2 0.48 73.68 ; - RECT 65.76 73.2 66.24 73.68 ; - LAYER met5 ; - RECT 0 5.88 3.2 9.08 ; - RECT 63.04 5.88 66.24 9.08 ; - RECT 0 46.68 3.2 49.88 ; - RECT 63.04 46.68 66.24 49.88 ; - LAYER met4 ; - RECT 10.74 0 11.34 0.6 ; - RECT 40.18 0 40.78 0.6 ; - RECT 10.74 75.56 11.34 76.16 ; - RECT 40.18 75.56 40.78 76.16 ; - END - END VDD - PIN VSS - DIRECTION INPUT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0 0 66.24 0.24 ; - RECT 0 5.2 0.48 5.68 ; - RECT 65.76 5.2 66.24 5.68 ; - RECT 0 10.64 0.48 11.12 ; - RECT 65.76 10.64 66.24 11.12 ; - RECT 0 16.08 0.48 16.56 ; - RECT 65.76 16.08 66.24 16.56 ; - RECT 0 21.52 0.48 22 ; - RECT 65.76 21.52 66.24 22 ; - RECT 0 26.96 0.48 27.44 ; - RECT 65.76 26.96 66.24 27.44 ; - RECT 0 32.4 0.48 32.88 ; - RECT 65.76 32.4 66.24 32.88 ; - RECT 0 37.84 0.48 38.32 ; - RECT 65.76 37.84 66.24 38.32 ; - RECT 0 43.28 0.48 43.76 ; - RECT 65.76 43.28 66.24 43.76 ; - RECT 0 48.72 0.48 49.2 ; - RECT 65.76 48.72 66.24 49.2 ; - RECT 0 54.16 0.48 54.64 ; - RECT 65.76 54.16 66.24 54.64 ; - RECT 0 59.6 0.48 60.08 ; - RECT 65.76 59.6 66.24 60.08 ; - RECT 0 65.04 0.48 65.52 ; - RECT 65.76 65.04 66.24 65.52 ; - RECT 0 70.48 0.48 70.96 ; - RECT 65.76 70.48 66.24 70.96 ; - RECT 0 75.92 66.24 76.16 ; - LAYER met5 ; - RECT 0 26.28 3.2 29.48 ; - RECT 63.04 26.28 66.24 29.48 ; - RECT 0 67.08 3.2 70.28 ; - RECT 63.04 67.08 66.24 70.28 ; - LAYER met4 ; - RECT 25.46 0 26.06 0.6 ; - RECT 54.9 0 55.5 0.6 ; - RECT 25.46 75.56 26.06 76.16 ; - RECT 54.9 75.56 55.5 76.16 ; - END - END VSS - PIN prog_clk__FEEDTHRU_1[0] - DIRECTION OUTPUT ; - USE CLOCK ; - PORT - LAYER met3 ; - RECT 64.86 9.37 66.24 9.67 ; - END - END prog_clk__FEEDTHRU_1[0] - PIN prog_clk__FEEDTHRU_2[0] - DIRECTION OUTPUT ; - USE CLOCK ; - PORT - LAYER met2 ; - RECT 27.07 74.8 27.21 76.16 ; - END - END prog_clk__FEEDTHRU_2[0] - OBS - LAYER li1 ; - RECT 0 76.075 66.24 76.245 ; - RECT 65.32 73.355 66.24 73.525 ; - RECT 0 73.355 3.68 73.525 ; - RECT 65.32 70.635 66.24 70.805 ; - RECT 0 70.635 1.84 70.805 ; - RECT 65.32 67.915 66.24 68.085 ; - RECT 0 67.915 1.84 68.085 ; - RECT 65.32 65.195 66.24 65.365 ; - RECT 0 65.195 1.84 65.365 ; - RECT 62.56 62.475 66.24 62.645 ; - RECT 0 62.475 1.84 62.645 ; - RECT 62.56 59.755 66.24 59.925 ; - RECT 0 59.755 1.84 59.925 ; - RECT 65.32 57.035 66.24 57.205 ; - RECT 0 57.035 3.68 57.205 ; - RECT 65.32 54.315 66.24 54.485 ; - RECT 0 54.315 3.68 54.485 ; - RECT 65.32 51.595 66.24 51.765 ; - RECT 0 51.595 1.84 51.765 ; - RECT 65.32 48.875 66.24 49.045 ; - RECT 0 48.875 1.84 49.045 ; - RECT 65.32 46.155 66.24 46.325 ; - RECT 0 46.155 1.84 46.325 ; - RECT 65.78 43.435 66.24 43.605 ; - RECT 0 43.435 1.84 43.605 ; - RECT 65.32 40.715 66.24 40.885 ; - RECT 0 40.715 3.68 40.885 ; - RECT 65.32 37.995 66.24 38.165 ; - RECT 0 37.995 3.68 38.165 ; - RECT 65.32 35.275 66.24 35.445 ; - RECT 0 35.275 1.84 35.445 ; - RECT 65.32 32.555 66.24 32.725 ; - RECT 0 32.555 3.68 32.725 ; - RECT 65.32 29.835 66.24 30.005 ; - RECT 0 29.835 3.68 30.005 ; - RECT 65.32 27.115 66.24 27.285 ; - RECT 0 27.115 1.84 27.285 ; - RECT 65.32 24.395 66.24 24.565 ; - RECT 0 24.395 1.84 24.565 ; - RECT 65.32 21.675 66.24 21.845 ; - RECT 0 21.675 1.84 21.845 ; - RECT 65.32 18.955 66.24 19.125 ; - RECT 0 18.955 1.84 19.125 ; - RECT 65.32 16.235 66.24 16.405 ; - RECT 0 16.235 3.68 16.405 ; - RECT 65.32 13.515 66.24 13.685 ; - RECT 0 13.515 3.68 13.685 ; - RECT 65.32 10.795 66.24 10.965 ; - RECT 0 10.795 3.68 10.965 ; - RECT 65.32 8.075 66.24 8.245 ; - RECT 0 8.075 3.68 8.245 ; - RECT 65.32 5.355 66.24 5.525 ; - RECT 0 5.355 3.68 5.525 ; - RECT 65.32 2.635 66.24 2.805 ; - RECT 0 2.635 3.68 2.805 ; - RECT 0 -0.085 66.24 0.085 ; - LAYER met2 ; - RECT 55.06 75.975 55.34 76.345 ; - RECT 25.62 75.975 25.9 76.345 ; - RECT 45.41 74.3 45.67 74.62 ; - RECT 37.59 74.3 37.85 74.62 ; - RECT 27.93 74.3 28.19 74.62 ; - RECT 46.33 1.54 46.59 1.86 ; - RECT 19.19 1.54 19.45 1.86 ; - RECT 55.06 -0.185 55.34 0.185 ; - RECT 25.62 -0.185 25.9 0.185 ; - POLYGON 65.96 75.88 65.96 0.28 58.77 0.28 58.77 1.64 58.07 1.64 58.07 0.28 57.85 0.28 57.85 1.64 57.15 1.64 57.15 0.28 56.93 0.28 56.93 1.64 56.23 1.64 56.23 0.28 54.63 0.28 54.63 1.64 53.93 1.64 53.93 0.28 53.71 0.28 53.71 1.64 53.01 1.64 53.01 0.28 52.79 0.28 52.79 1.64 52.09 1.64 52.09 0.28 51.87 0.28 51.87 1.64 51.17 1.64 51.17 0.28 50.95 0.28 50.95 1.64 50.25 1.64 50.25 0.28 50.03 0.28 50.03 1.64 49.33 1.64 49.33 0.28 49.11 0.28 49.11 1.64 48.41 1.64 48.41 0.28 48.19 0.28 48.19 1.64 47.49 1.64 47.49 0.28 47.27 0.28 47.27 1.64 46.57 1.64 46.57 0.28 45.89 0.28 45.89 1.64 45.19 1.64 45.19 0.28 44.51 0.28 44.51 1.64 43.81 1.64 43.81 0.28 43.59 0.28 43.59 1.64 42.89 1.64 42.89 0.28 42.67 0.28 42.67 1.64 41.97 1.64 41.97 0.28 41.75 0.28 41.75 1.64 41.05 1.64 41.05 0.28 40.83 0.28 40.83 1.64 40.13 1.64 40.13 0.28 39.45 0.28 39.45 1.64 38.75 1.64 38.75 0.28 38.53 0.28 38.53 1.64 37.83 1.64 37.83 0.28 37.15 0.28 37.15 1.64 36.45 1.64 36.45 0.28 36.23 0.28 36.23 1.64 35.53 1.64 35.53 0.28 35.31 0.28 35.31 1.64 34.61 1.64 34.61 0.28 33.93 0.28 33.93 1.64 33.23 1.64 33.23 0.28 33.01 0.28 33.01 1.64 32.31 1.64 32.31 0.28 32.09 0.28 32.09 1.64 31.39 1.64 31.39 0.28 31.17 0.28 31.17 1.64 30.47 1.64 30.47 0.28 29.79 0.28 29.79 1.64 29.09 1.64 29.09 0.28 27.95 0.28 27.95 1.64 27.25 1.64 27.25 0.28 27.03 0.28 27.03 1.64 26.33 1.64 26.33 0.28 25.19 0.28 25.19 1.64 24.49 1.64 24.49 0.28 24.27 0.28 24.27 1.64 23.57 1.64 23.57 0.28 22.89 0.28 22.89 1.64 22.19 1.64 22.19 0.28 21.97 0.28 21.97 1.64 21.27 1.64 21.27 0.28 21.05 0.28 21.05 1.64 20.35 1.64 20.35 0.28 20.13 0.28 20.13 1.64 19.43 1.64 19.43 0.28 19.21 0.28 19.21 1.64 18.51 1.64 18.51 0.28 18.29 0.28 18.29 1.64 17.59 1.64 17.59 0.28 9.09 0.28 9.09 1.64 8.39 1.64 8.39 0.28 0.28 0.28 0.28 75.88 8.39 75.88 8.39 74.52 9.09 74.52 9.09 75.88 18.97 75.88 18.97 74.52 19.67 74.52 19.67 75.88 19.89 75.88 19.89 74.52 20.59 74.52 20.59 75.88 20.81 75.88 20.81 74.52 21.51 74.52 21.51 75.88 21.73 75.88 21.73 74.52 22.43 74.52 22.43 75.88 22.65 75.88 22.65 74.52 23.35 74.52 23.35 75.88 23.57 75.88 23.57 74.52 24.27 74.52 24.27 75.88 24.49 75.88 24.49 74.52 25.19 74.52 25.19 75.88 26.79 75.88 26.79 74.52 27.49 74.52 27.49 75.88 28.17 75.88 28.17 74.52 28.87 74.52 28.87 75.88 29.09 75.88 29.09 74.52 29.79 74.52 29.79 75.88 30.01 75.88 30.01 74.52 30.71 74.52 30.71 75.88 30.93 75.88 30.93 74.52 31.63 74.52 31.63 75.88 32.31 75.88 32.31 74.52 33.01 74.52 33.01 75.88 33.23 75.88 33.23 74.52 33.93 74.52 33.93 75.88 34.15 75.88 34.15 74.52 34.85 74.52 34.85 75.88 35.07 75.88 35.07 74.52 35.77 74.52 35.77 75.88 36.45 75.88 36.45 74.52 37.15 74.52 37.15 75.88 37.83 75.88 37.83 74.52 38.53 74.52 38.53 75.88 39.21 75.88 39.21 74.52 39.91 74.52 39.91 75.88 40.13 75.88 40.13 74.52 40.83 74.52 40.83 75.88 41.05 75.88 41.05 74.52 41.75 74.52 41.75 75.88 41.97 75.88 41.97 74.52 42.67 74.52 42.67 75.88 42.89 75.88 42.89 74.52 43.59 74.52 43.59 75.88 43.81 75.88 43.81 74.52 44.51 74.52 44.51 75.88 44.73 75.88 44.73 74.52 45.43 74.52 45.43 75.88 45.65 75.88 45.65 74.52 46.35 74.52 46.35 75.88 46.57 75.88 46.57 74.52 47.27 74.52 47.27 75.88 47.49 75.88 47.49 74.52 48.19 74.52 48.19 75.88 48.41 75.88 48.41 74.52 49.11 74.52 49.11 75.88 49.33 75.88 49.33 74.52 50.03 74.52 50.03 75.88 50.25 75.88 50.25 74.52 50.95 74.52 50.95 75.88 51.17 75.88 51.17 74.52 51.87 74.52 51.87 75.88 52.09 75.88 52.09 74.52 52.79 74.52 52.79 75.88 53.01 75.88 53.01 74.52 53.71 74.52 53.71 75.88 53.93 75.88 53.93 74.52 54.63 74.52 54.63 75.88 55.77 75.88 55.77 74.52 56.47 74.52 56.47 75.88 56.69 75.88 56.69 74.52 57.39 74.52 57.39 75.88 61.29 75.88 61.29 74.52 61.99 74.52 61.99 75.88 62.21 75.88 62.21 74.52 62.91 74.52 62.91 75.88 63.13 75.88 63.13 74.52 63.83 74.52 63.83 75.88 ; - LAYER met3 ; - POLYGON 55.365 76.325 55.365 76.32 55.58 76.32 55.58 76 55.365 76 55.365 75.995 55.035 75.995 55.035 76 54.82 76 54.82 76.32 55.035 76.32 55.035 76.325 ; - POLYGON 25.925 76.325 25.925 76.32 26.14 76.32 26.14 76 25.925 76 25.925 75.995 25.595 75.995 25.595 76 25.38 76 25.38 76.32 25.595 76.32 25.595 76.325 ; - POLYGON 55.365 0.165 55.365 0.16 55.58 0.16 55.58 -0.16 55.365 -0.16 55.365 -0.165 55.035 -0.165 55.035 -0.16 54.82 -0.16 54.82 0.16 55.035 0.16 55.035 0.165 ; - POLYGON 25.925 0.165 25.925 0.16 26.14 0.16 26.14 -0.16 25.925 -0.16 25.925 -0.165 25.595 -0.165 25.595 -0.16 25.38 -0.16 25.38 0.16 25.595 0.16 25.595 0.165 ; - POLYGON 65.84 75.76 65.84 52.23 64.46 52.23 64.46 51.13 65.84 51.13 65.84 10.07 64.46 10.07 64.46 8.97 65.84 8.97 65.84 0.4 0.4 0.4 0.4 4.21 1.78 4.21 1.78 5.31 0.4 5.31 0.4 5.57 1.78 5.57 1.78 6.67 0.4 6.67 0.4 6.93 1.78 6.93 1.78 8.03 0.4 8.03 0.4 8.29 1.78 8.29 1.78 9.39 0.4 9.39 0.4 12.37 1.78 12.37 1.78 13.47 0.4 13.47 0.4 13.73 1.78 13.73 1.78 14.83 0.4 14.83 0.4 23.93 1.78 23.93 1.78 25.03 0.4 25.03 0.4 25.29 1.78 25.29 1.78 26.39 0.4 26.39 0.4 26.65 1.78 26.65 1.78 27.75 0.4 27.75 0.4 28.01 1.78 28.01 1.78 29.11 0.4 29.11 0.4 29.37 1.78 29.37 1.78 30.47 0.4 30.47 0.4 30.73 1.78 30.73 1.78 31.83 0.4 31.83 0.4 32.09 1.78 32.09 1.78 33.19 0.4 33.19 0.4 49.77 1.78 49.77 1.78 50.87 0.4 50.87 0.4 51.13 1.78 51.13 1.78 52.23 0.4 52.23 0.4 52.49 1.78 52.49 1.78 53.59 0.4 53.59 0.4 64.73 1.78 64.73 1.78 65.83 0.4 65.83 0.4 75.76 ; - LAYER met4 ; - POLYGON 65.84 75.76 65.84 0.4 55.9 0.4 55.9 1 54.5 1 54.5 0.4 42.87 0.4 42.87 1.76 41.77 1.76 41.77 0.4 41.18 0.4 41.18 1 39.78 1 39.78 0.4 38.27 0.4 38.27 1.76 37.17 1.76 37.17 0.4 26.46 0.4 26.46 1 25.06 1 25.06 0.4 11.74 0.4 11.74 1 10.34 1 10.34 0.4 0.4 0.4 0.4 75.76 10.34 75.76 10.34 75.16 11.74 75.16 11.74 75.76 25.06 75.76 25.06 75.16 26.46 75.16 26.46 75.76 39.78 75.76 39.78 75.16 41.18 75.16 41.18 75.76 54.5 75.76 54.5 75.16 55.9 75.16 55.9 75.76 ; - LAYER met5 ; - POLYGON 64.64 74.56 64.64 71.88 61.44 71.88 61.44 65.48 64.64 65.48 64.64 51.48 61.44 51.48 61.44 45.08 64.64 45.08 64.64 31.08 61.44 31.08 61.44 24.68 64.64 24.68 64.64 10.68 61.44 10.68 61.44 4.28 64.64 4.28 64.64 1.6 1.6 1.6 1.6 4.28 4.8 4.28 4.8 10.68 1.6 10.68 1.6 24.68 4.8 24.68 4.8 31.08 1.6 31.08 1.6 45.08 4.8 45.08 4.8 51.48 1.6 51.48 1.6 65.48 4.8 65.48 4.8 71.88 1.6 71.88 1.6 74.56 ; - LAYER met1 ; - POLYGON 65.96 75.64 65.96 73.96 65.48 73.96 65.48 72.92 65.96 72.92 65.96 71.24 65.48 71.24 65.48 70.2 65.96 70.2 65.96 68.52 65.48 68.52 65.48 67.48 65.96 67.48 65.96 65.8 65.48 65.8 65.48 64.76 65.96 64.76 65.96 63.08 65.48 63.08 65.48 62.04 65.96 62.04 65.96 60.36 65.48 60.36 65.48 59.32 65.96 59.32 65.96 57.64 65.48 57.64 65.48 56.6 65.96 56.6 65.96 54.92 65.48 54.92 65.48 53.88 65.96 53.88 65.96 52.2 65.48 52.2 65.48 51.16 65.96 51.16 65.96 49.48 65.48 49.48 65.48 48.44 65.96 48.44 65.96 46.76 65.48 46.76 65.48 45.72 65.96 45.72 65.96 44.04 65.48 44.04 65.48 43 65.96 43 65.96 41.32 65.48 41.32 65.48 40.28 65.96 40.28 65.96 38.6 65.48 38.6 65.48 37.56 65.96 37.56 65.96 35.88 65.48 35.88 65.48 34.84 65.96 34.84 65.96 33.16 65.48 33.16 65.48 32.12 65.96 32.12 65.96 30.44 65.48 30.44 65.48 29.4 65.96 29.4 65.96 27.72 65.48 27.72 65.48 26.68 65.96 26.68 65.96 25 65.48 25 65.48 23.96 65.96 23.96 65.96 22.28 65.48 22.28 65.48 21.24 65.96 21.24 65.96 19.56 65.48 19.56 65.48 18.52 65.96 18.52 65.96 16.84 65.48 16.84 65.48 15.8 65.96 15.8 65.96 14.12 65.48 14.12 65.48 13.08 65.96 13.08 65.96 11.4 65.48 11.4 65.48 10.36 65.96 10.36 65.96 8.68 65.48 8.68 65.48 7.64 65.96 7.64 65.96 5.96 65.48 5.96 65.48 4.92 65.96 4.92 65.96 3.24 65.48 3.24 65.48 2.2 65.96 2.2 65.96 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 0.76 10.36 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 ; - LAYER li1 ; - RECT 0.17 0.17 66.07 75.99 ; - LAYER mcon ; - RECT 65.925 76.075 66.095 76.245 ; - RECT 65.465 76.075 65.635 76.245 ; - RECT 65.005 76.075 65.175 76.245 ; - RECT 64.545 76.075 64.715 76.245 ; - RECT 64.085 76.075 64.255 76.245 ; - RECT 63.625 76.075 63.795 76.245 ; - RECT 63.165 76.075 63.335 76.245 ; - RECT 62.705 76.075 62.875 76.245 ; - RECT 62.245 76.075 62.415 76.245 ; - RECT 61.785 76.075 61.955 76.245 ; - RECT 61.325 76.075 61.495 76.245 ; - RECT 60.865 76.075 61.035 76.245 ; - RECT 60.405 76.075 60.575 76.245 ; - RECT 59.945 76.075 60.115 76.245 ; - RECT 59.485 76.075 59.655 76.245 ; - RECT 59.025 76.075 59.195 76.245 ; - RECT 58.565 76.075 58.735 76.245 ; - RECT 58.105 76.075 58.275 76.245 ; - RECT 57.645 76.075 57.815 76.245 ; - RECT 57.185 76.075 57.355 76.245 ; - RECT 56.725 76.075 56.895 76.245 ; - RECT 56.265 76.075 56.435 76.245 ; - RECT 55.805 76.075 55.975 76.245 ; - RECT 55.345 76.075 55.515 76.245 ; - RECT 54.885 76.075 55.055 76.245 ; - RECT 54.425 76.075 54.595 76.245 ; - RECT 53.965 76.075 54.135 76.245 ; - RECT 53.505 76.075 53.675 76.245 ; - RECT 53.045 76.075 53.215 76.245 ; - RECT 52.585 76.075 52.755 76.245 ; - RECT 52.125 76.075 52.295 76.245 ; - RECT 51.665 76.075 51.835 76.245 ; - RECT 51.205 76.075 51.375 76.245 ; - RECT 50.745 76.075 50.915 76.245 ; - RECT 50.285 76.075 50.455 76.245 ; - RECT 49.825 76.075 49.995 76.245 ; - RECT 49.365 76.075 49.535 76.245 ; - RECT 48.905 76.075 49.075 76.245 ; - RECT 48.445 76.075 48.615 76.245 ; - RECT 47.985 76.075 48.155 76.245 ; - RECT 47.525 76.075 47.695 76.245 ; - RECT 47.065 76.075 47.235 76.245 ; - RECT 46.605 76.075 46.775 76.245 ; - RECT 46.145 76.075 46.315 76.245 ; - RECT 45.685 76.075 45.855 76.245 ; - RECT 45.225 76.075 45.395 76.245 ; - RECT 44.765 76.075 44.935 76.245 ; - RECT 44.305 76.075 44.475 76.245 ; - RECT 43.845 76.075 44.015 76.245 ; - RECT 43.385 76.075 43.555 76.245 ; - RECT 42.925 76.075 43.095 76.245 ; - RECT 42.465 76.075 42.635 76.245 ; - RECT 42.005 76.075 42.175 76.245 ; - RECT 41.545 76.075 41.715 76.245 ; - RECT 41.085 76.075 41.255 76.245 ; - RECT 40.625 76.075 40.795 76.245 ; - RECT 40.165 76.075 40.335 76.245 ; - RECT 39.705 76.075 39.875 76.245 ; - RECT 39.245 76.075 39.415 76.245 ; - RECT 38.785 76.075 38.955 76.245 ; - RECT 38.325 76.075 38.495 76.245 ; - RECT 37.865 76.075 38.035 76.245 ; - RECT 37.405 76.075 37.575 76.245 ; - RECT 36.945 76.075 37.115 76.245 ; - RECT 36.485 76.075 36.655 76.245 ; - RECT 36.025 76.075 36.195 76.245 ; - RECT 35.565 76.075 35.735 76.245 ; - RECT 35.105 76.075 35.275 76.245 ; - RECT 34.645 76.075 34.815 76.245 ; - RECT 34.185 76.075 34.355 76.245 ; - RECT 33.725 76.075 33.895 76.245 ; - RECT 33.265 76.075 33.435 76.245 ; - RECT 32.805 76.075 32.975 76.245 ; - RECT 32.345 76.075 32.515 76.245 ; - RECT 31.885 76.075 32.055 76.245 ; - RECT 31.425 76.075 31.595 76.245 ; - RECT 30.965 76.075 31.135 76.245 ; - RECT 30.505 76.075 30.675 76.245 ; - RECT 30.045 76.075 30.215 76.245 ; - RECT 29.585 76.075 29.755 76.245 ; - RECT 29.125 76.075 29.295 76.245 ; - RECT 28.665 76.075 28.835 76.245 ; - RECT 28.205 76.075 28.375 76.245 ; - RECT 27.745 76.075 27.915 76.245 ; - RECT 27.285 76.075 27.455 76.245 ; - RECT 26.825 76.075 26.995 76.245 ; - RECT 26.365 76.075 26.535 76.245 ; - RECT 25.905 76.075 26.075 76.245 ; - RECT 25.445 76.075 25.615 76.245 ; - RECT 24.985 76.075 25.155 76.245 ; - RECT 24.525 76.075 24.695 76.245 ; - RECT 24.065 76.075 24.235 76.245 ; - RECT 23.605 76.075 23.775 76.245 ; - RECT 23.145 76.075 23.315 76.245 ; - RECT 22.685 76.075 22.855 76.245 ; - RECT 22.225 76.075 22.395 76.245 ; - RECT 21.765 76.075 21.935 76.245 ; - RECT 21.305 76.075 21.475 76.245 ; - RECT 20.845 76.075 21.015 76.245 ; - RECT 20.385 76.075 20.555 76.245 ; - RECT 19.925 76.075 20.095 76.245 ; - RECT 19.465 76.075 19.635 76.245 ; - RECT 19.005 76.075 19.175 76.245 ; - RECT 18.545 76.075 18.715 76.245 ; - RECT 18.085 76.075 18.255 76.245 ; - RECT 17.625 76.075 17.795 76.245 ; - RECT 17.165 76.075 17.335 76.245 ; - RECT 16.705 76.075 16.875 76.245 ; - RECT 16.245 76.075 16.415 76.245 ; - RECT 15.785 76.075 15.955 76.245 ; - RECT 15.325 76.075 15.495 76.245 ; - RECT 14.865 76.075 15.035 76.245 ; - RECT 14.405 76.075 14.575 76.245 ; - RECT 13.945 76.075 14.115 76.245 ; - RECT 13.485 76.075 13.655 76.245 ; - RECT 13.025 76.075 13.195 76.245 ; - RECT 12.565 76.075 12.735 76.245 ; - RECT 12.105 76.075 12.275 76.245 ; - RECT 11.645 76.075 11.815 76.245 ; - RECT 11.185 76.075 11.355 76.245 ; - RECT 10.725 76.075 10.895 76.245 ; - RECT 10.265 76.075 10.435 76.245 ; - RECT 9.805 76.075 9.975 76.245 ; - RECT 9.345 76.075 9.515 76.245 ; - RECT 8.885 76.075 9.055 76.245 ; - RECT 8.425 76.075 8.595 76.245 ; - RECT 7.965 76.075 8.135 76.245 ; - RECT 7.505 76.075 7.675 76.245 ; - RECT 7.045 76.075 7.215 76.245 ; - RECT 6.585 76.075 6.755 76.245 ; - RECT 6.125 76.075 6.295 76.245 ; - RECT 5.665 76.075 5.835 76.245 ; - RECT 5.205 76.075 5.375 76.245 ; - RECT 4.745 76.075 4.915 76.245 ; - RECT 4.285 76.075 4.455 76.245 ; - RECT 3.825 76.075 3.995 76.245 ; - RECT 3.365 76.075 3.535 76.245 ; - RECT 2.905 76.075 3.075 76.245 ; - RECT 2.445 76.075 2.615 76.245 ; - RECT 1.985 76.075 2.155 76.245 ; - RECT 1.525 76.075 1.695 76.245 ; - RECT 1.065 76.075 1.235 76.245 ; - RECT 0.605 76.075 0.775 76.245 ; - RECT 0.145 76.075 0.315 76.245 ; - RECT 65.925 73.355 66.095 73.525 ; - RECT 65.465 73.355 65.635 73.525 ; - RECT 0.605 73.355 0.775 73.525 ; - RECT 0.145 73.355 0.315 73.525 ; - RECT 65.925 70.635 66.095 70.805 ; - RECT 65.465 70.635 65.635 70.805 ; - RECT 0.605 70.635 0.775 70.805 ; - RECT 0.145 70.635 0.315 70.805 ; - RECT 65.925 67.915 66.095 68.085 ; - RECT 65.465 67.915 65.635 68.085 ; - RECT 0.605 67.915 0.775 68.085 ; - RECT 0.145 67.915 0.315 68.085 ; - RECT 65.925 65.195 66.095 65.365 ; - RECT 65.465 65.195 65.635 65.365 ; - RECT 0.605 65.195 0.775 65.365 ; - RECT 0.145 65.195 0.315 65.365 ; - RECT 65.925 62.475 66.095 62.645 ; - RECT 65.465 62.475 65.635 62.645 ; - RECT 0.605 62.475 0.775 62.645 ; - RECT 0.145 62.475 0.315 62.645 ; - RECT 65.925 59.755 66.095 59.925 ; - RECT 65.465 59.755 65.635 59.925 ; - RECT 0.605 59.755 0.775 59.925 ; - RECT 0.145 59.755 0.315 59.925 ; - RECT 65.925 57.035 66.095 57.205 ; - RECT 65.465 57.035 65.635 57.205 ; - RECT 0.605 57.035 0.775 57.205 ; - RECT 0.145 57.035 0.315 57.205 ; - RECT 65.925 54.315 66.095 54.485 ; - RECT 65.465 54.315 65.635 54.485 ; - RECT 0.605 54.315 0.775 54.485 ; - RECT 0.145 54.315 0.315 54.485 ; - RECT 65.925 51.595 66.095 51.765 ; - RECT 65.465 51.595 65.635 51.765 ; - RECT 0.605 51.595 0.775 51.765 ; - RECT 0.145 51.595 0.315 51.765 ; - RECT 65.925 48.875 66.095 49.045 ; - RECT 65.465 48.875 65.635 49.045 ; - RECT 0.605 48.875 0.775 49.045 ; - RECT 0.145 48.875 0.315 49.045 ; - RECT 65.925 46.155 66.095 46.325 ; - RECT 65.465 46.155 65.635 46.325 ; - RECT 0.605 46.155 0.775 46.325 ; - RECT 0.145 46.155 0.315 46.325 ; - RECT 65.925 43.435 66.095 43.605 ; - RECT 65.465 43.435 65.635 43.605 ; - RECT 0.605 43.435 0.775 43.605 ; - RECT 0.145 43.435 0.315 43.605 ; - RECT 65.925 40.715 66.095 40.885 ; - RECT 65.465 40.715 65.635 40.885 ; - RECT 0.605 40.715 0.775 40.885 ; - RECT 0.145 40.715 0.315 40.885 ; - RECT 65.925 37.995 66.095 38.165 ; - RECT 65.465 37.995 65.635 38.165 ; - RECT 0.605 37.995 0.775 38.165 ; - RECT 0.145 37.995 0.315 38.165 ; - RECT 65.925 35.275 66.095 35.445 ; - RECT 65.465 35.275 65.635 35.445 ; - RECT 0.605 35.275 0.775 35.445 ; - RECT 0.145 35.275 0.315 35.445 ; - RECT 65.925 32.555 66.095 32.725 ; - RECT 65.465 32.555 65.635 32.725 ; - RECT 0.605 32.555 0.775 32.725 ; - RECT 0.145 32.555 0.315 32.725 ; - RECT 65.925 29.835 66.095 30.005 ; - RECT 65.465 29.835 65.635 30.005 ; - RECT 0.605 29.835 0.775 30.005 ; - RECT 0.145 29.835 0.315 30.005 ; - RECT 65.925 27.115 66.095 27.285 ; - RECT 65.465 27.115 65.635 27.285 ; - RECT 0.605 27.115 0.775 27.285 ; - RECT 0.145 27.115 0.315 27.285 ; - RECT 65.925 24.395 66.095 24.565 ; - RECT 65.465 24.395 65.635 24.565 ; - RECT 0.605 24.395 0.775 24.565 ; - RECT 0.145 24.395 0.315 24.565 ; - RECT 65.925 21.675 66.095 21.845 ; - RECT 65.465 21.675 65.635 21.845 ; - RECT 0.605 21.675 0.775 21.845 ; - RECT 0.145 21.675 0.315 21.845 ; - RECT 65.925 18.955 66.095 19.125 ; - RECT 65.465 18.955 65.635 19.125 ; - RECT 0.605 18.955 0.775 19.125 ; - RECT 0.145 18.955 0.315 19.125 ; - RECT 65.925 16.235 66.095 16.405 ; - RECT 65.465 16.235 65.635 16.405 ; - RECT 0.605 16.235 0.775 16.405 ; - RECT 0.145 16.235 0.315 16.405 ; - RECT 65.925 13.515 66.095 13.685 ; - RECT 65.465 13.515 65.635 13.685 ; - RECT 0.605 13.515 0.775 13.685 ; - RECT 0.145 13.515 0.315 13.685 ; - RECT 65.925 10.795 66.095 10.965 ; - RECT 65.465 10.795 65.635 10.965 ; - RECT 0.605 10.795 0.775 10.965 ; - RECT 0.145 10.795 0.315 10.965 ; - RECT 65.925 8.075 66.095 8.245 ; - RECT 65.465 8.075 65.635 8.245 ; - RECT 0.605 8.075 0.775 8.245 ; - RECT 0.145 8.075 0.315 8.245 ; - RECT 65.925 5.355 66.095 5.525 ; - RECT 65.465 5.355 65.635 5.525 ; - RECT 0.605 5.355 0.775 5.525 ; - RECT 0.145 5.355 0.315 5.525 ; - RECT 65.925 2.635 66.095 2.805 ; - RECT 65.465 2.635 65.635 2.805 ; - RECT 0.605 2.635 0.775 2.805 ; - RECT 0.145 2.635 0.315 2.805 ; - RECT 65.925 -0.085 66.095 0.085 ; - RECT 65.465 -0.085 65.635 0.085 ; - RECT 65.005 -0.085 65.175 0.085 ; - RECT 64.545 -0.085 64.715 0.085 ; - RECT 64.085 -0.085 64.255 0.085 ; - RECT 63.625 -0.085 63.795 0.085 ; - RECT 63.165 -0.085 63.335 0.085 ; - RECT 62.705 -0.085 62.875 0.085 ; - RECT 62.245 -0.085 62.415 0.085 ; - RECT 61.785 -0.085 61.955 0.085 ; - RECT 61.325 -0.085 61.495 0.085 ; - RECT 60.865 -0.085 61.035 0.085 ; - RECT 60.405 -0.085 60.575 0.085 ; - RECT 59.945 -0.085 60.115 0.085 ; - RECT 59.485 -0.085 59.655 0.085 ; - RECT 59.025 -0.085 59.195 0.085 ; - RECT 58.565 -0.085 58.735 0.085 ; - RECT 58.105 -0.085 58.275 0.085 ; - RECT 57.645 -0.085 57.815 0.085 ; - RECT 57.185 -0.085 57.355 0.085 ; - RECT 56.725 -0.085 56.895 0.085 ; - RECT 56.265 -0.085 56.435 0.085 ; - RECT 55.805 -0.085 55.975 0.085 ; - RECT 55.345 -0.085 55.515 0.085 ; - RECT 54.885 -0.085 55.055 0.085 ; - RECT 54.425 -0.085 54.595 0.085 ; - RECT 53.965 -0.085 54.135 0.085 ; - RECT 53.505 -0.085 53.675 0.085 ; - RECT 53.045 -0.085 53.215 0.085 ; - RECT 52.585 -0.085 52.755 0.085 ; - RECT 52.125 -0.085 52.295 0.085 ; - RECT 51.665 -0.085 51.835 0.085 ; - RECT 51.205 -0.085 51.375 0.085 ; - RECT 50.745 -0.085 50.915 0.085 ; - RECT 50.285 -0.085 50.455 0.085 ; - RECT 49.825 -0.085 49.995 0.085 ; - RECT 49.365 -0.085 49.535 0.085 ; - RECT 48.905 -0.085 49.075 0.085 ; - RECT 48.445 -0.085 48.615 0.085 ; - RECT 47.985 -0.085 48.155 0.085 ; - RECT 47.525 -0.085 47.695 0.085 ; - RECT 47.065 -0.085 47.235 0.085 ; - RECT 46.605 -0.085 46.775 0.085 ; - RECT 46.145 -0.085 46.315 0.085 ; - RECT 45.685 -0.085 45.855 0.085 ; - RECT 45.225 -0.085 45.395 0.085 ; - RECT 44.765 -0.085 44.935 0.085 ; - RECT 44.305 -0.085 44.475 0.085 ; - RECT 43.845 -0.085 44.015 0.085 ; - RECT 43.385 -0.085 43.555 0.085 ; - RECT 42.925 -0.085 43.095 0.085 ; - RECT 42.465 -0.085 42.635 0.085 ; - RECT 42.005 -0.085 42.175 0.085 ; - RECT 41.545 -0.085 41.715 0.085 ; - RECT 41.085 -0.085 41.255 0.085 ; - RECT 40.625 -0.085 40.795 0.085 ; - RECT 40.165 -0.085 40.335 0.085 ; - RECT 39.705 -0.085 39.875 0.085 ; - RECT 39.245 -0.085 39.415 0.085 ; - RECT 38.785 -0.085 38.955 0.085 ; - RECT 38.325 -0.085 38.495 0.085 ; - RECT 37.865 -0.085 38.035 0.085 ; - RECT 37.405 -0.085 37.575 0.085 ; - RECT 36.945 -0.085 37.115 0.085 ; - RECT 36.485 -0.085 36.655 0.085 ; - RECT 36.025 -0.085 36.195 0.085 ; - RECT 35.565 -0.085 35.735 0.085 ; - RECT 35.105 -0.085 35.275 0.085 ; - RECT 34.645 -0.085 34.815 0.085 ; - RECT 34.185 -0.085 34.355 0.085 ; - RECT 33.725 -0.085 33.895 0.085 ; - RECT 33.265 -0.085 33.435 0.085 ; - RECT 32.805 -0.085 32.975 0.085 ; - RECT 32.345 -0.085 32.515 0.085 ; - RECT 31.885 -0.085 32.055 0.085 ; - RECT 31.425 -0.085 31.595 0.085 ; - RECT 30.965 -0.085 31.135 0.085 ; - RECT 30.505 -0.085 30.675 0.085 ; - RECT 30.045 -0.085 30.215 0.085 ; - RECT 29.585 -0.085 29.755 0.085 ; - RECT 29.125 -0.085 29.295 0.085 ; - RECT 28.665 -0.085 28.835 0.085 ; - RECT 28.205 -0.085 28.375 0.085 ; - RECT 27.745 -0.085 27.915 0.085 ; - RECT 27.285 -0.085 27.455 0.085 ; - RECT 26.825 -0.085 26.995 0.085 ; - RECT 26.365 -0.085 26.535 0.085 ; - RECT 25.905 -0.085 26.075 0.085 ; - RECT 25.445 -0.085 25.615 0.085 ; - RECT 24.985 -0.085 25.155 0.085 ; - RECT 24.525 -0.085 24.695 0.085 ; - RECT 24.065 -0.085 24.235 0.085 ; - RECT 23.605 -0.085 23.775 0.085 ; - RECT 23.145 -0.085 23.315 0.085 ; - RECT 22.685 -0.085 22.855 0.085 ; - RECT 22.225 -0.085 22.395 0.085 ; - RECT 21.765 -0.085 21.935 0.085 ; - RECT 21.305 -0.085 21.475 0.085 ; - RECT 20.845 -0.085 21.015 0.085 ; - RECT 20.385 -0.085 20.555 0.085 ; - RECT 19.925 -0.085 20.095 0.085 ; - RECT 19.465 -0.085 19.635 0.085 ; - RECT 19.005 -0.085 19.175 0.085 ; - RECT 18.545 -0.085 18.715 0.085 ; - RECT 18.085 -0.085 18.255 0.085 ; - RECT 17.625 -0.085 17.795 0.085 ; - RECT 17.165 -0.085 17.335 0.085 ; - RECT 16.705 -0.085 16.875 0.085 ; - RECT 16.245 -0.085 16.415 0.085 ; - RECT 15.785 -0.085 15.955 0.085 ; - RECT 15.325 -0.085 15.495 0.085 ; - RECT 14.865 -0.085 15.035 0.085 ; - RECT 14.405 -0.085 14.575 0.085 ; - RECT 13.945 -0.085 14.115 0.085 ; - RECT 13.485 -0.085 13.655 0.085 ; - RECT 13.025 -0.085 13.195 0.085 ; - RECT 12.565 -0.085 12.735 0.085 ; - RECT 12.105 -0.085 12.275 0.085 ; - RECT 11.645 -0.085 11.815 0.085 ; - RECT 11.185 -0.085 11.355 0.085 ; - RECT 10.725 -0.085 10.895 0.085 ; - RECT 10.265 -0.085 10.435 0.085 ; - RECT 9.805 -0.085 9.975 0.085 ; - RECT 9.345 -0.085 9.515 0.085 ; - RECT 8.885 -0.085 9.055 0.085 ; - RECT 8.425 -0.085 8.595 0.085 ; - RECT 7.965 -0.085 8.135 0.085 ; - RECT 7.505 -0.085 7.675 0.085 ; - RECT 7.045 -0.085 7.215 0.085 ; - RECT 6.585 -0.085 6.755 0.085 ; - RECT 6.125 -0.085 6.295 0.085 ; - RECT 5.665 -0.085 5.835 0.085 ; - RECT 5.205 -0.085 5.375 0.085 ; - RECT 4.745 -0.085 4.915 0.085 ; - RECT 4.285 -0.085 4.455 0.085 ; - RECT 3.825 -0.085 3.995 0.085 ; - RECT 3.365 -0.085 3.535 0.085 ; - RECT 2.905 -0.085 3.075 0.085 ; - RECT 2.445 -0.085 2.615 0.085 ; - RECT 1.985 -0.085 2.155 0.085 ; - RECT 1.525 -0.085 1.695 0.085 ; - RECT 1.065 -0.085 1.235 0.085 ; - RECT 0.605 -0.085 0.775 0.085 ; - RECT 0.145 -0.085 0.315 0.085 ; - LAYER via ; - RECT 55.125 76.085 55.275 76.235 ; - RECT 25.685 76.085 25.835 76.235 ; - RECT 43.165 74.385 43.315 74.535 ; - RECT 33.505 74.385 33.655 74.535 ; - RECT 30.285 74.385 30.435 74.535 ; - RECT 57.425 1.625 57.575 1.775 ; - RECT 43.165 1.625 43.315 1.775 ; - RECT 33.505 1.625 33.655 1.775 ; - RECT 8.665 1.625 8.815 1.775 ; - RECT 55.125 -0.075 55.275 0.075 ; - RECT 25.685 -0.075 25.835 0.075 ; - LAYER via2 ; - RECT 55.1 76.06 55.3 76.26 ; - RECT 25.66 76.06 25.86 76.26 ; - RECT 1.28 65.18 1.48 65.38 ; - RECT 64.76 51.58 64.96 51.78 ; - RECT 1.28 51.58 1.48 51.78 ; - RECT 1.28 31.18 1.48 31.38 ; - RECT 1.28 14.18 1.48 14.38 ; - RECT 1.28 7.38 1.48 7.58 ; - RECT 1.28 4.66 1.48 4.86 ; - RECT 55.1 -0.1 55.3 0.1 ; - RECT 25.66 -0.1 25.86 0.1 ; - LAYER via3 ; - RECT 55.1 76.06 55.3 76.26 ; - RECT 25.66 76.06 25.86 76.26 ; - RECT 55.1 -0.1 55.3 0.1 ; - RECT 25.66 -0.1 25.86 0.1 ; - LAYER OVERLAP ; - POLYGON 0 0 0 76.16 66.24 76.16 66.24 0 ; - END -END cby_1__1_ - -END LIBRARY diff --git a/FPGA22_HIER_SKY_PNR/modules/lef/cby_2__1__icv_in_design.lef b/FPGA22_HIER_SKY_PNR/modules/lef/cby_2__1__icv_in_design.lef deleted file mode 100644 index 4680740..0000000 --- a/FPGA22_HIER_SKY_PNR/modules/lef/cby_2__1__icv_in_design.lef +++ /dev/null @@ -1,1811 +0,0 @@ -VERSION 5.7 ; -BUSBITCHARS "[]" ; - -UNITS - DATABASE MICRONS 1000 ; -END UNITS - -MANUFACTURINGGRID 0.005 ; - -LAYER li1 - TYPE ROUTING ; - DIRECTION VERTICAL ; - PITCH 0.46 ; - WIDTH 0.17 ; -END li1 - -LAYER mcon - TYPE CUT ; -END mcon - -LAYER met1 - TYPE ROUTING ; - DIRECTION HORIZONTAL ; - PITCH 0.34 ; - WIDTH 0.14 ; -END met1 - -LAYER via - TYPE CUT ; -END via - -LAYER met2 - TYPE ROUTING ; - DIRECTION VERTICAL ; - PITCH 0.46 ; - WIDTH 0.14 ; -END met2 - -LAYER via2 - TYPE CUT ; -END via2 - -LAYER met3 - TYPE ROUTING ; - DIRECTION HORIZONTAL ; - PITCH 0.68 ; - WIDTH 0.3 ; -END met3 - -LAYER via3 - TYPE CUT ; -END via3 - -LAYER met4 - TYPE ROUTING ; - DIRECTION VERTICAL ; - PITCH 0.92 ; - WIDTH 0.3 ; -END met4 - -LAYER via4 - TYPE CUT ; -END via4 - -LAYER met5 - TYPE ROUTING ; - DIRECTION HORIZONTAL ; - PITCH 3.4 ; - WIDTH 1.6 ; -END met5 - -LAYER nwell - TYPE MASTERSLICE ; -END nwell - -LAYER pwell - TYPE MASTERSLICE ; -END pwell - -LAYER OVERLAP - TYPE OVERLAP ; -END OVERLAP - -VIA L1M1_PR - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.145 -0.115 0.145 0.115 ; -END L1M1_PR - -VIA L1M1_PR_R - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.115 -0.145 0.115 0.145 ; -END L1M1_PR_R - -VIA L1M1_PR_M - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.115 -0.145 0.115 0.145 ; -END L1M1_PR_M - -VIA L1M1_PR_MR - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.145 -0.115 0.145 0.115 ; -END L1M1_PR_MR - -VIA L1M1_PR_C - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.145 -0.145 0.145 0.145 ; -END L1M1_PR_C - -VIA M1M2_PR - LAYER met1 ; - RECT -0.16 -0.13 0.16 0.13 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.13 -0.16 0.13 0.16 ; -END M1M2_PR - -VIA M1M2_PR_Enc - LAYER met1 ; - RECT -0.16 -0.13 0.16 0.13 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.16 -0.13 0.16 0.13 ; -END M1M2_PR_Enc - -VIA M1M2_PR_R - LAYER met1 ; - RECT -0.13 -0.16 0.13 0.16 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.16 -0.13 0.16 0.13 ; -END M1M2_PR_R - -VIA M1M2_PR_R_Enc - LAYER met1 ; - RECT -0.13 -0.16 0.13 0.16 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.13 -0.16 0.13 0.16 ; -END M1M2_PR_R_Enc - -VIA M1M2_PR_M - LAYER met1 ; - RECT -0.16 -0.13 0.16 0.13 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.16 -0.13 0.16 0.13 ; -END M1M2_PR_M - -VIA M1M2_PR_M_Enc - LAYER met1 ; - RECT -0.16 -0.13 0.16 0.13 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.13 -0.16 0.13 0.16 ; -END M1M2_PR_M_Enc - -VIA M1M2_PR_MR - LAYER met1 ; - RECT -0.13 -0.16 0.13 0.16 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.13 -0.16 0.13 0.16 ; -END M1M2_PR_MR - -VIA M1M2_PR_MR_Enc - LAYER met1 ; - RECT -0.13 -0.16 0.13 0.16 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.16 -0.13 0.16 0.13 ; -END M1M2_PR_MR_Enc - -VIA M1M2_PR_C - LAYER met1 ; - RECT -0.16 -0.16 0.16 0.16 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.16 -0.16 0.16 0.16 ; -END M1M2_PR_C - -VIA M2M3_PR - LAYER met2 ; - RECT -0.14 -0.185 0.14 0.185 ; - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met3 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M2M3_PR - -VIA M2M3_PR_R - LAYER met2 ; - RECT -0.185 -0.14 0.185 0.14 ; - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met3 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M2M3_PR_R - -VIA M2M3_PR_M - LAYER met2 ; - RECT -0.14 -0.185 0.14 0.185 ; - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met3 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M2M3_PR_M - -VIA M2M3_PR_MR - LAYER met2 ; - RECT -0.185 -0.14 0.185 0.14 ; - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met3 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M2M3_PR_MR - -VIA M2M3_PR_C - LAYER met2 ; - RECT -0.185 -0.185 0.185 0.185 ; - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met3 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M2M3_PR_C - -VIA M3M4_PR - LAYER met3 ; - RECT -0.19 -0.16 0.19 0.16 ; - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR - -VIA M3M4_PR_R - LAYER met3 ; - RECT -0.16 -0.19 0.16 0.19 ; - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR_R - -VIA M3M4_PR_M - LAYER met3 ; - RECT -0.19 -0.16 0.19 0.16 ; - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR_M - -VIA M3M4_PR_MR - LAYER met3 ; - RECT -0.16 -0.19 0.16 0.19 ; - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR_MR - -VIA M3M4_PR_C - LAYER met3 ; - RECT -0.19 -0.19 0.19 0.19 ; - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR_C - -VIA M4M5_PR - LAYER met4 ; - RECT -0.59 -0.59 0.59 0.59 ; - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - LAYER met5 ; - RECT -0.71 -0.71 0.71 0.71 ; -END M4M5_PR - -VIA M4M5_PR_R - LAYER met4 ; - RECT -0.59 -0.59 0.59 0.59 ; - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - LAYER met5 ; - RECT -0.71 -0.71 0.71 0.71 ; -END M4M5_PR_R - -VIA M4M5_PR_M - LAYER met4 ; - RECT -0.59 -0.59 0.59 0.59 ; - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - LAYER met5 ; - RECT -0.71 -0.71 0.71 0.71 ; -END M4M5_PR_M - -VIA M4M5_PR_MR - LAYER met4 ; - RECT -0.59 -0.59 0.59 0.59 ; - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - LAYER met5 ; - RECT -0.71 -0.71 0.71 0.71 ; -END M4M5_PR_MR - -VIA M4M5_PR_C - LAYER met4 ; - RECT -0.59 -0.59 0.59 0.59 ; - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - LAYER met5 ; - RECT -0.71 -0.71 0.71 0.71 ; -END M4M5_PR_C - -SITE unit - CLASS CORE ; - SYMMETRY Y ; - SIZE 0.46 BY 2.72 ; -END unit - -SITE unithddbl - CLASS CORE ; - SIZE 0.46 BY 5.44 ; -END unithddbl - -MACRO cby_2__1_ - CLASS BLOCK ; - ORIGIN 0 0 ; - SIZE 66.24 BY 76.16 ; - SYMMETRY X Y ; - PIN prog_clk[0] - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER met3 ; - RECT 0 10.73 1.38 11.03 ; - END - END prog_clk[0] - PIN chany_bottom_in[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 11.89 0 12.03 1.36 ; - END - END chany_bottom_in[0] - PIN chany_bottom_in[1] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 24.77 0 24.91 1.36 ; - END - END chany_bottom_in[1] - PIN chany_bottom_in[2] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 38.11 0 38.25 1.36 ; - END - END chany_bottom_in[2] - PIN chany_bottom_in[3] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 10.97 0 11.11 1.36 ; - END - END chany_bottom_in[3] - PIN chany_bottom_in[4] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 31.67 0 31.81 1.36 ; - END - END chany_bottom_in[4] - PIN chany_bottom_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 20.17 0 20.31 1.36 ; - END - END chany_bottom_in[5] - PIN chany_bottom_in[6] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 37.19 0 37.33 1.36 ; - END - END chany_bottom_in[6] - PIN chany_bottom_in[7] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 16.49 0 16.63 1.36 ; - END - END chany_bottom_in[7] - PIN chany_bottom_in[8] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 34.43 0 34.57 1.36 ; - END - END chany_bottom_in[8] - PIN chany_bottom_in[9] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 13.73 0 13.87 1.36 ; - END - END chany_bottom_in[9] - PIN chany_bottom_in[10] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 40.87 0 41.01 1.36 ; - END - END chany_bottom_in[10] - PIN chany_bottom_in[11] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 14.65 0 14.79 1.36 ; - END - END chany_bottom_in[11] - PIN chany_bottom_in[12] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 36.27 0 36.41 1.36 ; - END - END chany_bottom_in[12] - PIN chany_bottom_in[13] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 15.57 0 15.71 1.36 ; - END - END chany_bottom_in[13] - PIN chany_bottom_in[14] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 46.39 0 46.53 1.36 ; - END - END chany_bottom_in[14] - PIN chany_bottom_in[15] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 22.01 0 22.15 1.36 ; - END - END chany_bottom_in[15] - PIN chany_bottom_in[16] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 56.05 0 56.19 1.36 ; - END - END chany_bottom_in[16] - PIN chany_bottom_in[17] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 18.79 0 18.93 1.36 ; - END - END chany_bottom_in[17] - PIN chany_bottom_in[18] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 44.55 0 44.69 1.36 ; - END - END chany_bottom_in[18] - PIN chany_bottom_in[19] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 6.37 0 6.51 1.36 ; - END - END chany_bottom_in[19] - PIN chany_top_in[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 38.11 74.8 38.25 76.16 ; - END - END chany_top_in[0] - PIN chany_top_in[1] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 32.97 74.8 33.27 76.16 ; - END - END chany_top_in[1] - PIN chany_top_in[2] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 56.05 74.8 56.19 76.16 ; - END - END chany_top_in[2] - PIN chany_top_in[3] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 15.11 74.8 15.25 76.16 ; - END - END chany_top_in[3] - PIN chany_top_in[4] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 11.43 74.8 11.57 76.16 ; - END - END chany_top_in[4] - PIN chany_top_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 16.03 74.8 16.17 76.16 ; - END - END chany_top_in[5] - PIN chany_top_in[6] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 40.41 74.8 40.55 76.16 ; - END - END chany_top_in[6] - PIN chany_top_in[7] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 22.01 74.8 22.15 76.16 ; - END - END chany_top_in[7] - PIN chany_top_in[8] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 31.67 74.8 31.81 76.16 ; - END - END chany_top_in[8] - PIN chany_top_in[9] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 12.35 74.8 12.49 76.16 ; - END - END chany_top_in[9] - PIN chany_top_in[10] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 45.93 74.8 46.07 76.16 ; - END - END chany_top_in[10] - PIN chany_top_in[11] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 8.21 74.8 8.35 76.16 ; - END - END chany_top_in[11] - PIN chany_top_in[12] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 33.05 74.8 33.19 76.16 ; - END - END chany_top_in[12] - PIN chany_top_in[13] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 6.37 74.8 6.51 76.16 ; - END - END chany_top_in[13] - PIN chany_top_in[14] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 41.33 74.8 41.47 76.16 ; - END - END chany_top_in[14] - PIN chany_top_in[15] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 23.39 74.8 23.53 76.16 ; - END - END chany_top_in[15] - PIN chany_top_in[16] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 26.61 74.8 26.75 76.16 ; - END - END chany_top_in[16] - PIN chany_top_in[17] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 19.71 74.8 19.85 76.16 ; - END - END chany_top_in[17] - PIN chany_top_in[18] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 45.01 74.8 45.15 76.16 ; - END - END chany_top_in[18] - PIN chany_top_in[19] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 5.45 74.8 5.59 76.16 ; - END - END chany_top_in[19] - PIN ccff_head[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 65.13 1.38 65.43 ; - END - END ccff_head[0] - PIN chany_bottom_out[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 33.51 0 33.65 1.36 ; - END - END chany_bottom_out[0] - PIN chany_bottom_out[1] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 37.57 0 37.87 1.36 ; - END - END chany_bottom_out[1] - PIN chany_bottom_out[2] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 46.77 0 47.07 1.36 ; - END - END chany_bottom_out[2] - PIN chany_bottom_out[3] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 26.61 0 26.75 1.36 ; - END - END chany_bottom_out[3] - PIN chany_bottom_out[4] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 41.79 0 41.93 1.36 ; - END - END chany_bottom_out[4] - PIN chany_bottom_out[5] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 39.03 0 39.17 1.36 ; - END - END chany_bottom_out[5] - PIN chany_bottom_out[6] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 47.31 0 47.45 1.36 ; - END - END chany_bottom_out[6] - PIN chany_bottom_out[7] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 22.93 0 23.07 1.36 ; - END - END chany_bottom_out[7] - PIN chany_bottom_out[8] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 30.29 0 30.43 1.36 ; - END - END chany_bottom_out[8] - PIN chany_bottom_out[9] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 33.89 0 34.19 1.36 ; - END - END chany_bottom_out[9] - PIN chany_bottom_out[10] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 27.45 0 27.75 1.36 ; - END - END chany_bottom_out[10] - PIN chany_bottom_out[11] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 21.09 0 21.23 1.36 ; - END - END chany_bottom_out[11] - PIN chany_bottom_out[12] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 23.85 0 23.99 1.36 ; - END - END chany_bottom_out[12] - PIN chany_bottom_out[13] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 17.87 0 18.01 1.36 ; - END - END chany_bottom_out[13] - PIN chany_bottom_out[14] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 43.63 0 43.77 1.36 ; - END - END chany_bottom_out[14] - PIN chany_bottom_out[15] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 35.35 0 35.49 1.36 ; - END - END chany_bottom_out[15] - PIN chany_bottom_out[16] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 42.71 0 42.85 1.36 ; - END - END chany_bottom_out[16] - PIN chany_bottom_out[17] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 48.23 0 48.37 1.36 ; - END - END chany_bottom_out[17] - PIN chany_bottom_out[18] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 45.47 0 45.61 1.36 ; - END - END chany_bottom_out[18] - PIN chany_bottom_out[19] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 39.95 0 40.09 1.36 ; - END - END chany_bottom_out[19] - PIN chany_top_out[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 29.83 74.8 29.97 76.16 ; - END - END chany_top_out[0] - PIN chany_top_out[1] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 24.77 74.8 24.91 76.16 ; - END - END chany_top_out[1] - PIN chany_top_out[2] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 31.13 74.8 31.43 76.16 ; - END - END chany_top_out[2] - PIN chany_top_out[3] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 21.09 74.8 21.23 76.16 ; - END - END chany_top_out[3] - PIN chany_top_out[4] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 28.45 74.8 28.59 76.16 ; - END - END chany_top_out[4] - PIN chany_top_out[5] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 27.53 74.8 27.67 76.16 ; - END - END chany_top_out[5] - PIN chany_top_out[6] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 43.63 74.8 43.77 76.16 ; - END - END chany_top_out[6] - PIN chany_top_out[7] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 37.19 74.8 37.33 76.16 ; - END - END chany_top_out[7] - PIN chany_top_out[8] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 46.85 74.8 46.99 76.16 ; - END - END chany_top_out[8] - PIN chany_top_out[9] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 39.03 74.8 39.17 76.16 ; - END - END chany_top_out[9] - PIN chany_top_out[10] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 14.19 74.8 14.33 76.16 ; - END - END chany_top_out[10] - PIN chany_top_out[11] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 36.27 74.8 36.41 76.16 ; - END - END chany_top_out[11] - PIN chany_top_out[12] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 16.95 74.8 17.09 76.16 ; - END - END chany_top_out[12] - PIN chany_top_out[13] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 18.33 74.8 18.47 76.16 ; - END - END chany_top_out[13] - PIN chany_top_out[14] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 30.75 74.8 30.89 76.16 ; - END - END chany_top_out[14] - PIN chany_top_out[15] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 34.43 74.8 34.57 76.16 ; - END - END chany_top_out[15] - PIN chany_top_out[16] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 42.71 74.8 42.85 76.16 ; - END - END chany_top_out[16] - PIN chany_top_out[17] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 47.77 74.8 47.91 76.16 ; - END - END chany_top_out[17] - PIN chany_top_out[18] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 48.69 74.8 48.83 76.16 ; - END - END chany_top_out[18] - PIN chany_top_out[19] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 35.35 74.8 35.49 76.16 ; - END - END chany_top_out[19] - PIN right_grid_pin_0_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 14.81 66.24 15.11 ; - END - END right_grid_pin_0_[0] - PIN left_grid_pin_16_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 27.05 1.38 27.35 ; - END - END left_grid_pin_16_[0] - PIN left_grid_pin_17_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 32.49 1.38 32.79 ; - END - END left_grid_pin_17_[0] - PIN left_grid_pin_18_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 4.61 1.38 4.91 ; - END - END left_grid_pin_18_[0] - PIN left_grid_pin_19_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 31.13 1.38 31.43 ; - END - END left_grid_pin_19_[0] - PIN left_grid_pin_20_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 8.69 1.38 8.99 ; - END - END left_grid_pin_20_[0] - PIN left_grid_pin_21_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 5.97 1.38 6.27 ; - END - END left_grid_pin_21_[0] - PIN left_grid_pin_22_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 7.33 1.38 7.63 ; - END - END left_grid_pin_22_[0] - PIN left_grid_pin_23_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 12.77 1.38 13.07 ; - END - END left_grid_pin_23_[0] - PIN left_grid_pin_24_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 25.69 1.38 25.99 ; - END - END left_grid_pin_24_[0] - PIN left_grid_pin_25_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 24.33 1.38 24.63 ; - END - END left_grid_pin_25_[0] - PIN left_grid_pin_26_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 14.13 1.38 14.43 ; - END - END left_grid_pin_26_[0] - PIN left_grid_pin_27_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 52.89 1.38 53.19 ; - END - END left_grid_pin_27_[0] - PIN left_grid_pin_28_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 50.17 1.38 50.47 ; - END - END left_grid_pin_28_[0] - PIN left_grid_pin_29_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 29.77 1.38 30.07 ; - END - END left_grid_pin_29_[0] - PIN left_grid_pin_30_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 28.41 1.38 28.71 ; - END - END left_grid_pin_30_[0] - PIN left_grid_pin_31_[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 51.53 1.38 51.83 ; - END - END left_grid_pin_31_[0] - PIN ccff_tail[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 12.81 0 12.95 1.36 ; - END - END ccff_tail[0] - PIN gfpga_pad_EMBEDDED_IO_SOC_IN[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 38.61 66.24 38.91 ; - END - END gfpga_pad_EMBEDDED_IO_SOC_IN[0] - PIN gfpga_pad_EMBEDDED_IO_SOC_OUT[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 18.89 66.24 19.19 ; - END - END gfpga_pad_EMBEDDED_IO_SOC_OUT[0] - PIN gfpga_pad_EMBEDDED_IO_SOC_DIR[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 3.25 66.24 3.55 ; - END - END gfpga_pad_EMBEDDED_IO_SOC_DIR[0] - PIN left_width_0_height_0__pin_0_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 64.86 16.17 66.24 16.47 ; - END - END left_width_0_height_0__pin_0_[0] - PIN left_width_0_height_0__pin_1_upper[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 13.27 74.8 13.41 76.16 ; - END - END left_width_0_height_0__pin_1_upper[0] - PIN left_width_0_height_0__pin_1_lower[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 28.45 0 28.59 1.36 ; - END - END left_width_0_height_0__pin_1_lower[0] - PIN VDD - DIRECTION INPUT ; - USE POWER ; - PORT - LAYER met5 ; - RECT 0 5.88 3.2 9.08 ; - RECT 63.04 5.88 66.24 9.08 ; - RECT 0 46.68 3.2 49.88 ; - RECT 63.04 46.68 66.24 49.88 ; - LAYER met1 ; - RECT 0 2.48 0.48 2.96 ; - RECT 65.76 2.48 66.24 2.96 ; - RECT 0 7.92 0.48 8.4 ; - RECT 65.76 7.92 66.24 8.4 ; - RECT 0 13.36 0.48 13.84 ; - RECT 65.76 13.36 66.24 13.84 ; - RECT 0 18.8 0.48 19.28 ; - RECT 65.76 18.8 66.24 19.28 ; - RECT 0 24.24 0.48 24.72 ; - RECT 65.76 24.24 66.24 24.72 ; - RECT 0 29.68 0.48 30.16 ; - RECT 65.76 29.68 66.24 30.16 ; - RECT 0 35.12 0.48 35.6 ; - RECT 65.76 35.12 66.24 35.6 ; - RECT 0 40.56 0.48 41.04 ; - RECT 65.76 40.56 66.24 41.04 ; - RECT 0 46 0.48 46.48 ; - RECT 65.76 46 66.24 46.48 ; - RECT 0 51.44 0.48 51.92 ; - RECT 65.76 51.44 66.24 51.92 ; - RECT 0 56.88 0.48 57.36 ; - RECT 65.76 56.88 66.24 57.36 ; - RECT 0 62.32 0.48 62.8 ; - RECT 65.76 62.32 66.24 62.8 ; - RECT 0 67.76 0.48 68.24 ; - RECT 65.76 67.76 66.24 68.24 ; - RECT 0 73.2 0.48 73.68 ; - RECT 65.76 73.2 66.24 73.68 ; - LAYER met4 ; - RECT 10.74 0 11.34 0.6 ; - RECT 40.18 0 40.78 0.6 ; - RECT 10.74 75.56 11.34 76.16 ; - RECT 40.18 75.56 40.78 76.16 ; - END - END VDD - PIN VSS - DIRECTION INPUT ; - USE GROUND ; - PORT - LAYER met5 ; - RECT 0 26.28 3.2 29.48 ; - RECT 63.04 26.28 66.24 29.48 ; - RECT 0 67.08 3.2 70.28 ; - RECT 63.04 67.08 66.24 70.28 ; - LAYER met1 ; - RECT 0 0 66.24 0.24 ; - RECT 0 5.2 0.48 5.68 ; - RECT 65.76 5.2 66.24 5.68 ; - RECT 0 10.64 0.48 11.12 ; - RECT 65.76 10.64 66.24 11.12 ; - RECT 0 16.08 0.48 16.56 ; - RECT 65.76 16.08 66.24 16.56 ; - RECT 0 21.52 0.48 22 ; - RECT 65.76 21.52 66.24 22 ; - RECT 0 26.96 0.48 27.44 ; - RECT 65.76 26.96 66.24 27.44 ; - RECT 0 32.4 0.48 32.88 ; - RECT 65.76 32.4 66.24 32.88 ; - RECT 0 37.84 0.48 38.32 ; - RECT 65.76 37.84 66.24 38.32 ; - RECT 0 43.28 0.48 43.76 ; - RECT 65.76 43.28 66.24 43.76 ; - RECT 0 48.72 0.48 49.2 ; - RECT 65.76 48.72 66.24 49.2 ; - RECT 0 54.16 0.48 54.64 ; - RECT 65.76 54.16 66.24 54.64 ; - RECT 0 59.6 0.48 60.08 ; - RECT 65.76 59.6 66.24 60.08 ; - RECT 0 65.04 0.48 65.52 ; - RECT 65.76 65.04 66.24 65.52 ; - RECT 0 70.48 0.48 70.96 ; - RECT 65.76 70.48 66.24 70.96 ; - RECT 0 75.92 66.24 76.16 ; - LAYER met4 ; - RECT 25.46 0 26.06 0.6 ; - RECT 54.9 0 55.5 0.6 ; - RECT 25.46 75.56 26.06 76.16 ; - RECT 54.9 75.56 55.5 76.16 ; - END - END VSS - OBS - LAYER li1 ; - RECT 0 76.075 66.24 76.245 ; - RECT 65.32 73.355 66.24 73.525 ; - RECT 0 73.355 3.68 73.525 ; - RECT 65.32 70.635 66.24 70.805 ; - RECT 0 70.635 1.84 70.805 ; - RECT 65.32 67.915 66.24 68.085 ; - RECT 0 67.915 1.84 68.085 ; - RECT 65.32 65.195 66.24 65.365 ; - RECT 0 65.195 1.84 65.365 ; - RECT 65.32 62.475 66.24 62.645 ; - RECT 0 62.475 1.84 62.645 ; - RECT 65.32 59.755 66.24 59.925 ; - RECT 0 59.755 1.84 59.925 ; - RECT 65.32 57.035 66.24 57.205 ; - RECT 0 57.035 1.84 57.205 ; - RECT 65.32 54.315 66.24 54.485 ; - RECT 0 54.315 1.84 54.485 ; - RECT 65.32 51.595 66.24 51.765 ; - RECT 0 51.595 3.68 51.765 ; - RECT 65.32 48.875 66.24 49.045 ; - RECT 0 48.875 3.68 49.045 ; - RECT 65.32 46.155 66.24 46.325 ; - RECT 0 46.155 1.84 46.325 ; - RECT 65.32 43.435 66.24 43.605 ; - RECT 0 43.435 3.68 43.605 ; - RECT 65.32 40.715 66.24 40.885 ; - RECT 0 40.715 3.68 40.885 ; - RECT 65.32 37.995 66.24 38.165 ; - RECT 0 37.995 1.84 38.165 ; - RECT 65.32 35.275 66.24 35.445 ; - RECT 0 35.275 1.84 35.445 ; - RECT 65.32 32.555 66.24 32.725 ; - RECT 0 32.555 1.84 32.725 ; - RECT 65.32 29.835 66.24 30.005 ; - RECT 0 29.835 3.68 30.005 ; - RECT 65.32 27.115 66.24 27.285 ; - RECT 0 27.115 3.68 27.285 ; - RECT 65.32 24.395 66.24 24.565 ; - RECT 0 24.395 1.84 24.565 ; - RECT 65.32 21.675 66.24 21.845 ; - RECT 0 21.675 1.84 21.845 ; - RECT 65.32 18.955 66.24 19.125 ; - RECT 0 18.955 1.84 19.125 ; - RECT 65.32 16.235 66.24 16.405 ; - RECT 0 16.235 1.84 16.405 ; - RECT 65.32 13.515 66.24 13.685 ; - RECT 0 13.515 1.84 13.685 ; - RECT 65.32 10.795 66.24 10.965 ; - RECT 0 10.795 1.84 10.965 ; - RECT 65.78 8.075 66.24 8.245 ; - RECT 0 8.075 1.84 8.245 ; - RECT 65.32 5.355 66.24 5.525 ; - RECT 0 5.355 3.68 5.525 ; - RECT 65.32 2.635 66.24 2.805 ; - RECT 0 2.635 3.68 2.805 ; - RECT 0 -0.085 66.24 0.085 ; - LAYER met3 ; - POLYGON 55.365 76.325 55.365 76.32 55.58 76.32 55.58 76 55.365 76 55.365 75.995 55.035 75.995 55.035 76 54.82 76 54.82 76.32 55.035 76.32 55.035 76.325 ; - POLYGON 25.925 76.325 25.925 76.32 26.14 76.32 26.14 76 25.925 76 25.925 75.995 25.595 75.995 25.595 76 25.38 76 25.38 76.32 25.595 76.32 25.595 76.325 ; - POLYGON 55.365 0.165 55.365 0.16 55.58 0.16 55.58 -0.16 55.365 -0.16 55.365 -0.165 55.035 -0.165 55.035 -0.16 54.82 -0.16 54.82 0.16 55.035 0.16 55.035 0.165 ; - POLYGON 25.925 0.165 25.925 0.16 26.14 0.16 26.14 -0.16 25.925 -0.16 25.925 -0.165 25.595 -0.165 25.595 -0.16 25.38 -0.16 25.38 0.16 25.595 0.16 25.595 0.165 ; - POLYGON 65.84 75.76 65.84 39.31 64.46 39.31 64.46 38.21 65.84 38.21 65.84 19.59 64.46 19.59 64.46 18.49 65.84 18.49 65.84 16.87 64.46 16.87 64.46 15.77 65.84 15.77 65.84 15.51 64.46 15.51 64.46 14.41 65.84 14.41 65.84 3.95 64.46 3.95 64.46 2.85 65.84 2.85 65.84 0.4 0.4 0.4 0.4 4.21 1.78 4.21 1.78 5.31 0.4 5.31 0.4 5.57 1.78 5.57 1.78 6.67 0.4 6.67 0.4 6.93 1.78 6.93 1.78 8.03 0.4 8.03 0.4 8.29 1.78 8.29 1.78 9.39 0.4 9.39 0.4 10.33 1.78 10.33 1.78 11.43 0.4 11.43 0.4 12.37 1.78 12.37 1.78 13.47 0.4 13.47 0.4 13.73 1.78 13.73 1.78 14.83 0.4 14.83 0.4 23.93 1.78 23.93 1.78 25.03 0.4 25.03 0.4 25.29 1.78 25.29 1.78 26.39 0.4 26.39 0.4 26.65 1.78 26.65 1.78 27.75 0.4 27.75 0.4 28.01 1.78 28.01 1.78 29.11 0.4 29.11 0.4 29.37 1.78 29.37 1.78 30.47 0.4 30.47 0.4 30.73 1.78 30.73 1.78 31.83 0.4 31.83 0.4 32.09 1.78 32.09 1.78 33.19 0.4 33.19 0.4 49.77 1.78 49.77 1.78 50.87 0.4 50.87 0.4 51.13 1.78 51.13 1.78 52.23 0.4 52.23 0.4 52.49 1.78 52.49 1.78 53.59 0.4 53.59 0.4 64.73 1.78 64.73 1.78 65.83 0.4 65.83 0.4 75.76 ; - LAYER met2 ; - RECT 55.06 75.975 55.34 76.345 ; - RECT 25.62 75.975 25.9 76.345 ; - RECT 40.81 74.3 41.07 74.62 ; - RECT 35.75 74.3 36.01 74.62 ; - RECT 33.45 74.3 33.71 74.62 ; - RECT 43.11 1.54 43.37 1.86 ; - RECT 16.89 1.54 17.15 1.86 ; - RECT 55.06 -0.185 55.34 0.185 ; - RECT 25.62 -0.185 25.9 0.185 ; - POLYGON 65.96 75.88 65.96 0.28 56.47 0.28 56.47 1.64 55.77 1.64 55.77 0.28 48.65 0.28 48.65 1.64 47.95 1.64 47.95 0.28 47.73 0.28 47.73 1.64 47.03 1.64 47.03 0.28 46.81 0.28 46.81 1.64 46.11 1.64 46.11 0.28 45.89 0.28 45.89 1.64 45.19 1.64 45.19 0.28 44.97 0.28 44.97 1.64 44.27 1.64 44.27 0.28 44.05 0.28 44.05 1.64 43.35 1.64 43.35 0.28 43.13 0.28 43.13 1.64 42.43 1.64 42.43 0.28 42.21 0.28 42.21 1.64 41.51 1.64 41.51 0.28 41.29 0.28 41.29 1.64 40.59 1.64 40.59 0.28 40.37 0.28 40.37 1.64 39.67 1.64 39.67 0.28 39.45 0.28 39.45 1.64 38.75 1.64 38.75 0.28 38.53 0.28 38.53 1.64 37.83 1.64 37.83 0.28 37.61 0.28 37.61 1.64 36.91 1.64 36.91 0.28 36.69 0.28 36.69 1.64 35.99 1.64 35.99 0.28 35.77 0.28 35.77 1.64 35.07 1.64 35.07 0.28 34.85 0.28 34.85 1.64 34.15 1.64 34.15 0.28 33.93 0.28 33.93 1.64 33.23 1.64 33.23 0.28 32.09 0.28 32.09 1.64 31.39 1.64 31.39 0.28 30.71 0.28 30.71 1.64 30.01 1.64 30.01 0.28 28.87 0.28 28.87 1.64 28.17 1.64 28.17 0.28 27.03 0.28 27.03 1.64 26.33 1.64 26.33 0.28 25.19 0.28 25.19 1.64 24.49 1.64 24.49 0.28 24.27 0.28 24.27 1.64 23.57 1.64 23.57 0.28 23.35 0.28 23.35 1.64 22.65 1.64 22.65 0.28 22.43 0.28 22.43 1.64 21.73 1.64 21.73 0.28 21.51 0.28 21.51 1.64 20.81 1.64 20.81 0.28 20.59 0.28 20.59 1.64 19.89 1.64 19.89 0.28 19.21 0.28 19.21 1.64 18.51 1.64 18.51 0.28 18.29 0.28 18.29 1.64 17.59 1.64 17.59 0.28 16.91 0.28 16.91 1.64 16.21 1.64 16.21 0.28 15.99 0.28 15.99 1.64 15.29 1.64 15.29 0.28 15.07 0.28 15.07 1.64 14.37 1.64 14.37 0.28 14.15 0.28 14.15 1.64 13.45 1.64 13.45 0.28 13.23 0.28 13.23 1.64 12.53 1.64 12.53 0.28 12.31 0.28 12.31 1.64 11.61 1.64 11.61 0.28 11.39 0.28 11.39 1.64 10.69 1.64 10.69 0.28 6.79 0.28 6.79 1.64 6.09 1.64 6.09 0.28 0.28 0.28 0.28 75.88 5.17 75.88 5.17 74.52 5.87 74.52 5.87 75.88 6.09 75.88 6.09 74.52 6.79 74.52 6.79 75.88 7.93 75.88 7.93 74.52 8.63 74.52 8.63 75.88 11.15 75.88 11.15 74.52 11.85 74.52 11.85 75.88 12.07 75.88 12.07 74.52 12.77 74.52 12.77 75.88 12.99 75.88 12.99 74.52 13.69 74.52 13.69 75.88 13.91 75.88 13.91 74.52 14.61 74.52 14.61 75.88 14.83 75.88 14.83 74.52 15.53 74.52 15.53 75.88 15.75 75.88 15.75 74.52 16.45 74.52 16.45 75.88 16.67 75.88 16.67 74.52 17.37 74.52 17.37 75.88 18.05 75.88 18.05 74.52 18.75 74.52 18.75 75.88 19.43 75.88 19.43 74.52 20.13 74.52 20.13 75.88 20.81 75.88 20.81 74.52 21.51 74.52 21.51 75.88 21.73 75.88 21.73 74.52 22.43 74.52 22.43 75.88 23.11 75.88 23.11 74.52 23.81 74.52 23.81 75.88 24.49 75.88 24.49 74.52 25.19 74.52 25.19 75.88 26.33 75.88 26.33 74.52 27.03 74.52 27.03 75.88 27.25 75.88 27.25 74.52 27.95 74.52 27.95 75.88 28.17 75.88 28.17 74.52 28.87 74.52 28.87 75.88 29.55 75.88 29.55 74.52 30.25 74.52 30.25 75.88 30.47 75.88 30.47 74.52 31.17 74.52 31.17 75.88 31.39 75.88 31.39 74.52 32.09 74.52 32.09 75.88 32.77 75.88 32.77 74.52 33.47 74.52 33.47 75.88 34.15 75.88 34.15 74.52 34.85 74.52 34.85 75.88 35.07 75.88 35.07 74.52 35.77 74.52 35.77 75.88 35.99 75.88 35.99 74.52 36.69 74.52 36.69 75.88 36.91 75.88 36.91 74.52 37.61 74.52 37.61 75.88 37.83 75.88 37.83 74.52 38.53 74.52 38.53 75.88 38.75 75.88 38.75 74.52 39.45 74.52 39.45 75.88 40.13 75.88 40.13 74.52 40.83 74.52 40.83 75.88 41.05 75.88 41.05 74.52 41.75 74.52 41.75 75.88 42.43 75.88 42.43 74.52 43.13 74.52 43.13 75.88 43.35 75.88 43.35 74.52 44.05 74.52 44.05 75.88 44.73 75.88 44.73 74.52 45.43 74.52 45.43 75.88 45.65 75.88 45.65 74.52 46.35 74.52 46.35 75.88 46.57 75.88 46.57 74.52 47.27 74.52 47.27 75.88 47.49 75.88 47.49 74.52 48.19 74.52 48.19 75.88 48.41 75.88 48.41 74.52 49.11 74.52 49.11 75.88 55.77 75.88 55.77 74.52 56.47 74.52 56.47 75.88 ; - LAYER met4 ; - POLYGON 65.84 75.76 65.84 0.4 55.9 0.4 55.9 1 54.5 1 54.5 0.4 47.47 0.4 47.47 1.76 46.37 1.76 46.37 0.4 41.18 0.4 41.18 1 39.78 1 39.78 0.4 38.27 0.4 38.27 1.76 37.17 1.76 37.17 0.4 34.59 0.4 34.59 1.76 33.49 1.76 33.49 0.4 28.15 0.4 28.15 1.76 27.05 1.76 27.05 0.4 26.46 0.4 26.46 1 25.06 1 25.06 0.4 11.74 0.4 11.74 1 10.34 1 10.34 0.4 0.4 0.4 0.4 75.76 10.34 75.76 10.34 75.16 11.74 75.16 11.74 75.76 25.06 75.76 25.06 75.16 26.46 75.16 26.46 75.76 30.73 75.76 30.73 74.4 31.83 74.4 31.83 75.76 32.57 75.76 32.57 74.4 33.67 74.4 33.67 75.76 39.78 75.76 39.78 75.16 41.18 75.16 41.18 75.76 54.5 75.76 54.5 75.16 55.9 75.16 55.9 75.76 ; - LAYER met1 ; - POLYGON 65.96 75.64 65.96 73.96 65.48 73.96 65.48 72.92 65.96 72.92 65.96 71.24 65.48 71.24 65.48 70.2 65.96 70.2 65.96 68.52 65.48 68.52 65.48 67.48 65.96 67.48 65.96 65.8 65.48 65.8 65.48 64.76 65.96 64.76 65.96 63.08 65.48 63.08 65.48 62.04 65.96 62.04 65.96 60.36 65.48 60.36 65.48 59.32 65.96 59.32 65.96 57.64 65.48 57.64 65.48 56.6 65.96 56.6 65.96 54.92 65.48 54.92 65.48 53.88 65.96 53.88 65.96 52.2 65.48 52.2 65.48 51.16 65.96 51.16 65.96 49.48 65.48 49.48 65.48 48.44 65.96 48.44 65.96 46.76 65.48 46.76 65.48 45.72 65.96 45.72 65.96 44.04 65.48 44.04 65.48 43 65.96 43 65.96 41.32 65.48 41.32 65.48 40.28 65.96 40.28 65.96 38.6 65.48 38.6 65.48 37.56 65.96 37.56 65.96 35.88 65.48 35.88 65.48 34.84 65.96 34.84 65.96 33.16 65.48 33.16 65.48 32.12 65.96 32.12 65.96 30.44 65.48 30.44 65.48 29.4 65.96 29.4 65.96 27.72 65.48 27.72 65.48 26.68 65.96 26.68 65.96 25 65.48 25 65.48 23.96 65.96 23.96 65.96 22.28 65.48 22.28 65.48 21.24 65.96 21.24 65.96 19.56 65.48 19.56 65.48 18.52 65.96 18.52 65.96 16.84 65.48 16.84 65.48 15.8 65.96 15.8 65.96 14.12 65.48 14.12 65.48 13.08 65.96 13.08 65.96 11.4 65.48 11.4 65.48 10.36 65.96 10.36 65.96 8.68 65.48 8.68 65.48 7.64 65.96 7.64 65.96 5.96 65.48 5.96 65.48 4.92 65.96 4.92 65.96 3.24 65.48 3.24 65.48 2.2 65.96 2.2 65.96 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 0.76 10.36 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 ; - LAYER met5 ; - POLYGON 64.64 74.56 64.64 71.88 61.44 71.88 61.44 65.48 64.64 65.48 64.64 51.48 61.44 51.48 61.44 45.08 64.64 45.08 64.64 31.08 61.44 31.08 61.44 24.68 64.64 24.68 64.64 10.68 61.44 10.68 61.44 4.28 64.64 4.28 64.64 1.6 1.6 1.6 1.6 4.28 4.8 4.28 4.8 10.68 1.6 10.68 1.6 24.68 4.8 24.68 4.8 31.08 1.6 31.08 1.6 45.08 4.8 45.08 4.8 51.48 1.6 51.48 1.6 65.48 4.8 65.48 4.8 71.88 1.6 71.88 1.6 74.56 ; - LAYER li1 ; - RECT 0.17 0.17 66.07 75.99 ; - LAYER mcon ; - RECT 65.925 76.075 66.095 76.245 ; - RECT 65.465 76.075 65.635 76.245 ; - RECT 65.005 76.075 65.175 76.245 ; - RECT 64.545 76.075 64.715 76.245 ; - RECT 64.085 76.075 64.255 76.245 ; - RECT 63.625 76.075 63.795 76.245 ; - RECT 63.165 76.075 63.335 76.245 ; - RECT 62.705 76.075 62.875 76.245 ; - RECT 62.245 76.075 62.415 76.245 ; - RECT 61.785 76.075 61.955 76.245 ; - RECT 61.325 76.075 61.495 76.245 ; - RECT 60.865 76.075 61.035 76.245 ; - RECT 60.405 76.075 60.575 76.245 ; - RECT 59.945 76.075 60.115 76.245 ; - RECT 59.485 76.075 59.655 76.245 ; - RECT 59.025 76.075 59.195 76.245 ; - RECT 58.565 76.075 58.735 76.245 ; - RECT 58.105 76.075 58.275 76.245 ; - RECT 57.645 76.075 57.815 76.245 ; - RECT 57.185 76.075 57.355 76.245 ; - RECT 56.725 76.075 56.895 76.245 ; - RECT 56.265 76.075 56.435 76.245 ; - RECT 55.805 76.075 55.975 76.245 ; - RECT 55.345 76.075 55.515 76.245 ; - RECT 54.885 76.075 55.055 76.245 ; - RECT 54.425 76.075 54.595 76.245 ; - RECT 53.965 76.075 54.135 76.245 ; - RECT 53.505 76.075 53.675 76.245 ; - RECT 53.045 76.075 53.215 76.245 ; - RECT 52.585 76.075 52.755 76.245 ; - RECT 52.125 76.075 52.295 76.245 ; - RECT 51.665 76.075 51.835 76.245 ; - RECT 51.205 76.075 51.375 76.245 ; - RECT 50.745 76.075 50.915 76.245 ; - RECT 50.285 76.075 50.455 76.245 ; - RECT 49.825 76.075 49.995 76.245 ; - RECT 49.365 76.075 49.535 76.245 ; - RECT 48.905 76.075 49.075 76.245 ; - RECT 48.445 76.075 48.615 76.245 ; - RECT 47.985 76.075 48.155 76.245 ; - RECT 47.525 76.075 47.695 76.245 ; - RECT 47.065 76.075 47.235 76.245 ; - RECT 46.605 76.075 46.775 76.245 ; - RECT 46.145 76.075 46.315 76.245 ; - RECT 45.685 76.075 45.855 76.245 ; - RECT 45.225 76.075 45.395 76.245 ; - RECT 44.765 76.075 44.935 76.245 ; - RECT 44.305 76.075 44.475 76.245 ; - RECT 43.845 76.075 44.015 76.245 ; - RECT 43.385 76.075 43.555 76.245 ; - RECT 42.925 76.075 43.095 76.245 ; - RECT 42.465 76.075 42.635 76.245 ; - RECT 42.005 76.075 42.175 76.245 ; - RECT 41.545 76.075 41.715 76.245 ; - RECT 41.085 76.075 41.255 76.245 ; - RECT 40.625 76.075 40.795 76.245 ; - RECT 40.165 76.075 40.335 76.245 ; - RECT 39.705 76.075 39.875 76.245 ; - RECT 39.245 76.075 39.415 76.245 ; - RECT 38.785 76.075 38.955 76.245 ; - RECT 38.325 76.075 38.495 76.245 ; - RECT 37.865 76.075 38.035 76.245 ; - RECT 37.405 76.075 37.575 76.245 ; - RECT 36.945 76.075 37.115 76.245 ; - RECT 36.485 76.075 36.655 76.245 ; - RECT 36.025 76.075 36.195 76.245 ; - RECT 35.565 76.075 35.735 76.245 ; - RECT 35.105 76.075 35.275 76.245 ; - RECT 34.645 76.075 34.815 76.245 ; - RECT 34.185 76.075 34.355 76.245 ; - RECT 33.725 76.075 33.895 76.245 ; - RECT 33.265 76.075 33.435 76.245 ; - RECT 32.805 76.075 32.975 76.245 ; - RECT 32.345 76.075 32.515 76.245 ; - RECT 31.885 76.075 32.055 76.245 ; - RECT 31.425 76.075 31.595 76.245 ; - RECT 30.965 76.075 31.135 76.245 ; - RECT 30.505 76.075 30.675 76.245 ; - RECT 30.045 76.075 30.215 76.245 ; - RECT 29.585 76.075 29.755 76.245 ; - RECT 29.125 76.075 29.295 76.245 ; - RECT 28.665 76.075 28.835 76.245 ; - RECT 28.205 76.075 28.375 76.245 ; - RECT 27.745 76.075 27.915 76.245 ; - RECT 27.285 76.075 27.455 76.245 ; - RECT 26.825 76.075 26.995 76.245 ; - RECT 26.365 76.075 26.535 76.245 ; - RECT 25.905 76.075 26.075 76.245 ; - RECT 25.445 76.075 25.615 76.245 ; - RECT 24.985 76.075 25.155 76.245 ; - RECT 24.525 76.075 24.695 76.245 ; - RECT 24.065 76.075 24.235 76.245 ; - RECT 23.605 76.075 23.775 76.245 ; - RECT 23.145 76.075 23.315 76.245 ; - RECT 22.685 76.075 22.855 76.245 ; - RECT 22.225 76.075 22.395 76.245 ; - RECT 21.765 76.075 21.935 76.245 ; - RECT 21.305 76.075 21.475 76.245 ; - RECT 20.845 76.075 21.015 76.245 ; - RECT 20.385 76.075 20.555 76.245 ; - RECT 19.925 76.075 20.095 76.245 ; - RECT 19.465 76.075 19.635 76.245 ; - RECT 19.005 76.075 19.175 76.245 ; - RECT 18.545 76.075 18.715 76.245 ; - RECT 18.085 76.075 18.255 76.245 ; - RECT 17.625 76.075 17.795 76.245 ; - RECT 17.165 76.075 17.335 76.245 ; - RECT 16.705 76.075 16.875 76.245 ; - RECT 16.245 76.075 16.415 76.245 ; - RECT 15.785 76.075 15.955 76.245 ; - RECT 15.325 76.075 15.495 76.245 ; - RECT 14.865 76.075 15.035 76.245 ; - RECT 14.405 76.075 14.575 76.245 ; - RECT 13.945 76.075 14.115 76.245 ; - RECT 13.485 76.075 13.655 76.245 ; - RECT 13.025 76.075 13.195 76.245 ; - RECT 12.565 76.075 12.735 76.245 ; - RECT 12.105 76.075 12.275 76.245 ; - RECT 11.645 76.075 11.815 76.245 ; - RECT 11.185 76.075 11.355 76.245 ; - RECT 10.725 76.075 10.895 76.245 ; - RECT 10.265 76.075 10.435 76.245 ; - RECT 9.805 76.075 9.975 76.245 ; - RECT 9.345 76.075 9.515 76.245 ; - RECT 8.885 76.075 9.055 76.245 ; - RECT 8.425 76.075 8.595 76.245 ; - RECT 7.965 76.075 8.135 76.245 ; - RECT 7.505 76.075 7.675 76.245 ; - RECT 7.045 76.075 7.215 76.245 ; - RECT 6.585 76.075 6.755 76.245 ; - RECT 6.125 76.075 6.295 76.245 ; - RECT 5.665 76.075 5.835 76.245 ; - RECT 5.205 76.075 5.375 76.245 ; - RECT 4.745 76.075 4.915 76.245 ; - RECT 4.285 76.075 4.455 76.245 ; - RECT 3.825 76.075 3.995 76.245 ; - RECT 3.365 76.075 3.535 76.245 ; - RECT 2.905 76.075 3.075 76.245 ; - RECT 2.445 76.075 2.615 76.245 ; - RECT 1.985 76.075 2.155 76.245 ; - RECT 1.525 76.075 1.695 76.245 ; - RECT 1.065 76.075 1.235 76.245 ; - RECT 0.605 76.075 0.775 76.245 ; - RECT 0.145 76.075 0.315 76.245 ; - RECT 65.925 73.355 66.095 73.525 ; - RECT 65.465 73.355 65.635 73.525 ; - RECT 0.605 73.355 0.775 73.525 ; - RECT 0.145 73.355 0.315 73.525 ; - RECT 65.925 70.635 66.095 70.805 ; - RECT 65.465 70.635 65.635 70.805 ; - RECT 0.605 70.635 0.775 70.805 ; - RECT 0.145 70.635 0.315 70.805 ; - RECT 65.925 67.915 66.095 68.085 ; - RECT 65.465 67.915 65.635 68.085 ; - RECT 0.605 67.915 0.775 68.085 ; - RECT 0.145 67.915 0.315 68.085 ; - RECT 65.925 65.195 66.095 65.365 ; - RECT 65.465 65.195 65.635 65.365 ; - RECT 0.605 65.195 0.775 65.365 ; - RECT 0.145 65.195 0.315 65.365 ; - RECT 65.925 62.475 66.095 62.645 ; - RECT 65.465 62.475 65.635 62.645 ; - RECT 0.605 62.475 0.775 62.645 ; - RECT 0.145 62.475 0.315 62.645 ; - RECT 65.925 59.755 66.095 59.925 ; - RECT 65.465 59.755 65.635 59.925 ; - RECT 0.605 59.755 0.775 59.925 ; - RECT 0.145 59.755 0.315 59.925 ; - RECT 65.925 57.035 66.095 57.205 ; - RECT 65.465 57.035 65.635 57.205 ; - RECT 0.605 57.035 0.775 57.205 ; - RECT 0.145 57.035 0.315 57.205 ; - RECT 65.925 54.315 66.095 54.485 ; - RECT 65.465 54.315 65.635 54.485 ; - RECT 0.605 54.315 0.775 54.485 ; - RECT 0.145 54.315 0.315 54.485 ; - RECT 65.925 51.595 66.095 51.765 ; - RECT 65.465 51.595 65.635 51.765 ; - RECT 0.605 51.595 0.775 51.765 ; - RECT 0.145 51.595 0.315 51.765 ; - RECT 65.925 48.875 66.095 49.045 ; - RECT 65.465 48.875 65.635 49.045 ; - RECT 0.605 48.875 0.775 49.045 ; - RECT 0.145 48.875 0.315 49.045 ; - RECT 65.925 46.155 66.095 46.325 ; - RECT 65.465 46.155 65.635 46.325 ; - RECT 0.605 46.155 0.775 46.325 ; - RECT 0.145 46.155 0.315 46.325 ; - RECT 65.925 43.435 66.095 43.605 ; - RECT 65.465 43.435 65.635 43.605 ; - RECT 0.605 43.435 0.775 43.605 ; - RECT 0.145 43.435 0.315 43.605 ; - RECT 65.925 40.715 66.095 40.885 ; - RECT 65.465 40.715 65.635 40.885 ; - RECT 0.605 40.715 0.775 40.885 ; - RECT 0.145 40.715 0.315 40.885 ; - RECT 65.925 37.995 66.095 38.165 ; - RECT 65.465 37.995 65.635 38.165 ; - RECT 0.605 37.995 0.775 38.165 ; - RECT 0.145 37.995 0.315 38.165 ; - RECT 65.925 35.275 66.095 35.445 ; - RECT 65.465 35.275 65.635 35.445 ; - RECT 0.605 35.275 0.775 35.445 ; - RECT 0.145 35.275 0.315 35.445 ; - RECT 65.925 32.555 66.095 32.725 ; - RECT 65.465 32.555 65.635 32.725 ; - RECT 0.605 32.555 0.775 32.725 ; - RECT 0.145 32.555 0.315 32.725 ; - RECT 65.925 29.835 66.095 30.005 ; - RECT 65.465 29.835 65.635 30.005 ; - RECT 0.605 29.835 0.775 30.005 ; - RECT 0.145 29.835 0.315 30.005 ; - RECT 65.925 27.115 66.095 27.285 ; - RECT 65.465 27.115 65.635 27.285 ; - RECT 0.605 27.115 0.775 27.285 ; - RECT 0.145 27.115 0.315 27.285 ; - RECT 65.925 24.395 66.095 24.565 ; - RECT 65.465 24.395 65.635 24.565 ; - RECT 0.605 24.395 0.775 24.565 ; - RECT 0.145 24.395 0.315 24.565 ; - RECT 65.925 21.675 66.095 21.845 ; - RECT 65.465 21.675 65.635 21.845 ; - RECT 0.605 21.675 0.775 21.845 ; - RECT 0.145 21.675 0.315 21.845 ; - RECT 65.925 18.955 66.095 19.125 ; - RECT 65.465 18.955 65.635 19.125 ; - RECT 0.605 18.955 0.775 19.125 ; - RECT 0.145 18.955 0.315 19.125 ; - RECT 65.925 16.235 66.095 16.405 ; - RECT 65.465 16.235 65.635 16.405 ; - RECT 0.605 16.235 0.775 16.405 ; - RECT 0.145 16.235 0.315 16.405 ; - RECT 65.925 13.515 66.095 13.685 ; - RECT 65.465 13.515 65.635 13.685 ; - RECT 0.605 13.515 0.775 13.685 ; - RECT 0.145 13.515 0.315 13.685 ; - RECT 65.925 10.795 66.095 10.965 ; - RECT 65.465 10.795 65.635 10.965 ; - RECT 0.605 10.795 0.775 10.965 ; - RECT 0.145 10.795 0.315 10.965 ; - RECT 65.925 8.075 66.095 8.245 ; - RECT 65.465 8.075 65.635 8.245 ; - RECT 0.605 8.075 0.775 8.245 ; - RECT 0.145 8.075 0.315 8.245 ; - RECT 65.925 5.355 66.095 5.525 ; - RECT 65.465 5.355 65.635 5.525 ; - RECT 0.605 5.355 0.775 5.525 ; - RECT 0.145 5.355 0.315 5.525 ; - RECT 65.925 2.635 66.095 2.805 ; - RECT 65.465 2.635 65.635 2.805 ; - RECT 0.605 2.635 0.775 2.805 ; - RECT 0.145 2.635 0.315 2.805 ; - RECT 65.925 -0.085 66.095 0.085 ; - RECT 65.465 -0.085 65.635 0.085 ; - RECT 65.005 -0.085 65.175 0.085 ; - RECT 64.545 -0.085 64.715 0.085 ; - RECT 64.085 -0.085 64.255 0.085 ; - RECT 63.625 -0.085 63.795 0.085 ; - RECT 63.165 -0.085 63.335 0.085 ; - RECT 62.705 -0.085 62.875 0.085 ; - RECT 62.245 -0.085 62.415 0.085 ; - RECT 61.785 -0.085 61.955 0.085 ; - RECT 61.325 -0.085 61.495 0.085 ; - RECT 60.865 -0.085 61.035 0.085 ; - RECT 60.405 -0.085 60.575 0.085 ; - RECT 59.945 -0.085 60.115 0.085 ; - RECT 59.485 -0.085 59.655 0.085 ; - RECT 59.025 -0.085 59.195 0.085 ; - RECT 58.565 -0.085 58.735 0.085 ; - RECT 58.105 -0.085 58.275 0.085 ; - RECT 57.645 -0.085 57.815 0.085 ; - RECT 57.185 -0.085 57.355 0.085 ; - RECT 56.725 -0.085 56.895 0.085 ; - RECT 56.265 -0.085 56.435 0.085 ; - RECT 55.805 -0.085 55.975 0.085 ; - RECT 55.345 -0.085 55.515 0.085 ; - RECT 54.885 -0.085 55.055 0.085 ; - RECT 54.425 -0.085 54.595 0.085 ; - RECT 53.965 -0.085 54.135 0.085 ; - RECT 53.505 -0.085 53.675 0.085 ; - RECT 53.045 -0.085 53.215 0.085 ; - RECT 52.585 -0.085 52.755 0.085 ; - RECT 52.125 -0.085 52.295 0.085 ; - RECT 51.665 -0.085 51.835 0.085 ; - RECT 51.205 -0.085 51.375 0.085 ; - RECT 50.745 -0.085 50.915 0.085 ; - RECT 50.285 -0.085 50.455 0.085 ; - RECT 49.825 -0.085 49.995 0.085 ; - RECT 49.365 -0.085 49.535 0.085 ; - RECT 48.905 -0.085 49.075 0.085 ; - RECT 48.445 -0.085 48.615 0.085 ; - RECT 47.985 -0.085 48.155 0.085 ; - RECT 47.525 -0.085 47.695 0.085 ; - RECT 47.065 -0.085 47.235 0.085 ; - RECT 46.605 -0.085 46.775 0.085 ; - RECT 46.145 -0.085 46.315 0.085 ; - RECT 45.685 -0.085 45.855 0.085 ; - RECT 45.225 -0.085 45.395 0.085 ; - RECT 44.765 -0.085 44.935 0.085 ; - RECT 44.305 -0.085 44.475 0.085 ; - RECT 43.845 -0.085 44.015 0.085 ; - RECT 43.385 -0.085 43.555 0.085 ; - RECT 42.925 -0.085 43.095 0.085 ; - RECT 42.465 -0.085 42.635 0.085 ; - RECT 42.005 -0.085 42.175 0.085 ; - RECT 41.545 -0.085 41.715 0.085 ; - RECT 41.085 -0.085 41.255 0.085 ; - RECT 40.625 -0.085 40.795 0.085 ; - RECT 40.165 -0.085 40.335 0.085 ; - RECT 39.705 -0.085 39.875 0.085 ; - RECT 39.245 -0.085 39.415 0.085 ; - RECT 38.785 -0.085 38.955 0.085 ; - RECT 38.325 -0.085 38.495 0.085 ; - RECT 37.865 -0.085 38.035 0.085 ; - RECT 37.405 -0.085 37.575 0.085 ; - RECT 36.945 -0.085 37.115 0.085 ; - RECT 36.485 -0.085 36.655 0.085 ; - RECT 36.025 -0.085 36.195 0.085 ; - RECT 35.565 -0.085 35.735 0.085 ; - RECT 35.105 -0.085 35.275 0.085 ; - RECT 34.645 -0.085 34.815 0.085 ; - RECT 34.185 -0.085 34.355 0.085 ; - RECT 33.725 -0.085 33.895 0.085 ; - RECT 33.265 -0.085 33.435 0.085 ; - RECT 32.805 -0.085 32.975 0.085 ; - RECT 32.345 -0.085 32.515 0.085 ; - RECT 31.885 -0.085 32.055 0.085 ; - RECT 31.425 -0.085 31.595 0.085 ; - RECT 30.965 -0.085 31.135 0.085 ; - RECT 30.505 -0.085 30.675 0.085 ; - RECT 30.045 -0.085 30.215 0.085 ; - RECT 29.585 -0.085 29.755 0.085 ; - RECT 29.125 -0.085 29.295 0.085 ; - RECT 28.665 -0.085 28.835 0.085 ; - RECT 28.205 -0.085 28.375 0.085 ; - RECT 27.745 -0.085 27.915 0.085 ; - RECT 27.285 -0.085 27.455 0.085 ; - RECT 26.825 -0.085 26.995 0.085 ; - RECT 26.365 -0.085 26.535 0.085 ; - RECT 25.905 -0.085 26.075 0.085 ; - RECT 25.445 -0.085 25.615 0.085 ; - RECT 24.985 -0.085 25.155 0.085 ; - RECT 24.525 -0.085 24.695 0.085 ; - RECT 24.065 -0.085 24.235 0.085 ; - RECT 23.605 -0.085 23.775 0.085 ; - RECT 23.145 -0.085 23.315 0.085 ; - RECT 22.685 -0.085 22.855 0.085 ; - RECT 22.225 -0.085 22.395 0.085 ; - RECT 21.765 -0.085 21.935 0.085 ; - RECT 21.305 -0.085 21.475 0.085 ; - RECT 20.845 -0.085 21.015 0.085 ; - RECT 20.385 -0.085 20.555 0.085 ; - RECT 19.925 -0.085 20.095 0.085 ; - RECT 19.465 -0.085 19.635 0.085 ; - RECT 19.005 -0.085 19.175 0.085 ; - RECT 18.545 -0.085 18.715 0.085 ; - RECT 18.085 -0.085 18.255 0.085 ; - RECT 17.625 -0.085 17.795 0.085 ; - RECT 17.165 -0.085 17.335 0.085 ; - RECT 16.705 -0.085 16.875 0.085 ; - RECT 16.245 -0.085 16.415 0.085 ; - RECT 15.785 -0.085 15.955 0.085 ; - RECT 15.325 -0.085 15.495 0.085 ; - RECT 14.865 -0.085 15.035 0.085 ; - RECT 14.405 -0.085 14.575 0.085 ; - RECT 13.945 -0.085 14.115 0.085 ; - RECT 13.485 -0.085 13.655 0.085 ; - RECT 13.025 -0.085 13.195 0.085 ; - RECT 12.565 -0.085 12.735 0.085 ; - RECT 12.105 -0.085 12.275 0.085 ; - RECT 11.645 -0.085 11.815 0.085 ; - RECT 11.185 -0.085 11.355 0.085 ; - RECT 10.725 -0.085 10.895 0.085 ; - RECT 10.265 -0.085 10.435 0.085 ; - RECT 9.805 -0.085 9.975 0.085 ; - RECT 9.345 -0.085 9.515 0.085 ; - RECT 8.885 -0.085 9.055 0.085 ; - RECT 8.425 -0.085 8.595 0.085 ; - RECT 7.965 -0.085 8.135 0.085 ; - RECT 7.505 -0.085 7.675 0.085 ; - RECT 7.045 -0.085 7.215 0.085 ; - RECT 6.585 -0.085 6.755 0.085 ; - RECT 6.125 -0.085 6.295 0.085 ; - RECT 5.665 -0.085 5.835 0.085 ; - RECT 5.205 -0.085 5.375 0.085 ; - RECT 4.745 -0.085 4.915 0.085 ; - RECT 4.285 -0.085 4.455 0.085 ; - RECT 3.825 -0.085 3.995 0.085 ; - RECT 3.365 -0.085 3.535 0.085 ; - RECT 2.905 -0.085 3.075 0.085 ; - RECT 2.445 -0.085 2.615 0.085 ; - RECT 1.985 -0.085 2.155 0.085 ; - RECT 1.525 -0.085 1.695 0.085 ; - RECT 1.065 -0.085 1.235 0.085 ; - RECT 0.605 -0.085 0.775 0.085 ; - RECT 0.145 -0.085 0.315 0.085 ; - LAYER via ; - RECT 55.125 76.085 55.275 76.235 ; - RECT 25.685 76.085 25.835 76.235 ; - RECT 13.265 74.385 13.415 74.535 ; - RECT 11.425 74.385 11.575 74.535 ; - RECT 10.965 1.625 11.115 1.775 ; - RECT 55.125 -0.075 55.275 0.075 ; - RECT 25.685 -0.075 25.835 0.075 ; - LAYER via2 ; - RECT 55.1 76.06 55.3 76.26 ; - RECT 25.66 76.06 25.86 76.26 ; - RECT 1.28 65.18 1.48 65.38 ; - RECT 1.28 51.58 1.48 51.78 ; - RECT 1.74 32.54 1.94 32.74 ; - RECT 1.28 25.74 1.48 25.94 ; - RECT 64.76 14.86 64.96 15.06 ; - RECT 1.74 6.02 1.94 6.22 ; - RECT 55.1 -0.1 55.3 0.1 ; - RECT 25.66 -0.1 25.86 0.1 ; - LAYER via3 ; - RECT 55.1 76.06 55.3 76.26 ; - RECT 25.66 76.06 25.86 76.26 ; - RECT 64.3 18.94 64.5 19.14 ; - RECT 64.3 16.22 64.5 16.42 ; - RECT 1.74 12.82 1.94 13.02 ; - RECT 55.1 -0.1 55.3 0.1 ; - RECT 25.66 -0.1 25.86 0.1 ; - LAYER OVERLAP ; - POLYGON 0 0 0 76.16 66.24 76.16 66.24 0 ; - END -END cby_2__1_ - -END LIBRARY diff --git a/FPGA22_HIER_SKY_PNR/modules/lef/sb_0__0__icv_in_design.lef b/FPGA22_HIER_SKY_PNR/modules/lef/sb_0__0__icv_in_design.lef deleted file mode 100644 index 088a988..0000000 --- a/FPGA22_HIER_SKY_PNR/modules/lef/sb_0__0__icv_in_design.lef +++ /dev/null @@ -1,1995 +0,0 @@ -VERSION 5.7 ; -BUSBITCHARS "[]" ; - -UNITS - DATABASE MICRONS 1000 ; -END UNITS - -MANUFACTURINGGRID 0.005 ; - -LAYER li1 - TYPE ROUTING ; - DIRECTION VERTICAL ; - PITCH 0.46 ; - WIDTH 0.17 ; -END li1 - -LAYER mcon - TYPE CUT ; -END mcon - -LAYER met1 - TYPE ROUTING ; - DIRECTION HORIZONTAL ; - PITCH 0.34 ; - WIDTH 0.14 ; -END met1 - -LAYER via - TYPE CUT ; -END via - -LAYER met2 - TYPE ROUTING ; - DIRECTION VERTICAL ; - PITCH 0.46 ; - WIDTH 0.14 ; -END met2 - -LAYER via2 - TYPE CUT ; -END via2 - -LAYER met3 - TYPE ROUTING ; - DIRECTION HORIZONTAL ; - PITCH 0.68 ; - WIDTH 0.3 ; -END met3 - -LAYER via3 - TYPE CUT ; -END via3 - -LAYER met4 - TYPE ROUTING ; - DIRECTION VERTICAL ; - PITCH 0.92 ; - WIDTH 0.3 ; -END met4 - -LAYER via4 - TYPE CUT ; -END via4 - -LAYER met5 - TYPE ROUTING ; - DIRECTION HORIZONTAL ; - PITCH 3.4 ; - WIDTH 1.6 ; -END met5 - -LAYER nwell - TYPE MASTERSLICE ; -END nwell - -LAYER pwell - TYPE MASTERSLICE ; -END pwell - -LAYER OVERLAP - TYPE OVERLAP ; -END OVERLAP - -VIA L1M1_PR - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.145 -0.115 0.145 0.115 ; -END L1M1_PR - -VIA L1M1_PR_R - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.115 -0.145 0.115 0.145 ; -END L1M1_PR_R - -VIA L1M1_PR_M - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.115 -0.145 0.115 0.145 ; -END L1M1_PR_M - -VIA L1M1_PR_MR - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.145 -0.115 0.145 0.115 ; -END L1M1_PR_MR - -VIA L1M1_PR_C - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.145 -0.145 0.145 0.145 ; -END L1M1_PR_C - -VIA M1M2_PR - LAYER met1 ; - RECT -0.16 -0.13 0.16 0.13 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.13 -0.16 0.13 0.16 ; -END M1M2_PR - -VIA M1M2_PR_Enc - LAYER met1 ; - RECT -0.16 -0.13 0.16 0.13 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.16 -0.13 0.16 0.13 ; -END M1M2_PR_Enc - -VIA M1M2_PR_R - LAYER met1 ; - RECT -0.13 -0.16 0.13 0.16 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.16 -0.13 0.16 0.13 ; -END M1M2_PR_R - -VIA M1M2_PR_R_Enc - LAYER met1 ; - RECT -0.13 -0.16 0.13 0.16 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.13 -0.16 0.13 0.16 ; -END M1M2_PR_R_Enc - -VIA M1M2_PR_M - LAYER met1 ; - RECT -0.16 -0.13 0.16 0.13 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.16 -0.13 0.16 0.13 ; -END M1M2_PR_M - -VIA M1M2_PR_M_Enc - LAYER met1 ; - RECT -0.16 -0.13 0.16 0.13 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.13 -0.16 0.13 0.16 ; -END M1M2_PR_M_Enc - -VIA M1M2_PR_MR - LAYER met1 ; - RECT -0.13 -0.16 0.13 0.16 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.13 -0.16 0.13 0.16 ; -END M1M2_PR_MR - -VIA M1M2_PR_MR_Enc - LAYER met1 ; - RECT -0.13 -0.16 0.13 0.16 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.16 -0.13 0.16 0.13 ; -END M1M2_PR_MR_Enc - -VIA M1M2_PR_C - LAYER met1 ; - RECT -0.16 -0.16 0.16 0.16 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.16 -0.16 0.16 0.16 ; -END M1M2_PR_C - -VIA M2M3_PR - LAYER met2 ; - RECT -0.14 -0.185 0.14 0.185 ; - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met3 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M2M3_PR - -VIA M2M3_PR_R - LAYER met2 ; - RECT -0.185 -0.14 0.185 0.14 ; - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met3 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M2M3_PR_R - -VIA M2M3_PR_M - LAYER met2 ; - RECT -0.14 -0.185 0.14 0.185 ; - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met3 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M2M3_PR_M - -VIA M2M3_PR_MR - LAYER met2 ; - RECT -0.185 -0.14 0.185 0.14 ; - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met3 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M2M3_PR_MR - -VIA M2M3_PR_C - LAYER met2 ; - RECT -0.185 -0.185 0.185 0.185 ; - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met3 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M2M3_PR_C - -VIA M3M4_PR - LAYER met3 ; - RECT -0.19 -0.16 0.19 0.16 ; - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR - -VIA M3M4_PR_R - LAYER met3 ; - RECT -0.16 -0.19 0.16 0.19 ; - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR_R - -VIA M3M4_PR_M - LAYER met3 ; - RECT -0.19 -0.16 0.19 0.16 ; - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR_M - -VIA M3M4_PR_MR - LAYER met3 ; - RECT -0.16 -0.19 0.16 0.19 ; - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR_MR - -VIA M3M4_PR_C - LAYER met3 ; - RECT -0.19 -0.19 0.19 0.19 ; - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR_C - -VIA M4M5_PR - LAYER met4 ; - RECT -0.59 -0.59 0.59 0.59 ; - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - LAYER met5 ; - RECT -0.71 -0.71 0.71 0.71 ; -END M4M5_PR - -VIA M4M5_PR_R - LAYER met4 ; - RECT -0.59 -0.59 0.59 0.59 ; - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - LAYER met5 ; - RECT -0.71 -0.71 0.71 0.71 ; -END M4M5_PR_R - -VIA M4M5_PR_M - LAYER met4 ; - RECT -0.59 -0.59 0.59 0.59 ; - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - LAYER met5 ; - RECT -0.71 -0.71 0.71 0.71 ; -END M4M5_PR_M - -VIA M4M5_PR_MR - LAYER met4 ; - RECT -0.59 -0.59 0.59 0.59 ; - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - LAYER met5 ; - RECT -0.71 -0.71 0.71 0.71 ; -END M4M5_PR_MR - -VIA M4M5_PR_C - LAYER met4 ; - RECT -0.59 -0.59 0.59 0.59 ; - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - LAYER met5 ; - RECT -0.71 -0.71 0.71 0.71 ; -END M4M5_PR_C - -SITE unit - CLASS CORE ; - SYMMETRY Y ; - SIZE 0.46 BY 2.72 ; -END unit - -SITE unithddbl - CLASS CORE ; - SIZE 0.46 BY 5.44 ; -END unithddbl - -MACRO sb_0__0_ - CLASS BLOCK ; - ORIGIN 0 0 ; - SIZE 92 BY 97.92 ; - SYMMETRY X Y ; - PIN prog_clk[0] - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER met2 ; - RECT 73.53 85.68 73.67 87.04 ; - END - END prog_clk[0] - PIN chany_top_in[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 44.55 96.56 44.69 97.92 ; - END - END chany_top_in[0] - PIN chany_top_in[1] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 53.75 96.56 53.89 97.92 ; - END - END chany_top_in[1] - PIN chany_top_in[2] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 57.89 96.56 58.03 97.92 ; - END - END chany_top_in[2] - PIN chany_top_in[3] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 46.39 96.56 46.53 97.92 ; - END - END chany_top_in[3] - PIN chany_top_in[4] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 39.95 96.56 40.09 97.92 ; - END - END chany_top_in[4] - PIN chany_top_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 27.53 96.56 27.67 97.92 ; - END - END chany_top_in[5] - PIN chany_top_in[6] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 8.21 96.56 8.35 97.92 ; - END - END chany_top_in[6] - PIN chany_top_in[7] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 28.45 96.56 28.59 97.92 ; - END - END chany_top_in[7] - PIN chany_top_in[8] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 29.37 96.56 29.51 97.92 ; - END - END chany_top_in[8] - PIN chany_top_in[9] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 36.65 96.56 36.95 97.92 ; - END - END chany_top_in[9] - PIN chany_top_in[10] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 44.93 96.56 45.23 97.92 ; - END - END chany_top_in[10] - PIN chany_top_in[11] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 50.07 96.56 50.21 97.92 ; - END - END chany_top_in[11] - PIN chany_top_in[12] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 49.15 96.56 49.29 97.92 ; - END - END chany_top_in[12] - PIN chany_top_in[13] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 56.97 96.56 57.11 97.92 ; - END - END chany_top_in[13] - PIN chany_top_in[14] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 9.13 96.56 9.27 97.92 ; - END - END chany_top_in[14] - PIN chany_top_in[15] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 30.29 96.56 30.43 97.92 ; - END - END chany_top_in[15] - PIN chany_top_in[16] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 33.51 96.56 33.65 97.92 ; - END - END chany_top_in[16] - PIN chany_top_in[17] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 56.89 96.56 57.19 97.92 ; - END - END chany_top_in[17] - PIN chany_top_in[18] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 21.93 96.56 22.23 97.92 ; - END - END chany_top_in[18] - PIN chany_top_in[19] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 52.83 96.56 52.97 97.92 ; - END - END chany_top_in[19] - PIN top_left_grid_pin_1_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 60.19 96.56 60.33 97.92 ; - END - END top_left_grid_pin_1_[0] - PIN chanx_right_in[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 73.29 92 73.59 ; - END - END chanx_right_in[0] - PIN chanx_right_in[1] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 71.93 92 72.23 ; - END - END chanx_right_in[1] - PIN chanx_right_in[2] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 9.37 92 9.67 ; - END - END chanx_right_in[2] - PIN chanx_right_in[3] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 21.61 92 21.91 ; - END - END chanx_right_in[3] - PIN chanx_right_in[4] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 76.01 92 76.31 ; - END - END chanx_right_in[4] - PIN chanx_right_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 22.97 92 23.27 ; - END - END chanx_right_in[5] - PIN chanx_right_in[6] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 42.01 92 42.31 ; - END - END chanx_right_in[6] - PIN chanx_right_in[7] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 36.57 92 36.87 ; - END - END chanx_right_in[7] - PIN chanx_right_in[8] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 24.33 92 24.63 ; - END - END chanx_right_in[8] - PIN chanx_right_in[9] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 44.73 92 45.03 ; - END - END chanx_right_in[9] - PIN chanx_right_in[10] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 54.93 92 55.23 ; - END - END chanx_right_in[10] - PIN chanx_right_in[11] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 31.13 92 31.43 ; - END - END chanx_right_in[11] - PIN chanx_right_in[12] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 12.09 92 12.39 ; - END - END chanx_right_in[12] - PIN chanx_right_in[13] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 83.49 92 83.79 ; - END - END chanx_right_in[13] - PIN chanx_right_in[14] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 77.37 92 77.67 ; - END - END chanx_right_in[14] - PIN chanx_right_in[15] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 26.37 92 26.67 ; - END - END chanx_right_in[15] - PIN chanx_right_in[16] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 32.49 92 32.79 ; - END - END chanx_right_in[16] - PIN chanx_right_in[17] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 10.73 92 11.03 ; - END - END chanx_right_in[17] - PIN chanx_right_in[18] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 35.21 92 35.51 ; - END - END chanx_right_in[18] - PIN chanx_right_in[19] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 28.41 92 28.71 ; - END - END chanx_right_in[19] - PIN right_bottom_grid_pin_1_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 74.65 92 74.95 ; - END - END right_bottom_grid_pin_1_[0] - PIN right_bottom_grid_pin_3_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 59.69 92 59.99 ; - END - END right_bottom_grid_pin_3_[0] - PIN right_bottom_grid_pin_5_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 66.49 92 66.79 ; - END - END right_bottom_grid_pin_5_[0] - PIN right_bottom_grid_pin_7_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 50.17 92 50.47 ; - END - END right_bottom_grid_pin_7_[0] - PIN right_bottom_grid_pin_9_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 61.73 92 62.03 ; - END - END right_bottom_grid_pin_9_[0] - PIN right_bottom_grid_pin_11_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 48.81 92 49.11 ; - END - END right_bottom_grid_pin_11_[0] - PIN ccff_head[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 13.45 92 13.75 ; - END - END ccff_head[0] - PIN chany_top_out[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 45.47 96.56 45.61 97.92 ; - END - END chany_top_out[0] - PIN chany_top_out[1] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 12.73 96.56 13.03 97.92 ; - END - END chany_top_out[1] - PIN chany_top_out[2] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 47.31 96.56 47.45 97.92 ; - END - END chany_top_out[2] - PIN chany_top_out[3] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 5.37 96.56 5.67 97.92 ; - END - END chany_top_out[3] - PIN chany_top_out[4] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 56.05 96.56 56.19 97.92 ; - END - END chany_top_out[4] - PIN chany_top_out[5] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 46.77 96.56 47.07 97.92 ; - END - END chany_top_out[5] - PIN chany_top_out[6] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 34.81 96.56 35.11 97.92 ; - END - END chany_top_out[6] - PIN chany_top_out[7] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 23.77 96.56 24.07 97.92 ; - END - END chany_top_out[7] - PIN chany_top_out[8] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 7.21 96.56 7.51 97.92 ; - END - END chany_top_out[8] - PIN chany_top_out[9] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 32.97 96.56 33.27 97.92 ; - END - END chany_top_out[9] - PIN chany_top_out[10] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 48.23 96.56 48.37 97.92 ; - END - END chany_top_out[10] - PIN chany_top_out[11] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 48.61 96.56 48.91 97.92 ; - END - END chany_top_out[11] - PIN chany_top_out[12] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 50.99 96.56 51.13 97.92 ; - END - END chany_top_out[12] - PIN chany_top_out[13] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 31.13 96.56 31.43 97.92 ; - END - END chany_top_out[13] - PIN chany_top_out[14] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 9.05 96.56 9.35 97.92 ; - END - END chany_top_out[14] - PIN chany_top_out[15] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 27.45 96.56 27.75 97.92 ; - END - END chany_top_out[15] - PIN chany_top_out[16] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 51.91 96.56 52.05 97.92 ; - END - END chany_top_out[16] - PIN chany_top_out[17] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 52.29 96.56 52.59 97.92 ; - END - END chany_top_out[17] - PIN chany_top_out[18] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 50.45 96.56 50.75 97.92 ; - END - END chany_top_out[18] - PIN chany_top_out[19] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 29.29 96.56 29.59 97.92 ; - END - END chany_top_out[19] - PIN chanx_right_out[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 56.97 92 57.27 ; - END - END chanx_right_out[0] - PIN chanx_right_out[1] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 67.85 92 68.15 ; - END - END chanx_right_out[1] - PIN chanx_right_out[2] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 43.37 92 43.67 ; - END - END chanx_right_out[2] - PIN chanx_right_out[3] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 80.09 92 80.39 ; - END - END chanx_right_out[3] - PIN chanx_right_out[4] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 33.85 92 34.15 ; - END - END chanx_right_out[4] - PIN chanx_right_out[5] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 82.13 92 82.43 ; - END - END chanx_right_out[5] - PIN chanx_right_out[6] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 39.29 92 39.59 ; - END - END chanx_right_out[6] - PIN chanx_right_out[7] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 53.57 92 53.87 ; - END - END chanx_right_out[7] - PIN chanx_right_out[8] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 47.45 92 47.75 ; - END - END chanx_right_out[8] - PIN chanx_right_out[9] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 78.73 92 79.03 ; - END - END chanx_right_out[9] - PIN chanx_right_out[10] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 46.09 92 46.39 ; - END - END chanx_right_out[10] - PIN chanx_right_out[11] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 69.21 92 69.51 ; - END - END chanx_right_out[11] - PIN chanx_right_out[12] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 40.65 92 40.95 ; - END - END chanx_right_out[12] - PIN chanx_right_out[13] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 37.93 92 38.23 ; - END - END chanx_right_out[13] - PIN chanx_right_out[14] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 29.77 92 30.07 ; - END - END chanx_right_out[14] - PIN chanx_right_out[15] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 52.21 92 52.51 ; - END - END chanx_right_out[15] - PIN chanx_right_out[16] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 58.33 92 58.63 ; - END - END chanx_right_out[16] - PIN chanx_right_out[17] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 63.09 92 63.39 ; - END - END chanx_right_out[17] - PIN chanx_right_out[18] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 70.57 92 70.87 ; - END - END chanx_right_out[18] - PIN chanx_right_out[19] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 65.13 92 65.43 ; - END - END chanx_right_out[19] - PIN ccff_tail[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 23.85 0 23.99 1.36 ; - END - END ccff_tail[0] - PIN VDD - DIRECTION INPUT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0 2.48 0.48 2.96 ; - RECT 91.52 2.48 92 2.96 ; - RECT 0 7.92 0.48 8.4 ; - RECT 91.52 7.92 92 8.4 ; - RECT 0 13.36 0.48 13.84 ; - RECT 91.52 13.36 92 13.84 ; - RECT 0 18.8 0.48 19.28 ; - RECT 91.52 18.8 92 19.28 ; - RECT 0 24.24 0.48 24.72 ; - RECT 91.52 24.24 92 24.72 ; - RECT 0 29.68 0.48 30.16 ; - RECT 91.52 29.68 92 30.16 ; - RECT 0 35.12 0.48 35.6 ; - RECT 91.52 35.12 92 35.6 ; - RECT 0 40.56 0.48 41.04 ; - RECT 91.52 40.56 92 41.04 ; - RECT 0 46 0.48 46.48 ; - RECT 91.52 46 92 46.48 ; - RECT 0 51.44 0.48 51.92 ; - RECT 91.52 51.44 92 51.92 ; - RECT 0 56.88 0.48 57.36 ; - RECT 91.52 56.88 92 57.36 ; - RECT 0 62.32 0.48 62.8 ; - RECT 91.52 62.32 92 62.8 ; - RECT 0 67.76 0.48 68.24 ; - RECT 91.52 67.76 92 68.24 ; - RECT 0 73.2 0.48 73.68 ; - RECT 91.52 73.2 92 73.68 ; - RECT 0 78.64 0.48 79.12 ; - RECT 91.52 78.64 92 79.12 ; - RECT 0 84.08 0.48 84.56 ; - RECT 91.52 84.08 92 84.56 ; - RECT 0 89.52 0.48 90 ; - RECT 65.76 89.52 66.24 90 ; - RECT 0 94.96 0.48 95.44 ; - RECT 65.76 94.96 66.24 95.44 ; - LAYER met4 ; - RECT 10.74 0 11.34 0.6 ; - RECT 40.18 0 40.78 0.6 ; - RECT 80.66 0 81.26 0.6 ; - RECT 80.66 86.44 81.26 87.04 ; - RECT 10.74 97.32 11.34 97.92 ; - RECT 40.18 97.32 40.78 97.92 ; - LAYER met5 ; - RECT 0 11.32 3.2 14.52 ; - RECT 88.8 11.32 92 14.52 ; - RECT 0 52.12 3.2 55.32 ; - RECT 88.8 52.12 92 55.32 ; - END - END VDD - PIN VSS - DIRECTION INPUT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0 0 92 0.24 ; - RECT 0 5.2 0.48 5.68 ; - RECT 91.52 5.2 92 5.68 ; - RECT 0 10.64 0.48 11.12 ; - RECT 91.52 10.64 92 11.12 ; - RECT 0 16.08 0.48 16.56 ; - RECT 91.52 16.08 92 16.56 ; - RECT 0 21.52 0.48 22 ; - RECT 91.52 21.52 92 22 ; - RECT 0 26.96 0.48 27.44 ; - RECT 91.52 26.96 92 27.44 ; - RECT 0 32.4 0.48 32.88 ; - RECT 91.52 32.4 92 32.88 ; - RECT 0 37.84 0.48 38.32 ; - RECT 91.52 37.84 92 38.32 ; - RECT 0 43.28 0.48 43.76 ; - RECT 91.52 43.28 92 43.76 ; - RECT 0 48.72 0.48 49.2 ; - RECT 91.52 48.72 92 49.2 ; - RECT 0 54.16 0.48 54.64 ; - RECT 91.52 54.16 92 54.64 ; - RECT 0 59.6 0.48 60.08 ; - RECT 91.52 59.6 92 60.08 ; - RECT 0 65.04 0.48 65.52 ; - RECT 91.52 65.04 92 65.52 ; - RECT 0 70.48 0.48 70.96 ; - RECT 91.52 70.48 92 70.96 ; - RECT 0 75.92 0.48 76.4 ; - RECT 91.52 75.92 92 76.4 ; - RECT 0 81.36 0.48 81.84 ; - RECT 91.52 81.36 92 81.84 ; - RECT 0 86.8 92 87.28 ; - RECT 0 92.24 0.48 92.72 ; - RECT 65.76 92.24 66.24 92.72 ; - RECT 0 97.68 66.24 97.92 ; - LAYER met4 ; - RECT 25.46 0 26.06 0.6 ; - RECT 54.9 0 55.5 0.6 ; - RECT 25.46 97.32 26.06 97.92 ; - RECT 54.9 97.32 55.5 97.92 ; - LAYER met5 ; - RECT 0 31.72 3.2 34.92 ; - RECT 88.8 31.72 92 34.92 ; - RECT 0 72.52 3.2 75.72 ; - RECT 88.8 72.52 92 75.72 ; - END - END VSS - OBS - LAYER li1 ; - RECT 0 97.835 66.24 98.005 ; - RECT 65.32 95.115 66.24 95.285 ; - RECT 0 95.115 3.68 95.285 ; - RECT 65.32 92.395 66.24 92.565 ; - RECT 0 92.395 3.68 92.565 ; - RECT 65.32 89.675 66.24 89.845 ; - RECT 0 89.675 3.68 89.845 ; - RECT 62.56 86.955 92 87.125 ; - RECT 0 86.955 3.68 87.125 ; - RECT 91.54 84.235 92 84.405 ; - RECT 0 84.235 3.68 84.405 ; - RECT 91.08 81.515 92 81.685 ; - RECT 0 81.515 3.68 81.685 ; - RECT 91.08 78.795 92 78.965 ; - RECT 0 78.795 3.68 78.965 ; - RECT 91.54 76.075 92 76.245 ; - RECT 0 76.075 3.68 76.245 ; - RECT 91.54 73.355 92 73.525 ; - RECT 0 73.355 3.68 73.525 ; - RECT 91.08 70.635 92 70.805 ; - RECT 0 70.635 3.68 70.805 ; - RECT 91.08 67.915 92 68.085 ; - RECT 0 67.915 3.68 68.085 ; - RECT 91.08 65.195 92 65.365 ; - RECT 0 65.195 3.68 65.365 ; - RECT 91.08 62.475 92 62.645 ; - RECT 0 62.475 3.68 62.645 ; - RECT 91.08 59.755 92 59.925 ; - RECT 0 59.755 3.68 59.925 ; - RECT 91.08 57.035 92 57.205 ; - RECT 0 57.035 3.68 57.205 ; - RECT 91.08 54.315 92 54.485 ; - RECT 0 54.315 3.68 54.485 ; - RECT 91.08 51.595 92 51.765 ; - RECT 0 51.595 3.68 51.765 ; - RECT 91.08 48.875 92 49.045 ; - RECT 0 48.875 3.68 49.045 ; - RECT 91.08 46.155 92 46.325 ; - RECT 0 46.155 3.68 46.325 ; - RECT 91.08 43.435 92 43.605 ; - RECT 0 43.435 3.68 43.605 ; - RECT 91.08 40.715 92 40.885 ; - RECT 0 40.715 3.68 40.885 ; - RECT 91.08 37.995 92 38.165 ; - RECT 0 37.995 3.68 38.165 ; - RECT 91.08 35.275 92 35.445 ; - RECT 0 35.275 3.68 35.445 ; - RECT 91.54 32.555 92 32.725 ; - RECT 0 32.555 3.68 32.725 ; - RECT 91.54 29.835 92 30.005 ; - RECT 0 29.835 3.68 30.005 ; - RECT 91.54 27.115 92 27.285 ; - RECT 0 27.115 3.68 27.285 ; - RECT 91.54 24.395 92 24.565 ; - RECT 0 24.395 3.68 24.565 ; - RECT 91.54 21.675 92 21.845 ; - RECT 0 21.675 3.68 21.845 ; - RECT 91.54 18.955 92 19.125 ; - RECT 0 18.955 3.68 19.125 ; - RECT 91.54 16.235 92 16.405 ; - RECT 0 16.235 3.68 16.405 ; - RECT 91.54 13.515 92 13.685 ; - RECT 0 13.515 3.68 13.685 ; - RECT 91.54 10.795 92 10.965 ; - RECT 0 10.795 3.68 10.965 ; - RECT 91.54 8.075 92 8.245 ; - RECT 0 8.075 3.68 8.245 ; - RECT 91.54 5.355 92 5.525 ; - RECT 0 5.355 3.68 5.525 ; - RECT 91.54 2.635 92 2.805 ; - RECT 0 2.635 3.68 2.805 ; - RECT 0 -0.085 92 0.085 ; - LAYER met2 ; - RECT 55.06 97.735 55.34 98.105 ; - RECT 25.62 97.735 25.9 98.105 ; - RECT 55.06 -0.185 55.34 0.185 ; - RECT 25.62 -0.185 25.9 0.185 ; - POLYGON 65.96 97.64 65.96 86.76 73.25 86.76 73.25 85.4 73.95 85.4 73.95 86.76 91.72 86.76 91.72 0.28 24.27 0.28 24.27 1.64 23.57 1.64 23.57 0.28 0.28 0.28 0.28 97.64 7.93 97.64 7.93 96.28 8.63 96.28 8.63 97.64 8.85 97.64 8.85 96.28 9.55 96.28 9.55 97.64 27.25 97.64 27.25 96.28 27.95 96.28 27.95 97.64 28.17 97.64 28.17 96.28 28.87 96.28 28.87 97.64 29.09 97.64 29.09 96.28 29.79 96.28 29.79 97.64 30.01 97.64 30.01 96.28 30.71 96.28 30.71 97.64 33.23 97.64 33.23 96.28 33.93 96.28 33.93 97.64 39.67 97.64 39.67 96.28 40.37 96.28 40.37 97.64 44.27 97.64 44.27 96.28 44.97 96.28 44.97 97.64 45.19 97.64 45.19 96.28 45.89 96.28 45.89 97.64 46.11 97.64 46.11 96.28 46.81 96.28 46.81 97.64 47.03 97.64 47.03 96.28 47.73 96.28 47.73 97.64 47.95 97.64 47.95 96.28 48.65 96.28 48.65 97.64 48.87 97.64 48.87 96.28 49.57 96.28 49.57 97.64 49.79 97.64 49.79 96.28 50.49 96.28 50.49 97.64 50.71 97.64 50.71 96.28 51.41 96.28 51.41 97.64 51.63 97.64 51.63 96.28 52.33 96.28 52.33 97.64 52.55 97.64 52.55 96.28 53.25 96.28 53.25 97.64 53.47 97.64 53.47 96.28 54.17 96.28 54.17 97.64 55.77 97.64 55.77 96.28 56.47 96.28 56.47 97.64 56.69 97.64 56.69 96.28 57.39 96.28 57.39 97.64 57.61 97.64 57.61 96.28 58.31 96.28 58.31 97.64 59.91 97.64 59.91 96.28 60.61 96.28 60.61 97.64 ; - LAYER met4 ; - POLYGON 65.84 97.52 65.84 86.64 80.26 86.64 80.26 86.04 81.66 86.04 81.66 86.64 91.6 86.64 91.6 0.4 81.66 0.4 81.66 1 80.26 1 80.26 0.4 55.9 0.4 55.9 1 54.5 1 54.5 0.4 41.18 0.4 41.18 1 39.78 1 39.78 0.4 26.46 0.4 26.46 1 25.06 1 25.06 0.4 11.74 0.4 11.74 1 10.34 1 10.34 0.4 0.4 0.4 0.4 97.52 4.97 97.52 4.97 96.16 6.07 96.16 6.07 97.52 6.81 97.52 6.81 96.16 7.91 96.16 7.91 97.52 8.65 97.52 8.65 96.16 9.75 96.16 9.75 97.52 10.34 97.52 10.34 96.92 11.74 96.92 11.74 97.52 12.33 97.52 12.33 96.16 13.43 96.16 13.43 97.52 21.53 97.52 21.53 96.16 22.63 96.16 22.63 97.52 23.37 97.52 23.37 96.16 24.47 96.16 24.47 97.52 25.06 97.52 25.06 96.92 26.46 96.92 26.46 97.52 27.05 97.52 27.05 96.16 28.15 96.16 28.15 97.52 28.89 97.52 28.89 96.16 29.99 96.16 29.99 97.52 30.73 97.52 30.73 96.16 31.83 96.16 31.83 97.52 32.57 97.52 32.57 96.16 33.67 96.16 33.67 97.52 34.41 97.52 34.41 96.16 35.51 96.16 35.51 97.52 36.25 97.52 36.25 96.16 37.35 96.16 37.35 97.52 39.78 97.52 39.78 96.92 41.18 96.92 41.18 97.52 44.53 97.52 44.53 96.16 45.63 96.16 45.63 97.52 46.37 97.52 46.37 96.16 47.47 96.16 47.47 97.52 48.21 97.52 48.21 96.16 49.31 96.16 49.31 97.52 50.05 97.52 50.05 96.16 51.15 96.16 51.15 97.52 51.89 97.52 51.89 96.16 52.99 96.16 52.99 97.52 54.5 97.52 54.5 96.92 55.9 96.92 55.9 97.52 56.49 97.52 56.49 96.16 57.59 96.16 57.59 97.52 ; - LAYER met3 ; - POLYGON 55.365 98.085 55.365 98.08 55.58 98.08 55.58 97.76 55.365 97.76 55.365 97.755 55.035 97.755 55.035 97.76 54.82 97.76 54.82 98.08 55.035 98.08 55.035 98.085 ; - POLYGON 25.925 98.085 25.925 98.08 26.14 98.08 26.14 97.76 25.925 97.76 25.925 97.755 25.595 97.755 25.595 97.76 25.38 97.76 25.38 98.08 25.595 98.08 25.595 98.085 ; - POLYGON 90.785 56.605 90.785 56.275 90.455 56.275 90.455 56.29 76.67 56.29 76.67 56.59 90.455 56.59 90.455 56.605 ; - POLYGON 90.77 30.75 90.77 30.47 90.22 30.47 90.22 30.45 72.53 30.45 72.53 30.75 ; - POLYGON 55.365 0.165 55.365 0.16 55.58 0.16 55.58 -0.16 55.365 -0.16 55.365 -0.165 55.035 -0.165 55.035 -0.16 54.82 -0.16 54.82 0.16 55.035 0.16 55.035 0.165 ; - POLYGON 25.925 0.165 25.925 0.16 26.14 0.16 26.14 -0.16 25.925 -0.16 25.925 -0.165 25.595 -0.165 25.595 -0.16 25.38 -0.16 25.38 0.16 25.595 0.16 25.595 0.165 ; - POLYGON 65.84 97.52 65.84 86.64 91.6 86.64 91.6 84.19 90.22 84.19 90.22 83.09 91.6 83.09 91.6 82.83 90.22 82.83 90.22 81.73 91.6 81.73 91.6 80.79 90.22 80.79 90.22 79.69 91.6 79.69 91.6 79.43 90.22 79.43 90.22 78.33 91.6 78.33 91.6 78.07 90.22 78.07 90.22 76.97 91.6 76.97 91.6 76.71 90.22 76.71 90.22 75.61 91.6 75.61 91.6 75.35 90.22 75.35 90.22 74.25 91.6 74.25 91.6 73.99 90.22 73.99 90.22 72.89 91.6 72.89 91.6 72.63 90.22 72.63 90.22 71.53 91.6 71.53 91.6 71.27 90.22 71.27 90.22 70.17 91.6 70.17 91.6 69.91 90.22 69.91 90.22 68.81 91.6 68.81 91.6 68.55 90.22 68.55 90.22 67.45 91.6 67.45 91.6 67.19 90.22 67.19 90.22 66.09 91.6 66.09 91.6 65.83 90.22 65.83 90.22 64.73 91.6 64.73 91.6 63.79 90.22 63.79 90.22 62.69 91.6 62.69 91.6 62.43 90.22 62.43 90.22 61.33 91.6 61.33 91.6 60.39 90.22 60.39 90.22 59.29 91.6 59.29 91.6 59.03 90.22 59.03 90.22 57.93 91.6 57.93 91.6 57.67 90.22 57.67 90.22 56.57 91.6 56.57 91.6 55.63 90.22 55.63 90.22 54.53 91.6 54.53 91.6 54.27 90.22 54.27 90.22 53.17 91.6 53.17 91.6 52.91 90.22 52.91 90.22 51.81 91.6 51.81 91.6 50.87 90.22 50.87 90.22 49.77 91.6 49.77 91.6 49.51 90.22 49.51 90.22 48.41 91.6 48.41 91.6 48.15 90.22 48.15 90.22 47.05 91.6 47.05 91.6 46.79 90.22 46.79 90.22 45.69 91.6 45.69 91.6 45.43 90.22 45.43 90.22 44.33 91.6 44.33 91.6 44.07 90.22 44.07 90.22 42.97 91.6 42.97 91.6 42.71 90.22 42.71 90.22 41.61 91.6 41.61 91.6 41.35 90.22 41.35 90.22 40.25 91.6 40.25 91.6 39.99 90.22 39.99 90.22 38.89 91.6 38.89 91.6 38.63 90.22 38.63 90.22 37.53 91.6 37.53 91.6 37.27 90.22 37.27 90.22 36.17 91.6 36.17 91.6 35.91 90.22 35.91 90.22 34.81 91.6 34.81 91.6 34.55 90.22 34.55 90.22 33.45 91.6 33.45 91.6 33.19 90.22 33.19 90.22 32.09 91.6 32.09 91.6 31.83 90.22 31.83 90.22 30.73 91.6 30.73 91.6 30.47 90.22 30.47 90.22 29.37 91.6 29.37 91.6 29.11 90.22 29.11 90.22 28.01 91.6 28.01 91.6 27.07 90.22 27.07 90.22 25.97 91.6 25.97 91.6 25.03 90.22 25.03 90.22 23.93 91.6 23.93 91.6 23.67 90.22 23.67 90.22 22.57 91.6 22.57 91.6 22.31 90.22 22.31 90.22 21.21 91.6 21.21 91.6 14.15 90.22 14.15 90.22 13.05 91.6 13.05 91.6 12.79 90.22 12.79 90.22 11.69 91.6 11.69 91.6 11.43 90.22 11.43 90.22 10.33 91.6 10.33 91.6 10.07 90.22 10.07 90.22 8.97 91.6 8.97 91.6 0.4 0.4 0.4 0.4 97.52 ; - LAYER met5 ; - POLYGON 64.64 96.32 64.64 85.44 90.4 85.44 90.4 77.32 87.2 77.32 87.2 70.92 90.4 70.92 90.4 56.92 87.2 56.92 87.2 50.52 90.4 50.52 90.4 36.52 87.2 36.52 87.2 30.12 90.4 30.12 90.4 16.12 87.2 16.12 87.2 9.72 90.4 9.72 90.4 1.6 1.6 1.6 1.6 9.72 4.8 9.72 4.8 16.12 1.6 16.12 1.6 30.12 4.8 30.12 4.8 36.52 1.6 36.52 1.6 50.52 4.8 50.52 4.8 56.92 1.6 56.92 1.6 70.92 4.8 70.92 4.8 77.32 1.6 77.32 1.6 96.32 ; - LAYER met1 ; - POLYGON 65.96 97.4 65.96 95.72 65.48 95.72 65.48 94.68 65.96 94.68 65.96 93 65.48 93 65.48 91.96 65.96 91.96 65.96 90.28 65.48 90.28 65.48 89.24 65.96 89.24 65.96 87.56 0.28 87.56 0.28 89.24 0.76 89.24 0.76 90.28 0.28 90.28 0.28 91.96 0.76 91.96 0.76 93 0.28 93 0.28 94.68 0.76 94.68 0.76 95.72 0.28 95.72 0.28 97.4 ; - POLYGON 91.72 86.52 91.72 84.84 91.24 84.84 91.24 83.8 91.72 83.8 91.72 82.12 91.24 82.12 91.24 81.08 91.72 81.08 91.72 79.4 91.24 79.4 91.24 78.36 91.72 78.36 91.72 76.68 91.24 76.68 91.24 75.64 91.72 75.64 91.72 73.96 91.24 73.96 91.24 72.92 91.72 72.92 91.72 71.24 91.24 71.24 91.24 70.2 91.72 70.2 91.72 68.52 91.24 68.52 91.24 67.48 91.72 67.48 91.72 65.8 91.24 65.8 91.24 64.76 91.72 64.76 91.72 63.08 91.24 63.08 91.24 62.04 91.72 62.04 91.72 60.36 91.24 60.36 91.24 59.32 91.72 59.32 91.72 57.64 91.24 57.64 91.24 56.6 91.72 56.6 91.72 54.92 91.24 54.92 91.24 53.88 91.72 53.88 91.72 52.2 91.24 52.2 91.24 51.16 91.72 51.16 91.72 49.48 91.24 49.48 91.24 48.44 91.72 48.44 91.72 46.76 91.24 46.76 91.24 45.72 91.72 45.72 91.72 44.04 91.24 44.04 91.24 43 91.72 43 91.72 41.32 91.24 41.32 91.24 40.28 91.72 40.28 91.72 38.6 91.24 38.6 91.24 37.56 91.72 37.56 91.72 35.88 91.24 35.88 91.24 34.84 91.72 34.84 91.72 33.16 91.24 33.16 91.24 32.12 91.72 32.12 91.72 30.44 91.24 30.44 91.24 29.4 91.72 29.4 91.72 27.72 91.24 27.72 91.24 26.68 91.72 26.68 91.72 25 91.24 25 91.24 23.96 91.72 23.96 91.72 22.28 91.24 22.28 91.24 21.24 91.72 21.24 91.72 19.56 91.24 19.56 91.24 18.52 91.72 18.52 91.72 16.84 91.24 16.84 91.24 15.8 91.72 15.8 91.72 14.12 91.24 14.12 91.24 13.08 91.72 13.08 91.72 11.4 91.24 11.4 91.24 10.36 91.72 10.36 91.72 8.68 91.24 8.68 91.24 7.64 91.72 7.64 91.72 5.96 91.24 5.96 91.24 4.92 91.72 4.92 91.72 3.24 91.24 3.24 91.24 2.2 91.72 2.2 91.72 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 0.76 10.36 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 0.76 81.08 0.76 82.12 0.28 82.12 0.28 83.8 0.76 83.8 0.76 84.84 0.28 84.84 0.28 86.52 ; - LAYER li1 ; - POLYGON 66.07 97.75 66.07 86.87 91.83 86.87 91.83 0.17 0.17 0.17 0.17 97.75 ; - LAYER mcon ; - RECT 65.925 97.835 66.095 98.005 ; - RECT 65.465 97.835 65.635 98.005 ; - RECT 65.005 97.835 65.175 98.005 ; - RECT 64.545 97.835 64.715 98.005 ; - RECT 64.085 97.835 64.255 98.005 ; - RECT 63.625 97.835 63.795 98.005 ; - RECT 63.165 97.835 63.335 98.005 ; - RECT 62.705 97.835 62.875 98.005 ; - RECT 62.245 97.835 62.415 98.005 ; - RECT 61.785 97.835 61.955 98.005 ; - RECT 61.325 97.835 61.495 98.005 ; - RECT 60.865 97.835 61.035 98.005 ; - RECT 60.405 97.835 60.575 98.005 ; - RECT 59.945 97.835 60.115 98.005 ; - RECT 59.485 97.835 59.655 98.005 ; - RECT 59.025 97.835 59.195 98.005 ; - RECT 58.565 97.835 58.735 98.005 ; - RECT 58.105 97.835 58.275 98.005 ; - RECT 57.645 97.835 57.815 98.005 ; - RECT 57.185 97.835 57.355 98.005 ; - RECT 56.725 97.835 56.895 98.005 ; - RECT 56.265 97.835 56.435 98.005 ; - RECT 55.805 97.835 55.975 98.005 ; - RECT 55.345 97.835 55.515 98.005 ; - RECT 54.885 97.835 55.055 98.005 ; - RECT 54.425 97.835 54.595 98.005 ; - RECT 53.965 97.835 54.135 98.005 ; - RECT 53.505 97.835 53.675 98.005 ; - RECT 53.045 97.835 53.215 98.005 ; - RECT 52.585 97.835 52.755 98.005 ; - RECT 52.125 97.835 52.295 98.005 ; - RECT 51.665 97.835 51.835 98.005 ; - RECT 51.205 97.835 51.375 98.005 ; - RECT 50.745 97.835 50.915 98.005 ; - RECT 50.285 97.835 50.455 98.005 ; - RECT 49.825 97.835 49.995 98.005 ; - RECT 49.365 97.835 49.535 98.005 ; - RECT 48.905 97.835 49.075 98.005 ; - RECT 48.445 97.835 48.615 98.005 ; - RECT 47.985 97.835 48.155 98.005 ; - RECT 47.525 97.835 47.695 98.005 ; - RECT 47.065 97.835 47.235 98.005 ; - RECT 46.605 97.835 46.775 98.005 ; - RECT 46.145 97.835 46.315 98.005 ; - RECT 45.685 97.835 45.855 98.005 ; - RECT 45.225 97.835 45.395 98.005 ; - RECT 44.765 97.835 44.935 98.005 ; - RECT 44.305 97.835 44.475 98.005 ; - RECT 43.845 97.835 44.015 98.005 ; - RECT 43.385 97.835 43.555 98.005 ; - RECT 42.925 97.835 43.095 98.005 ; - RECT 42.465 97.835 42.635 98.005 ; - RECT 42.005 97.835 42.175 98.005 ; - RECT 41.545 97.835 41.715 98.005 ; - RECT 41.085 97.835 41.255 98.005 ; - RECT 40.625 97.835 40.795 98.005 ; - RECT 40.165 97.835 40.335 98.005 ; - RECT 39.705 97.835 39.875 98.005 ; - RECT 39.245 97.835 39.415 98.005 ; - RECT 38.785 97.835 38.955 98.005 ; - RECT 38.325 97.835 38.495 98.005 ; - RECT 37.865 97.835 38.035 98.005 ; - RECT 37.405 97.835 37.575 98.005 ; - RECT 36.945 97.835 37.115 98.005 ; - RECT 36.485 97.835 36.655 98.005 ; - RECT 36.025 97.835 36.195 98.005 ; - RECT 35.565 97.835 35.735 98.005 ; - RECT 35.105 97.835 35.275 98.005 ; - RECT 34.645 97.835 34.815 98.005 ; - RECT 34.185 97.835 34.355 98.005 ; - RECT 33.725 97.835 33.895 98.005 ; - RECT 33.265 97.835 33.435 98.005 ; - RECT 32.805 97.835 32.975 98.005 ; - RECT 32.345 97.835 32.515 98.005 ; - RECT 31.885 97.835 32.055 98.005 ; - RECT 31.425 97.835 31.595 98.005 ; - RECT 30.965 97.835 31.135 98.005 ; - RECT 30.505 97.835 30.675 98.005 ; - RECT 30.045 97.835 30.215 98.005 ; - RECT 29.585 97.835 29.755 98.005 ; - RECT 29.125 97.835 29.295 98.005 ; - RECT 28.665 97.835 28.835 98.005 ; - RECT 28.205 97.835 28.375 98.005 ; - RECT 27.745 97.835 27.915 98.005 ; - RECT 27.285 97.835 27.455 98.005 ; - RECT 26.825 97.835 26.995 98.005 ; - RECT 26.365 97.835 26.535 98.005 ; - RECT 25.905 97.835 26.075 98.005 ; - RECT 25.445 97.835 25.615 98.005 ; - RECT 24.985 97.835 25.155 98.005 ; - RECT 24.525 97.835 24.695 98.005 ; - RECT 24.065 97.835 24.235 98.005 ; - RECT 23.605 97.835 23.775 98.005 ; - RECT 23.145 97.835 23.315 98.005 ; - RECT 22.685 97.835 22.855 98.005 ; - RECT 22.225 97.835 22.395 98.005 ; - RECT 21.765 97.835 21.935 98.005 ; - RECT 21.305 97.835 21.475 98.005 ; - RECT 20.845 97.835 21.015 98.005 ; - RECT 20.385 97.835 20.555 98.005 ; - RECT 19.925 97.835 20.095 98.005 ; - RECT 19.465 97.835 19.635 98.005 ; - RECT 19.005 97.835 19.175 98.005 ; - RECT 18.545 97.835 18.715 98.005 ; - RECT 18.085 97.835 18.255 98.005 ; - RECT 17.625 97.835 17.795 98.005 ; - RECT 17.165 97.835 17.335 98.005 ; - RECT 16.705 97.835 16.875 98.005 ; - RECT 16.245 97.835 16.415 98.005 ; - RECT 15.785 97.835 15.955 98.005 ; - RECT 15.325 97.835 15.495 98.005 ; - RECT 14.865 97.835 15.035 98.005 ; - RECT 14.405 97.835 14.575 98.005 ; - RECT 13.945 97.835 14.115 98.005 ; - RECT 13.485 97.835 13.655 98.005 ; - RECT 13.025 97.835 13.195 98.005 ; - RECT 12.565 97.835 12.735 98.005 ; - RECT 12.105 97.835 12.275 98.005 ; - RECT 11.645 97.835 11.815 98.005 ; - RECT 11.185 97.835 11.355 98.005 ; - RECT 10.725 97.835 10.895 98.005 ; - RECT 10.265 97.835 10.435 98.005 ; - RECT 9.805 97.835 9.975 98.005 ; - RECT 9.345 97.835 9.515 98.005 ; - RECT 8.885 97.835 9.055 98.005 ; - RECT 8.425 97.835 8.595 98.005 ; - RECT 7.965 97.835 8.135 98.005 ; - RECT 7.505 97.835 7.675 98.005 ; - RECT 7.045 97.835 7.215 98.005 ; - RECT 6.585 97.835 6.755 98.005 ; - RECT 6.125 97.835 6.295 98.005 ; - RECT 5.665 97.835 5.835 98.005 ; - RECT 5.205 97.835 5.375 98.005 ; - RECT 4.745 97.835 4.915 98.005 ; - RECT 4.285 97.835 4.455 98.005 ; - RECT 3.825 97.835 3.995 98.005 ; - RECT 3.365 97.835 3.535 98.005 ; - RECT 2.905 97.835 3.075 98.005 ; - RECT 2.445 97.835 2.615 98.005 ; - RECT 1.985 97.835 2.155 98.005 ; - RECT 1.525 97.835 1.695 98.005 ; - RECT 1.065 97.835 1.235 98.005 ; - RECT 0.605 97.835 0.775 98.005 ; - RECT 0.145 97.835 0.315 98.005 ; - RECT 65.925 95.115 66.095 95.285 ; - RECT 65.465 95.115 65.635 95.285 ; - RECT 0.605 95.115 0.775 95.285 ; - RECT 0.145 95.115 0.315 95.285 ; - RECT 65.925 92.395 66.095 92.565 ; - RECT 65.465 92.395 65.635 92.565 ; - RECT 0.605 92.395 0.775 92.565 ; - RECT 0.145 92.395 0.315 92.565 ; - RECT 65.925 89.675 66.095 89.845 ; - RECT 65.465 89.675 65.635 89.845 ; - RECT 0.605 89.675 0.775 89.845 ; - RECT 0.145 89.675 0.315 89.845 ; - RECT 91.685 86.955 91.855 87.125 ; - RECT 91.225 86.955 91.395 87.125 ; - RECT 90.765 86.955 90.935 87.125 ; - RECT 90.305 86.955 90.475 87.125 ; - RECT 89.845 86.955 90.015 87.125 ; - RECT 89.385 86.955 89.555 87.125 ; - RECT 88.925 86.955 89.095 87.125 ; - RECT 88.465 86.955 88.635 87.125 ; - RECT 88.005 86.955 88.175 87.125 ; - RECT 87.545 86.955 87.715 87.125 ; - RECT 87.085 86.955 87.255 87.125 ; - RECT 86.625 86.955 86.795 87.125 ; - RECT 86.165 86.955 86.335 87.125 ; - RECT 85.705 86.955 85.875 87.125 ; - RECT 85.245 86.955 85.415 87.125 ; - RECT 84.785 86.955 84.955 87.125 ; - RECT 84.325 86.955 84.495 87.125 ; - RECT 83.865 86.955 84.035 87.125 ; - RECT 83.405 86.955 83.575 87.125 ; - RECT 82.945 86.955 83.115 87.125 ; - RECT 82.485 86.955 82.655 87.125 ; - RECT 82.025 86.955 82.195 87.125 ; - RECT 81.565 86.955 81.735 87.125 ; - RECT 81.105 86.955 81.275 87.125 ; - RECT 80.645 86.955 80.815 87.125 ; - RECT 80.185 86.955 80.355 87.125 ; - RECT 79.725 86.955 79.895 87.125 ; - RECT 79.265 86.955 79.435 87.125 ; - RECT 78.805 86.955 78.975 87.125 ; - RECT 78.345 86.955 78.515 87.125 ; - RECT 77.885 86.955 78.055 87.125 ; - RECT 77.425 86.955 77.595 87.125 ; - RECT 76.965 86.955 77.135 87.125 ; - RECT 76.505 86.955 76.675 87.125 ; - RECT 76.045 86.955 76.215 87.125 ; - RECT 75.585 86.955 75.755 87.125 ; - RECT 75.125 86.955 75.295 87.125 ; - RECT 74.665 86.955 74.835 87.125 ; - RECT 74.205 86.955 74.375 87.125 ; - RECT 73.745 86.955 73.915 87.125 ; - RECT 73.285 86.955 73.455 87.125 ; - RECT 72.825 86.955 72.995 87.125 ; - RECT 72.365 86.955 72.535 87.125 ; - RECT 71.905 86.955 72.075 87.125 ; - RECT 71.445 86.955 71.615 87.125 ; - RECT 70.985 86.955 71.155 87.125 ; - RECT 70.525 86.955 70.695 87.125 ; - RECT 70.065 86.955 70.235 87.125 ; - RECT 69.605 86.955 69.775 87.125 ; - RECT 69.145 86.955 69.315 87.125 ; - RECT 68.685 86.955 68.855 87.125 ; - RECT 68.225 86.955 68.395 87.125 ; - RECT 67.765 86.955 67.935 87.125 ; - RECT 67.305 86.955 67.475 87.125 ; - RECT 66.845 86.955 67.015 87.125 ; - RECT 66.385 86.955 66.555 87.125 ; - RECT 65.925 86.955 66.095 87.125 ; - RECT 65.465 86.955 65.635 87.125 ; - RECT 65.005 86.955 65.175 87.125 ; - RECT 64.545 86.955 64.715 87.125 ; - RECT 64.085 86.955 64.255 87.125 ; - RECT 63.625 86.955 63.795 87.125 ; - RECT 63.165 86.955 63.335 87.125 ; - RECT 62.705 86.955 62.875 87.125 ; - RECT 62.245 86.955 62.415 87.125 ; - RECT 61.785 86.955 61.955 87.125 ; - RECT 61.325 86.955 61.495 87.125 ; - RECT 60.865 86.955 61.035 87.125 ; - RECT 60.405 86.955 60.575 87.125 ; - RECT 59.945 86.955 60.115 87.125 ; - RECT 59.485 86.955 59.655 87.125 ; - RECT 59.025 86.955 59.195 87.125 ; - RECT 58.565 86.955 58.735 87.125 ; - RECT 58.105 86.955 58.275 87.125 ; - RECT 57.645 86.955 57.815 87.125 ; - RECT 57.185 86.955 57.355 87.125 ; - RECT 56.725 86.955 56.895 87.125 ; - RECT 56.265 86.955 56.435 87.125 ; - RECT 55.805 86.955 55.975 87.125 ; - RECT 55.345 86.955 55.515 87.125 ; - RECT 54.885 86.955 55.055 87.125 ; - RECT 54.425 86.955 54.595 87.125 ; - RECT 53.965 86.955 54.135 87.125 ; - RECT 53.505 86.955 53.675 87.125 ; - RECT 53.045 86.955 53.215 87.125 ; - RECT 52.585 86.955 52.755 87.125 ; - RECT 52.125 86.955 52.295 87.125 ; - RECT 51.665 86.955 51.835 87.125 ; - RECT 51.205 86.955 51.375 87.125 ; - RECT 50.745 86.955 50.915 87.125 ; - RECT 50.285 86.955 50.455 87.125 ; - RECT 49.825 86.955 49.995 87.125 ; - RECT 49.365 86.955 49.535 87.125 ; - RECT 48.905 86.955 49.075 87.125 ; - RECT 48.445 86.955 48.615 87.125 ; - RECT 47.985 86.955 48.155 87.125 ; - RECT 47.525 86.955 47.695 87.125 ; - RECT 47.065 86.955 47.235 87.125 ; - RECT 46.605 86.955 46.775 87.125 ; - RECT 46.145 86.955 46.315 87.125 ; - RECT 45.685 86.955 45.855 87.125 ; - RECT 45.225 86.955 45.395 87.125 ; - RECT 44.765 86.955 44.935 87.125 ; - RECT 44.305 86.955 44.475 87.125 ; - RECT 43.845 86.955 44.015 87.125 ; - RECT 43.385 86.955 43.555 87.125 ; - RECT 42.925 86.955 43.095 87.125 ; - RECT 42.465 86.955 42.635 87.125 ; - RECT 42.005 86.955 42.175 87.125 ; - RECT 41.545 86.955 41.715 87.125 ; - RECT 41.085 86.955 41.255 87.125 ; - RECT 40.625 86.955 40.795 87.125 ; - RECT 40.165 86.955 40.335 87.125 ; - RECT 39.705 86.955 39.875 87.125 ; - RECT 39.245 86.955 39.415 87.125 ; - RECT 38.785 86.955 38.955 87.125 ; - RECT 38.325 86.955 38.495 87.125 ; - RECT 37.865 86.955 38.035 87.125 ; - RECT 37.405 86.955 37.575 87.125 ; - RECT 36.945 86.955 37.115 87.125 ; - RECT 36.485 86.955 36.655 87.125 ; - RECT 36.025 86.955 36.195 87.125 ; - RECT 35.565 86.955 35.735 87.125 ; - RECT 35.105 86.955 35.275 87.125 ; - RECT 34.645 86.955 34.815 87.125 ; - RECT 34.185 86.955 34.355 87.125 ; - RECT 33.725 86.955 33.895 87.125 ; - RECT 33.265 86.955 33.435 87.125 ; - RECT 32.805 86.955 32.975 87.125 ; - RECT 32.345 86.955 32.515 87.125 ; - RECT 31.885 86.955 32.055 87.125 ; - RECT 31.425 86.955 31.595 87.125 ; - RECT 30.965 86.955 31.135 87.125 ; - RECT 30.505 86.955 30.675 87.125 ; - RECT 30.045 86.955 30.215 87.125 ; - RECT 29.585 86.955 29.755 87.125 ; - RECT 29.125 86.955 29.295 87.125 ; - RECT 28.665 86.955 28.835 87.125 ; - RECT 28.205 86.955 28.375 87.125 ; - RECT 27.745 86.955 27.915 87.125 ; - RECT 27.285 86.955 27.455 87.125 ; - RECT 26.825 86.955 26.995 87.125 ; - RECT 26.365 86.955 26.535 87.125 ; - RECT 25.905 86.955 26.075 87.125 ; - RECT 25.445 86.955 25.615 87.125 ; - RECT 24.985 86.955 25.155 87.125 ; - RECT 24.525 86.955 24.695 87.125 ; - RECT 24.065 86.955 24.235 87.125 ; - RECT 23.605 86.955 23.775 87.125 ; - RECT 23.145 86.955 23.315 87.125 ; - RECT 22.685 86.955 22.855 87.125 ; - RECT 22.225 86.955 22.395 87.125 ; - RECT 21.765 86.955 21.935 87.125 ; - RECT 21.305 86.955 21.475 87.125 ; - RECT 20.845 86.955 21.015 87.125 ; - RECT 20.385 86.955 20.555 87.125 ; - RECT 19.925 86.955 20.095 87.125 ; - RECT 19.465 86.955 19.635 87.125 ; - RECT 19.005 86.955 19.175 87.125 ; - RECT 18.545 86.955 18.715 87.125 ; - RECT 18.085 86.955 18.255 87.125 ; - RECT 17.625 86.955 17.795 87.125 ; - RECT 17.165 86.955 17.335 87.125 ; - RECT 16.705 86.955 16.875 87.125 ; - RECT 16.245 86.955 16.415 87.125 ; - RECT 15.785 86.955 15.955 87.125 ; - RECT 15.325 86.955 15.495 87.125 ; - RECT 14.865 86.955 15.035 87.125 ; - RECT 14.405 86.955 14.575 87.125 ; - RECT 13.945 86.955 14.115 87.125 ; - RECT 13.485 86.955 13.655 87.125 ; - RECT 13.025 86.955 13.195 87.125 ; - RECT 12.565 86.955 12.735 87.125 ; - RECT 12.105 86.955 12.275 87.125 ; - RECT 11.645 86.955 11.815 87.125 ; - RECT 11.185 86.955 11.355 87.125 ; - RECT 10.725 86.955 10.895 87.125 ; - RECT 10.265 86.955 10.435 87.125 ; - RECT 9.805 86.955 9.975 87.125 ; - RECT 9.345 86.955 9.515 87.125 ; - RECT 8.885 86.955 9.055 87.125 ; - RECT 8.425 86.955 8.595 87.125 ; - RECT 7.965 86.955 8.135 87.125 ; - RECT 7.505 86.955 7.675 87.125 ; - RECT 7.045 86.955 7.215 87.125 ; - RECT 6.585 86.955 6.755 87.125 ; - RECT 6.125 86.955 6.295 87.125 ; - RECT 5.665 86.955 5.835 87.125 ; - RECT 5.205 86.955 5.375 87.125 ; - RECT 4.745 86.955 4.915 87.125 ; - RECT 4.285 86.955 4.455 87.125 ; - RECT 3.825 86.955 3.995 87.125 ; - RECT 3.365 86.955 3.535 87.125 ; - RECT 2.905 86.955 3.075 87.125 ; - RECT 2.445 86.955 2.615 87.125 ; - RECT 1.985 86.955 2.155 87.125 ; - RECT 1.525 86.955 1.695 87.125 ; - RECT 1.065 86.955 1.235 87.125 ; - RECT 0.605 86.955 0.775 87.125 ; - RECT 0.145 86.955 0.315 87.125 ; - RECT 91.685 84.235 91.855 84.405 ; - RECT 91.225 84.235 91.395 84.405 ; - RECT 0.605 84.235 0.775 84.405 ; - RECT 0.145 84.235 0.315 84.405 ; - RECT 91.685 81.515 91.855 81.685 ; - RECT 91.225 81.515 91.395 81.685 ; - RECT 0.605 81.515 0.775 81.685 ; - RECT 0.145 81.515 0.315 81.685 ; - RECT 91.685 78.795 91.855 78.965 ; - RECT 91.225 78.795 91.395 78.965 ; - RECT 0.605 78.795 0.775 78.965 ; - RECT 0.145 78.795 0.315 78.965 ; - RECT 91.685 76.075 91.855 76.245 ; - RECT 91.225 76.075 91.395 76.245 ; - RECT 0.605 76.075 0.775 76.245 ; - RECT 0.145 76.075 0.315 76.245 ; - RECT 91.685 73.355 91.855 73.525 ; - RECT 91.225 73.355 91.395 73.525 ; - RECT 0.605 73.355 0.775 73.525 ; - RECT 0.145 73.355 0.315 73.525 ; - RECT 91.685 70.635 91.855 70.805 ; - RECT 91.225 70.635 91.395 70.805 ; - RECT 0.605 70.635 0.775 70.805 ; - RECT 0.145 70.635 0.315 70.805 ; - RECT 91.685 67.915 91.855 68.085 ; - RECT 91.225 67.915 91.395 68.085 ; - RECT 0.605 67.915 0.775 68.085 ; - RECT 0.145 67.915 0.315 68.085 ; - RECT 91.685 65.195 91.855 65.365 ; - RECT 91.225 65.195 91.395 65.365 ; - RECT 0.605 65.195 0.775 65.365 ; - RECT 0.145 65.195 0.315 65.365 ; - RECT 91.685 62.475 91.855 62.645 ; - RECT 91.225 62.475 91.395 62.645 ; - RECT 0.605 62.475 0.775 62.645 ; - RECT 0.145 62.475 0.315 62.645 ; - RECT 91.685 59.755 91.855 59.925 ; - RECT 91.225 59.755 91.395 59.925 ; - RECT 0.605 59.755 0.775 59.925 ; - RECT 0.145 59.755 0.315 59.925 ; - RECT 91.685 57.035 91.855 57.205 ; - RECT 91.225 57.035 91.395 57.205 ; - RECT 0.605 57.035 0.775 57.205 ; - RECT 0.145 57.035 0.315 57.205 ; - RECT 91.685 54.315 91.855 54.485 ; - RECT 91.225 54.315 91.395 54.485 ; - RECT 0.605 54.315 0.775 54.485 ; - RECT 0.145 54.315 0.315 54.485 ; - RECT 91.685 51.595 91.855 51.765 ; - RECT 91.225 51.595 91.395 51.765 ; - RECT 0.605 51.595 0.775 51.765 ; - RECT 0.145 51.595 0.315 51.765 ; - RECT 91.685 48.875 91.855 49.045 ; - RECT 91.225 48.875 91.395 49.045 ; - RECT 0.605 48.875 0.775 49.045 ; - RECT 0.145 48.875 0.315 49.045 ; - RECT 91.685 46.155 91.855 46.325 ; - RECT 91.225 46.155 91.395 46.325 ; - RECT 0.605 46.155 0.775 46.325 ; - RECT 0.145 46.155 0.315 46.325 ; - RECT 91.685 43.435 91.855 43.605 ; - RECT 91.225 43.435 91.395 43.605 ; - RECT 0.605 43.435 0.775 43.605 ; - RECT 0.145 43.435 0.315 43.605 ; - RECT 91.685 40.715 91.855 40.885 ; - RECT 91.225 40.715 91.395 40.885 ; - RECT 0.605 40.715 0.775 40.885 ; - RECT 0.145 40.715 0.315 40.885 ; - RECT 91.685 37.995 91.855 38.165 ; - RECT 91.225 37.995 91.395 38.165 ; - RECT 0.605 37.995 0.775 38.165 ; - RECT 0.145 37.995 0.315 38.165 ; - RECT 91.685 35.275 91.855 35.445 ; - RECT 91.225 35.275 91.395 35.445 ; - RECT 0.605 35.275 0.775 35.445 ; - RECT 0.145 35.275 0.315 35.445 ; - RECT 91.685 32.555 91.855 32.725 ; - RECT 91.225 32.555 91.395 32.725 ; - RECT 0.605 32.555 0.775 32.725 ; - RECT 0.145 32.555 0.315 32.725 ; - RECT 91.685 29.835 91.855 30.005 ; - RECT 91.225 29.835 91.395 30.005 ; - RECT 0.605 29.835 0.775 30.005 ; - RECT 0.145 29.835 0.315 30.005 ; - RECT 91.685 27.115 91.855 27.285 ; - RECT 91.225 27.115 91.395 27.285 ; - RECT 0.605 27.115 0.775 27.285 ; - RECT 0.145 27.115 0.315 27.285 ; - RECT 91.685 24.395 91.855 24.565 ; - RECT 91.225 24.395 91.395 24.565 ; - RECT 0.605 24.395 0.775 24.565 ; - RECT 0.145 24.395 0.315 24.565 ; - RECT 91.685 21.675 91.855 21.845 ; - RECT 91.225 21.675 91.395 21.845 ; - RECT 0.605 21.675 0.775 21.845 ; - RECT 0.145 21.675 0.315 21.845 ; - RECT 91.685 18.955 91.855 19.125 ; - RECT 91.225 18.955 91.395 19.125 ; - RECT 0.605 18.955 0.775 19.125 ; - RECT 0.145 18.955 0.315 19.125 ; - RECT 91.685 16.235 91.855 16.405 ; - RECT 91.225 16.235 91.395 16.405 ; - RECT 0.605 16.235 0.775 16.405 ; - RECT 0.145 16.235 0.315 16.405 ; - RECT 91.685 13.515 91.855 13.685 ; - RECT 91.225 13.515 91.395 13.685 ; - RECT 0.605 13.515 0.775 13.685 ; - RECT 0.145 13.515 0.315 13.685 ; - RECT 91.685 10.795 91.855 10.965 ; - RECT 91.225 10.795 91.395 10.965 ; - RECT 0.605 10.795 0.775 10.965 ; - RECT 0.145 10.795 0.315 10.965 ; - RECT 91.685 8.075 91.855 8.245 ; - RECT 91.225 8.075 91.395 8.245 ; - RECT 0.605 8.075 0.775 8.245 ; - RECT 0.145 8.075 0.315 8.245 ; - RECT 91.685 5.355 91.855 5.525 ; - RECT 91.225 5.355 91.395 5.525 ; - RECT 0.605 5.355 0.775 5.525 ; - RECT 0.145 5.355 0.315 5.525 ; - RECT 91.685 2.635 91.855 2.805 ; - RECT 91.225 2.635 91.395 2.805 ; - RECT 0.605 2.635 0.775 2.805 ; - RECT 0.145 2.635 0.315 2.805 ; - RECT 91.685 -0.085 91.855 0.085 ; - RECT 91.225 -0.085 91.395 0.085 ; - RECT 90.765 -0.085 90.935 0.085 ; - RECT 90.305 -0.085 90.475 0.085 ; - RECT 89.845 -0.085 90.015 0.085 ; - RECT 89.385 -0.085 89.555 0.085 ; - RECT 88.925 -0.085 89.095 0.085 ; - RECT 88.465 -0.085 88.635 0.085 ; - RECT 88.005 -0.085 88.175 0.085 ; - RECT 87.545 -0.085 87.715 0.085 ; - RECT 87.085 -0.085 87.255 0.085 ; - RECT 86.625 -0.085 86.795 0.085 ; - RECT 86.165 -0.085 86.335 0.085 ; - RECT 85.705 -0.085 85.875 0.085 ; - RECT 85.245 -0.085 85.415 0.085 ; - RECT 84.785 -0.085 84.955 0.085 ; - RECT 84.325 -0.085 84.495 0.085 ; - RECT 83.865 -0.085 84.035 0.085 ; - RECT 83.405 -0.085 83.575 0.085 ; - RECT 82.945 -0.085 83.115 0.085 ; - RECT 82.485 -0.085 82.655 0.085 ; - RECT 82.025 -0.085 82.195 0.085 ; - RECT 81.565 -0.085 81.735 0.085 ; - RECT 81.105 -0.085 81.275 0.085 ; - RECT 80.645 -0.085 80.815 0.085 ; - RECT 80.185 -0.085 80.355 0.085 ; - RECT 79.725 -0.085 79.895 0.085 ; - RECT 79.265 -0.085 79.435 0.085 ; - RECT 78.805 -0.085 78.975 0.085 ; - RECT 78.345 -0.085 78.515 0.085 ; - RECT 77.885 -0.085 78.055 0.085 ; - RECT 77.425 -0.085 77.595 0.085 ; - RECT 76.965 -0.085 77.135 0.085 ; - RECT 76.505 -0.085 76.675 0.085 ; - RECT 76.045 -0.085 76.215 0.085 ; - RECT 75.585 -0.085 75.755 0.085 ; - RECT 75.125 -0.085 75.295 0.085 ; - RECT 74.665 -0.085 74.835 0.085 ; - RECT 74.205 -0.085 74.375 0.085 ; - RECT 73.745 -0.085 73.915 0.085 ; - RECT 73.285 -0.085 73.455 0.085 ; - RECT 72.825 -0.085 72.995 0.085 ; - RECT 72.365 -0.085 72.535 0.085 ; - RECT 71.905 -0.085 72.075 0.085 ; - RECT 71.445 -0.085 71.615 0.085 ; - RECT 70.985 -0.085 71.155 0.085 ; - RECT 70.525 -0.085 70.695 0.085 ; - RECT 70.065 -0.085 70.235 0.085 ; - RECT 69.605 -0.085 69.775 0.085 ; - RECT 69.145 -0.085 69.315 0.085 ; - RECT 68.685 -0.085 68.855 0.085 ; - RECT 68.225 -0.085 68.395 0.085 ; - RECT 67.765 -0.085 67.935 0.085 ; - RECT 67.305 -0.085 67.475 0.085 ; - RECT 66.845 -0.085 67.015 0.085 ; - RECT 66.385 -0.085 66.555 0.085 ; - RECT 65.925 -0.085 66.095 0.085 ; - RECT 65.465 -0.085 65.635 0.085 ; - RECT 65.005 -0.085 65.175 0.085 ; - RECT 64.545 -0.085 64.715 0.085 ; - RECT 64.085 -0.085 64.255 0.085 ; - RECT 63.625 -0.085 63.795 0.085 ; - RECT 63.165 -0.085 63.335 0.085 ; - RECT 62.705 -0.085 62.875 0.085 ; - RECT 62.245 -0.085 62.415 0.085 ; - RECT 61.785 -0.085 61.955 0.085 ; - RECT 61.325 -0.085 61.495 0.085 ; - RECT 60.865 -0.085 61.035 0.085 ; - RECT 60.405 -0.085 60.575 0.085 ; - RECT 59.945 -0.085 60.115 0.085 ; - RECT 59.485 -0.085 59.655 0.085 ; - RECT 59.025 -0.085 59.195 0.085 ; - RECT 58.565 -0.085 58.735 0.085 ; - RECT 58.105 -0.085 58.275 0.085 ; - RECT 57.645 -0.085 57.815 0.085 ; - RECT 57.185 -0.085 57.355 0.085 ; - RECT 56.725 -0.085 56.895 0.085 ; - RECT 56.265 -0.085 56.435 0.085 ; - RECT 55.805 -0.085 55.975 0.085 ; - RECT 55.345 -0.085 55.515 0.085 ; - RECT 54.885 -0.085 55.055 0.085 ; - RECT 54.425 -0.085 54.595 0.085 ; - RECT 53.965 -0.085 54.135 0.085 ; - RECT 53.505 -0.085 53.675 0.085 ; - RECT 53.045 -0.085 53.215 0.085 ; - RECT 52.585 -0.085 52.755 0.085 ; - RECT 52.125 -0.085 52.295 0.085 ; - RECT 51.665 -0.085 51.835 0.085 ; - RECT 51.205 -0.085 51.375 0.085 ; - RECT 50.745 -0.085 50.915 0.085 ; - RECT 50.285 -0.085 50.455 0.085 ; - RECT 49.825 -0.085 49.995 0.085 ; - RECT 49.365 -0.085 49.535 0.085 ; - RECT 48.905 -0.085 49.075 0.085 ; - RECT 48.445 -0.085 48.615 0.085 ; - RECT 47.985 -0.085 48.155 0.085 ; - RECT 47.525 -0.085 47.695 0.085 ; - RECT 47.065 -0.085 47.235 0.085 ; - RECT 46.605 -0.085 46.775 0.085 ; - RECT 46.145 -0.085 46.315 0.085 ; - RECT 45.685 -0.085 45.855 0.085 ; - RECT 45.225 -0.085 45.395 0.085 ; - RECT 44.765 -0.085 44.935 0.085 ; - RECT 44.305 -0.085 44.475 0.085 ; - RECT 43.845 -0.085 44.015 0.085 ; - RECT 43.385 -0.085 43.555 0.085 ; - RECT 42.925 -0.085 43.095 0.085 ; - RECT 42.465 -0.085 42.635 0.085 ; - RECT 42.005 -0.085 42.175 0.085 ; - RECT 41.545 -0.085 41.715 0.085 ; - RECT 41.085 -0.085 41.255 0.085 ; - RECT 40.625 -0.085 40.795 0.085 ; - RECT 40.165 -0.085 40.335 0.085 ; - RECT 39.705 -0.085 39.875 0.085 ; - RECT 39.245 -0.085 39.415 0.085 ; - RECT 38.785 -0.085 38.955 0.085 ; - RECT 38.325 -0.085 38.495 0.085 ; - RECT 37.865 -0.085 38.035 0.085 ; - RECT 37.405 -0.085 37.575 0.085 ; - RECT 36.945 -0.085 37.115 0.085 ; - RECT 36.485 -0.085 36.655 0.085 ; - RECT 36.025 -0.085 36.195 0.085 ; - RECT 35.565 -0.085 35.735 0.085 ; - RECT 35.105 -0.085 35.275 0.085 ; - RECT 34.645 -0.085 34.815 0.085 ; - RECT 34.185 -0.085 34.355 0.085 ; - RECT 33.725 -0.085 33.895 0.085 ; - RECT 33.265 -0.085 33.435 0.085 ; - RECT 32.805 -0.085 32.975 0.085 ; - RECT 32.345 -0.085 32.515 0.085 ; - RECT 31.885 -0.085 32.055 0.085 ; - RECT 31.425 -0.085 31.595 0.085 ; - RECT 30.965 -0.085 31.135 0.085 ; - RECT 30.505 -0.085 30.675 0.085 ; - RECT 30.045 -0.085 30.215 0.085 ; - RECT 29.585 -0.085 29.755 0.085 ; - RECT 29.125 -0.085 29.295 0.085 ; - RECT 28.665 -0.085 28.835 0.085 ; - RECT 28.205 -0.085 28.375 0.085 ; - RECT 27.745 -0.085 27.915 0.085 ; - RECT 27.285 -0.085 27.455 0.085 ; - RECT 26.825 -0.085 26.995 0.085 ; - RECT 26.365 -0.085 26.535 0.085 ; - RECT 25.905 -0.085 26.075 0.085 ; - RECT 25.445 -0.085 25.615 0.085 ; - RECT 24.985 -0.085 25.155 0.085 ; - RECT 24.525 -0.085 24.695 0.085 ; - RECT 24.065 -0.085 24.235 0.085 ; - RECT 23.605 -0.085 23.775 0.085 ; - RECT 23.145 -0.085 23.315 0.085 ; - RECT 22.685 -0.085 22.855 0.085 ; - RECT 22.225 -0.085 22.395 0.085 ; - RECT 21.765 -0.085 21.935 0.085 ; - RECT 21.305 -0.085 21.475 0.085 ; - RECT 20.845 -0.085 21.015 0.085 ; - RECT 20.385 -0.085 20.555 0.085 ; - RECT 19.925 -0.085 20.095 0.085 ; - RECT 19.465 -0.085 19.635 0.085 ; - RECT 19.005 -0.085 19.175 0.085 ; - RECT 18.545 -0.085 18.715 0.085 ; - RECT 18.085 -0.085 18.255 0.085 ; - RECT 17.625 -0.085 17.795 0.085 ; - RECT 17.165 -0.085 17.335 0.085 ; - RECT 16.705 -0.085 16.875 0.085 ; - RECT 16.245 -0.085 16.415 0.085 ; - RECT 15.785 -0.085 15.955 0.085 ; - RECT 15.325 -0.085 15.495 0.085 ; - RECT 14.865 -0.085 15.035 0.085 ; - RECT 14.405 -0.085 14.575 0.085 ; - RECT 13.945 -0.085 14.115 0.085 ; - RECT 13.485 -0.085 13.655 0.085 ; - RECT 13.025 -0.085 13.195 0.085 ; - RECT 12.565 -0.085 12.735 0.085 ; - RECT 12.105 -0.085 12.275 0.085 ; - RECT 11.645 -0.085 11.815 0.085 ; - RECT 11.185 -0.085 11.355 0.085 ; - RECT 10.725 -0.085 10.895 0.085 ; - RECT 10.265 -0.085 10.435 0.085 ; - RECT 9.805 -0.085 9.975 0.085 ; - RECT 9.345 -0.085 9.515 0.085 ; - RECT 8.885 -0.085 9.055 0.085 ; - RECT 8.425 -0.085 8.595 0.085 ; - RECT 7.965 -0.085 8.135 0.085 ; - RECT 7.505 -0.085 7.675 0.085 ; - RECT 7.045 -0.085 7.215 0.085 ; - RECT 6.585 -0.085 6.755 0.085 ; - RECT 6.125 -0.085 6.295 0.085 ; - RECT 5.665 -0.085 5.835 0.085 ; - RECT 5.205 -0.085 5.375 0.085 ; - RECT 4.745 -0.085 4.915 0.085 ; - RECT 4.285 -0.085 4.455 0.085 ; - RECT 3.825 -0.085 3.995 0.085 ; - RECT 3.365 -0.085 3.535 0.085 ; - RECT 2.905 -0.085 3.075 0.085 ; - RECT 2.445 -0.085 2.615 0.085 ; - RECT 1.985 -0.085 2.155 0.085 ; - RECT 1.525 -0.085 1.695 0.085 ; - RECT 1.065 -0.085 1.235 0.085 ; - RECT 0.605 -0.085 0.775 0.085 ; - RECT 0.145 -0.085 0.315 0.085 ; - LAYER via ; - RECT 55.125 97.845 55.275 97.995 ; - RECT 25.685 97.845 25.835 97.995 ; - RECT 46.385 96.145 46.535 96.295 ; - RECT 29.365 96.145 29.515 96.295 ; - RECT 55.125 86.965 55.275 87.115 ; - RECT 25.685 86.965 25.835 87.115 ; - RECT 55.125 -0.075 55.275 0.075 ; - RECT 25.685 -0.075 25.835 0.075 ; - LAYER via2 ; - RECT 55.1 97.82 55.3 98.02 ; - RECT 25.66 97.82 25.86 98.02 ; - RECT 90.52 78.78 90.72 78.98 ; - RECT 90.52 70.62 90.72 70.82 ; - RECT 90.52 61.78 90.72 61.98 ; - RECT 90.52 52.26 90.72 52.46 ; - RECT 90.52 46.14 90.72 46.34 ; - RECT 55.1 -0.1 55.3 0.1 ; - RECT 25.66 -0.1 25.86 0.1 ; - LAYER via3 ; - RECT 55.1 97.82 55.3 98.02 ; - RECT 25.66 97.82 25.86 98.02 ; - RECT 55.1 -0.1 55.3 0.1 ; - RECT 25.66 -0.1 25.86 0.1 ; - LAYER OVERLAP ; - POLYGON 0 0 0 97.92 66.24 97.92 66.24 87.04 92 87.04 92 0 ; - END -END sb_0__0_ - -END LIBRARY diff --git a/FPGA22_HIER_SKY_PNR/modules/lef/sb_0__1__icv_in_design.lef b/FPGA22_HIER_SKY_PNR/modules/lef/sb_0__1__icv_in_design.lef deleted file mode 100644 index c20b096..0000000 --- a/FPGA22_HIER_SKY_PNR/modules/lef/sb_0__1__icv_in_design.lef +++ /dev/null @@ -1,2529 +0,0 @@ -VERSION 5.7 ; -BUSBITCHARS "[]" ; - -UNITS - DATABASE MICRONS 1000 ; -END UNITS - -MANUFACTURINGGRID 0.005 ; - -LAYER li1 - TYPE ROUTING ; - DIRECTION VERTICAL ; - PITCH 0.46 ; - WIDTH 0.17 ; -END li1 - -LAYER mcon - TYPE CUT ; -END mcon - -LAYER met1 - TYPE ROUTING ; - DIRECTION HORIZONTAL ; - PITCH 0.34 ; - WIDTH 0.14 ; -END met1 - -LAYER via - TYPE CUT ; -END via - -LAYER met2 - TYPE ROUTING ; - DIRECTION VERTICAL ; - PITCH 0.46 ; - WIDTH 0.14 ; -END met2 - -LAYER via2 - TYPE CUT ; -END via2 - -LAYER met3 - TYPE ROUTING ; - DIRECTION HORIZONTAL ; - PITCH 0.68 ; - WIDTH 0.3 ; -END met3 - -LAYER via3 - TYPE CUT ; -END via3 - -LAYER met4 - TYPE ROUTING ; - DIRECTION VERTICAL ; - PITCH 0.92 ; - WIDTH 0.3 ; -END met4 - -LAYER via4 - TYPE CUT ; -END via4 - -LAYER met5 - TYPE ROUTING ; - DIRECTION HORIZONTAL ; - PITCH 3.4 ; - WIDTH 1.6 ; -END met5 - -LAYER nwell - TYPE MASTERSLICE ; -END nwell - -LAYER pwell - TYPE MASTERSLICE ; -END pwell - -LAYER OVERLAP - TYPE OVERLAP ; -END OVERLAP - -VIA L1M1_PR - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.145 -0.115 0.145 0.115 ; -END L1M1_PR - -VIA L1M1_PR_R - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.115 -0.145 0.115 0.145 ; -END L1M1_PR_R - -VIA L1M1_PR_M - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.115 -0.145 0.115 0.145 ; -END L1M1_PR_M - -VIA L1M1_PR_MR - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.145 -0.115 0.145 0.115 ; -END L1M1_PR_MR - -VIA L1M1_PR_C - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.145 -0.145 0.145 0.145 ; -END L1M1_PR_C - -VIA M1M2_PR - LAYER met1 ; - RECT -0.16 -0.13 0.16 0.13 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.13 -0.16 0.13 0.16 ; -END M1M2_PR - -VIA M1M2_PR_Enc - LAYER met1 ; - RECT -0.16 -0.13 0.16 0.13 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.16 -0.13 0.16 0.13 ; -END M1M2_PR_Enc - -VIA M1M2_PR_R - LAYER met1 ; - RECT -0.13 -0.16 0.13 0.16 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.16 -0.13 0.16 0.13 ; -END M1M2_PR_R - -VIA M1M2_PR_R_Enc - LAYER met1 ; - RECT -0.13 -0.16 0.13 0.16 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.13 -0.16 0.13 0.16 ; -END M1M2_PR_R_Enc - -VIA M1M2_PR_M - LAYER met1 ; - RECT -0.16 -0.13 0.16 0.13 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.16 -0.13 0.16 0.13 ; -END M1M2_PR_M - -VIA M1M2_PR_M_Enc - LAYER met1 ; - RECT -0.16 -0.13 0.16 0.13 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.13 -0.16 0.13 0.16 ; -END M1M2_PR_M_Enc - -VIA M1M2_PR_MR - LAYER met1 ; - RECT -0.13 -0.16 0.13 0.16 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.13 -0.16 0.13 0.16 ; -END M1M2_PR_MR - -VIA M1M2_PR_MR_Enc - LAYER met1 ; - RECT -0.13 -0.16 0.13 0.16 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.16 -0.13 0.16 0.13 ; -END M1M2_PR_MR_Enc - -VIA M1M2_PR_C - LAYER met1 ; - RECT -0.16 -0.16 0.16 0.16 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.16 -0.16 0.16 0.16 ; -END M1M2_PR_C - -VIA M2M3_PR - LAYER met2 ; - RECT -0.14 -0.185 0.14 0.185 ; - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met3 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M2M3_PR - -VIA M2M3_PR_R - LAYER met2 ; - RECT -0.185 -0.14 0.185 0.14 ; - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met3 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M2M3_PR_R - -VIA M2M3_PR_M - LAYER met2 ; - RECT -0.14 -0.185 0.14 0.185 ; - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met3 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M2M3_PR_M - -VIA M2M3_PR_MR - LAYER met2 ; - RECT -0.185 -0.14 0.185 0.14 ; - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met3 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M2M3_PR_MR - -VIA M2M3_PR_C - LAYER met2 ; - RECT -0.185 -0.185 0.185 0.185 ; - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met3 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M2M3_PR_C - -VIA M3M4_PR - LAYER met3 ; - RECT -0.19 -0.16 0.19 0.16 ; - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR - -VIA M3M4_PR_R - LAYER met3 ; - RECT -0.16 -0.19 0.16 0.19 ; - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR_R - -VIA M3M4_PR_M - LAYER met3 ; - RECT -0.19 -0.16 0.19 0.16 ; - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR_M - -VIA M3M4_PR_MR - LAYER met3 ; - RECT -0.16 -0.19 0.16 0.19 ; - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR_MR - -VIA M3M4_PR_C - LAYER met3 ; - RECT -0.19 -0.19 0.19 0.19 ; - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR_C - -VIA M4M5_PR - LAYER met4 ; - RECT -0.59 -0.59 0.59 0.59 ; - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - LAYER met5 ; - RECT -0.71 -0.71 0.71 0.71 ; -END M4M5_PR - -VIA M4M5_PR_R - LAYER met4 ; - RECT -0.59 -0.59 0.59 0.59 ; - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - LAYER met5 ; - RECT -0.71 -0.71 0.71 0.71 ; -END M4M5_PR_R - -VIA M4M5_PR_M - LAYER met4 ; - RECT -0.59 -0.59 0.59 0.59 ; - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - LAYER met5 ; - RECT -0.71 -0.71 0.71 0.71 ; -END M4M5_PR_M - -VIA M4M5_PR_MR - LAYER met4 ; - RECT -0.59 -0.59 0.59 0.59 ; - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - LAYER met5 ; - RECT -0.71 -0.71 0.71 0.71 ; -END M4M5_PR_MR - -VIA M4M5_PR_C - LAYER met4 ; - RECT -0.59 -0.59 0.59 0.59 ; - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - LAYER met5 ; - RECT -0.71 -0.71 0.71 0.71 ; -END M4M5_PR_C - -SITE unit - CLASS CORE ; - SYMMETRY Y ; - SIZE 0.46 BY 2.72 ; -END unit - -SITE unithddbl - CLASS CORE ; - SIZE 0.46 BY 5.44 ; -END unithddbl - -MACRO sb_0__1_ - CLASS BLOCK ; - ORIGIN 0 0 ; - SIZE 92 BY 108.8 ; - SYMMETRY X Y ; - PIN prog_clk[0] - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER met2 ; - RECT 78.59 10.88 78.73 12.24 ; - END - END prog_clk[0] - PIN chany_top_in[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 44.55 107.44 44.69 108.8 ; - END - END chany_top_in[0] - PIN chany_top_in[1] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 53.75 107.44 53.89 108.8 ; - END - END chany_top_in[1] - PIN chany_top_in[2] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 57.89 107.44 58.03 108.8 ; - END - END chany_top_in[2] - PIN chany_top_in[3] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 46.39 107.44 46.53 108.8 ; - END - END chany_top_in[3] - PIN chany_top_in[4] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 39.95 107.44 40.09 108.8 ; - END - END chany_top_in[4] - PIN chany_top_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 27.53 107.44 27.67 108.8 ; - END - END chany_top_in[5] - PIN chany_top_in[6] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 8.21 107.44 8.35 108.8 ; - END - END chany_top_in[6] - PIN chany_top_in[7] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 28.45 107.44 28.59 108.8 ; - END - END chany_top_in[7] - PIN chany_top_in[8] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 29.37 107.44 29.51 108.8 ; - END - END chany_top_in[8] - PIN chany_top_in[9] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 36.65 107.44 36.95 108.8 ; - END - END chany_top_in[9] - PIN chany_top_in[10] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 44.93 107.44 45.23 108.8 ; - END - END chany_top_in[10] - PIN chany_top_in[11] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 50.07 107.44 50.21 108.8 ; - END - END chany_top_in[11] - PIN chany_top_in[12] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 49.15 107.44 49.29 108.8 ; - END - END chany_top_in[12] - PIN chany_top_in[13] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 56.97 107.44 57.11 108.8 ; - END - END chany_top_in[13] - PIN chany_top_in[14] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 9.13 107.44 9.27 108.8 ; - END - END chany_top_in[14] - PIN chany_top_in[15] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 30.29 107.44 30.43 108.8 ; - END - END chany_top_in[15] - PIN chany_top_in[16] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 33.51 107.44 33.65 108.8 ; - END - END chany_top_in[16] - PIN chany_top_in[17] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 56.89 107.44 57.19 108.8 ; - END - END chany_top_in[17] - PIN chany_top_in[18] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 21.93 107.44 22.23 108.8 ; - END - END chany_top_in[18] - PIN chany_top_in[19] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 52.83 107.44 52.97 108.8 ; - END - END chany_top_in[19] - PIN top_left_grid_pin_1_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 60.19 107.44 60.33 108.8 ; - END - END top_left_grid_pin_1_[0] - PIN chanx_right_in[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 66.49 92 66.79 ; - END - END chanx_right_in[0] - PIN chanx_right_in[1] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 82.81 92 83.11 ; - END - END chanx_right_in[1] - PIN chanx_right_in[2] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 92.33 92 92.63 ; - END - END chanx_right_in[2] - PIN chanx_right_in[3] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 36.57 92 36.87 ; - END - END chanx_right_in[3] - PIN chanx_right_in[4] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 74.65 92 74.95 ; - END - END chanx_right_in[4] - PIN chanx_right_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 77.37 92 77.67 ; - END - END chanx_right_in[5] - PIN chanx_right_in[6] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 33.85 92 34.15 ; - END - END chanx_right_in[6] - PIN chanx_right_in[7] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 46.09 92 46.39 ; - END - END chanx_right_in[7] - PIN chanx_right_in[8] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 56.97 92 57.27 ; - END - END chanx_right_in[8] - PIN chanx_right_in[9] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 73.29 92 73.59 ; - END - END chanx_right_in[9] - PIN chanx_right_in[10] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 84.17 92 84.47 ; - END - END chanx_right_in[10] - PIN chanx_right_in[11] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 90.97 92 91.27 ; - END - END chanx_right_in[11] - PIN chanx_right_in[12] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 81.45 92 81.75 ; - END - END chanx_right_in[12] - PIN chanx_right_in[13] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 44.73 92 45.03 ; - END - END chanx_right_in[13] - PIN chanx_right_in[14] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 31.81 92 32.11 ; - END - END chanx_right_in[14] - PIN chanx_right_in[15] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 61.73 92 62.03 ; - END - END chanx_right_in[15] - PIN chanx_right_in[16] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 65.13 92 65.43 ; - END - END chanx_right_in[16] - PIN chanx_right_in[17] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 48.81 92 49.11 ; - END - END chanx_right_in[17] - PIN chanx_right_in[18] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 69.21 92 69.51 ; - END - END chanx_right_in[18] - PIN chanx_right_in[19] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 89.61 92 89.91 ; - END - END chanx_right_in[19] - PIN right_bottom_grid_pin_34_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 83.65 10.88 83.79 12.24 ; - END - END right_bottom_grid_pin_34_[0] - PIN right_bottom_grid_pin_35_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 85.95 10.88 86.09 12.24 ; - END - END right_bottom_grid_pin_35_[0] - PIN right_bottom_grid_pin_36_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 88.25 10.88 88.39 12.24 ; - END - END right_bottom_grid_pin_36_[0] - PIN right_bottom_grid_pin_37_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 82.73 10.88 82.87 12.24 ; - END - END right_bottom_grid_pin_37_[0] - PIN right_bottom_grid_pin_38_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 85.03 10.88 85.17 12.24 ; - END - END right_bottom_grid_pin_38_[0] - PIN right_bottom_grid_pin_39_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 87.33 10.88 87.47 12.24 ; - END - END right_bottom_grid_pin_39_[0] - PIN right_bottom_grid_pin_40_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 75.83 10.88 75.97 12.24 ; - END - END right_bottom_grid_pin_40_[0] - PIN right_bottom_grid_pin_41_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 80.43 10.88 80.57 12.24 ; - END - END right_bottom_grid_pin_41_[0] - PIN chany_bottom_in[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 61.11 0 61.25 1.36 ; - END - END chany_bottom_in[0] - PIN chany_bottom_in[1] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 60.19 0 60.33 1.36 ; - END - END chany_bottom_in[1] - PIN chany_bottom_in[2] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 44.55 0 44.69 1.36 ; - END - END chany_bottom_in[2] - PIN chany_bottom_in[3] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 46.39 0 46.53 1.36 ; - END - END chany_bottom_in[3] - PIN chany_bottom_in[4] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 58.35 0 58.49 1.36 ; - END - END chany_bottom_in[4] - PIN chany_bottom_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 27.53 0 27.67 1.36 ; - END - END chany_bottom_in[5] - PIN chany_bottom_in[6] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 33.05 0 33.19 1.36 ; - END - END chany_bottom_in[6] - PIN chany_bottom_in[7] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 52.83 0 52.97 1.36 ; - END - END chany_bottom_in[7] - PIN chany_bottom_in[8] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 10.05 0 10.19 1.36 ; - END - END chany_bottom_in[8] - PIN chany_bottom_in[9] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 26.61 0 26.75 1.36 ; - END - END chany_bottom_in[9] - PIN chany_bottom_in[10] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 17.87 0 18.01 1.36 ; - END - END chany_bottom_in[10] - PIN chany_bottom_in[11] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 48.23 0 48.37 1.36 ; - END - END chany_bottom_in[11] - PIN chany_bottom_in[12] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 45.47 0 45.61 1.36 ; - END - END chany_bottom_in[12] - PIN chany_bottom_in[13] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 32.13 0 32.27 1.36 ; - END - END chany_bottom_in[13] - PIN chany_bottom_in[14] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 29.37 0 29.51 1.36 ; - END - END chany_bottom_in[14] - PIN chany_bottom_in[15] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 30.29 0 30.43 1.36 ; - END - END chany_bottom_in[15] - PIN chany_bottom_in[16] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 39.03 0 39.17 1.36 ; - END - END chany_bottom_in[16] - PIN chany_bottom_in[17] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 8.21 0 8.35 1.36 ; - END - END chany_bottom_in[17] - PIN chany_bottom_in[18] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 7.29 0 7.43 1.36 ; - END - END chany_bottom_in[18] - PIN chany_bottom_in[19] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 31.21 0 31.35 1.36 ; - END - END chany_bottom_in[19] - PIN bottom_left_grid_pin_1_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 59.27 0 59.41 1.36 ; - END - END bottom_left_grid_pin_1_[0] - PIN ccff_head[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 43.37 92 43.67 ; - END - END ccff_head[0] - PIN chany_top_out[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 45.47 107.44 45.61 108.8 ; - END - END chany_top_out[0] - PIN chany_top_out[1] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 12.73 107.44 13.03 108.8 ; - END - END chany_top_out[1] - PIN chany_top_out[2] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 47.31 107.44 47.45 108.8 ; - END - END chany_top_out[2] - PIN chany_top_out[3] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 5.37 107.44 5.67 108.8 ; - END - END chany_top_out[3] - PIN chany_top_out[4] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 56.05 107.44 56.19 108.8 ; - END - END chany_top_out[4] - PIN chany_top_out[5] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 46.77 107.44 47.07 108.8 ; - END - END chany_top_out[5] - PIN chany_top_out[6] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 34.81 107.44 35.11 108.8 ; - END - END chany_top_out[6] - PIN chany_top_out[7] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 23.77 107.44 24.07 108.8 ; - END - END chany_top_out[7] - PIN chany_top_out[8] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 7.21 107.44 7.51 108.8 ; - END - END chany_top_out[8] - PIN chany_top_out[9] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 32.97 107.44 33.27 108.8 ; - END - END chany_top_out[9] - PIN chany_top_out[10] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 48.23 107.44 48.37 108.8 ; - END - END chany_top_out[10] - PIN chany_top_out[11] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 48.61 107.44 48.91 108.8 ; - END - END chany_top_out[11] - PIN chany_top_out[12] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 50.99 107.44 51.13 108.8 ; - END - END chany_top_out[12] - PIN chany_top_out[13] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 31.13 107.44 31.43 108.8 ; - END - END chany_top_out[13] - PIN chany_top_out[14] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 9.05 107.44 9.35 108.8 ; - END - END chany_top_out[14] - PIN chany_top_out[15] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 27.45 107.44 27.75 108.8 ; - END - END chany_top_out[15] - PIN chany_top_out[16] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 51.91 107.44 52.05 108.8 ; - END - END chany_top_out[16] - PIN chany_top_out[17] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 52.29 107.44 52.59 108.8 ; - END - END chany_top_out[17] - PIN chany_top_out[18] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 50.45 107.44 50.75 108.8 ; - END - END chany_top_out[18] - PIN chany_top_out[19] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 29.29 107.44 29.59 108.8 ; - END - END chany_top_out[19] - PIN chanx_right_out[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 70.57 92 70.87 ; - END - END chanx_right_out[0] - PIN chanx_right_out[1] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 55.61 92 55.91 ; - END - END chanx_right_out[1] - PIN chanx_right_out[2] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 71.93 92 72.23 ; - END - END chanx_right_out[2] - PIN chanx_right_out[3] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 54.25 92 54.55 ; - END - END chanx_right_out[3] - PIN chanx_right_out[4] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 37.93 92 38.23 ; - END - END chanx_right_out[4] - PIN chanx_right_out[5] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 80.09 92 80.39 ; - END - END chanx_right_out[5] - PIN chanx_right_out[6] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 50.17 92 50.47 ; - END - END chanx_right_out[6] - PIN chanx_right_out[7] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 63.77 92 64.07 ; - END - END chanx_right_out[7] - PIN chanx_right_out[8] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 42.01 92 42.31 ; - END - END chanx_right_out[8] - PIN chanx_right_out[9] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 51.53 92 51.83 ; - END - END chanx_right_out[9] - PIN chanx_right_out[10] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 52.89 92 53.19 ; - END - END chanx_right_out[10] - PIN chanx_right_out[11] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 39.29 92 39.59 ; - END - END chanx_right_out[11] - PIN chanx_right_out[12] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 78.73 92 79.03 ; - END - END chanx_right_out[12] - PIN chanx_right_out[13] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 67.85 92 68.15 ; - END - END chanx_right_out[13] - PIN chanx_right_out[14] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 35.21 92 35.51 ; - END - END chanx_right_out[14] - PIN chanx_right_out[15] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 40.65 92 40.95 ; - END - END chanx_right_out[15] - PIN chanx_right_out[16] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 58.33 92 58.63 ; - END - END chanx_right_out[16] - PIN chanx_right_out[17] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 47.45 92 47.75 ; - END - END chanx_right_out[17] - PIN chanx_right_out[18] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 59.69 92 59.99 ; - END - END chanx_right_out[18] - PIN chanx_right_out[19] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 76.01 92 76.31 ; - END - END chanx_right_out[19] - PIN chany_bottom_out[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 47.31 0 47.45 1.36 ; - END - END chany_bottom_out[0] - PIN chany_bottom_out[1] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 49.15 0 49.29 1.36 ; - END - END chany_bottom_out[1] - PIN chany_bottom_out[2] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 53.75 0 53.89 1.36 ; - END - END chany_bottom_out[2] - PIN chany_bottom_out[3] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 46.77 0 47.07 1.36 ; - END - END chany_bottom_out[3] - PIN chany_bottom_out[4] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 57.43 0 57.57 1.36 ; - END - END chany_bottom_out[4] - PIN chany_bottom_out[5] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 5.37 0 5.67 1.36 ; - END - END chany_bottom_out[5] - PIN chany_bottom_out[6] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 27.45 0 27.75 1.36 ; - END - END chany_bottom_out[6] - PIN chany_bottom_out[7] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 48.61 0 48.91 1.36 ; - END - END chany_bottom_out[7] - PIN chany_bottom_out[8] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 51.91 0 52.05 1.36 ; - END - END chany_bottom_out[8] - PIN chany_bottom_out[9] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 52.29 0 52.59 1.36 ; - END - END chany_bottom_out[9] - PIN chany_bottom_out[10] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 56.05 0 56.19 1.36 ; - END - END chany_bottom_out[10] - PIN chany_bottom_out[11] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 29.29 0 29.59 1.36 ; - END - END chany_bottom_out[11] - PIN chany_bottom_out[12] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 28.45 0 28.59 1.36 ; - END - END chany_bottom_out[12] - PIN chany_bottom_out[13] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 7.21 0 7.51 1.36 ; - END - END chany_bottom_out[13] - PIN chany_bottom_out[14] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 9.05 0 9.35 1.36 ; - END - END chany_bottom_out[14] - PIN chany_bottom_out[15] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 50.45 0 50.75 1.36 ; - END - END chany_bottom_out[15] - PIN chany_bottom_out[16] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 42.71 0 42.85 1.36 ; - END - END chany_bottom_out[16] - PIN chany_bottom_out[17] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 50.07 0 50.21 1.36 ; - END - END chany_bottom_out[17] - PIN chany_bottom_out[18] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 9.13 0 9.27 1.36 ; - END - END chany_bottom_out[18] - PIN chany_bottom_out[19] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 50.99 0 51.13 1.36 ; - END - END chany_bottom_out[19] - PIN ccff_tail[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 40.87 0 41.01 1.36 ; - END - END ccff_tail[0] - PIN VDD - DIRECTION INPUT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0 2.48 0.48 2.96 ; - RECT 65.76 2.48 66.24 2.96 ; - RECT 0 7.92 0.48 8.4 ; - RECT 65.76 7.92 66.24 8.4 ; - RECT 0 13.36 0.48 13.84 ; - RECT 91.52 13.36 92 13.84 ; - RECT 0 18.8 0.48 19.28 ; - RECT 91.52 18.8 92 19.28 ; - RECT 0 24.24 0.48 24.72 ; - RECT 91.52 24.24 92 24.72 ; - RECT 0 29.68 0.48 30.16 ; - RECT 91.52 29.68 92 30.16 ; - RECT 0 35.12 0.48 35.6 ; - RECT 91.52 35.12 92 35.6 ; - RECT 0 40.56 0.48 41.04 ; - RECT 91.52 40.56 92 41.04 ; - RECT 0 46 0.48 46.48 ; - RECT 91.52 46 92 46.48 ; - RECT 0 51.44 0.48 51.92 ; - RECT 91.52 51.44 92 51.92 ; - RECT 0 56.88 0.48 57.36 ; - RECT 91.52 56.88 92 57.36 ; - RECT 0 62.32 0.48 62.8 ; - RECT 91.52 62.32 92 62.8 ; - RECT 0 67.76 0.48 68.24 ; - RECT 91.52 67.76 92 68.24 ; - RECT 0 73.2 0.48 73.68 ; - RECT 91.52 73.2 92 73.68 ; - RECT 0 78.64 0.48 79.12 ; - RECT 91.52 78.64 92 79.12 ; - RECT 0 84.08 0.48 84.56 ; - RECT 91.52 84.08 92 84.56 ; - RECT 0 89.52 0.48 90 ; - RECT 91.52 89.52 92 90 ; - RECT 0 94.96 0.48 95.44 ; - RECT 91.52 94.96 92 95.44 ; - RECT 0 100.4 0.48 100.88 ; - RECT 65.76 100.4 66.24 100.88 ; - RECT 0 105.84 0.48 106.32 ; - RECT 65.76 105.84 66.24 106.32 ; - LAYER met4 ; - RECT 10.74 0 11.34 0.6 ; - RECT 40.18 0 40.78 0.6 ; - RECT 80.66 10.88 81.26 11.48 ; - RECT 80.66 97.32 81.26 97.92 ; - RECT 10.74 108.2 11.34 108.8 ; - RECT 40.18 108.2 40.78 108.8 ; - LAYER met5 ; - RECT 0 22.2 3.2 25.4 ; - RECT 88.8 22.2 92 25.4 ; - RECT 0 63 3.2 66.2 ; - RECT 88.8 63 92 66.2 ; - END - END VDD - PIN VSS - DIRECTION INPUT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0 0 66.24 0.24 ; - RECT 0 5.2 0.48 5.68 ; - RECT 65.76 5.2 66.24 5.68 ; - RECT 0 10.64 92 11.12 ; - RECT 0 16.08 0.48 16.56 ; - RECT 91.52 16.08 92 16.56 ; - RECT 0 21.52 0.48 22 ; - RECT 91.52 21.52 92 22 ; - RECT 0 26.96 0.48 27.44 ; - RECT 91.52 26.96 92 27.44 ; - RECT 0 32.4 0.48 32.88 ; - RECT 91.52 32.4 92 32.88 ; - RECT 0 37.84 0.48 38.32 ; - RECT 91.52 37.84 92 38.32 ; - RECT 0 43.28 0.48 43.76 ; - RECT 91.52 43.28 92 43.76 ; - RECT 0 48.72 0.48 49.2 ; - RECT 91.52 48.72 92 49.2 ; - RECT 0 54.16 0.48 54.64 ; - RECT 91.52 54.16 92 54.64 ; - RECT 0 59.6 0.48 60.08 ; - RECT 91.52 59.6 92 60.08 ; - RECT 0 65.04 0.48 65.52 ; - RECT 91.52 65.04 92 65.52 ; - RECT 0 70.48 0.48 70.96 ; - RECT 91.52 70.48 92 70.96 ; - RECT 0 75.92 0.48 76.4 ; - RECT 91.52 75.92 92 76.4 ; - RECT 0 81.36 0.48 81.84 ; - RECT 91.52 81.36 92 81.84 ; - RECT 0 86.8 0.48 87.28 ; - RECT 91.52 86.8 92 87.28 ; - RECT 0 92.24 0.48 92.72 ; - RECT 91.52 92.24 92 92.72 ; - RECT 0 97.68 92 98.16 ; - RECT 0 103.12 0.48 103.6 ; - RECT 65.76 103.12 66.24 103.6 ; - RECT 0 108.56 66.24 108.8 ; - LAYER met4 ; - RECT 25.46 0 26.06 0.6 ; - RECT 54.9 0 55.5 0.6 ; - RECT 25.46 108.2 26.06 108.8 ; - RECT 54.9 108.2 55.5 108.8 ; - LAYER met5 ; - RECT 0 42.6 3.2 45.8 ; - RECT 88.8 42.6 92 45.8 ; - RECT 0 83.4 3.2 86.6 ; - RECT 88.8 83.4 92 86.6 ; - END - END VSS - PIN prog_clk__FEEDTHRU_1[0] - DIRECTION OUTPUT ; - USE CLOCK ; - PORT - LAYER met2 ; - RECT 73.53 96.56 73.67 97.92 ; - END - END prog_clk__FEEDTHRU_1[0] - OBS - LAYER li1 ; - RECT 0 108.715 66.24 108.885 ; - RECT 65.32 105.995 66.24 106.165 ; - RECT 0 105.995 3.68 106.165 ; - RECT 65.32 103.275 66.24 103.445 ; - RECT 0 103.275 3.68 103.445 ; - RECT 65.32 100.555 66.24 100.725 ; - RECT 0 100.555 3.68 100.725 ; - RECT 63.02 97.835 92 98.005 ; - RECT 0 97.835 3.68 98.005 ; - RECT 91.54 95.115 92 95.285 ; - RECT 0 95.115 3.68 95.285 ; - RECT 91.08 92.395 92 92.565 ; - RECT 0 92.395 3.68 92.565 ; - RECT 91.08 89.675 92 89.845 ; - RECT 0 89.675 3.68 89.845 ; - RECT 88.32 86.955 92 87.125 ; - RECT 0 86.955 3.68 87.125 ; - RECT 88.32 84.235 92 84.405 ; - RECT 0 84.235 3.68 84.405 ; - RECT 91.08 81.515 92 81.685 ; - RECT 0 81.515 3.68 81.685 ; - RECT 91.08 78.795 92 78.965 ; - RECT 0 78.795 3.68 78.965 ; - RECT 91.08 76.075 92 76.245 ; - RECT 0 76.075 3.68 76.245 ; - RECT 91.08 73.355 92 73.525 ; - RECT 0 73.355 3.68 73.525 ; - RECT 91.08 70.635 92 70.805 ; - RECT 0 70.635 3.68 70.805 ; - RECT 91.08 67.915 92 68.085 ; - RECT 0 67.915 3.68 68.085 ; - RECT 91.54 65.195 92 65.365 ; - RECT 0 65.195 3.68 65.365 ; - RECT 91.54 62.475 92 62.645 ; - RECT 0 62.475 3.68 62.645 ; - RECT 91.54 59.755 92 59.925 ; - RECT 0 59.755 3.68 59.925 ; - RECT 91.54 57.035 92 57.205 ; - RECT 0 57.035 3.68 57.205 ; - RECT 91.08 54.315 92 54.485 ; - RECT 0 54.315 3.68 54.485 ; - RECT 91.08 51.595 92 51.765 ; - RECT 0 51.595 3.68 51.765 ; - RECT 91.08 48.875 92 49.045 ; - RECT 0 48.875 3.68 49.045 ; - RECT 91.08 46.155 92 46.325 ; - RECT 0 46.155 3.68 46.325 ; - RECT 88.32 43.435 92 43.605 ; - RECT 0 43.435 3.68 43.605 ; - RECT 88.32 40.715 92 40.885 ; - RECT 0 40.715 3.68 40.885 ; - RECT 91.54 37.995 92 38.165 ; - RECT 0 37.995 3.68 38.165 ; - RECT 91.54 35.275 92 35.445 ; - RECT 0 35.275 3.68 35.445 ; - RECT 91.54 32.555 92 32.725 ; - RECT 0 32.555 3.68 32.725 ; - RECT 91.54 29.835 92 30.005 ; - RECT 0 29.835 3.68 30.005 ; - RECT 91.08 27.115 92 27.285 ; - RECT 0 27.115 3.68 27.285 ; - RECT 91.08 24.395 92 24.565 ; - RECT 0 24.395 3.68 24.565 ; - RECT 91.08 21.675 92 21.845 ; - RECT 0 21.675 3.68 21.845 ; - RECT 91.08 18.955 92 19.125 ; - RECT 0 18.955 3.68 19.125 ; - RECT 88.32 16.235 92 16.405 ; - RECT 0 16.235 3.68 16.405 ; - RECT 88.32 13.515 92 13.685 ; - RECT 0 13.515 3.68 13.685 ; - RECT 63.02 10.795 92 10.965 ; - RECT 0 10.795 3.68 10.965 ; - RECT 65.32 8.075 66.24 8.245 ; - RECT 0 8.075 3.68 8.245 ; - RECT 65.32 5.355 66.24 5.525 ; - RECT 0 5.355 3.68 5.525 ; - RECT 65.78 2.635 66.24 2.805 ; - RECT 0 2.635 3.68 2.805 ; - RECT 0 -0.085 66.24 0.085 ; - LAYER met2 ; - RECT 55.06 108.615 55.34 108.985 ; - RECT 25.62 108.615 25.9 108.985 ; - RECT 83.13 12.42 83.39 12.74 ; - RECT 55.06 -0.185 55.34 0.185 ; - RECT 25.62 -0.185 25.9 0.185 ; - POLYGON 65.96 108.52 65.96 97.64 73.25 97.64 73.25 96.28 73.95 96.28 73.95 97.64 91.72 97.64 91.72 11.16 88.67 11.16 88.67 12.52 87.97 12.52 87.97 11.16 87.75 11.16 87.75 12.52 87.05 12.52 87.05 11.16 86.37 11.16 86.37 12.52 85.67 12.52 85.67 11.16 85.45 11.16 85.45 12.52 84.75 12.52 84.75 11.16 84.07 11.16 84.07 12.52 83.37 12.52 83.37 11.16 83.15 11.16 83.15 12.52 82.45 12.52 82.45 11.16 80.85 11.16 80.85 12.52 80.15 12.52 80.15 11.16 79.01 11.16 79.01 12.52 78.31 12.52 78.31 11.16 76.25 11.16 76.25 12.52 75.55 12.52 75.55 11.16 65.96 11.16 65.96 0.28 61.53 0.28 61.53 1.64 60.83 1.64 60.83 0.28 60.61 0.28 60.61 1.64 59.91 1.64 59.91 0.28 59.69 0.28 59.69 1.64 58.99 1.64 58.99 0.28 58.77 0.28 58.77 1.64 58.07 1.64 58.07 0.28 57.85 0.28 57.85 1.64 57.15 1.64 57.15 0.28 56.47 0.28 56.47 1.64 55.77 1.64 55.77 0.28 54.17 0.28 54.17 1.64 53.47 1.64 53.47 0.28 53.25 0.28 53.25 1.64 52.55 1.64 52.55 0.28 52.33 0.28 52.33 1.64 51.63 1.64 51.63 0.28 51.41 0.28 51.41 1.64 50.71 1.64 50.71 0.28 50.49 0.28 50.49 1.64 49.79 1.64 49.79 0.28 49.57 0.28 49.57 1.64 48.87 1.64 48.87 0.28 48.65 0.28 48.65 1.64 47.95 1.64 47.95 0.28 47.73 0.28 47.73 1.64 47.03 1.64 47.03 0.28 46.81 0.28 46.81 1.64 46.11 1.64 46.11 0.28 45.89 0.28 45.89 1.64 45.19 1.64 45.19 0.28 44.97 0.28 44.97 1.64 44.27 1.64 44.27 0.28 43.13 0.28 43.13 1.64 42.43 1.64 42.43 0.28 41.29 0.28 41.29 1.64 40.59 1.64 40.59 0.28 39.45 0.28 39.45 1.64 38.75 1.64 38.75 0.28 33.47 0.28 33.47 1.64 32.77 1.64 32.77 0.28 32.55 0.28 32.55 1.64 31.85 1.64 31.85 0.28 31.63 0.28 31.63 1.64 30.93 1.64 30.93 0.28 30.71 0.28 30.71 1.64 30.01 1.64 30.01 0.28 29.79 0.28 29.79 1.64 29.09 1.64 29.09 0.28 28.87 0.28 28.87 1.64 28.17 1.64 28.17 0.28 27.95 0.28 27.95 1.64 27.25 1.64 27.25 0.28 27.03 0.28 27.03 1.64 26.33 1.64 26.33 0.28 18.29 0.28 18.29 1.64 17.59 1.64 17.59 0.28 10.47 0.28 10.47 1.64 9.77 1.64 9.77 0.28 9.55 0.28 9.55 1.64 8.85 1.64 8.85 0.28 8.63 0.28 8.63 1.64 7.93 1.64 7.93 0.28 7.71 0.28 7.71 1.64 7.01 1.64 7.01 0.28 0.28 0.28 0.28 108.52 7.93 108.52 7.93 107.16 8.63 107.16 8.63 108.52 8.85 108.52 8.85 107.16 9.55 107.16 9.55 108.52 27.25 108.52 27.25 107.16 27.95 107.16 27.95 108.52 28.17 108.52 28.17 107.16 28.87 107.16 28.87 108.52 29.09 108.52 29.09 107.16 29.79 107.16 29.79 108.52 30.01 108.52 30.01 107.16 30.71 107.16 30.71 108.52 33.23 108.52 33.23 107.16 33.93 107.16 33.93 108.52 39.67 108.52 39.67 107.16 40.37 107.16 40.37 108.52 44.27 108.52 44.27 107.16 44.97 107.16 44.97 108.52 45.19 108.52 45.19 107.16 45.89 107.16 45.89 108.52 46.11 108.52 46.11 107.16 46.81 107.16 46.81 108.52 47.03 108.52 47.03 107.16 47.73 107.16 47.73 108.52 47.95 108.52 47.95 107.16 48.65 107.16 48.65 108.52 48.87 108.52 48.87 107.16 49.57 107.16 49.57 108.52 49.79 108.52 49.79 107.16 50.49 107.16 50.49 108.52 50.71 108.52 50.71 107.16 51.41 107.16 51.41 108.52 51.63 108.52 51.63 107.16 52.33 107.16 52.33 108.52 52.55 108.52 52.55 107.16 53.25 107.16 53.25 108.52 53.47 108.52 53.47 107.16 54.17 107.16 54.17 108.52 55.77 108.52 55.77 107.16 56.47 107.16 56.47 108.52 56.69 108.52 56.69 107.16 57.39 107.16 57.39 108.52 57.61 108.52 57.61 107.16 58.31 107.16 58.31 108.52 59.91 108.52 59.91 107.16 60.61 107.16 60.61 108.52 ; - LAYER met4 ; - POLYGON 65.84 108.4 65.84 97.52 80.26 97.52 80.26 96.92 81.66 96.92 81.66 97.52 91.6 97.52 91.6 11.28 81.66 11.28 81.66 11.88 80.26 11.88 80.26 11.28 65.84 11.28 65.84 0.4 55.9 0.4 55.9 1 54.5 1 54.5 0.4 52.99 0.4 52.99 1.76 51.89 1.76 51.89 0.4 51.15 0.4 51.15 1.76 50.05 1.76 50.05 0.4 49.31 0.4 49.31 1.76 48.21 1.76 48.21 0.4 47.47 0.4 47.47 1.76 46.37 1.76 46.37 0.4 41.18 0.4 41.18 1 39.78 1 39.78 0.4 29.99 0.4 29.99 1.76 28.89 1.76 28.89 0.4 28.15 0.4 28.15 1.76 27.05 1.76 27.05 0.4 26.46 0.4 26.46 1 25.06 1 25.06 0.4 11.74 0.4 11.74 1 10.34 1 10.34 0.4 9.75 0.4 9.75 1.76 8.65 1.76 8.65 0.4 7.91 0.4 7.91 1.76 6.81 1.76 6.81 0.4 6.07 0.4 6.07 1.76 4.97 1.76 4.97 0.4 0.4 0.4 0.4 108.4 4.97 108.4 4.97 107.04 6.07 107.04 6.07 108.4 6.81 108.4 6.81 107.04 7.91 107.04 7.91 108.4 8.65 108.4 8.65 107.04 9.75 107.04 9.75 108.4 10.34 108.4 10.34 107.8 11.74 107.8 11.74 108.4 12.33 108.4 12.33 107.04 13.43 107.04 13.43 108.4 21.53 108.4 21.53 107.04 22.63 107.04 22.63 108.4 23.37 108.4 23.37 107.04 24.47 107.04 24.47 108.4 25.06 108.4 25.06 107.8 26.46 107.8 26.46 108.4 27.05 108.4 27.05 107.04 28.15 107.04 28.15 108.4 28.89 108.4 28.89 107.04 29.99 107.04 29.99 108.4 30.73 108.4 30.73 107.04 31.83 107.04 31.83 108.4 32.57 108.4 32.57 107.04 33.67 107.04 33.67 108.4 34.41 108.4 34.41 107.04 35.51 107.04 35.51 108.4 36.25 108.4 36.25 107.04 37.35 107.04 37.35 108.4 39.78 108.4 39.78 107.8 41.18 107.8 41.18 108.4 44.53 108.4 44.53 107.04 45.63 107.04 45.63 108.4 46.37 108.4 46.37 107.04 47.47 107.04 47.47 108.4 48.21 108.4 48.21 107.04 49.31 107.04 49.31 108.4 50.05 108.4 50.05 107.04 51.15 107.04 51.15 108.4 51.89 108.4 51.89 107.04 52.99 107.04 52.99 108.4 54.5 108.4 54.5 107.8 55.9 107.8 55.9 108.4 56.49 108.4 56.49 107.04 57.59 107.04 57.59 108.4 ; - LAYER met3 ; - POLYGON 55.365 108.965 55.365 108.96 55.58 108.96 55.58 108.64 55.365 108.64 55.365 108.635 55.035 108.635 55.035 108.64 54.82 108.64 54.82 108.96 55.035 108.96 55.035 108.965 ; - POLYGON 25.925 108.965 25.925 108.96 26.14 108.96 26.14 108.64 25.925 108.64 25.925 108.635 25.595 108.635 25.595 108.64 25.38 108.64 25.38 108.96 25.595 108.96 25.595 108.965 ; - POLYGON 90.77 78.35 90.77 78.07 90.22 78.07 90.22 78.05 57.81 78.05 57.81 78.35 ; - POLYGON 90.35 77 90.35 76.68 89.97 76.68 89.97 76.69 75.29 76.69 75.29 76.99 89.97 76.99 89.97 77 ; - POLYGON 90.22 69.51 90.22 68.81 90.31 68.81 90.31 68.53 58.27 68.53 58.27 68.83 90.01 68.83 90.01 69.51 ; - POLYGON 90.77 34.83 90.77 34.55 90.22 34.55 90.22 34.53 32.97 34.53 32.97 34.83 ; - POLYGON 55.365 0.165 55.365 0.16 55.58 0.16 55.58 -0.16 55.365 -0.16 55.365 -0.165 55.035 -0.165 55.035 -0.16 54.82 -0.16 54.82 0.16 55.035 0.16 55.035 0.165 ; - POLYGON 25.925 0.165 25.925 0.16 26.14 0.16 26.14 -0.16 25.925 -0.16 25.925 -0.165 25.595 -0.165 25.595 -0.16 25.38 -0.16 25.38 0.16 25.595 0.16 25.595 0.165 ; - POLYGON 65.84 108.4 65.84 97.52 91.6 97.52 91.6 93.03 90.22 93.03 90.22 91.93 91.6 91.93 91.6 91.67 90.22 91.67 90.22 90.57 91.6 90.57 91.6 90.31 90.22 90.31 90.22 89.21 91.6 89.21 91.6 84.87 90.22 84.87 90.22 83.77 91.6 83.77 91.6 83.51 90.22 83.51 90.22 82.41 91.6 82.41 91.6 82.15 90.22 82.15 90.22 81.05 91.6 81.05 91.6 80.79 90.22 80.79 90.22 79.69 91.6 79.69 91.6 79.43 90.22 79.43 90.22 78.33 91.6 78.33 91.6 78.07 90.22 78.07 90.22 76.97 91.6 76.97 91.6 76.71 90.22 76.71 90.22 75.61 91.6 75.61 91.6 75.35 90.22 75.35 90.22 74.25 91.6 74.25 91.6 73.99 90.22 73.99 90.22 72.89 91.6 72.89 91.6 72.63 90.22 72.63 90.22 71.53 91.6 71.53 91.6 71.27 90.22 71.27 90.22 70.17 91.6 70.17 91.6 69.91 90.22 69.91 90.22 68.81 91.6 68.81 91.6 68.55 90.22 68.55 90.22 67.45 91.6 67.45 91.6 67.19 90.22 67.19 90.22 66.09 91.6 66.09 91.6 65.83 90.22 65.83 90.22 64.73 91.6 64.73 91.6 64.47 90.22 64.47 90.22 63.37 91.6 63.37 91.6 62.43 90.22 62.43 90.22 61.33 91.6 61.33 91.6 60.39 90.22 60.39 90.22 59.29 91.6 59.29 91.6 59.03 90.22 59.03 90.22 57.93 91.6 57.93 91.6 57.67 90.22 57.67 90.22 56.57 91.6 56.57 91.6 56.31 90.22 56.31 90.22 55.21 91.6 55.21 91.6 54.95 90.22 54.95 90.22 53.85 91.6 53.85 91.6 53.59 90.22 53.59 90.22 52.49 91.6 52.49 91.6 52.23 90.22 52.23 90.22 51.13 91.6 51.13 91.6 50.87 90.22 50.87 90.22 49.77 91.6 49.77 91.6 49.51 90.22 49.51 90.22 48.41 91.6 48.41 91.6 48.15 90.22 48.15 90.22 47.05 91.6 47.05 91.6 46.79 90.22 46.79 90.22 45.69 91.6 45.69 91.6 45.43 90.22 45.43 90.22 44.33 91.6 44.33 91.6 44.07 90.22 44.07 90.22 42.97 91.6 42.97 91.6 42.71 90.22 42.71 90.22 41.61 91.6 41.61 91.6 41.35 90.22 41.35 90.22 40.25 91.6 40.25 91.6 39.99 90.22 39.99 90.22 38.89 91.6 38.89 91.6 38.63 90.22 38.63 90.22 37.53 91.6 37.53 91.6 37.27 90.22 37.27 90.22 36.17 91.6 36.17 91.6 35.91 90.22 35.91 90.22 34.81 91.6 34.81 91.6 34.55 90.22 34.55 90.22 33.45 91.6 33.45 91.6 32.51 90.22 32.51 90.22 31.41 91.6 31.41 91.6 11.28 65.84 11.28 65.84 0.4 0.4 0.4 0.4 108.4 ; - LAYER met5 ; - POLYGON 64.64 107.2 64.64 96.32 90.4 96.32 90.4 88.2 87.2 88.2 87.2 81.8 90.4 81.8 90.4 67.8 87.2 67.8 87.2 61.4 90.4 61.4 90.4 47.4 87.2 47.4 87.2 41 90.4 41 90.4 27 87.2 27 87.2 20.6 90.4 20.6 90.4 12.48 64.64 12.48 64.64 1.6 1.6 1.6 1.6 20.6 4.8 20.6 4.8 27 1.6 27 1.6 41 4.8 41 4.8 47.4 1.6 47.4 1.6 61.4 4.8 61.4 4.8 67.8 1.6 67.8 1.6 81.8 4.8 81.8 4.8 88.2 1.6 88.2 1.6 107.2 ; - LAYER met1 ; - POLYGON 47.54 98.57 47.54 98.31 47.22 98.31 47.22 98.37 46.145 98.37 46.145 98.325 45.855 98.325 45.855 98.555 46.145 98.555 46.145 98.51 47.22 98.51 47.22 98.57 ; - POLYGON 65.96 108.28 65.96 106.6 65.48 106.6 65.48 105.56 65.96 105.56 65.96 103.88 65.48 103.88 65.48 102.84 65.96 102.84 65.96 101.16 65.48 101.16 65.48 100.12 65.96 100.12 65.96 98.44 0.28 98.44 0.28 100.12 0.76 100.12 0.76 101.16 0.28 101.16 0.28 102.84 0.76 102.84 0.76 103.88 0.28 103.88 0.28 105.56 0.76 105.56 0.76 106.6 0.28 106.6 0.28 108.28 ; - POLYGON 91.72 97.4 91.72 95.72 91.24 95.72 91.24 94.68 91.72 94.68 91.72 93 91.24 93 91.24 91.96 91.72 91.96 91.72 90.28 91.24 90.28 91.24 89.24 91.72 89.24 91.72 87.56 91.24 87.56 91.24 86.52 91.72 86.52 91.72 84.84 91.24 84.84 91.24 83.8 91.72 83.8 91.72 82.12 91.24 82.12 91.24 81.08 91.72 81.08 91.72 79.4 91.24 79.4 91.24 78.36 91.72 78.36 91.72 76.68 91.24 76.68 91.24 75.64 91.72 75.64 91.72 73.96 91.24 73.96 91.24 72.92 91.72 72.92 91.72 71.24 91.24 71.24 91.24 70.2 91.72 70.2 91.72 68.52 91.24 68.52 91.24 67.48 91.72 67.48 91.72 65.8 91.24 65.8 91.24 64.76 91.72 64.76 91.72 63.08 91.24 63.08 91.24 62.04 91.72 62.04 91.72 60.36 91.24 60.36 91.24 59.32 91.72 59.32 91.72 57.64 91.24 57.64 91.24 56.6 91.72 56.6 91.72 54.92 91.24 54.92 91.24 53.88 91.72 53.88 91.72 52.2 91.24 52.2 91.24 51.16 91.72 51.16 91.72 49.48 91.24 49.48 91.24 48.44 91.72 48.44 91.72 46.76 91.24 46.76 91.24 45.72 91.72 45.72 91.72 44.04 91.24 44.04 91.24 43 91.72 43 91.72 41.32 91.24 41.32 91.24 40.28 91.72 40.28 91.72 38.6 91.24 38.6 91.24 37.56 91.72 37.56 91.72 35.88 91.24 35.88 91.24 34.84 91.72 34.84 91.72 33.16 91.24 33.16 91.24 32.12 91.72 32.12 91.72 30.44 91.24 30.44 91.24 29.4 91.72 29.4 91.72 27.72 91.24 27.72 91.24 26.68 91.72 26.68 91.72 25 91.24 25 91.24 23.96 91.72 23.96 91.72 22.28 91.24 22.28 91.24 21.24 91.72 21.24 91.72 19.56 91.24 19.56 91.24 18.52 91.72 18.52 91.72 16.84 91.24 16.84 91.24 15.8 91.72 15.8 91.72 14.12 91.24 14.12 91.24 13.08 91.72 13.08 91.72 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 0.76 81.08 0.76 82.12 0.28 82.12 0.28 83.8 0.76 83.8 0.76 84.84 0.28 84.84 0.28 86.52 0.76 86.52 0.76 87.56 0.28 87.56 0.28 89.24 0.76 89.24 0.76 90.28 0.28 90.28 0.28 91.96 0.76 91.96 0.76 93 0.28 93 0.28 94.68 0.76 94.68 0.76 95.72 0.28 95.72 0.28 97.4 ; - POLYGON 65.96 10.36 65.96 8.68 65.48 8.68 65.48 7.64 65.96 7.64 65.96 5.96 65.48 5.96 65.48 4.92 65.96 4.92 65.96 3.24 65.48 3.24 65.48 2.2 65.96 2.2 65.96 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 ; - LAYER li1 ; - POLYGON 66.07 108.63 66.07 97.75 91.83 97.75 91.83 11.05 66.07 11.05 66.07 0.17 0.17 0.17 0.17 108.63 ; - LAYER mcon ; - RECT 65.925 108.715 66.095 108.885 ; - RECT 65.465 108.715 65.635 108.885 ; - RECT 65.005 108.715 65.175 108.885 ; - RECT 64.545 108.715 64.715 108.885 ; - RECT 64.085 108.715 64.255 108.885 ; - RECT 63.625 108.715 63.795 108.885 ; - RECT 63.165 108.715 63.335 108.885 ; - RECT 62.705 108.715 62.875 108.885 ; - RECT 62.245 108.715 62.415 108.885 ; - RECT 61.785 108.715 61.955 108.885 ; - RECT 61.325 108.715 61.495 108.885 ; - RECT 60.865 108.715 61.035 108.885 ; - RECT 60.405 108.715 60.575 108.885 ; - RECT 59.945 108.715 60.115 108.885 ; - RECT 59.485 108.715 59.655 108.885 ; - RECT 59.025 108.715 59.195 108.885 ; - RECT 58.565 108.715 58.735 108.885 ; - RECT 58.105 108.715 58.275 108.885 ; - RECT 57.645 108.715 57.815 108.885 ; - RECT 57.185 108.715 57.355 108.885 ; - RECT 56.725 108.715 56.895 108.885 ; - RECT 56.265 108.715 56.435 108.885 ; - RECT 55.805 108.715 55.975 108.885 ; - RECT 55.345 108.715 55.515 108.885 ; - RECT 54.885 108.715 55.055 108.885 ; - RECT 54.425 108.715 54.595 108.885 ; - RECT 53.965 108.715 54.135 108.885 ; - RECT 53.505 108.715 53.675 108.885 ; - RECT 53.045 108.715 53.215 108.885 ; - RECT 52.585 108.715 52.755 108.885 ; - RECT 52.125 108.715 52.295 108.885 ; - RECT 51.665 108.715 51.835 108.885 ; - RECT 51.205 108.715 51.375 108.885 ; - RECT 50.745 108.715 50.915 108.885 ; - RECT 50.285 108.715 50.455 108.885 ; - RECT 49.825 108.715 49.995 108.885 ; - RECT 49.365 108.715 49.535 108.885 ; - RECT 48.905 108.715 49.075 108.885 ; - RECT 48.445 108.715 48.615 108.885 ; - RECT 47.985 108.715 48.155 108.885 ; - RECT 47.525 108.715 47.695 108.885 ; - RECT 47.065 108.715 47.235 108.885 ; - RECT 46.605 108.715 46.775 108.885 ; - RECT 46.145 108.715 46.315 108.885 ; - RECT 45.685 108.715 45.855 108.885 ; - RECT 45.225 108.715 45.395 108.885 ; - RECT 44.765 108.715 44.935 108.885 ; - RECT 44.305 108.715 44.475 108.885 ; - RECT 43.845 108.715 44.015 108.885 ; - RECT 43.385 108.715 43.555 108.885 ; - RECT 42.925 108.715 43.095 108.885 ; - RECT 42.465 108.715 42.635 108.885 ; - RECT 42.005 108.715 42.175 108.885 ; - RECT 41.545 108.715 41.715 108.885 ; - RECT 41.085 108.715 41.255 108.885 ; - RECT 40.625 108.715 40.795 108.885 ; - RECT 40.165 108.715 40.335 108.885 ; - RECT 39.705 108.715 39.875 108.885 ; - RECT 39.245 108.715 39.415 108.885 ; - RECT 38.785 108.715 38.955 108.885 ; - RECT 38.325 108.715 38.495 108.885 ; - RECT 37.865 108.715 38.035 108.885 ; - RECT 37.405 108.715 37.575 108.885 ; - RECT 36.945 108.715 37.115 108.885 ; - RECT 36.485 108.715 36.655 108.885 ; - RECT 36.025 108.715 36.195 108.885 ; - RECT 35.565 108.715 35.735 108.885 ; - RECT 35.105 108.715 35.275 108.885 ; - RECT 34.645 108.715 34.815 108.885 ; - RECT 34.185 108.715 34.355 108.885 ; - RECT 33.725 108.715 33.895 108.885 ; - RECT 33.265 108.715 33.435 108.885 ; - RECT 32.805 108.715 32.975 108.885 ; - RECT 32.345 108.715 32.515 108.885 ; - RECT 31.885 108.715 32.055 108.885 ; - RECT 31.425 108.715 31.595 108.885 ; - RECT 30.965 108.715 31.135 108.885 ; - RECT 30.505 108.715 30.675 108.885 ; - RECT 30.045 108.715 30.215 108.885 ; - RECT 29.585 108.715 29.755 108.885 ; - RECT 29.125 108.715 29.295 108.885 ; - RECT 28.665 108.715 28.835 108.885 ; - RECT 28.205 108.715 28.375 108.885 ; - RECT 27.745 108.715 27.915 108.885 ; - RECT 27.285 108.715 27.455 108.885 ; - RECT 26.825 108.715 26.995 108.885 ; - RECT 26.365 108.715 26.535 108.885 ; - RECT 25.905 108.715 26.075 108.885 ; - RECT 25.445 108.715 25.615 108.885 ; - RECT 24.985 108.715 25.155 108.885 ; - RECT 24.525 108.715 24.695 108.885 ; - RECT 24.065 108.715 24.235 108.885 ; - RECT 23.605 108.715 23.775 108.885 ; - RECT 23.145 108.715 23.315 108.885 ; - RECT 22.685 108.715 22.855 108.885 ; - RECT 22.225 108.715 22.395 108.885 ; - RECT 21.765 108.715 21.935 108.885 ; - RECT 21.305 108.715 21.475 108.885 ; - RECT 20.845 108.715 21.015 108.885 ; - RECT 20.385 108.715 20.555 108.885 ; - RECT 19.925 108.715 20.095 108.885 ; - RECT 19.465 108.715 19.635 108.885 ; - RECT 19.005 108.715 19.175 108.885 ; - RECT 18.545 108.715 18.715 108.885 ; - RECT 18.085 108.715 18.255 108.885 ; - RECT 17.625 108.715 17.795 108.885 ; - RECT 17.165 108.715 17.335 108.885 ; - RECT 16.705 108.715 16.875 108.885 ; - RECT 16.245 108.715 16.415 108.885 ; - RECT 15.785 108.715 15.955 108.885 ; - RECT 15.325 108.715 15.495 108.885 ; - RECT 14.865 108.715 15.035 108.885 ; - RECT 14.405 108.715 14.575 108.885 ; - RECT 13.945 108.715 14.115 108.885 ; - RECT 13.485 108.715 13.655 108.885 ; - RECT 13.025 108.715 13.195 108.885 ; - RECT 12.565 108.715 12.735 108.885 ; - RECT 12.105 108.715 12.275 108.885 ; - RECT 11.645 108.715 11.815 108.885 ; - RECT 11.185 108.715 11.355 108.885 ; - RECT 10.725 108.715 10.895 108.885 ; - RECT 10.265 108.715 10.435 108.885 ; - RECT 9.805 108.715 9.975 108.885 ; - RECT 9.345 108.715 9.515 108.885 ; - RECT 8.885 108.715 9.055 108.885 ; - RECT 8.425 108.715 8.595 108.885 ; - RECT 7.965 108.715 8.135 108.885 ; - RECT 7.505 108.715 7.675 108.885 ; - RECT 7.045 108.715 7.215 108.885 ; - RECT 6.585 108.715 6.755 108.885 ; - RECT 6.125 108.715 6.295 108.885 ; - RECT 5.665 108.715 5.835 108.885 ; - RECT 5.205 108.715 5.375 108.885 ; - RECT 4.745 108.715 4.915 108.885 ; - RECT 4.285 108.715 4.455 108.885 ; - RECT 3.825 108.715 3.995 108.885 ; - RECT 3.365 108.715 3.535 108.885 ; - RECT 2.905 108.715 3.075 108.885 ; - RECT 2.445 108.715 2.615 108.885 ; - RECT 1.985 108.715 2.155 108.885 ; - RECT 1.525 108.715 1.695 108.885 ; - RECT 1.065 108.715 1.235 108.885 ; - RECT 0.605 108.715 0.775 108.885 ; - RECT 0.145 108.715 0.315 108.885 ; - RECT 65.925 105.995 66.095 106.165 ; - RECT 65.465 105.995 65.635 106.165 ; - RECT 0.605 105.995 0.775 106.165 ; - RECT 0.145 105.995 0.315 106.165 ; - RECT 65.925 103.275 66.095 103.445 ; - RECT 65.465 103.275 65.635 103.445 ; - RECT 0.605 103.275 0.775 103.445 ; - RECT 0.145 103.275 0.315 103.445 ; - RECT 65.925 100.555 66.095 100.725 ; - RECT 65.465 100.555 65.635 100.725 ; - RECT 0.605 100.555 0.775 100.725 ; - RECT 0.145 100.555 0.315 100.725 ; - RECT 45.915 98.355 46.085 98.525 ; - RECT 91.685 97.835 91.855 98.005 ; - RECT 91.225 97.835 91.395 98.005 ; - RECT 90.765 97.835 90.935 98.005 ; - RECT 90.305 97.835 90.475 98.005 ; - RECT 89.845 97.835 90.015 98.005 ; - RECT 89.385 97.835 89.555 98.005 ; - RECT 88.925 97.835 89.095 98.005 ; - RECT 88.465 97.835 88.635 98.005 ; - RECT 88.005 97.835 88.175 98.005 ; - RECT 87.545 97.835 87.715 98.005 ; - RECT 87.085 97.835 87.255 98.005 ; - RECT 86.625 97.835 86.795 98.005 ; - RECT 86.165 97.835 86.335 98.005 ; - RECT 85.705 97.835 85.875 98.005 ; - RECT 85.245 97.835 85.415 98.005 ; - RECT 84.785 97.835 84.955 98.005 ; - RECT 84.325 97.835 84.495 98.005 ; - RECT 83.865 97.835 84.035 98.005 ; - RECT 83.405 97.835 83.575 98.005 ; - RECT 82.945 97.835 83.115 98.005 ; - RECT 82.485 97.835 82.655 98.005 ; - RECT 82.025 97.835 82.195 98.005 ; - RECT 81.565 97.835 81.735 98.005 ; - RECT 81.105 97.835 81.275 98.005 ; - RECT 80.645 97.835 80.815 98.005 ; - RECT 80.185 97.835 80.355 98.005 ; - RECT 79.725 97.835 79.895 98.005 ; - RECT 79.265 97.835 79.435 98.005 ; - RECT 78.805 97.835 78.975 98.005 ; - RECT 78.345 97.835 78.515 98.005 ; - RECT 77.885 97.835 78.055 98.005 ; - RECT 77.425 97.835 77.595 98.005 ; - RECT 76.965 97.835 77.135 98.005 ; - RECT 76.505 97.835 76.675 98.005 ; - RECT 76.045 97.835 76.215 98.005 ; - RECT 75.585 97.835 75.755 98.005 ; - RECT 75.125 97.835 75.295 98.005 ; - RECT 74.665 97.835 74.835 98.005 ; - RECT 74.205 97.835 74.375 98.005 ; - RECT 73.745 97.835 73.915 98.005 ; - RECT 73.285 97.835 73.455 98.005 ; - RECT 72.825 97.835 72.995 98.005 ; - RECT 72.365 97.835 72.535 98.005 ; - RECT 71.905 97.835 72.075 98.005 ; - RECT 71.445 97.835 71.615 98.005 ; - RECT 70.985 97.835 71.155 98.005 ; - RECT 70.525 97.835 70.695 98.005 ; - RECT 70.065 97.835 70.235 98.005 ; - RECT 69.605 97.835 69.775 98.005 ; - RECT 69.145 97.835 69.315 98.005 ; - RECT 68.685 97.835 68.855 98.005 ; - RECT 68.225 97.835 68.395 98.005 ; - RECT 67.765 97.835 67.935 98.005 ; - RECT 67.305 97.835 67.475 98.005 ; - RECT 66.845 97.835 67.015 98.005 ; - RECT 66.385 97.835 66.555 98.005 ; - RECT 65.925 97.835 66.095 98.005 ; - RECT 65.465 97.835 65.635 98.005 ; - RECT 65.005 97.835 65.175 98.005 ; - RECT 64.545 97.835 64.715 98.005 ; - RECT 64.085 97.835 64.255 98.005 ; - RECT 63.625 97.835 63.795 98.005 ; - RECT 63.165 97.835 63.335 98.005 ; - RECT 62.705 97.835 62.875 98.005 ; - RECT 62.245 97.835 62.415 98.005 ; - RECT 61.785 97.835 61.955 98.005 ; - RECT 61.325 97.835 61.495 98.005 ; - RECT 60.865 97.835 61.035 98.005 ; - RECT 60.405 97.835 60.575 98.005 ; - RECT 59.945 97.835 60.115 98.005 ; - RECT 59.485 97.835 59.655 98.005 ; - RECT 59.025 97.835 59.195 98.005 ; - RECT 58.565 97.835 58.735 98.005 ; - RECT 58.105 97.835 58.275 98.005 ; - RECT 57.645 97.835 57.815 98.005 ; - RECT 57.185 97.835 57.355 98.005 ; - RECT 56.725 97.835 56.895 98.005 ; - RECT 56.265 97.835 56.435 98.005 ; - RECT 55.805 97.835 55.975 98.005 ; - RECT 55.345 97.835 55.515 98.005 ; - RECT 54.885 97.835 55.055 98.005 ; - RECT 54.425 97.835 54.595 98.005 ; - RECT 53.965 97.835 54.135 98.005 ; - RECT 53.505 97.835 53.675 98.005 ; - RECT 53.045 97.835 53.215 98.005 ; - RECT 52.585 97.835 52.755 98.005 ; - RECT 52.125 97.835 52.295 98.005 ; - RECT 51.665 97.835 51.835 98.005 ; - RECT 51.205 97.835 51.375 98.005 ; - RECT 50.745 97.835 50.915 98.005 ; - RECT 50.285 97.835 50.455 98.005 ; - RECT 49.825 97.835 49.995 98.005 ; - RECT 49.365 97.835 49.535 98.005 ; - RECT 48.905 97.835 49.075 98.005 ; - RECT 48.445 97.835 48.615 98.005 ; - RECT 47.985 97.835 48.155 98.005 ; - RECT 47.525 97.835 47.695 98.005 ; - RECT 47.065 97.835 47.235 98.005 ; - RECT 46.605 97.835 46.775 98.005 ; - RECT 46.145 97.835 46.315 98.005 ; - RECT 45.685 97.835 45.855 98.005 ; - RECT 45.225 97.835 45.395 98.005 ; - RECT 44.765 97.835 44.935 98.005 ; - RECT 44.305 97.835 44.475 98.005 ; - RECT 43.845 97.835 44.015 98.005 ; - RECT 43.385 97.835 43.555 98.005 ; - RECT 42.925 97.835 43.095 98.005 ; - RECT 42.465 97.835 42.635 98.005 ; - RECT 42.005 97.835 42.175 98.005 ; - RECT 41.545 97.835 41.715 98.005 ; - RECT 41.085 97.835 41.255 98.005 ; - RECT 40.625 97.835 40.795 98.005 ; - RECT 40.165 97.835 40.335 98.005 ; - RECT 39.705 97.835 39.875 98.005 ; - RECT 39.245 97.835 39.415 98.005 ; - RECT 38.785 97.835 38.955 98.005 ; - RECT 38.325 97.835 38.495 98.005 ; - RECT 37.865 97.835 38.035 98.005 ; - RECT 37.405 97.835 37.575 98.005 ; - RECT 36.945 97.835 37.115 98.005 ; - RECT 36.485 97.835 36.655 98.005 ; - RECT 36.025 97.835 36.195 98.005 ; - RECT 35.565 97.835 35.735 98.005 ; - RECT 35.105 97.835 35.275 98.005 ; - RECT 34.645 97.835 34.815 98.005 ; - RECT 34.185 97.835 34.355 98.005 ; - RECT 33.725 97.835 33.895 98.005 ; - RECT 33.265 97.835 33.435 98.005 ; - RECT 32.805 97.835 32.975 98.005 ; - RECT 32.345 97.835 32.515 98.005 ; - RECT 31.885 97.835 32.055 98.005 ; - RECT 31.425 97.835 31.595 98.005 ; - RECT 30.965 97.835 31.135 98.005 ; - RECT 30.505 97.835 30.675 98.005 ; - RECT 30.045 97.835 30.215 98.005 ; - RECT 29.585 97.835 29.755 98.005 ; - RECT 29.125 97.835 29.295 98.005 ; - RECT 28.665 97.835 28.835 98.005 ; - RECT 28.205 97.835 28.375 98.005 ; - RECT 27.745 97.835 27.915 98.005 ; - RECT 27.285 97.835 27.455 98.005 ; - RECT 26.825 97.835 26.995 98.005 ; - RECT 26.365 97.835 26.535 98.005 ; - RECT 25.905 97.835 26.075 98.005 ; - RECT 25.445 97.835 25.615 98.005 ; - RECT 24.985 97.835 25.155 98.005 ; - RECT 24.525 97.835 24.695 98.005 ; - RECT 24.065 97.835 24.235 98.005 ; - RECT 23.605 97.835 23.775 98.005 ; - RECT 23.145 97.835 23.315 98.005 ; - RECT 22.685 97.835 22.855 98.005 ; - RECT 22.225 97.835 22.395 98.005 ; - RECT 21.765 97.835 21.935 98.005 ; - RECT 21.305 97.835 21.475 98.005 ; - RECT 20.845 97.835 21.015 98.005 ; - RECT 20.385 97.835 20.555 98.005 ; - RECT 19.925 97.835 20.095 98.005 ; - RECT 19.465 97.835 19.635 98.005 ; - RECT 19.005 97.835 19.175 98.005 ; - RECT 18.545 97.835 18.715 98.005 ; - RECT 18.085 97.835 18.255 98.005 ; - RECT 17.625 97.835 17.795 98.005 ; - RECT 17.165 97.835 17.335 98.005 ; - RECT 16.705 97.835 16.875 98.005 ; - RECT 16.245 97.835 16.415 98.005 ; - RECT 15.785 97.835 15.955 98.005 ; - RECT 15.325 97.835 15.495 98.005 ; - RECT 14.865 97.835 15.035 98.005 ; - RECT 14.405 97.835 14.575 98.005 ; - RECT 13.945 97.835 14.115 98.005 ; - RECT 13.485 97.835 13.655 98.005 ; - RECT 13.025 97.835 13.195 98.005 ; - RECT 12.565 97.835 12.735 98.005 ; - RECT 12.105 97.835 12.275 98.005 ; - RECT 11.645 97.835 11.815 98.005 ; - RECT 11.185 97.835 11.355 98.005 ; - RECT 10.725 97.835 10.895 98.005 ; - RECT 10.265 97.835 10.435 98.005 ; - RECT 9.805 97.835 9.975 98.005 ; - RECT 9.345 97.835 9.515 98.005 ; - RECT 8.885 97.835 9.055 98.005 ; - RECT 8.425 97.835 8.595 98.005 ; - RECT 7.965 97.835 8.135 98.005 ; - RECT 7.505 97.835 7.675 98.005 ; - RECT 7.045 97.835 7.215 98.005 ; - RECT 6.585 97.835 6.755 98.005 ; - RECT 6.125 97.835 6.295 98.005 ; - RECT 5.665 97.835 5.835 98.005 ; - RECT 5.205 97.835 5.375 98.005 ; - RECT 4.745 97.835 4.915 98.005 ; - RECT 4.285 97.835 4.455 98.005 ; - RECT 3.825 97.835 3.995 98.005 ; - RECT 3.365 97.835 3.535 98.005 ; - RECT 2.905 97.835 3.075 98.005 ; - RECT 2.445 97.835 2.615 98.005 ; - RECT 1.985 97.835 2.155 98.005 ; - RECT 1.525 97.835 1.695 98.005 ; - RECT 1.065 97.835 1.235 98.005 ; - RECT 0.605 97.835 0.775 98.005 ; - RECT 0.145 97.835 0.315 98.005 ; - RECT 91.685 95.115 91.855 95.285 ; - RECT 91.225 95.115 91.395 95.285 ; - RECT 0.605 95.115 0.775 95.285 ; - RECT 0.145 95.115 0.315 95.285 ; - RECT 91.685 92.395 91.855 92.565 ; - RECT 91.225 92.395 91.395 92.565 ; - RECT 0.605 92.395 0.775 92.565 ; - RECT 0.145 92.395 0.315 92.565 ; - RECT 91.685 89.675 91.855 89.845 ; - RECT 91.225 89.675 91.395 89.845 ; - RECT 0.605 89.675 0.775 89.845 ; - RECT 0.145 89.675 0.315 89.845 ; - RECT 91.685 86.955 91.855 87.125 ; - RECT 91.225 86.955 91.395 87.125 ; - RECT 0.605 86.955 0.775 87.125 ; - RECT 0.145 86.955 0.315 87.125 ; - RECT 91.685 84.235 91.855 84.405 ; - RECT 91.225 84.235 91.395 84.405 ; - RECT 0.605 84.235 0.775 84.405 ; - RECT 0.145 84.235 0.315 84.405 ; - RECT 91.685 81.515 91.855 81.685 ; - RECT 91.225 81.515 91.395 81.685 ; - RECT 0.605 81.515 0.775 81.685 ; - RECT 0.145 81.515 0.315 81.685 ; - RECT 91.685 78.795 91.855 78.965 ; - RECT 91.225 78.795 91.395 78.965 ; - RECT 0.605 78.795 0.775 78.965 ; - RECT 0.145 78.795 0.315 78.965 ; - RECT 91.685 76.075 91.855 76.245 ; - RECT 91.225 76.075 91.395 76.245 ; - RECT 0.605 76.075 0.775 76.245 ; - RECT 0.145 76.075 0.315 76.245 ; - RECT 91.685 73.355 91.855 73.525 ; - RECT 91.225 73.355 91.395 73.525 ; - RECT 0.605 73.355 0.775 73.525 ; - RECT 0.145 73.355 0.315 73.525 ; - RECT 91.685 70.635 91.855 70.805 ; - RECT 91.225 70.635 91.395 70.805 ; - RECT 0.605 70.635 0.775 70.805 ; - RECT 0.145 70.635 0.315 70.805 ; - RECT 91.685 67.915 91.855 68.085 ; - RECT 91.225 67.915 91.395 68.085 ; - RECT 0.605 67.915 0.775 68.085 ; - RECT 0.145 67.915 0.315 68.085 ; - RECT 91.685 65.195 91.855 65.365 ; - RECT 91.225 65.195 91.395 65.365 ; - RECT 0.605 65.195 0.775 65.365 ; - RECT 0.145 65.195 0.315 65.365 ; - RECT 91.685 62.475 91.855 62.645 ; - RECT 91.225 62.475 91.395 62.645 ; - RECT 0.605 62.475 0.775 62.645 ; - RECT 0.145 62.475 0.315 62.645 ; - RECT 91.685 59.755 91.855 59.925 ; - RECT 91.225 59.755 91.395 59.925 ; - RECT 0.605 59.755 0.775 59.925 ; - RECT 0.145 59.755 0.315 59.925 ; - RECT 91.685 57.035 91.855 57.205 ; - RECT 91.225 57.035 91.395 57.205 ; - RECT 0.605 57.035 0.775 57.205 ; - RECT 0.145 57.035 0.315 57.205 ; - RECT 91.685 54.315 91.855 54.485 ; - RECT 91.225 54.315 91.395 54.485 ; - RECT 0.605 54.315 0.775 54.485 ; - RECT 0.145 54.315 0.315 54.485 ; - RECT 91.685 51.595 91.855 51.765 ; - RECT 91.225 51.595 91.395 51.765 ; - RECT 0.605 51.595 0.775 51.765 ; - RECT 0.145 51.595 0.315 51.765 ; - RECT 91.685 48.875 91.855 49.045 ; - RECT 91.225 48.875 91.395 49.045 ; - RECT 0.605 48.875 0.775 49.045 ; - RECT 0.145 48.875 0.315 49.045 ; - RECT 91.685 46.155 91.855 46.325 ; - RECT 91.225 46.155 91.395 46.325 ; - RECT 0.605 46.155 0.775 46.325 ; - RECT 0.145 46.155 0.315 46.325 ; - RECT 91.685 43.435 91.855 43.605 ; - RECT 91.225 43.435 91.395 43.605 ; - RECT 0.605 43.435 0.775 43.605 ; - RECT 0.145 43.435 0.315 43.605 ; - RECT 91.685 40.715 91.855 40.885 ; - RECT 91.225 40.715 91.395 40.885 ; - RECT 0.605 40.715 0.775 40.885 ; - RECT 0.145 40.715 0.315 40.885 ; - RECT 91.685 37.995 91.855 38.165 ; - RECT 91.225 37.995 91.395 38.165 ; - RECT 0.605 37.995 0.775 38.165 ; - RECT 0.145 37.995 0.315 38.165 ; - RECT 91.685 35.275 91.855 35.445 ; - RECT 91.225 35.275 91.395 35.445 ; - RECT 0.605 35.275 0.775 35.445 ; - RECT 0.145 35.275 0.315 35.445 ; - RECT 91.685 32.555 91.855 32.725 ; - RECT 91.225 32.555 91.395 32.725 ; - RECT 0.605 32.555 0.775 32.725 ; - RECT 0.145 32.555 0.315 32.725 ; - RECT 91.685 29.835 91.855 30.005 ; - RECT 91.225 29.835 91.395 30.005 ; - RECT 0.605 29.835 0.775 30.005 ; - RECT 0.145 29.835 0.315 30.005 ; - RECT 91.685 27.115 91.855 27.285 ; - RECT 91.225 27.115 91.395 27.285 ; - RECT 0.605 27.115 0.775 27.285 ; - RECT 0.145 27.115 0.315 27.285 ; - RECT 91.685 24.395 91.855 24.565 ; - RECT 91.225 24.395 91.395 24.565 ; - RECT 0.605 24.395 0.775 24.565 ; - RECT 0.145 24.395 0.315 24.565 ; - RECT 91.685 21.675 91.855 21.845 ; - RECT 91.225 21.675 91.395 21.845 ; - RECT 0.605 21.675 0.775 21.845 ; - RECT 0.145 21.675 0.315 21.845 ; - RECT 91.685 18.955 91.855 19.125 ; - RECT 91.225 18.955 91.395 19.125 ; - RECT 0.605 18.955 0.775 19.125 ; - RECT 0.145 18.955 0.315 19.125 ; - RECT 91.685 16.235 91.855 16.405 ; - RECT 91.225 16.235 91.395 16.405 ; - RECT 0.605 16.235 0.775 16.405 ; - RECT 0.145 16.235 0.315 16.405 ; - RECT 91.685 13.515 91.855 13.685 ; - RECT 91.225 13.515 91.395 13.685 ; - RECT 0.605 13.515 0.775 13.685 ; - RECT 0.145 13.515 0.315 13.685 ; - RECT 91.685 10.795 91.855 10.965 ; - RECT 91.225 10.795 91.395 10.965 ; - RECT 90.765 10.795 90.935 10.965 ; - RECT 90.305 10.795 90.475 10.965 ; - RECT 89.845 10.795 90.015 10.965 ; - RECT 89.385 10.795 89.555 10.965 ; - RECT 88.925 10.795 89.095 10.965 ; - RECT 88.465 10.795 88.635 10.965 ; - RECT 88.005 10.795 88.175 10.965 ; - RECT 87.545 10.795 87.715 10.965 ; - RECT 87.085 10.795 87.255 10.965 ; - RECT 86.625 10.795 86.795 10.965 ; - RECT 86.165 10.795 86.335 10.965 ; - RECT 85.705 10.795 85.875 10.965 ; - RECT 85.245 10.795 85.415 10.965 ; - RECT 84.785 10.795 84.955 10.965 ; - RECT 84.325 10.795 84.495 10.965 ; - RECT 83.865 10.795 84.035 10.965 ; - RECT 83.405 10.795 83.575 10.965 ; - RECT 82.945 10.795 83.115 10.965 ; - RECT 82.485 10.795 82.655 10.965 ; - RECT 82.025 10.795 82.195 10.965 ; - RECT 81.565 10.795 81.735 10.965 ; - RECT 81.105 10.795 81.275 10.965 ; - RECT 80.645 10.795 80.815 10.965 ; - RECT 80.185 10.795 80.355 10.965 ; - RECT 79.725 10.795 79.895 10.965 ; - RECT 79.265 10.795 79.435 10.965 ; - RECT 78.805 10.795 78.975 10.965 ; - RECT 78.345 10.795 78.515 10.965 ; - RECT 77.885 10.795 78.055 10.965 ; - RECT 77.425 10.795 77.595 10.965 ; - RECT 76.965 10.795 77.135 10.965 ; - RECT 76.505 10.795 76.675 10.965 ; - RECT 76.045 10.795 76.215 10.965 ; - RECT 75.585 10.795 75.755 10.965 ; - RECT 75.125 10.795 75.295 10.965 ; - RECT 74.665 10.795 74.835 10.965 ; - RECT 74.205 10.795 74.375 10.965 ; - RECT 73.745 10.795 73.915 10.965 ; - RECT 73.285 10.795 73.455 10.965 ; - RECT 72.825 10.795 72.995 10.965 ; - RECT 72.365 10.795 72.535 10.965 ; - RECT 71.905 10.795 72.075 10.965 ; - RECT 71.445 10.795 71.615 10.965 ; - RECT 70.985 10.795 71.155 10.965 ; - RECT 70.525 10.795 70.695 10.965 ; - RECT 70.065 10.795 70.235 10.965 ; - RECT 69.605 10.795 69.775 10.965 ; - RECT 69.145 10.795 69.315 10.965 ; - RECT 68.685 10.795 68.855 10.965 ; - RECT 68.225 10.795 68.395 10.965 ; - RECT 67.765 10.795 67.935 10.965 ; - RECT 67.305 10.795 67.475 10.965 ; - RECT 66.845 10.795 67.015 10.965 ; - RECT 66.385 10.795 66.555 10.965 ; - RECT 65.925 10.795 66.095 10.965 ; - RECT 65.465 10.795 65.635 10.965 ; - RECT 65.005 10.795 65.175 10.965 ; - RECT 64.545 10.795 64.715 10.965 ; - RECT 64.085 10.795 64.255 10.965 ; - RECT 63.625 10.795 63.795 10.965 ; - RECT 63.165 10.795 63.335 10.965 ; - RECT 62.705 10.795 62.875 10.965 ; - RECT 62.245 10.795 62.415 10.965 ; - RECT 61.785 10.795 61.955 10.965 ; - RECT 61.325 10.795 61.495 10.965 ; - RECT 60.865 10.795 61.035 10.965 ; - RECT 60.405 10.795 60.575 10.965 ; - RECT 59.945 10.795 60.115 10.965 ; - RECT 59.485 10.795 59.655 10.965 ; - RECT 59.025 10.795 59.195 10.965 ; - RECT 58.565 10.795 58.735 10.965 ; - RECT 58.105 10.795 58.275 10.965 ; - RECT 57.645 10.795 57.815 10.965 ; - RECT 57.185 10.795 57.355 10.965 ; - RECT 56.725 10.795 56.895 10.965 ; - RECT 56.265 10.795 56.435 10.965 ; - RECT 55.805 10.795 55.975 10.965 ; - RECT 55.345 10.795 55.515 10.965 ; - RECT 54.885 10.795 55.055 10.965 ; - RECT 54.425 10.795 54.595 10.965 ; - RECT 53.965 10.795 54.135 10.965 ; - RECT 53.505 10.795 53.675 10.965 ; - RECT 53.045 10.795 53.215 10.965 ; - RECT 52.585 10.795 52.755 10.965 ; - RECT 52.125 10.795 52.295 10.965 ; - RECT 51.665 10.795 51.835 10.965 ; - RECT 51.205 10.795 51.375 10.965 ; - RECT 50.745 10.795 50.915 10.965 ; - RECT 50.285 10.795 50.455 10.965 ; - RECT 49.825 10.795 49.995 10.965 ; - RECT 49.365 10.795 49.535 10.965 ; - RECT 48.905 10.795 49.075 10.965 ; - RECT 48.445 10.795 48.615 10.965 ; - RECT 47.985 10.795 48.155 10.965 ; - RECT 47.525 10.795 47.695 10.965 ; - RECT 47.065 10.795 47.235 10.965 ; - RECT 46.605 10.795 46.775 10.965 ; - RECT 46.145 10.795 46.315 10.965 ; - RECT 45.685 10.795 45.855 10.965 ; - RECT 45.225 10.795 45.395 10.965 ; - RECT 44.765 10.795 44.935 10.965 ; - RECT 44.305 10.795 44.475 10.965 ; - RECT 43.845 10.795 44.015 10.965 ; - RECT 43.385 10.795 43.555 10.965 ; - RECT 42.925 10.795 43.095 10.965 ; - RECT 42.465 10.795 42.635 10.965 ; - RECT 42.005 10.795 42.175 10.965 ; - RECT 41.545 10.795 41.715 10.965 ; - RECT 41.085 10.795 41.255 10.965 ; - RECT 40.625 10.795 40.795 10.965 ; - RECT 40.165 10.795 40.335 10.965 ; - RECT 39.705 10.795 39.875 10.965 ; - RECT 39.245 10.795 39.415 10.965 ; - RECT 38.785 10.795 38.955 10.965 ; - RECT 38.325 10.795 38.495 10.965 ; - RECT 37.865 10.795 38.035 10.965 ; - RECT 37.405 10.795 37.575 10.965 ; - RECT 36.945 10.795 37.115 10.965 ; - RECT 36.485 10.795 36.655 10.965 ; - RECT 36.025 10.795 36.195 10.965 ; - RECT 35.565 10.795 35.735 10.965 ; - RECT 35.105 10.795 35.275 10.965 ; - RECT 34.645 10.795 34.815 10.965 ; - RECT 34.185 10.795 34.355 10.965 ; - RECT 33.725 10.795 33.895 10.965 ; - RECT 33.265 10.795 33.435 10.965 ; - RECT 32.805 10.795 32.975 10.965 ; - RECT 32.345 10.795 32.515 10.965 ; - RECT 31.885 10.795 32.055 10.965 ; - RECT 31.425 10.795 31.595 10.965 ; - RECT 30.965 10.795 31.135 10.965 ; - RECT 30.505 10.795 30.675 10.965 ; - RECT 30.045 10.795 30.215 10.965 ; - RECT 29.585 10.795 29.755 10.965 ; - RECT 29.125 10.795 29.295 10.965 ; - RECT 28.665 10.795 28.835 10.965 ; - RECT 28.205 10.795 28.375 10.965 ; - RECT 27.745 10.795 27.915 10.965 ; - RECT 27.285 10.795 27.455 10.965 ; - RECT 26.825 10.795 26.995 10.965 ; - RECT 26.365 10.795 26.535 10.965 ; - RECT 25.905 10.795 26.075 10.965 ; - RECT 25.445 10.795 25.615 10.965 ; - RECT 24.985 10.795 25.155 10.965 ; - RECT 24.525 10.795 24.695 10.965 ; - RECT 24.065 10.795 24.235 10.965 ; - RECT 23.605 10.795 23.775 10.965 ; - RECT 23.145 10.795 23.315 10.965 ; - RECT 22.685 10.795 22.855 10.965 ; - RECT 22.225 10.795 22.395 10.965 ; - RECT 21.765 10.795 21.935 10.965 ; - RECT 21.305 10.795 21.475 10.965 ; - RECT 20.845 10.795 21.015 10.965 ; - RECT 20.385 10.795 20.555 10.965 ; - RECT 19.925 10.795 20.095 10.965 ; - RECT 19.465 10.795 19.635 10.965 ; - RECT 19.005 10.795 19.175 10.965 ; - RECT 18.545 10.795 18.715 10.965 ; - RECT 18.085 10.795 18.255 10.965 ; - RECT 17.625 10.795 17.795 10.965 ; - RECT 17.165 10.795 17.335 10.965 ; - RECT 16.705 10.795 16.875 10.965 ; - RECT 16.245 10.795 16.415 10.965 ; - RECT 15.785 10.795 15.955 10.965 ; - RECT 15.325 10.795 15.495 10.965 ; - RECT 14.865 10.795 15.035 10.965 ; - RECT 14.405 10.795 14.575 10.965 ; - RECT 13.945 10.795 14.115 10.965 ; - RECT 13.485 10.795 13.655 10.965 ; - RECT 13.025 10.795 13.195 10.965 ; - RECT 12.565 10.795 12.735 10.965 ; - RECT 12.105 10.795 12.275 10.965 ; - RECT 11.645 10.795 11.815 10.965 ; - RECT 11.185 10.795 11.355 10.965 ; - RECT 10.725 10.795 10.895 10.965 ; - RECT 10.265 10.795 10.435 10.965 ; - RECT 9.805 10.795 9.975 10.965 ; - RECT 9.345 10.795 9.515 10.965 ; - RECT 8.885 10.795 9.055 10.965 ; - RECT 8.425 10.795 8.595 10.965 ; - RECT 7.965 10.795 8.135 10.965 ; - RECT 7.505 10.795 7.675 10.965 ; - RECT 7.045 10.795 7.215 10.965 ; - RECT 6.585 10.795 6.755 10.965 ; - RECT 6.125 10.795 6.295 10.965 ; - RECT 5.665 10.795 5.835 10.965 ; - RECT 5.205 10.795 5.375 10.965 ; - RECT 4.745 10.795 4.915 10.965 ; - RECT 4.285 10.795 4.455 10.965 ; - RECT 3.825 10.795 3.995 10.965 ; - RECT 3.365 10.795 3.535 10.965 ; - RECT 2.905 10.795 3.075 10.965 ; - RECT 2.445 10.795 2.615 10.965 ; - RECT 1.985 10.795 2.155 10.965 ; - RECT 1.525 10.795 1.695 10.965 ; - RECT 1.065 10.795 1.235 10.965 ; - RECT 0.605 10.795 0.775 10.965 ; - RECT 0.145 10.795 0.315 10.965 ; - RECT 65.925 8.075 66.095 8.245 ; - RECT 65.465 8.075 65.635 8.245 ; - RECT 0.605 8.075 0.775 8.245 ; - RECT 0.145 8.075 0.315 8.245 ; - RECT 65.925 5.355 66.095 5.525 ; - RECT 65.465 5.355 65.635 5.525 ; - RECT 0.605 5.355 0.775 5.525 ; - RECT 0.145 5.355 0.315 5.525 ; - RECT 65.925 2.635 66.095 2.805 ; - RECT 65.465 2.635 65.635 2.805 ; - RECT 0.605 2.635 0.775 2.805 ; - RECT 0.145 2.635 0.315 2.805 ; - RECT 65.925 -0.085 66.095 0.085 ; - RECT 65.465 -0.085 65.635 0.085 ; - RECT 65.005 -0.085 65.175 0.085 ; - RECT 64.545 -0.085 64.715 0.085 ; - RECT 64.085 -0.085 64.255 0.085 ; - RECT 63.625 -0.085 63.795 0.085 ; - RECT 63.165 -0.085 63.335 0.085 ; - RECT 62.705 -0.085 62.875 0.085 ; - RECT 62.245 -0.085 62.415 0.085 ; - RECT 61.785 -0.085 61.955 0.085 ; - RECT 61.325 -0.085 61.495 0.085 ; - RECT 60.865 -0.085 61.035 0.085 ; - RECT 60.405 -0.085 60.575 0.085 ; - RECT 59.945 -0.085 60.115 0.085 ; - RECT 59.485 -0.085 59.655 0.085 ; - RECT 59.025 -0.085 59.195 0.085 ; - RECT 58.565 -0.085 58.735 0.085 ; - RECT 58.105 -0.085 58.275 0.085 ; - RECT 57.645 -0.085 57.815 0.085 ; - RECT 57.185 -0.085 57.355 0.085 ; - RECT 56.725 -0.085 56.895 0.085 ; - RECT 56.265 -0.085 56.435 0.085 ; - RECT 55.805 -0.085 55.975 0.085 ; - RECT 55.345 -0.085 55.515 0.085 ; - RECT 54.885 -0.085 55.055 0.085 ; - RECT 54.425 -0.085 54.595 0.085 ; - RECT 53.965 -0.085 54.135 0.085 ; - RECT 53.505 -0.085 53.675 0.085 ; - RECT 53.045 -0.085 53.215 0.085 ; - RECT 52.585 -0.085 52.755 0.085 ; - RECT 52.125 -0.085 52.295 0.085 ; - RECT 51.665 -0.085 51.835 0.085 ; - RECT 51.205 -0.085 51.375 0.085 ; - RECT 50.745 -0.085 50.915 0.085 ; - RECT 50.285 -0.085 50.455 0.085 ; - RECT 49.825 -0.085 49.995 0.085 ; - RECT 49.365 -0.085 49.535 0.085 ; - RECT 48.905 -0.085 49.075 0.085 ; - RECT 48.445 -0.085 48.615 0.085 ; - RECT 47.985 -0.085 48.155 0.085 ; - RECT 47.525 -0.085 47.695 0.085 ; - RECT 47.065 -0.085 47.235 0.085 ; - RECT 46.605 -0.085 46.775 0.085 ; - RECT 46.145 -0.085 46.315 0.085 ; - RECT 45.685 -0.085 45.855 0.085 ; - RECT 45.225 -0.085 45.395 0.085 ; - RECT 44.765 -0.085 44.935 0.085 ; - RECT 44.305 -0.085 44.475 0.085 ; - RECT 43.845 -0.085 44.015 0.085 ; - RECT 43.385 -0.085 43.555 0.085 ; - RECT 42.925 -0.085 43.095 0.085 ; - RECT 42.465 -0.085 42.635 0.085 ; - RECT 42.005 -0.085 42.175 0.085 ; - RECT 41.545 -0.085 41.715 0.085 ; - RECT 41.085 -0.085 41.255 0.085 ; - RECT 40.625 -0.085 40.795 0.085 ; - RECT 40.165 -0.085 40.335 0.085 ; - RECT 39.705 -0.085 39.875 0.085 ; - RECT 39.245 -0.085 39.415 0.085 ; - RECT 38.785 -0.085 38.955 0.085 ; - RECT 38.325 -0.085 38.495 0.085 ; - RECT 37.865 -0.085 38.035 0.085 ; - RECT 37.405 -0.085 37.575 0.085 ; - RECT 36.945 -0.085 37.115 0.085 ; - RECT 36.485 -0.085 36.655 0.085 ; - RECT 36.025 -0.085 36.195 0.085 ; - RECT 35.565 -0.085 35.735 0.085 ; - RECT 35.105 -0.085 35.275 0.085 ; - RECT 34.645 -0.085 34.815 0.085 ; - RECT 34.185 -0.085 34.355 0.085 ; - RECT 33.725 -0.085 33.895 0.085 ; - RECT 33.265 -0.085 33.435 0.085 ; - RECT 32.805 -0.085 32.975 0.085 ; - RECT 32.345 -0.085 32.515 0.085 ; - RECT 31.885 -0.085 32.055 0.085 ; - RECT 31.425 -0.085 31.595 0.085 ; - RECT 30.965 -0.085 31.135 0.085 ; - RECT 30.505 -0.085 30.675 0.085 ; - RECT 30.045 -0.085 30.215 0.085 ; - RECT 29.585 -0.085 29.755 0.085 ; - RECT 29.125 -0.085 29.295 0.085 ; - RECT 28.665 -0.085 28.835 0.085 ; - RECT 28.205 -0.085 28.375 0.085 ; - RECT 27.745 -0.085 27.915 0.085 ; - RECT 27.285 -0.085 27.455 0.085 ; - RECT 26.825 -0.085 26.995 0.085 ; - RECT 26.365 -0.085 26.535 0.085 ; - RECT 25.905 -0.085 26.075 0.085 ; - RECT 25.445 -0.085 25.615 0.085 ; - RECT 24.985 -0.085 25.155 0.085 ; - RECT 24.525 -0.085 24.695 0.085 ; - RECT 24.065 -0.085 24.235 0.085 ; - RECT 23.605 -0.085 23.775 0.085 ; - RECT 23.145 -0.085 23.315 0.085 ; - RECT 22.685 -0.085 22.855 0.085 ; - RECT 22.225 -0.085 22.395 0.085 ; - RECT 21.765 -0.085 21.935 0.085 ; - RECT 21.305 -0.085 21.475 0.085 ; - RECT 20.845 -0.085 21.015 0.085 ; - RECT 20.385 -0.085 20.555 0.085 ; - RECT 19.925 -0.085 20.095 0.085 ; - RECT 19.465 -0.085 19.635 0.085 ; - RECT 19.005 -0.085 19.175 0.085 ; - RECT 18.545 -0.085 18.715 0.085 ; - RECT 18.085 -0.085 18.255 0.085 ; - RECT 17.625 -0.085 17.795 0.085 ; - RECT 17.165 -0.085 17.335 0.085 ; - RECT 16.705 -0.085 16.875 0.085 ; - RECT 16.245 -0.085 16.415 0.085 ; - RECT 15.785 -0.085 15.955 0.085 ; - RECT 15.325 -0.085 15.495 0.085 ; - RECT 14.865 -0.085 15.035 0.085 ; - RECT 14.405 -0.085 14.575 0.085 ; - RECT 13.945 -0.085 14.115 0.085 ; - RECT 13.485 -0.085 13.655 0.085 ; - RECT 13.025 -0.085 13.195 0.085 ; - RECT 12.565 -0.085 12.735 0.085 ; - RECT 12.105 -0.085 12.275 0.085 ; - RECT 11.645 -0.085 11.815 0.085 ; - RECT 11.185 -0.085 11.355 0.085 ; - RECT 10.725 -0.085 10.895 0.085 ; - RECT 10.265 -0.085 10.435 0.085 ; - RECT 9.805 -0.085 9.975 0.085 ; - RECT 9.345 -0.085 9.515 0.085 ; - RECT 8.885 -0.085 9.055 0.085 ; - RECT 8.425 -0.085 8.595 0.085 ; - RECT 7.965 -0.085 8.135 0.085 ; - RECT 7.505 -0.085 7.675 0.085 ; - RECT 7.045 -0.085 7.215 0.085 ; - RECT 6.585 -0.085 6.755 0.085 ; - RECT 6.125 -0.085 6.295 0.085 ; - RECT 5.665 -0.085 5.835 0.085 ; - RECT 5.205 -0.085 5.375 0.085 ; - RECT 4.745 -0.085 4.915 0.085 ; - RECT 4.285 -0.085 4.455 0.085 ; - RECT 3.825 -0.085 3.995 0.085 ; - RECT 3.365 -0.085 3.535 0.085 ; - RECT 2.905 -0.085 3.075 0.085 ; - RECT 2.445 -0.085 2.615 0.085 ; - RECT 1.985 -0.085 2.155 0.085 ; - RECT 1.525 -0.085 1.695 0.085 ; - RECT 1.065 -0.085 1.235 0.085 ; - RECT 0.605 -0.085 0.775 0.085 ; - RECT 0.145 -0.085 0.315 0.085 ; - LAYER via ; - RECT 55.125 108.725 55.275 108.875 ; - RECT 25.685 108.725 25.835 108.875 ; - RECT 47.305 98.365 47.455 98.515 ; - RECT 55.125 97.845 55.275 97.995 ; - RECT 25.685 97.845 25.835 97.995 ; - RECT 88.245 12.505 88.395 12.655 ; - RECT 80.425 12.505 80.575 12.655 ; - RECT 55.125 10.805 55.275 10.955 ; - RECT 25.685 10.805 25.835 10.955 ; - RECT 60.185 1.625 60.335 1.775 ; - RECT 47.305 1.625 47.455 1.775 ; - RECT 31.205 1.625 31.355 1.775 ; - RECT 55.125 -0.075 55.275 0.075 ; - RECT 25.685 -0.075 25.835 0.075 ; - LAYER via2 ; - RECT 55.1 108.7 55.3 108.9 ; - RECT 25.66 108.7 25.86 108.9 ; - RECT 90.52 70.62 90.72 70.82 ; - RECT 90.52 52.94 90.72 53.14 ; - RECT 90.06 37.98 90.26 38.18 ; - RECT 55.1 -0.1 55.3 0.1 ; - RECT 25.66 -0.1 25.86 0.1 ; - LAYER via3 ; - RECT 55.1 108.7 55.3 108.9 ; - RECT 25.66 108.7 25.86 108.9 ; - RECT 90.06 36.62 90.26 36.82 ; - RECT 55.1 -0.1 55.3 0.1 ; - RECT 25.66 -0.1 25.86 0.1 ; - LAYER OVERLAP ; - POLYGON 0 0 0 108.8 66.24 108.8 66.24 97.92 92 97.92 92 10.88 66.24 10.88 66.24 0 ; - END -END sb_0__1_ - -END LIBRARY diff --git a/FPGA22_HIER_SKY_PNR/modules/lef/sb_0__2__icv_in_design.lef b/FPGA22_HIER_SKY_PNR/modules/lef/sb_0__2__icv_in_design.lef deleted file mode 100644 index 8412b71..0000000 --- a/FPGA22_HIER_SKY_PNR/modules/lef/sb_0__2__icv_in_design.lef +++ /dev/null @@ -1,2051 +0,0 @@ -VERSION 5.7 ; -BUSBITCHARS "[]" ; - -UNITS - DATABASE MICRONS 1000 ; -END UNITS - -MANUFACTURINGGRID 0.005 ; - -LAYER li1 - TYPE ROUTING ; - DIRECTION VERTICAL ; - PITCH 0.46 ; - WIDTH 0.17 ; -END li1 - -LAYER mcon - TYPE CUT ; -END mcon - -LAYER met1 - TYPE ROUTING ; - DIRECTION HORIZONTAL ; - PITCH 0.34 ; - WIDTH 0.14 ; -END met1 - -LAYER via - TYPE CUT ; -END via - -LAYER met2 - TYPE ROUTING ; - DIRECTION VERTICAL ; - PITCH 0.46 ; - WIDTH 0.14 ; -END met2 - -LAYER via2 - TYPE CUT ; -END via2 - -LAYER met3 - TYPE ROUTING ; - DIRECTION HORIZONTAL ; - PITCH 0.68 ; - WIDTH 0.3 ; -END met3 - -LAYER via3 - TYPE CUT ; -END via3 - -LAYER met4 - TYPE ROUTING ; - DIRECTION VERTICAL ; - PITCH 0.92 ; - WIDTH 0.3 ; -END met4 - -LAYER via4 - TYPE CUT ; -END via4 - -LAYER met5 - TYPE ROUTING ; - DIRECTION HORIZONTAL ; - PITCH 3.4 ; - WIDTH 1.6 ; -END met5 - -LAYER nwell - TYPE MASTERSLICE ; -END nwell - -LAYER pwell - TYPE MASTERSLICE ; -END pwell - -LAYER OVERLAP - TYPE OVERLAP ; -END OVERLAP - -VIA L1M1_PR - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.145 -0.115 0.145 0.115 ; -END L1M1_PR - -VIA L1M1_PR_R - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.115 -0.145 0.115 0.145 ; -END L1M1_PR_R - -VIA L1M1_PR_M - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.115 -0.145 0.115 0.145 ; -END L1M1_PR_M - -VIA L1M1_PR_MR - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.145 -0.115 0.145 0.115 ; -END L1M1_PR_MR - -VIA L1M1_PR_C - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.145 -0.145 0.145 0.145 ; -END L1M1_PR_C - -VIA M1M2_PR - LAYER met1 ; - RECT -0.16 -0.13 0.16 0.13 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.13 -0.16 0.13 0.16 ; -END M1M2_PR - -VIA M1M2_PR_Enc - LAYER met1 ; - RECT -0.16 -0.13 0.16 0.13 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.16 -0.13 0.16 0.13 ; -END M1M2_PR_Enc - -VIA M1M2_PR_R - LAYER met1 ; - RECT -0.13 -0.16 0.13 0.16 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.16 -0.13 0.16 0.13 ; -END M1M2_PR_R - -VIA M1M2_PR_R_Enc - LAYER met1 ; - RECT -0.13 -0.16 0.13 0.16 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.13 -0.16 0.13 0.16 ; -END M1M2_PR_R_Enc - -VIA M1M2_PR_M - LAYER met1 ; - RECT -0.16 -0.13 0.16 0.13 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.16 -0.13 0.16 0.13 ; -END M1M2_PR_M - -VIA M1M2_PR_M_Enc - LAYER met1 ; - RECT -0.16 -0.13 0.16 0.13 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.13 -0.16 0.13 0.16 ; -END M1M2_PR_M_Enc - -VIA M1M2_PR_MR - LAYER met1 ; - RECT -0.13 -0.16 0.13 0.16 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.13 -0.16 0.13 0.16 ; -END M1M2_PR_MR - -VIA M1M2_PR_MR_Enc - LAYER met1 ; - RECT -0.13 -0.16 0.13 0.16 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.16 -0.13 0.16 0.13 ; -END M1M2_PR_MR_Enc - -VIA M1M2_PR_C - LAYER met1 ; - RECT -0.16 -0.16 0.16 0.16 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.16 -0.16 0.16 0.16 ; -END M1M2_PR_C - -VIA M2M3_PR - LAYER met2 ; - RECT -0.14 -0.185 0.14 0.185 ; - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met3 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M2M3_PR - -VIA M2M3_PR_R - LAYER met2 ; - RECT -0.185 -0.14 0.185 0.14 ; - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met3 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M2M3_PR_R - -VIA M2M3_PR_M - LAYER met2 ; - RECT -0.14 -0.185 0.14 0.185 ; - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met3 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M2M3_PR_M - -VIA M2M3_PR_MR - LAYER met2 ; - RECT -0.185 -0.14 0.185 0.14 ; - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met3 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M2M3_PR_MR - -VIA M2M3_PR_C - LAYER met2 ; - RECT -0.185 -0.185 0.185 0.185 ; - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met3 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M2M3_PR_C - -VIA M3M4_PR - LAYER met3 ; - RECT -0.19 -0.16 0.19 0.16 ; - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR - -VIA M3M4_PR_R - LAYER met3 ; - RECT -0.16 -0.19 0.16 0.19 ; - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR_R - -VIA M3M4_PR_M - LAYER met3 ; - RECT -0.19 -0.16 0.19 0.16 ; - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR_M - -VIA M3M4_PR_MR - LAYER met3 ; - RECT -0.16 -0.19 0.16 0.19 ; - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR_MR - -VIA M3M4_PR_C - LAYER met3 ; - RECT -0.19 -0.19 0.19 0.19 ; - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR_C - -VIA M4M5_PR - LAYER met4 ; - RECT -0.59 -0.59 0.59 0.59 ; - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - LAYER met5 ; - RECT -0.71 -0.71 0.71 0.71 ; -END M4M5_PR - -VIA M4M5_PR_R - LAYER met4 ; - RECT -0.59 -0.59 0.59 0.59 ; - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - LAYER met5 ; - RECT -0.71 -0.71 0.71 0.71 ; -END M4M5_PR_R - -VIA M4M5_PR_M - LAYER met4 ; - RECT -0.59 -0.59 0.59 0.59 ; - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - LAYER met5 ; - RECT -0.71 -0.71 0.71 0.71 ; -END M4M5_PR_M - -VIA M4M5_PR_MR - LAYER met4 ; - RECT -0.59 -0.59 0.59 0.59 ; - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - LAYER met5 ; - RECT -0.71 -0.71 0.71 0.71 ; -END M4M5_PR_MR - -VIA M4M5_PR_C - LAYER met4 ; - RECT -0.59 -0.59 0.59 0.59 ; - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - LAYER met5 ; - RECT -0.71 -0.71 0.71 0.71 ; -END M4M5_PR_C - -SITE unit - CLASS CORE ; - SYMMETRY Y ; - SIZE 0.46 BY 2.72 ; -END unit - -SITE unithddbl - CLASS CORE ; - SIZE 0.46 BY 5.44 ; -END unithddbl - -MACRO sb_0__2_ - CLASS BLOCK ; - ORIGIN 0 0 ; - SIZE 92 BY 97.92 ; - SYMMETRY X Y ; - PIN prog_clk[0] - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER met3 ; - RECT 90.62 17.53 92 17.83 ; - END - END prog_clk[0] - PIN chanx_right_in[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 81.45 92 81.75 ; - END - END chanx_right_in[0] - PIN chanx_right_in[1] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 53.57 92 53.87 ; - END - END chanx_right_in[1] - PIN chanx_right_in[2] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 80.09 92 80.39 ; - END - END chanx_right_in[2] - PIN chanx_right_in[3] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 72.61 92 72.91 ; - END - END chanx_right_in[3] - PIN chanx_right_in[4] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 33.85 92 34.15 ; - END - END chanx_right_in[4] - PIN chanx_right_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 22.97 92 23.27 ; - END - END chanx_right_in[5] - PIN chanx_right_in[6] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 24.33 92 24.63 ; - END - END chanx_right_in[6] - PIN chanx_right_in[7] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 49.49 92 49.79 ; - END - END chanx_right_in[7] - PIN chanx_right_in[8] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 77.37 92 77.67 ; - END - END chanx_right_in[8] - PIN chanx_right_in[9] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 59.69 92 59.99 ; - END - END chanx_right_in[9] - PIN chanx_right_in[10] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 73.97 92 74.27 ; - END - END chanx_right_in[10] - PIN chanx_right_in[11] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 68.53 92 68.83 ; - END - END chanx_right_in[11] - PIN chanx_right_in[12] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 50.85 92 51.15 ; - END - END chanx_right_in[12] - PIN chanx_right_in[13] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 71.25 92 71.55 ; - END - END chanx_right_in[13] - PIN chanx_right_in[14] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 31.13 92 31.43 ; - END - END chanx_right_in[14] - PIN chanx_right_in[15] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 55.61 92 55.91 ; - END - END chanx_right_in[15] - PIN chanx_right_in[16] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 29.09 92 29.39 ; - END - END chanx_right_in[16] - PIN chanx_right_in[17] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 52.21 92 52.51 ; - END - END chanx_right_in[17] - PIN chanx_right_in[18] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 56.97 92 57.27 ; - END - END chanx_right_in[18] - PIN chanx_right_in[19] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 58.33 92 58.63 ; - END - END chanx_right_in[19] - PIN right_top_grid_pin_1_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 37.93 92 38.23 ; - END - END right_top_grid_pin_1_[0] - PIN right_bottom_grid_pin_34_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 83.65 10.88 83.79 12.24 ; - END - END right_bottom_grid_pin_34_[0] - PIN right_bottom_grid_pin_35_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 85.95 10.88 86.09 12.24 ; - END - END right_bottom_grid_pin_35_[0] - PIN right_bottom_grid_pin_36_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 88.25 10.88 88.39 12.24 ; - END - END right_bottom_grid_pin_36_[0] - PIN right_bottom_grid_pin_37_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 82.73 10.88 82.87 12.24 ; - END - END right_bottom_grid_pin_37_[0] - PIN right_bottom_grid_pin_38_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 85.03 10.88 85.17 12.24 ; - END - END right_bottom_grid_pin_38_[0] - PIN right_bottom_grid_pin_39_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 87.33 10.88 87.47 12.24 ; - END - END right_bottom_grid_pin_39_[0] - PIN right_bottom_grid_pin_40_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 75.83 10.88 75.97 12.24 ; - END - END right_bottom_grid_pin_40_[0] - PIN right_bottom_grid_pin_41_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 80.43 10.88 80.57 12.24 ; - END - END right_bottom_grid_pin_41_[0] - PIN chany_bottom_in[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 61.11 0 61.25 1.36 ; - END - END chany_bottom_in[0] - PIN chany_bottom_in[1] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 60.19 0 60.33 1.36 ; - END - END chany_bottom_in[1] - PIN chany_bottom_in[2] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 44.55 0 44.69 1.36 ; - END - END chany_bottom_in[2] - PIN chany_bottom_in[3] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 46.39 0 46.53 1.36 ; - END - END chany_bottom_in[3] - PIN chany_bottom_in[4] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 58.35 0 58.49 1.36 ; - END - END chany_bottom_in[4] - PIN chany_bottom_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 27.53 0 27.67 1.36 ; - END - END chany_bottom_in[5] - PIN chany_bottom_in[6] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 33.05 0 33.19 1.36 ; - END - END chany_bottom_in[6] - PIN chany_bottom_in[7] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 52.83 0 52.97 1.36 ; - END - END chany_bottom_in[7] - PIN chany_bottom_in[8] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 10.05 0 10.19 1.36 ; - END - END chany_bottom_in[8] - PIN chany_bottom_in[9] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 26.61 0 26.75 1.36 ; - END - END chany_bottom_in[9] - PIN chany_bottom_in[10] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 17.87 0 18.01 1.36 ; - END - END chany_bottom_in[10] - PIN chany_bottom_in[11] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 48.23 0 48.37 1.36 ; - END - END chany_bottom_in[11] - PIN chany_bottom_in[12] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 45.47 0 45.61 1.36 ; - END - END chany_bottom_in[12] - PIN chany_bottom_in[13] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 32.13 0 32.27 1.36 ; - END - END chany_bottom_in[13] - PIN chany_bottom_in[14] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 29.37 0 29.51 1.36 ; - END - END chany_bottom_in[14] - PIN chany_bottom_in[15] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 30.29 0 30.43 1.36 ; - END - END chany_bottom_in[15] - PIN chany_bottom_in[16] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 39.03 0 39.17 1.36 ; - END - END chany_bottom_in[16] - PIN chany_bottom_in[17] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 8.21 0 8.35 1.36 ; - END - END chany_bottom_in[17] - PIN chany_bottom_in[18] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 7.29 0 7.43 1.36 ; - END - END chany_bottom_in[18] - PIN chany_bottom_in[19] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 31.21 0 31.35 1.36 ; - END - END chany_bottom_in[19] - PIN bottom_left_grid_pin_1_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 59.27 0 59.41 1.36 ; - END - END bottom_left_grid_pin_1_[0] - PIN ccff_head[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 48.13 92 48.43 ; - END - END ccff_head[0] - PIN chanx_right_out[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 14.13 92 14.43 ; - END - END chanx_right_out[0] - PIN chanx_right_out[1] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 32.49 92 32.79 ; - END - END chanx_right_out[1] - PIN chanx_right_out[2] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 15.49 92 15.79 ; - END - END chanx_right_out[2] - PIN chanx_right_out[3] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 61.05 92 61.35 ; - END - END chanx_right_out[3] - PIN chanx_right_out[4] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 21.61 92 21.91 ; - END - END chanx_right_out[4] - PIN chanx_right_out[5] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 26.37 92 26.67 ; - END - END chanx_right_out[5] - PIN chanx_right_out[6] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 46.77 92 47.07 ; - END - END chanx_right_out[6] - PIN chanx_right_out[7] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 41.33 92 41.63 ; - END - END chanx_right_out[7] - PIN chanx_right_out[8] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 67.17 92 67.47 ; - END - END chanx_right_out[8] - PIN chanx_right_out[9] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 44.05 92 44.35 ; - END - END chanx_right_out[9] - PIN chanx_right_out[10] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 36.57 92 36.87 ; - END - END chanx_right_out[10] - PIN chanx_right_out[11] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 39.97 92 40.27 ; - END - END chanx_right_out[11] - PIN chanx_right_out[12] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 20.25 92 20.55 ; - END - END chanx_right_out[12] - PIN chanx_right_out[13] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 27.73 92 28.03 ; - END - END chanx_right_out[13] - PIN chanx_right_out[14] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 69.89 92 70.19 ; - END - END chanx_right_out[14] - PIN chanx_right_out[15] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 42.69 92 42.99 ; - END - END chanx_right_out[15] - PIN chanx_right_out[16] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 75.33 92 75.63 ; - END - END chanx_right_out[16] - PIN chanx_right_out[17] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 45.41 92 45.71 ; - END - END chanx_right_out[17] - PIN chanx_right_out[18] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 64.45 92 64.75 ; - END - END chanx_right_out[18] - PIN chanx_right_out[19] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 35.21 92 35.51 ; - END - END chanx_right_out[19] - PIN chany_bottom_out[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 47.31 0 47.45 1.36 ; - END - END chany_bottom_out[0] - PIN chany_bottom_out[1] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 49.15 0 49.29 1.36 ; - END - END chany_bottom_out[1] - PIN chany_bottom_out[2] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 53.75 0 53.89 1.36 ; - END - END chany_bottom_out[2] - PIN chany_bottom_out[3] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 46.77 0 47.07 1.36 ; - END - END chany_bottom_out[3] - PIN chany_bottom_out[4] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 57.43 0 57.57 1.36 ; - END - END chany_bottom_out[4] - PIN chany_bottom_out[5] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 5.37 0 5.67 1.36 ; - END - END chany_bottom_out[5] - PIN chany_bottom_out[6] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 27.45 0 27.75 1.36 ; - END - END chany_bottom_out[6] - PIN chany_bottom_out[7] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 48.61 0 48.91 1.36 ; - END - END chany_bottom_out[7] - PIN chany_bottom_out[8] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 51.91 0 52.05 1.36 ; - END - END chany_bottom_out[8] - PIN chany_bottom_out[9] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 52.29 0 52.59 1.36 ; - END - END chany_bottom_out[9] - PIN chany_bottom_out[10] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 56.05 0 56.19 1.36 ; - END - END chany_bottom_out[10] - PIN chany_bottom_out[11] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 29.29 0 29.59 1.36 ; - END - END chany_bottom_out[11] - PIN chany_bottom_out[12] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 28.45 0 28.59 1.36 ; - END - END chany_bottom_out[12] - PIN chany_bottom_out[13] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 7.21 0 7.51 1.36 ; - END - END chany_bottom_out[13] - PIN chany_bottom_out[14] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 9.05 0 9.35 1.36 ; - END - END chany_bottom_out[14] - PIN chany_bottom_out[15] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 50.45 0 50.75 1.36 ; - END - END chany_bottom_out[15] - PIN chany_bottom_out[16] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 42.71 0 42.85 1.36 ; - END - END chany_bottom_out[16] - PIN chany_bottom_out[17] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 50.07 0 50.21 1.36 ; - END - END chany_bottom_out[17] - PIN chany_bottom_out[18] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 9.13 0 9.27 1.36 ; - END - END chany_bottom_out[18] - PIN chany_bottom_out[19] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 50.99 0 51.13 1.36 ; - END - END chany_bottom_out[19] - PIN ccff_tail[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 40.87 0 41.01 1.36 ; - END - END ccff_tail[0] - PIN SC_IN_TOP - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 77.37 1.38 77.67 ; - END - END SC_IN_TOP - PIN SC_IN_BOT - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 47.45 1.38 47.75 ; - END - END SC_IN_BOT - PIN SC_OUT_TOP - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 48.81 1.38 49.11 ; - END - END SC_OUT_TOP - PIN SC_OUT_BOT - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 90.62 78.73 92 79.03 ; - END - END SC_OUT_BOT - PIN VDD - DIRECTION INPUT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0 2.48 0.48 2.96 ; - RECT 65.76 2.48 66.24 2.96 ; - RECT 0 7.92 0.48 8.4 ; - RECT 65.76 7.92 66.24 8.4 ; - RECT 0 13.36 0.48 13.84 ; - RECT 91.52 13.36 92 13.84 ; - RECT 0 18.8 0.48 19.28 ; - RECT 91.52 18.8 92 19.28 ; - RECT 0 24.24 0.48 24.72 ; - RECT 91.52 24.24 92 24.72 ; - RECT 0 29.68 0.48 30.16 ; - RECT 91.52 29.68 92 30.16 ; - RECT 0 35.12 0.48 35.6 ; - RECT 91.52 35.12 92 35.6 ; - RECT 0 40.56 0.48 41.04 ; - RECT 91.52 40.56 92 41.04 ; - RECT 0 46 0.48 46.48 ; - RECT 91.52 46 92 46.48 ; - RECT 0 51.44 0.48 51.92 ; - RECT 91.52 51.44 92 51.92 ; - RECT 0 56.88 0.48 57.36 ; - RECT 91.52 56.88 92 57.36 ; - RECT 0 62.32 0.48 62.8 ; - RECT 91.52 62.32 92 62.8 ; - RECT 0 67.76 0.48 68.24 ; - RECT 91.52 67.76 92 68.24 ; - RECT 0 73.2 0.48 73.68 ; - RECT 91.52 73.2 92 73.68 ; - RECT 0 78.64 0.48 79.12 ; - RECT 91.52 78.64 92 79.12 ; - RECT 0 84.08 0.48 84.56 ; - RECT 91.52 84.08 92 84.56 ; - RECT 0 89.52 0.48 90 ; - RECT 91.52 89.52 92 90 ; - RECT 0 94.96 0.48 95.44 ; - RECT 91.52 94.96 92 95.44 ; - LAYER met4 ; - RECT 10.74 0 11.34 0.6 ; - RECT 40.18 0 40.78 0.6 ; - RECT 80.66 10.88 81.26 11.48 ; - RECT 10.74 97.32 11.34 97.92 ; - RECT 40.18 97.32 40.78 97.92 ; - RECT 80.66 97.32 81.26 97.92 ; - LAYER met5 ; - RECT 0 22.2 3.2 25.4 ; - RECT 88.8 22.2 92 25.4 ; - RECT 0 63 3.2 66.2 ; - RECT 88.8 63 92 66.2 ; - END - END VDD - PIN VSS - DIRECTION INPUT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0 0 66.24 0.24 ; - RECT 0 5.2 0.48 5.68 ; - RECT 65.76 5.2 66.24 5.68 ; - RECT 0 10.64 92 11.12 ; - RECT 0 16.08 0.48 16.56 ; - RECT 91.52 16.08 92 16.56 ; - RECT 0 21.52 0.48 22 ; - RECT 91.52 21.52 92 22 ; - RECT 0 26.96 0.48 27.44 ; - RECT 91.52 26.96 92 27.44 ; - RECT 0 32.4 0.48 32.88 ; - RECT 91.52 32.4 92 32.88 ; - RECT 0 37.84 0.48 38.32 ; - RECT 91.52 37.84 92 38.32 ; - RECT 0 43.28 0.48 43.76 ; - RECT 91.52 43.28 92 43.76 ; - RECT 0 48.72 0.48 49.2 ; - RECT 91.52 48.72 92 49.2 ; - RECT 0 54.16 0.48 54.64 ; - RECT 91.52 54.16 92 54.64 ; - RECT 0 59.6 0.48 60.08 ; - RECT 91.52 59.6 92 60.08 ; - RECT 0 65.04 0.48 65.52 ; - RECT 91.52 65.04 92 65.52 ; - RECT 0 70.48 0.48 70.96 ; - RECT 91.52 70.48 92 70.96 ; - RECT 0 75.92 0.48 76.4 ; - RECT 91.52 75.92 92 76.4 ; - RECT 0 81.36 0.48 81.84 ; - RECT 91.52 81.36 92 81.84 ; - RECT 0 86.8 0.48 87.28 ; - RECT 91.52 86.8 92 87.28 ; - RECT 0 92.24 0.48 92.72 ; - RECT 91.52 92.24 92 92.72 ; - RECT 0 97.68 92 97.92 ; - LAYER met4 ; - RECT 25.46 0 26.06 0.6 ; - RECT 54.9 0 55.5 0.6 ; - RECT 25.46 97.32 26.06 97.92 ; - RECT 54.9 97.32 55.5 97.92 ; - LAYER met5 ; - RECT 0 42.6 3.2 45.8 ; - RECT 88.8 42.6 92 45.8 ; - RECT 0 83.4 3.2 86.6 ; - RECT 88.8 83.4 92 86.6 ; - END - END VSS - OBS - LAYER li1 ; - RECT 0 97.835 92 98.005 ; - RECT 91.54 95.115 92 95.285 ; - RECT 0 95.115 3.68 95.285 ; - RECT 91.54 92.395 92 92.565 ; - RECT 0 92.395 3.68 92.565 ; - RECT 91.54 89.675 92 89.845 ; - RECT 0 89.675 3.68 89.845 ; - RECT 91.54 86.955 92 87.125 ; - RECT 0 86.955 3.68 87.125 ; - RECT 91.54 84.235 92 84.405 ; - RECT 0 84.235 3.68 84.405 ; - RECT 91.08 81.515 92 81.685 ; - RECT 0 81.515 3.68 81.685 ; - RECT 91.08 78.795 92 78.965 ; - RECT 0 78.795 3.68 78.965 ; - RECT 91.54 76.075 92 76.245 ; - RECT 0 76.075 3.68 76.245 ; - RECT 91.54 73.355 92 73.525 ; - RECT 0 73.355 3.68 73.525 ; - RECT 91.08 70.635 92 70.805 ; - RECT 0 70.635 3.68 70.805 ; - RECT 91.08 67.915 92 68.085 ; - RECT 0 67.915 3.68 68.085 ; - RECT 91.54 65.195 92 65.365 ; - RECT 0 65.195 3.68 65.365 ; - RECT 91.54 62.475 92 62.645 ; - RECT 0 62.475 3.68 62.645 ; - RECT 91.54 59.755 92 59.925 ; - RECT 0 59.755 3.68 59.925 ; - RECT 91.54 57.035 92 57.205 ; - RECT 0 57.035 3.68 57.205 ; - RECT 90.16 54.315 92 54.485 ; - RECT 0 54.315 3.68 54.485 ; - RECT 90.16 51.595 92 51.765 ; - RECT 0 51.595 3.68 51.765 ; - RECT 91.08 48.875 92 49.045 ; - RECT 0 48.875 3.68 49.045 ; - RECT 91.08 46.155 92 46.325 ; - RECT 0 46.155 3.68 46.325 ; - RECT 91.08 43.435 92 43.605 ; - RECT 0 43.435 3.68 43.605 ; - RECT 91.08 40.715 92 40.885 ; - RECT 0 40.715 3.68 40.885 ; - RECT 88.32 37.995 92 38.165 ; - RECT 0 37.995 3.68 38.165 ; - RECT 88.32 35.275 92 35.445 ; - RECT 0 35.275 3.68 35.445 ; - RECT 91.08 32.555 92 32.725 ; - RECT 0 32.555 3.68 32.725 ; - RECT 91.08 29.835 92 30.005 ; - RECT 0 29.835 3.68 30.005 ; - RECT 91.08 27.115 92 27.285 ; - RECT 0 27.115 3.68 27.285 ; - RECT 91.08 24.395 92 24.565 ; - RECT 0 24.395 3.68 24.565 ; - RECT 90.16 21.675 92 21.845 ; - RECT 0 21.675 3.68 21.845 ; - RECT 90.16 18.955 92 19.125 ; - RECT 0 18.955 3.68 19.125 ; - RECT 88.32 16.235 92 16.405 ; - RECT 0 16.235 3.68 16.405 ; - RECT 88.32 13.515 92 13.685 ; - RECT 0 13.515 3.68 13.685 ; - RECT 63.48 10.795 92 10.965 ; - RECT 0 10.795 3.68 10.965 ; - RECT 65.32 8.075 66.24 8.245 ; - RECT 0 8.075 3.68 8.245 ; - RECT 65.32 5.355 66.24 5.525 ; - RECT 0 5.355 3.68 5.525 ; - RECT 65.78 2.635 66.24 2.805 ; - RECT 0 2.635 3.68 2.805 ; - RECT 0 -0.085 66.24 0.085 ; - LAYER met3 ; - POLYGON 55.365 98.085 55.365 98.08 55.58 98.08 55.58 97.76 55.365 97.76 55.365 97.755 55.035 97.755 55.035 97.76 54.82 97.76 54.82 98.08 55.035 98.08 55.035 98.085 ; - POLYGON 25.925 98.085 25.925 98.08 26.14 98.08 26.14 97.76 25.925 97.76 25.925 97.755 25.595 97.755 25.595 97.76 25.38 97.76 25.38 98.08 25.595 98.08 25.595 98.085 ; - POLYGON 90.77 57.95 90.77 57.67 90.22 57.67 90.22 57.65 77.13 57.65 77.13 57.95 ; - POLYGON 90.22 22.59 90.22 22.57 90.77 22.57 90.77 22.29 13.19 22.29 13.19 22.59 ; - POLYGON 55.365 0.165 55.365 0.16 55.58 0.16 55.58 -0.16 55.365 -0.16 55.365 -0.165 55.035 -0.165 55.035 -0.16 54.82 -0.16 54.82 0.16 55.035 0.16 55.035 0.165 ; - POLYGON 25.925 0.165 25.925 0.16 26.14 0.16 26.14 -0.16 25.925 -0.16 25.925 -0.165 25.595 -0.165 25.595 -0.16 25.38 -0.16 25.38 0.16 25.595 0.16 25.595 0.165 ; - POLYGON 91.6 97.52 91.6 82.15 90.22 82.15 90.22 81.05 91.6 81.05 91.6 80.79 90.22 80.79 90.22 79.69 91.6 79.69 91.6 79.43 90.22 79.43 90.22 78.33 91.6 78.33 91.6 78.07 90.22 78.07 90.22 76.97 91.6 76.97 91.6 76.03 90.22 76.03 90.22 74.93 91.6 74.93 91.6 74.67 90.22 74.67 90.22 73.57 91.6 73.57 91.6 73.31 90.22 73.31 90.22 72.21 91.6 72.21 91.6 71.95 90.22 71.95 90.22 70.85 91.6 70.85 91.6 70.59 90.22 70.59 90.22 69.49 91.6 69.49 91.6 69.23 90.22 69.23 90.22 68.13 91.6 68.13 91.6 67.87 90.22 67.87 90.22 66.77 91.6 66.77 91.6 65.15 90.22 65.15 90.22 64.05 91.6 64.05 91.6 61.75 90.22 61.75 90.22 60.65 91.6 60.65 91.6 60.39 90.22 60.39 90.22 59.29 91.6 59.29 91.6 59.03 90.22 59.03 90.22 57.93 91.6 57.93 91.6 57.67 90.22 57.67 90.22 56.57 91.6 56.57 91.6 56.31 90.22 56.31 90.22 55.21 91.6 55.21 91.6 54.27 90.22 54.27 90.22 53.17 91.6 53.17 91.6 52.91 90.22 52.91 90.22 51.81 91.6 51.81 91.6 51.55 90.22 51.55 90.22 50.45 91.6 50.45 91.6 50.19 90.22 50.19 90.22 49.09 91.6 49.09 91.6 48.83 90.22 48.83 90.22 47.73 91.6 47.73 91.6 47.47 90.22 47.47 90.22 46.37 91.6 46.37 91.6 46.11 90.22 46.11 90.22 45.01 91.6 45.01 91.6 44.75 90.22 44.75 90.22 43.65 91.6 43.65 91.6 43.39 90.22 43.39 90.22 42.29 91.6 42.29 91.6 42.03 90.22 42.03 90.22 40.93 91.6 40.93 91.6 40.67 90.22 40.67 90.22 39.57 91.6 39.57 91.6 38.63 90.22 38.63 90.22 37.53 91.6 37.53 91.6 37.27 90.22 37.27 90.22 36.17 91.6 36.17 91.6 35.91 90.22 35.91 90.22 34.81 91.6 34.81 91.6 34.55 90.22 34.55 90.22 33.45 91.6 33.45 91.6 33.19 90.22 33.19 90.22 32.09 91.6 32.09 91.6 31.83 90.22 31.83 90.22 30.73 91.6 30.73 91.6 29.79 90.22 29.79 90.22 28.69 91.6 28.69 91.6 28.43 90.22 28.43 90.22 27.33 91.6 27.33 91.6 27.07 90.22 27.07 90.22 25.97 91.6 25.97 91.6 25.03 90.22 25.03 90.22 23.93 91.6 23.93 91.6 23.67 90.22 23.67 90.22 22.57 91.6 22.57 91.6 22.31 90.22 22.31 90.22 21.21 91.6 21.21 91.6 20.95 90.22 20.95 90.22 19.85 91.6 19.85 91.6 18.23 90.22 18.23 90.22 17.13 91.6 17.13 91.6 16.19 90.22 16.19 90.22 15.09 91.6 15.09 91.6 14.83 90.22 14.83 90.22 13.73 91.6 13.73 91.6 11.28 65.84 11.28 65.84 0.4 0.4 0.4 0.4 47.05 1.78 47.05 1.78 48.15 0.4 48.15 0.4 48.41 1.78 48.41 1.78 49.51 0.4 49.51 0.4 76.97 1.78 76.97 1.78 78.07 0.4 78.07 0.4 97.52 ; - LAYER met2 ; - RECT 55.06 97.735 55.34 98.105 ; - RECT 25.62 97.735 25.9 98.105 ; - RECT 55.06 -0.185 55.34 0.185 ; - RECT 25.62 -0.185 25.9 0.185 ; - POLYGON 91.72 97.64 91.72 11.16 88.67 11.16 88.67 12.52 87.97 12.52 87.97 11.16 87.75 11.16 87.75 12.52 87.05 12.52 87.05 11.16 86.37 11.16 86.37 12.52 85.67 12.52 85.67 11.16 85.45 11.16 85.45 12.52 84.75 12.52 84.75 11.16 84.07 11.16 84.07 12.52 83.37 12.52 83.37 11.16 83.15 11.16 83.15 12.52 82.45 12.52 82.45 11.16 80.85 11.16 80.85 12.52 80.15 12.52 80.15 11.16 76.25 11.16 76.25 12.52 75.55 12.52 75.55 11.16 65.96 11.16 65.96 0.28 61.53 0.28 61.53 1.64 60.83 1.64 60.83 0.28 60.61 0.28 60.61 1.64 59.91 1.64 59.91 0.28 59.69 0.28 59.69 1.64 58.99 1.64 58.99 0.28 58.77 0.28 58.77 1.64 58.07 1.64 58.07 0.28 57.85 0.28 57.85 1.64 57.15 1.64 57.15 0.28 56.47 0.28 56.47 1.64 55.77 1.64 55.77 0.28 54.17 0.28 54.17 1.64 53.47 1.64 53.47 0.28 53.25 0.28 53.25 1.64 52.55 1.64 52.55 0.28 52.33 0.28 52.33 1.64 51.63 1.64 51.63 0.28 51.41 0.28 51.41 1.64 50.71 1.64 50.71 0.28 50.49 0.28 50.49 1.64 49.79 1.64 49.79 0.28 49.57 0.28 49.57 1.64 48.87 1.64 48.87 0.28 48.65 0.28 48.65 1.64 47.95 1.64 47.95 0.28 47.73 0.28 47.73 1.64 47.03 1.64 47.03 0.28 46.81 0.28 46.81 1.64 46.11 1.64 46.11 0.28 45.89 0.28 45.89 1.64 45.19 1.64 45.19 0.28 44.97 0.28 44.97 1.64 44.27 1.64 44.27 0.28 43.13 0.28 43.13 1.64 42.43 1.64 42.43 0.28 41.29 0.28 41.29 1.64 40.59 1.64 40.59 0.28 39.45 0.28 39.45 1.64 38.75 1.64 38.75 0.28 33.47 0.28 33.47 1.64 32.77 1.64 32.77 0.28 32.55 0.28 32.55 1.64 31.85 1.64 31.85 0.28 31.63 0.28 31.63 1.64 30.93 1.64 30.93 0.28 30.71 0.28 30.71 1.64 30.01 1.64 30.01 0.28 29.79 0.28 29.79 1.64 29.09 1.64 29.09 0.28 28.87 0.28 28.87 1.64 28.17 1.64 28.17 0.28 27.95 0.28 27.95 1.64 27.25 1.64 27.25 0.28 27.03 0.28 27.03 1.64 26.33 1.64 26.33 0.28 18.29 0.28 18.29 1.64 17.59 1.64 17.59 0.28 10.47 0.28 10.47 1.64 9.77 1.64 9.77 0.28 9.55 0.28 9.55 1.64 8.85 1.64 8.85 0.28 8.63 0.28 8.63 1.64 7.93 1.64 7.93 0.28 7.71 0.28 7.71 1.64 7.01 1.64 7.01 0.28 0.28 0.28 0.28 97.64 ; - LAYER met4 ; - POLYGON 91.6 97.52 91.6 11.28 81.66 11.28 81.66 11.88 80.26 11.88 80.26 11.28 65.84 11.28 65.84 0.4 55.9 0.4 55.9 1 54.5 1 54.5 0.4 52.99 0.4 52.99 1.76 51.89 1.76 51.89 0.4 51.15 0.4 51.15 1.76 50.05 1.76 50.05 0.4 49.31 0.4 49.31 1.76 48.21 1.76 48.21 0.4 47.47 0.4 47.47 1.76 46.37 1.76 46.37 0.4 41.18 0.4 41.18 1 39.78 1 39.78 0.4 29.99 0.4 29.99 1.76 28.89 1.76 28.89 0.4 28.15 0.4 28.15 1.76 27.05 1.76 27.05 0.4 26.46 0.4 26.46 1 25.06 1 25.06 0.4 11.74 0.4 11.74 1 10.34 1 10.34 0.4 9.75 0.4 9.75 1.76 8.65 1.76 8.65 0.4 7.91 0.4 7.91 1.76 6.81 1.76 6.81 0.4 6.07 0.4 6.07 1.76 4.97 1.76 4.97 0.4 0.4 0.4 0.4 97.52 10.34 97.52 10.34 96.92 11.74 96.92 11.74 97.52 25.06 97.52 25.06 96.92 26.46 96.92 26.46 97.52 39.78 97.52 39.78 96.92 41.18 96.92 41.18 97.52 54.5 97.52 54.5 96.92 55.9 96.92 55.9 97.52 80.26 97.52 80.26 96.92 81.66 96.92 81.66 97.52 ; - LAYER met5 ; - POLYGON 90.4 96.32 90.4 88.2 87.2 88.2 87.2 81.8 90.4 81.8 90.4 67.8 87.2 67.8 87.2 61.4 90.4 61.4 90.4 47.4 87.2 47.4 87.2 41 90.4 41 90.4 27 87.2 27 87.2 20.6 90.4 20.6 90.4 12.48 64.64 12.48 64.64 1.6 1.6 1.6 1.6 20.6 4.8 20.6 4.8 27 1.6 27 1.6 41 4.8 41 4.8 47.4 1.6 47.4 1.6 61.4 4.8 61.4 4.8 67.8 1.6 67.8 1.6 81.8 4.8 81.8 4.8 88.2 1.6 88.2 1.6 96.32 ; - LAYER met1 ; - POLYGON 91.72 97.4 91.72 95.72 91.24 95.72 91.24 94.68 91.72 94.68 91.72 93 91.24 93 91.24 91.96 91.72 91.96 91.72 90.28 91.24 90.28 91.24 89.24 91.72 89.24 91.72 87.56 91.24 87.56 91.24 86.52 91.72 86.52 91.72 84.84 91.24 84.84 91.24 83.8 91.72 83.8 91.72 82.12 91.24 82.12 91.24 81.08 91.72 81.08 91.72 79.4 91.24 79.4 91.24 78.36 91.72 78.36 91.72 76.68 91.24 76.68 91.24 75.64 91.72 75.64 91.72 73.96 91.24 73.96 91.24 72.92 91.72 72.92 91.72 71.24 91.24 71.24 91.24 70.2 91.72 70.2 91.72 68.52 91.24 68.52 91.24 67.48 91.72 67.48 91.72 65.8 91.24 65.8 91.24 64.76 91.72 64.76 91.72 63.08 91.24 63.08 91.24 62.04 91.72 62.04 91.72 60.36 91.24 60.36 91.24 59.32 91.72 59.32 91.72 57.64 91.24 57.64 91.24 56.6 91.72 56.6 91.72 54.92 91.24 54.92 91.24 53.88 91.72 53.88 91.72 52.2 91.24 52.2 91.24 51.16 91.72 51.16 91.72 49.48 91.24 49.48 91.24 48.44 91.72 48.44 91.72 46.76 91.24 46.76 91.24 45.72 91.72 45.72 91.72 44.04 91.24 44.04 91.24 43 91.72 43 91.72 41.32 91.24 41.32 91.24 40.28 91.72 40.28 91.72 38.6 91.24 38.6 91.24 37.56 91.72 37.56 91.72 35.88 91.24 35.88 91.24 34.84 91.72 34.84 91.72 33.16 91.24 33.16 91.24 32.12 91.72 32.12 91.72 30.44 91.24 30.44 91.24 29.4 91.72 29.4 91.72 27.72 91.24 27.72 91.24 26.68 91.72 26.68 91.72 25 91.24 25 91.24 23.96 91.72 23.96 91.72 22.28 91.24 22.28 91.24 21.24 91.72 21.24 91.72 19.56 91.24 19.56 91.24 18.52 91.72 18.52 91.72 16.84 91.24 16.84 91.24 15.8 91.72 15.8 91.72 14.12 91.24 14.12 91.24 13.08 91.72 13.08 91.72 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 0.76 81.08 0.76 82.12 0.28 82.12 0.28 83.8 0.76 83.8 0.76 84.84 0.28 84.84 0.28 86.52 0.76 86.52 0.76 87.56 0.28 87.56 0.28 89.24 0.76 89.24 0.76 90.28 0.28 90.28 0.28 91.96 0.76 91.96 0.76 93 0.28 93 0.28 94.68 0.76 94.68 0.76 95.72 0.28 95.72 0.28 97.4 ; - POLYGON 65.96 10.36 65.96 8.68 65.48 8.68 65.48 7.64 65.96 7.64 65.96 5.96 65.48 5.96 65.48 4.92 65.96 4.92 65.96 3.24 65.48 3.24 65.48 2.2 65.96 2.2 65.96 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 ; - LAYER li1 ; - POLYGON 91.83 97.75 91.83 11.05 66.07 11.05 66.07 0.17 0.17 0.17 0.17 97.75 ; - LAYER mcon ; - RECT 91.685 97.835 91.855 98.005 ; - RECT 91.225 97.835 91.395 98.005 ; - RECT 90.765 97.835 90.935 98.005 ; - RECT 90.305 97.835 90.475 98.005 ; - RECT 89.845 97.835 90.015 98.005 ; - RECT 89.385 97.835 89.555 98.005 ; - RECT 88.925 97.835 89.095 98.005 ; - RECT 88.465 97.835 88.635 98.005 ; - RECT 88.005 97.835 88.175 98.005 ; - RECT 87.545 97.835 87.715 98.005 ; - RECT 87.085 97.835 87.255 98.005 ; - RECT 86.625 97.835 86.795 98.005 ; - RECT 86.165 97.835 86.335 98.005 ; - RECT 85.705 97.835 85.875 98.005 ; - RECT 85.245 97.835 85.415 98.005 ; - RECT 84.785 97.835 84.955 98.005 ; - RECT 84.325 97.835 84.495 98.005 ; - RECT 83.865 97.835 84.035 98.005 ; - RECT 83.405 97.835 83.575 98.005 ; - RECT 82.945 97.835 83.115 98.005 ; - RECT 82.485 97.835 82.655 98.005 ; - RECT 82.025 97.835 82.195 98.005 ; - RECT 81.565 97.835 81.735 98.005 ; - RECT 81.105 97.835 81.275 98.005 ; - RECT 80.645 97.835 80.815 98.005 ; - RECT 80.185 97.835 80.355 98.005 ; - RECT 79.725 97.835 79.895 98.005 ; - RECT 79.265 97.835 79.435 98.005 ; - RECT 78.805 97.835 78.975 98.005 ; - RECT 78.345 97.835 78.515 98.005 ; - RECT 77.885 97.835 78.055 98.005 ; - RECT 77.425 97.835 77.595 98.005 ; - RECT 76.965 97.835 77.135 98.005 ; - RECT 76.505 97.835 76.675 98.005 ; - RECT 76.045 97.835 76.215 98.005 ; - RECT 75.585 97.835 75.755 98.005 ; - RECT 75.125 97.835 75.295 98.005 ; - RECT 74.665 97.835 74.835 98.005 ; - RECT 74.205 97.835 74.375 98.005 ; - RECT 73.745 97.835 73.915 98.005 ; - RECT 73.285 97.835 73.455 98.005 ; - RECT 72.825 97.835 72.995 98.005 ; - RECT 72.365 97.835 72.535 98.005 ; - RECT 71.905 97.835 72.075 98.005 ; - RECT 71.445 97.835 71.615 98.005 ; - RECT 70.985 97.835 71.155 98.005 ; - RECT 70.525 97.835 70.695 98.005 ; - RECT 70.065 97.835 70.235 98.005 ; - RECT 69.605 97.835 69.775 98.005 ; - RECT 69.145 97.835 69.315 98.005 ; - RECT 68.685 97.835 68.855 98.005 ; - RECT 68.225 97.835 68.395 98.005 ; - RECT 67.765 97.835 67.935 98.005 ; - RECT 67.305 97.835 67.475 98.005 ; - RECT 66.845 97.835 67.015 98.005 ; - RECT 66.385 97.835 66.555 98.005 ; - RECT 65.925 97.835 66.095 98.005 ; - RECT 65.465 97.835 65.635 98.005 ; - RECT 65.005 97.835 65.175 98.005 ; - RECT 64.545 97.835 64.715 98.005 ; - RECT 64.085 97.835 64.255 98.005 ; - RECT 63.625 97.835 63.795 98.005 ; - RECT 63.165 97.835 63.335 98.005 ; - RECT 62.705 97.835 62.875 98.005 ; - RECT 62.245 97.835 62.415 98.005 ; - RECT 61.785 97.835 61.955 98.005 ; - RECT 61.325 97.835 61.495 98.005 ; - RECT 60.865 97.835 61.035 98.005 ; - RECT 60.405 97.835 60.575 98.005 ; - RECT 59.945 97.835 60.115 98.005 ; - RECT 59.485 97.835 59.655 98.005 ; - RECT 59.025 97.835 59.195 98.005 ; - RECT 58.565 97.835 58.735 98.005 ; - RECT 58.105 97.835 58.275 98.005 ; - RECT 57.645 97.835 57.815 98.005 ; - RECT 57.185 97.835 57.355 98.005 ; - RECT 56.725 97.835 56.895 98.005 ; - RECT 56.265 97.835 56.435 98.005 ; - RECT 55.805 97.835 55.975 98.005 ; - RECT 55.345 97.835 55.515 98.005 ; - RECT 54.885 97.835 55.055 98.005 ; - RECT 54.425 97.835 54.595 98.005 ; - RECT 53.965 97.835 54.135 98.005 ; - RECT 53.505 97.835 53.675 98.005 ; - RECT 53.045 97.835 53.215 98.005 ; - RECT 52.585 97.835 52.755 98.005 ; - RECT 52.125 97.835 52.295 98.005 ; - RECT 51.665 97.835 51.835 98.005 ; - RECT 51.205 97.835 51.375 98.005 ; - RECT 50.745 97.835 50.915 98.005 ; - RECT 50.285 97.835 50.455 98.005 ; - RECT 49.825 97.835 49.995 98.005 ; - RECT 49.365 97.835 49.535 98.005 ; - RECT 48.905 97.835 49.075 98.005 ; - RECT 48.445 97.835 48.615 98.005 ; - RECT 47.985 97.835 48.155 98.005 ; - RECT 47.525 97.835 47.695 98.005 ; - RECT 47.065 97.835 47.235 98.005 ; - RECT 46.605 97.835 46.775 98.005 ; - RECT 46.145 97.835 46.315 98.005 ; - RECT 45.685 97.835 45.855 98.005 ; - RECT 45.225 97.835 45.395 98.005 ; - RECT 44.765 97.835 44.935 98.005 ; - RECT 44.305 97.835 44.475 98.005 ; - RECT 43.845 97.835 44.015 98.005 ; - RECT 43.385 97.835 43.555 98.005 ; - RECT 42.925 97.835 43.095 98.005 ; - RECT 42.465 97.835 42.635 98.005 ; - RECT 42.005 97.835 42.175 98.005 ; - RECT 41.545 97.835 41.715 98.005 ; - RECT 41.085 97.835 41.255 98.005 ; - RECT 40.625 97.835 40.795 98.005 ; - RECT 40.165 97.835 40.335 98.005 ; - RECT 39.705 97.835 39.875 98.005 ; - RECT 39.245 97.835 39.415 98.005 ; - RECT 38.785 97.835 38.955 98.005 ; - RECT 38.325 97.835 38.495 98.005 ; - RECT 37.865 97.835 38.035 98.005 ; - RECT 37.405 97.835 37.575 98.005 ; - RECT 36.945 97.835 37.115 98.005 ; - RECT 36.485 97.835 36.655 98.005 ; - RECT 36.025 97.835 36.195 98.005 ; - RECT 35.565 97.835 35.735 98.005 ; - RECT 35.105 97.835 35.275 98.005 ; - RECT 34.645 97.835 34.815 98.005 ; - RECT 34.185 97.835 34.355 98.005 ; - RECT 33.725 97.835 33.895 98.005 ; - RECT 33.265 97.835 33.435 98.005 ; - RECT 32.805 97.835 32.975 98.005 ; - RECT 32.345 97.835 32.515 98.005 ; - RECT 31.885 97.835 32.055 98.005 ; - RECT 31.425 97.835 31.595 98.005 ; - RECT 30.965 97.835 31.135 98.005 ; - RECT 30.505 97.835 30.675 98.005 ; - RECT 30.045 97.835 30.215 98.005 ; - RECT 29.585 97.835 29.755 98.005 ; - RECT 29.125 97.835 29.295 98.005 ; - RECT 28.665 97.835 28.835 98.005 ; - RECT 28.205 97.835 28.375 98.005 ; - RECT 27.745 97.835 27.915 98.005 ; - RECT 27.285 97.835 27.455 98.005 ; - RECT 26.825 97.835 26.995 98.005 ; - RECT 26.365 97.835 26.535 98.005 ; - RECT 25.905 97.835 26.075 98.005 ; - RECT 25.445 97.835 25.615 98.005 ; - RECT 24.985 97.835 25.155 98.005 ; - RECT 24.525 97.835 24.695 98.005 ; - RECT 24.065 97.835 24.235 98.005 ; - RECT 23.605 97.835 23.775 98.005 ; - RECT 23.145 97.835 23.315 98.005 ; - RECT 22.685 97.835 22.855 98.005 ; - RECT 22.225 97.835 22.395 98.005 ; - RECT 21.765 97.835 21.935 98.005 ; - RECT 21.305 97.835 21.475 98.005 ; - RECT 20.845 97.835 21.015 98.005 ; - RECT 20.385 97.835 20.555 98.005 ; - RECT 19.925 97.835 20.095 98.005 ; - RECT 19.465 97.835 19.635 98.005 ; - RECT 19.005 97.835 19.175 98.005 ; - RECT 18.545 97.835 18.715 98.005 ; - RECT 18.085 97.835 18.255 98.005 ; - RECT 17.625 97.835 17.795 98.005 ; - RECT 17.165 97.835 17.335 98.005 ; - RECT 16.705 97.835 16.875 98.005 ; - RECT 16.245 97.835 16.415 98.005 ; - RECT 15.785 97.835 15.955 98.005 ; - RECT 15.325 97.835 15.495 98.005 ; - RECT 14.865 97.835 15.035 98.005 ; - RECT 14.405 97.835 14.575 98.005 ; - RECT 13.945 97.835 14.115 98.005 ; - RECT 13.485 97.835 13.655 98.005 ; - RECT 13.025 97.835 13.195 98.005 ; - RECT 12.565 97.835 12.735 98.005 ; - RECT 12.105 97.835 12.275 98.005 ; - RECT 11.645 97.835 11.815 98.005 ; - RECT 11.185 97.835 11.355 98.005 ; - RECT 10.725 97.835 10.895 98.005 ; - RECT 10.265 97.835 10.435 98.005 ; - RECT 9.805 97.835 9.975 98.005 ; - RECT 9.345 97.835 9.515 98.005 ; - RECT 8.885 97.835 9.055 98.005 ; - RECT 8.425 97.835 8.595 98.005 ; - RECT 7.965 97.835 8.135 98.005 ; - RECT 7.505 97.835 7.675 98.005 ; - RECT 7.045 97.835 7.215 98.005 ; - RECT 6.585 97.835 6.755 98.005 ; - RECT 6.125 97.835 6.295 98.005 ; - RECT 5.665 97.835 5.835 98.005 ; - RECT 5.205 97.835 5.375 98.005 ; - RECT 4.745 97.835 4.915 98.005 ; - RECT 4.285 97.835 4.455 98.005 ; - RECT 3.825 97.835 3.995 98.005 ; - RECT 3.365 97.835 3.535 98.005 ; - RECT 2.905 97.835 3.075 98.005 ; - RECT 2.445 97.835 2.615 98.005 ; - RECT 1.985 97.835 2.155 98.005 ; - RECT 1.525 97.835 1.695 98.005 ; - RECT 1.065 97.835 1.235 98.005 ; - RECT 0.605 97.835 0.775 98.005 ; - RECT 0.145 97.835 0.315 98.005 ; - RECT 91.685 95.115 91.855 95.285 ; - RECT 91.225 95.115 91.395 95.285 ; - RECT 0.605 95.115 0.775 95.285 ; - RECT 0.145 95.115 0.315 95.285 ; - RECT 91.685 92.395 91.855 92.565 ; - RECT 91.225 92.395 91.395 92.565 ; - RECT 0.605 92.395 0.775 92.565 ; - RECT 0.145 92.395 0.315 92.565 ; - RECT 91.685 89.675 91.855 89.845 ; - RECT 91.225 89.675 91.395 89.845 ; - RECT 0.605 89.675 0.775 89.845 ; - RECT 0.145 89.675 0.315 89.845 ; - RECT 91.685 86.955 91.855 87.125 ; - RECT 91.225 86.955 91.395 87.125 ; - RECT 0.605 86.955 0.775 87.125 ; - RECT 0.145 86.955 0.315 87.125 ; - RECT 91.685 84.235 91.855 84.405 ; - RECT 91.225 84.235 91.395 84.405 ; - RECT 0.605 84.235 0.775 84.405 ; - RECT 0.145 84.235 0.315 84.405 ; - RECT 91.685 81.515 91.855 81.685 ; - RECT 91.225 81.515 91.395 81.685 ; - RECT 0.605 81.515 0.775 81.685 ; - RECT 0.145 81.515 0.315 81.685 ; - RECT 91.685 78.795 91.855 78.965 ; - RECT 91.225 78.795 91.395 78.965 ; - RECT 0.605 78.795 0.775 78.965 ; - RECT 0.145 78.795 0.315 78.965 ; - RECT 91.685 76.075 91.855 76.245 ; - RECT 91.225 76.075 91.395 76.245 ; - RECT 0.605 76.075 0.775 76.245 ; - RECT 0.145 76.075 0.315 76.245 ; - RECT 91.685 73.355 91.855 73.525 ; - RECT 91.225 73.355 91.395 73.525 ; - RECT 0.605 73.355 0.775 73.525 ; - RECT 0.145 73.355 0.315 73.525 ; - RECT 91.685 70.635 91.855 70.805 ; - RECT 91.225 70.635 91.395 70.805 ; - RECT 0.605 70.635 0.775 70.805 ; - RECT 0.145 70.635 0.315 70.805 ; - RECT 91.685 67.915 91.855 68.085 ; - RECT 91.225 67.915 91.395 68.085 ; - RECT 0.605 67.915 0.775 68.085 ; - RECT 0.145 67.915 0.315 68.085 ; - RECT 91.685 65.195 91.855 65.365 ; - RECT 91.225 65.195 91.395 65.365 ; - RECT 0.605 65.195 0.775 65.365 ; - RECT 0.145 65.195 0.315 65.365 ; - RECT 91.685 62.475 91.855 62.645 ; - RECT 91.225 62.475 91.395 62.645 ; - RECT 0.605 62.475 0.775 62.645 ; - RECT 0.145 62.475 0.315 62.645 ; - RECT 91.685 59.755 91.855 59.925 ; - RECT 91.225 59.755 91.395 59.925 ; - RECT 0.605 59.755 0.775 59.925 ; - RECT 0.145 59.755 0.315 59.925 ; - RECT 91.685 57.035 91.855 57.205 ; - RECT 91.225 57.035 91.395 57.205 ; - RECT 0.605 57.035 0.775 57.205 ; - RECT 0.145 57.035 0.315 57.205 ; - RECT 91.685 54.315 91.855 54.485 ; - RECT 91.225 54.315 91.395 54.485 ; - RECT 0.605 54.315 0.775 54.485 ; - RECT 0.145 54.315 0.315 54.485 ; - RECT 91.685 51.595 91.855 51.765 ; - RECT 91.225 51.595 91.395 51.765 ; - RECT 0.605 51.595 0.775 51.765 ; - RECT 0.145 51.595 0.315 51.765 ; - RECT 91.685 48.875 91.855 49.045 ; - RECT 91.225 48.875 91.395 49.045 ; - RECT 0.605 48.875 0.775 49.045 ; - RECT 0.145 48.875 0.315 49.045 ; - RECT 91.685 46.155 91.855 46.325 ; - RECT 91.225 46.155 91.395 46.325 ; - RECT 0.605 46.155 0.775 46.325 ; - RECT 0.145 46.155 0.315 46.325 ; - RECT 91.685 43.435 91.855 43.605 ; - RECT 91.225 43.435 91.395 43.605 ; - RECT 0.605 43.435 0.775 43.605 ; - RECT 0.145 43.435 0.315 43.605 ; - RECT 91.685 40.715 91.855 40.885 ; - RECT 91.225 40.715 91.395 40.885 ; - RECT 0.605 40.715 0.775 40.885 ; - RECT 0.145 40.715 0.315 40.885 ; - RECT 91.685 37.995 91.855 38.165 ; - RECT 91.225 37.995 91.395 38.165 ; - RECT 0.605 37.995 0.775 38.165 ; - RECT 0.145 37.995 0.315 38.165 ; - RECT 91.685 35.275 91.855 35.445 ; - RECT 91.225 35.275 91.395 35.445 ; - RECT 0.605 35.275 0.775 35.445 ; - RECT 0.145 35.275 0.315 35.445 ; - RECT 91.685 32.555 91.855 32.725 ; - RECT 91.225 32.555 91.395 32.725 ; - RECT 0.605 32.555 0.775 32.725 ; - RECT 0.145 32.555 0.315 32.725 ; - RECT 91.685 29.835 91.855 30.005 ; - RECT 91.225 29.835 91.395 30.005 ; - RECT 0.605 29.835 0.775 30.005 ; - RECT 0.145 29.835 0.315 30.005 ; - RECT 91.685 27.115 91.855 27.285 ; - RECT 91.225 27.115 91.395 27.285 ; - RECT 0.605 27.115 0.775 27.285 ; - RECT 0.145 27.115 0.315 27.285 ; - RECT 91.685 24.395 91.855 24.565 ; - RECT 91.225 24.395 91.395 24.565 ; - RECT 0.605 24.395 0.775 24.565 ; - RECT 0.145 24.395 0.315 24.565 ; - RECT 91.685 21.675 91.855 21.845 ; - RECT 91.225 21.675 91.395 21.845 ; - RECT 0.605 21.675 0.775 21.845 ; - RECT 0.145 21.675 0.315 21.845 ; - RECT 91.685 18.955 91.855 19.125 ; - RECT 91.225 18.955 91.395 19.125 ; - RECT 0.605 18.955 0.775 19.125 ; - RECT 0.145 18.955 0.315 19.125 ; - RECT 91.685 16.235 91.855 16.405 ; - RECT 91.225 16.235 91.395 16.405 ; - RECT 0.605 16.235 0.775 16.405 ; - RECT 0.145 16.235 0.315 16.405 ; - RECT 91.685 13.515 91.855 13.685 ; - RECT 91.225 13.515 91.395 13.685 ; - RECT 0.605 13.515 0.775 13.685 ; - RECT 0.145 13.515 0.315 13.685 ; - RECT 91.685 10.795 91.855 10.965 ; - RECT 91.225 10.795 91.395 10.965 ; - RECT 90.765 10.795 90.935 10.965 ; - RECT 90.305 10.795 90.475 10.965 ; - RECT 89.845 10.795 90.015 10.965 ; - RECT 89.385 10.795 89.555 10.965 ; - RECT 88.925 10.795 89.095 10.965 ; - RECT 88.465 10.795 88.635 10.965 ; - RECT 88.005 10.795 88.175 10.965 ; - RECT 87.545 10.795 87.715 10.965 ; - RECT 87.085 10.795 87.255 10.965 ; - RECT 86.625 10.795 86.795 10.965 ; - RECT 86.165 10.795 86.335 10.965 ; - RECT 85.705 10.795 85.875 10.965 ; - RECT 85.245 10.795 85.415 10.965 ; - RECT 84.785 10.795 84.955 10.965 ; - RECT 84.325 10.795 84.495 10.965 ; - RECT 83.865 10.795 84.035 10.965 ; - RECT 83.405 10.795 83.575 10.965 ; - RECT 82.945 10.795 83.115 10.965 ; - RECT 82.485 10.795 82.655 10.965 ; - RECT 82.025 10.795 82.195 10.965 ; - RECT 81.565 10.795 81.735 10.965 ; - RECT 81.105 10.795 81.275 10.965 ; - RECT 80.645 10.795 80.815 10.965 ; - RECT 80.185 10.795 80.355 10.965 ; - RECT 79.725 10.795 79.895 10.965 ; - RECT 79.265 10.795 79.435 10.965 ; - RECT 78.805 10.795 78.975 10.965 ; - RECT 78.345 10.795 78.515 10.965 ; - RECT 77.885 10.795 78.055 10.965 ; - RECT 77.425 10.795 77.595 10.965 ; - RECT 76.965 10.795 77.135 10.965 ; - RECT 76.505 10.795 76.675 10.965 ; - RECT 76.045 10.795 76.215 10.965 ; - RECT 75.585 10.795 75.755 10.965 ; - RECT 75.125 10.795 75.295 10.965 ; - RECT 74.665 10.795 74.835 10.965 ; - RECT 74.205 10.795 74.375 10.965 ; - RECT 73.745 10.795 73.915 10.965 ; - RECT 73.285 10.795 73.455 10.965 ; - RECT 72.825 10.795 72.995 10.965 ; - RECT 72.365 10.795 72.535 10.965 ; - RECT 71.905 10.795 72.075 10.965 ; - RECT 71.445 10.795 71.615 10.965 ; - RECT 70.985 10.795 71.155 10.965 ; - RECT 70.525 10.795 70.695 10.965 ; - RECT 70.065 10.795 70.235 10.965 ; - RECT 69.605 10.795 69.775 10.965 ; - RECT 69.145 10.795 69.315 10.965 ; - RECT 68.685 10.795 68.855 10.965 ; - RECT 68.225 10.795 68.395 10.965 ; - RECT 67.765 10.795 67.935 10.965 ; - RECT 67.305 10.795 67.475 10.965 ; - RECT 66.845 10.795 67.015 10.965 ; - RECT 66.385 10.795 66.555 10.965 ; - RECT 65.925 10.795 66.095 10.965 ; - RECT 65.465 10.795 65.635 10.965 ; - RECT 65.005 10.795 65.175 10.965 ; - RECT 64.545 10.795 64.715 10.965 ; - RECT 64.085 10.795 64.255 10.965 ; - RECT 63.625 10.795 63.795 10.965 ; - RECT 63.165 10.795 63.335 10.965 ; - RECT 62.705 10.795 62.875 10.965 ; - RECT 62.245 10.795 62.415 10.965 ; - RECT 61.785 10.795 61.955 10.965 ; - RECT 61.325 10.795 61.495 10.965 ; - RECT 60.865 10.795 61.035 10.965 ; - RECT 60.405 10.795 60.575 10.965 ; - RECT 59.945 10.795 60.115 10.965 ; - RECT 59.485 10.795 59.655 10.965 ; - RECT 59.025 10.795 59.195 10.965 ; - RECT 58.565 10.795 58.735 10.965 ; - RECT 58.105 10.795 58.275 10.965 ; - RECT 57.645 10.795 57.815 10.965 ; - RECT 57.185 10.795 57.355 10.965 ; - RECT 56.725 10.795 56.895 10.965 ; - RECT 56.265 10.795 56.435 10.965 ; - RECT 55.805 10.795 55.975 10.965 ; - RECT 55.345 10.795 55.515 10.965 ; - RECT 54.885 10.795 55.055 10.965 ; - RECT 54.425 10.795 54.595 10.965 ; - RECT 53.965 10.795 54.135 10.965 ; - RECT 53.505 10.795 53.675 10.965 ; - RECT 53.045 10.795 53.215 10.965 ; - RECT 52.585 10.795 52.755 10.965 ; - RECT 52.125 10.795 52.295 10.965 ; - RECT 51.665 10.795 51.835 10.965 ; - RECT 51.205 10.795 51.375 10.965 ; - RECT 50.745 10.795 50.915 10.965 ; - RECT 50.285 10.795 50.455 10.965 ; - RECT 49.825 10.795 49.995 10.965 ; - RECT 49.365 10.795 49.535 10.965 ; - RECT 48.905 10.795 49.075 10.965 ; - RECT 48.445 10.795 48.615 10.965 ; - RECT 47.985 10.795 48.155 10.965 ; - RECT 47.525 10.795 47.695 10.965 ; - RECT 47.065 10.795 47.235 10.965 ; - RECT 46.605 10.795 46.775 10.965 ; - RECT 46.145 10.795 46.315 10.965 ; - RECT 45.685 10.795 45.855 10.965 ; - RECT 45.225 10.795 45.395 10.965 ; - RECT 44.765 10.795 44.935 10.965 ; - RECT 44.305 10.795 44.475 10.965 ; - RECT 43.845 10.795 44.015 10.965 ; - RECT 43.385 10.795 43.555 10.965 ; - RECT 42.925 10.795 43.095 10.965 ; - RECT 42.465 10.795 42.635 10.965 ; - RECT 42.005 10.795 42.175 10.965 ; - RECT 41.545 10.795 41.715 10.965 ; - RECT 41.085 10.795 41.255 10.965 ; - RECT 40.625 10.795 40.795 10.965 ; - RECT 40.165 10.795 40.335 10.965 ; - RECT 39.705 10.795 39.875 10.965 ; - RECT 39.245 10.795 39.415 10.965 ; - RECT 38.785 10.795 38.955 10.965 ; - RECT 38.325 10.795 38.495 10.965 ; - RECT 37.865 10.795 38.035 10.965 ; - RECT 37.405 10.795 37.575 10.965 ; - RECT 36.945 10.795 37.115 10.965 ; - RECT 36.485 10.795 36.655 10.965 ; - RECT 36.025 10.795 36.195 10.965 ; - RECT 35.565 10.795 35.735 10.965 ; - RECT 35.105 10.795 35.275 10.965 ; - RECT 34.645 10.795 34.815 10.965 ; - RECT 34.185 10.795 34.355 10.965 ; - RECT 33.725 10.795 33.895 10.965 ; - RECT 33.265 10.795 33.435 10.965 ; - RECT 32.805 10.795 32.975 10.965 ; - RECT 32.345 10.795 32.515 10.965 ; - RECT 31.885 10.795 32.055 10.965 ; - RECT 31.425 10.795 31.595 10.965 ; - RECT 30.965 10.795 31.135 10.965 ; - RECT 30.505 10.795 30.675 10.965 ; - RECT 30.045 10.795 30.215 10.965 ; - RECT 29.585 10.795 29.755 10.965 ; - RECT 29.125 10.795 29.295 10.965 ; - RECT 28.665 10.795 28.835 10.965 ; - RECT 28.205 10.795 28.375 10.965 ; - RECT 27.745 10.795 27.915 10.965 ; - RECT 27.285 10.795 27.455 10.965 ; - RECT 26.825 10.795 26.995 10.965 ; - RECT 26.365 10.795 26.535 10.965 ; - RECT 25.905 10.795 26.075 10.965 ; - RECT 25.445 10.795 25.615 10.965 ; - RECT 24.985 10.795 25.155 10.965 ; - RECT 24.525 10.795 24.695 10.965 ; - RECT 24.065 10.795 24.235 10.965 ; - RECT 23.605 10.795 23.775 10.965 ; - RECT 23.145 10.795 23.315 10.965 ; - RECT 22.685 10.795 22.855 10.965 ; - RECT 22.225 10.795 22.395 10.965 ; - RECT 21.765 10.795 21.935 10.965 ; - RECT 21.305 10.795 21.475 10.965 ; - RECT 20.845 10.795 21.015 10.965 ; - RECT 20.385 10.795 20.555 10.965 ; - RECT 19.925 10.795 20.095 10.965 ; - RECT 19.465 10.795 19.635 10.965 ; - RECT 19.005 10.795 19.175 10.965 ; - RECT 18.545 10.795 18.715 10.965 ; - RECT 18.085 10.795 18.255 10.965 ; - RECT 17.625 10.795 17.795 10.965 ; - RECT 17.165 10.795 17.335 10.965 ; - RECT 16.705 10.795 16.875 10.965 ; - RECT 16.245 10.795 16.415 10.965 ; - RECT 15.785 10.795 15.955 10.965 ; - RECT 15.325 10.795 15.495 10.965 ; - RECT 14.865 10.795 15.035 10.965 ; - RECT 14.405 10.795 14.575 10.965 ; - RECT 13.945 10.795 14.115 10.965 ; - RECT 13.485 10.795 13.655 10.965 ; - RECT 13.025 10.795 13.195 10.965 ; - RECT 12.565 10.795 12.735 10.965 ; - RECT 12.105 10.795 12.275 10.965 ; - RECT 11.645 10.795 11.815 10.965 ; - RECT 11.185 10.795 11.355 10.965 ; - RECT 10.725 10.795 10.895 10.965 ; - RECT 10.265 10.795 10.435 10.965 ; - RECT 9.805 10.795 9.975 10.965 ; - RECT 9.345 10.795 9.515 10.965 ; - RECT 8.885 10.795 9.055 10.965 ; - RECT 8.425 10.795 8.595 10.965 ; - RECT 7.965 10.795 8.135 10.965 ; - RECT 7.505 10.795 7.675 10.965 ; - RECT 7.045 10.795 7.215 10.965 ; - RECT 6.585 10.795 6.755 10.965 ; - RECT 6.125 10.795 6.295 10.965 ; - RECT 5.665 10.795 5.835 10.965 ; - RECT 5.205 10.795 5.375 10.965 ; - RECT 4.745 10.795 4.915 10.965 ; - RECT 4.285 10.795 4.455 10.965 ; - RECT 3.825 10.795 3.995 10.965 ; - RECT 3.365 10.795 3.535 10.965 ; - RECT 2.905 10.795 3.075 10.965 ; - RECT 2.445 10.795 2.615 10.965 ; - RECT 1.985 10.795 2.155 10.965 ; - RECT 1.525 10.795 1.695 10.965 ; - RECT 1.065 10.795 1.235 10.965 ; - RECT 0.605 10.795 0.775 10.965 ; - RECT 0.145 10.795 0.315 10.965 ; - RECT 65.925 8.075 66.095 8.245 ; - RECT 65.465 8.075 65.635 8.245 ; - RECT 0.605 8.075 0.775 8.245 ; - RECT 0.145 8.075 0.315 8.245 ; - RECT 65.925 5.355 66.095 5.525 ; - RECT 65.465 5.355 65.635 5.525 ; - RECT 0.605 5.355 0.775 5.525 ; - RECT 0.145 5.355 0.315 5.525 ; - RECT 65.925 2.635 66.095 2.805 ; - RECT 65.465 2.635 65.635 2.805 ; - RECT 0.605 2.635 0.775 2.805 ; - RECT 0.145 2.635 0.315 2.805 ; - RECT 65.925 -0.085 66.095 0.085 ; - RECT 65.465 -0.085 65.635 0.085 ; - RECT 65.005 -0.085 65.175 0.085 ; - RECT 64.545 -0.085 64.715 0.085 ; - RECT 64.085 -0.085 64.255 0.085 ; - RECT 63.625 -0.085 63.795 0.085 ; - RECT 63.165 -0.085 63.335 0.085 ; - RECT 62.705 -0.085 62.875 0.085 ; - RECT 62.245 -0.085 62.415 0.085 ; - RECT 61.785 -0.085 61.955 0.085 ; - RECT 61.325 -0.085 61.495 0.085 ; - RECT 60.865 -0.085 61.035 0.085 ; - RECT 60.405 -0.085 60.575 0.085 ; - RECT 59.945 -0.085 60.115 0.085 ; - RECT 59.485 -0.085 59.655 0.085 ; - RECT 59.025 -0.085 59.195 0.085 ; - RECT 58.565 -0.085 58.735 0.085 ; - RECT 58.105 -0.085 58.275 0.085 ; - RECT 57.645 -0.085 57.815 0.085 ; - RECT 57.185 -0.085 57.355 0.085 ; - RECT 56.725 -0.085 56.895 0.085 ; - RECT 56.265 -0.085 56.435 0.085 ; - RECT 55.805 -0.085 55.975 0.085 ; - RECT 55.345 -0.085 55.515 0.085 ; - RECT 54.885 -0.085 55.055 0.085 ; - RECT 54.425 -0.085 54.595 0.085 ; - RECT 53.965 -0.085 54.135 0.085 ; - RECT 53.505 -0.085 53.675 0.085 ; - RECT 53.045 -0.085 53.215 0.085 ; - RECT 52.585 -0.085 52.755 0.085 ; - RECT 52.125 -0.085 52.295 0.085 ; - RECT 51.665 -0.085 51.835 0.085 ; - RECT 51.205 -0.085 51.375 0.085 ; - RECT 50.745 -0.085 50.915 0.085 ; - RECT 50.285 -0.085 50.455 0.085 ; - RECT 49.825 -0.085 49.995 0.085 ; - RECT 49.365 -0.085 49.535 0.085 ; - RECT 48.905 -0.085 49.075 0.085 ; - RECT 48.445 -0.085 48.615 0.085 ; - RECT 47.985 -0.085 48.155 0.085 ; - RECT 47.525 -0.085 47.695 0.085 ; - RECT 47.065 -0.085 47.235 0.085 ; - RECT 46.605 -0.085 46.775 0.085 ; - RECT 46.145 -0.085 46.315 0.085 ; - RECT 45.685 -0.085 45.855 0.085 ; - RECT 45.225 -0.085 45.395 0.085 ; - RECT 44.765 -0.085 44.935 0.085 ; - RECT 44.305 -0.085 44.475 0.085 ; - RECT 43.845 -0.085 44.015 0.085 ; - RECT 43.385 -0.085 43.555 0.085 ; - RECT 42.925 -0.085 43.095 0.085 ; - RECT 42.465 -0.085 42.635 0.085 ; - RECT 42.005 -0.085 42.175 0.085 ; - RECT 41.545 -0.085 41.715 0.085 ; - RECT 41.085 -0.085 41.255 0.085 ; - RECT 40.625 -0.085 40.795 0.085 ; - RECT 40.165 -0.085 40.335 0.085 ; - RECT 39.705 -0.085 39.875 0.085 ; - RECT 39.245 -0.085 39.415 0.085 ; - RECT 38.785 -0.085 38.955 0.085 ; - RECT 38.325 -0.085 38.495 0.085 ; - RECT 37.865 -0.085 38.035 0.085 ; - RECT 37.405 -0.085 37.575 0.085 ; - RECT 36.945 -0.085 37.115 0.085 ; - RECT 36.485 -0.085 36.655 0.085 ; - RECT 36.025 -0.085 36.195 0.085 ; - RECT 35.565 -0.085 35.735 0.085 ; - RECT 35.105 -0.085 35.275 0.085 ; - RECT 34.645 -0.085 34.815 0.085 ; - RECT 34.185 -0.085 34.355 0.085 ; - RECT 33.725 -0.085 33.895 0.085 ; - RECT 33.265 -0.085 33.435 0.085 ; - RECT 32.805 -0.085 32.975 0.085 ; - RECT 32.345 -0.085 32.515 0.085 ; - RECT 31.885 -0.085 32.055 0.085 ; - RECT 31.425 -0.085 31.595 0.085 ; - RECT 30.965 -0.085 31.135 0.085 ; - RECT 30.505 -0.085 30.675 0.085 ; - RECT 30.045 -0.085 30.215 0.085 ; - RECT 29.585 -0.085 29.755 0.085 ; - RECT 29.125 -0.085 29.295 0.085 ; - RECT 28.665 -0.085 28.835 0.085 ; - RECT 28.205 -0.085 28.375 0.085 ; - RECT 27.745 -0.085 27.915 0.085 ; - RECT 27.285 -0.085 27.455 0.085 ; - RECT 26.825 -0.085 26.995 0.085 ; - RECT 26.365 -0.085 26.535 0.085 ; - RECT 25.905 -0.085 26.075 0.085 ; - RECT 25.445 -0.085 25.615 0.085 ; - RECT 24.985 -0.085 25.155 0.085 ; - RECT 24.525 -0.085 24.695 0.085 ; - RECT 24.065 -0.085 24.235 0.085 ; - RECT 23.605 -0.085 23.775 0.085 ; - RECT 23.145 -0.085 23.315 0.085 ; - RECT 22.685 -0.085 22.855 0.085 ; - RECT 22.225 -0.085 22.395 0.085 ; - RECT 21.765 -0.085 21.935 0.085 ; - RECT 21.305 -0.085 21.475 0.085 ; - RECT 20.845 -0.085 21.015 0.085 ; - RECT 20.385 -0.085 20.555 0.085 ; - RECT 19.925 -0.085 20.095 0.085 ; - RECT 19.465 -0.085 19.635 0.085 ; - RECT 19.005 -0.085 19.175 0.085 ; - RECT 18.545 -0.085 18.715 0.085 ; - RECT 18.085 -0.085 18.255 0.085 ; - RECT 17.625 -0.085 17.795 0.085 ; - RECT 17.165 -0.085 17.335 0.085 ; - RECT 16.705 -0.085 16.875 0.085 ; - RECT 16.245 -0.085 16.415 0.085 ; - RECT 15.785 -0.085 15.955 0.085 ; - RECT 15.325 -0.085 15.495 0.085 ; - RECT 14.865 -0.085 15.035 0.085 ; - RECT 14.405 -0.085 14.575 0.085 ; - RECT 13.945 -0.085 14.115 0.085 ; - RECT 13.485 -0.085 13.655 0.085 ; - RECT 13.025 -0.085 13.195 0.085 ; - RECT 12.565 -0.085 12.735 0.085 ; - RECT 12.105 -0.085 12.275 0.085 ; - RECT 11.645 -0.085 11.815 0.085 ; - RECT 11.185 -0.085 11.355 0.085 ; - RECT 10.725 -0.085 10.895 0.085 ; - RECT 10.265 -0.085 10.435 0.085 ; - RECT 9.805 -0.085 9.975 0.085 ; - RECT 9.345 -0.085 9.515 0.085 ; - RECT 8.885 -0.085 9.055 0.085 ; - RECT 8.425 -0.085 8.595 0.085 ; - RECT 7.965 -0.085 8.135 0.085 ; - RECT 7.505 -0.085 7.675 0.085 ; - RECT 7.045 -0.085 7.215 0.085 ; - RECT 6.585 -0.085 6.755 0.085 ; - RECT 6.125 -0.085 6.295 0.085 ; - RECT 5.665 -0.085 5.835 0.085 ; - RECT 5.205 -0.085 5.375 0.085 ; - RECT 4.745 -0.085 4.915 0.085 ; - RECT 4.285 -0.085 4.455 0.085 ; - RECT 3.825 -0.085 3.995 0.085 ; - RECT 3.365 -0.085 3.535 0.085 ; - RECT 2.905 -0.085 3.075 0.085 ; - RECT 2.445 -0.085 2.615 0.085 ; - RECT 1.985 -0.085 2.155 0.085 ; - RECT 1.525 -0.085 1.695 0.085 ; - RECT 1.065 -0.085 1.235 0.085 ; - RECT 0.605 -0.085 0.775 0.085 ; - RECT 0.145 -0.085 0.315 0.085 ; - LAYER via ; - RECT 55.125 97.845 55.275 97.995 ; - RECT 25.685 97.845 25.835 97.995 ; - RECT 85.025 12.505 85.175 12.655 ; - RECT 55.125 10.805 55.275 10.955 ; - RECT 25.685 10.805 25.835 10.955 ; - RECT 55.125 -0.075 55.275 0.075 ; - RECT 25.685 -0.075 25.835 0.075 ; - LAYER via2 ; - RECT 55.1 97.82 55.3 98.02 ; - RECT 25.66 97.82 25.86 98.02 ; - RECT 90.06 78.78 90.26 78.98 ; - RECT 1.28 77.42 1.48 77.62 ; - RECT 90.52 48.18 90.72 48.38 ; - RECT 1.28 47.5 1.48 47.7 ; - RECT 90.52 29.14 90.72 29.34 ; - RECT 90.06 24.38 90.26 24.58 ; - RECT 55.1 -0.1 55.3 0.1 ; - RECT 25.66 -0.1 25.86 0.1 ; - LAYER via3 ; - RECT 55.1 97.82 55.3 98.02 ; - RECT 25.66 97.82 25.86 98.02 ; - RECT 55.1 -0.1 55.3 0.1 ; - RECT 25.66 -0.1 25.86 0.1 ; - LAYER OVERLAP ; - POLYGON 0 0 0 97.92 92 97.92 92 10.88 66.24 10.88 66.24 0 ; - END -END sb_0__2_ - -END LIBRARY diff --git a/FPGA22_HIER_SKY_PNR/modules/lef/sb_1__0__icv_in_design.lef b/FPGA22_HIER_SKY_PNR/modules/lef/sb_1__0__icv_in_design.lef deleted file mode 100644 index 1e482d1..0000000 --- a/FPGA22_HIER_SKY_PNR/modules/lef/sb_1__0__icv_in_design.lef +++ /dev/null @@ -1,2606 +0,0 @@ -VERSION 5.7 ; -BUSBITCHARS "[]" ; - -UNITS - DATABASE MICRONS 1000 ; -END UNITS - -MANUFACTURINGGRID 0.005 ; - -LAYER li1 - TYPE ROUTING ; - DIRECTION VERTICAL ; - PITCH 0.46 ; - WIDTH 0.17 ; -END li1 - -LAYER mcon - TYPE CUT ; -END mcon - -LAYER met1 - TYPE ROUTING ; - DIRECTION HORIZONTAL ; - PITCH 0.34 ; - WIDTH 0.14 ; -END met1 - -LAYER via - TYPE CUT ; -END via - -LAYER met2 - TYPE ROUTING ; - DIRECTION VERTICAL ; - PITCH 0.46 ; - WIDTH 0.14 ; -END met2 - -LAYER via2 - TYPE CUT ; -END via2 - -LAYER met3 - TYPE ROUTING ; - DIRECTION HORIZONTAL ; - PITCH 0.68 ; - WIDTH 0.3 ; -END met3 - -LAYER via3 - TYPE CUT ; -END via3 - -LAYER met4 - TYPE ROUTING ; - DIRECTION VERTICAL ; - PITCH 0.92 ; - WIDTH 0.3 ; -END met4 - -LAYER via4 - TYPE CUT ; -END via4 - -LAYER met5 - TYPE ROUTING ; - DIRECTION HORIZONTAL ; - PITCH 3.4 ; - WIDTH 1.6 ; -END met5 - -LAYER nwell - TYPE MASTERSLICE ; -END nwell - -LAYER pwell - TYPE MASTERSLICE ; -END pwell - -LAYER OVERLAP - TYPE OVERLAP ; -END OVERLAP - -VIA L1M1_PR - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.145 -0.115 0.145 0.115 ; -END L1M1_PR - -VIA L1M1_PR_R - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.115 -0.145 0.115 0.145 ; -END L1M1_PR_R - -VIA L1M1_PR_M - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.115 -0.145 0.115 0.145 ; -END L1M1_PR_M - -VIA L1M1_PR_MR - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.145 -0.115 0.145 0.115 ; -END L1M1_PR_MR - -VIA L1M1_PR_C - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.145 -0.145 0.145 0.145 ; -END L1M1_PR_C - -VIA M1M2_PR - LAYER met1 ; - RECT -0.16 -0.13 0.16 0.13 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.13 -0.16 0.13 0.16 ; -END M1M2_PR - -VIA M1M2_PR_Enc - LAYER met1 ; - RECT -0.16 -0.13 0.16 0.13 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.16 -0.13 0.16 0.13 ; -END M1M2_PR_Enc - -VIA M1M2_PR_R - LAYER met1 ; - RECT -0.13 -0.16 0.13 0.16 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.16 -0.13 0.16 0.13 ; -END M1M2_PR_R - -VIA M1M2_PR_R_Enc - LAYER met1 ; - RECT -0.13 -0.16 0.13 0.16 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.13 -0.16 0.13 0.16 ; -END M1M2_PR_R_Enc - -VIA M1M2_PR_M - LAYER met1 ; - RECT -0.16 -0.13 0.16 0.13 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.16 -0.13 0.16 0.13 ; -END M1M2_PR_M - -VIA M1M2_PR_M_Enc - LAYER met1 ; - RECT -0.16 -0.13 0.16 0.13 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.13 -0.16 0.13 0.16 ; -END M1M2_PR_M_Enc - -VIA M1M2_PR_MR - LAYER met1 ; - RECT -0.13 -0.16 0.13 0.16 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.13 -0.16 0.13 0.16 ; -END M1M2_PR_MR - -VIA M1M2_PR_MR_Enc - LAYER met1 ; - RECT -0.13 -0.16 0.13 0.16 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.16 -0.13 0.16 0.13 ; -END M1M2_PR_MR_Enc - -VIA M1M2_PR_C - LAYER met1 ; - RECT -0.16 -0.16 0.16 0.16 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.16 -0.16 0.16 0.16 ; -END M1M2_PR_C - -VIA M2M3_PR - LAYER met2 ; - RECT -0.14 -0.185 0.14 0.185 ; - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met3 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M2M3_PR - -VIA M2M3_PR_R - LAYER met2 ; - RECT -0.185 -0.14 0.185 0.14 ; - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met3 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M2M3_PR_R - -VIA M2M3_PR_M - LAYER met2 ; - RECT -0.14 -0.185 0.14 0.185 ; - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met3 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M2M3_PR_M - -VIA M2M3_PR_MR - LAYER met2 ; - RECT -0.185 -0.14 0.185 0.14 ; - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met3 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M2M3_PR_MR - -VIA M2M3_PR_C - LAYER met2 ; - RECT -0.185 -0.185 0.185 0.185 ; - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met3 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M2M3_PR_C - -VIA M3M4_PR - LAYER met3 ; - RECT -0.19 -0.16 0.19 0.16 ; - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR - -VIA M3M4_PR_R - LAYER met3 ; - RECT -0.16 -0.19 0.16 0.19 ; - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR_R - -VIA M3M4_PR_M - LAYER met3 ; - RECT -0.19 -0.16 0.19 0.16 ; - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR_M - -VIA M3M4_PR_MR - LAYER met3 ; - RECT -0.16 -0.19 0.16 0.19 ; - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR_MR - -VIA M3M4_PR_C - LAYER met3 ; - RECT -0.19 -0.19 0.19 0.19 ; - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR_C - -VIA M4M5_PR - LAYER met4 ; - RECT -0.59 -0.59 0.59 0.59 ; - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - LAYER met5 ; - RECT -0.71 -0.71 0.71 0.71 ; -END M4M5_PR - -VIA M4M5_PR_R - LAYER met4 ; - RECT -0.59 -0.59 0.59 0.59 ; - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - LAYER met5 ; - RECT -0.71 -0.71 0.71 0.71 ; -END M4M5_PR_R - -VIA M4M5_PR_M - LAYER met4 ; - RECT -0.59 -0.59 0.59 0.59 ; - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - LAYER met5 ; - RECT -0.71 -0.71 0.71 0.71 ; -END M4M5_PR_M - -VIA M4M5_PR_MR - LAYER met4 ; - RECT -0.59 -0.59 0.59 0.59 ; - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - LAYER met5 ; - RECT -0.71 -0.71 0.71 0.71 ; -END M4M5_PR_MR - -VIA M4M5_PR_C - LAYER met4 ; - RECT -0.59 -0.59 0.59 0.59 ; - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - LAYER met5 ; - RECT -0.71 -0.71 0.71 0.71 ; -END M4M5_PR_C - -SITE unit - CLASS CORE ; - SYMMETRY Y ; - SIZE 0.46 BY 2.72 ; -END unit - -SITE unithddbl - CLASS CORE ; - SIZE 0.46 BY 5.44 ; -END unithddbl - -MACRO sb_1__0_ - CLASS BLOCK ; - ORIGIN 0 0 ; - SIZE 117.76 BY 97.92 ; - SYMMETRY X Y ; - PIN prog_clk[0] - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER met2 ; - RECT 55.59 0 55.73 1.36 ; - END - END prog_clk[0] - PIN chany_top_in[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 63.87 96.56 64.01 97.92 ; - END - END chany_top_in[0] - PIN chany_top_in[1] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 59.27 96.56 59.41 97.92 ; - END - END chany_top_in[1] - PIN chany_top_in[2] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 67.93 96.56 68.23 97.92 ; - END - END chany_top_in[2] - PIN chany_top_in[3] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 78.13 96.56 78.27 97.92 ; - END - END chany_top_in[3] - PIN chany_top_in[4] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 58.35 96.56 58.49 97.92 ; - END - END chany_top_in[4] - PIN chany_top_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 68.93 96.56 69.07 97.92 ; - END - END chany_top_in[5] - PIN chany_top_in[6] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 46.39 96.56 46.53 97.92 ; - END - END chany_top_in[6] - PIN chany_top_in[7] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 73.53 96.56 73.67 97.92 ; - END - END chany_top_in[7] - PIN chany_top_in[8] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 56.51 96.56 56.65 97.92 ; - END - END chany_top_in[8] - PIN chany_top_in[9] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 77.21 96.56 77.35 97.92 ; - END - END chany_top_in[9] - PIN chany_top_in[10] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 66.17 96.56 66.31 97.92 ; - END - END chany_top_in[10] - PIN chany_top_in[11] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 43.63 96.56 43.77 97.92 ; - END - END chany_top_in[11] - PIN chany_top_in[12] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 63.33 96.56 63.63 97.92 ; - END - END chany_top_in[12] - PIN chany_top_in[13] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 49.61 96.56 49.75 97.92 ; - END - END chany_top_in[13] - PIN chany_top_in[14] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 83.19 96.56 83.33 97.92 ; - END - END chany_top_in[14] - PIN chany_top_in[15] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 45.47 96.56 45.61 97.92 ; - END - END chany_top_in[15] - PIN chany_top_in[16] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 79.05 96.56 79.19 97.92 ; - END - END chany_top_in[16] - PIN chany_top_in[17] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 67.09 96.56 67.23 97.92 ; - END - END chany_top_in[17] - PIN chany_top_in[18] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 44.55 96.56 44.69 97.92 ; - END - END chany_top_in[18] - PIN chany_top_in[19] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 60.65 96.56 60.79 97.92 ; - END - END chany_top_in[19] - PIN top_left_grid_pin_42_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 9.13 85.68 9.27 87.04 ; - END - END top_left_grid_pin_42_[0] - PIN top_left_grid_pin_43_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 6.83 85.68 6.97 87.04 ; - END - END top_left_grid_pin_43_[0] - PIN top_left_grid_pin_44_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 12.81 85.68 12.95 87.04 ; - END - END top_left_grid_pin_44_[0] - PIN top_left_grid_pin_45_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 27.99 96.56 28.13 97.92 ; - END - END top_left_grid_pin_45_[0] - PIN top_left_grid_pin_46_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 14.19 85.68 14.33 87.04 ; - END - END top_left_grid_pin_46_[0] - PIN top_left_grid_pin_47_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 7.75 85.68 7.89 87.04 ; - END - END top_left_grid_pin_47_[0] - PIN top_left_grid_pin_48_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 16.03 85.68 16.17 87.04 ; - END - END top_left_grid_pin_48_[0] - PIN top_left_grid_pin_49_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 28.91 96.56 29.05 97.92 ; - END - END top_left_grid_pin_49_[0] - PIN chanx_right_in[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 73.29 117.76 73.59 ; - END - END chanx_right_in[0] - PIN chanx_right_in[1] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 71.93 117.76 72.23 ; - END - END chanx_right_in[1] - PIN chanx_right_in[2] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 9.37 117.76 9.67 ; - END - END chanx_right_in[2] - PIN chanx_right_in[3] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 21.61 117.76 21.91 ; - END - END chanx_right_in[3] - PIN chanx_right_in[4] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 76.01 117.76 76.31 ; - END - END chanx_right_in[4] - PIN chanx_right_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 22.97 117.76 23.27 ; - END - END chanx_right_in[5] - PIN chanx_right_in[6] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 42.01 117.76 42.31 ; - END - END chanx_right_in[6] - PIN chanx_right_in[7] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 36.57 117.76 36.87 ; - END - END chanx_right_in[7] - PIN chanx_right_in[8] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 24.33 117.76 24.63 ; - END - END chanx_right_in[8] - PIN chanx_right_in[9] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 44.73 117.76 45.03 ; - END - END chanx_right_in[9] - PIN chanx_right_in[10] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 54.93 117.76 55.23 ; - END - END chanx_right_in[10] - PIN chanx_right_in[11] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 31.13 117.76 31.43 ; - END - END chanx_right_in[11] - PIN chanx_right_in[12] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 12.09 117.76 12.39 ; - END - END chanx_right_in[12] - PIN chanx_right_in[13] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 83.49 117.76 83.79 ; - END - END chanx_right_in[13] - PIN chanx_right_in[14] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 77.37 117.76 77.67 ; - END - END chanx_right_in[14] - PIN chanx_right_in[15] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 26.37 117.76 26.67 ; - END - END chanx_right_in[15] - PIN chanx_right_in[16] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 32.49 117.76 32.79 ; - END - END chanx_right_in[16] - PIN chanx_right_in[17] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 10.73 117.76 11.03 ; - END - END chanx_right_in[17] - PIN chanx_right_in[18] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 35.21 117.76 35.51 ; - END - END chanx_right_in[18] - PIN chanx_right_in[19] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 28.41 117.76 28.71 ; - END - END chanx_right_in[19] - PIN right_bottom_grid_pin_1_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 74.65 117.76 74.95 ; - END - END right_bottom_grid_pin_1_[0] - PIN right_bottom_grid_pin_3_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 59.69 117.76 59.99 ; - END - END right_bottom_grid_pin_3_[0] - PIN right_bottom_grid_pin_5_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 66.49 117.76 66.79 ; - END - END right_bottom_grid_pin_5_[0] - PIN right_bottom_grid_pin_7_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 50.17 117.76 50.47 ; - END - END right_bottom_grid_pin_7_[0] - PIN right_bottom_grid_pin_9_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 61.73 117.76 62.03 ; - END - END right_bottom_grid_pin_9_[0] - PIN right_bottom_grid_pin_11_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 48.81 117.76 49.11 ; - END - END right_bottom_grid_pin_11_[0] - PIN chanx_left_in[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 11.41 1.38 11.71 ; - END - END chanx_left_in[0] - PIN chanx_left_in[1] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 66.49 1.38 66.79 ; - END - END chanx_left_in[1] - PIN chanx_left_in[2] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 10.05 1.38 10.35 ; - END - END chanx_left_in[2] - PIN chanx_left_in[3] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 21.61 1.38 21.91 ; - END - END chanx_left_in[3] - PIN chanx_left_in[4] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 78.73 1.38 79.03 ; - END - END chanx_left_in[4] - PIN chanx_left_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 15.49 1.38 15.79 ; - END - END chanx_left_in[5] - PIN chanx_left_in[6] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 33.17 1.38 33.47 ; - END - END chanx_left_in[6] - PIN chanx_left_in[7] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 83.49 1.38 83.79 ; - END - END chanx_left_in[7] - PIN chanx_left_in[8] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 25.69 1.38 25.99 ; - END - END chanx_left_in[8] - PIN chanx_left_in[9] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 34.53 1.38 34.83 ; - END - END chanx_left_in[9] - PIN chanx_left_in[10] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 39.29 1.38 39.59 ; - END - END chanx_left_in[10] - PIN chanx_left_in[11] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 18.21 1.38 18.51 ; - END - END chanx_left_in[11] - PIN chanx_left_in[12] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 76.01 1.38 76.31 ; - END - END chanx_left_in[12] - PIN chanx_left_in[13] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 69.21 1.38 69.51 ; - END - END chanx_left_in[13] - PIN chanx_left_in[14] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 42.01 1.38 42.31 ; - END - END chanx_left_in[14] - PIN chanx_left_in[15] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 46.09 1.38 46.39 ; - END - END chanx_left_in[15] - PIN chanx_left_in[16] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 29.77 1.38 30.07 ; - END - END chanx_left_in[16] - PIN chanx_left_in[17] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 24.33 1.38 24.63 ; - END - END chanx_left_in[17] - PIN chanx_left_in[18] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 22.97 1.38 23.27 ; - END - END chanx_left_in[18] - PIN chanx_left_in[19] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 67.85 1.38 68.15 ; - END - END chanx_left_in[19] - PIN left_bottom_grid_pin_1_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 63.77 1.38 64.07 ; - END - END left_bottom_grid_pin_1_[0] - PIN left_bottom_grid_pin_3_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 31.13 1.38 31.43 ; - END - END left_bottom_grid_pin_3_[0] - PIN left_bottom_grid_pin_5_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 43.37 1.38 43.67 ; - END - END left_bottom_grid_pin_5_[0] - PIN left_bottom_grid_pin_7_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 54.25 1.38 54.55 ; - END - END left_bottom_grid_pin_7_[0] - PIN left_bottom_grid_pin_9_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 61.73 1.38 62.03 ; - END - END left_bottom_grid_pin_9_[0] - PIN left_bottom_grid_pin_11_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 37.25 1.38 37.55 ; - END - END left_bottom_grid_pin_11_[0] - PIN ccff_head[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 13.45 117.76 13.75 ; - END - END ccff_head[0] - PIN chany_top_out[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 79.97 96.56 80.11 97.92 ; - END - END chany_top_out[0] - PIN chany_top_out[1] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 62.49 96.56 62.63 97.92 ; - END - END chany_top_out[1] - PIN chany_top_out[2] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 47.31 96.56 47.45 97.92 ; - END - END chany_top_out[2] - PIN chany_top_out[3] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 75.37 96.56 75.51 97.92 ; - END - END chany_top_out[3] - PIN chany_top_out[4] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 52.37 96.56 52.51 97.92 ; - END - END chany_top_out[4] - PIN chany_top_out[5] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 76.29 96.56 76.43 97.92 ; - END - END chany_top_out[5] - PIN chany_top_out[6] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 57.43 96.56 57.57 97.92 ; - END - END chany_top_out[6] - PIN chany_top_out[7] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 69.85 96.56 69.99 97.92 ; - END - END chany_top_out[7] - PIN chany_top_out[8] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 48.23 96.56 48.37 97.92 ; - END - END chany_top_out[8] - PIN chany_top_out[9] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 71.23 96.56 71.37 97.92 ; - END - END chany_top_out[9] - PIN chany_top_out[10] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 61.57 96.56 61.71 97.92 ; - END - END chany_top_out[10] - PIN chany_top_out[11] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 64.79 96.56 64.93 97.92 ; - END - END chany_top_out[11] - PIN chany_top_out[12] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 84.11 96.56 84.25 97.92 ; - END - END chany_top_out[12] - PIN chany_top_out[13] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 68.01 96.56 68.15 97.92 ; - END - END chany_top_out[13] - PIN chany_top_out[14] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 34.43 96.56 34.57 97.92 ; - END - END chany_top_out[14] - PIN chany_top_out[15] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 72.61 96.56 72.75 97.92 ; - END - END chany_top_out[15] - PIN chany_top_out[16] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 50.53 96.56 50.67 97.92 ; - END - END chany_top_out[16] - PIN chany_top_out[17] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 74.45 96.56 74.59 97.92 ; - END - END chany_top_out[17] - PIN chany_top_out[18] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 53.29 96.56 53.43 97.92 ; - END - END chany_top_out[18] - PIN chany_top_out[19] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 82.27 96.56 82.41 97.92 ; - END - END chany_top_out[19] - PIN chanx_right_out[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 56.97 117.76 57.27 ; - END - END chanx_right_out[0] - PIN chanx_right_out[1] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 67.85 117.76 68.15 ; - END - END chanx_right_out[1] - PIN chanx_right_out[2] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 43.37 117.76 43.67 ; - END - END chanx_right_out[2] - PIN chanx_right_out[3] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 80.09 117.76 80.39 ; - END - END chanx_right_out[3] - PIN chanx_right_out[4] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 33.85 117.76 34.15 ; - END - END chanx_right_out[4] - PIN chanx_right_out[5] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 82.13 117.76 82.43 ; - END - END chanx_right_out[5] - PIN chanx_right_out[6] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 39.29 117.76 39.59 ; - END - END chanx_right_out[6] - PIN chanx_right_out[7] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 53.57 117.76 53.87 ; - END - END chanx_right_out[7] - PIN chanx_right_out[8] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 47.45 117.76 47.75 ; - END - END chanx_right_out[8] - PIN chanx_right_out[9] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 78.73 117.76 79.03 ; - END - END chanx_right_out[9] - PIN chanx_right_out[10] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 46.09 117.76 46.39 ; - END - END chanx_right_out[10] - PIN chanx_right_out[11] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 69.21 117.76 69.51 ; - END - END chanx_right_out[11] - PIN chanx_right_out[12] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 40.65 117.76 40.95 ; - END - END chanx_right_out[12] - PIN chanx_right_out[13] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 37.93 117.76 38.23 ; - END - END chanx_right_out[13] - PIN chanx_right_out[14] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 29.77 117.76 30.07 ; - END - END chanx_right_out[14] - PIN chanx_right_out[15] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 52.21 117.76 52.51 ; - END - END chanx_right_out[15] - PIN chanx_right_out[16] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 58.33 117.76 58.63 ; - END - END chanx_right_out[16] - PIN chanx_right_out[17] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 63.09 117.76 63.39 ; - END - END chanx_right_out[17] - PIN chanx_right_out[18] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 70.57 117.76 70.87 ; - END - END chanx_right_out[18] - PIN chanx_right_out[19] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 65.13 117.76 65.43 ; - END - END chanx_right_out[19] - PIN chanx_left_out[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 59.69 1.38 59.99 ; - END - END chanx_left_out[0] - PIN chanx_left_out[1] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 56.29 1.38 56.59 ; - END - END chanx_left_out[1] - PIN chanx_left_out[2] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 77.37 1.38 77.67 ; - END - END chanx_left_out[2] - PIN chanx_left_out[3] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 80.09 1.38 80.39 ; - END - END chanx_left_out[3] - PIN chanx_left_out[4] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 48.13 1.38 48.43 ; - END - END chanx_left_out[4] - PIN chanx_left_out[5] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 82.13 1.38 82.43 ; - END - END chanx_left_out[5] - PIN chanx_left_out[6] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 73.29 1.38 73.59 ; - END - END chanx_left_out[6] - PIN chanx_left_out[7] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 58.33 1.38 58.63 ; - END - END chanx_left_out[7] - PIN chanx_left_out[8] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 19.57 1.38 19.87 ; - END - END chanx_left_out[8] - PIN chanx_left_out[9] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 44.73 1.38 45.03 ; - END - END chanx_left_out[9] - PIN chanx_left_out[10] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 71.93 1.38 72.23 ; - END - END chanx_left_out[10] - PIN chanx_left_out[11] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 70.57 1.38 70.87 ; - END - END chanx_left_out[11] - PIN chanx_left_out[12] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 74.65 1.38 74.95 ; - END - END chanx_left_out[12] - PIN chanx_left_out[13] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 65.13 1.38 65.43 ; - END - END chanx_left_out[13] - PIN chanx_left_out[14] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 27.73 1.38 28.03 ; - END - END chanx_left_out[14] - PIN chanx_left_out[15] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 49.49 1.38 49.79 ; - END - END chanx_left_out[15] - PIN chanx_left_out[16] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 40.65 1.38 40.95 ; - END - END chanx_left_out[16] - PIN chanx_left_out[17] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 8.69 1.38 8.99 ; - END - END chanx_left_out[17] - PIN chanx_left_out[18] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 50.85 1.38 51.15 ; - END - END chanx_left_out[18] - PIN chanx_left_out[19] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 52.21 1.38 52.51 ; - END - END chanx_left_out[19] - PIN ccff_tail[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 16.85 1.38 17.15 ; - END - END ccff_tail[0] - PIN SC_IN_TOP - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 35.89 1.38 36.19 ; - END - END SC_IN_TOP - PIN SC_IN_BOT - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 58.73 96.56 59.03 97.92 ; - END - END SC_IN_BOT - PIN SC_OUT_TOP - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 54.21 96.56 54.35 97.92 ; - END - END SC_OUT_TOP - PIN SC_OUT_BOT - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 115.39 85.68 115.53 87.04 ; - END - END SC_OUT_BOT - PIN VDD - DIRECTION INPUT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0 2.48 0.48 2.96 ; - RECT 117.28 2.48 117.76 2.96 ; - RECT 0 7.92 0.48 8.4 ; - RECT 117.28 7.92 117.76 8.4 ; - RECT 0 13.36 0.48 13.84 ; - RECT 117.28 13.36 117.76 13.84 ; - RECT 0 18.8 0.48 19.28 ; - RECT 117.28 18.8 117.76 19.28 ; - RECT 0 24.24 0.48 24.72 ; - RECT 117.28 24.24 117.76 24.72 ; - RECT 0 29.68 0.48 30.16 ; - RECT 117.28 29.68 117.76 30.16 ; - RECT 0 35.12 0.48 35.6 ; - RECT 117.28 35.12 117.76 35.6 ; - RECT 0 40.56 0.48 41.04 ; - RECT 117.28 40.56 117.76 41.04 ; - RECT 0 46 0.48 46.48 ; - RECT 117.28 46 117.76 46.48 ; - RECT 0 51.44 0.48 51.92 ; - RECT 117.28 51.44 117.76 51.92 ; - RECT 0 56.88 0.48 57.36 ; - RECT 117.28 56.88 117.76 57.36 ; - RECT 0 62.32 0.48 62.8 ; - RECT 117.28 62.32 117.76 62.8 ; - RECT 0 67.76 0.48 68.24 ; - RECT 117.28 67.76 117.76 68.24 ; - RECT 0 73.2 0.48 73.68 ; - RECT 117.28 73.2 117.76 73.68 ; - RECT 0 78.64 0.48 79.12 ; - RECT 117.28 78.64 117.76 79.12 ; - RECT 0 84.08 0.48 84.56 ; - RECT 117.28 84.08 117.76 84.56 ; - RECT 25.76 89.52 26.24 90 ; - RECT 91.52 89.52 92 90 ; - RECT 25.76 94.96 26.24 95.44 ; - RECT 91.52 94.96 92 95.44 ; - LAYER met4 ; - RECT 36.5 0 37.1 0.6 ; - RECT 65.94 0 66.54 0.6 ; - RECT 106.42 0 107.02 0.6 ; - RECT 106.42 86.44 107.02 87.04 ; - RECT 36.5 97.32 37.1 97.92 ; - RECT 65.94 97.32 66.54 97.92 ; - LAYER met5 ; - RECT 0 11.32 3.2 14.52 ; - RECT 114.56 11.32 117.76 14.52 ; - RECT 0 52.12 3.2 55.32 ; - RECT 114.56 52.12 117.76 55.32 ; - END - END VDD - PIN VSS - DIRECTION INPUT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0 0 117.76 0.24 ; - RECT 0 5.2 0.48 5.68 ; - RECT 117.28 5.2 117.76 5.68 ; - RECT 0 10.64 0.48 11.12 ; - RECT 117.28 10.64 117.76 11.12 ; - RECT 0 16.08 0.48 16.56 ; - RECT 117.28 16.08 117.76 16.56 ; - RECT 0 21.52 0.48 22 ; - RECT 117.28 21.52 117.76 22 ; - RECT 0 26.96 0.48 27.44 ; - RECT 117.28 26.96 117.76 27.44 ; - RECT 0 32.4 0.48 32.88 ; - RECT 117.28 32.4 117.76 32.88 ; - RECT 0 37.84 0.48 38.32 ; - RECT 117.28 37.84 117.76 38.32 ; - RECT 0 43.28 0.48 43.76 ; - RECT 117.28 43.28 117.76 43.76 ; - RECT 0 48.72 0.48 49.2 ; - RECT 117.28 48.72 117.76 49.2 ; - RECT 0 54.16 0.48 54.64 ; - RECT 117.28 54.16 117.76 54.64 ; - RECT 0 59.6 0.48 60.08 ; - RECT 117.28 59.6 117.76 60.08 ; - RECT 0 65.04 0.48 65.52 ; - RECT 117.28 65.04 117.76 65.52 ; - RECT 0 70.48 0.48 70.96 ; - RECT 117.28 70.48 117.76 70.96 ; - RECT 0 75.92 0.48 76.4 ; - RECT 117.28 75.92 117.76 76.4 ; - RECT 0 81.36 0.48 81.84 ; - RECT 117.28 81.36 117.76 81.84 ; - RECT 0 86.8 117.76 87.28 ; - RECT 25.76 92.24 26.24 92.72 ; - RECT 91.52 92.24 92 92.72 ; - RECT 25.76 97.68 92 97.92 ; - LAYER met4 ; - RECT 10.74 0 11.34 0.6 ; - RECT 51.22 0 51.82 0.6 ; - RECT 80.66 0 81.26 0.6 ; - RECT 10.74 86.44 11.34 87.04 ; - RECT 51.22 97.32 51.82 97.92 ; - RECT 80.66 97.32 81.26 97.92 ; - LAYER met5 ; - RECT 0 31.72 3.2 34.92 ; - RECT 114.56 31.72 117.76 34.92 ; - RECT 0 72.52 3.2 75.72 ; - RECT 114.56 72.52 117.76 75.72 ; - END - END VSS - PIN prog_clk__FEEDTHRU_1[0] - DIRECTION OUTPUT ; - USE CLOCK ; - PORT - LAYER met3 ; - RECT 0 13.45 1.38 13.75 ; - END - END prog_clk__FEEDTHRU_1[0] - PIN prog_clk__FEEDTHRU_2[0] - DIRECTION OUTPUT ; - USE CLOCK ; - PORT - LAYER met2 ; - RECT 55.13 96.56 55.27 97.92 ; - END - END prog_clk__FEEDTHRU_2[0] - OBS - LAYER li1 ; - RECT 25.76 97.835 92 98.005 ; - RECT 91.54 95.115 92 95.285 ; - RECT 25.76 95.115 29.44 95.285 ; - RECT 91.08 92.395 92 92.565 ; - RECT 25.76 92.395 29.44 92.565 ; - RECT 91.08 89.675 92 89.845 ; - RECT 25.76 89.675 29.44 89.845 ; - RECT 89.24 86.955 117.76 87.125 ; - RECT 0 86.955 29.44 87.125 ; - RECT 116.84 84.235 117.76 84.405 ; - RECT 0 84.235 3.68 84.405 ; - RECT 116.84 81.515 117.76 81.685 ; - RECT 0 81.515 1.84 81.685 ; - RECT 116.84 78.795 117.76 78.965 ; - RECT 0 78.795 1.84 78.965 ; - RECT 116.84 76.075 117.76 76.245 ; - RECT 0 76.075 1.84 76.245 ; - RECT 116.84 73.355 117.76 73.525 ; - RECT 0 73.355 1.84 73.525 ; - RECT 116.84 70.635 117.76 70.805 ; - RECT 0 70.635 1.84 70.805 ; - RECT 116.84 67.915 117.76 68.085 ; - RECT 0 67.915 1.84 68.085 ; - RECT 116.84 65.195 117.76 65.365 ; - RECT 0 65.195 1.84 65.365 ; - RECT 116.84 62.475 117.76 62.645 ; - RECT 0 62.475 1.84 62.645 ; - RECT 116.84 59.755 117.76 59.925 ; - RECT 0 59.755 1.84 59.925 ; - RECT 116.84 57.035 117.76 57.205 ; - RECT 0 57.035 1.84 57.205 ; - RECT 116.84 54.315 117.76 54.485 ; - RECT 0 54.315 1.84 54.485 ; - RECT 116.84 51.595 117.76 51.765 ; - RECT 0 51.595 1.84 51.765 ; - RECT 116.84 48.875 117.76 49.045 ; - RECT 0 48.875 1.84 49.045 ; - RECT 116.84 46.155 117.76 46.325 ; - RECT 0 46.155 1.84 46.325 ; - RECT 116.84 43.435 117.76 43.605 ; - RECT 0 43.435 1.84 43.605 ; - RECT 116.84 40.715 117.76 40.885 ; - RECT 0 40.715 3.68 40.885 ; - RECT 114.08 37.995 117.76 38.165 ; - RECT 0 37.995 3.68 38.165 ; - RECT 114.08 35.275 117.76 35.445 ; - RECT 0 35.275 3.68 35.445 ; - RECT 116.84 32.555 117.76 32.725 ; - RECT 0 32.555 3.68 32.725 ; - RECT 115.92 29.835 117.76 30.005 ; - RECT 0 29.835 3.68 30.005 ; - RECT 115.92 27.115 117.76 27.285 ; - RECT 0 27.115 1.84 27.285 ; - RECT 116.84 24.395 117.76 24.565 ; - RECT 0 24.395 3.68 24.565 ; - RECT 117.3 21.675 117.76 21.845 ; - RECT 0 21.675 3.68 21.845 ; - RECT 117.3 18.955 117.76 19.125 ; - RECT 0 18.955 1.84 19.125 ; - RECT 117.3 16.235 117.76 16.405 ; - RECT 0 16.235 3.68 16.405 ; - RECT 117.3 13.515 117.76 13.685 ; - RECT 0 13.515 3.68 13.685 ; - RECT 117.3 10.795 117.76 10.965 ; - RECT 0 10.795 1.84 10.965 ; - RECT 117.3 8.075 117.76 8.245 ; - RECT 0 8.075 3.68 8.245 ; - RECT 115.92 5.355 117.76 5.525 ; - RECT 0 5.355 3.68 5.525 ; - RECT 115.92 2.635 117.76 2.805 ; - RECT 0 2.635 3.68 2.805 ; - RECT 0 -0.085 117.76 0.085 ; - LAYER met2 ; - RECT 80.82 97.735 81.1 98.105 ; - RECT 51.38 97.735 51.66 98.105 ; - POLYGON 74.13 96.63 74.13 96.38 74.19 96.38 74.19 96.06 73.93 96.06 73.93 96.28 73.95 96.28 73.95 96.63 ; - RECT 78.53 96.06 78.79 96.38 ; - RECT 64.27 96.06 64.53 96.38 ; - RECT 55.53 96.06 55.79 96.38 ; - RECT 10.9 86.855 11.18 87.225 ; - RECT 80.82 -0.185 81.1 0.185 ; - RECT 51.38 -0.185 51.66 0.185 ; - RECT 10.9 -0.185 11.18 0.185 ; - POLYGON 91.72 97.64 91.72 86.76 115.11 86.76 115.11 85.4 115.81 85.4 115.81 86.76 117.48 86.76 117.48 0.28 56.01 0.28 56.01 1.64 55.31 1.64 55.31 0.28 0.28 0.28 0.28 86.76 6.55 86.76 6.55 85.4 7.25 85.4 7.25 86.76 7.47 86.76 7.47 85.4 8.17 85.4 8.17 86.76 8.85 86.76 8.85 85.4 9.55 85.4 9.55 86.76 12.53 86.76 12.53 85.4 13.23 85.4 13.23 86.76 13.91 86.76 13.91 85.4 14.61 85.4 14.61 86.76 15.75 86.76 15.75 85.4 16.45 85.4 16.45 86.76 26.04 86.76 26.04 97.64 27.71 97.64 27.71 96.28 28.41 96.28 28.41 97.64 28.63 97.64 28.63 96.28 29.33 96.28 29.33 97.64 34.15 97.64 34.15 96.28 34.85 96.28 34.85 97.64 43.35 97.64 43.35 96.28 44.05 96.28 44.05 97.64 44.27 97.64 44.27 96.28 44.97 96.28 44.97 97.64 45.19 97.64 45.19 96.28 45.89 96.28 45.89 97.64 46.11 97.64 46.11 96.28 46.81 96.28 46.81 97.64 47.03 97.64 47.03 96.28 47.73 96.28 47.73 97.64 47.95 97.64 47.95 96.28 48.65 96.28 48.65 97.64 49.33 97.64 49.33 96.28 50.03 96.28 50.03 97.64 50.25 97.64 50.25 96.28 50.95 96.28 50.95 97.64 52.09 97.64 52.09 96.28 52.79 96.28 52.79 97.64 53.01 97.64 53.01 96.28 53.71 96.28 53.71 97.64 53.93 97.64 53.93 96.28 54.63 96.28 54.63 97.64 54.85 97.64 54.85 96.28 55.55 96.28 55.55 97.64 56.23 97.64 56.23 96.28 56.93 96.28 56.93 97.64 57.15 97.64 57.15 96.28 57.85 96.28 57.85 97.64 58.07 97.64 58.07 96.28 58.77 96.28 58.77 97.64 58.99 97.64 58.99 96.28 59.69 96.28 59.69 97.64 60.37 97.64 60.37 96.28 61.07 96.28 61.07 97.64 61.29 97.64 61.29 96.28 61.99 96.28 61.99 97.64 62.21 97.64 62.21 96.28 62.91 96.28 62.91 97.64 63.59 97.64 63.59 96.28 64.29 96.28 64.29 97.64 64.51 97.64 64.51 96.28 65.21 96.28 65.21 97.64 65.89 97.64 65.89 96.28 66.59 96.28 66.59 97.64 66.81 97.64 66.81 96.28 67.51 96.28 67.51 97.64 67.73 97.64 67.73 96.28 68.43 96.28 68.43 97.64 68.65 97.64 68.65 96.28 69.35 96.28 69.35 97.64 69.57 97.64 69.57 96.28 70.27 96.28 70.27 97.64 70.95 97.64 70.95 96.28 71.65 96.28 71.65 97.64 72.33 97.64 72.33 96.28 73.03 96.28 73.03 97.64 73.25 97.64 73.25 96.28 73.95 96.28 73.95 97.64 74.17 97.64 74.17 96.28 74.87 96.28 74.87 97.64 75.09 97.64 75.09 96.28 75.79 96.28 75.79 97.64 76.01 97.64 76.01 96.28 76.71 96.28 76.71 97.64 76.93 97.64 76.93 96.28 77.63 96.28 77.63 97.64 77.85 97.64 77.85 96.28 78.55 96.28 78.55 97.64 78.77 97.64 78.77 96.28 79.47 96.28 79.47 97.64 79.69 97.64 79.69 96.28 80.39 96.28 80.39 97.64 81.99 97.64 81.99 96.28 82.69 96.28 82.69 97.64 82.91 97.64 82.91 96.28 83.61 96.28 83.61 97.64 83.83 97.64 83.83 96.28 84.53 96.28 84.53 97.64 ; - LAYER met4 ; - POLYGON 91.6 97.52 91.6 86.64 106.02 86.64 106.02 86.04 107.42 86.04 107.42 86.64 117.36 86.64 117.36 0.4 107.42 0.4 107.42 1 106.02 1 106.02 0.4 81.66 0.4 81.66 1 80.26 1 80.26 0.4 66.94 0.4 66.94 1 65.54 1 65.54 0.4 52.22 0.4 52.22 1 50.82 1 50.82 0.4 37.5 0.4 37.5 1 36.1 1 36.1 0.4 11.74 0.4 11.74 1 10.34 1 10.34 0.4 0.4 0.4 0.4 86.64 10.34 86.64 10.34 86.04 11.74 86.04 11.74 86.64 26.16 86.64 26.16 97.52 36.1 97.52 36.1 96.92 37.5 96.92 37.5 97.52 50.82 97.52 50.82 96.92 52.22 96.92 52.22 97.52 58.33 97.52 58.33 96.16 59.43 96.16 59.43 97.52 62.93 97.52 62.93 96.16 64.03 96.16 64.03 97.52 65.54 97.52 65.54 96.92 66.94 96.92 66.94 97.52 67.53 97.52 67.53 96.16 68.63 96.16 68.63 97.52 80.26 97.52 80.26 96.92 81.66 96.92 81.66 97.52 ; - LAYER met3 ; - POLYGON 81.125 98.085 81.125 98.08 81.34 98.08 81.34 97.76 81.125 97.76 81.125 97.755 80.795 97.755 80.795 97.76 80.58 97.76 80.58 98.08 80.795 98.08 80.795 98.085 ; - POLYGON 51.685 98.085 51.685 98.08 51.9 98.08 51.9 97.76 51.685 97.76 51.685 97.755 51.355 97.755 51.355 97.76 51.14 97.76 51.14 98.08 51.355 98.08 51.355 98.085 ; - POLYGON 11.205 87.205 11.205 87.2 11.42 87.2 11.42 86.88 11.205 86.88 11.205 86.875 10.875 86.875 10.875 86.88 10.66 86.88 10.66 87.2 10.875 87.2 10.875 87.205 ; - POLYGON 2.03 78.36 2.03 78.35 5.21 78.35 5.21 78.05 2.03 78.05 2.03 78.04 1.65 78.04 1.65 78.36 ; - POLYGON 2.005 77.005 2.005 77 2.03 77 2.03 76.68 2.005 76.68 2.005 76.675 1.275 76.675 1.275 77.005 ; - RECT 1.69 73.97 2.45 74.27 ; - POLYGON 87.55 23.95 87.55 23.65 1.78 23.65 1.78 23.67 1.23 23.67 1.23 23.95 ; - POLYGON 81.125 0.165 81.125 0.16 81.34 0.16 81.34 -0.16 81.125 -0.16 81.125 -0.165 80.795 -0.165 80.795 -0.16 80.58 -0.16 80.58 0.16 80.795 0.16 80.795 0.165 ; - POLYGON 51.685 0.165 51.685 0.16 51.9 0.16 51.9 -0.16 51.685 -0.16 51.685 -0.165 51.355 -0.165 51.355 -0.16 51.14 -0.16 51.14 0.16 51.355 0.16 51.355 0.165 ; - POLYGON 11.205 0.165 11.205 0.16 11.42 0.16 11.42 -0.16 11.205 -0.16 11.205 -0.165 10.875 -0.165 10.875 -0.16 10.66 -0.16 10.66 0.16 10.875 0.16 10.875 0.165 ; - POLYGON 91.6 97.52 91.6 86.64 117.36 86.64 117.36 84.19 115.98 84.19 115.98 83.09 117.36 83.09 117.36 82.83 115.98 82.83 115.98 81.73 117.36 81.73 117.36 80.79 115.98 80.79 115.98 79.69 117.36 79.69 117.36 79.43 115.98 79.43 115.98 78.33 117.36 78.33 117.36 78.07 115.98 78.07 115.98 76.97 117.36 76.97 117.36 76.71 115.98 76.71 115.98 75.61 117.36 75.61 117.36 75.35 115.98 75.35 115.98 74.25 117.36 74.25 117.36 73.99 115.98 73.99 115.98 72.89 117.36 72.89 117.36 72.63 115.98 72.63 115.98 71.53 117.36 71.53 117.36 71.27 115.98 71.27 115.98 70.17 117.36 70.17 117.36 69.91 115.98 69.91 115.98 68.81 117.36 68.81 117.36 68.55 115.98 68.55 115.98 67.45 117.36 67.45 117.36 67.19 115.98 67.19 115.98 66.09 117.36 66.09 117.36 65.83 115.98 65.83 115.98 64.73 117.36 64.73 117.36 63.79 115.98 63.79 115.98 62.69 117.36 62.69 117.36 62.43 115.98 62.43 115.98 61.33 117.36 61.33 117.36 60.39 115.98 60.39 115.98 59.29 117.36 59.29 117.36 59.03 115.98 59.03 115.98 57.93 117.36 57.93 117.36 57.67 115.98 57.67 115.98 56.57 117.36 56.57 117.36 55.63 115.98 55.63 115.98 54.53 117.36 54.53 117.36 54.27 115.98 54.27 115.98 53.17 117.36 53.17 117.36 52.91 115.98 52.91 115.98 51.81 117.36 51.81 117.36 50.87 115.98 50.87 115.98 49.77 117.36 49.77 117.36 49.51 115.98 49.51 115.98 48.41 117.36 48.41 117.36 48.15 115.98 48.15 115.98 47.05 117.36 47.05 117.36 46.79 115.98 46.79 115.98 45.69 117.36 45.69 117.36 45.43 115.98 45.43 115.98 44.33 117.36 44.33 117.36 44.07 115.98 44.07 115.98 42.97 117.36 42.97 117.36 42.71 115.98 42.71 115.98 41.61 117.36 41.61 117.36 41.35 115.98 41.35 115.98 40.25 117.36 40.25 117.36 39.99 115.98 39.99 115.98 38.89 117.36 38.89 117.36 38.63 115.98 38.63 115.98 37.53 117.36 37.53 117.36 37.27 115.98 37.27 115.98 36.17 117.36 36.17 117.36 35.91 115.98 35.91 115.98 34.81 117.36 34.81 117.36 34.55 115.98 34.55 115.98 33.45 117.36 33.45 117.36 33.19 115.98 33.19 115.98 32.09 117.36 32.09 117.36 31.83 115.98 31.83 115.98 30.73 117.36 30.73 117.36 30.47 115.98 30.47 115.98 29.37 117.36 29.37 117.36 29.11 115.98 29.11 115.98 28.01 117.36 28.01 117.36 27.07 115.98 27.07 115.98 25.97 117.36 25.97 117.36 25.03 115.98 25.03 115.98 23.93 117.36 23.93 117.36 23.67 115.98 23.67 115.98 22.57 117.36 22.57 117.36 22.31 115.98 22.31 115.98 21.21 117.36 21.21 117.36 14.15 115.98 14.15 115.98 13.05 117.36 13.05 117.36 12.79 115.98 12.79 115.98 11.69 117.36 11.69 117.36 11.43 115.98 11.43 115.98 10.33 117.36 10.33 117.36 10.07 115.98 10.07 115.98 8.97 117.36 8.97 117.36 0.4 0.4 0.4 0.4 8.29 1.78 8.29 1.78 9.39 0.4 9.39 0.4 9.65 1.78 9.65 1.78 10.75 0.4 10.75 0.4 11.01 1.78 11.01 1.78 12.11 0.4 12.11 0.4 13.05 1.78 13.05 1.78 14.15 0.4 14.15 0.4 15.09 1.78 15.09 1.78 16.19 0.4 16.19 0.4 16.45 1.78 16.45 1.78 17.55 0.4 17.55 0.4 17.81 1.78 17.81 1.78 18.91 0.4 18.91 0.4 19.17 1.78 19.17 1.78 20.27 0.4 20.27 0.4 21.21 1.78 21.21 1.78 22.31 0.4 22.31 0.4 22.57 1.78 22.57 1.78 23.67 0.4 23.67 0.4 23.93 1.78 23.93 1.78 25.03 0.4 25.03 0.4 25.29 1.78 25.29 1.78 26.39 0.4 26.39 0.4 27.33 1.78 27.33 1.78 28.43 0.4 28.43 0.4 29.37 1.78 29.37 1.78 30.47 0.4 30.47 0.4 30.73 1.78 30.73 1.78 31.83 0.4 31.83 0.4 32.77 1.78 32.77 1.78 33.87 0.4 33.87 0.4 34.13 1.78 34.13 1.78 35.23 0.4 35.23 0.4 35.49 1.78 35.49 1.78 36.59 0.4 36.59 0.4 36.85 1.78 36.85 1.78 37.95 0.4 37.95 0.4 38.89 1.78 38.89 1.78 39.99 0.4 39.99 0.4 40.25 1.78 40.25 1.78 41.35 0.4 41.35 0.4 41.61 1.78 41.61 1.78 42.71 0.4 42.71 0.4 42.97 1.78 42.97 1.78 44.07 0.4 44.07 0.4 44.33 1.78 44.33 1.78 45.43 0.4 45.43 0.4 45.69 1.78 45.69 1.78 46.79 0.4 46.79 0.4 47.73 1.78 47.73 1.78 48.83 0.4 48.83 0.4 49.09 1.78 49.09 1.78 50.19 0.4 50.19 0.4 50.45 1.78 50.45 1.78 51.55 0.4 51.55 0.4 51.81 1.78 51.81 1.78 52.91 0.4 52.91 0.4 53.85 1.78 53.85 1.78 54.95 0.4 54.95 0.4 55.89 1.78 55.89 1.78 56.99 0.4 56.99 0.4 57.93 1.78 57.93 1.78 59.03 0.4 59.03 0.4 59.29 1.78 59.29 1.78 60.39 0.4 60.39 0.4 61.33 1.78 61.33 1.78 62.43 0.4 62.43 0.4 63.37 1.78 63.37 1.78 64.47 0.4 64.47 0.4 64.73 1.78 64.73 1.78 65.83 0.4 65.83 0.4 66.09 1.78 66.09 1.78 67.19 0.4 67.19 0.4 67.45 1.78 67.45 1.78 68.55 0.4 68.55 0.4 68.81 1.78 68.81 1.78 69.91 0.4 69.91 0.4 70.17 1.78 70.17 1.78 71.27 0.4 71.27 0.4 71.53 1.78 71.53 1.78 72.63 0.4 72.63 0.4 72.89 1.78 72.89 1.78 73.99 0.4 73.99 0.4 74.25 1.78 74.25 1.78 75.35 0.4 75.35 0.4 75.61 1.78 75.61 1.78 76.71 0.4 76.71 0.4 76.97 1.78 76.97 1.78 78.07 0.4 78.07 0.4 78.33 1.78 78.33 1.78 79.43 0.4 79.43 0.4 79.69 1.78 79.69 1.78 80.79 0.4 80.79 0.4 81.73 1.78 81.73 1.78 82.83 0.4 82.83 0.4 83.09 1.78 83.09 1.78 84.19 0.4 84.19 0.4 86.64 26.16 86.64 26.16 97.52 ; - LAYER met5 ; - POLYGON 90.4 96.32 90.4 85.44 116.16 85.44 116.16 77.32 112.96 77.32 112.96 70.92 116.16 70.92 116.16 56.92 112.96 56.92 112.96 50.52 116.16 50.52 116.16 36.52 112.96 36.52 112.96 30.12 116.16 30.12 116.16 16.12 112.96 16.12 112.96 9.72 116.16 9.72 116.16 1.6 1.6 1.6 1.6 9.72 4.8 9.72 4.8 16.12 1.6 16.12 1.6 30.12 4.8 30.12 4.8 36.52 1.6 36.52 1.6 50.52 4.8 50.52 4.8 56.92 1.6 56.92 1.6 70.92 4.8 70.92 4.8 77.32 1.6 77.32 1.6 85.44 27.36 85.44 27.36 96.32 ; - LAYER met1 ; - POLYGON 91.72 97.4 91.72 95.72 91.24 95.72 91.24 94.68 91.72 94.68 91.72 93 91.24 93 91.24 91.96 91.72 91.96 91.72 90.28 91.24 90.28 91.24 89.24 91.72 89.24 91.72 87.56 26.04 87.56 26.04 89.24 26.52 89.24 26.52 90.28 26.04 90.28 26.04 91.96 26.52 91.96 26.52 93 26.04 93 26.04 94.68 26.52 94.68 26.52 95.72 26.04 95.72 26.04 97.4 ; - POLYGON 117.48 86.52 117.48 84.84 117 84.84 117 83.8 117.48 83.8 117.48 82.12 117 82.12 117 81.08 117.48 81.08 117.48 79.4 117 79.4 117 78.36 117.48 78.36 117.48 76.68 117 76.68 117 75.64 117.48 75.64 117.48 73.96 117 73.96 117 72.92 117.48 72.92 117.48 71.24 117 71.24 117 70.2 117.48 70.2 117.48 68.52 117 68.52 117 67.48 117.48 67.48 117.48 65.8 117 65.8 117 64.76 117.48 64.76 117.48 63.08 117 63.08 117 62.04 117.48 62.04 117.48 60.36 117 60.36 117 59.32 117.48 59.32 117.48 57.64 117 57.64 117 56.6 117.48 56.6 117.48 54.92 117 54.92 117 53.88 117.48 53.88 117.48 52.2 117 52.2 117 51.16 117.48 51.16 117.48 49.48 117 49.48 117 48.44 117.48 48.44 117.48 46.76 117 46.76 117 45.72 117.48 45.72 117.48 44.04 117 44.04 117 43 117.48 43 117.48 41.32 117 41.32 117 40.28 117.48 40.28 117.48 38.6 117 38.6 117 37.56 117.48 37.56 117.48 35.88 117 35.88 117 34.84 117.48 34.84 117.48 33.16 117 33.16 117 32.12 117.48 32.12 117.48 30.44 117 30.44 117 29.4 117.48 29.4 117.48 27.72 117 27.72 117 26.68 117.48 26.68 117.48 25 117 25 117 23.96 117.48 23.96 117.48 22.28 117 22.28 117 21.24 117.48 21.24 117.48 19.56 117 19.56 117 18.52 117.48 18.52 117.48 16.84 117 16.84 117 15.8 117.48 15.8 117.48 14.12 117 14.12 117 13.08 117.48 13.08 117.48 11.4 117 11.4 117 10.36 117.48 10.36 117.48 8.68 117 8.68 117 7.64 117.48 7.64 117.48 5.96 117 5.96 117 4.92 117.48 4.92 117.48 3.24 117 3.24 117 2.2 117.48 2.2 117.48 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 0.76 10.36 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 0.76 81.08 0.76 82.12 0.28 82.12 0.28 83.8 0.76 83.8 0.76 84.84 0.28 84.84 0.28 86.52 ; - LAYER li1 ; - POLYGON 91.83 97.75 91.83 86.87 117.59 86.87 117.59 0.17 0.17 0.17 0.17 86.87 25.93 86.87 25.93 97.75 ; - LAYER mcon ; - RECT 91.685 97.835 91.855 98.005 ; - RECT 91.225 97.835 91.395 98.005 ; - RECT 90.765 97.835 90.935 98.005 ; - RECT 90.305 97.835 90.475 98.005 ; - RECT 89.845 97.835 90.015 98.005 ; - RECT 89.385 97.835 89.555 98.005 ; - RECT 88.925 97.835 89.095 98.005 ; - RECT 88.465 97.835 88.635 98.005 ; - RECT 88.005 97.835 88.175 98.005 ; - RECT 87.545 97.835 87.715 98.005 ; - RECT 87.085 97.835 87.255 98.005 ; - RECT 86.625 97.835 86.795 98.005 ; - RECT 86.165 97.835 86.335 98.005 ; - RECT 85.705 97.835 85.875 98.005 ; - RECT 85.245 97.835 85.415 98.005 ; - RECT 84.785 97.835 84.955 98.005 ; - RECT 84.325 97.835 84.495 98.005 ; - RECT 83.865 97.835 84.035 98.005 ; - RECT 83.405 97.835 83.575 98.005 ; - RECT 82.945 97.835 83.115 98.005 ; - RECT 82.485 97.835 82.655 98.005 ; - RECT 82.025 97.835 82.195 98.005 ; - RECT 81.565 97.835 81.735 98.005 ; - RECT 81.105 97.835 81.275 98.005 ; - RECT 80.645 97.835 80.815 98.005 ; - RECT 80.185 97.835 80.355 98.005 ; - RECT 79.725 97.835 79.895 98.005 ; - RECT 79.265 97.835 79.435 98.005 ; - RECT 78.805 97.835 78.975 98.005 ; - RECT 78.345 97.835 78.515 98.005 ; - RECT 77.885 97.835 78.055 98.005 ; - RECT 77.425 97.835 77.595 98.005 ; - RECT 76.965 97.835 77.135 98.005 ; - RECT 76.505 97.835 76.675 98.005 ; - RECT 76.045 97.835 76.215 98.005 ; - RECT 75.585 97.835 75.755 98.005 ; - RECT 75.125 97.835 75.295 98.005 ; - RECT 74.665 97.835 74.835 98.005 ; - RECT 74.205 97.835 74.375 98.005 ; - RECT 73.745 97.835 73.915 98.005 ; - RECT 73.285 97.835 73.455 98.005 ; - RECT 72.825 97.835 72.995 98.005 ; - RECT 72.365 97.835 72.535 98.005 ; - RECT 71.905 97.835 72.075 98.005 ; - RECT 71.445 97.835 71.615 98.005 ; - RECT 70.985 97.835 71.155 98.005 ; - RECT 70.525 97.835 70.695 98.005 ; - RECT 70.065 97.835 70.235 98.005 ; - RECT 69.605 97.835 69.775 98.005 ; - RECT 69.145 97.835 69.315 98.005 ; - RECT 68.685 97.835 68.855 98.005 ; - RECT 68.225 97.835 68.395 98.005 ; - RECT 67.765 97.835 67.935 98.005 ; - RECT 67.305 97.835 67.475 98.005 ; - RECT 66.845 97.835 67.015 98.005 ; - RECT 66.385 97.835 66.555 98.005 ; - RECT 65.925 97.835 66.095 98.005 ; - RECT 65.465 97.835 65.635 98.005 ; - RECT 65.005 97.835 65.175 98.005 ; - RECT 64.545 97.835 64.715 98.005 ; - RECT 64.085 97.835 64.255 98.005 ; - RECT 63.625 97.835 63.795 98.005 ; - RECT 63.165 97.835 63.335 98.005 ; - RECT 62.705 97.835 62.875 98.005 ; - RECT 62.245 97.835 62.415 98.005 ; - RECT 61.785 97.835 61.955 98.005 ; - RECT 61.325 97.835 61.495 98.005 ; - RECT 60.865 97.835 61.035 98.005 ; - RECT 60.405 97.835 60.575 98.005 ; - RECT 59.945 97.835 60.115 98.005 ; - RECT 59.485 97.835 59.655 98.005 ; - RECT 59.025 97.835 59.195 98.005 ; - RECT 58.565 97.835 58.735 98.005 ; - RECT 58.105 97.835 58.275 98.005 ; - RECT 57.645 97.835 57.815 98.005 ; - RECT 57.185 97.835 57.355 98.005 ; - RECT 56.725 97.835 56.895 98.005 ; - RECT 56.265 97.835 56.435 98.005 ; - RECT 55.805 97.835 55.975 98.005 ; - RECT 55.345 97.835 55.515 98.005 ; - RECT 54.885 97.835 55.055 98.005 ; - RECT 54.425 97.835 54.595 98.005 ; - RECT 53.965 97.835 54.135 98.005 ; - RECT 53.505 97.835 53.675 98.005 ; - RECT 53.045 97.835 53.215 98.005 ; - RECT 52.585 97.835 52.755 98.005 ; - RECT 52.125 97.835 52.295 98.005 ; - RECT 51.665 97.835 51.835 98.005 ; - RECT 51.205 97.835 51.375 98.005 ; - RECT 50.745 97.835 50.915 98.005 ; - RECT 50.285 97.835 50.455 98.005 ; - RECT 49.825 97.835 49.995 98.005 ; - RECT 49.365 97.835 49.535 98.005 ; - RECT 48.905 97.835 49.075 98.005 ; - RECT 48.445 97.835 48.615 98.005 ; - RECT 47.985 97.835 48.155 98.005 ; - RECT 47.525 97.835 47.695 98.005 ; - RECT 47.065 97.835 47.235 98.005 ; - RECT 46.605 97.835 46.775 98.005 ; - RECT 46.145 97.835 46.315 98.005 ; - RECT 45.685 97.835 45.855 98.005 ; - RECT 45.225 97.835 45.395 98.005 ; - RECT 44.765 97.835 44.935 98.005 ; - RECT 44.305 97.835 44.475 98.005 ; - RECT 43.845 97.835 44.015 98.005 ; - RECT 43.385 97.835 43.555 98.005 ; - RECT 42.925 97.835 43.095 98.005 ; - RECT 42.465 97.835 42.635 98.005 ; - RECT 42.005 97.835 42.175 98.005 ; - RECT 41.545 97.835 41.715 98.005 ; - RECT 41.085 97.835 41.255 98.005 ; - RECT 40.625 97.835 40.795 98.005 ; - RECT 40.165 97.835 40.335 98.005 ; - RECT 39.705 97.835 39.875 98.005 ; - RECT 39.245 97.835 39.415 98.005 ; - RECT 38.785 97.835 38.955 98.005 ; - RECT 38.325 97.835 38.495 98.005 ; - RECT 37.865 97.835 38.035 98.005 ; - RECT 37.405 97.835 37.575 98.005 ; - RECT 36.945 97.835 37.115 98.005 ; - RECT 36.485 97.835 36.655 98.005 ; - RECT 36.025 97.835 36.195 98.005 ; - RECT 35.565 97.835 35.735 98.005 ; - RECT 35.105 97.835 35.275 98.005 ; - RECT 34.645 97.835 34.815 98.005 ; - RECT 34.185 97.835 34.355 98.005 ; - RECT 33.725 97.835 33.895 98.005 ; - RECT 33.265 97.835 33.435 98.005 ; - RECT 32.805 97.835 32.975 98.005 ; - RECT 32.345 97.835 32.515 98.005 ; - RECT 31.885 97.835 32.055 98.005 ; - RECT 31.425 97.835 31.595 98.005 ; - RECT 30.965 97.835 31.135 98.005 ; - RECT 30.505 97.835 30.675 98.005 ; - RECT 30.045 97.835 30.215 98.005 ; - RECT 29.585 97.835 29.755 98.005 ; - RECT 29.125 97.835 29.295 98.005 ; - RECT 28.665 97.835 28.835 98.005 ; - RECT 28.205 97.835 28.375 98.005 ; - RECT 27.745 97.835 27.915 98.005 ; - RECT 27.285 97.835 27.455 98.005 ; - RECT 26.825 97.835 26.995 98.005 ; - RECT 26.365 97.835 26.535 98.005 ; - RECT 25.905 97.835 26.075 98.005 ; - RECT 91.685 95.115 91.855 95.285 ; - RECT 91.225 95.115 91.395 95.285 ; - RECT 26.365 95.115 26.535 95.285 ; - RECT 25.905 95.115 26.075 95.285 ; - RECT 91.685 92.395 91.855 92.565 ; - RECT 91.225 92.395 91.395 92.565 ; - RECT 26.365 92.395 26.535 92.565 ; - RECT 25.905 92.395 26.075 92.565 ; - RECT 91.685 89.675 91.855 89.845 ; - RECT 91.225 89.675 91.395 89.845 ; - RECT 26.365 89.675 26.535 89.845 ; - RECT 25.905 89.675 26.075 89.845 ; - RECT 117.445 86.955 117.615 87.125 ; - RECT 116.985 86.955 117.155 87.125 ; - RECT 116.525 86.955 116.695 87.125 ; - RECT 116.065 86.955 116.235 87.125 ; - RECT 115.605 86.955 115.775 87.125 ; - RECT 115.145 86.955 115.315 87.125 ; - RECT 114.685 86.955 114.855 87.125 ; - RECT 114.225 86.955 114.395 87.125 ; - RECT 113.765 86.955 113.935 87.125 ; - RECT 113.305 86.955 113.475 87.125 ; - RECT 112.845 86.955 113.015 87.125 ; - RECT 112.385 86.955 112.555 87.125 ; - RECT 111.925 86.955 112.095 87.125 ; - RECT 111.465 86.955 111.635 87.125 ; - RECT 111.005 86.955 111.175 87.125 ; - RECT 110.545 86.955 110.715 87.125 ; - RECT 110.085 86.955 110.255 87.125 ; - RECT 109.625 86.955 109.795 87.125 ; - RECT 109.165 86.955 109.335 87.125 ; - RECT 108.705 86.955 108.875 87.125 ; - RECT 108.245 86.955 108.415 87.125 ; - RECT 107.785 86.955 107.955 87.125 ; - RECT 107.325 86.955 107.495 87.125 ; - RECT 106.865 86.955 107.035 87.125 ; - RECT 106.405 86.955 106.575 87.125 ; - RECT 105.945 86.955 106.115 87.125 ; - RECT 105.485 86.955 105.655 87.125 ; - RECT 105.025 86.955 105.195 87.125 ; - RECT 104.565 86.955 104.735 87.125 ; - RECT 104.105 86.955 104.275 87.125 ; - RECT 103.645 86.955 103.815 87.125 ; - RECT 103.185 86.955 103.355 87.125 ; - RECT 102.725 86.955 102.895 87.125 ; - RECT 102.265 86.955 102.435 87.125 ; - RECT 101.805 86.955 101.975 87.125 ; - RECT 101.345 86.955 101.515 87.125 ; - RECT 100.885 86.955 101.055 87.125 ; - RECT 100.425 86.955 100.595 87.125 ; - RECT 99.965 86.955 100.135 87.125 ; - RECT 99.505 86.955 99.675 87.125 ; - RECT 99.045 86.955 99.215 87.125 ; - RECT 98.585 86.955 98.755 87.125 ; - RECT 98.125 86.955 98.295 87.125 ; - RECT 97.665 86.955 97.835 87.125 ; - RECT 97.205 86.955 97.375 87.125 ; - RECT 96.745 86.955 96.915 87.125 ; - RECT 96.285 86.955 96.455 87.125 ; - RECT 95.825 86.955 95.995 87.125 ; - RECT 95.365 86.955 95.535 87.125 ; - RECT 94.905 86.955 95.075 87.125 ; - RECT 94.445 86.955 94.615 87.125 ; - RECT 93.985 86.955 94.155 87.125 ; - RECT 93.525 86.955 93.695 87.125 ; - RECT 93.065 86.955 93.235 87.125 ; - RECT 92.605 86.955 92.775 87.125 ; - RECT 92.145 86.955 92.315 87.125 ; - RECT 91.685 86.955 91.855 87.125 ; - RECT 91.225 86.955 91.395 87.125 ; - RECT 90.765 86.955 90.935 87.125 ; - RECT 90.305 86.955 90.475 87.125 ; - RECT 89.845 86.955 90.015 87.125 ; - RECT 89.385 86.955 89.555 87.125 ; - RECT 88.925 86.955 89.095 87.125 ; - RECT 88.465 86.955 88.635 87.125 ; - RECT 88.005 86.955 88.175 87.125 ; - RECT 87.545 86.955 87.715 87.125 ; - RECT 87.085 86.955 87.255 87.125 ; - RECT 86.625 86.955 86.795 87.125 ; - RECT 86.165 86.955 86.335 87.125 ; - RECT 85.705 86.955 85.875 87.125 ; - RECT 85.245 86.955 85.415 87.125 ; - RECT 84.785 86.955 84.955 87.125 ; - RECT 84.325 86.955 84.495 87.125 ; - RECT 83.865 86.955 84.035 87.125 ; - RECT 83.405 86.955 83.575 87.125 ; - RECT 82.945 86.955 83.115 87.125 ; - RECT 82.485 86.955 82.655 87.125 ; - RECT 82.025 86.955 82.195 87.125 ; - RECT 81.565 86.955 81.735 87.125 ; - RECT 81.105 86.955 81.275 87.125 ; - RECT 80.645 86.955 80.815 87.125 ; - RECT 80.185 86.955 80.355 87.125 ; - RECT 79.725 86.955 79.895 87.125 ; - RECT 79.265 86.955 79.435 87.125 ; - RECT 78.805 86.955 78.975 87.125 ; - RECT 78.345 86.955 78.515 87.125 ; - RECT 77.885 86.955 78.055 87.125 ; - RECT 77.425 86.955 77.595 87.125 ; - RECT 76.965 86.955 77.135 87.125 ; - RECT 76.505 86.955 76.675 87.125 ; - RECT 76.045 86.955 76.215 87.125 ; - RECT 75.585 86.955 75.755 87.125 ; - RECT 75.125 86.955 75.295 87.125 ; - RECT 74.665 86.955 74.835 87.125 ; - RECT 74.205 86.955 74.375 87.125 ; - RECT 73.745 86.955 73.915 87.125 ; - RECT 73.285 86.955 73.455 87.125 ; - RECT 72.825 86.955 72.995 87.125 ; - RECT 72.365 86.955 72.535 87.125 ; - RECT 71.905 86.955 72.075 87.125 ; - RECT 71.445 86.955 71.615 87.125 ; - RECT 70.985 86.955 71.155 87.125 ; - RECT 70.525 86.955 70.695 87.125 ; - RECT 70.065 86.955 70.235 87.125 ; - RECT 69.605 86.955 69.775 87.125 ; - RECT 69.145 86.955 69.315 87.125 ; - RECT 68.685 86.955 68.855 87.125 ; - RECT 68.225 86.955 68.395 87.125 ; - RECT 67.765 86.955 67.935 87.125 ; - RECT 67.305 86.955 67.475 87.125 ; - RECT 66.845 86.955 67.015 87.125 ; - RECT 66.385 86.955 66.555 87.125 ; - RECT 65.925 86.955 66.095 87.125 ; - RECT 65.465 86.955 65.635 87.125 ; - RECT 65.005 86.955 65.175 87.125 ; - RECT 64.545 86.955 64.715 87.125 ; - RECT 64.085 86.955 64.255 87.125 ; - RECT 63.625 86.955 63.795 87.125 ; - RECT 63.165 86.955 63.335 87.125 ; - RECT 62.705 86.955 62.875 87.125 ; - RECT 62.245 86.955 62.415 87.125 ; - RECT 61.785 86.955 61.955 87.125 ; - RECT 61.325 86.955 61.495 87.125 ; - RECT 60.865 86.955 61.035 87.125 ; - RECT 60.405 86.955 60.575 87.125 ; - RECT 59.945 86.955 60.115 87.125 ; - RECT 59.485 86.955 59.655 87.125 ; - RECT 59.025 86.955 59.195 87.125 ; - RECT 58.565 86.955 58.735 87.125 ; - RECT 58.105 86.955 58.275 87.125 ; - RECT 57.645 86.955 57.815 87.125 ; - RECT 57.185 86.955 57.355 87.125 ; - RECT 56.725 86.955 56.895 87.125 ; - RECT 56.265 86.955 56.435 87.125 ; - RECT 55.805 86.955 55.975 87.125 ; - RECT 55.345 86.955 55.515 87.125 ; - RECT 54.885 86.955 55.055 87.125 ; - RECT 54.425 86.955 54.595 87.125 ; - RECT 53.965 86.955 54.135 87.125 ; - RECT 53.505 86.955 53.675 87.125 ; - RECT 53.045 86.955 53.215 87.125 ; - RECT 52.585 86.955 52.755 87.125 ; - RECT 52.125 86.955 52.295 87.125 ; - RECT 51.665 86.955 51.835 87.125 ; - RECT 51.205 86.955 51.375 87.125 ; - RECT 50.745 86.955 50.915 87.125 ; - RECT 50.285 86.955 50.455 87.125 ; - RECT 49.825 86.955 49.995 87.125 ; - RECT 49.365 86.955 49.535 87.125 ; - RECT 48.905 86.955 49.075 87.125 ; - RECT 48.445 86.955 48.615 87.125 ; - RECT 47.985 86.955 48.155 87.125 ; - RECT 47.525 86.955 47.695 87.125 ; - RECT 47.065 86.955 47.235 87.125 ; - RECT 46.605 86.955 46.775 87.125 ; - RECT 46.145 86.955 46.315 87.125 ; - RECT 45.685 86.955 45.855 87.125 ; - RECT 45.225 86.955 45.395 87.125 ; - RECT 44.765 86.955 44.935 87.125 ; - RECT 44.305 86.955 44.475 87.125 ; - RECT 43.845 86.955 44.015 87.125 ; - RECT 43.385 86.955 43.555 87.125 ; - RECT 42.925 86.955 43.095 87.125 ; - RECT 42.465 86.955 42.635 87.125 ; - RECT 42.005 86.955 42.175 87.125 ; - RECT 41.545 86.955 41.715 87.125 ; - RECT 41.085 86.955 41.255 87.125 ; - RECT 40.625 86.955 40.795 87.125 ; - RECT 40.165 86.955 40.335 87.125 ; - RECT 39.705 86.955 39.875 87.125 ; - RECT 39.245 86.955 39.415 87.125 ; - RECT 38.785 86.955 38.955 87.125 ; - RECT 38.325 86.955 38.495 87.125 ; - RECT 37.865 86.955 38.035 87.125 ; - RECT 37.405 86.955 37.575 87.125 ; - RECT 36.945 86.955 37.115 87.125 ; - RECT 36.485 86.955 36.655 87.125 ; - RECT 36.025 86.955 36.195 87.125 ; - RECT 35.565 86.955 35.735 87.125 ; - RECT 35.105 86.955 35.275 87.125 ; - RECT 34.645 86.955 34.815 87.125 ; - RECT 34.185 86.955 34.355 87.125 ; - RECT 33.725 86.955 33.895 87.125 ; - RECT 33.265 86.955 33.435 87.125 ; - RECT 32.805 86.955 32.975 87.125 ; - RECT 32.345 86.955 32.515 87.125 ; - RECT 31.885 86.955 32.055 87.125 ; - RECT 31.425 86.955 31.595 87.125 ; - RECT 30.965 86.955 31.135 87.125 ; - RECT 30.505 86.955 30.675 87.125 ; - RECT 30.045 86.955 30.215 87.125 ; - RECT 29.585 86.955 29.755 87.125 ; - RECT 29.125 86.955 29.295 87.125 ; - RECT 28.665 86.955 28.835 87.125 ; - RECT 28.205 86.955 28.375 87.125 ; - RECT 27.745 86.955 27.915 87.125 ; - RECT 27.285 86.955 27.455 87.125 ; - RECT 26.825 86.955 26.995 87.125 ; - RECT 26.365 86.955 26.535 87.125 ; - RECT 25.905 86.955 26.075 87.125 ; - RECT 25.445 86.955 25.615 87.125 ; - RECT 24.985 86.955 25.155 87.125 ; - RECT 24.525 86.955 24.695 87.125 ; - RECT 24.065 86.955 24.235 87.125 ; - RECT 23.605 86.955 23.775 87.125 ; - RECT 23.145 86.955 23.315 87.125 ; - RECT 22.685 86.955 22.855 87.125 ; - RECT 22.225 86.955 22.395 87.125 ; - RECT 21.765 86.955 21.935 87.125 ; - RECT 21.305 86.955 21.475 87.125 ; - RECT 20.845 86.955 21.015 87.125 ; - RECT 20.385 86.955 20.555 87.125 ; - RECT 19.925 86.955 20.095 87.125 ; - RECT 19.465 86.955 19.635 87.125 ; - RECT 19.005 86.955 19.175 87.125 ; - RECT 18.545 86.955 18.715 87.125 ; - RECT 18.085 86.955 18.255 87.125 ; - RECT 17.625 86.955 17.795 87.125 ; - RECT 17.165 86.955 17.335 87.125 ; - RECT 16.705 86.955 16.875 87.125 ; - RECT 16.245 86.955 16.415 87.125 ; - RECT 15.785 86.955 15.955 87.125 ; - RECT 15.325 86.955 15.495 87.125 ; - RECT 14.865 86.955 15.035 87.125 ; - RECT 14.405 86.955 14.575 87.125 ; - RECT 13.945 86.955 14.115 87.125 ; - RECT 13.485 86.955 13.655 87.125 ; - RECT 13.025 86.955 13.195 87.125 ; - RECT 12.565 86.955 12.735 87.125 ; - RECT 12.105 86.955 12.275 87.125 ; - RECT 11.645 86.955 11.815 87.125 ; - RECT 11.185 86.955 11.355 87.125 ; - RECT 10.725 86.955 10.895 87.125 ; - RECT 10.265 86.955 10.435 87.125 ; - RECT 9.805 86.955 9.975 87.125 ; - RECT 9.345 86.955 9.515 87.125 ; - RECT 8.885 86.955 9.055 87.125 ; - RECT 8.425 86.955 8.595 87.125 ; - RECT 7.965 86.955 8.135 87.125 ; - RECT 7.505 86.955 7.675 87.125 ; - RECT 7.045 86.955 7.215 87.125 ; - RECT 6.585 86.955 6.755 87.125 ; - RECT 6.125 86.955 6.295 87.125 ; - RECT 5.665 86.955 5.835 87.125 ; - RECT 5.205 86.955 5.375 87.125 ; - RECT 4.745 86.955 4.915 87.125 ; - RECT 4.285 86.955 4.455 87.125 ; - RECT 3.825 86.955 3.995 87.125 ; - RECT 3.365 86.955 3.535 87.125 ; - RECT 2.905 86.955 3.075 87.125 ; - RECT 2.445 86.955 2.615 87.125 ; - RECT 1.985 86.955 2.155 87.125 ; - RECT 1.525 86.955 1.695 87.125 ; - RECT 1.065 86.955 1.235 87.125 ; - RECT 0.605 86.955 0.775 87.125 ; - RECT 0.145 86.955 0.315 87.125 ; - RECT 117.445 84.235 117.615 84.405 ; - RECT 116.985 84.235 117.155 84.405 ; - RECT 0.605 84.235 0.775 84.405 ; - RECT 0.145 84.235 0.315 84.405 ; - RECT 117.445 81.515 117.615 81.685 ; - RECT 116.985 81.515 117.155 81.685 ; - RECT 0.605 81.515 0.775 81.685 ; - RECT 0.145 81.515 0.315 81.685 ; - RECT 117.445 78.795 117.615 78.965 ; - RECT 116.985 78.795 117.155 78.965 ; - RECT 0.605 78.795 0.775 78.965 ; - RECT 0.145 78.795 0.315 78.965 ; - RECT 117.445 76.075 117.615 76.245 ; - RECT 116.985 76.075 117.155 76.245 ; - RECT 0.605 76.075 0.775 76.245 ; - RECT 0.145 76.075 0.315 76.245 ; - RECT 117.445 73.355 117.615 73.525 ; - RECT 116.985 73.355 117.155 73.525 ; - RECT 0.605 73.355 0.775 73.525 ; - RECT 0.145 73.355 0.315 73.525 ; - RECT 117.445 70.635 117.615 70.805 ; - RECT 116.985 70.635 117.155 70.805 ; - RECT 0.605 70.635 0.775 70.805 ; - RECT 0.145 70.635 0.315 70.805 ; - RECT 117.445 67.915 117.615 68.085 ; - RECT 116.985 67.915 117.155 68.085 ; - RECT 0.605 67.915 0.775 68.085 ; - RECT 0.145 67.915 0.315 68.085 ; - RECT 117.445 65.195 117.615 65.365 ; - RECT 116.985 65.195 117.155 65.365 ; - RECT 0.605 65.195 0.775 65.365 ; - RECT 0.145 65.195 0.315 65.365 ; - RECT 117.445 62.475 117.615 62.645 ; - RECT 116.985 62.475 117.155 62.645 ; - RECT 0.605 62.475 0.775 62.645 ; - RECT 0.145 62.475 0.315 62.645 ; - RECT 117.445 59.755 117.615 59.925 ; - RECT 116.985 59.755 117.155 59.925 ; - RECT 0.605 59.755 0.775 59.925 ; - RECT 0.145 59.755 0.315 59.925 ; - RECT 117.445 57.035 117.615 57.205 ; - RECT 116.985 57.035 117.155 57.205 ; - RECT 0.605 57.035 0.775 57.205 ; - RECT 0.145 57.035 0.315 57.205 ; - RECT 117.445 54.315 117.615 54.485 ; - RECT 116.985 54.315 117.155 54.485 ; - RECT 0.605 54.315 0.775 54.485 ; - RECT 0.145 54.315 0.315 54.485 ; - RECT 117.445 51.595 117.615 51.765 ; - RECT 116.985 51.595 117.155 51.765 ; - RECT 0.605 51.595 0.775 51.765 ; - RECT 0.145 51.595 0.315 51.765 ; - RECT 117.445 48.875 117.615 49.045 ; - RECT 116.985 48.875 117.155 49.045 ; - RECT 0.605 48.875 0.775 49.045 ; - RECT 0.145 48.875 0.315 49.045 ; - RECT 117.445 46.155 117.615 46.325 ; - RECT 116.985 46.155 117.155 46.325 ; - RECT 0.605 46.155 0.775 46.325 ; - RECT 0.145 46.155 0.315 46.325 ; - RECT 117.445 43.435 117.615 43.605 ; - RECT 116.985 43.435 117.155 43.605 ; - RECT 0.605 43.435 0.775 43.605 ; - RECT 0.145 43.435 0.315 43.605 ; - RECT 117.445 40.715 117.615 40.885 ; - RECT 116.985 40.715 117.155 40.885 ; - RECT 0.605 40.715 0.775 40.885 ; - RECT 0.145 40.715 0.315 40.885 ; - RECT 117.445 37.995 117.615 38.165 ; - RECT 116.985 37.995 117.155 38.165 ; - RECT 0.605 37.995 0.775 38.165 ; - RECT 0.145 37.995 0.315 38.165 ; - RECT 117.445 35.275 117.615 35.445 ; - RECT 116.985 35.275 117.155 35.445 ; - RECT 0.605 35.275 0.775 35.445 ; - RECT 0.145 35.275 0.315 35.445 ; - RECT 117.445 32.555 117.615 32.725 ; - RECT 116.985 32.555 117.155 32.725 ; - RECT 0.605 32.555 0.775 32.725 ; - RECT 0.145 32.555 0.315 32.725 ; - RECT 117.445 29.835 117.615 30.005 ; - RECT 116.985 29.835 117.155 30.005 ; - RECT 0.605 29.835 0.775 30.005 ; - RECT 0.145 29.835 0.315 30.005 ; - RECT 117.445 27.115 117.615 27.285 ; - RECT 116.985 27.115 117.155 27.285 ; - RECT 0.605 27.115 0.775 27.285 ; - RECT 0.145 27.115 0.315 27.285 ; - RECT 117.445 24.395 117.615 24.565 ; - RECT 116.985 24.395 117.155 24.565 ; - RECT 0.605 24.395 0.775 24.565 ; - RECT 0.145 24.395 0.315 24.565 ; - RECT 117.445 21.675 117.615 21.845 ; - RECT 116.985 21.675 117.155 21.845 ; - RECT 0.605 21.675 0.775 21.845 ; - RECT 0.145 21.675 0.315 21.845 ; - RECT 117.445 18.955 117.615 19.125 ; - RECT 116.985 18.955 117.155 19.125 ; - RECT 0.605 18.955 0.775 19.125 ; - RECT 0.145 18.955 0.315 19.125 ; - RECT 117.445 16.235 117.615 16.405 ; - RECT 116.985 16.235 117.155 16.405 ; - RECT 0.605 16.235 0.775 16.405 ; - RECT 0.145 16.235 0.315 16.405 ; - RECT 117.445 13.515 117.615 13.685 ; - RECT 116.985 13.515 117.155 13.685 ; - RECT 0.605 13.515 0.775 13.685 ; - RECT 0.145 13.515 0.315 13.685 ; - RECT 117.445 10.795 117.615 10.965 ; - RECT 116.985 10.795 117.155 10.965 ; - RECT 0.605 10.795 0.775 10.965 ; - RECT 0.145 10.795 0.315 10.965 ; - RECT 117.445 8.075 117.615 8.245 ; - RECT 116.985 8.075 117.155 8.245 ; - RECT 0.605 8.075 0.775 8.245 ; - RECT 0.145 8.075 0.315 8.245 ; - RECT 117.445 5.355 117.615 5.525 ; - RECT 116.985 5.355 117.155 5.525 ; - RECT 0.605 5.355 0.775 5.525 ; - RECT 0.145 5.355 0.315 5.525 ; - RECT 117.445 2.635 117.615 2.805 ; - RECT 116.985 2.635 117.155 2.805 ; - RECT 0.605 2.635 0.775 2.805 ; - RECT 0.145 2.635 0.315 2.805 ; - RECT 117.445 -0.085 117.615 0.085 ; - RECT 116.985 -0.085 117.155 0.085 ; - RECT 116.525 -0.085 116.695 0.085 ; - RECT 116.065 -0.085 116.235 0.085 ; - RECT 115.605 -0.085 115.775 0.085 ; - RECT 115.145 -0.085 115.315 0.085 ; - RECT 114.685 -0.085 114.855 0.085 ; - RECT 114.225 -0.085 114.395 0.085 ; - RECT 113.765 -0.085 113.935 0.085 ; - RECT 113.305 -0.085 113.475 0.085 ; - RECT 112.845 -0.085 113.015 0.085 ; - RECT 112.385 -0.085 112.555 0.085 ; - RECT 111.925 -0.085 112.095 0.085 ; - RECT 111.465 -0.085 111.635 0.085 ; - RECT 111.005 -0.085 111.175 0.085 ; - RECT 110.545 -0.085 110.715 0.085 ; - RECT 110.085 -0.085 110.255 0.085 ; - RECT 109.625 -0.085 109.795 0.085 ; - RECT 109.165 -0.085 109.335 0.085 ; - RECT 108.705 -0.085 108.875 0.085 ; - RECT 108.245 -0.085 108.415 0.085 ; - RECT 107.785 -0.085 107.955 0.085 ; - RECT 107.325 -0.085 107.495 0.085 ; - RECT 106.865 -0.085 107.035 0.085 ; - RECT 106.405 -0.085 106.575 0.085 ; - RECT 105.945 -0.085 106.115 0.085 ; - RECT 105.485 -0.085 105.655 0.085 ; - RECT 105.025 -0.085 105.195 0.085 ; - RECT 104.565 -0.085 104.735 0.085 ; - RECT 104.105 -0.085 104.275 0.085 ; - RECT 103.645 -0.085 103.815 0.085 ; - RECT 103.185 -0.085 103.355 0.085 ; - RECT 102.725 -0.085 102.895 0.085 ; - RECT 102.265 -0.085 102.435 0.085 ; - RECT 101.805 -0.085 101.975 0.085 ; - RECT 101.345 -0.085 101.515 0.085 ; - RECT 100.885 -0.085 101.055 0.085 ; - RECT 100.425 -0.085 100.595 0.085 ; - RECT 99.965 -0.085 100.135 0.085 ; - RECT 99.505 -0.085 99.675 0.085 ; - RECT 99.045 -0.085 99.215 0.085 ; - RECT 98.585 -0.085 98.755 0.085 ; - RECT 98.125 -0.085 98.295 0.085 ; - RECT 97.665 -0.085 97.835 0.085 ; - RECT 97.205 -0.085 97.375 0.085 ; - RECT 96.745 -0.085 96.915 0.085 ; - RECT 96.285 -0.085 96.455 0.085 ; - RECT 95.825 -0.085 95.995 0.085 ; - RECT 95.365 -0.085 95.535 0.085 ; - RECT 94.905 -0.085 95.075 0.085 ; - RECT 94.445 -0.085 94.615 0.085 ; - RECT 93.985 -0.085 94.155 0.085 ; - RECT 93.525 -0.085 93.695 0.085 ; - RECT 93.065 -0.085 93.235 0.085 ; - RECT 92.605 -0.085 92.775 0.085 ; - RECT 92.145 -0.085 92.315 0.085 ; - RECT 91.685 -0.085 91.855 0.085 ; - RECT 91.225 -0.085 91.395 0.085 ; - RECT 90.765 -0.085 90.935 0.085 ; - RECT 90.305 -0.085 90.475 0.085 ; - RECT 89.845 -0.085 90.015 0.085 ; - RECT 89.385 -0.085 89.555 0.085 ; - RECT 88.925 -0.085 89.095 0.085 ; - RECT 88.465 -0.085 88.635 0.085 ; - RECT 88.005 -0.085 88.175 0.085 ; - RECT 87.545 -0.085 87.715 0.085 ; - RECT 87.085 -0.085 87.255 0.085 ; - RECT 86.625 -0.085 86.795 0.085 ; - RECT 86.165 -0.085 86.335 0.085 ; - RECT 85.705 -0.085 85.875 0.085 ; - RECT 85.245 -0.085 85.415 0.085 ; - RECT 84.785 -0.085 84.955 0.085 ; - RECT 84.325 -0.085 84.495 0.085 ; - RECT 83.865 -0.085 84.035 0.085 ; - RECT 83.405 -0.085 83.575 0.085 ; - RECT 82.945 -0.085 83.115 0.085 ; - RECT 82.485 -0.085 82.655 0.085 ; - RECT 82.025 -0.085 82.195 0.085 ; - RECT 81.565 -0.085 81.735 0.085 ; - RECT 81.105 -0.085 81.275 0.085 ; - RECT 80.645 -0.085 80.815 0.085 ; - RECT 80.185 -0.085 80.355 0.085 ; - RECT 79.725 -0.085 79.895 0.085 ; - RECT 79.265 -0.085 79.435 0.085 ; - RECT 78.805 -0.085 78.975 0.085 ; - RECT 78.345 -0.085 78.515 0.085 ; - RECT 77.885 -0.085 78.055 0.085 ; - RECT 77.425 -0.085 77.595 0.085 ; - RECT 76.965 -0.085 77.135 0.085 ; - RECT 76.505 -0.085 76.675 0.085 ; - RECT 76.045 -0.085 76.215 0.085 ; - RECT 75.585 -0.085 75.755 0.085 ; - RECT 75.125 -0.085 75.295 0.085 ; - RECT 74.665 -0.085 74.835 0.085 ; - RECT 74.205 -0.085 74.375 0.085 ; - RECT 73.745 -0.085 73.915 0.085 ; - RECT 73.285 -0.085 73.455 0.085 ; - RECT 72.825 -0.085 72.995 0.085 ; - RECT 72.365 -0.085 72.535 0.085 ; - RECT 71.905 -0.085 72.075 0.085 ; - RECT 71.445 -0.085 71.615 0.085 ; - RECT 70.985 -0.085 71.155 0.085 ; - RECT 70.525 -0.085 70.695 0.085 ; - RECT 70.065 -0.085 70.235 0.085 ; - RECT 69.605 -0.085 69.775 0.085 ; - RECT 69.145 -0.085 69.315 0.085 ; - RECT 68.685 -0.085 68.855 0.085 ; - RECT 68.225 -0.085 68.395 0.085 ; - RECT 67.765 -0.085 67.935 0.085 ; - RECT 67.305 -0.085 67.475 0.085 ; - RECT 66.845 -0.085 67.015 0.085 ; - RECT 66.385 -0.085 66.555 0.085 ; - RECT 65.925 -0.085 66.095 0.085 ; - RECT 65.465 -0.085 65.635 0.085 ; - RECT 65.005 -0.085 65.175 0.085 ; - RECT 64.545 -0.085 64.715 0.085 ; - RECT 64.085 -0.085 64.255 0.085 ; - RECT 63.625 -0.085 63.795 0.085 ; - RECT 63.165 -0.085 63.335 0.085 ; - RECT 62.705 -0.085 62.875 0.085 ; - RECT 62.245 -0.085 62.415 0.085 ; - RECT 61.785 -0.085 61.955 0.085 ; - RECT 61.325 -0.085 61.495 0.085 ; - RECT 60.865 -0.085 61.035 0.085 ; - RECT 60.405 -0.085 60.575 0.085 ; - RECT 59.945 -0.085 60.115 0.085 ; - RECT 59.485 -0.085 59.655 0.085 ; - RECT 59.025 -0.085 59.195 0.085 ; - RECT 58.565 -0.085 58.735 0.085 ; - RECT 58.105 -0.085 58.275 0.085 ; - RECT 57.645 -0.085 57.815 0.085 ; - RECT 57.185 -0.085 57.355 0.085 ; - RECT 56.725 -0.085 56.895 0.085 ; - RECT 56.265 -0.085 56.435 0.085 ; - RECT 55.805 -0.085 55.975 0.085 ; - RECT 55.345 -0.085 55.515 0.085 ; - RECT 54.885 -0.085 55.055 0.085 ; - RECT 54.425 -0.085 54.595 0.085 ; - RECT 53.965 -0.085 54.135 0.085 ; - RECT 53.505 -0.085 53.675 0.085 ; - RECT 53.045 -0.085 53.215 0.085 ; - RECT 52.585 -0.085 52.755 0.085 ; - RECT 52.125 -0.085 52.295 0.085 ; - RECT 51.665 -0.085 51.835 0.085 ; - RECT 51.205 -0.085 51.375 0.085 ; - RECT 50.745 -0.085 50.915 0.085 ; - RECT 50.285 -0.085 50.455 0.085 ; - RECT 49.825 -0.085 49.995 0.085 ; - RECT 49.365 -0.085 49.535 0.085 ; - RECT 48.905 -0.085 49.075 0.085 ; - RECT 48.445 -0.085 48.615 0.085 ; - RECT 47.985 -0.085 48.155 0.085 ; - RECT 47.525 -0.085 47.695 0.085 ; - RECT 47.065 -0.085 47.235 0.085 ; - RECT 46.605 -0.085 46.775 0.085 ; - RECT 46.145 -0.085 46.315 0.085 ; - RECT 45.685 -0.085 45.855 0.085 ; - RECT 45.225 -0.085 45.395 0.085 ; - RECT 44.765 -0.085 44.935 0.085 ; - RECT 44.305 -0.085 44.475 0.085 ; - RECT 43.845 -0.085 44.015 0.085 ; - RECT 43.385 -0.085 43.555 0.085 ; - RECT 42.925 -0.085 43.095 0.085 ; - RECT 42.465 -0.085 42.635 0.085 ; - RECT 42.005 -0.085 42.175 0.085 ; - RECT 41.545 -0.085 41.715 0.085 ; - RECT 41.085 -0.085 41.255 0.085 ; - RECT 40.625 -0.085 40.795 0.085 ; - RECT 40.165 -0.085 40.335 0.085 ; - RECT 39.705 -0.085 39.875 0.085 ; - RECT 39.245 -0.085 39.415 0.085 ; - RECT 38.785 -0.085 38.955 0.085 ; - RECT 38.325 -0.085 38.495 0.085 ; - RECT 37.865 -0.085 38.035 0.085 ; - RECT 37.405 -0.085 37.575 0.085 ; - RECT 36.945 -0.085 37.115 0.085 ; - RECT 36.485 -0.085 36.655 0.085 ; - RECT 36.025 -0.085 36.195 0.085 ; - RECT 35.565 -0.085 35.735 0.085 ; - RECT 35.105 -0.085 35.275 0.085 ; - RECT 34.645 -0.085 34.815 0.085 ; - RECT 34.185 -0.085 34.355 0.085 ; - RECT 33.725 -0.085 33.895 0.085 ; - RECT 33.265 -0.085 33.435 0.085 ; - RECT 32.805 -0.085 32.975 0.085 ; - RECT 32.345 -0.085 32.515 0.085 ; - RECT 31.885 -0.085 32.055 0.085 ; - RECT 31.425 -0.085 31.595 0.085 ; - RECT 30.965 -0.085 31.135 0.085 ; - RECT 30.505 -0.085 30.675 0.085 ; - RECT 30.045 -0.085 30.215 0.085 ; - RECT 29.585 -0.085 29.755 0.085 ; - RECT 29.125 -0.085 29.295 0.085 ; - RECT 28.665 -0.085 28.835 0.085 ; - RECT 28.205 -0.085 28.375 0.085 ; - RECT 27.745 -0.085 27.915 0.085 ; - RECT 27.285 -0.085 27.455 0.085 ; - RECT 26.825 -0.085 26.995 0.085 ; - RECT 26.365 -0.085 26.535 0.085 ; - RECT 25.905 -0.085 26.075 0.085 ; - RECT 25.445 -0.085 25.615 0.085 ; - RECT 24.985 -0.085 25.155 0.085 ; - RECT 24.525 -0.085 24.695 0.085 ; - RECT 24.065 -0.085 24.235 0.085 ; - RECT 23.605 -0.085 23.775 0.085 ; - RECT 23.145 -0.085 23.315 0.085 ; - RECT 22.685 -0.085 22.855 0.085 ; - RECT 22.225 -0.085 22.395 0.085 ; - RECT 21.765 -0.085 21.935 0.085 ; - RECT 21.305 -0.085 21.475 0.085 ; - RECT 20.845 -0.085 21.015 0.085 ; - RECT 20.385 -0.085 20.555 0.085 ; - RECT 19.925 -0.085 20.095 0.085 ; - RECT 19.465 -0.085 19.635 0.085 ; - RECT 19.005 -0.085 19.175 0.085 ; - RECT 18.545 -0.085 18.715 0.085 ; - RECT 18.085 -0.085 18.255 0.085 ; - RECT 17.625 -0.085 17.795 0.085 ; - RECT 17.165 -0.085 17.335 0.085 ; - RECT 16.705 -0.085 16.875 0.085 ; - RECT 16.245 -0.085 16.415 0.085 ; - RECT 15.785 -0.085 15.955 0.085 ; - RECT 15.325 -0.085 15.495 0.085 ; - RECT 14.865 -0.085 15.035 0.085 ; - RECT 14.405 -0.085 14.575 0.085 ; - RECT 13.945 -0.085 14.115 0.085 ; - RECT 13.485 -0.085 13.655 0.085 ; - RECT 13.025 -0.085 13.195 0.085 ; - RECT 12.565 -0.085 12.735 0.085 ; - RECT 12.105 -0.085 12.275 0.085 ; - RECT 11.645 -0.085 11.815 0.085 ; - RECT 11.185 -0.085 11.355 0.085 ; - RECT 10.725 -0.085 10.895 0.085 ; - RECT 10.265 -0.085 10.435 0.085 ; - RECT 9.805 -0.085 9.975 0.085 ; - RECT 9.345 -0.085 9.515 0.085 ; - RECT 8.885 -0.085 9.055 0.085 ; - RECT 8.425 -0.085 8.595 0.085 ; - RECT 7.965 -0.085 8.135 0.085 ; - RECT 7.505 -0.085 7.675 0.085 ; - RECT 7.045 -0.085 7.215 0.085 ; - RECT 6.585 -0.085 6.755 0.085 ; - RECT 6.125 -0.085 6.295 0.085 ; - RECT 5.665 -0.085 5.835 0.085 ; - RECT 5.205 -0.085 5.375 0.085 ; - RECT 4.745 -0.085 4.915 0.085 ; - RECT 4.285 -0.085 4.455 0.085 ; - RECT 3.825 -0.085 3.995 0.085 ; - RECT 3.365 -0.085 3.535 0.085 ; - RECT 2.905 -0.085 3.075 0.085 ; - RECT 2.445 -0.085 2.615 0.085 ; - RECT 1.985 -0.085 2.155 0.085 ; - RECT 1.525 -0.085 1.695 0.085 ; - RECT 1.065 -0.085 1.235 0.085 ; - RECT 0.605 -0.085 0.775 0.085 ; - RECT 0.145 -0.085 0.315 0.085 ; - LAYER via ; - RECT 80.885 97.845 81.035 97.995 ; - RECT 51.445 97.845 51.595 97.995 ; - RECT 53.285 96.145 53.435 96.295 ; - RECT 47.305 96.145 47.455 96.295 ; - RECT 27.985 96.145 28.135 96.295 ; - RECT 80.885 86.965 81.035 87.115 ; - RECT 51.445 86.965 51.595 87.115 ; - RECT 10.965 86.965 11.115 87.115 ; - RECT 14.185 85.265 14.335 85.415 ; - RECT 80.885 -0.075 81.035 0.075 ; - RECT 51.445 -0.075 51.595 0.075 ; - RECT 10.965 -0.075 11.115 0.075 ; - LAYER via2 ; - RECT 80.86 97.82 81.06 98.02 ; - RECT 51.42 97.82 51.62 98.02 ; - RECT 10.94 86.94 11.14 87.14 ; - RECT 1.74 82.18 1.94 82.38 ; - RECT 1.28 65.18 1.48 65.38 ; - RECT 1.74 58.38 1.94 58.58 ; - RECT 1.28 52.26 1.48 52.46 ; - RECT 1.74 49.54 1.94 49.74 ; - RECT 116.28 48.86 116.48 49.06 ; - RECT 116.28 39.34 116.48 39.54 ; - RECT 116.28 29.82 116.48 30.02 ; - RECT 116.28 23.02 116.48 23.22 ; - RECT 1.28 19.62 1.48 19.82 ; - RECT 1.28 16.9 1.48 17.1 ; - RECT 1.28 15.54 1.48 15.74 ; - RECT 80.86 -0.1 81.06 0.1 ; - RECT 51.42 -0.1 51.62 0.1 ; - RECT 10.94 -0.1 11.14 0.1 ; - LAYER via3 ; - RECT 80.86 97.82 81.06 98.02 ; - RECT 51.42 97.82 51.62 98.02 ; - RECT 10.94 86.94 11.14 87.14 ; - RECT 80.86 -0.1 81.06 0.1 ; - RECT 51.42 -0.1 51.62 0.1 ; - RECT 10.94 -0.1 11.14 0.1 ; - LAYER OVERLAP ; - POLYGON 0 0 0 87.04 25.76 87.04 25.76 97.92 92 97.92 92 87.04 117.76 87.04 117.76 0 ; - END -END sb_1__0_ - -END LIBRARY diff --git a/FPGA22_HIER_SKY_PNR/modules/lef/sb_1__1__icv_in_design.lef b/FPGA22_HIER_SKY_PNR/modules/lef/sb_1__1__icv_in_design.lef deleted file mode 100644 index f33057f..0000000 --- a/FPGA22_HIER_SKY_PNR/modules/lef/sb_1__1__icv_in_design.lef +++ /dev/null @@ -1,3212 +0,0 @@ -VERSION 5.7 ; -BUSBITCHARS "[]" ; - -UNITS - DATABASE MICRONS 1000 ; -END UNITS - -MANUFACTURINGGRID 0.005 ; - -LAYER li1 - TYPE ROUTING ; - DIRECTION VERTICAL ; - PITCH 0.46 ; - WIDTH 0.17 ; -END li1 - -LAYER mcon - TYPE CUT ; -END mcon - -LAYER met1 - TYPE ROUTING ; - DIRECTION HORIZONTAL ; - PITCH 0.34 ; - WIDTH 0.14 ; -END met1 - -LAYER via - TYPE CUT ; -END via - -LAYER met2 - TYPE ROUTING ; - DIRECTION VERTICAL ; - PITCH 0.46 ; - WIDTH 0.14 ; -END met2 - -LAYER via2 - TYPE CUT ; -END via2 - -LAYER met3 - TYPE ROUTING ; - DIRECTION HORIZONTAL ; - PITCH 0.68 ; - WIDTH 0.3 ; -END met3 - -LAYER via3 - TYPE CUT ; -END via3 - -LAYER met4 - TYPE ROUTING ; - DIRECTION VERTICAL ; - PITCH 0.92 ; - WIDTH 0.3 ; -END met4 - -LAYER via4 - TYPE CUT ; -END via4 - -LAYER met5 - TYPE ROUTING ; - DIRECTION HORIZONTAL ; - PITCH 3.4 ; - WIDTH 1.6 ; -END met5 - -LAYER nwell - TYPE MASTERSLICE ; -END nwell - -LAYER pwell - TYPE MASTERSLICE ; -END pwell - -LAYER OVERLAP - TYPE OVERLAP ; -END OVERLAP - -VIA L1M1_PR - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.145 -0.115 0.145 0.115 ; -END L1M1_PR - -VIA L1M1_PR_R - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.115 -0.145 0.115 0.145 ; -END L1M1_PR_R - -VIA L1M1_PR_M - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.115 -0.145 0.115 0.145 ; -END L1M1_PR_M - -VIA L1M1_PR_MR - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.145 -0.115 0.145 0.115 ; -END L1M1_PR_MR - -VIA L1M1_PR_C - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.145 -0.145 0.145 0.145 ; -END L1M1_PR_C - -VIA M1M2_PR - LAYER met1 ; - RECT -0.16 -0.13 0.16 0.13 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.13 -0.16 0.13 0.16 ; -END M1M2_PR - -VIA M1M2_PR_Enc - LAYER met1 ; - RECT -0.16 -0.13 0.16 0.13 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.16 -0.13 0.16 0.13 ; -END M1M2_PR_Enc - -VIA M1M2_PR_R - LAYER met1 ; - RECT -0.13 -0.16 0.13 0.16 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.16 -0.13 0.16 0.13 ; -END M1M2_PR_R - -VIA M1M2_PR_R_Enc - LAYER met1 ; - RECT -0.13 -0.16 0.13 0.16 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.13 -0.16 0.13 0.16 ; -END M1M2_PR_R_Enc - -VIA M1M2_PR_M - LAYER met1 ; - RECT -0.16 -0.13 0.16 0.13 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.16 -0.13 0.16 0.13 ; -END M1M2_PR_M - -VIA M1M2_PR_M_Enc - LAYER met1 ; - RECT -0.16 -0.13 0.16 0.13 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.13 -0.16 0.13 0.16 ; -END M1M2_PR_M_Enc - -VIA M1M2_PR_MR - LAYER met1 ; - RECT -0.13 -0.16 0.13 0.16 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.13 -0.16 0.13 0.16 ; -END M1M2_PR_MR - -VIA M1M2_PR_MR_Enc - LAYER met1 ; - RECT -0.13 -0.16 0.13 0.16 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.16 -0.13 0.16 0.13 ; -END M1M2_PR_MR_Enc - -VIA M1M2_PR_C - LAYER met1 ; - RECT -0.16 -0.16 0.16 0.16 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.16 -0.16 0.16 0.16 ; -END M1M2_PR_C - -VIA M2M3_PR - LAYER met2 ; - RECT -0.14 -0.185 0.14 0.185 ; - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met3 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M2M3_PR - -VIA M2M3_PR_R - LAYER met2 ; - RECT -0.185 -0.14 0.185 0.14 ; - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met3 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M2M3_PR_R - -VIA M2M3_PR_M - LAYER met2 ; - RECT -0.14 -0.185 0.14 0.185 ; - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met3 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M2M3_PR_M - -VIA M2M3_PR_MR - LAYER met2 ; - RECT -0.185 -0.14 0.185 0.14 ; - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met3 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M2M3_PR_MR - -VIA M2M3_PR_C - LAYER met2 ; - RECT -0.185 -0.185 0.185 0.185 ; - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met3 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M2M3_PR_C - -VIA M3M4_PR - LAYER met3 ; - RECT -0.19 -0.16 0.19 0.16 ; - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR - -VIA M3M4_PR_R - LAYER met3 ; - RECT -0.16 -0.19 0.16 0.19 ; - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR_R - -VIA M3M4_PR_M - LAYER met3 ; - RECT -0.19 -0.16 0.19 0.16 ; - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR_M - -VIA M3M4_PR_MR - LAYER met3 ; - RECT -0.16 -0.19 0.16 0.19 ; - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR_MR - -VIA M3M4_PR_C - LAYER met3 ; - RECT -0.19 -0.19 0.19 0.19 ; - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR_C - -VIA M4M5_PR - LAYER met4 ; - RECT -0.59 -0.59 0.59 0.59 ; - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - LAYER met5 ; - RECT -0.71 -0.71 0.71 0.71 ; -END M4M5_PR - -VIA M4M5_PR_R - LAYER met4 ; - RECT -0.59 -0.59 0.59 0.59 ; - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - LAYER met5 ; - RECT -0.71 -0.71 0.71 0.71 ; -END M4M5_PR_R - -VIA M4M5_PR_M - LAYER met4 ; - RECT -0.59 -0.59 0.59 0.59 ; - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - LAYER met5 ; - RECT -0.71 -0.71 0.71 0.71 ; -END M4M5_PR_M - -VIA M4M5_PR_MR - LAYER met4 ; - RECT -0.59 -0.59 0.59 0.59 ; - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - LAYER met5 ; - RECT -0.71 -0.71 0.71 0.71 ; -END M4M5_PR_MR - -VIA M4M5_PR_C - LAYER met4 ; - RECT -0.59 -0.59 0.59 0.59 ; - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - LAYER met5 ; - RECT -0.71 -0.71 0.71 0.71 ; -END M4M5_PR_C - -SITE unit - CLASS CORE ; - SYMMETRY Y ; - SIZE 0.46 BY 2.72 ; -END unit - -SITE unithddbl - CLASS CORE ; - SIZE 0.46 BY 5.44 ; -END unithddbl - -MACRO sb_1__1_ - CLASS BLOCK ; - ORIGIN 0 0 ; - SIZE 117.76 BY 108.8 ; - SYMMETRY X Y ; - PIN prog_clk[0] - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER met2 ; - RECT 52.83 0 52.97 1.36 ; - END - END prog_clk[0] - PIN chany_top_in[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 63.87 107.44 64.01 108.8 ; - END - END chany_top_in[0] - PIN chany_top_in[1] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 59.27 107.44 59.41 108.8 ; - END - END chany_top_in[1] - PIN chany_top_in[2] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 67.93 107.44 68.23 108.8 ; - END - END chany_top_in[2] - PIN chany_top_in[3] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 78.13 107.44 78.27 108.8 ; - END - END chany_top_in[3] - PIN chany_top_in[4] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 58.35 107.44 58.49 108.8 ; - END - END chany_top_in[4] - PIN chany_top_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 68.93 107.44 69.07 108.8 ; - END - END chany_top_in[5] - PIN chany_top_in[6] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 46.39 107.44 46.53 108.8 ; - END - END chany_top_in[6] - PIN chany_top_in[7] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 73.53 107.44 73.67 108.8 ; - END - END chany_top_in[7] - PIN chany_top_in[8] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 56.51 107.44 56.65 108.8 ; - END - END chany_top_in[8] - PIN chany_top_in[9] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 77.21 107.44 77.35 108.8 ; - END - END chany_top_in[9] - PIN chany_top_in[10] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 66.17 107.44 66.31 108.8 ; - END - END chany_top_in[10] - PIN chany_top_in[11] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 43.63 107.44 43.77 108.8 ; - END - END chany_top_in[11] - PIN chany_top_in[12] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 63.33 107.44 63.63 108.8 ; - END - END chany_top_in[12] - PIN chany_top_in[13] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 49.61 107.44 49.75 108.8 ; - END - END chany_top_in[13] - PIN chany_top_in[14] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 83.19 107.44 83.33 108.8 ; - END - END chany_top_in[14] - PIN chany_top_in[15] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 45.47 107.44 45.61 108.8 ; - END - END chany_top_in[15] - PIN chany_top_in[16] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 79.05 107.44 79.19 108.8 ; - END - END chany_top_in[16] - PIN chany_top_in[17] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 67.09 107.44 67.23 108.8 ; - END - END chany_top_in[17] - PIN chany_top_in[18] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 44.55 107.44 44.69 108.8 ; - END - END chany_top_in[18] - PIN chany_top_in[19] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 60.65 107.44 60.79 108.8 ; - END - END chany_top_in[19] - PIN top_left_grid_pin_42_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 9.13 96.56 9.27 97.92 ; - END - END top_left_grid_pin_42_[0] - PIN top_left_grid_pin_43_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 6.83 96.56 6.97 97.92 ; - END - END top_left_grid_pin_43_[0] - PIN top_left_grid_pin_44_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 12.81 96.56 12.95 97.92 ; - END - END top_left_grid_pin_44_[0] - PIN top_left_grid_pin_45_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 27.99 107.44 28.13 108.8 ; - END - END top_left_grid_pin_45_[0] - PIN top_left_grid_pin_46_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 14.19 96.56 14.33 97.92 ; - END - END top_left_grid_pin_46_[0] - PIN top_left_grid_pin_47_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 7.75 96.56 7.89 97.92 ; - END - END top_left_grid_pin_47_[0] - PIN top_left_grid_pin_48_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 16.03 96.56 16.17 97.92 ; - END - END top_left_grid_pin_48_[0] - PIN top_left_grid_pin_49_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 28.91 107.44 29.05 108.8 ; - END - END top_left_grid_pin_49_[0] - PIN chanx_right_in[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 66.49 117.76 66.79 ; - END - END chanx_right_in[0] - PIN chanx_right_in[1] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 82.81 117.76 83.11 ; - END - END chanx_right_in[1] - PIN chanx_right_in[2] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 92.33 117.76 92.63 ; - END - END chanx_right_in[2] - PIN chanx_right_in[3] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 36.57 117.76 36.87 ; - END - END chanx_right_in[3] - PIN chanx_right_in[4] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 74.65 117.76 74.95 ; - END - END chanx_right_in[4] - PIN chanx_right_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 77.37 117.76 77.67 ; - END - END chanx_right_in[5] - PIN chanx_right_in[6] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 33.85 117.76 34.15 ; - END - END chanx_right_in[6] - PIN chanx_right_in[7] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 46.09 117.76 46.39 ; - END - END chanx_right_in[7] - PIN chanx_right_in[8] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 56.97 117.76 57.27 ; - END - END chanx_right_in[8] - PIN chanx_right_in[9] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 73.29 117.76 73.59 ; - END - END chanx_right_in[9] - PIN chanx_right_in[10] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 84.17 117.76 84.47 ; - END - END chanx_right_in[10] - PIN chanx_right_in[11] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 90.97 117.76 91.27 ; - END - END chanx_right_in[11] - PIN chanx_right_in[12] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 81.45 117.76 81.75 ; - END - END chanx_right_in[12] - PIN chanx_right_in[13] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 44.73 117.76 45.03 ; - END - END chanx_right_in[13] - PIN chanx_right_in[14] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 31.81 117.76 32.11 ; - END - END chanx_right_in[14] - PIN chanx_right_in[15] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 61.73 117.76 62.03 ; - END - END chanx_right_in[15] - PIN chanx_right_in[16] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 65.13 117.76 65.43 ; - END - END chanx_right_in[16] - PIN chanx_right_in[17] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 48.81 117.76 49.11 ; - END - END chanx_right_in[17] - PIN chanx_right_in[18] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 69.21 117.76 69.51 ; - END - END chanx_right_in[18] - PIN chanx_right_in[19] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 89.61 117.76 89.91 ; - END - END chanx_right_in[19] - PIN right_bottom_grid_pin_34_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 109.41 10.88 109.55 12.24 ; - END - END right_bottom_grid_pin_34_[0] - PIN right_bottom_grid_pin_35_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 111.71 10.88 111.85 12.24 ; - END - END right_bottom_grid_pin_35_[0] - PIN right_bottom_grid_pin_36_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 114.01 10.88 114.15 12.24 ; - END - END right_bottom_grid_pin_36_[0] - PIN right_bottom_grid_pin_37_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 108.49 10.88 108.63 12.24 ; - END - END right_bottom_grid_pin_37_[0] - PIN right_bottom_grid_pin_38_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 110.79 10.88 110.93 12.24 ; - END - END right_bottom_grid_pin_38_[0] - PIN right_bottom_grid_pin_39_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 113.09 10.88 113.23 12.24 ; - END - END right_bottom_grid_pin_39_[0] - PIN right_bottom_grid_pin_40_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 101.59 10.88 101.73 12.24 ; - END - END right_bottom_grid_pin_40_[0] - PIN right_bottom_grid_pin_41_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 106.19 10.88 106.33 12.24 ; - END - END right_bottom_grid_pin_41_[0] - PIN chany_bottom_in[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 77.21 0 77.35 1.36 ; - END - END chany_bottom_in[0] - PIN chany_bottom_in[1] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 68.93 0 69.07 1.36 ; - END - END chany_bottom_in[1] - PIN chany_bottom_in[2] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 79.05 0 79.19 1.36 ; - END - END chany_bottom_in[2] - PIN chany_bottom_in[3] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 69.85 0 69.99 1.36 ; - END - END chany_bottom_in[3] - PIN chany_bottom_in[4] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 65.25 0 65.39 1.36 ; - END - END chany_bottom_in[4] - PIN chany_bottom_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 59.27 0 59.41 1.36 ; - END - END chany_bottom_in[5] - PIN chany_bottom_in[6] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 46.85 0 46.99 1.36 ; - END - END chany_bottom_in[6] - PIN chany_bottom_in[7] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 60.19 0 60.33 1.36 ; - END - END chany_bottom_in[7] - PIN chany_bottom_in[8] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 47.77 0 47.91 1.36 ; - END - END chany_bottom_in[8] - PIN chany_bottom_in[9] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 67.09 0 67.23 1.36 ; - END - END chany_bottom_in[9] - PIN chany_bottom_in[10] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 68.01 0 68.15 1.36 ; - END - END chany_bottom_in[10] - PIN chany_bottom_in[11] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 70.77 0 70.91 1.36 ; - END - END chany_bottom_in[11] - PIN chany_bottom_in[12] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 62.49 0 62.63 1.36 ; - END - END chany_bottom_in[12] - PIN chany_bottom_in[13] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 61.11 0 61.25 1.36 ; - END - END chany_bottom_in[13] - PIN chany_bottom_in[14] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 48.69 0 48.83 1.36 ; - END - END chany_bottom_in[14] - PIN chany_bottom_in[15] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 56.97 0 57.11 1.36 ; - END - END chany_bottom_in[15] - PIN chany_bottom_in[16] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 78.13 0 78.27 1.36 ; - END - END chany_bottom_in[16] - PIN chany_bottom_in[17] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 45.93 0 46.07 1.36 ; - END - END chany_bottom_in[17] - PIN chany_bottom_in[18] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 49.61 0 49.75 1.36 ; - END - END chany_bottom_in[18] - PIN chany_bottom_in[19] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 72.61 0 72.75 1.36 ; - END - END chany_bottom_in[19] - PIN bottom_left_grid_pin_42_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 12.73 10.88 13.03 12.24 ; - END - END bottom_left_grid_pin_42_[0] - PIN bottom_left_grid_pin_43_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 9.05 10.88 9.35 12.24 ; - END - END bottom_left_grid_pin_43_[0] - PIN bottom_left_grid_pin_44_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 27.99 0 28.13 1.36 ; - END - END bottom_left_grid_pin_44_[0] - PIN bottom_left_grid_pin_45_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 7.29 10.88 7.43 12.24 ; - END - END bottom_left_grid_pin_45_[0] - PIN bottom_left_grid_pin_46_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 9.13 10.88 9.27 12.24 ; - END - END bottom_left_grid_pin_46_[0] - PIN bottom_left_grid_pin_47_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 15.11 10.88 15.25 12.24 ; - END - END bottom_left_grid_pin_47_[0] - PIN bottom_left_grid_pin_48_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 8.21 10.88 8.35 12.24 ; - END - END bottom_left_grid_pin_48_[0] - PIN bottom_left_grid_pin_49_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 10.05 10.88 10.19 12.24 ; - END - END bottom_left_grid_pin_49_[0] - PIN chanx_left_in[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 66.49 1.38 66.79 ; - END - END chanx_left_in[0] - PIN chanx_left_in[1] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 84.17 1.38 84.47 ; - END - END chanx_left_in[1] - PIN chanx_left_in[2] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 85.53 1.38 85.83 ; - END - END chanx_left_in[2] - PIN chanx_left_in[3] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 37.25 1.38 37.55 ; - END - END chanx_left_in[3] - PIN chanx_left_in[4] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 44.05 1.38 44.35 ; - END - END chanx_left_in[4] - PIN chanx_left_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 31.81 1.38 32.11 ; - END - END chanx_left_in[5] - PIN chanx_left_in[6] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 89.61 1.38 89.91 ; - END - END chanx_left_in[6] - PIN chanx_left_in[7] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 65.13 1.38 65.43 ; - END - END chanx_left_in[7] - PIN chanx_left_in[8] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 56.97 1.38 57.27 ; - END - END chanx_left_in[8] - PIN chanx_left_in[9] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 81.45 1.38 81.75 ; - END - END chanx_left_in[9] - PIN chanx_left_in[10] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 49.49 1.38 49.79 ; - END - END chanx_left_in[10] - PIN chanx_left_in[11] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 75.33 1.38 75.63 ; - END - END chanx_left_in[11] - PIN chanx_left_in[12] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 92.33 1.38 92.63 ; - END - END chanx_left_in[12] - PIN chanx_left_in[13] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 45.41 1.38 45.71 ; - END - END chanx_left_in[13] - PIN chanx_left_in[14] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 86.89 1.38 87.19 ; - END - END chanx_left_in[14] - PIN chanx_left_in[15] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 71.25 1.38 71.55 ; - END - END chanx_left_in[15] - PIN chanx_left_in[16] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 41.33 1.38 41.63 ; - END - END chanx_left_in[16] - PIN chanx_left_in[17] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 38.61 1.38 38.91 ; - END - END chanx_left_in[17] - PIN chanx_left_in[18] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 73.97 1.38 74.27 ; - END - END chanx_left_in[18] - PIN chanx_left_in[19] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 72.61 1.38 72.91 ; - END - END chanx_left_in[19] - PIN left_bottom_grid_pin_34_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 28.91 0 29.05 1.36 ; - END - END left_bottom_grid_pin_34_[0] - PIN left_bottom_grid_pin_35_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 12.81 10.88 12.95 12.24 ; - END - END left_bottom_grid_pin_35_[0] - PIN left_bottom_grid_pin_36_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 4.99 10.88 5.13 12.24 ; - END - END left_bottom_grid_pin_36_[0] - PIN left_bottom_grid_pin_37_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 4.07 10.88 4.21 12.24 ; - END - END left_bottom_grid_pin_37_[0] - PIN left_bottom_grid_pin_38_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 6.37 10.88 6.51 12.24 ; - END - END left_bottom_grid_pin_38_[0] - PIN left_bottom_grid_pin_39_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 4.45 10.88 4.75 12.24 ; - END - END left_bottom_grid_pin_39_[0] - PIN left_bottom_grid_pin_40_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 11.89 10.88 12.03 12.24 ; - END - END left_bottom_grid_pin_40_[0] - PIN left_bottom_grid_pin_41_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 16.03 10.88 16.17 12.24 ; - END - END left_bottom_grid_pin_41_[0] - PIN ccff_head[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 43.37 117.76 43.67 ; - END - END ccff_head[0] - PIN chany_top_out[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 79.97 107.44 80.11 108.8 ; - END - END chany_top_out[0] - PIN chany_top_out[1] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 62.49 107.44 62.63 108.8 ; - END - END chany_top_out[1] - PIN chany_top_out[2] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 47.31 107.44 47.45 108.8 ; - END - END chany_top_out[2] - PIN chany_top_out[3] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 75.37 107.44 75.51 108.8 ; - END - END chany_top_out[3] - PIN chany_top_out[4] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 52.37 107.44 52.51 108.8 ; - END - END chany_top_out[4] - PIN chany_top_out[5] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 76.29 107.44 76.43 108.8 ; - END - END chany_top_out[5] - PIN chany_top_out[6] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 57.43 107.44 57.57 108.8 ; - END - END chany_top_out[6] - PIN chany_top_out[7] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 69.85 107.44 69.99 108.8 ; - END - END chany_top_out[7] - PIN chany_top_out[8] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 48.23 107.44 48.37 108.8 ; - END - END chany_top_out[8] - PIN chany_top_out[9] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 71.23 107.44 71.37 108.8 ; - END - END chany_top_out[9] - PIN chany_top_out[10] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 61.57 107.44 61.71 108.8 ; - END - END chany_top_out[10] - PIN chany_top_out[11] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 64.79 107.44 64.93 108.8 ; - END - END chany_top_out[11] - PIN chany_top_out[12] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 84.11 107.44 84.25 108.8 ; - END - END chany_top_out[12] - PIN chany_top_out[13] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 68.01 107.44 68.15 108.8 ; - END - END chany_top_out[13] - PIN chany_top_out[14] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 34.43 107.44 34.57 108.8 ; - END - END chany_top_out[14] - PIN chany_top_out[15] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 72.61 107.44 72.75 108.8 ; - END - END chany_top_out[15] - PIN chany_top_out[16] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 50.53 107.44 50.67 108.8 ; - END - END chany_top_out[16] - PIN chany_top_out[17] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 74.45 107.44 74.59 108.8 ; - END - END chany_top_out[17] - PIN chany_top_out[18] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 53.29 107.44 53.43 108.8 ; - END - END chany_top_out[18] - PIN chany_top_out[19] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 82.27 107.44 82.41 108.8 ; - END - END chany_top_out[19] - PIN chanx_right_out[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 70.57 117.76 70.87 ; - END - END chanx_right_out[0] - PIN chanx_right_out[1] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 55.61 117.76 55.91 ; - END - END chanx_right_out[1] - PIN chanx_right_out[2] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 71.93 117.76 72.23 ; - END - END chanx_right_out[2] - PIN chanx_right_out[3] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 54.25 117.76 54.55 ; - END - END chanx_right_out[3] - PIN chanx_right_out[4] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 37.93 117.76 38.23 ; - END - END chanx_right_out[4] - PIN chanx_right_out[5] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 80.09 117.76 80.39 ; - END - END chanx_right_out[5] - PIN chanx_right_out[6] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 50.17 117.76 50.47 ; - END - END chanx_right_out[6] - PIN chanx_right_out[7] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 63.77 117.76 64.07 ; - END - END chanx_right_out[7] - PIN chanx_right_out[8] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 42.01 117.76 42.31 ; - END - END chanx_right_out[8] - PIN chanx_right_out[9] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 51.53 117.76 51.83 ; - END - END chanx_right_out[9] - PIN chanx_right_out[10] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 52.89 117.76 53.19 ; - END - END chanx_right_out[10] - PIN chanx_right_out[11] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 39.29 117.76 39.59 ; - END - END chanx_right_out[11] - PIN chanx_right_out[12] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 78.73 117.76 79.03 ; - END - END chanx_right_out[12] - PIN chanx_right_out[13] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 67.85 117.76 68.15 ; - END - END chanx_right_out[13] - PIN chanx_right_out[14] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 35.21 117.76 35.51 ; - END - END chanx_right_out[14] - PIN chanx_right_out[15] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 40.65 117.76 40.95 ; - END - END chanx_right_out[15] - PIN chanx_right_out[16] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 58.33 117.76 58.63 ; - END - END chanx_right_out[16] - PIN chanx_right_out[17] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 47.45 117.76 47.75 ; - END - END chanx_right_out[17] - PIN chanx_right_out[18] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 59.69 117.76 59.99 ; - END - END chanx_right_out[18] - PIN chanx_right_out[19] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 76.01 117.76 76.31 ; - END - END chanx_right_out[19] - PIN chany_bottom_out[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 63.87 0 64.01 1.36 ; - END - END chany_bottom_out[0] - PIN chany_bottom_out[1] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 45.01 0 45.15 1.36 ; - END - END chany_bottom_out[1] - PIN chany_bottom_out[2] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 55.13 0 55.27 1.36 ; - END - END chany_bottom_out[2] - PIN chany_bottom_out[3] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 66.17 0 66.31 1.36 ; - END - END chany_bottom_out[3] - PIN chany_bottom_out[4] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 58.35 0 58.49 1.36 ; - END - END chany_bottom_out[4] - PIN chany_bottom_out[5] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 75.37 0 75.51 1.36 ; - END - END chany_bottom_out[5] - PIN chany_bottom_out[6] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 50.53 0 50.67 1.36 ; - END - END chany_bottom_out[6] - PIN chany_bottom_out[7] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 73.53 0 73.67 1.36 ; - END - END chany_bottom_out[7] - PIN chany_bottom_out[8] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 82.73 0 82.87 1.36 ; - END - END chany_bottom_out[8] - PIN chany_bottom_out[9] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 74.45 0 74.59 1.36 ; - END - END chany_bottom_out[9] - PIN chany_bottom_out[10] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 56.05 0 56.19 1.36 ; - END - END chany_bottom_out[10] - PIN chany_bottom_out[11] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 71.69 0 71.83 1.36 ; - END - END chany_bottom_out[11] - PIN chany_bottom_out[12] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 79.97 0 80.11 1.36 ; - END - END chany_bottom_out[12] - PIN chany_bottom_out[13] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 76.29 0 76.43 1.36 ; - END - END chany_bottom_out[13] - PIN chany_bottom_out[14] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 34.43 0 34.57 1.36 ; - END - END chany_bottom_out[14] - PIN chany_bottom_out[15] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 88.25 0 88.39 1.36 ; - END - END chany_bottom_out[15] - PIN chany_bottom_out[16] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 81.81 0 81.95 1.36 ; - END - END chany_bottom_out[16] - PIN chany_bottom_out[17] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 87.33 0 87.47 1.36 ; - END - END chany_bottom_out[17] - PIN chany_bottom_out[18] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 54.21 0 54.35 1.36 ; - END - END chany_bottom_out[18] - PIN chany_bottom_out[19] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 89.17 0 89.31 1.36 ; - END - END chany_bottom_out[19] - PIN chanx_left_out[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 82.81 1.38 83.11 ; - END - END chanx_left_out[0] - PIN chanx_left_out[1] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 63.77 1.38 64.07 ; - END - END chanx_left_out[1] - PIN chanx_left_out[2] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 59.01 1.38 59.31 ; - END - END chanx_left_out[2] - PIN chanx_left_out[3] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 48.13 1.38 48.43 ; - END - END chanx_left_out[3] - PIN chanx_left_out[4] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 62.41 1.38 62.71 ; - END - END chanx_left_out[4] - PIN chanx_left_out[5] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 88.25 1.38 88.55 ; - END - END chanx_left_out[5] - PIN chanx_left_out[6] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 46.77 1.38 47.07 ; - END - END chanx_left_out[6] - PIN chanx_left_out[7] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 50.85 1.38 51.15 ; - END - END chanx_left_out[7] - PIN chanx_left_out[8] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 54.93 1.38 55.23 ; - END - END chanx_left_out[8] - PIN chanx_left_out[9] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 52.21 1.38 52.51 ; - END - END chanx_left_out[9] - PIN chanx_left_out[10] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 61.05 1.38 61.35 ; - END - END chanx_left_out[10] - PIN chanx_left_out[11] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 68.53 1.38 68.83 ; - END - END chanx_left_out[11] - PIN chanx_left_out[12] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 42.69 1.38 42.99 ; - END - END chanx_left_out[12] - PIN chanx_left_out[13] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 90.97 1.38 91.27 ; - END - END chanx_left_out[13] - PIN chanx_left_out[14] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 33.17 1.38 33.47 ; - END - END chanx_left_out[14] - PIN chanx_left_out[15] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 78.73 1.38 79.03 ; - END - END chanx_left_out[15] - PIN chanx_left_out[16] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 69.89 1.38 70.19 ; - END - END chanx_left_out[16] - PIN chanx_left_out[17] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 39.97 1.38 40.27 ; - END - END chanx_left_out[17] - PIN chanx_left_out[18] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 53.57 1.38 53.87 ; - END - END chanx_left_out[18] - PIN chanx_left_out[19] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 80.09 1.38 80.39 ; - END - END chanx_left_out[19] - PIN ccff_tail[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 76.69 1.38 76.99 ; - END - END ccff_tail[0] - PIN VDD - DIRECTION INPUT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 25.76 2.48 26.24 2.96 ; - RECT 91.52 2.48 92 2.96 ; - RECT 25.76 7.92 26.24 8.4 ; - RECT 91.52 7.92 92 8.4 ; - RECT 0 13.36 0.48 13.84 ; - RECT 117.28 13.36 117.76 13.84 ; - RECT 0 18.8 0.48 19.28 ; - RECT 117.28 18.8 117.76 19.28 ; - RECT 0 24.24 0.48 24.72 ; - RECT 117.28 24.24 117.76 24.72 ; - RECT 0 29.68 0.48 30.16 ; - RECT 117.28 29.68 117.76 30.16 ; - RECT 0 35.12 0.48 35.6 ; - RECT 117.28 35.12 117.76 35.6 ; - RECT 0 40.56 0.48 41.04 ; - RECT 117.28 40.56 117.76 41.04 ; - RECT 0 46 0.48 46.48 ; - RECT 117.28 46 117.76 46.48 ; - RECT 0 51.44 0.48 51.92 ; - RECT 117.28 51.44 117.76 51.92 ; - RECT 0 56.88 0.48 57.36 ; - RECT 117.28 56.88 117.76 57.36 ; - RECT 0 62.32 0.48 62.8 ; - RECT 117.28 62.32 117.76 62.8 ; - RECT 0 67.76 0.48 68.24 ; - RECT 117.28 67.76 117.76 68.24 ; - RECT 0 73.2 0.48 73.68 ; - RECT 117.28 73.2 117.76 73.68 ; - RECT 0 78.64 0.48 79.12 ; - RECT 117.28 78.64 117.76 79.12 ; - RECT 0 84.08 0.48 84.56 ; - RECT 117.28 84.08 117.76 84.56 ; - RECT 0 89.52 0.48 90 ; - RECT 117.28 89.52 117.76 90 ; - RECT 0 94.96 0.48 95.44 ; - RECT 117.28 94.96 117.76 95.44 ; - RECT 25.76 100.4 26.24 100.88 ; - RECT 91.52 100.4 92 100.88 ; - RECT 25.76 105.84 26.24 106.32 ; - RECT 91.52 105.84 92 106.32 ; - LAYER met4 ; - RECT 36.5 0 37.1 0.6 ; - RECT 65.94 0 66.54 0.6 ; - RECT 106.42 10.88 107.02 11.48 ; - RECT 106.42 97.32 107.02 97.92 ; - RECT 36.5 108.2 37.1 108.8 ; - RECT 65.94 108.2 66.54 108.8 ; - LAYER met5 ; - RECT 0 22.2 3.2 25.4 ; - RECT 114.56 22.2 117.76 25.4 ; - RECT 0 63 3.2 66.2 ; - RECT 114.56 63 117.76 66.2 ; - END - END VDD - PIN VSS - DIRECTION INPUT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 25.76 0 92 0.24 ; - RECT 25.76 5.2 26.24 5.68 ; - RECT 91.52 5.2 92 5.68 ; - RECT 0 10.64 117.76 11.12 ; - RECT 0 16.08 0.48 16.56 ; - RECT 117.28 16.08 117.76 16.56 ; - RECT 0 21.52 0.48 22 ; - RECT 117.28 21.52 117.76 22 ; - RECT 0 26.96 0.48 27.44 ; - RECT 117.28 26.96 117.76 27.44 ; - RECT 0 32.4 0.48 32.88 ; - RECT 117.28 32.4 117.76 32.88 ; - RECT 0 37.84 0.48 38.32 ; - RECT 117.28 37.84 117.76 38.32 ; - RECT 0 43.28 0.48 43.76 ; - RECT 117.28 43.28 117.76 43.76 ; - RECT 0 48.72 0.48 49.2 ; - RECT 117.28 48.72 117.76 49.2 ; - RECT 0 54.16 0.48 54.64 ; - RECT 117.28 54.16 117.76 54.64 ; - RECT 0 59.6 0.48 60.08 ; - RECT 117.28 59.6 117.76 60.08 ; - RECT 0 65.04 0.48 65.52 ; - RECT 117.28 65.04 117.76 65.52 ; - RECT 0 70.48 0.48 70.96 ; - RECT 117.28 70.48 117.76 70.96 ; - RECT 0 75.92 0.48 76.4 ; - RECT 117.28 75.92 117.76 76.4 ; - RECT 0 81.36 0.48 81.84 ; - RECT 117.28 81.36 117.76 81.84 ; - RECT 0 86.8 0.48 87.28 ; - RECT 117.28 86.8 117.76 87.28 ; - RECT 0 92.24 0.48 92.72 ; - RECT 117.28 92.24 117.76 92.72 ; - RECT 0 97.68 117.76 98.16 ; - RECT 25.76 103.12 26.24 103.6 ; - RECT 91.52 103.12 92 103.6 ; - RECT 25.76 108.56 92 108.8 ; - LAYER met4 ; - RECT 51.22 0 51.82 0.6 ; - RECT 80.66 0 81.26 0.6 ; - RECT 10.74 10.88 11.34 11.48 ; - RECT 10.74 97.32 11.34 97.92 ; - RECT 51.22 108.2 51.82 108.8 ; - RECT 80.66 108.2 81.26 108.8 ; - LAYER met5 ; - RECT 0 42.6 3.2 45.8 ; - RECT 114.56 42.6 117.76 45.8 ; - RECT 0 83.4 3.2 86.6 ; - RECT 114.56 83.4 117.76 86.6 ; - END - END VSS - PIN prog_clk__FEEDTHRU_1[0] - DIRECTION OUTPUT ; - USE CLOCK ; - PORT - LAYER met2 ; - RECT 55.13 107.44 55.27 108.8 ; - END - END prog_clk__FEEDTHRU_1[0] - PIN Test_en__FEEDTHRU_0[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 2.23 96.56 2.37 97.92 ; - END - END Test_en__FEEDTHRU_0[0] - PIN Test_en__FEEDTHRU_1[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 2.23 10.88 2.37 12.24 ; - END - END Test_en__FEEDTHRU_1[0] - PIN clk__FEEDTHRU_0[0] - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER met2 ; - RECT 3.15 96.56 3.29 97.92 ; - END - END clk__FEEDTHRU_0[0] - PIN clk__FEEDTHRU_1[0] - DIRECTION OUTPUT ; - USE CLOCK ; - PORT - LAYER met2 ; - RECT 3.15 10.88 3.29 12.24 ; - END - END clk__FEEDTHRU_1[0] - PIN grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 18.33 10.88 18.47 12.24 ; - END - END grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] - PIN grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 99.29 96.56 99.43 97.92 ; - END - END grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1[0] - OBS - LAYER li1 ; - RECT 25.76 108.715 92 108.885 ; - RECT 91.54 105.995 92 106.165 ; - RECT 25.76 105.995 29.44 106.165 ; - RECT 91.08 103.275 92 103.445 ; - RECT 25.76 103.275 27.6 103.445 ; - RECT 91.08 100.555 92 100.725 ; - RECT 25.76 100.555 29.44 100.725 ; - RECT 89.24 97.835 117.76 98.005 ; - RECT 0 97.835 29.44 98.005 ; - RECT 116.84 95.115 117.76 95.285 ; - RECT 0 95.115 3.68 95.285 ; - RECT 114.08 92.395 117.76 92.565 ; - RECT 0 92.395 3.68 92.565 ; - RECT 114.08 89.675 117.76 89.845 ; - RECT 0 89.675 1.84 89.845 ; - RECT 117.3 86.955 117.76 87.125 ; - RECT 0 86.955 1.84 87.125 ; - RECT 117.3 84.235 117.76 84.405 ; - RECT 0 84.235 1.84 84.405 ; - RECT 115.92 81.515 117.76 81.685 ; - RECT 0 81.515 1.84 81.685 ; - RECT 115.92 78.795 117.76 78.965 ; - RECT 0 78.795 1.84 78.965 ; - RECT 116.84 76.075 117.76 76.245 ; - RECT 0 76.075 1.84 76.245 ; - RECT 116.84 73.355 117.76 73.525 ; - RECT 0 73.355 1.84 73.525 ; - RECT 116.84 70.635 117.76 70.805 ; - RECT 0 70.635 1.84 70.805 ; - RECT 116.84 67.915 117.76 68.085 ; - RECT 0 67.915 1.84 68.085 ; - RECT 116.84 65.195 117.76 65.365 ; - RECT 0 65.195 1.84 65.365 ; - RECT 116.84 62.475 117.76 62.645 ; - RECT 0 62.475 1.84 62.645 ; - RECT 116.84 59.755 117.76 59.925 ; - RECT 0 59.755 1.84 59.925 ; - RECT 116.84 57.035 117.76 57.205 ; - RECT 0 57.035 1.84 57.205 ; - RECT 116.84 54.315 117.76 54.485 ; - RECT 0 54.315 1.84 54.485 ; - RECT 116.84 51.595 117.76 51.765 ; - RECT 0 51.595 1.84 51.765 ; - RECT 116.84 48.875 117.76 49.045 ; - RECT 0 48.875 1.84 49.045 ; - RECT 116.84 46.155 117.76 46.325 ; - RECT 0 46.155 1.84 46.325 ; - RECT 116.84 43.435 117.76 43.605 ; - RECT 0 43.435 1.84 43.605 ; - RECT 116.84 40.715 117.76 40.885 ; - RECT 0 40.715 1.84 40.885 ; - RECT 116.84 37.995 117.76 38.165 ; - RECT 0 37.995 1.84 38.165 ; - RECT 116.84 35.275 117.76 35.445 ; - RECT 0 35.275 3.68 35.445 ; - RECT 116.84 32.555 117.76 32.725 ; - RECT 0 32.555 3.68 32.725 ; - RECT 116.84 29.835 117.76 30.005 ; - RECT 0 29.835 3.68 30.005 ; - RECT 114.08 27.115 117.76 27.285 ; - RECT 0 27.115 3.68 27.285 ; - RECT 114.08 24.395 117.76 24.565 ; - RECT 0 24.395 3.68 24.565 ; - RECT 116.84 21.675 117.76 21.845 ; - RECT 0 21.675 3.68 21.845 ; - RECT 116.84 18.955 117.76 19.125 ; - RECT 0 18.955 3.68 19.125 ; - RECT 116.84 16.235 117.76 16.405 ; - RECT 0 16.235 1.84 16.405 ; - RECT 117.3 13.515 117.76 13.685 ; - RECT 0 13.515 3.68 13.685 ; - RECT 88.78 10.795 117.76 10.965 ; - RECT 0 10.795 29.44 10.965 ; - RECT 91.08 8.075 92 8.245 ; - RECT 25.76 8.075 29.44 8.245 ; - RECT 91.08 5.355 92 5.525 ; - RECT 25.76 5.355 29.44 5.525 ; - RECT 91.08 2.635 92 2.805 ; - RECT 25.76 2.635 29.44 2.805 ; - RECT 25.76 -0.085 92 0.085 ; - LAYER met2 ; - RECT 80.82 108.615 81.1 108.985 ; - RECT 51.38 108.615 51.66 108.985 ; - RECT 74.85 106.94 75.11 107.26 ; - RECT 66.57 106.94 66.83 107.26 ; - RECT 65.19 106.94 65.45 107.26 ; - RECT 46.79 106.94 47.05 107.26 ; - RECT 10.9 97.735 11.18 98.105 ; - RECT 107.97 12.42 108.23 12.74 ; - RECT 10.9 10.695 11.18 11.065 ; - RECT 68.41 1.54 68.67 1.86 ; - RECT 57.37 1.54 57.63 1.86 ; - RECT 50.93 1.54 51.19 1.86 ; - RECT 80.82 -0.185 81.1 0.185 ; - RECT 51.38 -0.185 51.66 0.185 ; - POLYGON 91.72 108.52 91.72 97.64 99.01 97.64 99.01 96.28 99.71 96.28 99.71 97.64 117.48 97.64 117.48 11.16 114.43 11.16 114.43 12.52 113.73 12.52 113.73 11.16 113.51 11.16 113.51 12.52 112.81 12.52 112.81 11.16 112.13 11.16 112.13 12.52 111.43 12.52 111.43 11.16 111.21 11.16 111.21 12.52 110.51 12.52 110.51 11.16 109.83 11.16 109.83 12.52 109.13 12.52 109.13 11.16 108.91 11.16 108.91 12.52 108.21 12.52 108.21 11.16 106.61 11.16 106.61 12.52 105.91 12.52 105.91 11.16 102.01 11.16 102.01 12.52 101.31 12.52 101.31 11.16 91.72 11.16 91.72 0.28 89.59 0.28 89.59 1.64 88.89 1.64 88.89 0.28 88.67 0.28 88.67 1.64 87.97 1.64 87.97 0.28 87.75 0.28 87.75 1.64 87.05 1.64 87.05 0.28 83.15 0.28 83.15 1.64 82.45 1.64 82.45 0.28 82.23 0.28 82.23 1.64 81.53 1.64 81.53 0.28 80.39 0.28 80.39 1.64 79.69 1.64 79.69 0.28 79.47 0.28 79.47 1.64 78.77 1.64 78.77 0.28 78.55 0.28 78.55 1.64 77.85 1.64 77.85 0.28 77.63 0.28 77.63 1.64 76.93 1.64 76.93 0.28 76.71 0.28 76.71 1.64 76.01 1.64 76.01 0.28 75.79 0.28 75.79 1.64 75.09 1.64 75.09 0.28 74.87 0.28 74.87 1.64 74.17 1.64 74.17 0.28 73.95 0.28 73.95 1.64 73.25 1.64 73.25 0.28 73.03 0.28 73.03 1.64 72.33 1.64 72.33 0.28 72.11 0.28 72.11 1.64 71.41 1.64 71.41 0.28 71.19 0.28 71.19 1.64 70.49 1.64 70.49 0.28 70.27 0.28 70.27 1.64 69.57 1.64 69.57 0.28 69.35 0.28 69.35 1.64 68.65 1.64 68.65 0.28 68.43 0.28 68.43 1.64 67.73 1.64 67.73 0.28 67.51 0.28 67.51 1.64 66.81 1.64 66.81 0.28 66.59 0.28 66.59 1.64 65.89 1.64 65.89 0.28 65.67 0.28 65.67 1.64 64.97 1.64 64.97 0.28 64.29 0.28 64.29 1.64 63.59 1.64 63.59 0.28 62.91 0.28 62.91 1.64 62.21 1.64 62.21 0.28 61.53 0.28 61.53 1.64 60.83 1.64 60.83 0.28 60.61 0.28 60.61 1.64 59.91 1.64 59.91 0.28 59.69 0.28 59.69 1.64 58.99 1.64 58.99 0.28 58.77 0.28 58.77 1.64 58.07 1.64 58.07 0.28 57.39 0.28 57.39 1.64 56.69 1.64 56.69 0.28 56.47 0.28 56.47 1.64 55.77 1.64 55.77 0.28 55.55 0.28 55.55 1.64 54.85 1.64 54.85 0.28 54.63 0.28 54.63 1.64 53.93 1.64 53.93 0.28 53.25 0.28 53.25 1.64 52.55 1.64 52.55 0.28 50.95 0.28 50.95 1.64 50.25 1.64 50.25 0.28 50.03 0.28 50.03 1.64 49.33 1.64 49.33 0.28 49.11 0.28 49.11 1.64 48.41 1.64 48.41 0.28 48.19 0.28 48.19 1.64 47.49 1.64 47.49 0.28 47.27 0.28 47.27 1.64 46.57 1.64 46.57 0.28 46.35 0.28 46.35 1.64 45.65 1.64 45.65 0.28 45.43 0.28 45.43 1.64 44.73 1.64 44.73 0.28 34.85 0.28 34.85 1.64 34.15 1.64 34.15 0.28 29.33 0.28 29.33 1.64 28.63 1.64 28.63 0.28 28.41 0.28 28.41 1.64 27.71 1.64 27.71 0.28 26.04 0.28 26.04 11.16 18.75 11.16 18.75 12.52 18.05 12.52 18.05 11.16 16.45 11.16 16.45 12.52 15.75 12.52 15.75 11.16 15.53 11.16 15.53 12.52 14.83 12.52 14.83 11.16 13.23 11.16 13.23 12.52 12.53 12.52 12.53 11.16 12.31 11.16 12.31 12.52 11.61 12.52 11.61 11.16 10.47 11.16 10.47 12.52 9.77 12.52 9.77 11.16 9.55 11.16 9.55 12.52 8.85 12.52 8.85 11.16 8.63 11.16 8.63 12.52 7.93 12.52 7.93 11.16 7.71 11.16 7.71 12.52 7.01 12.52 7.01 11.16 6.79 11.16 6.79 12.52 6.09 12.52 6.09 11.16 5.41 11.16 5.41 12.52 4.71 12.52 4.71 11.16 4.49 11.16 4.49 12.52 3.79 12.52 3.79 11.16 3.57 11.16 3.57 12.52 2.87 12.52 2.87 11.16 2.65 11.16 2.65 12.52 1.95 12.52 1.95 11.16 0.28 11.16 0.28 97.64 1.95 97.64 1.95 96.28 2.65 96.28 2.65 97.64 2.87 97.64 2.87 96.28 3.57 96.28 3.57 97.64 6.55 97.64 6.55 96.28 7.25 96.28 7.25 97.64 7.47 97.64 7.47 96.28 8.17 96.28 8.17 97.64 8.85 97.64 8.85 96.28 9.55 96.28 9.55 97.64 12.53 97.64 12.53 96.28 13.23 96.28 13.23 97.64 13.91 97.64 13.91 96.28 14.61 96.28 14.61 97.64 15.75 97.64 15.75 96.28 16.45 96.28 16.45 97.64 26.04 97.64 26.04 108.52 27.71 108.52 27.71 107.16 28.41 107.16 28.41 108.52 28.63 108.52 28.63 107.16 29.33 107.16 29.33 108.52 34.15 108.52 34.15 107.16 34.85 107.16 34.85 108.52 43.35 108.52 43.35 107.16 44.05 107.16 44.05 108.52 44.27 108.52 44.27 107.16 44.97 107.16 44.97 108.52 45.19 108.52 45.19 107.16 45.89 107.16 45.89 108.52 46.11 108.52 46.11 107.16 46.81 107.16 46.81 108.52 47.03 108.52 47.03 107.16 47.73 107.16 47.73 108.52 47.95 108.52 47.95 107.16 48.65 107.16 48.65 108.52 49.33 108.52 49.33 107.16 50.03 107.16 50.03 108.52 50.25 108.52 50.25 107.16 50.95 107.16 50.95 108.52 52.09 108.52 52.09 107.16 52.79 107.16 52.79 108.52 53.01 108.52 53.01 107.16 53.71 107.16 53.71 108.52 54.85 108.52 54.85 107.16 55.55 107.16 55.55 108.52 56.23 108.52 56.23 107.16 56.93 107.16 56.93 108.52 57.15 108.52 57.15 107.16 57.85 107.16 57.85 108.52 58.07 108.52 58.07 107.16 58.77 107.16 58.77 108.52 58.99 108.52 58.99 107.16 59.69 107.16 59.69 108.52 60.37 108.52 60.37 107.16 61.07 107.16 61.07 108.52 61.29 108.52 61.29 107.16 61.99 107.16 61.99 108.52 62.21 108.52 62.21 107.16 62.91 107.16 62.91 108.52 63.59 108.52 63.59 107.16 64.29 107.16 64.29 108.52 64.51 108.52 64.51 107.16 65.21 107.16 65.21 108.52 65.89 108.52 65.89 107.16 66.59 107.16 66.59 108.52 66.81 108.52 66.81 107.16 67.51 107.16 67.51 108.52 67.73 108.52 67.73 107.16 68.43 107.16 68.43 108.52 68.65 108.52 68.65 107.16 69.35 107.16 69.35 108.52 69.57 108.52 69.57 107.16 70.27 107.16 70.27 108.52 70.95 108.52 70.95 107.16 71.65 107.16 71.65 108.52 72.33 108.52 72.33 107.16 73.03 107.16 73.03 108.52 73.25 108.52 73.25 107.16 73.95 107.16 73.95 108.52 74.17 108.52 74.17 107.16 74.87 107.16 74.87 108.52 75.09 108.52 75.09 107.16 75.79 107.16 75.79 108.52 76.01 108.52 76.01 107.16 76.71 107.16 76.71 108.52 76.93 108.52 76.93 107.16 77.63 107.16 77.63 108.52 77.85 108.52 77.85 107.16 78.55 107.16 78.55 108.52 78.77 108.52 78.77 107.16 79.47 107.16 79.47 108.52 79.69 108.52 79.69 107.16 80.39 107.16 80.39 108.52 81.99 108.52 81.99 107.16 82.69 107.16 82.69 108.52 82.91 108.52 82.91 107.16 83.61 107.16 83.61 108.52 83.83 108.52 83.83 107.16 84.53 107.16 84.53 108.52 ; - LAYER met4 ; - POLYGON 91.6 108.4 91.6 97.52 106.02 97.52 106.02 96.92 107.42 96.92 107.42 97.52 117.36 97.52 117.36 11.28 107.42 11.28 107.42 11.88 106.02 11.88 106.02 11.28 91.6 11.28 91.6 0.4 81.66 0.4 81.66 1 80.26 1 80.26 0.4 66.94 0.4 66.94 1 65.54 1 65.54 0.4 52.22 0.4 52.22 1 50.82 1 50.82 0.4 37.5 0.4 37.5 1 36.1 1 36.1 0.4 26.16 0.4 26.16 11.28 13.43 11.28 13.43 12.64 12.33 12.64 12.33 11.28 11.74 11.28 11.74 11.88 10.34 11.88 10.34 11.28 9.75 11.28 9.75 12.64 8.65 12.64 8.65 11.28 5.15 11.28 5.15 12.64 4.05 12.64 4.05 11.28 0.4 11.28 0.4 97.52 10.34 97.52 10.34 96.92 11.74 96.92 11.74 97.52 26.16 97.52 26.16 108.4 36.1 108.4 36.1 107.8 37.5 107.8 37.5 108.4 50.82 108.4 50.82 107.8 52.22 107.8 52.22 108.4 62.93 108.4 62.93 107.04 64.03 107.04 64.03 108.4 65.54 108.4 65.54 107.8 66.94 107.8 66.94 108.4 67.53 108.4 67.53 107.04 68.63 107.04 68.63 108.4 80.26 108.4 80.26 107.8 81.66 107.8 81.66 108.4 ; - LAYER met3 ; - POLYGON 81.125 108.965 81.125 108.96 81.34 108.96 81.34 108.64 81.125 108.64 81.125 108.635 80.795 108.635 80.795 108.64 80.58 108.64 80.58 108.96 80.795 108.96 80.795 108.965 ; - POLYGON 51.685 108.965 51.685 108.96 51.9 108.96 51.9 108.64 51.685 108.64 51.685 108.635 51.355 108.635 51.355 108.64 51.14 108.64 51.14 108.96 51.355 108.96 51.355 108.965 ; - POLYGON 11.205 98.085 11.205 98.08 11.42 98.08 11.42 97.76 11.205 97.76 11.205 97.755 10.875 97.755 10.875 97.76 10.66 97.76 10.66 98.08 10.875 98.08 10.875 98.085 ; - POLYGON 15.79 87.87 15.79 87.57 1.78 87.57 1.78 87.59 1.23 87.59 1.23 87.87 ; - POLYGON 116.11 72.92 116.11 72.6 115.73 72.6 115.73 72.61 107.49 72.61 107.49 72.91 115.73 72.91 115.73 72.92 ; - POLYGON 17.63 66.11 17.63 65.81 1.78 65.81 1.78 65.83 1.23 65.83 1.23 66.11 ; - POLYGON 2.005 57.965 2.005 57.96 2.03 57.96 2.03 57.64 2.005 57.64 2.005 57.635 1.275 57.635 1.275 57.965 ; - POLYGON 19.01 46.39 19.01 46.09 1.78 46.09 1.78 46.11 1.23 46.11 1.23 46.39 ; - POLYGON 11.205 11.045 11.205 11.04 11.42 11.04 11.42 10.72 11.205 10.72 11.205 10.715 10.875 10.715 10.875 10.72 10.66 10.72 10.66 11.04 10.875 11.04 10.875 11.045 ; - POLYGON 81.125 0.165 81.125 0.16 81.34 0.16 81.34 -0.16 81.125 -0.16 81.125 -0.165 80.795 -0.165 80.795 -0.16 80.58 -0.16 80.58 0.16 80.795 0.16 80.795 0.165 ; - POLYGON 51.685 0.165 51.685 0.16 51.9 0.16 51.9 -0.16 51.685 -0.16 51.685 -0.165 51.355 -0.165 51.355 -0.16 51.14 -0.16 51.14 0.16 51.355 0.16 51.355 0.165 ; - POLYGON 91.6 108.4 91.6 97.52 117.36 97.52 117.36 93.03 115.98 93.03 115.98 91.93 117.36 91.93 117.36 91.67 115.98 91.67 115.98 90.57 117.36 90.57 117.36 90.31 115.98 90.31 115.98 89.21 117.36 89.21 117.36 84.87 115.98 84.87 115.98 83.77 117.36 83.77 117.36 83.51 115.98 83.51 115.98 82.41 117.36 82.41 117.36 82.15 115.98 82.15 115.98 81.05 117.36 81.05 117.36 80.79 115.98 80.79 115.98 79.69 117.36 79.69 117.36 79.43 115.98 79.43 115.98 78.33 117.36 78.33 117.36 78.07 115.98 78.07 115.98 76.97 117.36 76.97 117.36 76.71 115.98 76.71 115.98 75.61 117.36 75.61 117.36 75.35 115.98 75.35 115.98 74.25 117.36 74.25 117.36 73.99 115.98 73.99 115.98 72.89 117.36 72.89 117.36 72.63 115.98 72.63 115.98 71.53 117.36 71.53 117.36 71.27 115.98 71.27 115.98 70.17 117.36 70.17 117.36 69.91 115.98 69.91 115.98 68.81 117.36 68.81 117.36 68.55 115.98 68.55 115.98 67.45 117.36 67.45 117.36 67.19 115.98 67.19 115.98 66.09 117.36 66.09 117.36 65.83 115.98 65.83 115.98 64.73 117.36 64.73 117.36 64.47 115.98 64.47 115.98 63.37 117.36 63.37 117.36 62.43 115.98 62.43 115.98 61.33 117.36 61.33 117.36 60.39 115.98 60.39 115.98 59.29 117.36 59.29 117.36 59.03 115.98 59.03 115.98 57.93 117.36 57.93 117.36 57.67 115.98 57.67 115.98 56.57 117.36 56.57 117.36 56.31 115.98 56.31 115.98 55.21 117.36 55.21 117.36 54.95 115.98 54.95 115.98 53.85 117.36 53.85 117.36 53.59 115.98 53.59 115.98 52.49 117.36 52.49 117.36 52.23 115.98 52.23 115.98 51.13 117.36 51.13 117.36 50.87 115.98 50.87 115.98 49.77 117.36 49.77 117.36 49.51 115.98 49.51 115.98 48.41 117.36 48.41 117.36 48.15 115.98 48.15 115.98 47.05 117.36 47.05 117.36 46.79 115.98 46.79 115.98 45.69 117.36 45.69 117.36 45.43 115.98 45.43 115.98 44.33 117.36 44.33 117.36 44.07 115.98 44.07 115.98 42.97 117.36 42.97 117.36 42.71 115.98 42.71 115.98 41.61 117.36 41.61 117.36 41.35 115.98 41.35 115.98 40.25 117.36 40.25 117.36 39.99 115.98 39.99 115.98 38.89 117.36 38.89 117.36 38.63 115.98 38.63 115.98 37.53 117.36 37.53 117.36 37.27 115.98 37.27 115.98 36.17 117.36 36.17 117.36 35.91 115.98 35.91 115.98 34.81 117.36 34.81 117.36 34.55 115.98 34.55 115.98 33.45 117.36 33.45 117.36 32.51 115.98 32.51 115.98 31.41 117.36 31.41 117.36 11.28 91.6 11.28 91.6 0.4 26.16 0.4 26.16 11.28 0.4 11.28 0.4 31.41 1.78 31.41 1.78 32.51 0.4 32.51 0.4 32.77 1.78 32.77 1.78 33.87 0.4 33.87 0.4 36.85 1.78 36.85 1.78 37.95 0.4 37.95 0.4 38.21 1.78 38.21 1.78 39.31 0.4 39.31 0.4 39.57 1.78 39.57 1.78 40.67 0.4 40.67 0.4 40.93 1.78 40.93 1.78 42.03 0.4 42.03 0.4 42.29 1.78 42.29 1.78 43.39 0.4 43.39 0.4 43.65 1.78 43.65 1.78 44.75 0.4 44.75 0.4 45.01 1.78 45.01 1.78 46.11 0.4 46.11 0.4 46.37 1.78 46.37 1.78 47.47 0.4 47.47 0.4 47.73 1.78 47.73 1.78 48.83 0.4 48.83 0.4 49.09 1.78 49.09 1.78 50.19 0.4 50.19 0.4 50.45 1.78 50.45 1.78 51.55 0.4 51.55 0.4 51.81 1.78 51.81 1.78 52.91 0.4 52.91 0.4 53.17 1.78 53.17 1.78 54.27 0.4 54.27 0.4 54.53 1.78 54.53 1.78 55.63 0.4 55.63 0.4 56.57 1.78 56.57 1.78 57.67 0.4 57.67 0.4 58.61 1.78 58.61 1.78 59.71 0.4 59.71 0.4 60.65 1.78 60.65 1.78 61.75 0.4 61.75 0.4 62.01 1.78 62.01 1.78 63.11 0.4 63.11 0.4 63.37 1.78 63.37 1.78 64.47 0.4 64.47 0.4 64.73 1.78 64.73 1.78 65.83 0.4 65.83 0.4 66.09 1.78 66.09 1.78 67.19 0.4 67.19 0.4 68.13 1.78 68.13 1.78 69.23 0.4 69.23 0.4 69.49 1.78 69.49 1.78 70.59 0.4 70.59 0.4 70.85 1.78 70.85 1.78 71.95 0.4 71.95 0.4 72.21 1.78 72.21 1.78 73.31 0.4 73.31 0.4 73.57 1.78 73.57 1.78 74.67 0.4 74.67 0.4 74.93 1.78 74.93 1.78 76.03 0.4 76.03 0.4 76.29 1.78 76.29 1.78 77.39 0.4 77.39 0.4 78.33 1.78 78.33 1.78 79.43 0.4 79.43 0.4 79.69 1.78 79.69 1.78 80.79 0.4 80.79 0.4 81.05 1.78 81.05 1.78 82.15 0.4 82.15 0.4 82.41 1.78 82.41 1.78 83.51 0.4 83.51 0.4 83.77 1.78 83.77 1.78 84.87 0.4 84.87 0.4 85.13 1.78 85.13 1.78 86.23 0.4 86.23 0.4 86.49 1.78 86.49 1.78 87.59 0.4 87.59 0.4 87.85 1.78 87.85 1.78 88.95 0.4 88.95 0.4 89.21 1.78 89.21 1.78 90.31 0.4 90.31 0.4 90.57 1.78 90.57 1.78 91.67 0.4 91.67 0.4 91.93 1.78 91.93 1.78 93.03 0.4 93.03 0.4 97.52 26.16 97.52 26.16 108.4 ; - LAYER met5 ; - POLYGON 90.4 107.2 90.4 96.32 116.16 96.32 116.16 88.2 112.96 88.2 112.96 81.8 116.16 81.8 116.16 67.8 112.96 67.8 112.96 61.4 116.16 61.4 116.16 47.4 112.96 47.4 112.96 41 116.16 41 116.16 27 112.96 27 112.96 20.6 116.16 20.6 116.16 12.48 90.4 12.48 90.4 1.6 27.36 1.6 27.36 12.48 1.6 12.48 1.6 20.6 4.8 20.6 4.8 27 1.6 27 1.6 41 4.8 41 4.8 47.4 1.6 47.4 1.6 61.4 4.8 61.4 4.8 67.8 1.6 67.8 1.6 81.8 4.8 81.8 4.8 88.2 1.6 88.2 1.6 96.32 27.36 96.32 27.36 107.2 ; - LAYER met1 ; - POLYGON 91.72 108.28 91.72 106.6 91.24 106.6 91.24 105.56 91.72 105.56 91.72 103.88 91.24 103.88 91.24 102.84 91.72 102.84 91.72 101.16 91.24 101.16 91.24 100.12 91.72 100.12 91.72 98.44 26.04 98.44 26.04 100.12 26.52 100.12 26.52 101.16 26.04 101.16 26.04 102.84 26.52 102.84 26.52 103.88 26.04 103.88 26.04 105.56 26.52 105.56 26.52 106.6 26.04 106.6 26.04 108.28 ; - POLYGON 117.48 97.4 117.48 95.72 117 95.72 117 94.68 117.48 94.68 117.48 93 117 93 117 91.96 117.48 91.96 117.48 90.28 117 90.28 117 89.24 117.48 89.24 117.48 87.56 117 87.56 117 86.52 117.48 86.52 117.48 84.84 117 84.84 117 83.8 117.48 83.8 117.48 82.12 117 82.12 117 81.08 117.48 81.08 117.48 79.4 117 79.4 117 78.36 117.48 78.36 117.48 76.68 117 76.68 117 75.64 117.48 75.64 117.48 73.96 117 73.96 117 72.92 117.48 72.92 117.48 71.24 117 71.24 117 70.2 117.48 70.2 117.48 68.52 117 68.52 117 67.48 117.48 67.48 117.48 65.8 117 65.8 117 64.76 117.48 64.76 117.48 63.08 117 63.08 117 62.04 117.48 62.04 117.48 60.36 117 60.36 117 59.32 117.48 59.32 117.48 57.64 117 57.64 117 56.6 117.48 56.6 117.48 54.92 117 54.92 117 53.88 117.48 53.88 117.48 52.2 117 52.2 117 51.16 117.48 51.16 117.48 49.48 117 49.48 117 48.44 117.48 48.44 117.48 46.76 117 46.76 117 45.72 117.48 45.72 117.48 44.04 117 44.04 117 43 117.48 43 117.48 41.32 117 41.32 117 40.28 117.48 40.28 117.48 38.6 117 38.6 117 37.56 117.48 37.56 117.48 35.88 117 35.88 117 34.84 117.48 34.84 117.48 33.16 117 33.16 117 32.12 117.48 32.12 117.48 30.44 117 30.44 117 29.4 117.48 29.4 117.48 27.72 117 27.72 117 26.68 117.48 26.68 117.48 25 117 25 117 23.96 117.48 23.96 117.48 22.28 117 22.28 117 21.24 117.48 21.24 117.48 19.56 117 19.56 117 18.52 117.48 18.52 117.48 16.84 117 16.84 117 15.8 117.48 15.8 117.48 14.12 117 14.12 117 13.08 117.48 13.08 117.48 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 0.76 81.08 0.76 82.12 0.28 82.12 0.28 83.8 0.76 83.8 0.76 84.84 0.28 84.84 0.28 86.52 0.76 86.52 0.76 87.56 0.28 87.56 0.28 89.24 0.76 89.24 0.76 90.28 0.28 90.28 0.28 91.96 0.76 91.96 0.76 93 0.28 93 0.28 94.68 0.76 94.68 0.76 95.72 0.28 95.72 0.28 97.4 ; - POLYGON 91.72 10.36 91.72 8.68 91.24 8.68 91.24 7.64 91.72 7.64 91.72 5.96 91.24 5.96 91.24 4.92 91.72 4.92 91.72 3.24 91.24 3.24 91.24 2.2 91.72 2.2 91.72 0.52 26.04 0.52 26.04 2.2 26.52 2.2 26.52 3.24 26.04 3.24 26.04 4.92 26.52 4.92 26.52 5.96 26.04 5.96 26.04 7.64 26.52 7.64 26.52 8.68 26.04 8.68 26.04 10.36 ; - LAYER li1 ; - POLYGON 91.83 108.63 91.83 97.75 117.59 97.75 117.59 11.05 91.83 11.05 91.83 0.17 25.93 0.17 25.93 11.05 0.17 11.05 0.17 97.75 25.93 97.75 25.93 108.63 ; - LAYER mcon ; - RECT 91.685 108.715 91.855 108.885 ; - RECT 91.225 108.715 91.395 108.885 ; - RECT 90.765 108.715 90.935 108.885 ; - RECT 90.305 108.715 90.475 108.885 ; - RECT 89.845 108.715 90.015 108.885 ; - RECT 89.385 108.715 89.555 108.885 ; - RECT 88.925 108.715 89.095 108.885 ; - RECT 88.465 108.715 88.635 108.885 ; - RECT 88.005 108.715 88.175 108.885 ; - RECT 87.545 108.715 87.715 108.885 ; - RECT 87.085 108.715 87.255 108.885 ; - RECT 86.625 108.715 86.795 108.885 ; - RECT 86.165 108.715 86.335 108.885 ; - RECT 85.705 108.715 85.875 108.885 ; - RECT 85.245 108.715 85.415 108.885 ; - RECT 84.785 108.715 84.955 108.885 ; - RECT 84.325 108.715 84.495 108.885 ; - RECT 83.865 108.715 84.035 108.885 ; - RECT 83.405 108.715 83.575 108.885 ; - RECT 82.945 108.715 83.115 108.885 ; - RECT 82.485 108.715 82.655 108.885 ; - RECT 82.025 108.715 82.195 108.885 ; - RECT 81.565 108.715 81.735 108.885 ; - RECT 81.105 108.715 81.275 108.885 ; - RECT 80.645 108.715 80.815 108.885 ; - RECT 80.185 108.715 80.355 108.885 ; - RECT 79.725 108.715 79.895 108.885 ; - RECT 79.265 108.715 79.435 108.885 ; - RECT 78.805 108.715 78.975 108.885 ; - RECT 78.345 108.715 78.515 108.885 ; - RECT 77.885 108.715 78.055 108.885 ; - RECT 77.425 108.715 77.595 108.885 ; - RECT 76.965 108.715 77.135 108.885 ; - RECT 76.505 108.715 76.675 108.885 ; - RECT 76.045 108.715 76.215 108.885 ; - RECT 75.585 108.715 75.755 108.885 ; - RECT 75.125 108.715 75.295 108.885 ; - RECT 74.665 108.715 74.835 108.885 ; - RECT 74.205 108.715 74.375 108.885 ; - RECT 73.745 108.715 73.915 108.885 ; - RECT 73.285 108.715 73.455 108.885 ; - RECT 72.825 108.715 72.995 108.885 ; - RECT 72.365 108.715 72.535 108.885 ; - RECT 71.905 108.715 72.075 108.885 ; - RECT 71.445 108.715 71.615 108.885 ; - RECT 70.985 108.715 71.155 108.885 ; - RECT 70.525 108.715 70.695 108.885 ; - RECT 70.065 108.715 70.235 108.885 ; - RECT 69.605 108.715 69.775 108.885 ; - RECT 69.145 108.715 69.315 108.885 ; - RECT 68.685 108.715 68.855 108.885 ; - RECT 68.225 108.715 68.395 108.885 ; - RECT 67.765 108.715 67.935 108.885 ; - RECT 67.305 108.715 67.475 108.885 ; - RECT 66.845 108.715 67.015 108.885 ; - RECT 66.385 108.715 66.555 108.885 ; - RECT 65.925 108.715 66.095 108.885 ; - RECT 65.465 108.715 65.635 108.885 ; - RECT 65.005 108.715 65.175 108.885 ; - RECT 64.545 108.715 64.715 108.885 ; - RECT 64.085 108.715 64.255 108.885 ; - RECT 63.625 108.715 63.795 108.885 ; - RECT 63.165 108.715 63.335 108.885 ; - RECT 62.705 108.715 62.875 108.885 ; - RECT 62.245 108.715 62.415 108.885 ; - RECT 61.785 108.715 61.955 108.885 ; - RECT 61.325 108.715 61.495 108.885 ; - RECT 60.865 108.715 61.035 108.885 ; - RECT 60.405 108.715 60.575 108.885 ; - RECT 59.945 108.715 60.115 108.885 ; - RECT 59.485 108.715 59.655 108.885 ; - RECT 59.025 108.715 59.195 108.885 ; - RECT 58.565 108.715 58.735 108.885 ; - RECT 58.105 108.715 58.275 108.885 ; - RECT 57.645 108.715 57.815 108.885 ; - RECT 57.185 108.715 57.355 108.885 ; - RECT 56.725 108.715 56.895 108.885 ; - RECT 56.265 108.715 56.435 108.885 ; - RECT 55.805 108.715 55.975 108.885 ; - RECT 55.345 108.715 55.515 108.885 ; - RECT 54.885 108.715 55.055 108.885 ; - RECT 54.425 108.715 54.595 108.885 ; - RECT 53.965 108.715 54.135 108.885 ; - RECT 53.505 108.715 53.675 108.885 ; - RECT 53.045 108.715 53.215 108.885 ; - RECT 52.585 108.715 52.755 108.885 ; - RECT 52.125 108.715 52.295 108.885 ; - RECT 51.665 108.715 51.835 108.885 ; - RECT 51.205 108.715 51.375 108.885 ; - RECT 50.745 108.715 50.915 108.885 ; - RECT 50.285 108.715 50.455 108.885 ; - RECT 49.825 108.715 49.995 108.885 ; - RECT 49.365 108.715 49.535 108.885 ; - RECT 48.905 108.715 49.075 108.885 ; - RECT 48.445 108.715 48.615 108.885 ; - RECT 47.985 108.715 48.155 108.885 ; - RECT 47.525 108.715 47.695 108.885 ; - RECT 47.065 108.715 47.235 108.885 ; - RECT 46.605 108.715 46.775 108.885 ; - RECT 46.145 108.715 46.315 108.885 ; - RECT 45.685 108.715 45.855 108.885 ; - RECT 45.225 108.715 45.395 108.885 ; - RECT 44.765 108.715 44.935 108.885 ; - RECT 44.305 108.715 44.475 108.885 ; - RECT 43.845 108.715 44.015 108.885 ; - RECT 43.385 108.715 43.555 108.885 ; - RECT 42.925 108.715 43.095 108.885 ; - RECT 42.465 108.715 42.635 108.885 ; - RECT 42.005 108.715 42.175 108.885 ; - RECT 41.545 108.715 41.715 108.885 ; - RECT 41.085 108.715 41.255 108.885 ; - RECT 40.625 108.715 40.795 108.885 ; - RECT 40.165 108.715 40.335 108.885 ; - RECT 39.705 108.715 39.875 108.885 ; - RECT 39.245 108.715 39.415 108.885 ; - RECT 38.785 108.715 38.955 108.885 ; - RECT 38.325 108.715 38.495 108.885 ; - RECT 37.865 108.715 38.035 108.885 ; - RECT 37.405 108.715 37.575 108.885 ; - RECT 36.945 108.715 37.115 108.885 ; - RECT 36.485 108.715 36.655 108.885 ; - RECT 36.025 108.715 36.195 108.885 ; - RECT 35.565 108.715 35.735 108.885 ; - RECT 35.105 108.715 35.275 108.885 ; - RECT 34.645 108.715 34.815 108.885 ; - RECT 34.185 108.715 34.355 108.885 ; - RECT 33.725 108.715 33.895 108.885 ; - RECT 33.265 108.715 33.435 108.885 ; - RECT 32.805 108.715 32.975 108.885 ; - RECT 32.345 108.715 32.515 108.885 ; - RECT 31.885 108.715 32.055 108.885 ; - RECT 31.425 108.715 31.595 108.885 ; - RECT 30.965 108.715 31.135 108.885 ; - RECT 30.505 108.715 30.675 108.885 ; - RECT 30.045 108.715 30.215 108.885 ; - RECT 29.585 108.715 29.755 108.885 ; - RECT 29.125 108.715 29.295 108.885 ; - RECT 28.665 108.715 28.835 108.885 ; - RECT 28.205 108.715 28.375 108.885 ; - RECT 27.745 108.715 27.915 108.885 ; - RECT 27.285 108.715 27.455 108.885 ; - RECT 26.825 108.715 26.995 108.885 ; - RECT 26.365 108.715 26.535 108.885 ; - RECT 25.905 108.715 26.075 108.885 ; - RECT 91.685 105.995 91.855 106.165 ; - RECT 91.225 105.995 91.395 106.165 ; - RECT 26.365 105.995 26.535 106.165 ; - RECT 25.905 105.995 26.075 106.165 ; - RECT 91.685 103.275 91.855 103.445 ; - RECT 91.225 103.275 91.395 103.445 ; - RECT 26.365 103.275 26.535 103.445 ; - RECT 25.905 103.275 26.075 103.445 ; - RECT 91.685 100.555 91.855 100.725 ; - RECT 91.225 100.555 91.395 100.725 ; - RECT 26.365 100.555 26.535 100.725 ; - RECT 25.905 100.555 26.075 100.725 ; - RECT 117.445 97.835 117.615 98.005 ; - RECT 116.985 97.835 117.155 98.005 ; - RECT 116.525 97.835 116.695 98.005 ; - RECT 116.065 97.835 116.235 98.005 ; - RECT 115.605 97.835 115.775 98.005 ; - RECT 115.145 97.835 115.315 98.005 ; - RECT 114.685 97.835 114.855 98.005 ; - RECT 114.225 97.835 114.395 98.005 ; - RECT 113.765 97.835 113.935 98.005 ; - RECT 113.305 97.835 113.475 98.005 ; - RECT 112.845 97.835 113.015 98.005 ; - RECT 112.385 97.835 112.555 98.005 ; - RECT 111.925 97.835 112.095 98.005 ; - RECT 111.465 97.835 111.635 98.005 ; - RECT 111.005 97.835 111.175 98.005 ; - RECT 110.545 97.835 110.715 98.005 ; - RECT 110.085 97.835 110.255 98.005 ; - RECT 109.625 97.835 109.795 98.005 ; - RECT 109.165 97.835 109.335 98.005 ; - RECT 108.705 97.835 108.875 98.005 ; - RECT 108.245 97.835 108.415 98.005 ; - RECT 107.785 97.835 107.955 98.005 ; - RECT 107.325 97.835 107.495 98.005 ; - RECT 106.865 97.835 107.035 98.005 ; - RECT 106.405 97.835 106.575 98.005 ; - RECT 105.945 97.835 106.115 98.005 ; - RECT 105.485 97.835 105.655 98.005 ; - RECT 105.025 97.835 105.195 98.005 ; - RECT 104.565 97.835 104.735 98.005 ; - RECT 104.105 97.835 104.275 98.005 ; - RECT 103.645 97.835 103.815 98.005 ; - RECT 103.185 97.835 103.355 98.005 ; - RECT 102.725 97.835 102.895 98.005 ; - RECT 102.265 97.835 102.435 98.005 ; - RECT 101.805 97.835 101.975 98.005 ; - RECT 101.345 97.835 101.515 98.005 ; - RECT 100.885 97.835 101.055 98.005 ; - RECT 100.425 97.835 100.595 98.005 ; - RECT 99.965 97.835 100.135 98.005 ; - RECT 99.505 97.835 99.675 98.005 ; - RECT 99.045 97.835 99.215 98.005 ; - RECT 98.585 97.835 98.755 98.005 ; - RECT 98.125 97.835 98.295 98.005 ; - RECT 97.665 97.835 97.835 98.005 ; - RECT 97.205 97.835 97.375 98.005 ; - RECT 96.745 97.835 96.915 98.005 ; - RECT 96.285 97.835 96.455 98.005 ; - RECT 95.825 97.835 95.995 98.005 ; - RECT 95.365 97.835 95.535 98.005 ; - RECT 94.905 97.835 95.075 98.005 ; - RECT 94.445 97.835 94.615 98.005 ; - RECT 93.985 97.835 94.155 98.005 ; - RECT 93.525 97.835 93.695 98.005 ; - RECT 93.065 97.835 93.235 98.005 ; - RECT 92.605 97.835 92.775 98.005 ; - RECT 92.145 97.835 92.315 98.005 ; - RECT 91.685 97.835 91.855 98.005 ; - RECT 91.225 97.835 91.395 98.005 ; - RECT 90.765 97.835 90.935 98.005 ; - RECT 90.305 97.835 90.475 98.005 ; - RECT 89.845 97.835 90.015 98.005 ; - RECT 89.385 97.835 89.555 98.005 ; - RECT 88.925 97.835 89.095 98.005 ; - RECT 88.465 97.835 88.635 98.005 ; - RECT 88.005 97.835 88.175 98.005 ; - RECT 87.545 97.835 87.715 98.005 ; - RECT 87.085 97.835 87.255 98.005 ; - RECT 86.625 97.835 86.795 98.005 ; - RECT 86.165 97.835 86.335 98.005 ; - RECT 85.705 97.835 85.875 98.005 ; - RECT 85.245 97.835 85.415 98.005 ; - RECT 84.785 97.835 84.955 98.005 ; - RECT 84.325 97.835 84.495 98.005 ; - RECT 83.865 97.835 84.035 98.005 ; - RECT 83.405 97.835 83.575 98.005 ; - RECT 82.945 97.835 83.115 98.005 ; - RECT 82.485 97.835 82.655 98.005 ; - RECT 82.025 97.835 82.195 98.005 ; - RECT 81.565 97.835 81.735 98.005 ; - RECT 81.105 97.835 81.275 98.005 ; - RECT 80.645 97.835 80.815 98.005 ; - RECT 80.185 97.835 80.355 98.005 ; - RECT 79.725 97.835 79.895 98.005 ; - RECT 79.265 97.835 79.435 98.005 ; - RECT 78.805 97.835 78.975 98.005 ; - RECT 78.345 97.835 78.515 98.005 ; - RECT 77.885 97.835 78.055 98.005 ; - RECT 77.425 97.835 77.595 98.005 ; - RECT 76.965 97.835 77.135 98.005 ; - RECT 76.505 97.835 76.675 98.005 ; - RECT 76.045 97.835 76.215 98.005 ; - RECT 75.585 97.835 75.755 98.005 ; - RECT 75.125 97.835 75.295 98.005 ; - RECT 74.665 97.835 74.835 98.005 ; - RECT 74.205 97.835 74.375 98.005 ; - RECT 73.745 97.835 73.915 98.005 ; - RECT 73.285 97.835 73.455 98.005 ; - RECT 72.825 97.835 72.995 98.005 ; - RECT 72.365 97.835 72.535 98.005 ; - RECT 71.905 97.835 72.075 98.005 ; - RECT 71.445 97.835 71.615 98.005 ; - RECT 70.985 97.835 71.155 98.005 ; - RECT 70.525 97.835 70.695 98.005 ; - RECT 70.065 97.835 70.235 98.005 ; - RECT 69.605 97.835 69.775 98.005 ; - RECT 69.145 97.835 69.315 98.005 ; - RECT 68.685 97.835 68.855 98.005 ; - RECT 68.225 97.835 68.395 98.005 ; - RECT 67.765 97.835 67.935 98.005 ; - RECT 67.305 97.835 67.475 98.005 ; - RECT 66.845 97.835 67.015 98.005 ; - RECT 66.385 97.835 66.555 98.005 ; - RECT 65.925 97.835 66.095 98.005 ; - RECT 65.465 97.835 65.635 98.005 ; - RECT 65.005 97.835 65.175 98.005 ; - RECT 64.545 97.835 64.715 98.005 ; - RECT 64.085 97.835 64.255 98.005 ; - RECT 63.625 97.835 63.795 98.005 ; - RECT 63.165 97.835 63.335 98.005 ; - RECT 62.705 97.835 62.875 98.005 ; - RECT 62.245 97.835 62.415 98.005 ; - RECT 61.785 97.835 61.955 98.005 ; - RECT 61.325 97.835 61.495 98.005 ; - RECT 60.865 97.835 61.035 98.005 ; - RECT 60.405 97.835 60.575 98.005 ; - RECT 59.945 97.835 60.115 98.005 ; - RECT 59.485 97.835 59.655 98.005 ; - RECT 59.025 97.835 59.195 98.005 ; - RECT 58.565 97.835 58.735 98.005 ; - RECT 58.105 97.835 58.275 98.005 ; - RECT 57.645 97.835 57.815 98.005 ; - RECT 57.185 97.835 57.355 98.005 ; - RECT 56.725 97.835 56.895 98.005 ; - RECT 56.265 97.835 56.435 98.005 ; - RECT 55.805 97.835 55.975 98.005 ; - RECT 55.345 97.835 55.515 98.005 ; - RECT 54.885 97.835 55.055 98.005 ; - RECT 54.425 97.835 54.595 98.005 ; - RECT 53.965 97.835 54.135 98.005 ; - RECT 53.505 97.835 53.675 98.005 ; - RECT 53.045 97.835 53.215 98.005 ; - RECT 52.585 97.835 52.755 98.005 ; - RECT 52.125 97.835 52.295 98.005 ; - RECT 51.665 97.835 51.835 98.005 ; - RECT 51.205 97.835 51.375 98.005 ; - RECT 50.745 97.835 50.915 98.005 ; - RECT 50.285 97.835 50.455 98.005 ; - RECT 49.825 97.835 49.995 98.005 ; - RECT 49.365 97.835 49.535 98.005 ; - RECT 48.905 97.835 49.075 98.005 ; - RECT 48.445 97.835 48.615 98.005 ; - RECT 47.985 97.835 48.155 98.005 ; - RECT 47.525 97.835 47.695 98.005 ; - RECT 47.065 97.835 47.235 98.005 ; - RECT 46.605 97.835 46.775 98.005 ; - RECT 46.145 97.835 46.315 98.005 ; - RECT 45.685 97.835 45.855 98.005 ; - RECT 45.225 97.835 45.395 98.005 ; - RECT 44.765 97.835 44.935 98.005 ; - RECT 44.305 97.835 44.475 98.005 ; - RECT 43.845 97.835 44.015 98.005 ; - RECT 43.385 97.835 43.555 98.005 ; - RECT 42.925 97.835 43.095 98.005 ; - RECT 42.465 97.835 42.635 98.005 ; - RECT 42.005 97.835 42.175 98.005 ; - RECT 41.545 97.835 41.715 98.005 ; - RECT 41.085 97.835 41.255 98.005 ; - RECT 40.625 97.835 40.795 98.005 ; - RECT 40.165 97.835 40.335 98.005 ; - RECT 39.705 97.835 39.875 98.005 ; - RECT 39.245 97.835 39.415 98.005 ; - RECT 38.785 97.835 38.955 98.005 ; - RECT 38.325 97.835 38.495 98.005 ; - RECT 37.865 97.835 38.035 98.005 ; - RECT 37.405 97.835 37.575 98.005 ; - RECT 36.945 97.835 37.115 98.005 ; - RECT 36.485 97.835 36.655 98.005 ; - RECT 36.025 97.835 36.195 98.005 ; - RECT 35.565 97.835 35.735 98.005 ; - RECT 35.105 97.835 35.275 98.005 ; - RECT 34.645 97.835 34.815 98.005 ; - RECT 34.185 97.835 34.355 98.005 ; - RECT 33.725 97.835 33.895 98.005 ; - RECT 33.265 97.835 33.435 98.005 ; - RECT 32.805 97.835 32.975 98.005 ; - RECT 32.345 97.835 32.515 98.005 ; - RECT 31.885 97.835 32.055 98.005 ; - RECT 31.425 97.835 31.595 98.005 ; - RECT 30.965 97.835 31.135 98.005 ; - RECT 30.505 97.835 30.675 98.005 ; - RECT 30.045 97.835 30.215 98.005 ; - RECT 29.585 97.835 29.755 98.005 ; - RECT 29.125 97.835 29.295 98.005 ; - RECT 28.665 97.835 28.835 98.005 ; - RECT 28.205 97.835 28.375 98.005 ; - RECT 27.745 97.835 27.915 98.005 ; - RECT 27.285 97.835 27.455 98.005 ; - RECT 26.825 97.835 26.995 98.005 ; - RECT 26.365 97.835 26.535 98.005 ; - RECT 25.905 97.835 26.075 98.005 ; - RECT 25.445 97.835 25.615 98.005 ; - RECT 24.985 97.835 25.155 98.005 ; - RECT 24.525 97.835 24.695 98.005 ; - RECT 24.065 97.835 24.235 98.005 ; - RECT 23.605 97.835 23.775 98.005 ; - RECT 23.145 97.835 23.315 98.005 ; - RECT 22.685 97.835 22.855 98.005 ; - RECT 22.225 97.835 22.395 98.005 ; - RECT 21.765 97.835 21.935 98.005 ; - RECT 21.305 97.835 21.475 98.005 ; - RECT 20.845 97.835 21.015 98.005 ; - RECT 20.385 97.835 20.555 98.005 ; - RECT 19.925 97.835 20.095 98.005 ; - RECT 19.465 97.835 19.635 98.005 ; - RECT 19.005 97.835 19.175 98.005 ; - RECT 18.545 97.835 18.715 98.005 ; - RECT 18.085 97.835 18.255 98.005 ; - RECT 17.625 97.835 17.795 98.005 ; - RECT 17.165 97.835 17.335 98.005 ; - RECT 16.705 97.835 16.875 98.005 ; - RECT 16.245 97.835 16.415 98.005 ; - RECT 15.785 97.835 15.955 98.005 ; - RECT 15.325 97.835 15.495 98.005 ; - RECT 14.865 97.835 15.035 98.005 ; - RECT 14.405 97.835 14.575 98.005 ; - RECT 13.945 97.835 14.115 98.005 ; - RECT 13.485 97.835 13.655 98.005 ; - RECT 13.025 97.835 13.195 98.005 ; - RECT 12.565 97.835 12.735 98.005 ; - RECT 12.105 97.835 12.275 98.005 ; - RECT 11.645 97.835 11.815 98.005 ; - RECT 11.185 97.835 11.355 98.005 ; - RECT 10.725 97.835 10.895 98.005 ; - RECT 10.265 97.835 10.435 98.005 ; - RECT 9.805 97.835 9.975 98.005 ; - RECT 9.345 97.835 9.515 98.005 ; - RECT 8.885 97.835 9.055 98.005 ; - RECT 8.425 97.835 8.595 98.005 ; - RECT 7.965 97.835 8.135 98.005 ; - RECT 7.505 97.835 7.675 98.005 ; - RECT 7.045 97.835 7.215 98.005 ; - RECT 6.585 97.835 6.755 98.005 ; - RECT 6.125 97.835 6.295 98.005 ; - RECT 5.665 97.835 5.835 98.005 ; - RECT 5.205 97.835 5.375 98.005 ; - RECT 4.745 97.835 4.915 98.005 ; - RECT 4.285 97.835 4.455 98.005 ; - RECT 3.825 97.835 3.995 98.005 ; - RECT 3.365 97.835 3.535 98.005 ; - RECT 2.905 97.835 3.075 98.005 ; - RECT 2.445 97.835 2.615 98.005 ; - RECT 1.985 97.835 2.155 98.005 ; - RECT 1.525 97.835 1.695 98.005 ; - RECT 1.065 97.835 1.235 98.005 ; - RECT 0.605 97.835 0.775 98.005 ; - RECT 0.145 97.835 0.315 98.005 ; - RECT 117.445 95.115 117.615 95.285 ; - RECT 116.985 95.115 117.155 95.285 ; - RECT 0.605 95.115 0.775 95.285 ; - RECT 0.145 95.115 0.315 95.285 ; - RECT 117.445 92.395 117.615 92.565 ; - RECT 116.985 92.395 117.155 92.565 ; - RECT 0.605 92.395 0.775 92.565 ; - RECT 0.145 92.395 0.315 92.565 ; - RECT 117.445 89.675 117.615 89.845 ; - RECT 116.985 89.675 117.155 89.845 ; - RECT 0.605 89.675 0.775 89.845 ; - RECT 0.145 89.675 0.315 89.845 ; - RECT 117.445 86.955 117.615 87.125 ; - RECT 116.985 86.955 117.155 87.125 ; - RECT 0.605 86.955 0.775 87.125 ; - RECT 0.145 86.955 0.315 87.125 ; - RECT 117.445 84.235 117.615 84.405 ; - RECT 116.985 84.235 117.155 84.405 ; - RECT 0.605 84.235 0.775 84.405 ; - RECT 0.145 84.235 0.315 84.405 ; - RECT 117.445 81.515 117.615 81.685 ; - RECT 116.985 81.515 117.155 81.685 ; - RECT 0.605 81.515 0.775 81.685 ; - RECT 0.145 81.515 0.315 81.685 ; - RECT 117.445 78.795 117.615 78.965 ; - RECT 116.985 78.795 117.155 78.965 ; - RECT 0.605 78.795 0.775 78.965 ; - RECT 0.145 78.795 0.315 78.965 ; - RECT 117.445 76.075 117.615 76.245 ; - RECT 116.985 76.075 117.155 76.245 ; - RECT 0.605 76.075 0.775 76.245 ; - RECT 0.145 76.075 0.315 76.245 ; - RECT 117.445 73.355 117.615 73.525 ; - RECT 116.985 73.355 117.155 73.525 ; - RECT 0.605 73.355 0.775 73.525 ; - RECT 0.145 73.355 0.315 73.525 ; - RECT 117.445 70.635 117.615 70.805 ; - RECT 116.985 70.635 117.155 70.805 ; - RECT 0.605 70.635 0.775 70.805 ; - RECT 0.145 70.635 0.315 70.805 ; - RECT 117.445 67.915 117.615 68.085 ; - RECT 116.985 67.915 117.155 68.085 ; - RECT 0.605 67.915 0.775 68.085 ; - RECT 0.145 67.915 0.315 68.085 ; - RECT 117.445 65.195 117.615 65.365 ; - RECT 116.985 65.195 117.155 65.365 ; - RECT 0.605 65.195 0.775 65.365 ; - RECT 0.145 65.195 0.315 65.365 ; - RECT 117.445 62.475 117.615 62.645 ; - RECT 116.985 62.475 117.155 62.645 ; - RECT 0.605 62.475 0.775 62.645 ; - RECT 0.145 62.475 0.315 62.645 ; - RECT 117.445 59.755 117.615 59.925 ; - RECT 116.985 59.755 117.155 59.925 ; - RECT 0.605 59.755 0.775 59.925 ; - RECT 0.145 59.755 0.315 59.925 ; - RECT 117.445 57.035 117.615 57.205 ; - RECT 116.985 57.035 117.155 57.205 ; - RECT 0.605 57.035 0.775 57.205 ; - RECT 0.145 57.035 0.315 57.205 ; - RECT 117.445 54.315 117.615 54.485 ; - RECT 116.985 54.315 117.155 54.485 ; - RECT 0.605 54.315 0.775 54.485 ; - RECT 0.145 54.315 0.315 54.485 ; - RECT 117.445 51.595 117.615 51.765 ; - RECT 116.985 51.595 117.155 51.765 ; - RECT 0.605 51.595 0.775 51.765 ; - RECT 0.145 51.595 0.315 51.765 ; - RECT 117.445 48.875 117.615 49.045 ; - RECT 116.985 48.875 117.155 49.045 ; - RECT 0.605 48.875 0.775 49.045 ; - RECT 0.145 48.875 0.315 49.045 ; - RECT 117.445 46.155 117.615 46.325 ; - RECT 116.985 46.155 117.155 46.325 ; - RECT 0.605 46.155 0.775 46.325 ; - RECT 0.145 46.155 0.315 46.325 ; - RECT 117.445 43.435 117.615 43.605 ; - RECT 116.985 43.435 117.155 43.605 ; - RECT 0.605 43.435 0.775 43.605 ; - RECT 0.145 43.435 0.315 43.605 ; - RECT 117.445 40.715 117.615 40.885 ; - RECT 116.985 40.715 117.155 40.885 ; - RECT 0.605 40.715 0.775 40.885 ; - RECT 0.145 40.715 0.315 40.885 ; - RECT 117.445 37.995 117.615 38.165 ; - RECT 116.985 37.995 117.155 38.165 ; - RECT 0.605 37.995 0.775 38.165 ; - RECT 0.145 37.995 0.315 38.165 ; - RECT 117.445 35.275 117.615 35.445 ; - RECT 116.985 35.275 117.155 35.445 ; - RECT 0.605 35.275 0.775 35.445 ; - RECT 0.145 35.275 0.315 35.445 ; - RECT 117.445 32.555 117.615 32.725 ; - RECT 116.985 32.555 117.155 32.725 ; - RECT 0.605 32.555 0.775 32.725 ; - RECT 0.145 32.555 0.315 32.725 ; - RECT 117.445 29.835 117.615 30.005 ; - RECT 116.985 29.835 117.155 30.005 ; - RECT 0.605 29.835 0.775 30.005 ; - RECT 0.145 29.835 0.315 30.005 ; - RECT 117.445 27.115 117.615 27.285 ; - RECT 116.985 27.115 117.155 27.285 ; - RECT 0.605 27.115 0.775 27.285 ; - RECT 0.145 27.115 0.315 27.285 ; - RECT 117.445 24.395 117.615 24.565 ; - RECT 116.985 24.395 117.155 24.565 ; - RECT 0.605 24.395 0.775 24.565 ; - RECT 0.145 24.395 0.315 24.565 ; - RECT 117.445 21.675 117.615 21.845 ; - RECT 116.985 21.675 117.155 21.845 ; - RECT 0.605 21.675 0.775 21.845 ; - RECT 0.145 21.675 0.315 21.845 ; - RECT 117.445 18.955 117.615 19.125 ; - RECT 116.985 18.955 117.155 19.125 ; - RECT 0.605 18.955 0.775 19.125 ; - RECT 0.145 18.955 0.315 19.125 ; - RECT 117.445 16.235 117.615 16.405 ; - RECT 116.985 16.235 117.155 16.405 ; - RECT 0.605 16.235 0.775 16.405 ; - RECT 0.145 16.235 0.315 16.405 ; - RECT 117.445 13.515 117.615 13.685 ; - RECT 116.985 13.515 117.155 13.685 ; - RECT 0.605 13.515 0.775 13.685 ; - RECT 0.145 13.515 0.315 13.685 ; - RECT 117.445 10.795 117.615 10.965 ; - RECT 116.985 10.795 117.155 10.965 ; - RECT 116.525 10.795 116.695 10.965 ; - RECT 116.065 10.795 116.235 10.965 ; - RECT 115.605 10.795 115.775 10.965 ; - RECT 115.145 10.795 115.315 10.965 ; - RECT 114.685 10.795 114.855 10.965 ; - RECT 114.225 10.795 114.395 10.965 ; - RECT 113.765 10.795 113.935 10.965 ; - RECT 113.305 10.795 113.475 10.965 ; - RECT 112.845 10.795 113.015 10.965 ; - RECT 112.385 10.795 112.555 10.965 ; - RECT 111.925 10.795 112.095 10.965 ; - RECT 111.465 10.795 111.635 10.965 ; - RECT 111.005 10.795 111.175 10.965 ; - RECT 110.545 10.795 110.715 10.965 ; - RECT 110.085 10.795 110.255 10.965 ; - RECT 109.625 10.795 109.795 10.965 ; - RECT 109.165 10.795 109.335 10.965 ; - RECT 108.705 10.795 108.875 10.965 ; - RECT 108.245 10.795 108.415 10.965 ; - RECT 107.785 10.795 107.955 10.965 ; - RECT 107.325 10.795 107.495 10.965 ; - RECT 106.865 10.795 107.035 10.965 ; - RECT 106.405 10.795 106.575 10.965 ; - RECT 105.945 10.795 106.115 10.965 ; - RECT 105.485 10.795 105.655 10.965 ; - RECT 105.025 10.795 105.195 10.965 ; - RECT 104.565 10.795 104.735 10.965 ; - RECT 104.105 10.795 104.275 10.965 ; - RECT 103.645 10.795 103.815 10.965 ; - RECT 103.185 10.795 103.355 10.965 ; - RECT 102.725 10.795 102.895 10.965 ; - RECT 102.265 10.795 102.435 10.965 ; - RECT 101.805 10.795 101.975 10.965 ; - RECT 101.345 10.795 101.515 10.965 ; - RECT 100.885 10.795 101.055 10.965 ; - RECT 100.425 10.795 100.595 10.965 ; - RECT 99.965 10.795 100.135 10.965 ; - RECT 99.505 10.795 99.675 10.965 ; - RECT 99.045 10.795 99.215 10.965 ; - RECT 98.585 10.795 98.755 10.965 ; - RECT 98.125 10.795 98.295 10.965 ; - RECT 97.665 10.795 97.835 10.965 ; - RECT 97.205 10.795 97.375 10.965 ; - RECT 96.745 10.795 96.915 10.965 ; - RECT 96.285 10.795 96.455 10.965 ; - RECT 95.825 10.795 95.995 10.965 ; - RECT 95.365 10.795 95.535 10.965 ; - RECT 94.905 10.795 95.075 10.965 ; - RECT 94.445 10.795 94.615 10.965 ; - RECT 93.985 10.795 94.155 10.965 ; - RECT 93.525 10.795 93.695 10.965 ; - RECT 93.065 10.795 93.235 10.965 ; - RECT 92.605 10.795 92.775 10.965 ; - RECT 92.145 10.795 92.315 10.965 ; - RECT 91.685 10.795 91.855 10.965 ; - RECT 91.225 10.795 91.395 10.965 ; - RECT 90.765 10.795 90.935 10.965 ; - RECT 90.305 10.795 90.475 10.965 ; - RECT 89.845 10.795 90.015 10.965 ; - RECT 89.385 10.795 89.555 10.965 ; - RECT 88.925 10.795 89.095 10.965 ; - RECT 88.465 10.795 88.635 10.965 ; - RECT 88.005 10.795 88.175 10.965 ; - RECT 87.545 10.795 87.715 10.965 ; - RECT 87.085 10.795 87.255 10.965 ; - RECT 86.625 10.795 86.795 10.965 ; - RECT 86.165 10.795 86.335 10.965 ; - RECT 85.705 10.795 85.875 10.965 ; - RECT 85.245 10.795 85.415 10.965 ; - RECT 84.785 10.795 84.955 10.965 ; - RECT 84.325 10.795 84.495 10.965 ; - RECT 83.865 10.795 84.035 10.965 ; - RECT 83.405 10.795 83.575 10.965 ; - RECT 82.945 10.795 83.115 10.965 ; - RECT 82.485 10.795 82.655 10.965 ; - RECT 82.025 10.795 82.195 10.965 ; - RECT 81.565 10.795 81.735 10.965 ; - RECT 81.105 10.795 81.275 10.965 ; - RECT 80.645 10.795 80.815 10.965 ; - RECT 80.185 10.795 80.355 10.965 ; - RECT 79.725 10.795 79.895 10.965 ; - RECT 79.265 10.795 79.435 10.965 ; - RECT 78.805 10.795 78.975 10.965 ; - RECT 78.345 10.795 78.515 10.965 ; - RECT 77.885 10.795 78.055 10.965 ; - RECT 77.425 10.795 77.595 10.965 ; - RECT 76.965 10.795 77.135 10.965 ; - RECT 76.505 10.795 76.675 10.965 ; - RECT 76.045 10.795 76.215 10.965 ; - RECT 75.585 10.795 75.755 10.965 ; - RECT 75.125 10.795 75.295 10.965 ; - RECT 74.665 10.795 74.835 10.965 ; - RECT 74.205 10.795 74.375 10.965 ; - RECT 73.745 10.795 73.915 10.965 ; - RECT 73.285 10.795 73.455 10.965 ; - RECT 72.825 10.795 72.995 10.965 ; - RECT 72.365 10.795 72.535 10.965 ; - RECT 71.905 10.795 72.075 10.965 ; - RECT 71.445 10.795 71.615 10.965 ; - RECT 70.985 10.795 71.155 10.965 ; - RECT 70.525 10.795 70.695 10.965 ; - RECT 70.065 10.795 70.235 10.965 ; - RECT 69.605 10.795 69.775 10.965 ; - RECT 69.145 10.795 69.315 10.965 ; - RECT 68.685 10.795 68.855 10.965 ; - RECT 68.225 10.795 68.395 10.965 ; - RECT 67.765 10.795 67.935 10.965 ; - RECT 67.305 10.795 67.475 10.965 ; - RECT 66.845 10.795 67.015 10.965 ; - RECT 66.385 10.795 66.555 10.965 ; - RECT 65.925 10.795 66.095 10.965 ; - RECT 65.465 10.795 65.635 10.965 ; - RECT 65.005 10.795 65.175 10.965 ; - RECT 64.545 10.795 64.715 10.965 ; - RECT 64.085 10.795 64.255 10.965 ; - RECT 63.625 10.795 63.795 10.965 ; - RECT 63.165 10.795 63.335 10.965 ; - RECT 62.705 10.795 62.875 10.965 ; - RECT 62.245 10.795 62.415 10.965 ; - RECT 61.785 10.795 61.955 10.965 ; - RECT 61.325 10.795 61.495 10.965 ; - RECT 60.865 10.795 61.035 10.965 ; - RECT 60.405 10.795 60.575 10.965 ; - RECT 59.945 10.795 60.115 10.965 ; - RECT 59.485 10.795 59.655 10.965 ; - RECT 59.025 10.795 59.195 10.965 ; - RECT 58.565 10.795 58.735 10.965 ; - RECT 58.105 10.795 58.275 10.965 ; - RECT 57.645 10.795 57.815 10.965 ; - RECT 57.185 10.795 57.355 10.965 ; - RECT 56.725 10.795 56.895 10.965 ; - RECT 56.265 10.795 56.435 10.965 ; - RECT 55.805 10.795 55.975 10.965 ; - RECT 55.345 10.795 55.515 10.965 ; - RECT 54.885 10.795 55.055 10.965 ; - RECT 54.425 10.795 54.595 10.965 ; - RECT 53.965 10.795 54.135 10.965 ; - RECT 53.505 10.795 53.675 10.965 ; - RECT 53.045 10.795 53.215 10.965 ; - RECT 52.585 10.795 52.755 10.965 ; - RECT 52.125 10.795 52.295 10.965 ; - RECT 51.665 10.795 51.835 10.965 ; - RECT 51.205 10.795 51.375 10.965 ; - RECT 50.745 10.795 50.915 10.965 ; - RECT 50.285 10.795 50.455 10.965 ; - RECT 49.825 10.795 49.995 10.965 ; - RECT 49.365 10.795 49.535 10.965 ; - RECT 48.905 10.795 49.075 10.965 ; - RECT 48.445 10.795 48.615 10.965 ; - RECT 47.985 10.795 48.155 10.965 ; - RECT 47.525 10.795 47.695 10.965 ; - RECT 47.065 10.795 47.235 10.965 ; - RECT 46.605 10.795 46.775 10.965 ; - RECT 46.145 10.795 46.315 10.965 ; - RECT 45.685 10.795 45.855 10.965 ; - RECT 45.225 10.795 45.395 10.965 ; - RECT 44.765 10.795 44.935 10.965 ; - RECT 44.305 10.795 44.475 10.965 ; - RECT 43.845 10.795 44.015 10.965 ; - RECT 43.385 10.795 43.555 10.965 ; - RECT 42.925 10.795 43.095 10.965 ; - RECT 42.465 10.795 42.635 10.965 ; - RECT 42.005 10.795 42.175 10.965 ; - RECT 41.545 10.795 41.715 10.965 ; - RECT 41.085 10.795 41.255 10.965 ; - RECT 40.625 10.795 40.795 10.965 ; - RECT 40.165 10.795 40.335 10.965 ; - RECT 39.705 10.795 39.875 10.965 ; - RECT 39.245 10.795 39.415 10.965 ; - RECT 38.785 10.795 38.955 10.965 ; - RECT 38.325 10.795 38.495 10.965 ; - RECT 37.865 10.795 38.035 10.965 ; - RECT 37.405 10.795 37.575 10.965 ; - RECT 36.945 10.795 37.115 10.965 ; - RECT 36.485 10.795 36.655 10.965 ; - RECT 36.025 10.795 36.195 10.965 ; - RECT 35.565 10.795 35.735 10.965 ; - RECT 35.105 10.795 35.275 10.965 ; - RECT 34.645 10.795 34.815 10.965 ; - RECT 34.185 10.795 34.355 10.965 ; - RECT 33.725 10.795 33.895 10.965 ; - RECT 33.265 10.795 33.435 10.965 ; - RECT 32.805 10.795 32.975 10.965 ; - RECT 32.345 10.795 32.515 10.965 ; - RECT 31.885 10.795 32.055 10.965 ; - RECT 31.425 10.795 31.595 10.965 ; - RECT 30.965 10.795 31.135 10.965 ; - RECT 30.505 10.795 30.675 10.965 ; - RECT 30.045 10.795 30.215 10.965 ; - RECT 29.585 10.795 29.755 10.965 ; - RECT 29.125 10.795 29.295 10.965 ; - RECT 28.665 10.795 28.835 10.965 ; - RECT 28.205 10.795 28.375 10.965 ; - RECT 27.745 10.795 27.915 10.965 ; - RECT 27.285 10.795 27.455 10.965 ; - RECT 26.825 10.795 26.995 10.965 ; - RECT 26.365 10.795 26.535 10.965 ; - RECT 25.905 10.795 26.075 10.965 ; - RECT 25.445 10.795 25.615 10.965 ; - RECT 24.985 10.795 25.155 10.965 ; - RECT 24.525 10.795 24.695 10.965 ; - RECT 24.065 10.795 24.235 10.965 ; - RECT 23.605 10.795 23.775 10.965 ; - RECT 23.145 10.795 23.315 10.965 ; - RECT 22.685 10.795 22.855 10.965 ; - RECT 22.225 10.795 22.395 10.965 ; - RECT 21.765 10.795 21.935 10.965 ; - RECT 21.305 10.795 21.475 10.965 ; - RECT 20.845 10.795 21.015 10.965 ; - RECT 20.385 10.795 20.555 10.965 ; - RECT 19.925 10.795 20.095 10.965 ; - RECT 19.465 10.795 19.635 10.965 ; - RECT 19.005 10.795 19.175 10.965 ; - RECT 18.545 10.795 18.715 10.965 ; - RECT 18.085 10.795 18.255 10.965 ; - RECT 17.625 10.795 17.795 10.965 ; - RECT 17.165 10.795 17.335 10.965 ; - RECT 16.705 10.795 16.875 10.965 ; - RECT 16.245 10.795 16.415 10.965 ; - RECT 15.785 10.795 15.955 10.965 ; - RECT 15.325 10.795 15.495 10.965 ; - RECT 14.865 10.795 15.035 10.965 ; - RECT 14.405 10.795 14.575 10.965 ; - RECT 13.945 10.795 14.115 10.965 ; - RECT 13.485 10.795 13.655 10.965 ; - RECT 13.025 10.795 13.195 10.965 ; - RECT 12.565 10.795 12.735 10.965 ; - RECT 12.105 10.795 12.275 10.965 ; - RECT 11.645 10.795 11.815 10.965 ; - RECT 11.185 10.795 11.355 10.965 ; - RECT 10.725 10.795 10.895 10.965 ; - RECT 10.265 10.795 10.435 10.965 ; - RECT 9.805 10.795 9.975 10.965 ; - RECT 9.345 10.795 9.515 10.965 ; - RECT 8.885 10.795 9.055 10.965 ; - RECT 8.425 10.795 8.595 10.965 ; - RECT 7.965 10.795 8.135 10.965 ; - RECT 7.505 10.795 7.675 10.965 ; - RECT 7.045 10.795 7.215 10.965 ; - RECT 6.585 10.795 6.755 10.965 ; - RECT 6.125 10.795 6.295 10.965 ; - RECT 5.665 10.795 5.835 10.965 ; - RECT 5.205 10.795 5.375 10.965 ; - RECT 4.745 10.795 4.915 10.965 ; - RECT 4.285 10.795 4.455 10.965 ; - RECT 3.825 10.795 3.995 10.965 ; - RECT 3.365 10.795 3.535 10.965 ; - RECT 2.905 10.795 3.075 10.965 ; - RECT 2.445 10.795 2.615 10.965 ; - RECT 1.985 10.795 2.155 10.965 ; - RECT 1.525 10.795 1.695 10.965 ; - RECT 1.065 10.795 1.235 10.965 ; - RECT 0.605 10.795 0.775 10.965 ; - RECT 0.145 10.795 0.315 10.965 ; - RECT 91.685 8.075 91.855 8.245 ; - RECT 91.225 8.075 91.395 8.245 ; - RECT 26.365 8.075 26.535 8.245 ; - RECT 25.905 8.075 26.075 8.245 ; - RECT 91.685 5.355 91.855 5.525 ; - RECT 91.225 5.355 91.395 5.525 ; - RECT 26.365 5.355 26.535 5.525 ; - RECT 25.905 5.355 26.075 5.525 ; - RECT 91.685 2.635 91.855 2.805 ; - RECT 91.225 2.635 91.395 2.805 ; - RECT 26.365 2.635 26.535 2.805 ; - RECT 25.905 2.635 26.075 2.805 ; - RECT 91.685 -0.085 91.855 0.085 ; - RECT 91.225 -0.085 91.395 0.085 ; - RECT 90.765 -0.085 90.935 0.085 ; - RECT 90.305 -0.085 90.475 0.085 ; - RECT 89.845 -0.085 90.015 0.085 ; - RECT 89.385 -0.085 89.555 0.085 ; - RECT 88.925 -0.085 89.095 0.085 ; - RECT 88.465 -0.085 88.635 0.085 ; - RECT 88.005 -0.085 88.175 0.085 ; - RECT 87.545 -0.085 87.715 0.085 ; - RECT 87.085 -0.085 87.255 0.085 ; - RECT 86.625 -0.085 86.795 0.085 ; - RECT 86.165 -0.085 86.335 0.085 ; - RECT 85.705 -0.085 85.875 0.085 ; - RECT 85.245 -0.085 85.415 0.085 ; - RECT 84.785 -0.085 84.955 0.085 ; - RECT 84.325 -0.085 84.495 0.085 ; - RECT 83.865 -0.085 84.035 0.085 ; - RECT 83.405 -0.085 83.575 0.085 ; - RECT 82.945 -0.085 83.115 0.085 ; - RECT 82.485 -0.085 82.655 0.085 ; - RECT 82.025 -0.085 82.195 0.085 ; - RECT 81.565 -0.085 81.735 0.085 ; - RECT 81.105 -0.085 81.275 0.085 ; - RECT 80.645 -0.085 80.815 0.085 ; - RECT 80.185 -0.085 80.355 0.085 ; - RECT 79.725 -0.085 79.895 0.085 ; - RECT 79.265 -0.085 79.435 0.085 ; - RECT 78.805 -0.085 78.975 0.085 ; - RECT 78.345 -0.085 78.515 0.085 ; - RECT 77.885 -0.085 78.055 0.085 ; - RECT 77.425 -0.085 77.595 0.085 ; - RECT 76.965 -0.085 77.135 0.085 ; - RECT 76.505 -0.085 76.675 0.085 ; - RECT 76.045 -0.085 76.215 0.085 ; - RECT 75.585 -0.085 75.755 0.085 ; - RECT 75.125 -0.085 75.295 0.085 ; - RECT 74.665 -0.085 74.835 0.085 ; - RECT 74.205 -0.085 74.375 0.085 ; - RECT 73.745 -0.085 73.915 0.085 ; - RECT 73.285 -0.085 73.455 0.085 ; - RECT 72.825 -0.085 72.995 0.085 ; - RECT 72.365 -0.085 72.535 0.085 ; - RECT 71.905 -0.085 72.075 0.085 ; - RECT 71.445 -0.085 71.615 0.085 ; - RECT 70.985 -0.085 71.155 0.085 ; - RECT 70.525 -0.085 70.695 0.085 ; - RECT 70.065 -0.085 70.235 0.085 ; - RECT 69.605 -0.085 69.775 0.085 ; - RECT 69.145 -0.085 69.315 0.085 ; - RECT 68.685 -0.085 68.855 0.085 ; - RECT 68.225 -0.085 68.395 0.085 ; - RECT 67.765 -0.085 67.935 0.085 ; - RECT 67.305 -0.085 67.475 0.085 ; - RECT 66.845 -0.085 67.015 0.085 ; - RECT 66.385 -0.085 66.555 0.085 ; - RECT 65.925 -0.085 66.095 0.085 ; - RECT 65.465 -0.085 65.635 0.085 ; - RECT 65.005 -0.085 65.175 0.085 ; - RECT 64.545 -0.085 64.715 0.085 ; - RECT 64.085 -0.085 64.255 0.085 ; - RECT 63.625 -0.085 63.795 0.085 ; - RECT 63.165 -0.085 63.335 0.085 ; - RECT 62.705 -0.085 62.875 0.085 ; - RECT 62.245 -0.085 62.415 0.085 ; - RECT 61.785 -0.085 61.955 0.085 ; - RECT 61.325 -0.085 61.495 0.085 ; - RECT 60.865 -0.085 61.035 0.085 ; - RECT 60.405 -0.085 60.575 0.085 ; - RECT 59.945 -0.085 60.115 0.085 ; - RECT 59.485 -0.085 59.655 0.085 ; - RECT 59.025 -0.085 59.195 0.085 ; - RECT 58.565 -0.085 58.735 0.085 ; - RECT 58.105 -0.085 58.275 0.085 ; - RECT 57.645 -0.085 57.815 0.085 ; - RECT 57.185 -0.085 57.355 0.085 ; - RECT 56.725 -0.085 56.895 0.085 ; - RECT 56.265 -0.085 56.435 0.085 ; - RECT 55.805 -0.085 55.975 0.085 ; - RECT 55.345 -0.085 55.515 0.085 ; - RECT 54.885 -0.085 55.055 0.085 ; - RECT 54.425 -0.085 54.595 0.085 ; - RECT 53.965 -0.085 54.135 0.085 ; - RECT 53.505 -0.085 53.675 0.085 ; - RECT 53.045 -0.085 53.215 0.085 ; - RECT 52.585 -0.085 52.755 0.085 ; - RECT 52.125 -0.085 52.295 0.085 ; - RECT 51.665 -0.085 51.835 0.085 ; - RECT 51.205 -0.085 51.375 0.085 ; - RECT 50.745 -0.085 50.915 0.085 ; - RECT 50.285 -0.085 50.455 0.085 ; - RECT 49.825 -0.085 49.995 0.085 ; - RECT 49.365 -0.085 49.535 0.085 ; - RECT 48.905 -0.085 49.075 0.085 ; - RECT 48.445 -0.085 48.615 0.085 ; - RECT 47.985 -0.085 48.155 0.085 ; - RECT 47.525 -0.085 47.695 0.085 ; - RECT 47.065 -0.085 47.235 0.085 ; - RECT 46.605 -0.085 46.775 0.085 ; - RECT 46.145 -0.085 46.315 0.085 ; - RECT 45.685 -0.085 45.855 0.085 ; - RECT 45.225 -0.085 45.395 0.085 ; - RECT 44.765 -0.085 44.935 0.085 ; - RECT 44.305 -0.085 44.475 0.085 ; - RECT 43.845 -0.085 44.015 0.085 ; - RECT 43.385 -0.085 43.555 0.085 ; - RECT 42.925 -0.085 43.095 0.085 ; - RECT 42.465 -0.085 42.635 0.085 ; - RECT 42.005 -0.085 42.175 0.085 ; - RECT 41.545 -0.085 41.715 0.085 ; - RECT 41.085 -0.085 41.255 0.085 ; - RECT 40.625 -0.085 40.795 0.085 ; - RECT 40.165 -0.085 40.335 0.085 ; - RECT 39.705 -0.085 39.875 0.085 ; - RECT 39.245 -0.085 39.415 0.085 ; - RECT 38.785 -0.085 38.955 0.085 ; - RECT 38.325 -0.085 38.495 0.085 ; - RECT 37.865 -0.085 38.035 0.085 ; - RECT 37.405 -0.085 37.575 0.085 ; - RECT 36.945 -0.085 37.115 0.085 ; - RECT 36.485 -0.085 36.655 0.085 ; - RECT 36.025 -0.085 36.195 0.085 ; - RECT 35.565 -0.085 35.735 0.085 ; - RECT 35.105 -0.085 35.275 0.085 ; - RECT 34.645 -0.085 34.815 0.085 ; - RECT 34.185 -0.085 34.355 0.085 ; - RECT 33.725 -0.085 33.895 0.085 ; - RECT 33.265 -0.085 33.435 0.085 ; - RECT 32.805 -0.085 32.975 0.085 ; - RECT 32.345 -0.085 32.515 0.085 ; - RECT 31.885 -0.085 32.055 0.085 ; - RECT 31.425 -0.085 31.595 0.085 ; - RECT 30.965 -0.085 31.135 0.085 ; - RECT 30.505 -0.085 30.675 0.085 ; - RECT 30.045 -0.085 30.215 0.085 ; - RECT 29.585 -0.085 29.755 0.085 ; - RECT 29.125 -0.085 29.295 0.085 ; - RECT 28.665 -0.085 28.835 0.085 ; - RECT 28.205 -0.085 28.375 0.085 ; - RECT 27.745 -0.085 27.915 0.085 ; - RECT 27.285 -0.085 27.455 0.085 ; - RECT 26.825 -0.085 26.995 0.085 ; - RECT 26.365 -0.085 26.535 0.085 ; - RECT 25.905 -0.085 26.075 0.085 ; - LAYER via ; - RECT 80.885 108.725 81.035 108.875 ; - RECT 51.445 108.725 51.595 108.875 ; - RECT 63.865 107.025 64.015 107.175 ; - RECT 49.605 107.025 49.755 107.175 ; - RECT 43.625 107.025 43.775 107.175 ; - RECT 80.885 97.845 81.035 97.995 ; - RECT 51.445 97.845 51.595 97.995 ; - RECT 10.965 97.845 11.115 97.995 ; - RECT 14.185 96.145 14.335 96.295 ; - RECT 9.125 96.145 9.275 96.295 ; - RECT 114.005 12.505 114.155 12.655 ; - RECT 4.985 12.505 5.135 12.655 ; - RECT 80.885 10.805 81.035 10.955 ; - RECT 51.445 10.805 51.595 10.955 ; - RECT 10.965 10.805 11.115 10.955 ; - RECT 69.845 1.625 69.995 1.775 ; - RECT 65.245 1.625 65.395 1.775 ; - RECT 80.885 -0.075 81.035 0.075 ; - RECT 51.445 -0.075 51.595 0.075 ; - LAYER via2 ; - RECT 80.86 108.7 81.06 108.9 ; - RECT 51.42 108.7 51.62 108.9 ; - RECT 10.94 97.82 11.14 98.02 ; - RECT 1.28 85.58 1.48 85.78 ; - RECT 1.74 80.14 1.94 80.34 ; - RECT 1.74 61.1 1.94 61.3 ; - RECT 1.28 59.06 1.48 59.26 ; - RECT 116.28 54.3 116.48 54.5 ; - RECT 115.82 47.5 116.02 47.7 ; - RECT 1.28 33.22 1.48 33.42 ; - RECT 116.28 31.86 116.48 32.06 ; - RECT 10.94 10.78 11.14 10.98 ; - RECT 80.86 -0.1 81.06 0.1 ; - RECT 51.42 -0.1 51.62 0.1 ; - LAYER via3 ; - RECT 80.86 108.7 81.06 108.9 ; - RECT 51.42 108.7 51.62 108.9 ; - RECT 10.94 97.82 11.14 98.02 ; - RECT 1.74 53.62 1.94 53.82 ; - RECT 115.82 43.42 116.02 43.62 ; - RECT 10.94 10.78 11.14 10.98 ; - RECT 80.86 -0.1 81.06 0.1 ; - RECT 51.42 -0.1 51.62 0.1 ; - LAYER OVERLAP ; - POLYGON 25.76 0 25.76 10.88 0 10.88 0 97.92 25.76 97.92 25.76 108.8 92 108.8 92 97.92 117.76 97.92 117.76 10.88 92 10.88 92 0 ; - END -END sb_1__1_ - -END LIBRARY diff --git a/FPGA22_HIER_SKY_PNR/modules/lef/sb_1__2__icv_in_design.lef b/FPGA22_HIER_SKY_PNR/modules/lef/sb_1__2__icv_in_design.lef deleted file mode 100644 index 115f31a..0000000 --- a/FPGA22_HIER_SKY_PNR/modules/lef/sb_1__2__icv_in_design.lef +++ /dev/null @@ -1,2685 +0,0 @@ -VERSION 5.7 ; -BUSBITCHARS "[]" ; - -UNITS - DATABASE MICRONS 1000 ; -END UNITS - -MANUFACTURINGGRID 0.005 ; - -LAYER li1 - TYPE ROUTING ; - DIRECTION VERTICAL ; - PITCH 0.46 ; - WIDTH 0.17 ; -END li1 - -LAYER mcon - TYPE CUT ; -END mcon - -LAYER met1 - TYPE ROUTING ; - DIRECTION HORIZONTAL ; - PITCH 0.34 ; - WIDTH 0.14 ; -END met1 - -LAYER via - TYPE CUT ; -END via - -LAYER met2 - TYPE ROUTING ; - DIRECTION VERTICAL ; - PITCH 0.46 ; - WIDTH 0.14 ; -END met2 - -LAYER via2 - TYPE CUT ; -END via2 - -LAYER met3 - TYPE ROUTING ; - DIRECTION HORIZONTAL ; - PITCH 0.68 ; - WIDTH 0.3 ; -END met3 - -LAYER via3 - TYPE CUT ; -END via3 - -LAYER met4 - TYPE ROUTING ; - DIRECTION VERTICAL ; - PITCH 0.92 ; - WIDTH 0.3 ; -END met4 - -LAYER via4 - TYPE CUT ; -END via4 - -LAYER met5 - TYPE ROUTING ; - DIRECTION HORIZONTAL ; - PITCH 3.4 ; - WIDTH 1.6 ; -END met5 - -LAYER nwell - TYPE MASTERSLICE ; -END nwell - -LAYER pwell - TYPE MASTERSLICE ; -END pwell - -LAYER OVERLAP - TYPE OVERLAP ; -END OVERLAP - -VIA L1M1_PR - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.145 -0.115 0.145 0.115 ; -END L1M1_PR - -VIA L1M1_PR_R - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.115 -0.145 0.115 0.145 ; -END L1M1_PR_R - -VIA L1M1_PR_M - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.115 -0.145 0.115 0.145 ; -END L1M1_PR_M - -VIA L1M1_PR_MR - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.145 -0.115 0.145 0.115 ; -END L1M1_PR_MR - -VIA L1M1_PR_C - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.145 -0.145 0.145 0.145 ; -END L1M1_PR_C - -VIA M1M2_PR - LAYER met1 ; - RECT -0.16 -0.13 0.16 0.13 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.13 -0.16 0.13 0.16 ; -END M1M2_PR - -VIA M1M2_PR_Enc - LAYER met1 ; - RECT -0.16 -0.13 0.16 0.13 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.16 -0.13 0.16 0.13 ; -END M1M2_PR_Enc - -VIA M1M2_PR_R - LAYER met1 ; - RECT -0.13 -0.16 0.13 0.16 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.16 -0.13 0.16 0.13 ; -END M1M2_PR_R - -VIA M1M2_PR_R_Enc - LAYER met1 ; - RECT -0.13 -0.16 0.13 0.16 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.13 -0.16 0.13 0.16 ; -END M1M2_PR_R_Enc - -VIA M1M2_PR_M - LAYER met1 ; - RECT -0.16 -0.13 0.16 0.13 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.16 -0.13 0.16 0.13 ; -END M1M2_PR_M - -VIA M1M2_PR_M_Enc - LAYER met1 ; - RECT -0.16 -0.13 0.16 0.13 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.13 -0.16 0.13 0.16 ; -END M1M2_PR_M_Enc - -VIA M1M2_PR_MR - LAYER met1 ; - RECT -0.13 -0.16 0.13 0.16 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.13 -0.16 0.13 0.16 ; -END M1M2_PR_MR - -VIA M1M2_PR_MR_Enc - LAYER met1 ; - RECT -0.13 -0.16 0.13 0.16 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.16 -0.13 0.16 0.13 ; -END M1M2_PR_MR_Enc - -VIA M1M2_PR_C - LAYER met1 ; - RECT -0.16 -0.16 0.16 0.16 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.16 -0.16 0.16 0.16 ; -END M1M2_PR_C - -VIA M2M3_PR - LAYER met2 ; - RECT -0.14 -0.185 0.14 0.185 ; - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met3 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M2M3_PR - -VIA M2M3_PR_R - LAYER met2 ; - RECT -0.185 -0.14 0.185 0.14 ; - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met3 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M2M3_PR_R - -VIA M2M3_PR_M - LAYER met2 ; - RECT -0.14 -0.185 0.14 0.185 ; - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met3 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M2M3_PR_M - -VIA M2M3_PR_MR - LAYER met2 ; - RECT -0.185 -0.14 0.185 0.14 ; - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met3 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M2M3_PR_MR - -VIA M2M3_PR_C - LAYER met2 ; - RECT -0.185 -0.185 0.185 0.185 ; - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met3 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M2M3_PR_C - -VIA M3M4_PR - LAYER met3 ; - RECT -0.19 -0.16 0.19 0.16 ; - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR - -VIA M3M4_PR_R - LAYER met3 ; - RECT -0.16 -0.19 0.16 0.19 ; - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR_R - -VIA M3M4_PR_M - LAYER met3 ; - RECT -0.19 -0.16 0.19 0.16 ; - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR_M - -VIA M3M4_PR_MR - LAYER met3 ; - RECT -0.16 -0.19 0.16 0.19 ; - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR_MR - -VIA M3M4_PR_C - LAYER met3 ; - RECT -0.19 -0.19 0.19 0.19 ; - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR_C - -VIA M4M5_PR - LAYER met4 ; - RECT -0.59 -0.59 0.59 0.59 ; - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - LAYER met5 ; - RECT -0.71 -0.71 0.71 0.71 ; -END M4M5_PR - -VIA M4M5_PR_R - LAYER met4 ; - RECT -0.59 -0.59 0.59 0.59 ; - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - LAYER met5 ; - RECT -0.71 -0.71 0.71 0.71 ; -END M4M5_PR_R - -VIA M4M5_PR_M - LAYER met4 ; - RECT -0.59 -0.59 0.59 0.59 ; - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - LAYER met5 ; - RECT -0.71 -0.71 0.71 0.71 ; -END M4M5_PR_M - -VIA M4M5_PR_MR - LAYER met4 ; - RECT -0.59 -0.59 0.59 0.59 ; - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - LAYER met5 ; - RECT -0.71 -0.71 0.71 0.71 ; -END M4M5_PR_MR - -VIA M4M5_PR_C - LAYER met4 ; - RECT -0.59 -0.59 0.59 0.59 ; - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - LAYER met5 ; - RECT -0.71 -0.71 0.71 0.71 ; -END M4M5_PR_C - -SITE unit - CLASS CORE ; - SYMMETRY Y ; - SIZE 0.46 BY 2.72 ; -END unit - -SITE unithddbl - CLASS CORE ; - SIZE 0.46 BY 5.44 ; -END unithddbl - -MACRO sb_1__2_ - CLASS BLOCK ; - ORIGIN 0 0 ; - SIZE 117.76 BY 97.92 ; - SYMMETRY X Y ; - PIN prog_clk[0] - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER met2 ; - RECT 52.83 0 52.97 1.36 ; - END - END prog_clk[0] - PIN chanx_right_in[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 81.45 117.76 81.75 ; - END - END chanx_right_in[0] - PIN chanx_right_in[1] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 53.57 117.76 53.87 ; - END - END chanx_right_in[1] - PIN chanx_right_in[2] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 80.09 117.76 80.39 ; - END - END chanx_right_in[2] - PIN chanx_right_in[3] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 72.61 117.76 72.91 ; - END - END chanx_right_in[3] - PIN chanx_right_in[4] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 33.85 117.76 34.15 ; - END - END chanx_right_in[4] - PIN chanx_right_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 22.97 117.76 23.27 ; - END - END chanx_right_in[5] - PIN chanx_right_in[6] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 24.33 117.76 24.63 ; - END - END chanx_right_in[6] - PIN chanx_right_in[7] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 49.49 117.76 49.79 ; - END - END chanx_right_in[7] - PIN chanx_right_in[8] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 77.37 117.76 77.67 ; - END - END chanx_right_in[8] - PIN chanx_right_in[9] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 59.69 117.76 59.99 ; - END - END chanx_right_in[9] - PIN chanx_right_in[10] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 73.97 117.76 74.27 ; - END - END chanx_right_in[10] - PIN chanx_right_in[11] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 68.53 117.76 68.83 ; - END - END chanx_right_in[11] - PIN chanx_right_in[12] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 50.85 117.76 51.15 ; - END - END chanx_right_in[12] - PIN chanx_right_in[13] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 71.25 117.76 71.55 ; - END - END chanx_right_in[13] - PIN chanx_right_in[14] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 31.13 117.76 31.43 ; - END - END chanx_right_in[14] - PIN chanx_right_in[15] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 55.61 117.76 55.91 ; - END - END chanx_right_in[15] - PIN chanx_right_in[16] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 29.09 117.76 29.39 ; - END - END chanx_right_in[16] - PIN chanx_right_in[17] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 52.21 117.76 52.51 ; - END - END chanx_right_in[17] - PIN chanx_right_in[18] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 56.97 117.76 57.27 ; - END - END chanx_right_in[18] - PIN chanx_right_in[19] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 58.33 117.76 58.63 ; - END - END chanx_right_in[19] - PIN right_top_grid_pin_1_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 37.93 117.76 38.23 ; - END - END right_top_grid_pin_1_[0] - PIN right_bottom_grid_pin_34_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 109.41 10.88 109.55 12.24 ; - END - END right_bottom_grid_pin_34_[0] - PIN right_bottom_grid_pin_35_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 111.71 10.88 111.85 12.24 ; - END - END right_bottom_grid_pin_35_[0] - PIN right_bottom_grid_pin_36_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 114.01 10.88 114.15 12.24 ; - END - END right_bottom_grid_pin_36_[0] - PIN right_bottom_grid_pin_37_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 108.49 10.88 108.63 12.24 ; - END - END right_bottom_grid_pin_37_[0] - PIN right_bottom_grid_pin_38_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 110.79 10.88 110.93 12.24 ; - END - END right_bottom_grid_pin_38_[0] - PIN right_bottom_grid_pin_39_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 113.09 10.88 113.23 12.24 ; - END - END right_bottom_grid_pin_39_[0] - PIN right_bottom_grid_pin_40_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 101.59 10.88 101.73 12.24 ; - END - END right_bottom_grid_pin_40_[0] - PIN right_bottom_grid_pin_41_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 106.19 10.88 106.33 12.24 ; - END - END right_bottom_grid_pin_41_[0] - PIN chany_bottom_in[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 77.21 0 77.35 1.36 ; - END - END chany_bottom_in[0] - PIN chany_bottom_in[1] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 68.93 0 69.07 1.36 ; - END - END chany_bottom_in[1] - PIN chany_bottom_in[2] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 79.05 0 79.19 1.36 ; - END - END chany_bottom_in[2] - PIN chany_bottom_in[3] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 69.85 0 69.99 1.36 ; - END - END chany_bottom_in[3] - PIN chany_bottom_in[4] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 65.25 0 65.39 1.36 ; - END - END chany_bottom_in[4] - PIN chany_bottom_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 59.27 0 59.41 1.36 ; - END - END chany_bottom_in[5] - PIN chany_bottom_in[6] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 46.85 0 46.99 1.36 ; - END - END chany_bottom_in[6] - PIN chany_bottom_in[7] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 60.19 0 60.33 1.36 ; - END - END chany_bottom_in[7] - PIN chany_bottom_in[8] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 47.77 0 47.91 1.36 ; - END - END chany_bottom_in[8] - PIN chany_bottom_in[9] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 67.09 0 67.23 1.36 ; - END - END chany_bottom_in[9] - PIN chany_bottom_in[10] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 68.01 0 68.15 1.36 ; - END - END chany_bottom_in[10] - PIN chany_bottom_in[11] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 70.77 0 70.91 1.36 ; - END - END chany_bottom_in[11] - PIN chany_bottom_in[12] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 62.49 0 62.63 1.36 ; - END - END chany_bottom_in[12] - PIN chany_bottom_in[13] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 61.11 0 61.25 1.36 ; - END - END chany_bottom_in[13] - PIN chany_bottom_in[14] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 48.69 0 48.83 1.36 ; - END - END chany_bottom_in[14] - PIN chany_bottom_in[15] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 56.97 0 57.11 1.36 ; - END - END chany_bottom_in[15] - PIN chany_bottom_in[16] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 78.13 0 78.27 1.36 ; - END - END chany_bottom_in[16] - PIN chany_bottom_in[17] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 45.93 0 46.07 1.36 ; - END - END chany_bottom_in[17] - PIN chany_bottom_in[18] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 49.61 0 49.75 1.36 ; - END - END chany_bottom_in[18] - PIN chany_bottom_in[19] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 72.61 0 72.75 1.36 ; - END - END chany_bottom_in[19] - PIN bottom_left_grid_pin_42_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 12.73 10.88 13.03 12.24 ; - END - END bottom_left_grid_pin_42_[0] - PIN bottom_left_grid_pin_43_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 9.05 10.88 9.35 12.24 ; - END - END bottom_left_grid_pin_43_[0] - PIN bottom_left_grid_pin_44_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 27.99 0 28.13 1.36 ; - END - END bottom_left_grid_pin_44_[0] - PIN bottom_left_grid_pin_45_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 7.29 10.88 7.43 12.24 ; - END - END bottom_left_grid_pin_45_[0] - PIN bottom_left_grid_pin_46_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 9.13 10.88 9.27 12.24 ; - END - END bottom_left_grid_pin_46_[0] - PIN bottom_left_grid_pin_47_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 15.11 10.88 15.25 12.24 ; - END - END bottom_left_grid_pin_47_[0] - PIN bottom_left_grid_pin_48_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 8.21 10.88 8.35 12.24 ; - END - END bottom_left_grid_pin_48_[0] - PIN bottom_left_grid_pin_49_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 10.05 10.88 10.19 12.24 ; - END - END bottom_left_grid_pin_49_[0] - PIN chanx_left_in[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 42.69 1.38 42.99 ; - END - END chanx_left_in[0] - PIN chanx_left_in[1] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 54.93 1.38 55.23 ; - END - END chanx_left_in[1] - PIN chanx_left_in[2] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 49.49 1.38 49.79 ; - END - END chanx_left_in[2] - PIN chanx_left_in[3] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 21.61 1.38 21.91 ; - END - END chanx_left_in[3] - PIN chanx_left_in[4] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 22.97 1.38 23.27 ; - END - END chanx_left_in[4] - PIN chanx_left_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 33.17 1.38 33.47 ; - END - END chanx_left_in[5] - PIN chanx_left_in[6] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 26.37 1.38 26.67 ; - END - END chanx_left_in[6] - PIN chanx_left_in[7] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 29.09 1.38 29.39 ; - END - END chanx_left_in[7] - PIN chanx_left_in[8] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 41.33 1.38 41.63 ; - END - END chanx_left_in[8] - PIN chanx_left_in[9] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 56.29 1.38 56.59 ; - END - END chanx_left_in[9] - PIN chanx_left_in[10] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 57.65 1.38 57.95 ; - END - END chanx_left_in[10] - PIN chanx_left_in[11] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 59.01 1.38 59.31 ; - END - END chanx_left_in[11] - PIN chanx_left_in[12] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 18.89 1.38 19.19 ; - END - END chanx_left_in[12] - PIN chanx_left_in[13] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 20.25 1.38 20.55 ; - END - END chanx_left_in[13] - PIN chanx_left_in[14] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 17.53 1.38 17.83 ; - END - END chanx_left_in[14] - PIN chanx_left_in[15] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 30.45 1.38 30.75 ; - END - END chanx_left_in[15] - PIN chanx_left_in[16] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 64.45 1.38 64.75 ; - END - END chanx_left_in[16] - PIN chanx_left_in[17] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 50.85 1.38 51.15 ; - END - END chanx_left_in[17] - PIN chanx_left_in[18] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 69.21 1.38 69.51 ; - END - END chanx_left_in[18] - PIN chanx_left_in[19] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 38.61 1.38 38.91 ; - END - END chanx_left_in[19] - PIN left_top_grid_pin_1_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 61.05 1.38 61.35 ; - END - END left_top_grid_pin_1_[0] - PIN left_bottom_grid_pin_34_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 28.91 0 29.05 1.36 ; - END - END left_bottom_grid_pin_34_[0] - PIN left_bottom_grid_pin_35_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 12.81 10.88 12.95 12.24 ; - END - END left_bottom_grid_pin_35_[0] - PIN left_bottom_grid_pin_36_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 4.99 10.88 5.13 12.24 ; - END - END left_bottom_grid_pin_36_[0] - PIN left_bottom_grid_pin_37_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 4.07 10.88 4.21 12.24 ; - END - END left_bottom_grid_pin_37_[0] - PIN left_bottom_grid_pin_38_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 6.37 10.88 6.51 12.24 ; - END - END left_bottom_grid_pin_38_[0] - PIN left_bottom_grid_pin_39_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 4.45 10.88 4.75 12.24 ; - END - END left_bottom_grid_pin_39_[0] - PIN left_bottom_grid_pin_40_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 11.89 10.88 12.03 12.24 ; - END - END left_bottom_grid_pin_40_[0] - PIN left_bottom_grid_pin_41_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 16.03 10.88 16.17 12.24 ; - END - END left_bottom_grid_pin_41_[0] - PIN ccff_head[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 48.13 117.76 48.43 ; - END - END ccff_head[0] - PIN chanx_right_out[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 14.13 117.76 14.43 ; - END - END chanx_right_out[0] - PIN chanx_right_out[1] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 32.49 117.76 32.79 ; - END - END chanx_right_out[1] - PIN chanx_right_out[2] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 15.49 117.76 15.79 ; - END - END chanx_right_out[2] - PIN chanx_right_out[3] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 61.05 117.76 61.35 ; - END - END chanx_right_out[3] - PIN chanx_right_out[4] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 21.61 117.76 21.91 ; - END - END chanx_right_out[4] - PIN chanx_right_out[5] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 26.37 117.76 26.67 ; - END - END chanx_right_out[5] - PIN chanx_right_out[6] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 46.77 117.76 47.07 ; - END - END chanx_right_out[6] - PIN chanx_right_out[7] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 41.33 117.76 41.63 ; - END - END chanx_right_out[7] - PIN chanx_right_out[8] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 67.17 117.76 67.47 ; - END - END chanx_right_out[8] - PIN chanx_right_out[9] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 44.05 117.76 44.35 ; - END - END chanx_right_out[9] - PIN chanx_right_out[10] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 36.57 117.76 36.87 ; - END - END chanx_right_out[10] - PIN chanx_right_out[11] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 39.97 117.76 40.27 ; - END - END chanx_right_out[11] - PIN chanx_right_out[12] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 20.25 117.76 20.55 ; - END - END chanx_right_out[12] - PIN chanx_right_out[13] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 27.73 117.76 28.03 ; - END - END chanx_right_out[13] - PIN chanx_right_out[14] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 69.89 117.76 70.19 ; - END - END chanx_right_out[14] - PIN chanx_right_out[15] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 42.69 117.76 42.99 ; - END - END chanx_right_out[15] - PIN chanx_right_out[16] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 75.33 117.76 75.63 ; - END - END chanx_right_out[16] - PIN chanx_right_out[17] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 45.41 117.76 45.71 ; - END - END chanx_right_out[17] - PIN chanx_right_out[18] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 64.45 117.76 64.75 ; - END - END chanx_right_out[18] - PIN chanx_right_out[19] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 116.38 35.21 117.76 35.51 ; - END - END chanx_right_out[19] - PIN chany_bottom_out[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 63.87 0 64.01 1.36 ; - END - END chany_bottom_out[0] - PIN chany_bottom_out[1] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 45.01 0 45.15 1.36 ; - END - END chany_bottom_out[1] - PIN chany_bottom_out[2] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 55.13 0 55.27 1.36 ; - END - END chany_bottom_out[2] - PIN chany_bottom_out[3] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 66.17 0 66.31 1.36 ; - END - END chany_bottom_out[3] - PIN chany_bottom_out[4] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 58.35 0 58.49 1.36 ; - END - END chany_bottom_out[4] - PIN chany_bottom_out[5] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 75.37 0 75.51 1.36 ; - END - END chany_bottom_out[5] - PIN chany_bottom_out[6] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 50.53 0 50.67 1.36 ; - END - END chany_bottom_out[6] - PIN chany_bottom_out[7] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 73.53 0 73.67 1.36 ; - END - END chany_bottom_out[7] - PIN chany_bottom_out[8] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 82.73 0 82.87 1.36 ; - END - END chany_bottom_out[8] - PIN chany_bottom_out[9] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 74.45 0 74.59 1.36 ; - END - END chany_bottom_out[9] - PIN chany_bottom_out[10] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 56.05 0 56.19 1.36 ; - END - END chany_bottom_out[10] - PIN chany_bottom_out[11] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 71.69 0 71.83 1.36 ; - END - END chany_bottom_out[11] - PIN chany_bottom_out[12] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 79.97 0 80.11 1.36 ; - END - END chany_bottom_out[12] - PIN chany_bottom_out[13] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 76.29 0 76.43 1.36 ; - END - END chany_bottom_out[13] - PIN chany_bottom_out[14] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 34.43 0 34.57 1.36 ; - END - END chany_bottom_out[14] - PIN chany_bottom_out[15] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 88.25 0 88.39 1.36 ; - END - END chany_bottom_out[15] - PIN chany_bottom_out[16] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 81.81 0 81.95 1.36 ; - END - END chany_bottom_out[16] - PIN chany_bottom_out[17] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 87.33 0 87.47 1.36 ; - END - END chany_bottom_out[17] - PIN chany_bottom_out[18] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 54.21 0 54.35 1.36 ; - END - END chany_bottom_out[18] - PIN chany_bottom_out[19] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 89.17 0 89.31 1.36 ; - END - END chany_bottom_out[19] - PIN chanx_left_out[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 71.93 1.38 72.23 ; - END - END chanx_left_out[0] - PIN chanx_left_out[1] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 89.61 1.38 89.91 ; - END - END chanx_left_out[1] - PIN chanx_left_out[2] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 73.29 1.38 73.59 ; - END - END chanx_left_out[2] - PIN chanx_left_out[3] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 52.21 1.38 52.51 ; - END - END chanx_left_out[3] - PIN chanx_left_out[4] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 70.57 1.38 70.87 ; - END - END chanx_left_out[4] - PIN chanx_left_out[5] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 67.85 1.38 68.15 ; - END - END chanx_left_out[5] - PIN chanx_left_out[6] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 46.77 1.38 47.07 ; - END - END chanx_left_out[6] - PIN chanx_left_out[7] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 48.13 1.38 48.43 ; - END - END chanx_left_out[7] - PIN chanx_left_out[8] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 77.37 1.38 77.67 ; - END - END chanx_left_out[8] - PIN chanx_left_out[9] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 44.05 1.38 44.35 ; - END - END chanx_left_out[9] - PIN chanx_left_out[10] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 53.57 1.38 53.87 ; - END - END chanx_left_out[10] - PIN chanx_left_out[11] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 37.25 1.38 37.55 ; - END - END chanx_left_out[11] - PIN chanx_left_out[12] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 74.65 1.38 74.95 ; - END - END chanx_left_out[12] - PIN chanx_left_out[13] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 27.73 1.38 28.03 ; - END - END chanx_left_out[13] - PIN chanx_left_out[14] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 63.09 1.38 63.39 ; - END - END chanx_left_out[14] - PIN chanx_left_out[15] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 39.97 1.38 40.27 ; - END - END chanx_left_out[15] - PIN chanx_left_out[16] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 24.33 1.38 24.63 ; - END - END chanx_left_out[16] - PIN chanx_left_out[17] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 31.81 1.38 32.11 ; - END - END chanx_left_out[17] - PIN chanx_left_out[18] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 45.41 1.38 45.71 ; - END - END chanx_left_out[18] - PIN chanx_left_out[19] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 65.81 1.38 66.11 ; - END - END chanx_left_out[19] - PIN ccff_tail[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 14.81 1.38 15.11 ; - END - END ccff_tail[0] - PIN SC_IN_TOP - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 62.49 96.56 62.63 97.92 ; - END - END SC_IN_TOP - PIN SC_IN_BOT - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 60.65 96.56 60.79 97.92 ; - END - END SC_IN_BOT - PIN SC_OUT_TOP - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 59.73 96.56 59.87 97.92 ; - END - END SC_OUT_TOP - PIN SC_OUT_BOT - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 58.81 96.56 58.95 97.92 ; - END - END SC_OUT_BOT - PIN VDD - DIRECTION INPUT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 25.76 2.48 26.24 2.96 ; - RECT 91.52 2.48 92 2.96 ; - RECT 25.76 7.92 26.24 8.4 ; - RECT 91.52 7.92 92 8.4 ; - RECT 0 13.36 0.48 13.84 ; - RECT 117.28 13.36 117.76 13.84 ; - RECT 0 18.8 0.48 19.28 ; - RECT 117.28 18.8 117.76 19.28 ; - RECT 0 24.24 0.48 24.72 ; - RECT 117.28 24.24 117.76 24.72 ; - RECT 0 29.68 0.48 30.16 ; - RECT 117.28 29.68 117.76 30.16 ; - RECT 0 35.12 0.48 35.6 ; - RECT 117.28 35.12 117.76 35.6 ; - RECT 0 40.56 0.48 41.04 ; - RECT 117.28 40.56 117.76 41.04 ; - RECT 0 46 0.48 46.48 ; - RECT 117.28 46 117.76 46.48 ; - RECT 0 51.44 0.48 51.92 ; - RECT 117.28 51.44 117.76 51.92 ; - RECT 0 56.88 0.48 57.36 ; - RECT 117.28 56.88 117.76 57.36 ; - RECT 0 62.32 0.48 62.8 ; - RECT 117.28 62.32 117.76 62.8 ; - RECT 0 67.76 0.48 68.24 ; - RECT 117.28 67.76 117.76 68.24 ; - RECT 0 73.2 0.48 73.68 ; - RECT 117.28 73.2 117.76 73.68 ; - RECT 0 78.64 0.48 79.12 ; - RECT 117.28 78.64 117.76 79.12 ; - RECT 0 84.08 0.48 84.56 ; - RECT 117.28 84.08 117.76 84.56 ; - RECT 0 89.52 0.48 90 ; - RECT 117.28 89.52 117.76 90 ; - RECT 0 94.96 0.48 95.44 ; - RECT 117.28 94.96 117.76 95.44 ; - LAYER met4 ; - RECT 36.5 0 37.1 0.6 ; - RECT 65.94 0 66.54 0.6 ; - RECT 106.42 10.88 107.02 11.48 ; - RECT 36.5 97.32 37.1 97.92 ; - RECT 65.94 97.32 66.54 97.92 ; - RECT 106.42 97.32 107.02 97.92 ; - LAYER met5 ; - RECT 0 22.2 3.2 25.4 ; - RECT 114.56 22.2 117.76 25.4 ; - RECT 0 63 3.2 66.2 ; - RECT 114.56 63 117.76 66.2 ; - END - END VDD - PIN VSS - DIRECTION INPUT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 25.76 0 92 0.24 ; - RECT 25.76 5.2 26.24 5.68 ; - RECT 91.52 5.2 92 5.68 ; - RECT 0 10.64 117.76 11.12 ; - RECT 0 16.08 0.48 16.56 ; - RECT 117.28 16.08 117.76 16.56 ; - RECT 0 21.52 0.48 22 ; - RECT 117.28 21.52 117.76 22 ; - RECT 0 26.96 0.48 27.44 ; - RECT 117.28 26.96 117.76 27.44 ; - RECT 0 32.4 0.48 32.88 ; - RECT 117.28 32.4 117.76 32.88 ; - RECT 0 37.84 0.48 38.32 ; - RECT 117.28 37.84 117.76 38.32 ; - RECT 0 43.28 0.48 43.76 ; - RECT 117.28 43.28 117.76 43.76 ; - RECT 0 48.72 0.48 49.2 ; - RECT 117.28 48.72 117.76 49.2 ; - RECT 0 54.16 0.48 54.64 ; - RECT 117.28 54.16 117.76 54.64 ; - RECT 0 59.6 0.48 60.08 ; - RECT 117.28 59.6 117.76 60.08 ; - RECT 0 65.04 0.48 65.52 ; - RECT 117.28 65.04 117.76 65.52 ; - RECT 0 70.48 0.48 70.96 ; - RECT 117.28 70.48 117.76 70.96 ; - RECT 0 75.92 0.48 76.4 ; - RECT 117.28 75.92 117.76 76.4 ; - RECT 0 81.36 0.48 81.84 ; - RECT 117.28 81.36 117.76 81.84 ; - RECT 0 86.8 0.48 87.28 ; - RECT 117.28 86.8 117.76 87.28 ; - RECT 0 92.24 0.48 92.72 ; - RECT 117.28 92.24 117.76 92.72 ; - RECT 0 97.68 117.76 97.92 ; - LAYER met4 ; - RECT 51.22 0 51.82 0.6 ; - RECT 80.66 0 81.26 0.6 ; - RECT 10.74 10.88 11.34 11.48 ; - RECT 10.74 97.32 11.34 97.92 ; - RECT 51.22 97.32 51.82 97.92 ; - RECT 80.66 97.32 81.26 97.92 ; - LAYER met5 ; - RECT 0 42.6 3.2 45.8 ; - RECT 114.56 42.6 117.76 45.8 ; - RECT 0 83.4 3.2 86.6 ; - RECT 114.56 83.4 117.76 86.6 ; - END - END VSS - PIN Test_en__FEEDTHRU_0[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 63.87 96.56 64.01 97.92 ; - END - END Test_en__FEEDTHRU_0[0] - PIN Test_en__FEEDTHRU_1[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 2.23 10.88 2.37 12.24 ; - END - END Test_en__FEEDTHRU_1[0] - PIN Test_en__FEEDTHRU_2[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 105.27 10.88 105.41 12.24 ; - END - END Test_en__FEEDTHRU_2[0] - PIN clk__FEEDTHRU_0[0] - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER met2 ; - RECT 61.57 96.56 61.71 97.92 ; - END - END clk__FEEDTHRU_0[0] - PIN clk__FEEDTHRU_1[0] - DIRECTION OUTPUT ; - USE CLOCK ; - PORT - LAYER met2 ; - RECT 3.15 10.88 3.29 12.24 ; - END - END clk__FEEDTHRU_1[0] - PIN clk__FEEDTHRU_2[0] - DIRECTION OUTPUT ; - USE CLOCK ; - PORT - LAYER met2 ; - RECT 115.39 10.88 115.53 12.24 ; - END - END clk__FEEDTHRU_2[0] - OBS - LAYER li1 ; - RECT 0 97.835 117.76 98.005 ; - RECT 117.3 95.115 117.76 95.285 ; - RECT 0 95.115 3.68 95.285 ; - RECT 117.3 92.395 117.76 92.565 ; - RECT 0 92.395 3.68 92.565 ; - RECT 117.3 89.675 117.76 89.845 ; - RECT 0 89.675 3.68 89.845 ; - RECT 116.84 86.955 117.76 87.125 ; - RECT 0 86.955 3.68 87.125 ; - RECT 116.84 84.235 117.76 84.405 ; - RECT 0 84.235 3.68 84.405 ; - RECT 117.3 81.515 117.76 81.685 ; - RECT 0 81.515 3.68 81.685 ; - RECT 114.08 78.795 117.76 78.965 ; - RECT 0 78.795 3.68 78.965 ; - RECT 114.08 76.075 117.76 76.245 ; - RECT 0 76.075 3.68 76.245 ; - RECT 116.84 73.355 117.76 73.525 ; - RECT 0 73.355 1.84 73.525 ; - RECT 116.84 70.635 117.76 70.805 ; - RECT 0 70.635 1.84 70.805 ; - RECT 116.84 67.915 117.76 68.085 ; - RECT 0 67.915 1.84 68.085 ; - RECT 114.08 65.195 117.76 65.365 ; - RECT 0 65.195 1.84 65.365 ; - RECT 114.08 62.475 117.76 62.645 ; - RECT 0 62.475 1.84 62.645 ; - RECT 116.84 59.755 117.76 59.925 ; - RECT 0 59.755 1.84 59.925 ; - RECT 114.08 57.035 117.76 57.205 ; - RECT 0 57.035 1.84 57.205 ; - RECT 114.08 54.315 117.76 54.485 ; - RECT 0 54.315 1.84 54.485 ; - RECT 116.84 51.595 117.76 51.765 ; - RECT 0 51.595 1.84 51.765 ; - RECT 116.84 48.875 117.76 49.045 ; - RECT 0 48.875 1.84 49.045 ; - RECT 116.84 46.155 117.76 46.325 ; - RECT 0 46.155 1.84 46.325 ; - RECT 116.84 43.435 117.76 43.605 ; - RECT 0 43.435 1.84 43.605 ; - RECT 116.84 40.715 117.76 40.885 ; - RECT 0 40.715 1.84 40.885 ; - RECT 116.84 37.995 117.76 38.165 ; - RECT 0 37.995 1.84 38.165 ; - RECT 116.84 35.275 117.76 35.445 ; - RECT 0 35.275 1.84 35.445 ; - RECT 116.84 32.555 117.76 32.725 ; - RECT 0 32.555 1.84 32.725 ; - RECT 116.84 29.835 117.76 30.005 ; - RECT 0 29.835 1.84 30.005 ; - RECT 116.84 27.115 117.76 27.285 ; - RECT 0 27.115 1.84 27.285 ; - RECT 116.84 24.395 117.76 24.565 ; - RECT 0 24.395 3.68 24.565 ; - RECT 116.84 21.675 117.76 21.845 ; - RECT 0 21.675 3.68 21.845 ; - RECT 116.84 18.955 117.76 19.125 ; - RECT 0 18.955 1.84 19.125 ; - RECT 116.84 16.235 117.76 16.405 ; - RECT 0 16.235 1.84 16.405 ; - RECT 116.84 13.515 117.76 13.685 ; - RECT 0 13.515 3.68 13.685 ; - RECT 88.78 10.795 117.76 10.965 ; - RECT 0 10.795 27.6 10.965 ; - RECT 91.08 8.075 92 8.245 ; - RECT 25.76 8.075 29.44 8.245 ; - RECT 91.08 5.355 92 5.525 ; - RECT 25.76 5.355 29.44 5.525 ; - RECT 91.08 2.635 92 2.805 ; - RECT 25.76 2.635 29.44 2.805 ; - RECT 25.76 -0.085 92 0.085 ; - LAYER met2 ; - RECT 80.82 97.735 81.1 98.105 ; - RECT 51.38 97.735 51.66 98.105 ; - RECT 10.9 97.735 11.18 98.105 ; - RECT 115.79 12.42 116.05 12.74 ; - RECT 14.59 12.42 14.85 12.74 ; - RECT 5.39 12.42 5.65 12.74 ; - RECT 10.9 10.695 11.18 11.065 ; - RECT 72.09 1.54 72.35 1.86 ; - RECT 80.82 -0.185 81.1 0.185 ; - RECT 51.38 -0.185 51.66 0.185 ; - POLYGON 117.48 97.64 117.48 11.16 115.81 11.16 115.81 12.52 115.11 12.52 115.11 11.16 114.43 11.16 114.43 12.52 113.73 12.52 113.73 11.16 113.51 11.16 113.51 12.52 112.81 12.52 112.81 11.16 112.13 11.16 112.13 12.52 111.43 12.52 111.43 11.16 111.21 11.16 111.21 12.52 110.51 12.52 110.51 11.16 109.83 11.16 109.83 12.52 109.13 12.52 109.13 11.16 108.91 11.16 108.91 12.52 108.21 12.52 108.21 11.16 106.61 11.16 106.61 12.52 105.91 12.52 105.91 11.16 105.69 11.16 105.69 12.52 104.99 12.52 104.99 11.16 102.01 11.16 102.01 12.52 101.31 12.52 101.31 11.16 91.72 11.16 91.72 0.28 89.59 0.28 89.59 1.64 88.89 1.64 88.89 0.28 88.67 0.28 88.67 1.64 87.97 1.64 87.97 0.28 87.75 0.28 87.75 1.64 87.05 1.64 87.05 0.28 83.15 0.28 83.15 1.64 82.45 1.64 82.45 0.28 82.23 0.28 82.23 1.64 81.53 1.64 81.53 0.28 80.39 0.28 80.39 1.64 79.69 1.64 79.69 0.28 79.47 0.28 79.47 1.64 78.77 1.64 78.77 0.28 78.55 0.28 78.55 1.64 77.85 1.64 77.85 0.28 77.63 0.28 77.63 1.64 76.93 1.64 76.93 0.28 76.71 0.28 76.71 1.64 76.01 1.64 76.01 0.28 75.79 0.28 75.79 1.64 75.09 1.64 75.09 0.28 74.87 0.28 74.87 1.64 74.17 1.64 74.17 0.28 73.95 0.28 73.95 1.64 73.25 1.64 73.25 0.28 73.03 0.28 73.03 1.64 72.33 1.64 72.33 0.28 72.11 0.28 72.11 1.64 71.41 1.64 71.41 0.28 71.19 0.28 71.19 1.64 70.49 1.64 70.49 0.28 70.27 0.28 70.27 1.64 69.57 1.64 69.57 0.28 69.35 0.28 69.35 1.64 68.65 1.64 68.65 0.28 68.43 0.28 68.43 1.64 67.73 1.64 67.73 0.28 67.51 0.28 67.51 1.64 66.81 1.64 66.81 0.28 66.59 0.28 66.59 1.64 65.89 1.64 65.89 0.28 65.67 0.28 65.67 1.64 64.97 1.64 64.97 0.28 64.29 0.28 64.29 1.64 63.59 1.64 63.59 0.28 62.91 0.28 62.91 1.64 62.21 1.64 62.21 0.28 61.53 0.28 61.53 1.64 60.83 1.64 60.83 0.28 60.61 0.28 60.61 1.64 59.91 1.64 59.91 0.28 59.69 0.28 59.69 1.64 58.99 1.64 58.99 0.28 58.77 0.28 58.77 1.64 58.07 1.64 58.07 0.28 57.39 0.28 57.39 1.64 56.69 1.64 56.69 0.28 56.47 0.28 56.47 1.64 55.77 1.64 55.77 0.28 55.55 0.28 55.55 1.64 54.85 1.64 54.85 0.28 54.63 0.28 54.63 1.64 53.93 1.64 53.93 0.28 53.25 0.28 53.25 1.64 52.55 1.64 52.55 0.28 50.95 0.28 50.95 1.64 50.25 1.64 50.25 0.28 50.03 0.28 50.03 1.64 49.33 1.64 49.33 0.28 49.11 0.28 49.11 1.64 48.41 1.64 48.41 0.28 48.19 0.28 48.19 1.64 47.49 1.64 47.49 0.28 47.27 0.28 47.27 1.64 46.57 1.64 46.57 0.28 46.35 0.28 46.35 1.64 45.65 1.64 45.65 0.28 45.43 0.28 45.43 1.64 44.73 1.64 44.73 0.28 34.85 0.28 34.85 1.64 34.15 1.64 34.15 0.28 29.33 0.28 29.33 1.64 28.63 1.64 28.63 0.28 28.41 0.28 28.41 1.64 27.71 1.64 27.71 0.28 26.04 0.28 26.04 11.16 16.45 11.16 16.45 12.52 15.75 12.52 15.75 11.16 15.53 11.16 15.53 12.52 14.83 12.52 14.83 11.16 13.23 11.16 13.23 12.52 12.53 12.52 12.53 11.16 12.31 11.16 12.31 12.52 11.61 12.52 11.61 11.16 10.47 11.16 10.47 12.52 9.77 12.52 9.77 11.16 9.55 11.16 9.55 12.52 8.85 12.52 8.85 11.16 8.63 11.16 8.63 12.52 7.93 12.52 7.93 11.16 7.71 11.16 7.71 12.52 7.01 12.52 7.01 11.16 6.79 11.16 6.79 12.52 6.09 12.52 6.09 11.16 5.41 11.16 5.41 12.52 4.71 12.52 4.71 11.16 4.49 11.16 4.49 12.52 3.79 12.52 3.79 11.16 3.57 11.16 3.57 12.52 2.87 12.52 2.87 11.16 2.65 11.16 2.65 12.52 1.95 12.52 1.95 11.16 0.28 11.16 0.28 97.64 58.53 97.64 58.53 96.28 59.23 96.28 59.23 97.64 59.45 97.64 59.45 96.28 60.15 96.28 60.15 97.64 60.37 97.64 60.37 96.28 61.07 96.28 61.07 97.64 61.29 97.64 61.29 96.28 61.99 96.28 61.99 97.64 62.21 97.64 62.21 96.28 62.91 96.28 62.91 97.64 63.59 97.64 63.59 96.28 64.29 96.28 64.29 97.64 ; - LAYER met3 ; - POLYGON 81.125 98.085 81.125 98.08 81.34 98.08 81.34 97.76 81.125 97.76 81.125 97.755 80.795 97.755 80.795 97.76 80.58 97.76 80.58 98.08 80.795 98.08 80.795 98.085 ; - POLYGON 51.685 98.085 51.685 98.08 51.9 98.08 51.9 97.76 51.685 97.76 51.685 97.755 51.355 97.755 51.355 97.76 51.14 97.76 51.14 98.08 51.355 98.08 51.355 98.085 ; - POLYGON 11.205 98.085 11.205 98.08 11.42 98.08 11.42 97.76 11.205 97.76 11.205 97.755 10.875 97.755 10.875 97.76 10.66 97.76 10.66 98.08 10.875 98.08 10.875 98.085 ; - POLYGON 92.15 68.83 92.15 68.53 1.23 68.53 1.23 68.81 1.78 68.81 1.78 68.83 ; - POLYGON 1.545 60.685 1.545 60.67 8.43 60.67 8.43 60.37 1.545 60.37 1.545 60.355 1.215 60.355 1.215 60.685 ; - POLYGON 2.91 47.75 2.91 47.45 1.78 47.45 1.78 47.47 1.23 47.47 1.23 47.75 ; - POLYGON 7.05 28.71 7.05 28.41 1.99 28.41 1.99 27.73 1.78 27.73 1.78 28.43 1.69 28.43 1.69 28.71 ; - POLYGON 11.205 11.045 11.205 11.04 11.42 11.04 11.42 10.72 11.205 10.72 11.205 10.715 10.875 10.715 10.875 10.72 10.66 10.72 10.66 11.04 10.875 11.04 10.875 11.045 ; - POLYGON 81.125 0.165 81.125 0.16 81.34 0.16 81.34 -0.16 81.125 -0.16 81.125 -0.165 80.795 -0.165 80.795 -0.16 80.58 -0.16 80.58 0.16 80.795 0.16 80.795 0.165 ; - POLYGON 51.685 0.165 51.685 0.16 51.9 0.16 51.9 -0.16 51.685 -0.16 51.685 -0.165 51.355 -0.165 51.355 -0.16 51.14 -0.16 51.14 0.16 51.355 0.16 51.355 0.165 ; - POLYGON 117.36 97.52 117.36 82.15 115.98 82.15 115.98 81.05 117.36 81.05 117.36 80.79 115.98 80.79 115.98 79.69 117.36 79.69 117.36 78.07 115.98 78.07 115.98 76.97 117.36 76.97 117.36 76.03 115.98 76.03 115.98 74.93 117.36 74.93 117.36 74.67 115.98 74.67 115.98 73.57 117.36 73.57 117.36 73.31 115.98 73.31 115.98 72.21 117.36 72.21 117.36 71.95 115.98 71.95 115.98 70.85 117.36 70.85 117.36 70.59 115.98 70.59 115.98 69.49 117.36 69.49 117.36 69.23 115.98 69.23 115.98 68.13 117.36 68.13 117.36 67.87 115.98 67.87 115.98 66.77 117.36 66.77 117.36 65.15 115.98 65.15 115.98 64.05 117.36 64.05 117.36 61.75 115.98 61.75 115.98 60.65 117.36 60.65 117.36 60.39 115.98 60.39 115.98 59.29 117.36 59.29 117.36 59.03 115.98 59.03 115.98 57.93 117.36 57.93 117.36 57.67 115.98 57.67 115.98 56.57 117.36 56.57 117.36 56.31 115.98 56.31 115.98 55.21 117.36 55.21 117.36 54.27 115.98 54.27 115.98 53.17 117.36 53.17 117.36 52.91 115.98 52.91 115.98 51.81 117.36 51.81 117.36 51.55 115.98 51.55 115.98 50.45 117.36 50.45 117.36 50.19 115.98 50.19 115.98 49.09 117.36 49.09 117.36 48.83 115.98 48.83 115.98 47.73 117.36 47.73 117.36 47.47 115.98 47.47 115.98 46.37 117.36 46.37 117.36 46.11 115.98 46.11 115.98 45.01 117.36 45.01 117.36 44.75 115.98 44.75 115.98 43.65 117.36 43.65 117.36 43.39 115.98 43.39 115.98 42.29 117.36 42.29 117.36 42.03 115.98 42.03 115.98 40.93 117.36 40.93 117.36 40.67 115.98 40.67 115.98 39.57 117.36 39.57 117.36 38.63 115.98 38.63 115.98 37.53 117.36 37.53 117.36 37.27 115.98 37.27 115.98 36.17 117.36 36.17 117.36 35.91 115.98 35.91 115.98 34.81 117.36 34.81 117.36 34.55 115.98 34.55 115.98 33.45 117.36 33.45 117.36 33.19 115.98 33.19 115.98 32.09 117.36 32.09 117.36 31.83 115.98 31.83 115.98 30.73 117.36 30.73 117.36 29.79 115.98 29.79 115.98 28.69 117.36 28.69 117.36 28.43 115.98 28.43 115.98 27.33 117.36 27.33 117.36 27.07 115.98 27.07 115.98 25.97 117.36 25.97 117.36 25.03 115.98 25.03 115.98 23.93 117.36 23.93 117.36 23.67 115.98 23.67 115.98 22.57 117.36 22.57 117.36 22.31 115.98 22.31 115.98 21.21 117.36 21.21 117.36 20.95 115.98 20.95 115.98 19.85 117.36 19.85 117.36 16.19 115.98 16.19 115.98 15.09 117.36 15.09 117.36 14.83 115.98 14.83 115.98 13.73 117.36 13.73 117.36 11.28 91.6 11.28 91.6 0.4 26.16 0.4 26.16 11.28 0.4 11.28 0.4 14.41 1.78 14.41 1.78 15.51 0.4 15.51 0.4 17.13 1.78 17.13 1.78 18.23 0.4 18.23 0.4 18.49 1.78 18.49 1.78 19.59 0.4 19.59 0.4 19.85 1.78 19.85 1.78 20.95 0.4 20.95 0.4 21.21 1.78 21.21 1.78 22.31 0.4 22.31 0.4 22.57 1.78 22.57 1.78 23.67 0.4 23.67 0.4 23.93 1.78 23.93 1.78 25.03 0.4 25.03 0.4 25.97 1.78 25.97 1.78 27.07 0.4 27.07 0.4 27.33 1.78 27.33 1.78 28.43 0.4 28.43 0.4 28.69 1.78 28.69 1.78 29.79 0.4 29.79 0.4 30.05 1.78 30.05 1.78 31.15 0.4 31.15 0.4 31.41 1.78 31.41 1.78 32.51 0.4 32.51 0.4 32.77 1.78 32.77 1.78 33.87 0.4 33.87 0.4 36.85 1.78 36.85 1.78 37.95 0.4 37.95 0.4 38.21 1.78 38.21 1.78 39.31 0.4 39.31 0.4 39.57 1.78 39.57 1.78 40.67 0.4 40.67 0.4 40.93 1.78 40.93 1.78 42.03 0.4 42.03 0.4 42.29 1.78 42.29 1.78 43.39 0.4 43.39 0.4 43.65 1.78 43.65 1.78 44.75 0.4 44.75 0.4 45.01 1.78 45.01 1.78 46.11 0.4 46.11 0.4 46.37 1.78 46.37 1.78 47.47 0.4 47.47 0.4 47.73 1.78 47.73 1.78 48.83 0.4 48.83 0.4 49.09 1.78 49.09 1.78 50.19 0.4 50.19 0.4 50.45 1.78 50.45 1.78 51.55 0.4 51.55 0.4 51.81 1.78 51.81 1.78 52.91 0.4 52.91 0.4 53.17 1.78 53.17 1.78 54.27 0.4 54.27 0.4 54.53 1.78 54.53 1.78 55.63 0.4 55.63 0.4 55.89 1.78 55.89 1.78 56.99 0.4 56.99 0.4 57.25 1.78 57.25 1.78 58.35 0.4 58.35 0.4 58.61 1.78 58.61 1.78 59.71 0.4 59.71 0.4 60.65 1.78 60.65 1.78 61.75 0.4 61.75 0.4 62.69 1.78 62.69 1.78 63.79 0.4 63.79 0.4 64.05 1.78 64.05 1.78 65.15 0.4 65.15 0.4 65.41 1.78 65.41 1.78 66.51 0.4 66.51 0.4 67.45 1.78 67.45 1.78 68.55 0.4 68.55 0.4 68.81 1.78 68.81 1.78 69.91 0.4 69.91 0.4 70.17 1.78 70.17 1.78 71.27 0.4 71.27 0.4 71.53 1.78 71.53 1.78 72.63 0.4 72.63 0.4 72.89 1.78 72.89 1.78 73.99 0.4 73.99 0.4 74.25 1.78 74.25 1.78 75.35 0.4 75.35 0.4 76.97 1.78 76.97 1.78 78.07 0.4 78.07 0.4 89.21 1.78 89.21 1.78 90.31 0.4 90.31 0.4 97.52 ; - LAYER met4 ; - POLYGON 117.36 97.52 117.36 11.28 107.42 11.28 107.42 11.88 106.02 11.88 106.02 11.28 91.6 11.28 91.6 0.4 81.66 0.4 81.66 1 80.26 1 80.26 0.4 66.94 0.4 66.94 1 65.54 1 65.54 0.4 52.22 0.4 52.22 1 50.82 1 50.82 0.4 37.5 0.4 37.5 1 36.1 1 36.1 0.4 26.16 0.4 26.16 11.28 13.43 11.28 13.43 12.64 12.33 12.64 12.33 11.28 11.74 11.28 11.74 11.88 10.34 11.88 10.34 11.28 9.75 11.28 9.75 12.64 8.65 12.64 8.65 11.28 5.15 11.28 5.15 12.64 4.05 12.64 4.05 11.28 0.4 11.28 0.4 97.52 10.34 97.52 10.34 96.92 11.74 96.92 11.74 97.52 36.1 97.52 36.1 96.92 37.5 96.92 37.5 97.52 50.82 97.52 50.82 96.92 52.22 96.92 52.22 97.52 65.54 97.52 65.54 96.92 66.94 96.92 66.94 97.52 80.26 97.52 80.26 96.92 81.66 96.92 81.66 97.52 106.02 97.52 106.02 96.92 107.42 96.92 107.42 97.52 ; - LAYER met5 ; - POLYGON 116.16 96.32 116.16 88.2 112.96 88.2 112.96 81.8 116.16 81.8 116.16 67.8 112.96 67.8 112.96 61.4 116.16 61.4 116.16 47.4 112.96 47.4 112.96 41 116.16 41 116.16 27 112.96 27 112.96 20.6 116.16 20.6 116.16 12.48 90.4 12.48 90.4 1.6 27.36 1.6 27.36 12.48 1.6 12.48 1.6 20.6 4.8 20.6 4.8 27 1.6 27 1.6 41 4.8 41 4.8 47.4 1.6 47.4 1.6 61.4 4.8 61.4 4.8 67.8 1.6 67.8 1.6 81.8 4.8 81.8 4.8 88.2 1.6 88.2 1.6 96.32 ; - LAYER met1 ; - POLYGON 117.48 97.4 117.48 95.72 117 95.72 117 94.68 117.48 94.68 117.48 93 117 93 117 91.96 117.48 91.96 117.48 90.28 117 90.28 117 89.24 117.48 89.24 117.48 87.56 117 87.56 117 86.52 117.48 86.52 117.48 84.84 117 84.84 117 83.8 117.48 83.8 117.48 82.12 117 82.12 117 81.08 117.48 81.08 117.48 79.4 117 79.4 117 78.36 117.48 78.36 117.48 76.68 117 76.68 117 75.64 117.48 75.64 117.48 73.96 117 73.96 117 72.92 117.48 72.92 117.48 71.24 117 71.24 117 70.2 117.48 70.2 117.48 68.52 117 68.52 117 67.48 117.48 67.48 117.48 65.8 117 65.8 117 64.76 117.48 64.76 117.48 63.08 117 63.08 117 62.04 117.48 62.04 117.48 60.36 117 60.36 117 59.32 117.48 59.32 117.48 57.64 117 57.64 117 56.6 117.48 56.6 117.48 54.92 117 54.92 117 53.88 117.48 53.88 117.48 52.2 117 52.2 117 51.16 117.48 51.16 117.48 49.48 117 49.48 117 48.44 117.48 48.44 117.48 46.76 117 46.76 117 45.72 117.48 45.72 117.48 44.04 117 44.04 117 43 117.48 43 117.48 41.32 117 41.32 117 40.28 117.48 40.28 117.48 38.6 117 38.6 117 37.56 117.48 37.56 117.48 35.88 117 35.88 117 34.84 117.48 34.84 117.48 33.16 117 33.16 117 32.12 117.48 32.12 117.48 30.44 117 30.44 117 29.4 117.48 29.4 117.48 27.72 117 27.72 117 26.68 117.48 26.68 117.48 25 117 25 117 23.96 117.48 23.96 117.48 22.28 117 22.28 117 21.24 117.48 21.24 117.48 19.56 117 19.56 117 18.52 117.48 18.52 117.48 16.84 117 16.84 117 15.8 117.48 15.8 117.48 14.12 117 14.12 117 13.08 117.48 13.08 117.48 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 0.76 81.08 0.76 82.12 0.28 82.12 0.28 83.8 0.76 83.8 0.76 84.84 0.28 84.84 0.28 86.52 0.76 86.52 0.76 87.56 0.28 87.56 0.28 89.24 0.76 89.24 0.76 90.28 0.28 90.28 0.28 91.96 0.76 91.96 0.76 93 0.28 93 0.28 94.68 0.76 94.68 0.76 95.72 0.28 95.72 0.28 97.4 ; - POLYGON 91.72 10.36 91.72 8.68 91.24 8.68 91.24 7.64 91.72 7.64 91.72 5.96 91.24 5.96 91.24 4.92 91.72 4.92 91.72 3.24 91.24 3.24 91.24 2.2 91.72 2.2 91.72 0.52 26.04 0.52 26.04 2.2 26.52 2.2 26.52 3.24 26.04 3.24 26.04 4.92 26.52 4.92 26.52 5.96 26.04 5.96 26.04 7.64 26.52 7.64 26.52 8.68 26.04 8.68 26.04 10.36 ; - LAYER li1 ; - POLYGON 117.59 97.75 117.59 11.05 91.83 11.05 91.83 0.17 25.93 0.17 25.93 11.05 0.17 11.05 0.17 97.75 ; - LAYER mcon ; - RECT 117.445 97.835 117.615 98.005 ; - RECT 116.985 97.835 117.155 98.005 ; - RECT 116.525 97.835 116.695 98.005 ; - RECT 116.065 97.835 116.235 98.005 ; - RECT 115.605 97.835 115.775 98.005 ; - RECT 115.145 97.835 115.315 98.005 ; - RECT 114.685 97.835 114.855 98.005 ; - RECT 114.225 97.835 114.395 98.005 ; - RECT 113.765 97.835 113.935 98.005 ; - RECT 113.305 97.835 113.475 98.005 ; - RECT 112.845 97.835 113.015 98.005 ; - RECT 112.385 97.835 112.555 98.005 ; - RECT 111.925 97.835 112.095 98.005 ; - RECT 111.465 97.835 111.635 98.005 ; - RECT 111.005 97.835 111.175 98.005 ; - RECT 110.545 97.835 110.715 98.005 ; - RECT 110.085 97.835 110.255 98.005 ; - RECT 109.625 97.835 109.795 98.005 ; - RECT 109.165 97.835 109.335 98.005 ; - RECT 108.705 97.835 108.875 98.005 ; - RECT 108.245 97.835 108.415 98.005 ; - RECT 107.785 97.835 107.955 98.005 ; - RECT 107.325 97.835 107.495 98.005 ; - RECT 106.865 97.835 107.035 98.005 ; - RECT 106.405 97.835 106.575 98.005 ; - RECT 105.945 97.835 106.115 98.005 ; - RECT 105.485 97.835 105.655 98.005 ; - RECT 105.025 97.835 105.195 98.005 ; - RECT 104.565 97.835 104.735 98.005 ; - RECT 104.105 97.835 104.275 98.005 ; - RECT 103.645 97.835 103.815 98.005 ; - RECT 103.185 97.835 103.355 98.005 ; - RECT 102.725 97.835 102.895 98.005 ; - RECT 102.265 97.835 102.435 98.005 ; - RECT 101.805 97.835 101.975 98.005 ; - RECT 101.345 97.835 101.515 98.005 ; - RECT 100.885 97.835 101.055 98.005 ; - RECT 100.425 97.835 100.595 98.005 ; - RECT 99.965 97.835 100.135 98.005 ; - RECT 99.505 97.835 99.675 98.005 ; - RECT 99.045 97.835 99.215 98.005 ; - RECT 98.585 97.835 98.755 98.005 ; - RECT 98.125 97.835 98.295 98.005 ; - RECT 97.665 97.835 97.835 98.005 ; - RECT 97.205 97.835 97.375 98.005 ; - RECT 96.745 97.835 96.915 98.005 ; - RECT 96.285 97.835 96.455 98.005 ; - RECT 95.825 97.835 95.995 98.005 ; - RECT 95.365 97.835 95.535 98.005 ; - RECT 94.905 97.835 95.075 98.005 ; - RECT 94.445 97.835 94.615 98.005 ; - RECT 93.985 97.835 94.155 98.005 ; - RECT 93.525 97.835 93.695 98.005 ; - RECT 93.065 97.835 93.235 98.005 ; - RECT 92.605 97.835 92.775 98.005 ; - RECT 92.145 97.835 92.315 98.005 ; - RECT 91.685 97.835 91.855 98.005 ; - RECT 91.225 97.835 91.395 98.005 ; - RECT 90.765 97.835 90.935 98.005 ; - RECT 90.305 97.835 90.475 98.005 ; - RECT 89.845 97.835 90.015 98.005 ; - RECT 89.385 97.835 89.555 98.005 ; - RECT 88.925 97.835 89.095 98.005 ; - RECT 88.465 97.835 88.635 98.005 ; - RECT 88.005 97.835 88.175 98.005 ; - RECT 87.545 97.835 87.715 98.005 ; - RECT 87.085 97.835 87.255 98.005 ; - RECT 86.625 97.835 86.795 98.005 ; - RECT 86.165 97.835 86.335 98.005 ; - RECT 85.705 97.835 85.875 98.005 ; - RECT 85.245 97.835 85.415 98.005 ; - RECT 84.785 97.835 84.955 98.005 ; - RECT 84.325 97.835 84.495 98.005 ; - RECT 83.865 97.835 84.035 98.005 ; - RECT 83.405 97.835 83.575 98.005 ; - RECT 82.945 97.835 83.115 98.005 ; - RECT 82.485 97.835 82.655 98.005 ; - RECT 82.025 97.835 82.195 98.005 ; - RECT 81.565 97.835 81.735 98.005 ; - RECT 81.105 97.835 81.275 98.005 ; - RECT 80.645 97.835 80.815 98.005 ; - RECT 80.185 97.835 80.355 98.005 ; - RECT 79.725 97.835 79.895 98.005 ; - RECT 79.265 97.835 79.435 98.005 ; - RECT 78.805 97.835 78.975 98.005 ; - RECT 78.345 97.835 78.515 98.005 ; - RECT 77.885 97.835 78.055 98.005 ; - RECT 77.425 97.835 77.595 98.005 ; - RECT 76.965 97.835 77.135 98.005 ; - RECT 76.505 97.835 76.675 98.005 ; - RECT 76.045 97.835 76.215 98.005 ; - RECT 75.585 97.835 75.755 98.005 ; - RECT 75.125 97.835 75.295 98.005 ; - RECT 74.665 97.835 74.835 98.005 ; - RECT 74.205 97.835 74.375 98.005 ; - RECT 73.745 97.835 73.915 98.005 ; - RECT 73.285 97.835 73.455 98.005 ; - RECT 72.825 97.835 72.995 98.005 ; - RECT 72.365 97.835 72.535 98.005 ; - RECT 71.905 97.835 72.075 98.005 ; - RECT 71.445 97.835 71.615 98.005 ; - RECT 70.985 97.835 71.155 98.005 ; - RECT 70.525 97.835 70.695 98.005 ; - RECT 70.065 97.835 70.235 98.005 ; - RECT 69.605 97.835 69.775 98.005 ; - RECT 69.145 97.835 69.315 98.005 ; - RECT 68.685 97.835 68.855 98.005 ; - RECT 68.225 97.835 68.395 98.005 ; - RECT 67.765 97.835 67.935 98.005 ; - RECT 67.305 97.835 67.475 98.005 ; - RECT 66.845 97.835 67.015 98.005 ; - RECT 66.385 97.835 66.555 98.005 ; - RECT 65.925 97.835 66.095 98.005 ; - RECT 65.465 97.835 65.635 98.005 ; - RECT 65.005 97.835 65.175 98.005 ; - RECT 64.545 97.835 64.715 98.005 ; - RECT 64.085 97.835 64.255 98.005 ; - RECT 63.625 97.835 63.795 98.005 ; - RECT 63.165 97.835 63.335 98.005 ; - RECT 62.705 97.835 62.875 98.005 ; - RECT 62.245 97.835 62.415 98.005 ; - RECT 61.785 97.835 61.955 98.005 ; - RECT 61.325 97.835 61.495 98.005 ; - RECT 60.865 97.835 61.035 98.005 ; - RECT 60.405 97.835 60.575 98.005 ; - RECT 59.945 97.835 60.115 98.005 ; - RECT 59.485 97.835 59.655 98.005 ; - RECT 59.025 97.835 59.195 98.005 ; - RECT 58.565 97.835 58.735 98.005 ; - RECT 58.105 97.835 58.275 98.005 ; - RECT 57.645 97.835 57.815 98.005 ; - RECT 57.185 97.835 57.355 98.005 ; - RECT 56.725 97.835 56.895 98.005 ; - RECT 56.265 97.835 56.435 98.005 ; - RECT 55.805 97.835 55.975 98.005 ; - RECT 55.345 97.835 55.515 98.005 ; - RECT 54.885 97.835 55.055 98.005 ; - RECT 54.425 97.835 54.595 98.005 ; - RECT 53.965 97.835 54.135 98.005 ; - RECT 53.505 97.835 53.675 98.005 ; - RECT 53.045 97.835 53.215 98.005 ; - RECT 52.585 97.835 52.755 98.005 ; - RECT 52.125 97.835 52.295 98.005 ; - RECT 51.665 97.835 51.835 98.005 ; - RECT 51.205 97.835 51.375 98.005 ; - RECT 50.745 97.835 50.915 98.005 ; - RECT 50.285 97.835 50.455 98.005 ; - RECT 49.825 97.835 49.995 98.005 ; - RECT 49.365 97.835 49.535 98.005 ; - RECT 48.905 97.835 49.075 98.005 ; - RECT 48.445 97.835 48.615 98.005 ; - RECT 47.985 97.835 48.155 98.005 ; - RECT 47.525 97.835 47.695 98.005 ; - RECT 47.065 97.835 47.235 98.005 ; - RECT 46.605 97.835 46.775 98.005 ; - RECT 46.145 97.835 46.315 98.005 ; - RECT 45.685 97.835 45.855 98.005 ; - RECT 45.225 97.835 45.395 98.005 ; - RECT 44.765 97.835 44.935 98.005 ; - RECT 44.305 97.835 44.475 98.005 ; - RECT 43.845 97.835 44.015 98.005 ; - RECT 43.385 97.835 43.555 98.005 ; - RECT 42.925 97.835 43.095 98.005 ; - RECT 42.465 97.835 42.635 98.005 ; - RECT 42.005 97.835 42.175 98.005 ; - RECT 41.545 97.835 41.715 98.005 ; - RECT 41.085 97.835 41.255 98.005 ; - RECT 40.625 97.835 40.795 98.005 ; - RECT 40.165 97.835 40.335 98.005 ; - RECT 39.705 97.835 39.875 98.005 ; - RECT 39.245 97.835 39.415 98.005 ; - RECT 38.785 97.835 38.955 98.005 ; - RECT 38.325 97.835 38.495 98.005 ; - RECT 37.865 97.835 38.035 98.005 ; - RECT 37.405 97.835 37.575 98.005 ; - RECT 36.945 97.835 37.115 98.005 ; - RECT 36.485 97.835 36.655 98.005 ; - RECT 36.025 97.835 36.195 98.005 ; - RECT 35.565 97.835 35.735 98.005 ; - RECT 35.105 97.835 35.275 98.005 ; - RECT 34.645 97.835 34.815 98.005 ; - RECT 34.185 97.835 34.355 98.005 ; - RECT 33.725 97.835 33.895 98.005 ; - RECT 33.265 97.835 33.435 98.005 ; - RECT 32.805 97.835 32.975 98.005 ; - RECT 32.345 97.835 32.515 98.005 ; - RECT 31.885 97.835 32.055 98.005 ; - RECT 31.425 97.835 31.595 98.005 ; - RECT 30.965 97.835 31.135 98.005 ; - RECT 30.505 97.835 30.675 98.005 ; - RECT 30.045 97.835 30.215 98.005 ; - RECT 29.585 97.835 29.755 98.005 ; - RECT 29.125 97.835 29.295 98.005 ; - RECT 28.665 97.835 28.835 98.005 ; - RECT 28.205 97.835 28.375 98.005 ; - RECT 27.745 97.835 27.915 98.005 ; - RECT 27.285 97.835 27.455 98.005 ; - RECT 26.825 97.835 26.995 98.005 ; - RECT 26.365 97.835 26.535 98.005 ; - RECT 25.905 97.835 26.075 98.005 ; - RECT 25.445 97.835 25.615 98.005 ; - RECT 24.985 97.835 25.155 98.005 ; - RECT 24.525 97.835 24.695 98.005 ; - RECT 24.065 97.835 24.235 98.005 ; - RECT 23.605 97.835 23.775 98.005 ; - RECT 23.145 97.835 23.315 98.005 ; - RECT 22.685 97.835 22.855 98.005 ; - RECT 22.225 97.835 22.395 98.005 ; - RECT 21.765 97.835 21.935 98.005 ; - RECT 21.305 97.835 21.475 98.005 ; - RECT 20.845 97.835 21.015 98.005 ; - RECT 20.385 97.835 20.555 98.005 ; - RECT 19.925 97.835 20.095 98.005 ; - RECT 19.465 97.835 19.635 98.005 ; - RECT 19.005 97.835 19.175 98.005 ; - RECT 18.545 97.835 18.715 98.005 ; - RECT 18.085 97.835 18.255 98.005 ; - RECT 17.625 97.835 17.795 98.005 ; - RECT 17.165 97.835 17.335 98.005 ; - RECT 16.705 97.835 16.875 98.005 ; - RECT 16.245 97.835 16.415 98.005 ; - RECT 15.785 97.835 15.955 98.005 ; - RECT 15.325 97.835 15.495 98.005 ; - RECT 14.865 97.835 15.035 98.005 ; - RECT 14.405 97.835 14.575 98.005 ; - RECT 13.945 97.835 14.115 98.005 ; - RECT 13.485 97.835 13.655 98.005 ; - RECT 13.025 97.835 13.195 98.005 ; - RECT 12.565 97.835 12.735 98.005 ; - RECT 12.105 97.835 12.275 98.005 ; - RECT 11.645 97.835 11.815 98.005 ; - RECT 11.185 97.835 11.355 98.005 ; - RECT 10.725 97.835 10.895 98.005 ; - RECT 10.265 97.835 10.435 98.005 ; - RECT 9.805 97.835 9.975 98.005 ; - RECT 9.345 97.835 9.515 98.005 ; - RECT 8.885 97.835 9.055 98.005 ; - RECT 8.425 97.835 8.595 98.005 ; - RECT 7.965 97.835 8.135 98.005 ; - RECT 7.505 97.835 7.675 98.005 ; - RECT 7.045 97.835 7.215 98.005 ; - RECT 6.585 97.835 6.755 98.005 ; - RECT 6.125 97.835 6.295 98.005 ; - RECT 5.665 97.835 5.835 98.005 ; - RECT 5.205 97.835 5.375 98.005 ; - RECT 4.745 97.835 4.915 98.005 ; - RECT 4.285 97.835 4.455 98.005 ; - RECT 3.825 97.835 3.995 98.005 ; - RECT 3.365 97.835 3.535 98.005 ; - RECT 2.905 97.835 3.075 98.005 ; - RECT 2.445 97.835 2.615 98.005 ; - RECT 1.985 97.835 2.155 98.005 ; - RECT 1.525 97.835 1.695 98.005 ; - RECT 1.065 97.835 1.235 98.005 ; - RECT 0.605 97.835 0.775 98.005 ; - RECT 0.145 97.835 0.315 98.005 ; - RECT 117.445 95.115 117.615 95.285 ; - RECT 116.985 95.115 117.155 95.285 ; - RECT 0.605 95.115 0.775 95.285 ; - RECT 0.145 95.115 0.315 95.285 ; - RECT 117.445 92.395 117.615 92.565 ; - RECT 116.985 92.395 117.155 92.565 ; - RECT 0.605 92.395 0.775 92.565 ; - RECT 0.145 92.395 0.315 92.565 ; - RECT 117.445 89.675 117.615 89.845 ; - RECT 116.985 89.675 117.155 89.845 ; - RECT 0.605 89.675 0.775 89.845 ; - RECT 0.145 89.675 0.315 89.845 ; - RECT 117.445 86.955 117.615 87.125 ; - RECT 116.985 86.955 117.155 87.125 ; - RECT 0.605 86.955 0.775 87.125 ; - RECT 0.145 86.955 0.315 87.125 ; - RECT 117.445 84.235 117.615 84.405 ; - RECT 116.985 84.235 117.155 84.405 ; - RECT 0.605 84.235 0.775 84.405 ; - RECT 0.145 84.235 0.315 84.405 ; - RECT 117.445 81.515 117.615 81.685 ; - RECT 116.985 81.515 117.155 81.685 ; - RECT 0.605 81.515 0.775 81.685 ; - RECT 0.145 81.515 0.315 81.685 ; - RECT 117.445 78.795 117.615 78.965 ; - RECT 116.985 78.795 117.155 78.965 ; - RECT 0.605 78.795 0.775 78.965 ; - RECT 0.145 78.795 0.315 78.965 ; - RECT 117.445 76.075 117.615 76.245 ; - RECT 116.985 76.075 117.155 76.245 ; - RECT 0.605 76.075 0.775 76.245 ; - RECT 0.145 76.075 0.315 76.245 ; - RECT 117.445 73.355 117.615 73.525 ; - RECT 116.985 73.355 117.155 73.525 ; - RECT 0.605 73.355 0.775 73.525 ; - RECT 0.145 73.355 0.315 73.525 ; - RECT 117.445 70.635 117.615 70.805 ; - RECT 116.985 70.635 117.155 70.805 ; - RECT 0.605 70.635 0.775 70.805 ; - RECT 0.145 70.635 0.315 70.805 ; - RECT 117.445 67.915 117.615 68.085 ; - RECT 116.985 67.915 117.155 68.085 ; - RECT 0.605 67.915 0.775 68.085 ; - RECT 0.145 67.915 0.315 68.085 ; - RECT 117.445 65.195 117.615 65.365 ; - RECT 116.985 65.195 117.155 65.365 ; - RECT 0.605 65.195 0.775 65.365 ; - RECT 0.145 65.195 0.315 65.365 ; - RECT 117.445 62.475 117.615 62.645 ; - RECT 116.985 62.475 117.155 62.645 ; - RECT 0.605 62.475 0.775 62.645 ; - RECT 0.145 62.475 0.315 62.645 ; - RECT 117.445 59.755 117.615 59.925 ; - RECT 116.985 59.755 117.155 59.925 ; - RECT 0.605 59.755 0.775 59.925 ; - RECT 0.145 59.755 0.315 59.925 ; - RECT 117.445 57.035 117.615 57.205 ; - RECT 116.985 57.035 117.155 57.205 ; - RECT 0.605 57.035 0.775 57.205 ; - RECT 0.145 57.035 0.315 57.205 ; - RECT 117.445 54.315 117.615 54.485 ; - RECT 116.985 54.315 117.155 54.485 ; - RECT 0.605 54.315 0.775 54.485 ; - RECT 0.145 54.315 0.315 54.485 ; - RECT 117.445 51.595 117.615 51.765 ; - RECT 116.985 51.595 117.155 51.765 ; - RECT 0.605 51.595 0.775 51.765 ; - RECT 0.145 51.595 0.315 51.765 ; - RECT 117.445 48.875 117.615 49.045 ; - RECT 116.985 48.875 117.155 49.045 ; - RECT 0.605 48.875 0.775 49.045 ; - RECT 0.145 48.875 0.315 49.045 ; - RECT 117.445 46.155 117.615 46.325 ; - RECT 116.985 46.155 117.155 46.325 ; - RECT 0.605 46.155 0.775 46.325 ; - RECT 0.145 46.155 0.315 46.325 ; - RECT 117.445 43.435 117.615 43.605 ; - RECT 116.985 43.435 117.155 43.605 ; - RECT 0.605 43.435 0.775 43.605 ; - RECT 0.145 43.435 0.315 43.605 ; - RECT 117.445 40.715 117.615 40.885 ; - RECT 116.985 40.715 117.155 40.885 ; - RECT 0.605 40.715 0.775 40.885 ; - RECT 0.145 40.715 0.315 40.885 ; - RECT 117.445 37.995 117.615 38.165 ; - RECT 116.985 37.995 117.155 38.165 ; - RECT 0.605 37.995 0.775 38.165 ; - RECT 0.145 37.995 0.315 38.165 ; - RECT 117.445 35.275 117.615 35.445 ; - RECT 116.985 35.275 117.155 35.445 ; - RECT 0.605 35.275 0.775 35.445 ; - RECT 0.145 35.275 0.315 35.445 ; - RECT 117.445 32.555 117.615 32.725 ; - RECT 116.985 32.555 117.155 32.725 ; - RECT 0.605 32.555 0.775 32.725 ; - RECT 0.145 32.555 0.315 32.725 ; - RECT 117.445 29.835 117.615 30.005 ; - RECT 116.985 29.835 117.155 30.005 ; - RECT 0.605 29.835 0.775 30.005 ; - RECT 0.145 29.835 0.315 30.005 ; - RECT 117.445 27.115 117.615 27.285 ; - RECT 116.985 27.115 117.155 27.285 ; - RECT 0.605 27.115 0.775 27.285 ; - RECT 0.145 27.115 0.315 27.285 ; - RECT 117.445 24.395 117.615 24.565 ; - RECT 116.985 24.395 117.155 24.565 ; - RECT 0.605 24.395 0.775 24.565 ; - RECT 0.145 24.395 0.315 24.565 ; - RECT 117.445 21.675 117.615 21.845 ; - RECT 116.985 21.675 117.155 21.845 ; - RECT 0.605 21.675 0.775 21.845 ; - RECT 0.145 21.675 0.315 21.845 ; - RECT 117.445 18.955 117.615 19.125 ; - RECT 116.985 18.955 117.155 19.125 ; - RECT 0.605 18.955 0.775 19.125 ; - RECT 0.145 18.955 0.315 19.125 ; - RECT 117.445 16.235 117.615 16.405 ; - RECT 116.985 16.235 117.155 16.405 ; - RECT 0.605 16.235 0.775 16.405 ; - RECT 0.145 16.235 0.315 16.405 ; - RECT 117.445 13.515 117.615 13.685 ; - RECT 116.985 13.515 117.155 13.685 ; - RECT 0.605 13.515 0.775 13.685 ; - RECT 0.145 13.515 0.315 13.685 ; - RECT 117.445 10.795 117.615 10.965 ; - RECT 116.985 10.795 117.155 10.965 ; - RECT 116.525 10.795 116.695 10.965 ; - RECT 116.065 10.795 116.235 10.965 ; - RECT 115.605 10.795 115.775 10.965 ; - RECT 115.145 10.795 115.315 10.965 ; - RECT 114.685 10.795 114.855 10.965 ; - RECT 114.225 10.795 114.395 10.965 ; - RECT 113.765 10.795 113.935 10.965 ; - RECT 113.305 10.795 113.475 10.965 ; - RECT 112.845 10.795 113.015 10.965 ; - RECT 112.385 10.795 112.555 10.965 ; - RECT 111.925 10.795 112.095 10.965 ; - RECT 111.465 10.795 111.635 10.965 ; - RECT 111.005 10.795 111.175 10.965 ; - RECT 110.545 10.795 110.715 10.965 ; - RECT 110.085 10.795 110.255 10.965 ; - RECT 109.625 10.795 109.795 10.965 ; - RECT 109.165 10.795 109.335 10.965 ; - RECT 108.705 10.795 108.875 10.965 ; - RECT 108.245 10.795 108.415 10.965 ; - RECT 107.785 10.795 107.955 10.965 ; - RECT 107.325 10.795 107.495 10.965 ; - RECT 106.865 10.795 107.035 10.965 ; - RECT 106.405 10.795 106.575 10.965 ; - RECT 105.945 10.795 106.115 10.965 ; - RECT 105.485 10.795 105.655 10.965 ; - RECT 105.025 10.795 105.195 10.965 ; - RECT 104.565 10.795 104.735 10.965 ; - RECT 104.105 10.795 104.275 10.965 ; - RECT 103.645 10.795 103.815 10.965 ; - RECT 103.185 10.795 103.355 10.965 ; - RECT 102.725 10.795 102.895 10.965 ; - RECT 102.265 10.795 102.435 10.965 ; - RECT 101.805 10.795 101.975 10.965 ; - RECT 101.345 10.795 101.515 10.965 ; - RECT 100.885 10.795 101.055 10.965 ; - RECT 100.425 10.795 100.595 10.965 ; - RECT 99.965 10.795 100.135 10.965 ; - RECT 99.505 10.795 99.675 10.965 ; - RECT 99.045 10.795 99.215 10.965 ; - RECT 98.585 10.795 98.755 10.965 ; - RECT 98.125 10.795 98.295 10.965 ; - RECT 97.665 10.795 97.835 10.965 ; - RECT 97.205 10.795 97.375 10.965 ; - RECT 96.745 10.795 96.915 10.965 ; - RECT 96.285 10.795 96.455 10.965 ; - RECT 95.825 10.795 95.995 10.965 ; - RECT 95.365 10.795 95.535 10.965 ; - RECT 94.905 10.795 95.075 10.965 ; - RECT 94.445 10.795 94.615 10.965 ; - RECT 93.985 10.795 94.155 10.965 ; - RECT 93.525 10.795 93.695 10.965 ; - RECT 93.065 10.795 93.235 10.965 ; - RECT 92.605 10.795 92.775 10.965 ; - RECT 92.145 10.795 92.315 10.965 ; - RECT 91.685 10.795 91.855 10.965 ; - RECT 91.225 10.795 91.395 10.965 ; - RECT 90.765 10.795 90.935 10.965 ; - RECT 90.305 10.795 90.475 10.965 ; - RECT 89.845 10.795 90.015 10.965 ; - RECT 89.385 10.795 89.555 10.965 ; - RECT 88.925 10.795 89.095 10.965 ; - RECT 88.465 10.795 88.635 10.965 ; - RECT 88.005 10.795 88.175 10.965 ; - RECT 87.545 10.795 87.715 10.965 ; - RECT 87.085 10.795 87.255 10.965 ; - RECT 86.625 10.795 86.795 10.965 ; - RECT 86.165 10.795 86.335 10.965 ; - RECT 85.705 10.795 85.875 10.965 ; - RECT 85.245 10.795 85.415 10.965 ; - RECT 84.785 10.795 84.955 10.965 ; - RECT 84.325 10.795 84.495 10.965 ; - RECT 83.865 10.795 84.035 10.965 ; - RECT 83.405 10.795 83.575 10.965 ; - RECT 82.945 10.795 83.115 10.965 ; - RECT 82.485 10.795 82.655 10.965 ; - RECT 82.025 10.795 82.195 10.965 ; - RECT 81.565 10.795 81.735 10.965 ; - RECT 81.105 10.795 81.275 10.965 ; - RECT 80.645 10.795 80.815 10.965 ; - RECT 80.185 10.795 80.355 10.965 ; - RECT 79.725 10.795 79.895 10.965 ; - RECT 79.265 10.795 79.435 10.965 ; - RECT 78.805 10.795 78.975 10.965 ; - RECT 78.345 10.795 78.515 10.965 ; - RECT 77.885 10.795 78.055 10.965 ; - RECT 77.425 10.795 77.595 10.965 ; - RECT 76.965 10.795 77.135 10.965 ; - RECT 76.505 10.795 76.675 10.965 ; - RECT 76.045 10.795 76.215 10.965 ; - RECT 75.585 10.795 75.755 10.965 ; - RECT 75.125 10.795 75.295 10.965 ; - RECT 74.665 10.795 74.835 10.965 ; - RECT 74.205 10.795 74.375 10.965 ; - RECT 73.745 10.795 73.915 10.965 ; - RECT 73.285 10.795 73.455 10.965 ; - RECT 72.825 10.795 72.995 10.965 ; - RECT 72.365 10.795 72.535 10.965 ; - RECT 71.905 10.795 72.075 10.965 ; - RECT 71.445 10.795 71.615 10.965 ; - RECT 70.985 10.795 71.155 10.965 ; - RECT 70.525 10.795 70.695 10.965 ; - RECT 70.065 10.795 70.235 10.965 ; - RECT 69.605 10.795 69.775 10.965 ; - RECT 69.145 10.795 69.315 10.965 ; - RECT 68.685 10.795 68.855 10.965 ; - RECT 68.225 10.795 68.395 10.965 ; - RECT 67.765 10.795 67.935 10.965 ; - RECT 67.305 10.795 67.475 10.965 ; - RECT 66.845 10.795 67.015 10.965 ; - RECT 66.385 10.795 66.555 10.965 ; - RECT 65.925 10.795 66.095 10.965 ; - RECT 65.465 10.795 65.635 10.965 ; - RECT 65.005 10.795 65.175 10.965 ; - RECT 64.545 10.795 64.715 10.965 ; - RECT 64.085 10.795 64.255 10.965 ; - RECT 63.625 10.795 63.795 10.965 ; - RECT 63.165 10.795 63.335 10.965 ; - RECT 62.705 10.795 62.875 10.965 ; - RECT 62.245 10.795 62.415 10.965 ; - RECT 61.785 10.795 61.955 10.965 ; - RECT 61.325 10.795 61.495 10.965 ; - RECT 60.865 10.795 61.035 10.965 ; - RECT 60.405 10.795 60.575 10.965 ; - RECT 59.945 10.795 60.115 10.965 ; - RECT 59.485 10.795 59.655 10.965 ; - RECT 59.025 10.795 59.195 10.965 ; - RECT 58.565 10.795 58.735 10.965 ; - RECT 58.105 10.795 58.275 10.965 ; - RECT 57.645 10.795 57.815 10.965 ; - RECT 57.185 10.795 57.355 10.965 ; - RECT 56.725 10.795 56.895 10.965 ; - RECT 56.265 10.795 56.435 10.965 ; - RECT 55.805 10.795 55.975 10.965 ; - RECT 55.345 10.795 55.515 10.965 ; - RECT 54.885 10.795 55.055 10.965 ; - RECT 54.425 10.795 54.595 10.965 ; - RECT 53.965 10.795 54.135 10.965 ; - RECT 53.505 10.795 53.675 10.965 ; - RECT 53.045 10.795 53.215 10.965 ; - RECT 52.585 10.795 52.755 10.965 ; - RECT 52.125 10.795 52.295 10.965 ; - RECT 51.665 10.795 51.835 10.965 ; - RECT 51.205 10.795 51.375 10.965 ; - RECT 50.745 10.795 50.915 10.965 ; - RECT 50.285 10.795 50.455 10.965 ; - RECT 49.825 10.795 49.995 10.965 ; - RECT 49.365 10.795 49.535 10.965 ; - RECT 48.905 10.795 49.075 10.965 ; - RECT 48.445 10.795 48.615 10.965 ; - RECT 47.985 10.795 48.155 10.965 ; - RECT 47.525 10.795 47.695 10.965 ; - RECT 47.065 10.795 47.235 10.965 ; - RECT 46.605 10.795 46.775 10.965 ; - RECT 46.145 10.795 46.315 10.965 ; - RECT 45.685 10.795 45.855 10.965 ; - RECT 45.225 10.795 45.395 10.965 ; - RECT 44.765 10.795 44.935 10.965 ; - RECT 44.305 10.795 44.475 10.965 ; - RECT 43.845 10.795 44.015 10.965 ; - RECT 43.385 10.795 43.555 10.965 ; - RECT 42.925 10.795 43.095 10.965 ; - RECT 42.465 10.795 42.635 10.965 ; - RECT 42.005 10.795 42.175 10.965 ; - RECT 41.545 10.795 41.715 10.965 ; - RECT 41.085 10.795 41.255 10.965 ; - RECT 40.625 10.795 40.795 10.965 ; - RECT 40.165 10.795 40.335 10.965 ; - RECT 39.705 10.795 39.875 10.965 ; - RECT 39.245 10.795 39.415 10.965 ; - RECT 38.785 10.795 38.955 10.965 ; - RECT 38.325 10.795 38.495 10.965 ; - RECT 37.865 10.795 38.035 10.965 ; - RECT 37.405 10.795 37.575 10.965 ; - RECT 36.945 10.795 37.115 10.965 ; - RECT 36.485 10.795 36.655 10.965 ; - RECT 36.025 10.795 36.195 10.965 ; - RECT 35.565 10.795 35.735 10.965 ; - RECT 35.105 10.795 35.275 10.965 ; - RECT 34.645 10.795 34.815 10.965 ; - RECT 34.185 10.795 34.355 10.965 ; - RECT 33.725 10.795 33.895 10.965 ; - RECT 33.265 10.795 33.435 10.965 ; - RECT 32.805 10.795 32.975 10.965 ; - RECT 32.345 10.795 32.515 10.965 ; - RECT 31.885 10.795 32.055 10.965 ; - RECT 31.425 10.795 31.595 10.965 ; - RECT 30.965 10.795 31.135 10.965 ; - RECT 30.505 10.795 30.675 10.965 ; - RECT 30.045 10.795 30.215 10.965 ; - RECT 29.585 10.795 29.755 10.965 ; - RECT 29.125 10.795 29.295 10.965 ; - RECT 28.665 10.795 28.835 10.965 ; - RECT 28.205 10.795 28.375 10.965 ; - RECT 27.745 10.795 27.915 10.965 ; - RECT 27.285 10.795 27.455 10.965 ; - RECT 26.825 10.795 26.995 10.965 ; - RECT 26.365 10.795 26.535 10.965 ; - RECT 25.905 10.795 26.075 10.965 ; - RECT 25.445 10.795 25.615 10.965 ; - RECT 24.985 10.795 25.155 10.965 ; - RECT 24.525 10.795 24.695 10.965 ; - RECT 24.065 10.795 24.235 10.965 ; - RECT 23.605 10.795 23.775 10.965 ; - RECT 23.145 10.795 23.315 10.965 ; - RECT 22.685 10.795 22.855 10.965 ; - RECT 22.225 10.795 22.395 10.965 ; - RECT 21.765 10.795 21.935 10.965 ; - RECT 21.305 10.795 21.475 10.965 ; - RECT 20.845 10.795 21.015 10.965 ; - RECT 20.385 10.795 20.555 10.965 ; - RECT 19.925 10.795 20.095 10.965 ; - RECT 19.465 10.795 19.635 10.965 ; - RECT 19.005 10.795 19.175 10.965 ; - RECT 18.545 10.795 18.715 10.965 ; - RECT 18.085 10.795 18.255 10.965 ; - RECT 17.625 10.795 17.795 10.965 ; - RECT 17.165 10.795 17.335 10.965 ; - RECT 16.705 10.795 16.875 10.965 ; - RECT 16.245 10.795 16.415 10.965 ; - RECT 15.785 10.795 15.955 10.965 ; - RECT 15.325 10.795 15.495 10.965 ; - RECT 14.865 10.795 15.035 10.965 ; - RECT 14.405 10.795 14.575 10.965 ; - RECT 13.945 10.795 14.115 10.965 ; - RECT 13.485 10.795 13.655 10.965 ; - RECT 13.025 10.795 13.195 10.965 ; - RECT 12.565 10.795 12.735 10.965 ; - RECT 12.105 10.795 12.275 10.965 ; - RECT 11.645 10.795 11.815 10.965 ; - RECT 11.185 10.795 11.355 10.965 ; - RECT 10.725 10.795 10.895 10.965 ; - RECT 10.265 10.795 10.435 10.965 ; - RECT 9.805 10.795 9.975 10.965 ; - RECT 9.345 10.795 9.515 10.965 ; - RECT 8.885 10.795 9.055 10.965 ; - RECT 8.425 10.795 8.595 10.965 ; - RECT 7.965 10.795 8.135 10.965 ; - RECT 7.505 10.795 7.675 10.965 ; - RECT 7.045 10.795 7.215 10.965 ; - RECT 6.585 10.795 6.755 10.965 ; - RECT 6.125 10.795 6.295 10.965 ; - RECT 5.665 10.795 5.835 10.965 ; - RECT 5.205 10.795 5.375 10.965 ; - RECT 4.745 10.795 4.915 10.965 ; - RECT 4.285 10.795 4.455 10.965 ; - RECT 3.825 10.795 3.995 10.965 ; - RECT 3.365 10.795 3.535 10.965 ; - RECT 2.905 10.795 3.075 10.965 ; - RECT 2.445 10.795 2.615 10.965 ; - RECT 1.985 10.795 2.155 10.965 ; - RECT 1.525 10.795 1.695 10.965 ; - RECT 1.065 10.795 1.235 10.965 ; - RECT 0.605 10.795 0.775 10.965 ; - RECT 0.145 10.795 0.315 10.965 ; - RECT 91.685 8.075 91.855 8.245 ; - RECT 91.225 8.075 91.395 8.245 ; - RECT 26.365 8.075 26.535 8.245 ; - RECT 25.905 8.075 26.075 8.245 ; - RECT 91.685 5.355 91.855 5.525 ; - RECT 91.225 5.355 91.395 5.525 ; - RECT 26.365 5.355 26.535 5.525 ; - RECT 25.905 5.355 26.075 5.525 ; - RECT 91.685 2.635 91.855 2.805 ; - RECT 91.225 2.635 91.395 2.805 ; - RECT 26.365 2.635 26.535 2.805 ; - RECT 25.905 2.635 26.075 2.805 ; - RECT 91.685 -0.085 91.855 0.085 ; - RECT 91.225 -0.085 91.395 0.085 ; - RECT 90.765 -0.085 90.935 0.085 ; - RECT 90.305 -0.085 90.475 0.085 ; - RECT 89.845 -0.085 90.015 0.085 ; - RECT 89.385 -0.085 89.555 0.085 ; - RECT 88.925 -0.085 89.095 0.085 ; - RECT 88.465 -0.085 88.635 0.085 ; - RECT 88.005 -0.085 88.175 0.085 ; - RECT 87.545 -0.085 87.715 0.085 ; - RECT 87.085 -0.085 87.255 0.085 ; - RECT 86.625 -0.085 86.795 0.085 ; - RECT 86.165 -0.085 86.335 0.085 ; - RECT 85.705 -0.085 85.875 0.085 ; - RECT 85.245 -0.085 85.415 0.085 ; - RECT 84.785 -0.085 84.955 0.085 ; - RECT 84.325 -0.085 84.495 0.085 ; - RECT 83.865 -0.085 84.035 0.085 ; - RECT 83.405 -0.085 83.575 0.085 ; - RECT 82.945 -0.085 83.115 0.085 ; - RECT 82.485 -0.085 82.655 0.085 ; - RECT 82.025 -0.085 82.195 0.085 ; - RECT 81.565 -0.085 81.735 0.085 ; - RECT 81.105 -0.085 81.275 0.085 ; - RECT 80.645 -0.085 80.815 0.085 ; - RECT 80.185 -0.085 80.355 0.085 ; - RECT 79.725 -0.085 79.895 0.085 ; - RECT 79.265 -0.085 79.435 0.085 ; - RECT 78.805 -0.085 78.975 0.085 ; - RECT 78.345 -0.085 78.515 0.085 ; - RECT 77.885 -0.085 78.055 0.085 ; - RECT 77.425 -0.085 77.595 0.085 ; - RECT 76.965 -0.085 77.135 0.085 ; - RECT 76.505 -0.085 76.675 0.085 ; - RECT 76.045 -0.085 76.215 0.085 ; - RECT 75.585 -0.085 75.755 0.085 ; - RECT 75.125 -0.085 75.295 0.085 ; - RECT 74.665 -0.085 74.835 0.085 ; - RECT 74.205 -0.085 74.375 0.085 ; - RECT 73.745 -0.085 73.915 0.085 ; - RECT 73.285 -0.085 73.455 0.085 ; - RECT 72.825 -0.085 72.995 0.085 ; - RECT 72.365 -0.085 72.535 0.085 ; - RECT 71.905 -0.085 72.075 0.085 ; - RECT 71.445 -0.085 71.615 0.085 ; - RECT 70.985 -0.085 71.155 0.085 ; - RECT 70.525 -0.085 70.695 0.085 ; - RECT 70.065 -0.085 70.235 0.085 ; - RECT 69.605 -0.085 69.775 0.085 ; - RECT 69.145 -0.085 69.315 0.085 ; - RECT 68.685 -0.085 68.855 0.085 ; - RECT 68.225 -0.085 68.395 0.085 ; - RECT 67.765 -0.085 67.935 0.085 ; - RECT 67.305 -0.085 67.475 0.085 ; - RECT 66.845 -0.085 67.015 0.085 ; - RECT 66.385 -0.085 66.555 0.085 ; - RECT 65.925 -0.085 66.095 0.085 ; - RECT 65.465 -0.085 65.635 0.085 ; - RECT 65.005 -0.085 65.175 0.085 ; - RECT 64.545 -0.085 64.715 0.085 ; - RECT 64.085 -0.085 64.255 0.085 ; - RECT 63.625 -0.085 63.795 0.085 ; - RECT 63.165 -0.085 63.335 0.085 ; - RECT 62.705 -0.085 62.875 0.085 ; - RECT 62.245 -0.085 62.415 0.085 ; - RECT 61.785 -0.085 61.955 0.085 ; - RECT 61.325 -0.085 61.495 0.085 ; - RECT 60.865 -0.085 61.035 0.085 ; - RECT 60.405 -0.085 60.575 0.085 ; - RECT 59.945 -0.085 60.115 0.085 ; - RECT 59.485 -0.085 59.655 0.085 ; - RECT 59.025 -0.085 59.195 0.085 ; - RECT 58.565 -0.085 58.735 0.085 ; - RECT 58.105 -0.085 58.275 0.085 ; - RECT 57.645 -0.085 57.815 0.085 ; - RECT 57.185 -0.085 57.355 0.085 ; - RECT 56.725 -0.085 56.895 0.085 ; - RECT 56.265 -0.085 56.435 0.085 ; - RECT 55.805 -0.085 55.975 0.085 ; - RECT 55.345 -0.085 55.515 0.085 ; - RECT 54.885 -0.085 55.055 0.085 ; - RECT 54.425 -0.085 54.595 0.085 ; - RECT 53.965 -0.085 54.135 0.085 ; - RECT 53.505 -0.085 53.675 0.085 ; - RECT 53.045 -0.085 53.215 0.085 ; - RECT 52.585 -0.085 52.755 0.085 ; - RECT 52.125 -0.085 52.295 0.085 ; - RECT 51.665 -0.085 51.835 0.085 ; - RECT 51.205 -0.085 51.375 0.085 ; - RECT 50.745 -0.085 50.915 0.085 ; - RECT 50.285 -0.085 50.455 0.085 ; - RECT 49.825 -0.085 49.995 0.085 ; - RECT 49.365 -0.085 49.535 0.085 ; - RECT 48.905 -0.085 49.075 0.085 ; - RECT 48.445 -0.085 48.615 0.085 ; - RECT 47.985 -0.085 48.155 0.085 ; - RECT 47.525 -0.085 47.695 0.085 ; - RECT 47.065 -0.085 47.235 0.085 ; - RECT 46.605 -0.085 46.775 0.085 ; - RECT 46.145 -0.085 46.315 0.085 ; - RECT 45.685 -0.085 45.855 0.085 ; - RECT 45.225 -0.085 45.395 0.085 ; - RECT 44.765 -0.085 44.935 0.085 ; - RECT 44.305 -0.085 44.475 0.085 ; - RECT 43.845 -0.085 44.015 0.085 ; - RECT 43.385 -0.085 43.555 0.085 ; - RECT 42.925 -0.085 43.095 0.085 ; - RECT 42.465 -0.085 42.635 0.085 ; - RECT 42.005 -0.085 42.175 0.085 ; - RECT 41.545 -0.085 41.715 0.085 ; - RECT 41.085 -0.085 41.255 0.085 ; - RECT 40.625 -0.085 40.795 0.085 ; - RECT 40.165 -0.085 40.335 0.085 ; - RECT 39.705 -0.085 39.875 0.085 ; - RECT 39.245 -0.085 39.415 0.085 ; - RECT 38.785 -0.085 38.955 0.085 ; - RECT 38.325 -0.085 38.495 0.085 ; - RECT 37.865 -0.085 38.035 0.085 ; - RECT 37.405 -0.085 37.575 0.085 ; - RECT 36.945 -0.085 37.115 0.085 ; - RECT 36.485 -0.085 36.655 0.085 ; - RECT 36.025 -0.085 36.195 0.085 ; - RECT 35.565 -0.085 35.735 0.085 ; - RECT 35.105 -0.085 35.275 0.085 ; - RECT 34.645 -0.085 34.815 0.085 ; - RECT 34.185 -0.085 34.355 0.085 ; - RECT 33.725 -0.085 33.895 0.085 ; - RECT 33.265 -0.085 33.435 0.085 ; - RECT 32.805 -0.085 32.975 0.085 ; - RECT 32.345 -0.085 32.515 0.085 ; - RECT 31.885 -0.085 32.055 0.085 ; - RECT 31.425 -0.085 31.595 0.085 ; - RECT 30.965 -0.085 31.135 0.085 ; - RECT 30.505 -0.085 30.675 0.085 ; - RECT 30.045 -0.085 30.215 0.085 ; - RECT 29.585 -0.085 29.755 0.085 ; - RECT 29.125 -0.085 29.295 0.085 ; - RECT 28.665 -0.085 28.835 0.085 ; - RECT 28.205 -0.085 28.375 0.085 ; - RECT 27.745 -0.085 27.915 0.085 ; - RECT 27.285 -0.085 27.455 0.085 ; - RECT 26.825 -0.085 26.995 0.085 ; - RECT 26.365 -0.085 26.535 0.085 ; - RECT 25.905 -0.085 26.075 0.085 ; - LAYER via ; - RECT 80.885 97.845 81.035 97.995 ; - RECT 51.445 97.845 51.595 97.995 ; - RECT 10.965 97.845 11.115 97.995 ; - RECT 62.485 96.145 62.635 96.295 ; - RECT 60.645 96.145 60.795 96.295 ; - RECT 110.785 12.505 110.935 12.655 ; - RECT 7.285 12.505 7.435 12.655 ; - RECT 2.225 12.505 2.375 12.655 ; - RECT 80.885 10.805 81.035 10.955 ; - RECT 51.445 10.805 51.595 10.955 ; - RECT 10.965 10.805 11.115 10.955 ; - RECT 76.285 1.625 76.435 1.775 ; - RECT 66.165 1.625 66.315 1.775 ; - RECT 80.885 -0.075 81.035 0.075 ; - RECT 51.445 -0.075 51.595 0.075 ; - LAYER via2 ; - RECT 80.86 97.82 81.06 98.02 ; - RECT 51.42 97.82 51.62 98.02 ; - RECT 10.94 97.82 11.14 98.02 ; - RECT 116.28 69.94 116.48 70.14 ; - RECT 115.82 64.5 116.02 64.7 ; - RECT 115.82 46.82 116.02 47.02 ; - RECT 1.28 40.02 1.48 40.22 ; - RECT 115.82 37.98 116.02 38.18 ; - RECT 1.74 37.3 1.94 37.5 ; - RECT 1.28 31.86 1.48 32.06 ; - RECT 1.28 14.86 1.48 15.06 ; - RECT 10.94 10.78 11.14 10.98 ; - RECT 80.86 -0.1 81.06 0.1 ; - RECT 51.42 -0.1 51.62 0.1 ; - LAYER via3 ; - RECT 80.86 97.82 81.06 98.02 ; - RECT 51.42 97.82 51.62 98.02 ; - RECT 10.94 97.82 11.14 98.02 ; - RECT 10.94 10.78 11.14 10.98 ; - RECT 80.86 -0.1 81.06 0.1 ; - RECT 51.42 -0.1 51.62 0.1 ; - LAYER OVERLAP ; - POLYGON 25.76 0 25.76 10.88 0 10.88 0 97.92 117.76 97.92 117.76 10.88 92 10.88 92 0 ; - END -END sb_1__2_ - -END LIBRARY diff --git a/FPGA22_HIER_SKY_PNR/modules/lef/sb_2__0__icv_in_design.lef b/FPGA22_HIER_SKY_PNR/modules/lef/sb_2__0__icv_in_design.lef deleted file mode 100644 index 42599b3..0000000 --- a/FPGA22_HIER_SKY_PNR/modules/lef/sb_2__0__icv_in_design.lef +++ /dev/null @@ -1,2071 +0,0 @@ -VERSION 5.7 ; -BUSBITCHARS "[]" ; - -UNITS - DATABASE MICRONS 1000 ; -END UNITS - -MANUFACTURINGGRID 0.005 ; - -LAYER li1 - TYPE ROUTING ; - DIRECTION VERTICAL ; - PITCH 0.46 ; - WIDTH 0.17 ; -END li1 - -LAYER mcon - TYPE CUT ; -END mcon - -LAYER met1 - TYPE ROUTING ; - DIRECTION HORIZONTAL ; - PITCH 0.34 ; - WIDTH 0.14 ; -END met1 - -LAYER via - TYPE CUT ; -END via - -LAYER met2 - TYPE ROUTING ; - DIRECTION VERTICAL ; - PITCH 0.46 ; - WIDTH 0.14 ; -END met2 - -LAYER via2 - TYPE CUT ; -END via2 - -LAYER met3 - TYPE ROUTING ; - DIRECTION HORIZONTAL ; - PITCH 0.68 ; - WIDTH 0.3 ; -END met3 - -LAYER via3 - TYPE CUT ; -END via3 - -LAYER met4 - TYPE ROUTING ; - DIRECTION VERTICAL ; - PITCH 0.92 ; - WIDTH 0.3 ; -END met4 - -LAYER via4 - TYPE CUT ; -END via4 - -LAYER met5 - TYPE ROUTING ; - DIRECTION HORIZONTAL ; - PITCH 3.4 ; - WIDTH 1.6 ; -END met5 - -LAYER nwell - TYPE MASTERSLICE ; -END nwell - -LAYER pwell - TYPE MASTERSLICE ; -END pwell - -LAYER OVERLAP - TYPE OVERLAP ; -END OVERLAP - -VIA L1M1_PR - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.145 -0.115 0.145 0.115 ; -END L1M1_PR - -VIA L1M1_PR_R - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.115 -0.145 0.115 0.145 ; -END L1M1_PR_R - -VIA L1M1_PR_M - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.115 -0.145 0.115 0.145 ; -END L1M1_PR_M - -VIA L1M1_PR_MR - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.145 -0.115 0.145 0.115 ; -END L1M1_PR_MR - -VIA L1M1_PR_C - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.145 -0.145 0.145 0.145 ; -END L1M1_PR_C - -VIA M1M2_PR - LAYER met1 ; - RECT -0.16 -0.13 0.16 0.13 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.13 -0.16 0.13 0.16 ; -END M1M2_PR - -VIA M1M2_PR_Enc - LAYER met1 ; - RECT -0.16 -0.13 0.16 0.13 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.16 -0.13 0.16 0.13 ; -END M1M2_PR_Enc - -VIA M1M2_PR_R - LAYER met1 ; - RECT -0.13 -0.16 0.13 0.16 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.16 -0.13 0.16 0.13 ; -END M1M2_PR_R - -VIA M1M2_PR_R_Enc - LAYER met1 ; - RECT -0.13 -0.16 0.13 0.16 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.13 -0.16 0.13 0.16 ; -END M1M2_PR_R_Enc - -VIA M1M2_PR_M - LAYER met1 ; - RECT -0.16 -0.13 0.16 0.13 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.16 -0.13 0.16 0.13 ; -END M1M2_PR_M - -VIA M1M2_PR_M_Enc - LAYER met1 ; - RECT -0.16 -0.13 0.16 0.13 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.13 -0.16 0.13 0.16 ; -END M1M2_PR_M_Enc - -VIA M1M2_PR_MR - LAYER met1 ; - RECT -0.13 -0.16 0.13 0.16 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.13 -0.16 0.13 0.16 ; -END M1M2_PR_MR - -VIA M1M2_PR_MR_Enc - LAYER met1 ; - RECT -0.13 -0.16 0.13 0.16 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.16 -0.13 0.16 0.13 ; -END M1M2_PR_MR_Enc - -VIA M1M2_PR_C - LAYER met1 ; - RECT -0.16 -0.16 0.16 0.16 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.16 -0.16 0.16 0.16 ; -END M1M2_PR_C - -VIA M2M3_PR - LAYER met2 ; - RECT -0.14 -0.185 0.14 0.185 ; - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met3 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M2M3_PR - -VIA M2M3_PR_R - LAYER met2 ; - RECT -0.185 -0.14 0.185 0.14 ; - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met3 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M2M3_PR_R - -VIA M2M3_PR_M - LAYER met2 ; - RECT -0.14 -0.185 0.14 0.185 ; - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met3 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M2M3_PR_M - -VIA M2M3_PR_MR - LAYER met2 ; - RECT -0.185 -0.14 0.185 0.14 ; - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met3 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M2M3_PR_MR - -VIA M2M3_PR_C - LAYER met2 ; - RECT -0.185 -0.185 0.185 0.185 ; - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met3 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M2M3_PR_C - -VIA M3M4_PR - LAYER met3 ; - RECT -0.19 -0.16 0.19 0.16 ; - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR - -VIA M3M4_PR_R - LAYER met3 ; - RECT -0.16 -0.19 0.16 0.19 ; - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR_R - -VIA M3M4_PR_M - LAYER met3 ; - RECT -0.19 -0.16 0.19 0.16 ; - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR_M - -VIA M3M4_PR_MR - LAYER met3 ; - RECT -0.16 -0.19 0.16 0.19 ; - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR_MR - -VIA M3M4_PR_C - LAYER met3 ; - RECT -0.19 -0.19 0.19 0.19 ; - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR_C - -VIA M4M5_PR - LAYER met4 ; - RECT -0.59 -0.59 0.59 0.59 ; - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - LAYER met5 ; - RECT -0.71 -0.71 0.71 0.71 ; -END M4M5_PR - -VIA M4M5_PR_R - LAYER met4 ; - RECT -0.59 -0.59 0.59 0.59 ; - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - LAYER met5 ; - RECT -0.71 -0.71 0.71 0.71 ; -END M4M5_PR_R - -VIA M4M5_PR_M - LAYER met4 ; - RECT -0.59 -0.59 0.59 0.59 ; - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - LAYER met5 ; - RECT -0.71 -0.71 0.71 0.71 ; -END M4M5_PR_M - -VIA M4M5_PR_MR - LAYER met4 ; - RECT -0.59 -0.59 0.59 0.59 ; - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - LAYER met5 ; - RECT -0.71 -0.71 0.71 0.71 ; -END M4M5_PR_MR - -VIA M4M5_PR_C - LAYER met4 ; - RECT -0.59 -0.59 0.59 0.59 ; - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - LAYER met5 ; - RECT -0.71 -0.71 0.71 0.71 ; -END M4M5_PR_C - -SITE unit - CLASS CORE ; - SYMMETRY Y ; - SIZE 0.46 BY 2.72 ; -END unit - -SITE unithddbl - CLASS CORE ; - SIZE 0.46 BY 5.44 ; -END unithddbl - -MACRO sb_2__0_ - CLASS BLOCK ; - ORIGIN 0 0 ; - SIZE 92 BY 97.92 ; - SYMMETRY X Y ; - PIN prog_clk[0] - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER met3 ; - RECT 0 13.45 1.38 13.75 ; - END - END prog_clk[0] - PIN chany_top_in[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 59.27 96.56 59.41 97.92 ; - END - END chany_top_in[0] - PIN chany_top_in[1] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 63.33 96.56 63.63 97.92 ; - END - END chany_top_in[1] - PIN chany_top_in[2] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 72.53 96.56 72.83 97.92 ; - END - END chany_top_in[2] - PIN chany_top_in[3] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 52.37 96.56 52.51 97.92 ; - END - END chany_top_in[3] - PIN chany_top_in[4] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 67.55 96.56 67.69 97.92 ; - END - END chany_top_in[4] - PIN chany_top_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 64.79 96.56 64.93 97.92 ; - END - END chany_top_in[5] - PIN chany_top_in[6] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 73.07 96.56 73.21 97.92 ; - END - END chany_top_in[6] - PIN chany_top_in[7] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 48.69 96.56 48.83 97.92 ; - END - END chany_top_in[7] - PIN chany_top_in[8] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 56.05 96.56 56.19 97.92 ; - END - END chany_top_in[8] - PIN chany_top_in[9] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 59.65 96.56 59.95 97.92 ; - END - END chany_top_in[9] - PIN chany_top_in[10] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 53.21 96.56 53.51 97.92 ; - END - END chany_top_in[10] - PIN chany_top_in[11] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 46.85 96.56 46.99 97.92 ; - END - END chany_top_in[11] - PIN chany_top_in[12] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 49.61 96.56 49.75 97.92 ; - END - END chany_top_in[12] - PIN chany_top_in[13] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 43.63 96.56 43.77 97.92 ; - END - END chany_top_in[13] - PIN chany_top_in[14] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 69.39 96.56 69.53 97.92 ; - END - END chany_top_in[14] - PIN chany_top_in[15] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 61.11 96.56 61.25 97.92 ; - END - END chany_top_in[15] - PIN chany_top_in[16] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 68.47 96.56 68.61 97.92 ; - END - END chany_top_in[16] - PIN chany_top_in[17] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 73.99 96.56 74.13 97.92 ; - END - END chany_top_in[17] - PIN chany_top_in[18] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 71.23 96.56 71.37 97.92 ; - END - END chany_top_in[18] - PIN chany_top_in[19] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 65.71 96.56 65.85 97.92 ; - END - END chany_top_in[19] - PIN top_left_grid_pin_42_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 9.13 85.68 9.27 87.04 ; - END - END top_left_grid_pin_42_[0] - PIN top_left_grid_pin_43_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 6.83 85.68 6.97 87.04 ; - END - END top_left_grid_pin_43_[0] - PIN top_left_grid_pin_44_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 12.81 85.68 12.95 87.04 ; - END - END top_left_grid_pin_44_[0] - PIN top_left_grid_pin_45_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 18.33 85.68 18.47 87.04 ; - END - END top_left_grid_pin_45_[0] - PIN top_left_grid_pin_46_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 14.19 85.68 14.33 87.04 ; - END - END top_left_grid_pin_46_[0] - PIN top_left_grid_pin_47_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 7.75 85.68 7.89 87.04 ; - END - END top_left_grid_pin_47_[0] - PIN top_left_grid_pin_48_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 16.03 85.68 16.17 87.04 ; - END - END top_left_grid_pin_48_[0] - PIN top_left_grid_pin_49_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 18.25 85.68 18.55 87.04 ; - END - END top_left_grid_pin_49_[0] - PIN top_right_grid_pin_1_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 54.21 96.56 54.35 97.92 ; - END - END top_right_grid_pin_1_[0] - PIN chanx_left_in[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 11.41 1.38 11.71 ; - END - END chanx_left_in[0] - PIN chanx_left_in[1] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 66.49 1.38 66.79 ; - END - END chanx_left_in[1] - PIN chanx_left_in[2] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 10.05 1.38 10.35 ; - END - END chanx_left_in[2] - PIN chanx_left_in[3] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 21.61 1.38 21.91 ; - END - END chanx_left_in[3] - PIN chanx_left_in[4] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 78.73 1.38 79.03 ; - END - END chanx_left_in[4] - PIN chanx_left_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 15.49 1.38 15.79 ; - END - END chanx_left_in[5] - PIN chanx_left_in[6] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 33.17 1.38 33.47 ; - END - END chanx_left_in[6] - PIN chanx_left_in[7] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 83.49 1.38 83.79 ; - END - END chanx_left_in[7] - PIN chanx_left_in[8] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 25.69 1.38 25.99 ; - END - END chanx_left_in[8] - PIN chanx_left_in[9] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 34.53 1.38 34.83 ; - END - END chanx_left_in[9] - PIN chanx_left_in[10] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 39.29 1.38 39.59 ; - END - END chanx_left_in[10] - PIN chanx_left_in[11] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 18.21 1.38 18.51 ; - END - END chanx_left_in[11] - PIN chanx_left_in[12] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 76.01 1.38 76.31 ; - END - END chanx_left_in[12] - PIN chanx_left_in[13] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 69.21 1.38 69.51 ; - END - END chanx_left_in[13] - PIN chanx_left_in[14] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 42.01 1.38 42.31 ; - END - END chanx_left_in[14] - PIN chanx_left_in[15] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 46.09 1.38 46.39 ; - END - END chanx_left_in[15] - PIN chanx_left_in[16] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 29.77 1.38 30.07 ; - END - END chanx_left_in[16] - PIN chanx_left_in[17] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 24.33 1.38 24.63 ; - END - END chanx_left_in[17] - PIN chanx_left_in[18] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 22.97 1.38 23.27 ; - END - END chanx_left_in[18] - PIN chanx_left_in[19] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 67.85 1.38 68.15 ; - END - END chanx_left_in[19] - PIN left_bottom_grid_pin_1_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 63.77 1.38 64.07 ; - END - END left_bottom_grid_pin_1_[0] - PIN left_bottom_grid_pin_3_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 31.13 1.38 31.43 ; - END - END left_bottom_grid_pin_3_[0] - PIN left_bottom_grid_pin_5_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 43.37 1.38 43.67 ; - END - END left_bottom_grid_pin_5_[0] - PIN left_bottom_grid_pin_7_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 54.25 1.38 54.55 ; - END - END left_bottom_grid_pin_7_[0] - PIN left_bottom_grid_pin_9_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 61.73 1.38 62.03 ; - END - END left_bottom_grid_pin_9_[0] - PIN left_bottom_grid_pin_11_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 37.25 1.38 37.55 ; - END - END left_bottom_grid_pin_11_[0] - PIN ccff_head[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 38.57 96.56 38.71 97.92 ; - END - END ccff_head[0] - PIN chany_top_out[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 37.65 96.56 37.79 97.92 ; - END - END chany_top_out[0] - PIN chany_top_out[1] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 50.53 96.56 50.67 97.92 ; - END - END chany_top_out[1] - PIN chany_top_out[2] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 63.87 96.56 64.01 97.92 ; - END - END chany_top_out[2] - PIN chany_top_out[3] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 36.73 96.56 36.87 97.92 ; - END - END chany_top_out[3] - PIN chany_top_out[4] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 57.43 96.56 57.57 97.92 ; - END - END chany_top_out[4] - PIN chany_top_out[5] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 45.93 96.56 46.07 97.92 ; - END - END chany_top_out[5] - PIN chany_top_out[6] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 62.95 96.56 63.09 97.92 ; - END - END chany_top_out[6] - PIN chany_top_out[7] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 42.25 96.56 42.39 97.92 ; - END - END chany_top_out[7] - PIN chany_top_out[8] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 60.19 96.56 60.33 97.92 ; - END - END chany_top_out[8] - PIN chany_top_out[9] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 39.49 96.56 39.63 97.92 ; - END - END chany_top_out[9] - PIN chany_top_out[10] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 66.63 96.56 66.77 97.92 ; - END - END chany_top_out[10] - PIN chany_top_out[11] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 40.41 96.56 40.55 97.92 ; - END - END chany_top_out[11] - PIN chany_top_out[12] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 62.03 96.56 62.17 97.92 ; - END - END chany_top_out[12] - PIN chany_top_out[13] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 41.33 96.56 41.47 97.92 ; - END - END chany_top_out[13] - PIN chany_top_out[14] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 72.15 96.56 72.29 97.92 ; - END - END chany_top_out[14] - PIN chany_top_out[15] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 47.77 96.56 47.91 97.92 ; - END - END chany_top_out[15] - PIN chany_top_out[16] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 81.81 96.56 81.95 97.92 ; - END - END chany_top_out[16] - PIN chany_top_out[17] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 44.55 96.56 44.69 97.92 ; - END - END chany_top_out[17] - PIN chany_top_out[18] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 70.31 96.56 70.45 97.92 ; - END - END chany_top_out[18] - PIN chany_top_out[19] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 32.13 96.56 32.27 97.92 ; - END - END chany_top_out[19] - PIN chanx_left_out[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 59.69 1.38 59.99 ; - END - END chanx_left_out[0] - PIN chanx_left_out[1] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 56.29 1.38 56.59 ; - END - END chanx_left_out[1] - PIN chanx_left_out[2] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 77.37 1.38 77.67 ; - END - END chanx_left_out[2] - PIN chanx_left_out[3] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 80.09 1.38 80.39 ; - END - END chanx_left_out[3] - PIN chanx_left_out[4] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 48.13 1.38 48.43 ; - END - END chanx_left_out[4] - PIN chanx_left_out[5] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 82.13 1.38 82.43 ; - END - END chanx_left_out[5] - PIN chanx_left_out[6] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 73.29 1.38 73.59 ; - END - END chanx_left_out[6] - PIN chanx_left_out[7] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 58.33 1.38 58.63 ; - END - END chanx_left_out[7] - PIN chanx_left_out[8] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 19.57 1.38 19.87 ; - END - END chanx_left_out[8] - PIN chanx_left_out[9] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 44.73 1.38 45.03 ; - END - END chanx_left_out[9] - PIN chanx_left_out[10] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 71.93 1.38 72.23 ; - END - END chanx_left_out[10] - PIN chanx_left_out[11] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 70.57 1.38 70.87 ; - END - END chanx_left_out[11] - PIN chanx_left_out[12] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 74.65 1.38 74.95 ; - END - END chanx_left_out[12] - PIN chanx_left_out[13] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 65.13 1.38 65.43 ; - END - END chanx_left_out[13] - PIN chanx_left_out[14] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 27.73 1.38 28.03 ; - END - END chanx_left_out[14] - PIN chanx_left_out[15] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 49.49 1.38 49.79 ; - END - END chanx_left_out[15] - PIN chanx_left_out[16] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 40.65 1.38 40.95 ; - END - END chanx_left_out[16] - PIN chanx_left_out[17] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 8.69 1.38 8.99 ; - END - END chanx_left_out[17] - PIN chanx_left_out[18] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 50.85 1.38 51.15 ; - END - END chanx_left_out[18] - PIN chanx_left_out[19] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 52.21 1.38 52.51 ; - END - END chanx_left_out[19] - PIN ccff_tail[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 16.85 1.38 17.15 ; - END - END ccff_tail[0] - PIN VDD - DIRECTION INPUT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 0 2.48 0.48 2.96 ; - RECT 91.52 2.48 92 2.96 ; - RECT 0 7.92 0.48 8.4 ; - RECT 91.52 7.92 92 8.4 ; - RECT 0 13.36 0.48 13.84 ; - RECT 91.52 13.36 92 13.84 ; - RECT 0 18.8 0.48 19.28 ; - RECT 91.52 18.8 92 19.28 ; - RECT 0 24.24 0.48 24.72 ; - RECT 91.52 24.24 92 24.72 ; - RECT 0 29.68 0.48 30.16 ; - RECT 91.52 29.68 92 30.16 ; - RECT 0 35.12 0.48 35.6 ; - RECT 91.52 35.12 92 35.6 ; - RECT 0 40.56 0.48 41.04 ; - RECT 91.52 40.56 92 41.04 ; - RECT 0 46 0.48 46.48 ; - RECT 91.52 46 92 46.48 ; - RECT 0 51.44 0.48 51.92 ; - RECT 91.52 51.44 92 51.92 ; - RECT 0 56.88 0.48 57.36 ; - RECT 91.52 56.88 92 57.36 ; - RECT 0 62.32 0.48 62.8 ; - RECT 91.52 62.32 92 62.8 ; - RECT 0 67.76 0.48 68.24 ; - RECT 91.52 67.76 92 68.24 ; - RECT 0 73.2 0.48 73.68 ; - RECT 91.52 73.2 92 73.68 ; - RECT 0 78.64 0.48 79.12 ; - RECT 91.52 78.64 92 79.12 ; - RECT 0 84.08 0.48 84.56 ; - RECT 91.52 84.08 92 84.56 ; - RECT 25.76 89.52 26.24 90 ; - RECT 91.52 89.52 92 90 ; - RECT 25.76 94.96 26.24 95.44 ; - RECT 91.52 94.96 92 95.44 ; - LAYER met4 ; - RECT 36.5 0 37.1 0.6 ; - RECT 65.94 0 66.54 0.6 ; - RECT 36.5 97.32 37.1 97.92 ; - RECT 65.94 97.32 66.54 97.92 ; - LAYER met5 ; - RECT 0 11.32 3.2 14.52 ; - RECT 88.8 11.32 92 14.52 ; - RECT 0 52.12 3.2 55.32 ; - RECT 88.8 52.12 92 55.32 ; - END - END VDD - PIN VSS - DIRECTION INPUT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 0 0 92 0.24 ; - RECT 0 5.2 0.48 5.68 ; - RECT 91.52 5.2 92 5.68 ; - RECT 0 10.64 0.48 11.12 ; - RECT 91.52 10.64 92 11.12 ; - RECT 0 16.08 0.48 16.56 ; - RECT 91.52 16.08 92 16.56 ; - RECT 0 21.52 0.48 22 ; - RECT 91.52 21.52 92 22 ; - RECT 0 26.96 0.48 27.44 ; - RECT 91.52 26.96 92 27.44 ; - RECT 0 32.4 0.48 32.88 ; - RECT 91.52 32.4 92 32.88 ; - RECT 0 37.84 0.48 38.32 ; - RECT 91.52 37.84 92 38.32 ; - RECT 0 43.28 0.48 43.76 ; - RECT 91.52 43.28 92 43.76 ; - RECT 0 48.72 0.48 49.2 ; - RECT 91.52 48.72 92 49.2 ; - RECT 0 54.16 0.48 54.64 ; - RECT 91.52 54.16 92 54.64 ; - RECT 0 59.6 0.48 60.08 ; - RECT 91.52 59.6 92 60.08 ; - RECT 0 65.04 0.48 65.52 ; - RECT 91.52 65.04 92 65.52 ; - RECT 0 70.48 0.48 70.96 ; - RECT 91.52 70.48 92 70.96 ; - RECT 0 75.92 0.48 76.4 ; - RECT 91.52 75.92 92 76.4 ; - RECT 0 81.36 0.48 81.84 ; - RECT 91.52 81.36 92 81.84 ; - RECT 0 86.8 92 87.28 ; - RECT 25.76 92.24 26.24 92.72 ; - RECT 91.52 92.24 92 92.72 ; - RECT 25.76 97.68 92 97.92 ; - LAYER met4 ; - RECT 10.74 0 11.34 0.6 ; - RECT 51.22 0 51.82 0.6 ; - RECT 80.66 0 81.26 0.6 ; - RECT 10.74 86.44 11.34 87.04 ; - RECT 51.22 97.32 51.82 97.92 ; - RECT 80.66 97.32 81.26 97.92 ; - LAYER met5 ; - RECT 0 31.72 3.2 34.92 ; - RECT 88.8 31.72 92 34.92 ; - RECT 0 72.52 3.2 75.72 ; - RECT 88.8 72.52 92 75.72 ; - END - END VSS - OBS - LAYER li1 ; - RECT 25.76 97.835 92 98.005 ; - RECT 91.54 95.115 92 95.285 ; - RECT 25.76 95.115 29.44 95.285 ; - RECT 90.16 92.395 92 92.565 ; - RECT 25.76 92.395 29.44 92.565 ; - RECT 90.16 89.675 92 89.845 ; - RECT 25.76 89.675 27.6 89.845 ; - RECT 91.08 86.955 92 87.125 ; - RECT 0 86.955 29.44 87.125 ; - RECT 91.08 84.235 92 84.405 ; - RECT 0 84.235 3.68 84.405 ; - RECT 91.54 81.515 92 81.685 ; - RECT 0 81.515 3.68 81.685 ; - RECT 91.54 78.795 92 78.965 ; - RECT 0 78.795 1.84 78.965 ; - RECT 91.08 76.075 92 76.245 ; - RECT 0 76.075 1.84 76.245 ; - RECT 91.08 73.355 92 73.525 ; - RECT 0 73.355 1.84 73.525 ; - RECT 88.32 70.635 92 70.805 ; - RECT 0 70.635 1.84 70.805 ; - RECT 88.32 67.915 92 68.085 ; - RECT 0 67.915 1.84 68.085 ; - RECT 91.54 65.195 92 65.365 ; - RECT 0 65.195 1.84 65.365 ; - RECT 91.54 62.475 92 62.645 ; - RECT 0 62.475 3.68 62.645 ; - RECT 88.32 59.755 92 59.925 ; - RECT 0 59.755 3.68 59.925 ; - RECT 88.32 57.035 92 57.205 ; - RECT 0 57.035 3.68 57.205 ; - RECT 91.54 54.315 92 54.485 ; - RECT 0 54.315 1.84 54.485 ; - RECT 91.54 51.595 92 51.765 ; - RECT 0 51.595 1.84 51.765 ; - RECT 91.08 48.875 92 49.045 ; - RECT 0 48.875 3.68 49.045 ; - RECT 91.08 46.155 92 46.325 ; - RECT 0 46.155 3.68 46.325 ; - RECT 90.16 43.435 92 43.605 ; - RECT 0 43.435 3.68 43.605 ; - RECT 90.16 40.715 92 40.885 ; - RECT 0 40.715 3.68 40.885 ; - RECT 91.54 37.995 92 38.165 ; - RECT 0 37.995 3.68 38.165 ; - RECT 91.54 35.275 92 35.445 ; - RECT 0 35.275 3.68 35.445 ; - RECT 91.08 32.555 92 32.725 ; - RECT 0 32.555 3.68 32.725 ; - RECT 91.08 29.835 92 30.005 ; - RECT 0 29.835 1.84 30.005 ; - RECT 88.32 27.115 92 27.285 ; - RECT 0 27.115 1.84 27.285 ; - RECT 88.32 24.395 92 24.565 ; - RECT 0 24.395 3.68 24.565 ; - RECT 91.54 21.675 92 21.845 ; - RECT 0 21.675 3.68 21.845 ; - RECT 91.54 18.955 92 19.125 ; - RECT 0 18.955 1.84 19.125 ; - RECT 91.54 16.235 92 16.405 ; - RECT 0 16.235 3.68 16.405 ; - RECT 91.54 13.515 92 13.685 ; - RECT 0 13.515 3.68 13.685 ; - RECT 91.54 10.795 92 10.965 ; - RECT 0 10.795 3.68 10.965 ; - RECT 91.54 8.075 92 8.245 ; - RECT 0 8.075 3.68 8.245 ; - RECT 91.54 5.355 92 5.525 ; - RECT 0 5.355 3.68 5.525 ; - RECT 91.54 2.635 92 2.805 ; - RECT 0 2.635 3.68 2.805 ; - RECT 0 -0.085 92 0.085 ; - LAYER met3 ; - POLYGON 81.125 98.085 81.125 98.08 81.34 98.08 81.34 97.76 81.125 97.76 81.125 97.755 80.795 97.755 80.795 97.76 80.58 97.76 80.58 98.08 80.795 98.08 80.795 98.085 ; - POLYGON 51.685 98.085 51.685 98.08 51.9 98.08 51.9 97.76 51.685 97.76 51.685 97.755 51.355 97.755 51.355 97.76 51.14 97.76 51.14 98.08 51.355 98.08 51.355 98.085 ; - POLYGON 11.205 87.205 11.205 87.2 11.42 87.2 11.42 86.88 11.205 86.88 11.205 86.875 10.875 86.875 10.875 86.88 10.66 86.88 10.66 87.2 10.875 87.2 10.875 87.205 ; - POLYGON 19.47 76.99 19.47 76.69 1.78 76.69 1.78 76.71 1.23 76.71 1.23 76.99 ; - POLYGON 25.91 59.31 25.91 59.01 1.78 59.01 1.78 59.03 1.23 59.03 1.23 59.31 ; - POLYGON 81.125 0.165 81.125 0.16 81.34 0.16 81.34 -0.16 81.125 -0.16 81.125 -0.165 80.795 -0.165 80.795 -0.16 80.58 -0.16 80.58 0.16 80.795 0.16 80.795 0.165 ; - POLYGON 51.685 0.165 51.685 0.16 51.9 0.16 51.9 -0.16 51.685 -0.16 51.685 -0.165 51.355 -0.165 51.355 -0.16 51.14 -0.16 51.14 0.16 51.355 0.16 51.355 0.165 ; - POLYGON 11.205 0.165 11.205 0.16 11.42 0.16 11.42 -0.16 11.205 -0.16 11.205 -0.165 10.875 -0.165 10.875 -0.16 10.66 -0.16 10.66 0.16 10.875 0.16 10.875 0.165 ; - POLYGON 91.6 97.52 91.6 0.4 0.4 0.4 0.4 8.29 1.78 8.29 1.78 9.39 0.4 9.39 0.4 9.65 1.78 9.65 1.78 10.75 0.4 10.75 0.4 11.01 1.78 11.01 1.78 12.11 0.4 12.11 0.4 13.05 1.78 13.05 1.78 14.15 0.4 14.15 0.4 15.09 1.78 15.09 1.78 16.19 0.4 16.19 0.4 16.45 1.78 16.45 1.78 17.55 0.4 17.55 0.4 17.81 1.78 17.81 1.78 18.91 0.4 18.91 0.4 19.17 1.78 19.17 1.78 20.27 0.4 20.27 0.4 21.21 1.78 21.21 1.78 22.31 0.4 22.31 0.4 22.57 1.78 22.57 1.78 23.67 0.4 23.67 0.4 23.93 1.78 23.93 1.78 25.03 0.4 25.03 0.4 25.29 1.78 25.29 1.78 26.39 0.4 26.39 0.4 27.33 1.78 27.33 1.78 28.43 0.4 28.43 0.4 29.37 1.78 29.37 1.78 30.47 0.4 30.47 0.4 30.73 1.78 30.73 1.78 31.83 0.4 31.83 0.4 32.77 1.78 32.77 1.78 33.87 0.4 33.87 0.4 34.13 1.78 34.13 1.78 35.23 0.4 35.23 0.4 36.85 1.78 36.85 1.78 37.95 0.4 37.95 0.4 38.89 1.78 38.89 1.78 39.99 0.4 39.99 0.4 40.25 1.78 40.25 1.78 41.35 0.4 41.35 0.4 41.61 1.78 41.61 1.78 42.71 0.4 42.71 0.4 42.97 1.78 42.97 1.78 44.07 0.4 44.07 0.4 44.33 1.78 44.33 1.78 45.43 0.4 45.43 0.4 45.69 1.78 45.69 1.78 46.79 0.4 46.79 0.4 47.73 1.78 47.73 1.78 48.83 0.4 48.83 0.4 49.09 1.78 49.09 1.78 50.19 0.4 50.19 0.4 50.45 1.78 50.45 1.78 51.55 0.4 51.55 0.4 51.81 1.78 51.81 1.78 52.91 0.4 52.91 0.4 53.85 1.78 53.85 1.78 54.95 0.4 54.95 0.4 55.89 1.78 55.89 1.78 56.99 0.4 56.99 0.4 57.93 1.78 57.93 1.78 59.03 0.4 59.03 0.4 59.29 1.78 59.29 1.78 60.39 0.4 60.39 0.4 61.33 1.78 61.33 1.78 62.43 0.4 62.43 0.4 63.37 1.78 63.37 1.78 64.47 0.4 64.47 0.4 64.73 1.78 64.73 1.78 65.83 0.4 65.83 0.4 66.09 1.78 66.09 1.78 67.19 0.4 67.19 0.4 67.45 1.78 67.45 1.78 68.55 0.4 68.55 0.4 68.81 1.78 68.81 1.78 69.91 0.4 69.91 0.4 70.17 1.78 70.17 1.78 71.27 0.4 71.27 0.4 71.53 1.78 71.53 1.78 72.63 0.4 72.63 0.4 72.89 1.78 72.89 1.78 73.99 0.4 73.99 0.4 74.25 1.78 74.25 1.78 75.35 0.4 75.35 0.4 75.61 1.78 75.61 1.78 76.71 0.4 76.71 0.4 76.97 1.78 76.97 1.78 78.07 0.4 78.07 0.4 78.33 1.78 78.33 1.78 79.43 0.4 79.43 0.4 79.69 1.78 79.69 1.78 80.79 0.4 80.79 0.4 81.73 1.78 81.73 1.78 82.83 0.4 82.83 0.4 83.09 1.78 83.09 1.78 84.19 0.4 84.19 0.4 86.64 26.16 86.64 26.16 97.52 ; - LAYER met2 ; - RECT 80.82 97.735 81.1 98.105 ; - RECT 51.38 97.735 51.66 98.105 ; - RECT 38.05 96.06 38.31 96.38 ; - RECT 10.9 86.855 11.18 87.225 ; - RECT 15.51 85.18 15.77 85.5 ; - RECT 80.82 -0.185 81.1 0.185 ; - RECT 51.38 -0.185 51.66 0.185 ; - RECT 10.9 -0.185 11.18 0.185 ; - POLYGON 91.72 97.64 91.72 0.28 0.28 0.28 0.28 86.76 6.55 86.76 6.55 85.4 7.25 85.4 7.25 86.76 7.47 86.76 7.47 85.4 8.17 85.4 8.17 86.76 8.85 86.76 8.85 85.4 9.55 85.4 9.55 86.76 12.53 86.76 12.53 85.4 13.23 85.4 13.23 86.76 13.91 86.76 13.91 85.4 14.61 85.4 14.61 86.76 15.75 86.76 15.75 85.4 16.45 85.4 16.45 86.76 18.05 86.76 18.05 85.4 18.75 85.4 18.75 86.76 26.04 86.76 26.04 97.64 31.85 97.64 31.85 96.28 32.55 96.28 32.55 97.64 36.45 97.64 36.45 96.28 37.15 96.28 37.15 97.64 37.37 97.64 37.37 96.28 38.07 96.28 38.07 97.64 38.29 97.64 38.29 96.28 38.99 96.28 38.99 97.64 39.21 97.64 39.21 96.28 39.91 96.28 39.91 97.64 40.13 97.64 40.13 96.28 40.83 96.28 40.83 97.64 41.05 97.64 41.05 96.28 41.75 96.28 41.75 97.64 41.97 97.64 41.97 96.28 42.67 96.28 42.67 97.64 43.35 97.64 43.35 96.28 44.05 96.28 44.05 97.64 44.27 97.64 44.27 96.28 44.97 96.28 44.97 97.64 45.65 97.64 45.65 96.28 46.35 96.28 46.35 97.64 46.57 97.64 46.57 96.28 47.27 96.28 47.27 97.64 47.49 97.64 47.49 96.28 48.19 96.28 48.19 97.64 48.41 97.64 48.41 96.28 49.11 96.28 49.11 97.64 49.33 97.64 49.33 96.28 50.03 96.28 50.03 97.64 50.25 97.64 50.25 96.28 50.95 96.28 50.95 97.64 52.09 97.64 52.09 96.28 52.79 96.28 52.79 97.64 53.93 97.64 53.93 96.28 54.63 96.28 54.63 97.64 55.77 97.64 55.77 96.28 56.47 96.28 56.47 97.64 57.15 97.64 57.15 96.28 57.85 96.28 57.85 97.64 58.99 97.64 58.99 96.28 59.69 96.28 59.69 97.64 59.91 97.64 59.91 96.28 60.61 96.28 60.61 97.64 60.83 97.64 60.83 96.28 61.53 96.28 61.53 97.64 61.75 97.64 61.75 96.28 62.45 96.28 62.45 97.64 62.67 97.64 62.67 96.28 63.37 96.28 63.37 97.64 63.59 97.64 63.59 96.28 64.29 96.28 64.29 97.64 64.51 97.64 64.51 96.28 65.21 96.28 65.21 97.64 65.43 97.64 65.43 96.28 66.13 96.28 66.13 97.64 66.35 97.64 66.35 96.28 67.05 96.28 67.05 97.64 67.27 97.64 67.27 96.28 67.97 96.28 67.97 97.64 68.19 97.64 68.19 96.28 68.89 96.28 68.89 97.64 69.11 97.64 69.11 96.28 69.81 96.28 69.81 97.64 70.03 97.64 70.03 96.28 70.73 96.28 70.73 97.64 70.95 97.64 70.95 96.28 71.65 96.28 71.65 97.64 71.87 97.64 71.87 96.28 72.57 96.28 72.57 97.64 72.79 97.64 72.79 96.28 73.49 96.28 73.49 97.64 73.71 97.64 73.71 96.28 74.41 96.28 74.41 97.64 81.53 97.64 81.53 96.28 82.23 96.28 82.23 97.64 ; - LAYER met4 ; - POLYGON 91.6 97.52 91.6 0.4 81.66 0.4 81.66 1 80.26 1 80.26 0.4 66.94 0.4 66.94 1 65.54 1 65.54 0.4 52.22 0.4 52.22 1 50.82 1 50.82 0.4 37.5 0.4 37.5 1 36.1 1 36.1 0.4 11.74 0.4 11.74 1 10.34 1 10.34 0.4 0.4 0.4 0.4 86.64 10.34 86.64 10.34 86.04 11.74 86.04 11.74 86.64 17.85 86.64 17.85 85.28 18.95 85.28 18.95 86.64 26.16 86.64 26.16 97.52 36.1 97.52 36.1 96.92 37.5 96.92 37.5 97.52 50.82 97.52 50.82 96.92 52.22 96.92 52.22 97.52 52.81 97.52 52.81 96.16 53.91 96.16 53.91 97.52 59.25 97.52 59.25 96.16 60.35 96.16 60.35 97.52 62.93 97.52 62.93 96.16 64.03 96.16 64.03 97.52 65.54 97.52 65.54 96.92 66.94 96.92 66.94 97.52 72.13 97.52 72.13 96.16 73.23 96.16 73.23 97.52 80.26 97.52 80.26 96.92 81.66 96.92 81.66 97.52 ; - LAYER met5 ; - POLYGON 90.4 96.32 90.4 77.32 87.2 77.32 87.2 70.92 90.4 70.92 90.4 56.92 87.2 56.92 87.2 50.52 90.4 50.52 90.4 36.52 87.2 36.52 87.2 30.12 90.4 30.12 90.4 16.12 87.2 16.12 87.2 9.72 90.4 9.72 90.4 1.6 1.6 1.6 1.6 9.72 4.8 9.72 4.8 16.12 1.6 16.12 1.6 30.12 4.8 30.12 4.8 36.52 1.6 36.52 1.6 50.52 4.8 50.52 4.8 56.92 1.6 56.92 1.6 70.92 4.8 70.92 4.8 77.32 1.6 77.32 1.6 85.44 27.36 85.44 27.36 96.32 ; - LAYER met1 ; - POLYGON 91.72 97.4 91.72 95.72 91.24 95.72 91.24 94.68 91.72 94.68 91.72 93 91.24 93 91.24 91.96 91.72 91.96 91.72 90.28 91.24 90.28 91.24 89.24 91.72 89.24 91.72 87.56 26.04 87.56 26.04 89.24 26.52 89.24 26.52 90.28 26.04 90.28 26.04 91.96 26.52 91.96 26.52 93 26.04 93 26.04 94.68 26.52 94.68 26.52 95.72 26.04 95.72 26.04 97.4 ; - POLYGON 91.72 86.52 91.72 84.84 91.24 84.84 91.24 83.8 91.72 83.8 91.72 82.12 91.24 82.12 91.24 81.08 91.72 81.08 91.72 79.4 91.24 79.4 91.24 78.36 91.72 78.36 91.72 76.68 91.24 76.68 91.24 75.64 91.72 75.64 91.72 73.96 91.24 73.96 91.24 72.92 91.72 72.92 91.72 71.24 91.24 71.24 91.24 70.2 91.72 70.2 91.72 68.52 91.24 68.52 91.24 67.48 91.72 67.48 91.72 65.8 91.24 65.8 91.24 64.76 91.72 64.76 91.72 63.08 91.24 63.08 91.24 62.04 91.72 62.04 91.72 60.36 91.24 60.36 91.24 59.32 91.72 59.32 91.72 57.64 91.24 57.64 91.24 56.6 91.72 56.6 91.72 54.92 91.24 54.92 91.24 53.88 91.72 53.88 91.72 52.2 91.24 52.2 91.24 51.16 91.72 51.16 91.72 49.48 91.24 49.48 91.24 48.44 91.72 48.44 91.72 46.76 91.24 46.76 91.24 45.72 91.72 45.72 91.72 44.04 91.24 44.04 91.24 43 91.72 43 91.72 41.32 91.24 41.32 91.24 40.28 91.72 40.28 91.72 38.6 91.24 38.6 91.24 37.56 91.72 37.56 91.72 35.88 91.24 35.88 91.24 34.84 91.72 34.84 91.72 33.16 91.24 33.16 91.24 32.12 91.72 32.12 91.72 30.44 91.24 30.44 91.24 29.4 91.72 29.4 91.72 27.72 91.24 27.72 91.24 26.68 91.72 26.68 91.72 25 91.24 25 91.24 23.96 91.72 23.96 91.72 22.28 91.24 22.28 91.24 21.24 91.72 21.24 91.72 19.56 91.24 19.56 91.24 18.52 91.72 18.52 91.72 16.84 91.24 16.84 91.24 15.8 91.72 15.8 91.72 14.12 91.24 14.12 91.24 13.08 91.72 13.08 91.72 11.4 91.24 11.4 91.24 10.36 91.72 10.36 91.72 8.68 91.24 8.68 91.24 7.64 91.72 7.64 91.72 5.96 91.24 5.96 91.24 4.92 91.72 4.92 91.72 3.24 91.24 3.24 91.24 2.2 91.72 2.2 91.72 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 0.76 10.36 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 0.76 81.08 0.76 82.12 0.28 82.12 0.28 83.8 0.76 83.8 0.76 84.84 0.28 84.84 0.28 86.52 ; - LAYER li1 ; - POLYGON 91.83 97.75 91.83 0.17 0.17 0.17 0.17 86.87 25.93 86.87 25.93 97.75 ; - LAYER mcon ; - RECT 91.685 97.835 91.855 98.005 ; - RECT 91.225 97.835 91.395 98.005 ; - RECT 90.765 97.835 90.935 98.005 ; - RECT 90.305 97.835 90.475 98.005 ; - RECT 89.845 97.835 90.015 98.005 ; - RECT 89.385 97.835 89.555 98.005 ; - RECT 88.925 97.835 89.095 98.005 ; - RECT 88.465 97.835 88.635 98.005 ; - RECT 88.005 97.835 88.175 98.005 ; - RECT 87.545 97.835 87.715 98.005 ; - RECT 87.085 97.835 87.255 98.005 ; - RECT 86.625 97.835 86.795 98.005 ; - RECT 86.165 97.835 86.335 98.005 ; - RECT 85.705 97.835 85.875 98.005 ; - RECT 85.245 97.835 85.415 98.005 ; - RECT 84.785 97.835 84.955 98.005 ; - RECT 84.325 97.835 84.495 98.005 ; - RECT 83.865 97.835 84.035 98.005 ; - RECT 83.405 97.835 83.575 98.005 ; - RECT 82.945 97.835 83.115 98.005 ; - RECT 82.485 97.835 82.655 98.005 ; - RECT 82.025 97.835 82.195 98.005 ; - RECT 81.565 97.835 81.735 98.005 ; - RECT 81.105 97.835 81.275 98.005 ; - RECT 80.645 97.835 80.815 98.005 ; - RECT 80.185 97.835 80.355 98.005 ; - RECT 79.725 97.835 79.895 98.005 ; - RECT 79.265 97.835 79.435 98.005 ; - RECT 78.805 97.835 78.975 98.005 ; - RECT 78.345 97.835 78.515 98.005 ; - RECT 77.885 97.835 78.055 98.005 ; - RECT 77.425 97.835 77.595 98.005 ; - RECT 76.965 97.835 77.135 98.005 ; - RECT 76.505 97.835 76.675 98.005 ; - RECT 76.045 97.835 76.215 98.005 ; - RECT 75.585 97.835 75.755 98.005 ; - RECT 75.125 97.835 75.295 98.005 ; - RECT 74.665 97.835 74.835 98.005 ; - RECT 74.205 97.835 74.375 98.005 ; - RECT 73.745 97.835 73.915 98.005 ; - RECT 73.285 97.835 73.455 98.005 ; - RECT 72.825 97.835 72.995 98.005 ; - RECT 72.365 97.835 72.535 98.005 ; - RECT 71.905 97.835 72.075 98.005 ; - RECT 71.445 97.835 71.615 98.005 ; - RECT 70.985 97.835 71.155 98.005 ; - RECT 70.525 97.835 70.695 98.005 ; - RECT 70.065 97.835 70.235 98.005 ; - RECT 69.605 97.835 69.775 98.005 ; - RECT 69.145 97.835 69.315 98.005 ; - RECT 68.685 97.835 68.855 98.005 ; - RECT 68.225 97.835 68.395 98.005 ; - RECT 67.765 97.835 67.935 98.005 ; - RECT 67.305 97.835 67.475 98.005 ; - RECT 66.845 97.835 67.015 98.005 ; - RECT 66.385 97.835 66.555 98.005 ; - RECT 65.925 97.835 66.095 98.005 ; - RECT 65.465 97.835 65.635 98.005 ; - RECT 65.005 97.835 65.175 98.005 ; - RECT 64.545 97.835 64.715 98.005 ; - RECT 64.085 97.835 64.255 98.005 ; - RECT 63.625 97.835 63.795 98.005 ; - RECT 63.165 97.835 63.335 98.005 ; - RECT 62.705 97.835 62.875 98.005 ; - RECT 62.245 97.835 62.415 98.005 ; - RECT 61.785 97.835 61.955 98.005 ; - RECT 61.325 97.835 61.495 98.005 ; - RECT 60.865 97.835 61.035 98.005 ; - RECT 60.405 97.835 60.575 98.005 ; - RECT 59.945 97.835 60.115 98.005 ; - RECT 59.485 97.835 59.655 98.005 ; - RECT 59.025 97.835 59.195 98.005 ; - RECT 58.565 97.835 58.735 98.005 ; - RECT 58.105 97.835 58.275 98.005 ; - RECT 57.645 97.835 57.815 98.005 ; - RECT 57.185 97.835 57.355 98.005 ; - RECT 56.725 97.835 56.895 98.005 ; - RECT 56.265 97.835 56.435 98.005 ; - RECT 55.805 97.835 55.975 98.005 ; - RECT 55.345 97.835 55.515 98.005 ; - RECT 54.885 97.835 55.055 98.005 ; - RECT 54.425 97.835 54.595 98.005 ; - RECT 53.965 97.835 54.135 98.005 ; - RECT 53.505 97.835 53.675 98.005 ; - RECT 53.045 97.835 53.215 98.005 ; - RECT 52.585 97.835 52.755 98.005 ; - RECT 52.125 97.835 52.295 98.005 ; - RECT 51.665 97.835 51.835 98.005 ; - RECT 51.205 97.835 51.375 98.005 ; - RECT 50.745 97.835 50.915 98.005 ; - RECT 50.285 97.835 50.455 98.005 ; - RECT 49.825 97.835 49.995 98.005 ; - RECT 49.365 97.835 49.535 98.005 ; - RECT 48.905 97.835 49.075 98.005 ; - RECT 48.445 97.835 48.615 98.005 ; - RECT 47.985 97.835 48.155 98.005 ; - RECT 47.525 97.835 47.695 98.005 ; - RECT 47.065 97.835 47.235 98.005 ; - RECT 46.605 97.835 46.775 98.005 ; - RECT 46.145 97.835 46.315 98.005 ; - RECT 45.685 97.835 45.855 98.005 ; - RECT 45.225 97.835 45.395 98.005 ; - RECT 44.765 97.835 44.935 98.005 ; - RECT 44.305 97.835 44.475 98.005 ; - RECT 43.845 97.835 44.015 98.005 ; - RECT 43.385 97.835 43.555 98.005 ; - RECT 42.925 97.835 43.095 98.005 ; - RECT 42.465 97.835 42.635 98.005 ; - RECT 42.005 97.835 42.175 98.005 ; - RECT 41.545 97.835 41.715 98.005 ; - RECT 41.085 97.835 41.255 98.005 ; - RECT 40.625 97.835 40.795 98.005 ; - RECT 40.165 97.835 40.335 98.005 ; - RECT 39.705 97.835 39.875 98.005 ; - RECT 39.245 97.835 39.415 98.005 ; - RECT 38.785 97.835 38.955 98.005 ; - RECT 38.325 97.835 38.495 98.005 ; - RECT 37.865 97.835 38.035 98.005 ; - RECT 37.405 97.835 37.575 98.005 ; - RECT 36.945 97.835 37.115 98.005 ; - RECT 36.485 97.835 36.655 98.005 ; - RECT 36.025 97.835 36.195 98.005 ; - RECT 35.565 97.835 35.735 98.005 ; - RECT 35.105 97.835 35.275 98.005 ; - RECT 34.645 97.835 34.815 98.005 ; - RECT 34.185 97.835 34.355 98.005 ; - RECT 33.725 97.835 33.895 98.005 ; - RECT 33.265 97.835 33.435 98.005 ; - RECT 32.805 97.835 32.975 98.005 ; - RECT 32.345 97.835 32.515 98.005 ; - RECT 31.885 97.835 32.055 98.005 ; - RECT 31.425 97.835 31.595 98.005 ; - RECT 30.965 97.835 31.135 98.005 ; - RECT 30.505 97.835 30.675 98.005 ; - RECT 30.045 97.835 30.215 98.005 ; - RECT 29.585 97.835 29.755 98.005 ; - RECT 29.125 97.835 29.295 98.005 ; - RECT 28.665 97.835 28.835 98.005 ; - RECT 28.205 97.835 28.375 98.005 ; - RECT 27.745 97.835 27.915 98.005 ; - RECT 27.285 97.835 27.455 98.005 ; - RECT 26.825 97.835 26.995 98.005 ; - RECT 26.365 97.835 26.535 98.005 ; - RECT 25.905 97.835 26.075 98.005 ; - RECT 91.685 95.115 91.855 95.285 ; - RECT 91.225 95.115 91.395 95.285 ; - RECT 26.365 95.115 26.535 95.285 ; - RECT 25.905 95.115 26.075 95.285 ; - RECT 91.685 92.395 91.855 92.565 ; - RECT 91.225 92.395 91.395 92.565 ; - RECT 26.365 92.395 26.535 92.565 ; - RECT 25.905 92.395 26.075 92.565 ; - RECT 91.685 89.675 91.855 89.845 ; - RECT 91.225 89.675 91.395 89.845 ; - RECT 26.365 89.675 26.535 89.845 ; - RECT 25.905 89.675 26.075 89.845 ; - RECT 91.685 86.955 91.855 87.125 ; - RECT 91.225 86.955 91.395 87.125 ; - RECT 90.765 86.955 90.935 87.125 ; - RECT 90.305 86.955 90.475 87.125 ; - RECT 89.845 86.955 90.015 87.125 ; - RECT 89.385 86.955 89.555 87.125 ; - RECT 88.925 86.955 89.095 87.125 ; - RECT 88.465 86.955 88.635 87.125 ; - RECT 88.005 86.955 88.175 87.125 ; - RECT 87.545 86.955 87.715 87.125 ; - RECT 87.085 86.955 87.255 87.125 ; - RECT 86.625 86.955 86.795 87.125 ; - RECT 86.165 86.955 86.335 87.125 ; - RECT 85.705 86.955 85.875 87.125 ; - RECT 85.245 86.955 85.415 87.125 ; - RECT 84.785 86.955 84.955 87.125 ; - RECT 84.325 86.955 84.495 87.125 ; - RECT 83.865 86.955 84.035 87.125 ; - RECT 83.405 86.955 83.575 87.125 ; - RECT 82.945 86.955 83.115 87.125 ; - RECT 82.485 86.955 82.655 87.125 ; - RECT 82.025 86.955 82.195 87.125 ; - RECT 81.565 86.955 81.735 87.125 ; - RECT 81.105 86.955 81.275 87.125 ; - RECT 80.645 86.955 80.815 87.125 ; - RECT 80.185 86.955 80.355 87.125 ; - RECT 79.725 86.955 79.895 87.125 ; - RECT 79.265 86.955 79.435 87.125 ; - RECT 78.805 86.955 78.975 87.125 ; - RECT 78.345 86.955 78.515 87.125 ; - RECT 77.885 86.955 78.055 87.125 ; - RECT 77.425 86.955 77.595 87.125 ; - RECT 76.965 86.955 77.135 87.125 ; - RECT 76.505 86.955 76.675 87.125 ; - RECT 76.045 86.955 76.215 87.125 ; - RECT 75.585 86.955 75.755 87.125 ; - RECT 75.125 86.955 75.295 87.125 ; - RECT 74.665 86.955 74.835 87.125 ; - RECT 74.205 86.955 74.375 87.125 ; - RECT 73.745 86.955 73.915 87.125 ; - RECT 73.285 86.955 73.455 87.125 ; - RECT 72.825 86.955 72.995 87.125 ; - RECT 72.365 86.955 72.535 87.125 ; - RECT 71.905 86.955 72.075 87.125 ; - RECT 71.445 86.955 71.615 87.125 ; - RECT 70.985 86.955 71.155 87.125 ; - RECT 70.525 86.955 70.695 87.125 ; - RECT 70.065 86.955 70.235 87.125 ; - RECT 69.605 86.955 69.775 87.125 ; - RECT 69.145 86.955 69.315 87.125 ; - RECT 68.685 86.955 68.855 87.125 ; - RECT 68.225 86.955 68.395 87.125 ; - RECT 67.765 86.955 67.935 87.125 ; - RECT 67.305 86.955 67.475 87.125 ; - RECT 66.845 86.955 67.015 87.125 ; - RECT 66.385 86.955 66.555 87.125 ; - RECT 65.925 86.955 66.095 87.125 ; - RECT 65.465 86.955 65.635 87.125 ; - RECT 65.005 86.955 65.175 87.125 ; - RECT 64.545 86.955 64.715 87.125 ; - RECT 64.085 86.955 64.255 87.125 ; - RECT 63.625 86.955 63.795 87.125 ; - RECT 63.165 86.955 63.335 87.125 ; - RECT 62.705 86.955 62.875 87.125 ; - RECT 62.245 86.955 62.415 87.125 ; - RECT 61.785 86.955 61.955 87.125 ; - RECT 61.325 86.955 61.495 87.125 ; - RECT 60.865 86.955 61.035 87.125 ; - RECT 60.405 86.955 60.575 87.125 ; - RECT 59.945 86.955 60.115 87.125 ; - RECT 59.485 86.955 59.655 87.125 ; - RECT 59.025 86.955 59.195 87.125 ; - RECT 58.565 86.955 58.735 87.125 ; - RECT 58.105 86.955 58.275 87.125 ; - RECT 57.645 86.955 57.815 87.125 ; - RECT 57.185 86.955 57.355 87.125 ; - RECT 56.725 86.955 56.895 87.125 ; - RECT 56.265 86.955 56.435 87.125 ; - RECT 55.805 86.955 55.975 87.125 ; - RECT 55.345 86.955 55.515 87.125 ; - RECT 54.885 86.955 55.055 87.125 ; - RECT 54.425 86.955 54.595 87.125 ; - RECT 53.965 86.955 54.135 87.125 ; - RECT 53.505 86.955 53.675 87.125 ; - RECT 53.045 86.955 53.215 87.125 ; - RECT 52.585 86.955 52.755 87.125 ; - RECT 52.125 86.955 52.295 87.125 ; - RECT 51.665 86.955 51.835 87.125 ; - RECT 51.205 86.955 51.375 87.125 ; - RECT 50.745 86.955 50.915 87.125 ; - RECT 50.285 86.955 50.455 87.125 ; - RECT 49.825 86.955 49.995 87.125 ; - RECT 49.365 86.955 49.535 87.125 ; - RECT 48.905 86.955 49.075 87.125 ; - RECT 48.445 86.955 48.615 87.125 ; - RECT 47.985 86.955 48.155 87.125 ; - RECT 47.525 86.955 47.695 87.125 ; - RECT 47.065 86.955 47.235 87.125 ; - RECT 46.605 86.955 46.775 87.125 ; - RECT 46.145 86.955 46.315 87.125 ; - RECT 45.685 86.955 45.855 87.125 ; - RECT 45.225 86.955 45.395 87.125 ; - RECT 44.765 86.955 44.935 87.125 ; - RECT 44.305 86.955 44.475 87.125 ; - RECT 43.845 86.955 44.015 87.125 ; - RECT 43.385 86.955 43.555 87.125 ; - RECT 42.925 86.955 43.095 87.125 ; - RECT 42.465 86.955 42.635 87.125 ; - RECT 42.005 86.955 42.175 87.125 ; - RECT 41.545 86.955 41.715 87.125 ; - RECT 41.085 86.955 41.255 87.125 ; - RECT 40.625 86.955 40.795 87.125 ; - RECT 40.165 86.955 40.335 87.125 ; - RECT 39.705 86.955 39.875 87.125 ; - RECT 39.245 86.955 39.415 87.125 ; - RECT 38.785 86.955 38.955 87.125 ; - RECT 38.325 86.955 38.495 87.125 ; - RECT 37.865 86.955 38.035 87.125 ; - RECT 37.405 86.955 37.575 87.125 ; - RECT 36.945 86.955 37.115 87.125 ; - RECT 36.485 86.955 36.655 87.125 ; - RECT 36.025 86.955 36.195 87.125 ; - RECT 35.565 86.955 35.735 87.125 ; - RECT 35.105 86.955 35.275 87.125 ; - RECT 34.645 86.955 34.815 87.125 ; - RECT 34.185 86.955 34.355 87.125 ; - RECT 33.725 86.955 33.895 87.125 ; - RECT 33.265 86.955 33.435 87.125 ; - RECT 32.805 86.955 32.975 87.125 ; - RECT 32.345 86.955 32.515 87.125 ; - RECT 31.885 86.955 32.055 87.125 ; - RECT 31.425 86.955 31.595 87.125 ; - RECT 30.965 86.955 31.135 87.125 ; - RECT 30.505 86.955 30.675 87.125 ; - RECT 30.045 86.955 30.215 87.125 ; - RECT 29.585 86.955 29.755 87.125 ; - RECT 29.125 86.955 29.295 87.125 ; - RECT 28.665 86.955 28.835 87.125 ; - RECT 28.205 86.955 28.375 87.125 ; - RECT 27.745 86.955 27.915 87.125 ; - RECT 27.285 86.955 27.455 87.125 ; - RECT 26.825 86.955 26.995 87.125 ; - RECT 26.365 86.955 26.535 87.125 ; - RECT 25.905 86.955 26.075 87.125 ; - RECT 25.445 86.955 25.615 87.125 ; - RECT 24.985 86.955 25.155 87.125 ; - RECT 24.525 86.955 24.695 87.125 ; - RECT 24.065 86.955 24.235 87.125 ; - RECT 23.605 86.955 23.775 87.125 ; - RECT 23.145 86.955 23.315 87.125 ; - RECT 22.685 86.955 22.855 87.125 ; - RECT 22.225 86.955 22.395 87.125 ; - RECT 21.765 86.955 21.935 87.125 ; - RECT 21.305 86.955 21.475 87.125 ; - RECT 20.845 86.955 21.015 87.125 ; - RECT 20.385 86.955 20.555 87.125 ; - RECT 19.925 86.955 20.095 87.125 ; - RECT 19.465 86.955 19.635 87.125 ; - RECT 19.005 86.955 19.175 87.125 ; - RECT 18.545 86.955 18.715 87.125 ; - RECT 18.085 86.955 18.255 87.125 ; - RECT 17.625 86.955 17.795 87.125 ; - RECT 17.165 86.955 17.335 87.125 ; - RECT 16.705 86.955 16.875 87.125 ; - RECT 16.245 86.955 16.415 87.125 ; - RECT 15.785 86.955 15.955 87.125 ; - RECT 15.325 86.955 15.495 87.125 ; - RECT 14.865 86.955 15.035 87.125 ; - RECT 14.405 86.955 14.575 87.125 ; - RECT 13.945 86.955 14.115 87.125 ; - RECT 13.485 86.955 13.655 87.125 ; - RECT 13.025 86.955 13.195 87.125 ; - RECT 12.565 86.955 12.735 87.125 ; - RECT 12.105 86.955 12.275 87.125 ; - RECT 11.645 86.955 11.815 87.125 ; - RECT 11.185 86.955 11.355 87.125 ; - RECT 10.725 86.955 10.895 87.125 ; - RECT 10.265 86.955 10.435 87.125 ; - RECT 9.805 86.955 9.975 87.125 ; - RECT 9.345 86.955 9.515 87.125 ; - RECT 8.885 86.955 9.055 87.125 ; - RECT 8.425 86.955 8.595 87.125 ; - RECT 7.965 86.955 8.135 87.125 ; - RECT 7.505 86.955 7.675 87.125 ; - RECT 7.045 86.955 7.215 87.125 ; - RECT 6.585 86.955 6.755 87.125 ; - RECT 6.125 86.955 6.295 87.125 ; - RECT 5.665 86.955 5.835 87.125 ; - RECT 5.205 86.955 5.375 87.125 ; - RECT 4.745 86.955 4.915 87.125 ; - RECT 4.285 86.955 4.455 87.125 ; - RECT 3.825 86.955 3.995 87.125 ; - RECT 3.365 86.955 3.535 87.125 ; - RECT 2.905 86.955 3.075 87.125 ; - RECT 2.445 86.955 2.615 87.125 ; - RECT 1.985 86.955 2.155 87.125 ; - RECT 1.525 86.955 1.695 87.125 ; - RECT 1.065 86.955 1.235 87.125 ; - RECT 0.605 86.955 0.775 87.125 ; - RECT 0.145 86.955 0.315 87.125 ; - RECT 91.685 84.235 91.855 84.405 ; - RECT 91.225 84.235 91.395 84.405 ; - RECT 0.605 84.235 0.775 84.405 ; - RECT 0.145 84.235 0.315 84.405 ; - RECT 91.685 81.515 91.855 81.685 ; - RECT 91.225 81.515 91.395 81.685 ; - RECT 0.605 81.515 0.775 81.685 ; - RECT 0.145 81.515 0.315 81.685 ; - RECT 91.685 78.795 91.855 78.965 ; - RECT 91.225 78.795 91.395 78.965 ; - RECT 0.605 78.795 0.775 78.965 ; - RECT 0.145 78.795 0.315 78.965 ; - RECT 91.685 76.075 91.855 76.245 ; - RECT 91.225 76.075 91.395 76.245 ; - RECT 0.605 76.075 0.775 76.245 ; - RECT 0.145 76.075 0.315 76.245 ; - RECT 91.685 73.355 91.855 73.525 ; - RECT 91.225 73.355 91.395 73.525 ; - RECT 0.605 73.355 0.775 73.525 ; - RECT 0.145 73.355 0.315 73.525 ; - RECT 91.685 70.635 91.855 70.805 ; - RECT 91.225 70.635 91.395 70.805 ; - RECT 0.605 70.635 0.775 70.805 ; - RECT 0.145 70.635 0.315 70.805 ; - RECT 91.685 67.915 91.855 68.085 ; - RECT 91.225 67.915 91.395 68.085 ; - RECT 0.605 67.915 0.775 68.085 ; - RECT 0.145 67.915 0.315 68.085 ; - RECT 91.685 65.195 91.855 65.365 ; - RECT 91.225 65.195 91.395 65.365 ; - RECT 0.605 65.195 0.775 65.365 ; - RECT 0.145 65.195 0.315 65.365 ; - RECT 91.685 62.475 91.855 62.645 ; - RECT 91.225 62.475 91.395 62.645 ; - RECT 0.605 62.475 0.775 62.645 ; - RECT 0.145 62.475 0.315 62.645 ; - RECT 91.685 59.755 91.855 59.925 ; - RECT 91.225 59.755 91.395 59.925 ; - RECT 0.605 59.755 0.775 59.925 ; - RECT 0.145 59.755 0.315 59.925 ; - RECT 91.685 57.035 91.855 57.205 ; - RECT 91.225 57.035 91.395 57.205 ; - RECT 0.605 57.035 0.775 57.205 ; - RECT 0.145 57.035 0.315 57.205 ; - RECT 91.685 54.315 91.855 54.485 ; - RECT 91.225 54.315 91.395 54.485 ; - RECT 0.605 54.315 0.775 54.485 ; - RECT 0.145 54.315 0.315 54.485 ; - RECT 91.685 51.595 91.855 51.765 ; - RECT 91.225 51.595 91.395 51.765 ; - RECT 0.605 51.595 0.775 51.765 ; - RECT 0.145 51.595 0.315 51.765 ; - RECT 91.685 48.875 91.855 49.045 ; - RECT 91.225 48.875 91.395 49.045 ; - RECT 0.605 48.875 0.775 49.045 ; - RECT 0.145 48.875 0.315 49.045 ; - RECT 91.685 46.155 91.855 46.325 ; - RECT 91.225 46.155 91.395 46.325 ; - RECT 0.605 46.155 0.775 46.325 ; - RECT 0.145 46.155 0.315 46.325 ; - RECT 91.685 43.435 91.855 43.605 ; - RECT 91.225 43.435 91.395 43.605 ; - RECT 0.605 43.435 0.775 43.605 ; - RECT 0.145 43.435 0.315 43.605 ; - RECT 91.685 40.715 91.855 40.885 ; - RECT 91.225 40.715 91.395 40.885 ; - RECT 0.605 40.715 0.775 40.885 ; - RECT 0.145 40.715 0.315 40.885 ; - RECT 91.685 37.995 91.855 38.165 ; - RECT 91.225 37.995 91.395 38.165 ; - RECT 0.605 37.995 0.775 38.165 ; - RECT 0.145 37.995 0.315 38.165 ; - RECT 91.685 35.275 91.855 35.445 ; - RECT 91.225 35.275 91.395 35.445 ; - RECT 0.605 35.275 0.775 35.445 ; - RECT 0.145 35.275 0.315 35.445 ; - RECT 91.685 32.555 91.855 32.725 ; - RECT 91.225 32.555 91.395 32.725 ; - RECT 0.605 32.555 0.775 32.725 ; - RECT 0.145 32.555 0.315 32.725 ; - RECT 91.685 29.835 91.855 30.005 ; - RECT 91.225 29.835 91.395 30.005 ; - RECT 0.605 29.835 0.775 30.005 ; - RECT 0.145 29.835 0.315 30.005 ; - RECT 91.685 27.115 91.855 27.285 ; - RECT 91.225 27.115 91.395 27.285 ; - RECT 0.605 27.115 0.775 27.285 ; - RECT 0.145 27.115 0.315 27.285 ; - RECT 91.685 24.395 91.855 24.565 ; - RECT 91.225 24.395 91.395 24.565 ; - RECT 0.605 24.395 0.775 24.565 ; - RECT 0.145 24.395 0.315 24.565 ; - RECT 91.685 21.675 91.855 21.845 ; - RECT 91.225 21.675 91.395 21.845 ; - RECT 0.605 21.675 0.775 21.845 ; - RECT 0.145 21.675 0.315 21.845 ; - RECT 91.685 18.955 91.855 19.125 ; - RECT 91.225 18.955 91.395 19.125 ; - RECT 0.605 18.955 0.775 19.125 ; - RECT 0.145 18.955 0.315 19.125 ; - RECT 91.685 16.235 91.855 16.405 ; - RECT 91.225 16.235 91.395 16.405 ; - RECT 0.605 16.235 0.775 16.405 ; - RECT 0.145 16.235 0.315 16.405 ; - RECT 91.685 13.515 91.855 13.685 ; - RECT 91.225 13.515 91.395 13.685 ; - RECT 0.605 13.515 0.775 13.685 ; - RECT 0.145 13.515 0.315 13.685 ; - RECT 91.685 10.795 91.855 10.965 ; - RECT 91.225 10.795 91.395 10.965 ; - RECT 0.605 10.795 0.775 10.965 ; - RECT 0.145 10.795 0.315 10.965 ; - RECT 91.685 8.075 91.855 8.245 ; - RECT 91.225 8.075 91.395 8.245 ; - RECT 0.605 8.075 0.775 8.245 ; - RECT 0.145 8.075 0.315 8.245 ; - RECT 91.685 5.355 91.855 5.525 ; - RECT 91.225 5.355 91.395 5.525 ; - RECT 0.605 5.355 0.775 5.525 ; - RECT 0.145 5.355 0.315 5.525 ; - RECT 91.685 2.635 91.855 2.805 ; - RECT 91.225 2.635 91.395 2.805 ; - RECT 0.605 2.635 0.775 2.805 ; - RECT 0.145 2.635 0.315 2.805 ; - RECT 91.685 -0.085 91.855 0.085 ; - RECT 91.225 -0.085 91.395 0.085 ; - RECT 90.765 -0.085 90.935 0.085 ; - RECT 90.305 -0.085 90.475 0.085 ; - RECT 89.845 -0.085 90.015 0.085 ; - RECT 89.385 -0.085 89.555 0.085 ; - RECT 88.925 -0.085 89.095 0.085 ; - RECT 88.465 -0.085 88.635 0.085 ; - RECT 88.005 -0.085 88.175 0.085 ; - RECT 87.545 -0.085 87.715 0.085 ; - RECT 87.085 -0.085 87.255 0.085 ; - RECT 86.625 -0.085 86.795 0.085 ; - RECT 86.165 -0.085 86.335 0.085 ; - RECT 85.705 -0.085 85.875 0.085 ; - RECT 85.245 -0.085 85.415 0.085 ; - RECT 84.785 -0.085 84.955 0.085 ; - RECT 84.325 -0.085 84.495 0.085 ; - RECT 83.865 -0.085 84.035 0.085 ; - RECT 83.405 -0.085 83.575 0.085 ; - RECT 82.945 -0.085 83.115 0.085 ; - RECT 82.485 -0.085 82.655 0.085 ; - RECT 82.025 -0.085 82.195 0.085 ; - RECT 81.565 -0.085 81.735 0.085 ; - RECT 81.105 -0.085 81.275 0.085 ; - RECT 80.645 -0.085 80.815 0.085 ; - RECT 80.185 -0.085 80.355 0.085 ; - RECT 79.725 -0.085 79.895 0.085 ; - RECT 79.265 -0.085 79.435 0.085 ; - RECT 78.805 -0.085 78.975 0.085 ; - RECT 78.345 -0.085 78.515 0.085 ; - RECT 77.885 -0.085 78.055 0.085 ; - RECT 77.425 -0.085 77.595 0.085 ; - RECT 76.965 -0.085 77.135 0.085 ; - RECT 76.505 -0.085 76.675 0.085 ; - RECT 76.045 -0.085 76.215 0.085 ; - RECT 75.585 -0.085 75.755 0.085 ; - RECT 75.125 -0.085 75.295 0.085 ; - RECT 74.665 -0.085 74.835 0.085 ; - RECT 74.205 -0.085 74.375 0.085 ; - RECT 73.745 -0.085 73.915 0.085 ; - RECT 73.285 -0.085 73.455 0.085 ; - RECT 72.825 -0.085 72.995 0.085 ; - RECT 72.365 -0.085 72.535 0.085 ; - RECT 71.905 -0.085 72.075 0.085 ; - RECT 71.445 -0.085 71.615 0.085 ; - RECT 70.985 -0.085 71.155 0.085 ; - RECT 70.525 -0.085 70.695 0.085 ; - RECT 70.065 -0.085 70.235 0.085 ; - RECT 69.605 -0.085 69.775 0.085 ; - RECT 69.145 -0.085 69.315 0.085 ; - RECT 68.685 -0.085 68.855 0.085 ; - RECT 68.225 -0.085 68.395 0.085 ; - RECT 67.765 -0.085 67.935 0.085 ; - RECT 67.305 -0.085 67.475 0.085 ; - RECT 66.845 -0.085 67.015 0.085 ; - RECT 66.385 -0.085 66.555 0.085 ; - RECT 65.925 -0.085 66.095 0.085 ; - RECT 65.465 -0.085 65.635 0.085 ; - RECT 65.005 -0.085 65.175 0.085 ; - RECT 64.545 -0.085 64.715 0.085 ; - RECT 64.085 -0.085 64.255 0.085 ; - RECT 63.625 -0.085 63.795 0.085 ; - RECT 63.165 -0.085 63.335 0.085 ; - RECT 62.705 -0.085 62.875 0.085 ; - RECT 62.245 -0.085 62.415 0.085 ; - RECT 61.785 -0.085 61.955 0.085 ; - RECT 61.325 -0.085 61.495 0.085 ; - RECT 60.865 -0.085 61.035 0.085 ; - RECT 60.405 -0.085 60.575 0.085 ; - RECT 59.945 -0.085 60.115 0.085 ; - RECT 59.485 -0.085 59.655 0.085 ; - RECT 59.025 -0.085 59.195 0.085 ; - RECT 58.565 -0.085 58.735 0.085 ; - RECT 58.105 -0.085 58.275 0.085 ; - RECT 57.645 -0.085 57.815 0.085 ; - RECT 57.185 -0.085 57.355 0.085 ; - RECT 56.725 -0.085 56.895 0.085 ; - RECT 56.265 -0.085 56.435 0.085 ; - RECT 55.805 -0.085 55.975 0.085 ; - RECT 55.345 -0.085 55.515 0.085 ; - RECT 54.885 -0.085 55.055 0.085 ; - RECT 54.425 -0.085 54.595 0.085 ; - RECT 53.965 -0.085 54.135 0.085 ; - RECT 53.505 -0.085 53.675 0.085 ; - RECT 53.045 -0.085 53.215 0.085 ; - RECT 52.585 -0.085 52.755 0.085 ; - RECT 52.125 -0.085 52.295 0.085 ; - RECT 51.665 -0.085 51.835 0.085 ; - RECT 51.205 -0.085 51.375 0.085 ; - RECT 50.745 -0.085 50.915 0.085 ; - RECT 50.285 -0.085 50.455 0.085 ; - RECT 49.825 -0.085 49.995 0.085 ; - RECT 49.365 -0.085 49.535 0.085 ; - RECT 48.905 -0.085 49.075 0.085 ; - RECT 48.445 -0.085 48.615 0.085 ; - RECT 47.985 -0.085 48.155 0.085 ; - RECT 47.525 -0.085 47.695 0.085 ; - RECT 47.065 -0.085 47.235 0.085 ; - RECT 46.605 -0.085 46.775 0.085 ; - RECT 46.145 -0.085 46.315 0.085 ; - RECT 45.685 -0.085 45.855 0.085 ; - RECT 45.225 -0.085 45.395 0.085 ; - RECT 44.765 -0.085 44.935 0.085 ; - RECT 44.305 -0.085 44.475 0.085 ; - RECT 43.845 -0.085 44.015 0.085 ; - RECT 43.385 -0.085 43.555 0.085 ; - RECT 42.925 -0.085 43.095 0.085 ; - RECT 42.465 -0.085 42.635 0.085 ; - RECT 42.005 -0.085 42.175 0.085 ; - RECT 41.545 -0.085 41.715 0.085 ; - RECT 41.085 -0.085 41.255 0.085 ; - RECT 40.625 -0.085 40.795 0.085 ; - RECT 40.165 -0.085 40.335 0.085 ; - RECT 39.705 -0.085 39.875 0.085 ; - RECT 39.245 -0.085 39.415 0.085 ; - RECT 38.785 -0.085 38.955 0.085 ; - RECT 38.325 -0.085 38.495 0.085 ; - RECT 37.865 -0.085 38.035 0.085 ; - RECT 37.405 -0.085 37.575 0.085 ; - RECT 36.945 -0.085 37.115 0.085 ; - RECT 36.485 -0.085 36.655 0.085 ; - RECT 36.025 -0.085 36.195 0.085 ; - RECT 35.565 -0.085 35.735 0.085 ; - RECT 35.105 -0.085 35.275 0.085 ; - RECT 34.645 -0.085 34.815 0.085 ; - RECT 34.185 -0.085 34.355 0.085 ; - RECT 33.725 -0.085 33.895 0.085 ; - RECT 33.265 -0.085 33.435 0.085 ; - RECT 32.805 -0.085 32.975 0.085 ; - RECT 32.345 -0.085 32.515 0.085 ; - RECT 31.885 -0.085 32.055 0.085 ; - RECT 31.425 -0.085 31.595 0.085 ; - RECT 30.965 -0.085 31.135 0.085 ; - RECT 30.505 -0.085 30.675 0.085 ; - RECT 30.045 -0.085 30.215 0.085 ; - RECT 29.585 -0.085 29.755 0.085 ; - RECT 29.125 -0.085 29.295 0.085 ; - RECT 28.665 -0.085 28.835 0.085 ; - RECT 28.205 -0.085 28.375 0.085 ; - RECT 27.745 -0.085 27.915 0.085 ; - RECT 27.285 -0.085 27.455 0.085 ; - RECT 26.825 -0.085 26.995 0.085 ; - RECT 26.365 -0.085 26.535 0.085 ; - RECT 25.905 -0.085 26.075 0.085 ; - RECT 25.445 -0.085 25.615 0.085 ; - RECT 24.985 -0.085 25.155 0.085 ; - RECT 24.525 -0.085 24.695 0.085 ; - RECT 24.065 -0.085 24.235 0.085 ; - RECT 23.605 -0.085 23.775 0.085 ; - RECT 23.145 -0.085 23.315 0.085 ; - RECT 22.685 -0.085 22.855 0.085 ; - RECT 22.225 -0.085 22.395 0.085 ; - RECT 21.765 -0.085 21.935 0.085 ; - RECT 21.305 -0.085 21.475 0.085 ; - RECT 20.845 -0.085 21.015 0.085 ; - RECT 20.385 -0.085 20.555 0.085 ; - RECT 19.925 -0.085 20.095 0.085 ; - RECT 19.465 -0.085 19.635 0.085 ; - RECT 19.005 -0.085 19.175 0.085 ; - RECT 18.545 -0.085 18.715 0.085 ; - RECT 18.085 -0.085 18.255 0.085 ; - RECT 17.625 -0.085 17.795 0.085 ; - RECT 17.165 -0.085 17.335 0.085 ; - RECT 16.705 -0.085 16.875 0.085 ; - RECT 16.245 -0.085 16.415 0.085 ; - RECT 15.785 -0.085 15.955 0.085 ; - RECT 15.325 -0.085 15.495 0.085 ; - RECT 14.865 -0.085 15.035 0.085 ; - RECT 14.405 -0.085 14.575 0.085 ; - RECT 13.945 -0.085 14.115 0.085 ; - RECT 13.485 -0.085 13.655 0.085 ; - RECT 13.025 -0.085 13.195 0.085 ; - RECT 12.565 -0.085 12.735 0.085 ; - RECT 12.105 -0.085 12.275 0.085 ; - RECT 11.645 -0.085 11.815 0.085 ; - RECT 11.185 -0.085 11.355 0.085 ; - RECT 10.725 -0.085 10.895 0.085 ; - RECT 10.265 -0.085 10.435 0.085 ; - RECT 9.805 -0.085 9.975 0.085 ; - RECT 9.345 -0.085 9.515 0.085 ; - RECT 8.885 -0.085 9.055 0.085 ; - RECT 8.425 -0.085 8.595 0.085 ; - RECT 7.965 -0.085 8.135 0.085 ; - RECT 7.505 -0.085 7.675 0.085 ; - RECT 7.045 -0.085 7.215 0.085 ; - RECT 6.585 -0.085 6.755 0.085 ; - RECT 6.125 -0.085 6.295 0.085 ; - RECT 5.665 -0.085 5.835 0.085 ; - RECT 5.205 -0.085 5.375 0.085 ; - RECT 4.745 -0.085 4.915 0.085 ; - RECT 4.285 -0.085 4.455 0.085 ; - RECT 3.825 -0.085 3.995 0.085 ; - RECT 3.365 -0.085 3.535 0.085 ; - RECT 2.905 -0.085 3.075 0.085 ; - RECT 2.445 -0.085 2.615 0.085 ; - RECT 1.985 -0.085 2.155 0.085 ; - RECT 1.525 -0.085 1.695 0.085 ; - RECT 1.065 -0.085 1.235 0.085 ; - RECT 0.605 -0.085 0.775 0.085 ; - RECT 0.145 -0.085 0.315 0.085 ; - LAYER via ; - RECT 80.885 97.845 81.035 97.995 ; - RECT 51.445 97.845 51.595 97.995 ; - RECT 69.385 96.145 69.535 96.295 ; - RECT 80.885 86.965 81.035 87.115 ; - RECT 51.445 86.965 51.595 87.115 ; - RECT 10.965 86.965 11.115 87.115 ; - RECT 80.885 -0.075 81.035 0.075 ; - RECT 51.445 -0.075 51.595 0.075 ; - RECT 10.965 -0.075 11.115 0.075 ; - LAYER via2 ; - RECT 80.86 97.82 81.06 98.02 ; - RECT 51.42 97.82 51.62 98.02 ; - RECT 10.94 86.94 11.14 87.14 ; - RECT 1.28 70.62 1.48 70.82 ; - RECT 1.28 46.14 1.48 46.34 ; - RECT 1.28 40.7 1.48 40.9 ; - RECT 1.28 23.02 1.48 23.22 ; - RECT 1.28 16.9 1.48 17.1 ; - RECT 1.28 13.5 1.48 13.7 ; - RECT 80.86 -0.1 81.06 0.1 ; - RECT 51.42 -0.1 51.62 0.1 ; - RECT 10.94 -0.1 11.14 0.1 ; - LAYER via3 ; - RECT 80.86 97.82 81.06 98.02 ; - RECT 51.42 97.82 51.62 98.02 ; - RECT 10.94 86.94 11.14 87.14 ; - RECT 80.86 -0.1 81.06 0.1 ; - RECT 51.42 -0.1 51.62 0.1 ; - RECT 10.94 -0.1 11.14 0.1 ; - LAYER OVERLAP ; - POLYGON 0 0 0 87.04 25.76 87.04 25.76 97.92 92 97.92 92 0 ; - END -END sb_2__0_ - -END LIBRARY diff --git a/FPGA22_HIER_SKY_PNR/modules/lef/sb_2__1__icv_in_design.lef b/FPGA22_HIER_SKY_PNR/modules/lef/sb_2__1__icv_in_design.lef deleted file mode 100644 index 44def72..0000000 --- a/FPGA22_HIER_SKY_PNR/modules/lef/sb_2__1__icv_in_design.lef +++ /dev/null @@ -1,2695 +0,0 @@ -VERSION 5.7 ; -BUSBITCHARS "[]" ; - -UNITS - DATABASE MICRONS 1000 ; -END UNITS - -MANUFACTURINGGRID 0.005 ; - -LAYER li1 - TYPE ROUTING ; - DIRECTION VERTICAL ; - PITCH 0.46 ; - WIDTH 0.17 ; -END li1 - -LAYER mcon - TYPE CUT ; -END mcon - -LAYER met1 - TYPE ROUTING ; - DIRECTION HORIZONTAL ; - PITCH 0.34 ; - WIDTH 0.14 ; -END met1 - -LAYER via - TYPE CUT ; -END via - -LAYER met2 - TYPE ROUTING ; - DIRECTION VERTICAL ; - PITCH 0.46 ; - WIDTH 0.14 ; -END met2 - -LAYER via2 - TYPE CUT ; -END via2 - -LAYER met3 - TYPE ROUTING ; - DIRECTION HORIZONTAL ; - PITCH 0.68 ; - WIDTH 0.3 ; -END met3 - -LAYER via3 - TYPE CUT ; -END via3 - -LAYER met4 - TYPE ROUTING ; - DIRECTION VERTICAL ; - PITCH 0.92 ; - WIDTH 0.3 ; -END met4 - -LAYER via4 - TYPE CUT ; -END via4 - -LAYER met5 - TYPE ROUTING ; - DIRECTION HORIZONTAL ; - PITCH 3.4 ; - WIDTH 1.6 ; -END met5 - -LAYER nwell - TYPE MASTERSLICE ; -END nwell - -LAYER pwell - TYPE MASTERSLICE ; -END pwell - -LAYER OVERLAP - TYPE OVERLAP ; -END OVERLAP - -VIA L1M1_PR - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.145 -0.115 0.145 0.115 ; -END L1M1_PR - -VIA L1M1_PR_R - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.115 -0.145 0.115 0.145 ; -END L1M1_PR_R - -VIA L1M1_PR_M - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.115 -0.145 0.115 0.145 ; -END L1M1_PR_M - -VIA L1M1_PR_MR - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.145 -0.115 0.145 0.115 ; -END L1M1_PR_MR - -VIA L1M1_PR_C - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.145 -0.145 0.145 0.145 ; -END L1M1_PR_C - -VIA M1M2_PR - LAYER met1 ; - RECT -0.16 -0.13 0.16 0.13 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.13 -0.16 0.13 0.16 ; -END M1M2_PR - -VIA M1M2_PR_Enc - LAYER met1 ; - RECT -0.16 -0.13 0.16 0.13 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.16 -0.13 0.16 0.13 ; -END M1M2_PR_Enc - -VIA M1M2_PR_R - LAYER met1 ; - RECT -0.13 -0.16 0.13 0.16 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.16 -0.13 0.16 0.13 ; -END M1M2_PR_R - -VIA M1M2_PR_R_Enc - LAYER met1 ; - RECT -0.13 -0.16 0.13 0.16 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.13 -0.16 0.13 0.16 ; -END M1M2_PR_R_Enc - -VIA M1M2_PR_M - LAYER met1 ; - RECT -0.16 -0.13 0.16 0.13 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.16 -0.13 0.16 0.13 ; -END M1M2_PR_M - -VIA M1M2_PR_M_Enc - LAYER met1 ; - RECT -0.16 -0.13 0.16 0.13 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.13 -0.16 0.13 0.16 ; -END M1M2_PR_M_Enc - -VIA M1M2_PR_MR - LAYER met1 ; - RECT -0.13 -0.16 0.13 0.16 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.13 -0.16 0.13 0.16 ; -END M1M2_PR_MR - -VIA M1M2_PR_MR_Enc - LAYER met1 ; - RECT -0.13 -0.16 0.13 0.16 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.16 -0.13 0.16 0.13 ; -END M1M2_PR_MR_Enc - -VIA M1M2_PR_C - LAYER met1 ; - RECT -0.16 -0.16 0.16 0.16 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.16 -0.16 0.16 0.16 ; -END M1M2_PR_C - -VIA M2M3_PR - LAYER met2 ; - RECT -0.14 -0.185 0.14 0.185 ; - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met3 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M2M3_PR - -VIA M2M3_PR_R - LAYER met2 ; - RECT -0.185 -0.14 0.185 0.14 ; - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met3 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M2M3_PR_R - -VIA M2M3_PR_M - LAYER met2 ; - RECT -0.14 -0.185 0.14 0.185 ; - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met3 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M2M3_PR_M - -VIA M2M3_PR_MR - LAYER met2 ; - RECT -0.185 -0.14 0.185 0.14 ; - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met3 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M2M3_PR_MR - -VIA M2M3_PR_C - LAYER met2 ; - RECT -0.185 -0.185 0.185 0.185 ; - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met3 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M2M3_PR_C - -VIA M3M4_PR - LAYER met3 ; - RECT -0.19 -0.16 0.19 0.16 ; - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR - -VIA M3M4_PR_R - LAYER met3 ; - RECT -0.16 -0.19 0.16 0.19 ; - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR_R - -VIA M3M4_PR_M - LAYER met3 ; - RECT -0.19 -0.16 0.19 0.16 ; - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR_M - -VIA M3M4_PR_MR - LAYER met3 ; - RECT -0.16 -0.19 0.16 0.19 ; - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR_MR - -VIA M3M4_PR_C - LAYER met3 ; - RECT -0.19 -0.19 0.19 0.19 ; - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR_C - -VIA M4M5_PR - LAYER met4 ; - RECT -0.59 -0.59 0.59 0.59 ; - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - LAYER met5 ; - RECT -0.71 -0.71 0.71 0.71 ; -END M4M5_PR - -VIA M4M5_PR_R - LAYER met4 ; - RECT -0.59 -0.59 0.59 0.59 ; - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - LAYER met5 ; - RECT -0.71 -0.71 0.71 0.71 ; -END M4M5_PR_R - -VIA M4M5_PR_M - LAYER met4 ; - RECT -0.59 -0.59 0.59 0.59 ; - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - LAYER met5 ; - RECT -0.71 -0.71 0.71 0.71 ; -END M4M5_PR_M - -VIA M4M5_PR_MR - LAYER met4 ; - RECT -0.59 -0.59 0.59 0.59 ; - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - LAYER met5 ; - RECT -0.71 -0.71 0.71 0.71 ; -END M4M5_PR_MR - -VIA M4M5_PR_C - LAYER met4 ; - RECT -0.59 -0.59 0.59 0.59 ; - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - LAYER met5 ; - RECT -0.71 -0.71 0.71 0.71 ; -END M4M5_PR_C - -SITE unit - CLASS CORE ; - SYMMETRY Y ; - SIZE 0.46 BY 2.72 ; -END unit - -SITE unithddbl - CLASS CORE ; - SIZE 0.46 BY 5.44 ; -END unithddbl - -MACRO sb_2__1_ - CLASS BLOCK ; - ORIGIN 0 0 ; - SIZE 92 BY 108.8 ; - SYMMETRY X Y ; - PIN prog_clk[0] - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER met3 ; - RECT 0 35.21 1.38 35.51 ; - END - END prog_clk[0] - PIN chany_top_in[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 59.27 107.44 59.41 108.8 ; - END - END chany_top_in[0] - PIN chany_top_in[1] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 63.33 107.44 63.63 108.8 ; - END - END chany_top_in[1] - PIN chany_top_in[2] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 72.53 107.44 72.83 108.8 ; - END - END chany_top_in[2] - PIN chany_top_in[3] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 52.37 107.44 52.51 108.8 ; - END - END chany_top_in[3] - PIN chany_top_in[4] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 67.55 107.44 67.69 108.8 ; - END - END chany_top_in[4] - PIN chany_top_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 64.79 107.44 64.93 108.8 ; - END - END chany_top_in[5] - PIN chany_top_in[6] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 73.07 107.44 73.21 108.8 ; - END - END chany_top_in[6] - PIN chany_top_in[7] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 48.69 107.44 48.83 108.8 ; - END - END chany_top_in[7] - PIN chany_top_in[8] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 56.05 107.44 56.19 108.8 ; - END - END chany_top_in[8] - PIN chany_top_in[9] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 59.65 107.44 59.95 108.8 ; - END - END chany_top_in[9] - PIN chany_top_in[10] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 53.21 107.44 53.51 108.8 ; - END - END chany_top_in[10] - PIN chany_top_in[11] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 46.85 107.44 46.99 108.8 ; - END - END chany_top_in[11] - PIN chany_top_in[12] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 49.61 107.44 49.75 108.8 ; - END - END chany_top_in[12] - PIN chany_top_in[13] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 43.63 107.44 43.77 108.8 ; - END - END chany_top_in[13] - PIN chany_top_in[14] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 69.39 107.44 69.53 108.8 ; - END - END chany_top_in[14] - PIN chany_top_in[15] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 61.11 107.44 61.25 108.8 ; - END - END chany_top_in[15] - PIN chany_top_in[16] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 68.47 107.44 68.61 108.8 ; - END - END chany_top_in[16] - PIN chany_top_in[17] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 73.99 107.44 74.13 108.8 ; - END - END chany_top_in[17] - PIN chany_top_in[18] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 71.23 107.44 71.37 108.8 ; - END - END chany_top_in[18] - PIN chany_top_in[19] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 65.71 107.44 65.85 108.8 ; - END - END chany_top_in[19] - PIN top_left_grid_pin_42_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 9.13 96.56 9.27 97.92 ; - END - END top_left_grid_pin_42_[0] - PIN top_left_grid_pin_43_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 6.83 96.56 6.97 97.92 ; - END - END top_left_grid_pin_43_[0] - PIN top_left_grid_pin_44_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 12.81 96.56 12.95 97.92 ; - END - END top_left_grid_pin_44_[0] - PIN top_left_grid_pin_45_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 18.25 96.56 18.55 97.92 ; - END - END top_left_grid_pin_45_[0] - PIN top_left_grid_pin_46_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 14.19 96.56 14.33 97.92 ; - END - END top_left_grid_pin_46_[0] - PIN top_left_grid_pin_47_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 7.75 96.56 7.89 97.92 ; - END - END top_left_grid_pin_47_[0] - PIN top_left_grid_pin_48_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 16.03 96.56 16.17 97.92 ; - END - END top_left_grid_pin_48_[0] - PIN top_left_grid_pin_49_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 18.33 96.56 18.47 97.92 ; - END - END top_left_grid_pin_49_[0] - PIN top_right_grid_pin_1_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 54.21 107.44 54.35 108.8 ; - END - END top_right_grid_pin_1_[0] - PIN chany_bottom_in[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 55.59 0 55.73 1.36 ; - END - END chany_bottom_in[0] - PIN chany_bottom_in[1] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 50.53 0 50.67 1.36 ; - END - END chany_bottom_in[1] - PIN chany_bottom_in[2] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 56.89 0 57.19 1.36 ; - END - END chany_bottom_in[2] - PIN chany_bottom_in[3] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 46.85 0 46.99 1.36 ; - END - END chany_bottom_in[3] - PIN chany_bottom_in[4] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 54.21 0 54.35 1.36 ; - END - END chany_bottom_in[4] - PIN chany_bottom_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 53.29 0 53.43 1.36 ; - END - END chany_bottom_in[5] - PIN chany_bottom_in[6] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 69.39 0 69.53 1.36 ; - END - END chany_bottom_in[6] - PIN chany_bottom_in[7] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 62.95 0 63.09 1.36 ; - END - END chany_bottom_in[7] - PIN chany_bottom_in[8] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 72.61 0 72.75 1.36 ; - END - END chany_bottom_in[8] - PIN chany_bottom_in[9] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 64.79 0 64.93 1.36 ; - END - END chany_bottom_in[9] - PIN chany_bottom_in[10] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 39.95 0 40.09 1.36 ; - END - END chany_bottom_in[10] - PIN chany_bottom_in[11] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 62.03 0 62.17 1.36 ; - END - END chany_bottom_in[11] - PIN chany_bottom_in[12] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 42.71 0 42.85 1.36 ; - END - END chany_bottom_in[12] - PIN chany_bottom_in[13] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 44.09 0 44.23 1.36 ; - END - END chany_bottom_in[13] - PIN chany_bottom_in[14] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 56.51 0 56.65 1.36 ; - END - END chany_bottom_in[14] - PIN chany_bottom_in[15] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 60.19 0 60.33 1.36 ; - END - END chany_bottom_in[15] - PIN chany_bottom_in[16] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 68.47 0 68.61 1.36 ; - END - END chany_bottom_in[16] - PIN chany_bottom_in[17] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 73.53 0 73.67 1.36 ; - END - END chany_bottom_in[17] - PIN chany_bottom_in[18] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 74.45 0 74.59 1.36 ; - END - END chany_bottom_in[18] - PIN chany_bottom_in[19] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 61.11 0 61.25 1.36 ; - END - END chany_bottom_in[19] - PIN bottom_right_grid_pin_1_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 39.03 0 39.17 1.36 ; - END - END bottom_right_grid_pin_1_[0] - PIN bottom_left_grid_pin_42_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 12.73 10.88 13.03 12.24 ; - END - END bottom_left_grid_pin_42_[0] - PIN bottom_left_grid_pin_43_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 9.05 10.88 9.35 12.24 ; - END - END bottom_left_grid_pin_43_[0] - PIN bottom_left_grid_pin_44_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 27.99 0 28.13 1.36 ; - END - END bottom_left_grid_pin_44_[0] - PIN bottom_left_grid_pin_45_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 7.29 10.88 7.43 12.24 ; - END - END bottom_left_grid_pin_45_[0] - PIN bottom_left_grid_pin_46_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 9.13 10.88 9.27 12.24 ; - END - END bottom_left_grid_pin_46_[0] - PIN bottom_left_grid_pin_47_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 15.11 10.88 15.25 12.24 ; - END - END bottom_left_grid_pin_47_[0] - PIN bottom_left_grid_pin_48_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 8.21 10.88 8.35 12.24 ; - END - END bottom_left_grid_pin_48_[0] - PIN bottom_left_grid_pin_49_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 10.05 10.88 10.19 12.24 ; - END - END bottom_left_grid_pin_49_[0] - PIN chanx_left_in[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 66.49 1.38 66.79 ; - END - END chanx_left_in[0] - PIN chanx_left_in[1] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 84.17 1.38 84.47 ; - END - END chanx_left_in[1] - PIN chanx_left_in[2] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 85.53 1.38 85.83 ; - END - END chanx_left_in[2] - PIN chanx_left_in[3] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 37.25 1.38 37.55 ; - END - END chanx_left_in[3] - PIN chanx_left_in[4] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 44.05 1.38 44.35 ; - END - END chanx_left_in[4] - PIN chanx_left_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 31.81 1.38 32.11 ; - END - END chanx_left_in[5] - PIN chanx_left_in[6] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 89.61 1.38 89.91 ; - END - END chanx_left_in[6] - PIN chanx_left_in[7] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 65.13 1.38 65.43 ; - END - END chanx_left_in[7] - PIN chanx_left_in[8] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 56.97 1.38 57.27 ; - END - END chanx_left_in[8] - PIN chanx_left_in[9] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 81.45 1.38 81.75 ; - END - END chanx_left_in[9] - PIN chanx_left_in[10] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 49.49 1.38 49.79 ; - END - END chanx_left_in[10] - PIN chanx_left_in[11] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 75.33 1.38 75.63 ; - END - END chanx_left_in[11] - PIN chanx_left_in[12] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 92.33 1.38 92.63 ; - END - END chanx_left_in[12] - PIN chanx_left_in[13] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 45.41 1.38 45.71 ; - END - END chanx_left_in[13] - PIN chanx_left_in[14] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 86.89 1.38 87.19 ; - END - END chanx_left_in[14] - PIN chanx_left_in[15] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 71.25 1.38 71.55 ; - END - END chanx_left_in[15] - PIN chanx_left_in[16] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 41.33 1.38 41.63 ; - END - END chanx_left_in[16] - PIN chanx_left_in[17] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 38.61 1.38 38.91 ; - END - END chanx_left_in[17] - PIN chanx_left_in[18] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 73.97 1.38 74.27 ; - END - END chanx_left_in[18] - PIN chanx_left_in[19] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 72.61 1.38 72.91 ; - END - END chanx_left_in[19] - PIN left_bottom_grid_pin_34_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 28.91 0 29.05 1.36 ; - END - END left_bottom_grid_pin_34_[0] - PIN left_bottom_grid_pin_35_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 12.81 10.88 12.95 12.24 ; - END - END left_bottom_grid_pin_35_[0] - PIN left_bottom_grid_pin_36_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 4.99 10.88 5.13 12.24 ; - END - END left_bottom_grid_pin_36_[0] - PIN left_bottom_grid_pin_37_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 4.07 10.88 4.21 12.24 ; - END - END left_bottom_grid_pin_37_[0] - PIN left_bottom_grid_pin_38_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 6.37 10.88 6.51 12.24 ; - END - END left_bottom_grid_pin_38_[0] - PIN left_bottom_grid_pin_39_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 4.45 10.88 4.75 12.24 ; - END - END left_bottom_grid_pin_39_[0] - PIN left_bottom_grid_pin_40_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 11.89 10.88 12.03 12.24 ; - END - END left_bottom_grid_pin_40_[0] - PIN left_bottom_grid_pin_41_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 16.03 10.88 16.17 12.24 ; - END - END left_bottom_grid_pin_41_[0] - PIN ccff_head[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 38.57 107.44 38.71 108.8 ; - END - END ccff_head[0] - PIN chany_top_out[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 37.65 107.44 37.79 108.8 ; - END - END chany_top_out[0] - PIN chany_top_out[1] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 50.53 107.44 50.67 108.8 ; - END - END chany_top_out[1] - PIN chany_top_out[2] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 63.87 107.44 64.01 108.8 ; - END - END chany_top_out[2] - PIN chany_top_out[3] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 36.73 107.44 36.87 108.8 ; - END - END chany_top_out[3] - PIN chany_top_out[4] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 57.43 107.44 57.57 108.8 ; - END - END chany_top_out[4] - PIN chany_top_out[5] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 45.93 107.44 46.07 108.8 ; - END - END chany_top_out[5] - PIN chany_top_out[6] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 62.95 107.44 63.09 108.8 ; - END - END chany_top_out[6] - PIN chany_top_out[7] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 42.25 107.44 42.39 108.8 ; - END - END chany_top_out[7] - PIN chany_top_out[8] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 60.19 107.44 60.33 108.8 ; - END - END chany_top_out[8] - PIN chany_top_out[9] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 39.49 107.44 39.63 108.8 ; - END - END chany_top_out[9] - PIN chany_top_out[10] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 66.63 107.44 66.77 108.8 ; - END - END chany_top_out[10] - PIN chany_top_out[11] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 40.41 107.44 40.55 108.8 ; - END - END chany_top_out[11] - PIN chany_top_out[12] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 62.03 107.44 62.17 108.8 ; - END - END chany_top_out[12] - PIN chany_top_out[13] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 41.33 107.44 41.47 108.8 ; - END - END chany_top_out[13] - PIN chany_top_out[14] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 72.15 107.44 72.29 108.8 ; - END - END chany_top_out[14] - PIN chany_top_out[15] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 47.77 107.44 47.91 108.8 ; - END - END chany_top_out[15] - PIN chany_top_out[16] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 81.81 107.44 81.95 108.8 ; - END - END chany_top_out[16] - PIN chany_top_out[17] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 44.55 107.44 44.69 108.8 ; - END - END chany_top_out[17] - PIN chany_top_out[18] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 70.31 107.44 70.45 108.8 ; - END - END chany_top_out[18] - PIN chany_top_out[19] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 32.13 107.44 32.27 108.8 ; - END - END chany_top_out[19] - PIN chany_bottom_out[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 63.87 0 64.01 1.36 ; - END - END chany_bottom_out[0] - PIN chany_bottom_out[1] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 58.73 0 59.03 1.36 ; - END - END chany_bottom_out[1] - PIN chany_bottom_out[2] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 81.81 0 81.95 1.36 ; - END - END chany_bottom_out[2] - PIN chany_bottom_out[3] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 40.87 0 41.01 1.36 ; - END - END chany_bottom_out[3] - PIN chany_bottom_out[4] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 37.19 0 37.33 1.36 ; - END - END chany_bottom_out[4] - PIN chany_bottom_out[5] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 41.79 0 41.93 1.36 ; - END - END chany_bottom_out[5] - PIN chany_bottom_out[6] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 66.17 0 66.31 1.36 ; - END - END chany_bottom_out[6] - PIN chany_bottom_out[7] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 47.77 0 47.91 1.36 ; - END - END chany_bottom_out[7] - PIN chany_bottom_out[8] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 57.43 0 57.57 1.36 ; - END - END chany_bottom_out[8] - PIN chany_bottom_out[9] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 38.11 0 38.25 1.36 ; - END - END chany_bottom_out[9] - PIN chany_bottom_out[10] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 71.69 0 71.83 1.36 ; - END - END chany_bottom_out[10] - PIN chany_bottom_out[11] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 33.97 0 34.11 1.36 ; - END - END chany_bottom_out[11] - PIN chany_bottom_out[12] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 58.81 0 58.95 1.36 ; - END - END chany_bottom_out[12] - PIN chany_bottom_out[13] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 32.13 0 32.27 1.36 ; - END - END chany_bottom_out[13] - PIN chany_bottom_out[14] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 67.09 0 67.23 1.36 ; - END - END chany_bottom_out[14] - PIN chany_bottom_out[15] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 49.15 0 49.29 1.36 ; - END - END chany_bottom_out[15] - PIN chany_bottom_out[16] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 52.37 0 52.51 1.36 ; - END - END chany_bottom_out[16] - PIN chany_bottom_out[17] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 45.47 0 45.61 1.36 ; - END - END chany_bottom_out[17] - PIN chany_bottom_out[18] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 70.77 0 70.91 1.36 ; - END - END chany_bottom_out[18] - PIN chany_bottom_out[19] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 31.21 0 31.35 1.36 ; - END - END chany_bottom_out[19] - PIN chanx_left_out[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 82.81 1.38 83.11 ; - END - END chanx_left_out[0] - PIN chanx_left_out[1] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 63.77 1.38 64.07 ; - END - END chanx_left_out[1] - PIN chanx_left_out[2] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 59.01 1.38 59.31 ; - END - END chanx_left_out[2] - PIN chanx_left_out[3] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 48.13 1.38 48.43 ; - END - END chanx_left_out[3] - PIN chanx_left_out[4] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 62.41 1.38 62.71 ; - END - END chanx_left_out[4] - PIN chanx_left_out[5] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 88.25 1.38 88.55 ; - END - END chanx_left_out[5] - PIN chanx_left_out[6] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 46.77 1.38 47.07 ; - END - END chanx_left_out[6] - PIN chanx_left_out[7] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 50.85 1.38 51.15 ; - END - END chanx_left_out[7] - PIN chanx_left_out[8] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 54.93 1.38 55.23 ; - END - END chanx_left_out[8] - PIN chanx_left_out[9] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 52.21 1.38 52.51 ; - END - END chanx_left_out[9] - PIN chanx_left_out[10] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 61.05 1.38 61.35 ; - END - END chanx_left_out[10] - PIN chanx_left_out[11] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 68.53 1.38 68.83 ; - END - END chanx_left_out[11] - PIN chanx_left_out[12] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 42.69 1.38 42.99 ; - END - END chanx_left_out[12] - PIN chanx_left_out[13] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 90.97 1.38 91.27 ; - END - END chanx_left_out[13] - PIN chanx_left_out[14] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 33.17 1.38 33.47 ; - END - END chanx_left_out[14] - PIN chanx_left_out[15] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 78.73 1.38 79.03 ; - END - END chanx_left_out[15] - PIN chanx_left_out[16] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 69.89 1.38 70.19 ; - END - END chanx_left_out[16] - PIN chanx_left_out[17] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 39.97 1.38 40.27 ; - END - END chanx_left_out[17] - PIN chanx_left_out[18] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 53.57 1.38 53.87 ; - END - END chanx_left_out[18] - PIN chanx_left_out[19] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 80.09 1.38 80.39 ; - END - END chanx_left_out[19] - PIN ccff_tail[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 76.69 1.38 76.99 ; - END - END ccff_tail[0] - PIN VDD - DIRECTION INPUT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 25.76 2.48 26.24 2.96 ; - RECT 91.52 2.48 92 2.96 ; - RECT 25.76 7.92 26.24 8.4 ; - RECT 91.52 7.92 92 8.4 ; - RECT 0 13.36 0.48 13.84 ; - RECT 91.52 13.36 92 13.84 ; - RECT 0 18.8 0.48 19.28 ; - RECT 91.52 18.8 92 19.28 ; - RECT 0 24.24 0.48 24.72 ; - RECT 91.52 24.24 92 24.72 ; - RECT 0 29.68 0.48 30.16 ; - RECT 91.52 29.68 92 30.16 ; - RECT 0 35.12 0.48 35.6 ; - RECT 91.52 35.12 92 35.6 ; - RECT 0 40.56 0.48 41.04 ; - RECT 91.52 40.56 92 41.04 ; - RECT 0 46 0.48 46.48 ; - RECT 91.52 46 92 46.48 ; - RECT 0 51.44 0.48 51.92 ; - RECT 91.52 51.44 92 51.92 ; - RECT 0 56.88 0.48 57.36 ; - RECT 91.52 56.88 92 57.36 ; - RECT 0 62.32 0.48 62.8 ; - RECT 91.52 62.32 92 62.8 ; - RECT 0 67.76 0.48 68.24 ; - RECT 91.52 67.76 92 68.24 ; - RECT 0 73.2 0.48 73.68 ; - RECT 91.52 73.2 92 73.68 ; - RECT 0 78.64 0.48 79.12 ; - RECT 91.52 78.64 92 79.12 ; - RECT 0 84.08 0.48 84.56 ; - RECT 91.52 84.08 92 84.56 ; - RECT 0 89.52 0.48 90 ; - RECT 91.52 89.52 92 90 ; - RECT 0 94.96 0.48 95.44 ; - RECT 91.52 94.96 92 95.44 ; - RECT 25.76 100.4 26.24 100.88 ; - RECT 91.52 100.4 92 100.88 ; - RECT 25.76 105.84 26.24 106.32 ; - RECT 91.52 105.84 92 106.32 ; - LAYER met4 ; - RECT 36.5 0 37.1 0.6 ; - RECT 65.94 0 66.54 0.6 ; - RECT 36.5 108.2 37.1 108.8 ; - RECT 65.94 108.2 66.54 108.8 ; - LAYER met5 ; - RECT 0 22.2 3.2 25.4 ; - RECT 88.8 22.2 92 25.4 ; - RECT 0 63 3.2 66.2 ; - RECT 88.8 63 92 66.2 ; - END - END VDD - PIN VSS - DIRECTION INPUT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 25.76 0 92 0.24 ; - RECT 25.76 5.2 26.24 5.68 ; - RECT 91.52 5.2 92 5.68 ; - RECT 0 10.64 92 11.12 ; - RECT 0 16.08 0.48 16.56 ; - RECT 91.52 16.08 92 16.56 ; - RECT 0 21.52 0.48 22 ; - RECT 91.52 21.52 92 22 ; - RECT 0 26.96 0.48 27.44 ; - RECT 91.52 26.96 92 27.44 ; - RECT 0 32.4 0.48 32.88 ; - RECT 91.52 32.4 92 32.88 ; - RECT 0 37.84 0.48 38.32 ; - RECT 91.52 37.84 92 38.32 ; - RECT 0 43.28 0.48 43.76 ; - RECT 91.52 43.28 92 43.76 ; - RECT 0 48.72 0.48 49.2 ; - RECT 91.52 48.72 92 49.2 ; - RECT 0 54.16 0.48 54.64 ; - RECT 91.52 54.16 92 54.64 ; - RECT 0 59.6 0.48 60.08 ; - RECT 91.52 59.6 92 60.08 ; - RECT 0 65.04 0.48 65.52 ; - RECT 91.52 65.04 92 65.52 ; - RECT 0 70.48 0.48 70.96 ; - RECT 91.52 70.48 92 70.96 ; - RECT 0 75.92 0.48 76.4 ; - RECT 91.52 75.92 92 76.4 ; - RECT 0 81.36 0.48 81.84 ; - RECT 91.52 81.36 92 81.84 ; - RECT 0 86.8 0.48 87.28 ; - RECT 91.52 86.8 92 87.28 ; - RECT 0 92.24 0.48 92.72 ; - RECT 91.52 92.24 92 92.72 ; - RECT 0 97.68 92 98.16 ; - RECT 25.76 103.12 26.24 103.6 ; - RECT 91.52 103.12 92 103.6 ; - RECT 25.76 108.56 92 108.8 ; - LAYER met4 ; - RECT 51.22 0 51.82 0.6 ; - RECT 80.66 0 81.26 0.6 ; - RECT 10.74 10.88 11.34 11.48 ; - RECT 10.74 97.32 11.34 97.92 ; - RECT 51.22 108.2 51.82 108.8 ; - RECT 80.66 108.2 81.26 108.8 ; - LAYER met5 ; - RECT 0 42.6 3.2 45.8 ; - RECT 88.8 42.6 92 45.8 ; - RECT 0 83.4 3.2 86.6 ; - RECT 88.8 83.4 92 86.6 ; - END - END VSS - PIN Test_en__FEEDTHRU_0[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 2.23 96.56 2.37 97.92 ; - END - END Test_en__FEEDTHRU_0[0] - PIN Test_en__FEEDTHRU_1[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 2.23 10.88 2.37 12.24 ; - END - END Test_en__FEEDTHRU_1[0] - PIN clk__FEEDTHRU_0[0] - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER met2 ; - RECT 3.15 96.56 3.29 97.92 ; - END - END clk__FEEDTHRU_0[0] - PIN clk__FEEDTHRU_1[0] - DIRECTION OUTPUT ; - USE CLOCK ; - PORT - LAYER met2 ; - RECT 3.15 10.88 3.29 12.24 ; - END - END clk__FEEDTHRU_1[0] - OBS - LAYER li1 ; - RECT 25.76 108.715 92 108.885 ; - RECT 91.54 105.995 92 106.165 ; - RECT 25.76 105.995 29.44 106.165 ; - RECT 91.08 103.275 92 103.445 ; - RECT 25.76 103.275 27.6 103.445 ; - RECT 91.08 100.555 92 100.725 ; - RECT 25.76 100.555 27.6 100.725 ; - RECT 91.54 97.835 92 98.005 ; - RECT 0 97.835 27.6 98.005 ; - RECT 91.54 95.115 92 95.285 ; - RECT 0 95.115 3.68 95.285 ; - RECT 88.32 92.395 92 92.565 ; - RECT 0 92.395 1.84 92.565 ; - RECT 88.32 89.675 92 89.845 ; - RECT 0 89.675 1.84 89.845 ; - RECT 91.54 86.955 92 87.125 ; - RECT 0 86.955 1.84 87.125 ; - RECT 91.54 84.235 92 84.405 ; - RECT 0 84.235 1.84 84.405 ; - RECT 91.08 81.515 92 81.685 ; - RECT 0 81.515 1.84 81.685 ; - RECT 91.08 78.795 92 78.965 ; - RECT 0 78.795 1.84 78.965 ; - RECT 91.54 76.075 92 76.245 ; - RECT 0 76.075 3.68 76.245 ; - RECT 91.54 73.355 92 73.525 ; - RECT 0 73.355 3.68 73.525 ; - RECT 90.16 70.635 92 70.805 ; - RECT 0 70.635 3.68 70.805 ; - RECT 90.16 67.915 92 68.085 ; - RECT 0 67.915 1.84 68.085 ; - RECT 88.32 65.195 92 65.365 ; - RECT 0 65.195 3.68 65.365 ; - RECT 88.32 62.475 92 62.645 ; - RECT 0 62.475 3.68 62.645 ; - RECT 91.08 59.755 92 59.925 ; - RECT 0 59.755 1.84 59.925 ; - RECT 91.08 57.035 92 57.205 ; - RECT 0 57.035 1.84 57.205 ; - RECT 91.54 54.315 92 54.485 ; - RECT 0 54.315 1.84 54.485 ; - RECT 91.54 51.595 92 51.765 ; - RECT 0 51.595 1.84 51.765 ; - RECT 91.08 48.875 92 49.045 ; - RECT 0 48.875 1.84 49.045 ; - RECT 91.08 46.155 92 46.325 ; - RECT 0 46.155 1.84 46.325 ; - RECT 91.54 43.435 92 43.605 ; - RECT 0 43.435 1.84 43.605 ; - RECT 91.54 40.715 92 40.885 ; - RECT 0 40.715 1.84 40.885 ; - RECT 91.08 37.995 92 38.165 ; - RECT 0 37.995 3.68 38.165 ; - RECT 91.08 35.275 92 35.445 ; - RECT 0 35.275 3.68 35.445 ; - RECT 91.54 32.555 92 32.725 ; - RECT 0 32.555 1.84 32.725 ; - RECT 91.54 29.835 92 30.005 ; - RECT 0 29.835 1.84 30.005 ; - RECT 91.54 27.115 92 27.285 ; - RECT 0 27.115 3.68 27.285 ; - RECT 91.54 24.395 92 24.565 ; - RECT 0 24.395 3.68 24.565 ; - RECT 91.08 21.675 92 21.845 ; - RECT 0 21.675 3.68 21.845 ; - RECT 91.08 18.955 92 19.125 ; - RECT 0 18.955 3.68 19.125 ; - RECT 91.54 16.235 92 16.405 ; - RECT 0 16.235 1.84 16.405 ; - RECT 91.54 13.515 92 13.685 ; - RECT 0 13.515 3.68 13.685 ; - RECT 91.54 10.795 92 10.965 ; - RECT 0 10.795 29.44 10.965 ; - RECT 91.54 8.075 92 8.245 ; - RECT 25.76 8.075 27.6 8.245 ; - RECT 91.54 5.355 92 5.525 ; - RECT 25.76 5.355 27.6 5.525 ; - RECT 91.54 2.635 92 2.805 ; - RECT 25.76 2.635 29.44 2.805 ; - RECT 25.76 -0.085 92 0.085 ; - LAYER met3 ; - POLYGON 81.125 108.965 81.125 108.96 81.34 108.96 81.34 108.64 81.125 108.64 81.125 108.635 80.795 108.635 80.795 108.64 80.58 108.64 80.58 108.96 80.795 108.96 80.795 108.965 ; - POLYGON 51.685 108.965 51.685 108.96 51.9 108.96 51.9 108.64 51.685 108.64 51.685 108.635 51.355 108.635 51.355 108.64 51.14 108.64 51.14 108.96 51.355 108.96 51.355 108.965 ; - POLYGON 11.205 98.085 11.205 98.08 11.42 98.08 11.42 97.76 11.205 97.76 11.205 97.755 10.875 97.755 10.875 97.76 10.66 97.76 10.66 98.08 10.875 98.08 10.875 98.085 ; - POLYGON 1.99 88.55 1.99 87.87 8.89 87.87 8.89 87.57 1.69 87.57 1.69 87.85 1.78 87.85 1.78 88.55 ; - RECT 1.65 84.84 2.46 85.16 ; - POLYGON 2.45 82.43 2.45 82.13 0.77 82.13 0.77 82.41 1.78 82.41 1.78 82.43 ; - POLYGON 2.005 76.325 2.005 76.31 5.67 76.31 5.67 76.01 2.005 76.01 2.005 75.995 1.675 75.995 1.675 76.325 ; - POLYGON 11.205 11.045 11.205 11.04 11.42 11.04 11.42 10.72 11.205 10.72 11.205 10.715 10.875 10.715 10.875 10.72 10.66 10.72 10.66 11.04 10.875 11.04 10.875 11.045 ; - POLYGON 81.125 0.165 81.125 0.16 81.34 0.16 81.34 -0.16 81.125 -0.16 81.125 -0.165 80.795 -0.165 80.795 -0.16 80.58 -0.16 80.58 0.16 80.795 0.16 80.795 0.165 ; - POLYGON 51.685 0.165 51.685 0.16 51.9 0.16 51.9 -0.16 51.685 -0.16 51.685 -0.165 51.355 -0.165 51.355 -0.16 51.14 -0.16 51.14 0.16 51.355 0.16 51.355 0.165 ; - POLYGON 91.6 108.4 91.6 0.4 26.16 0.4 26.16 11.28 0.4 11.28 0.4 31.41 1.78 31.41 1.78 32.51 0.4 32.51 0.4 32.77 1.78 32.77 1.78 33.87 0.4 33.87 0.4 34.81 1.78 34.81 1.78 35.91 0.4 35.91 0.4 36.85 1.78 36.85 1.78 37.95 0.4 37.95 0.4 38.21 1.78 38.21 1.78 39.31 0.4 39.31 0.4 39.57 1.78 39.57 1.78 40.67 0.4 40.67 0.4 40.93 1.78 40.93 1.78 42.03 0.4 42.03 0.4 42.29 1.78 42.29 1.78 43.39 0.4 43.39 0.4 43.65 1.78 43.65 1.78 44.75 0.4 44.75 0.4 45.01 1.78 45.01 1.78 46.11 0.4 46.11 0.4 46.37 1.78 46.37 1.78 47.47 0.4 47.47 0.4 47.73 1.78 47.73 1.78 48.83 0.4 48.83 0.4 49.09 1.78 49.09 1.78 50.19 0.4 50.19 0.4 50.45 1.78 50.45 1.78 51.55 0.4 51.55 0.4 51.81 1.78 51.81 1.78 52.91 0.4 52.91 0.4 53.17 1.78 53.17 1.78 54.27 0.4 54.27 0.4 54.53 1.78 54.53 1.78 55.63 0.4 55.63 0.4 56.57 1.78 56.57 1.78 57.67 0.4 57.67 0.4 58.61 1.78 58.61 1.78 59.71 0.4 59.71 0.4 60.65 1.78 60.65 1.78 61.75 0.4 61.75 0.4 62.01 1.78 62.01 1.78 63.11 0.4 63.11 0.4 63.37 1.78 63.37 1.78 64.47 0.4 64.47 0.4 64.73 1.78 64.73 1.78 65.83 0.4 65.83 0.4 66.09 1.78 66.09 1.78 67.19 0.4 67.19 0.4 68.13 1.78 68.13 1.78 69.23 0.4 69.23 0.4 69.49 1.78 69.49 1.78 70.59 0.4 70.59 0.4 70.85 1.78 70.85 1.78 71.95 0.4 71.95 0.4 72.21 1.78 72.21 1.78 73.31 0.4 73.31 0.4 73.57 1.78 73.57 1.78 74.67 0.4 74.67 0.4 74.93 1.78 74.93 1.78 76.03 0.4 76.03 0.4 76.29 1.78 76.29 1.78 77.39 0.4 77.39 0.4 78.33 1.78 78.33 1.78 79.43 0.4 79.43 0.4 79.69 1.78 79.69 1.78 80.79 0.4 80.79 0.4 81.05 1.78 81.05 1.78 82.15 0.4 82.15 0.4 82.41 1.78 82.41 1.78 83.51 0.4 83.51 0.4 83.77 1.78 83.77 1.78 84.87 0.4 84.87 0.4 85.13 1.78 85.13 1.78 86.23 0.4 86.23 0.4 86.49 1.78 86.49 1.78 87.59 0.4 87.59 0.4 87.85 1.78 87.85 1.78 88.95 0.4 88.95 0.4 89.21 1.78 89.21 1.78 90.31 0.4 90.31 0.4 90.57 1.78 90.57 1.78 91.67 0.4 91.67 0.4 91.93 1.78 91.93 1.78 93.03 0.4 93.03 0.4 97.52 26.16 97.52 26.16 108.4 ; - LAYER met2 ; - RECT 80.82 108.615 81.1 108.985 ; - RECT 51.38 108.615 51.66 108.985 ; - RECT 64.27 106.94 64.53 107.26 ; - RECT 61.51 106.94 61.77 107.26 ; - RECT 38.05 106.94 38.31 107.26 ; - RECT 10.9 97.735 11.18 98.105 ; - RECT 10.9 10.695 11.18 11.065 ; - RECT 55.99 1.54 56.25 1.86 ; - RECT 44.95 1.54 45.21 1.86 ; - RECT 80.82 -0.185 81.1 0.185 ; - RECT 51.38 -0.185 51.66 0.185 ; - POLYGON 91.72 108.52 91.72 0.28 82.23 0.28 82.23 1.64 81.53 1.64 81.53 0.28 74.87 0.28 74.87 1.64 74.17 1.64 74.17 0.28 73.95 0.28 73.95 1.64 73.25 1.64 73.25 0.28 73.03 0.28 73.03 1.64 72.33 1.64 72.33 0.28 72.11 0.28 72.11 1.64 71.41 1.64 71.41 0.28 71.19 0.28 71.19 1.64 70.49 1.64 70.49 0.28 69.81 0.28 69.81 1.64 69.11 1.64 69.11 0.28 68.89 0.28 68.89 1.64 68.19 1.64 68.19 0.28 67.51 0.28 67.51 1.64 66.81 1.64 66.81 0.28 66.59 0.28 66.59 1.64 65.89 1.64 65.89 0.28 65.21 0.28 65.21 1.64 64.51 1.64 64.51 0.28 64.29 0.28 64.29 1.64 63.59 1.64 63.59 0.28 63.37 0.28 63.37 1.64 62.67 1.64 62.67 0.28 62.45 0.28 62.45 1.64 61.75 1.64 61.75 0.28 61.53 0.28 61.53 1.64 60.83 1.64 60.83 0.28 60.61 0.28 60.61 1.64 59.91 1.64 59.91 0.28 59.23 0.28 59.23 1.64 58.53 1.64 58.53 0.28 57.85 0.28 57.85 1.64 57.15 1.64 57.15 0.28 56.93 0.28 56.93 1.64 56.23 1.64 56.23 0.28 56.01 0.28 56.01 1.64 55.31 1.64 55.31 0.28 54.63 0.28 54.63 1.64 53.93 1.64 53.93 0.28 53.71 0.28 53.71 1.64 53.01 1.64 53.01 0.28 52.79 0.28 52.79 1.64 52.09 1.64 52.09 0.28 50.95 0.28 50.95 1.64 50.25 1.64 50.25 0.28 49.57 0.28 49.57 1.64 48.87 1.64 48.87 0.28 48.19 0.28 48.19 1.64 47.49 1.64 47.49 0.28 47.27 0.28 47.27 1.64 46.57 1.64 46.57 0.28 45.89 0.28 45.89 1.64 45.19 1.64 45.19 0.28 44.51 0.28 44.51 1.64 43.81 1.64 43.81 0.28 43.13 0.28 43.13 1.64 42.43 1.64 42.43 0.28 42.21 0.28 42.21 1.64 41.51 1.64 41.51 0.28 41.29 0.28 41.29 1.64 40.59 1.64 40.59 0.28 40.37 0.28 40.37 1.64 39.67 1.64 39.67 0.28 39.45 0.28 39.45 1.64 38.75 1.64 38.75 0.28 38.53 0.28 38.53 1.64 37.83 1.64 37.83 0.28 37.61 0.28 37.61 1.64 36.91 1.64 36.91 0.28 34.39 0.28 34.39 1.64 33.69 1.64 33.69 0.28 32.55 0.28 32.55 1.64 31.85 1.64 31.85 0.28 31.63 0.28 31.63 1.64 30.93 1.64 30.93 0.28 29.33 0.28 29.33 1.64 28.63 1.64 28.63 0.28 28.41 0.28 28.41 1.64 27.71 1.64 27.71 0.28 26.04 0.28 26.04 11.16 16.45 11.16 16.45 12.52 15.75 12.52 15.75 11.16 15.53 11.16 15.53 12.52 14.83 12.52 14.83 11.16 13.23 11.16 13.23 12.52 12.53 12.52 12.53 11.16 12.31 11.16 12.31 12.52 11.61 12.52 11.61 11.16 10.47 11.16 10.47 12.52 9.77 12.52 9.77 11.16 9.55 11.16 9.55 12.52 8.85 12.52 8.85 11.16 8.63 11.16 8.63 12.52 7.93 12.52 7.93 11.16 7.71 11.16 7.71 12.52 7.01 12.52 7.01 11.16 6.79 11.16 6.79 12.52 6.09 12.52 6.09 11.16 5.41 11.16 5.41 12.52 4.71 12.52 4.71 11.16 4.49 11.16 4.49 12.52 3.79 12.52 3.79 11.16 3.57 11.16 3.57 12.52 2.87 12.52 2.87 11.16 2.65 11.16 2.65 12.52 1.95 12.52 1.95 11.16 0.28 11.16 0.28 97.64 1.95 97.64 1.95 96.28 2.65 96.28 2.65 97.64 2.87 97.64 2.87 96.28 3.57 96.28 3.57 97.64 6.55 97.64 6.55 96.28 7.25 96.28 7.25 97.64 7.47 97.64 7.47 96.28 8.17 96.28 8.17 97.64 8.85 97.64 8.85 96.28 9.55 96.28 9.55 97.64 12.53 97.64 12.53 96.28 13.23 96.28 13.23 97.64 13.91 97.64 13.91 96.28 14.61 96.28 14.61 97.64 15.75 97.64 15.75 96.28 16.45 96.28 16.45 97.64 18.05 97.64 18.05 96.28 18.75 96.28 18.75 97.64 26.04 97.64 26.04 108.52 31.85 108.52 31.85 107.16 32.55 107.16 32.55 108.52 36.45 108.52 36.45 107.16 37.15 107.16 37.15 108.52 37.37 108.52 37.37 107.16 38.07 107.16 38.07 108.52 38.29 108.52 38.29 107.16 38.99 107.16 38.99 108.52 39.21 108.52 39.21 107.16 39.91 107.16 39.91 108.52 40.13 108.52 40.13 107.16 40.83 107.16 40.83 108.52 41.05 108.52 41.05 107.16 41.75 107.16 41.75 108.52 41.97 108.52 41.97 107.16 42.67 107.16 42.67 108.52 43.35 108.52 43.35 107.16 44.05 107.16 44.05 108.52 44.27 108.52 44.27 107.16 44.97 107.16 44.97 108.52 45.65 108.52 45.65 107.16 46.35 107.16 46.35 108.52 46.57 108.52 46.57 107.16 47.27 107.16 47.27 108.52 47.49 108.52 47.49 107.16 48.19 107.16 48.19 108.52 48.41 108.52 48.41 107.16 49.11 107.16 49.11 108.52 49.33 108.52 49.33 107.16 50.03 107.16 50.03 108.52 50.25 108.52 50.25 107.16 50.95 107.16 50.95 108.52 52.09 108.52 52.09 107.16 52.79 107.16 52.79 108.52 53.93 108.52 53.93 107.16 54.63 107.16 54.63 108.52 55.77 108.52 55.77 107.16 56.47 107.16 56.47 108.52 57.15 108.52 57.15 107.16 57.85 107.16 57.85 108.52 58.99 108.52 58.99 107.16 59.69 107.16 59.69 108.52 59.91 108.52 59.91 107.16 60.61 107.16 60.61 108.52 60.83 108.52 60.83 107.16 61.53 107.16 61.53 108.52 61.75 108.52 61.75 107.16 62.45 107.16 62.45 108.52 62.67 108.52 62.67 107.16 63.37 107.16 63.37 108.52 63.59 108.52 63.59 107.16 64.29 107.16 64.29 108.52 64.51 108.52 64.51 107.16 65.21 107.16 65.21 108.52 65.43 108.52 65.43 107.16 66.13 107.16 66.13 108.52 66.35 108.52 66.35 107.16 67.05 107.16 67.05 108.52 67.27 108.52 67.27 107.16 67.97 107.16 67.97 108.52 68.19 108.52 68.19 107.16 68.89 107.16 68.89 108.52 69.11 108.52 69.11 107.16 69.81 107.16 69.81 108.52 70.03 108.52 70.03 107.16 70.73 107.16 70.73 108.52 70.95 108.52 70.95 107.16 71.65 107.16 71.65 108.52 71.87 108.52 71.87 107.16 72.57 107.16 72.57 108.52 72.79 108.52 72.79 107.16 73.49 107.16 73.49 108.52 73.71 108.52 73.71 107.16 74.41 107.16 74.41 108.52 81.53 108.52 81.53 107.16 82.23 107.16 82.23 108.52 ; - LAYER met4 ; - POLYGON 91.6 108.4 91.6 0.4 81.66 0.4 81.66 1 80.26 1 80.26 0.4 66.94 0.4 66.94 1 65.54 1 65.54 0.4 59.43 0.4 59.43 1.76 58.33 1.76 58.33 0.4 57.59 0.4 57.59 1.76 56.49 1.76 56.49 0.4 52.22 0.4 52.22 1 50.82 1 50.82 0.4 37.5 0.4 37.5 1 36.1 1 36.1 0.4 26.16 0.4 26.16 11.28 13.43 11.28 13.43 12.64 12.33 12.64 12.33 11.28 11.74 11.28 11.74 11.88 10.34 11.88 10.34 11.28 9.75 11.28 9.75 12.64 8.65 12.64 8.65 11.28 5.15 11.28 5.15 12.64 4.05 12.64 4.05 11.28 0.4 11.28 0.4 97.52 10.34 97.52 10.34 96.92 11.74 96.92 11.74 97.52 17.85 97.52 17.85 96.16 18.95 96.16 18.95 97.52 26.16 97.52 26.16 108.4 36.1 108.4 36.1 107.8 37.5 107.8 37.5 108.4 50.82 108.4 50.82 107.8 52.22 107.8 52.22 108.4 52.81 108.4 52.81 107.04 53.91 107.04 53.91 108.4 59.25 108.4 59.25 107.04 60.35 107.04 60.35 108.4 62.93 108.4 62.93 107.04 64.03 107.04 64.03 108.4 65.54 108.4 65.54 107.8 66.94 107.8 66.94 108.4 72.13 108.4 72.13 107.04 73.23 107.04 73.23 108.4 80.26 108.4 80.26 107.8 81.66 107.8 81.66 108.4 ; - LAYER met5 ; - POLYGON 90.4 107.2 90.4 88.2 87.2 88.2 87.2 81.8 90.4 81.8 90.4 67.8 87.2 67.8 87.2 61.4 90.4 61.4 90.4 47.4 87.2 47.4 87.2 41 90.4 41 90.4 27 87.2 27 87.2 20.6 90.4 20.6 90.4 1.6 27.36 1.6 27.36 12.48 1.6 12.48 1.6 20.6 4.8 20.6 4.8 27 1.6 27 1.6 41 4.8 41 4.8 47.4 1.6 47.4 1.6 61.4 4.8 61.4 4.8 67.8 1.6 67.8 1.6 81.8 4.8 81.8 4.8 88.2 1.6 88.2 1.6 96.32 27.36 96.32 27.36 107.2 ; - LAYER met1 ; - POLYGON 91.72 108.28 91.72 106.6 91.24 106.6 91.24 105.56 91.72 105.56 91.72 103.88 91.24 103.88 91.24 102.84 91.72 102.84 91.72 101.16 91.24 101.16 91.24 100.12 91.72 100.12 91.72 98.44 26.04 98.44 26.04 100.12 26.52 100.12 26.52 101.16 26.04 101.16 26.04 102.84 26.52 102.84 26.52 103.88 26.04 103.88 26.04 105.56 26.52 105.56 26.52 106.6 26.04 106.6 26.04 108.28 ; - POLYGON 91.72 97.4 91.72 95.72 91.24 95.72 91.24 94.68 91.72 94.68 91.72 93 91.24 93 91.24 91.96 91.72 91.96 91.72 90.28 91.24 90.28 91.24 89.24 91.72 89.24 91.72 87.56 91.24 87.56 91.24 86.52 91.72 86.52 91.72 84.84 91.24 84.84 91.24 83.8 91.72 83.8 91.72 82.12 91.24 82.12 91.24 81.08 91.72 81.08 91.72 79.4 91.24 79.4 91.24 78.36 91.72 78.36 91.72 76.68 91.24 76.68 91.24 75.64 91.72 75.64 91.72 73.96 91.24 73.96 91.24 72.92 91.72 72.92 91.72 71.24 91.24 71.24 91.24 70.2 91.72 70.2 91.72 68.52 91.24 68.52 91.24 67.48 91.72 67.48 91.72 65.8 91.24 65.8 91.24 64.76 91.72 64.76 91.72 63.08 91.24 63.08 91.24 62.04 91.72 62.04 91.72 60.36 91.24 60.36 91.24 59.32 91.72 59.32 91.72 57.64 91.24 57.64 91.24 56.6 91.72 56.6 91.72 54.92 91.24 54.92 91.24 53.88 91.72 53.88 91.72 52.2 91.24 52.2 91.24 51.16 91.72 51.16 91.72 49.48 91.24 49.48 91.24 48.44 91.72 48.44 91.72 46.76 91.24 46.76 91.24 45.72 91.72 45.72 91.72 44.04 91.24 44.04 91.24 43 91.72 43 91.72 41.32 91.24 41.32 91.24 40.28 91.72 40.28 91.72 38.6 91.24 38.6 91.24 37.56 91.72 37.56 91.72 35.88 91.24 35.88 91.24 34.84 91.72 34.84 91.72 33.16 91.24 33.16 91.24 32.12 91.72 32.12 91.72 30.44 91.24 30.44 91.24 29.4 91.72 29.4 91.72 27.72 91.24 27.72 91.24 26.68 91.72 26.68 91.72 25 91.24 25 91.24 23.96 91.72 23.96 91.72 22.28 91.24 22.28 91.24 21.24 91.72 21.24 91.72 19.56 91.24 19.56 91.24 18.52 91.72 18.52 91.72 16.84 91.24 16.84 91.24 15.8 91.72 15.8 91.72 14.12 91.24 14.12 91.24 13.08 91.72 13.08 91.72 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 0.76 81.08 0.76 82.12 0.28 82.12 0.28 83.8 0.76 83.8 0.76 84.84 0.28 84.84 0.28 86.52 0.76 86.52 0.76 87.56 0.28 87.56 0.28 89.24 0.76 89.24 0.76 90.28 0.28 90.28 0.28 91.96 0.76 91.96 0.76 93 0.28 93 0.28 94.68 0.76 94.68 0.76 95.72 0.28 95.72 0.28 97.4 ; - POLYGON 91.72 10.36 91.72 8.68 91.24 8.68 91.24 7.64 91.72 7.64 91.72 5.96 91.24 5.96 91.24 4.92 91.72 4.92 91.72 3.24 91.24 3.24 91.24 2.2 91.72 2.2 91.72 0.52 26.04 0.52 26.04 2.2 26.52 2.2 26.52 3.24 26.04 3.24 26.04 4.92 26.52 4.92 26.52 5.96 26.04 5.96 26.04 7.64 26.52 7.64 26.52 8.68 26.04 8.68 26.04 10.36 ; - LAYER li1 ; - POLYGON 91.83 108.63 91.83 0.17 25.93 0.17 25.93 11.05 0.17 11.05 0.17 97.75 25.93 97.75 25.93 108.63 ; - LAYER mcon ; - RECT 91.685 108.715 91.855 108.885 ; - RECT 91.225 108.715 91.395 108.885 ; - RECT 90.765 108.715 90.935 108.885 ; - RECT 90.305 108.715 90.475 108.885 ; - RECT 89.845 108.715 90.015 108.885 ; - RECT 89.385 108.715 89.555 108.885 ; - RECT 88.925 108.715 89.095 108.885 ; - RECT 88.465 108.715 88.635 108.885 ; - RECT 88.005 108.715 88.175 108.885 ; - RECT 87.545 108.715 87.715 108.885 ; - RECT 87.085 108.715 87.255 108.885 ; - RECT 86.625 108.715 86.795 108.885 ; - RECT 86.165 108.715 86.335 108.885 ; - RECT 85.705 108.715 85.875 108.885 ; - RECT 85.245 108.715 85.415 108.885 ; - RECT 84.785 108.715 84.955 108.885 ; - RECT 84.325 108.715 84.495 108.885 ; - RECT 83.865 108.715 84.035 108.885 ; - RECT 83.405 108.715 83.575 108.885 ; - RECT 82.945 108.715 83.115 108.885 ; - RECT 82.485 108.715 82.655 108.885 ; - RECT 82.025 108.715 82.195 108.885 ; - RECT 81.565 108.715 81.735 108.885 ; - RECT 81.105 108.715 81.275 108.885 ; - RECT 80.645 108.715 80.815 108.885 ; - RECT 80.185 108.715 80.355 108.885 ; - RECT 79.725 108.715 79.895 108.885 ; - RECT 79.265 108.715 79.435 108.885 ; - RECT 78.805 108.715 78.975 108.885 ; - RECT 78.345 108.715 78.515 108.885 ; - RECT 77.885 108.715 78.055 108.885 ; - RECT 77.425 108.715 77.595 108.885 ; - RECT 76.965 108.715 77.135 108.885 ; - RECT 76.505 108.715 76.675 108.885 ; - RECT 76.045 108.715 76.215 108.885 ; - RECT 75.585 108.715 75.755 108.885 ; - RECT 75.125 108.715 75.295 108.885 ; - RECT 74.665 108.715 74.835 108.885 ; - RECT 74.205 108.715 74.375 108.885 ; - RECT 73.745 108.715 73.915 108.885 ; - RECT 73.285 108.715 73.455 108.885 ; - RECT 72.825 108.715 72.995 108.885 ; - RECT 72.365 108.715 72.535 108.885 ; - RECT 71.905 108.715 72.075 108.885 ; - RECT 71.445 108.715 71.615 108.885 ; - RECT 70.985 108.715 71.155 108.885 ; - RECT 70.525 108.715 70.695 108.885 ; - RECT 70.065 108.715 70.235 108.885 ; - RECT 69.605 108.715 69.775 108.885 ; - RECT 69.145 108.715 69.315 108.885 ; - RECT 68.685 108.715 68.855 108.885 ; - RECT 68.225 108.715 68.395 108.885 ; - RECT 67.765 108.715 67.935 108.885 ; - RECT 67.305 108.715 67.475 108.885 ; - RECT 66.845 108.715 67.015 108.885 ; - RECT 66.385 108.715 66.555 108.885 ; - RECT 65.925 108.715 66.095 108.885 ; - RECT 65.465 108.715 65.635 108.885 ; - RECT 65.005 108.715 65.175 108.885 ; - RECT 64.545 108.715 64.715 108.885 ; - RECT 64.085 108.715 64.255 108.885 ; - RECT 63.625 108.715 63.795 108.885 ; - RECT 63.165 108.715 63.335 108.885 ; - RECT 62.705 108.715 62.875 108.885 ; - RECT 62.245 108.715 62.415 108.885 ; - RECT 61.785 108.715 61.955 108.885 ; - RECT 61.325 108.715 61.495 108.885 ; - RECT 60.865 108.715 61.035 108.885 ; - RECT 60.405 108.715 60.575 108.885 ; - RECT 59.945 108.715 60.115 108.885 ; - RECT 59.485 108.715 59.655 108.885 ; - RECT 59.025 108.715 59.195 108.885 ; - RECT 58.565 108.715 58.735 108.885 ; - RECT 58.105 108.715 58.275 108.885 ; - RECT 57.645 108.715 57.815 108.885 ; - RECT 57.185 108.715 57.355 108.885 ; - RECT 56.725 108.715 56.895 108.885 ; - RECT 56.265 108.715 56.435 108.885 ; - RECT 55.805 108.715 55.975 108.885 ; - RECT 55.345 108.715 55.515 108.885 ; - RECT 54.885 108.715 55.055 108.885 ; - RECT 54.425 108.715 54.595 108.885 ; - RECT 53.965 108.715 54.135 108.885 ; - RECT 53.505 108.715 53.675 108.885 ; - RECT 53.045 108.715 53.215 108.885 ; - RECT 52.585 108.715 52.755 108.885 ; - RECT 52.125 108.715 52.295 108.885 ; - RECT 51.665 108.715 51.835 108.885 ; - RECT 51.205 108.715 51.375 108.885 ; - RECT 50.745 108.715 50.915 108.885 ; - RECT 50.285 108.715 50.455 108.885 ; - RECT 49.825 108.715 49.995 108.885 ; - RECT 49.365 108.715 49.535 108.885 ; - RECT 48.905 108.715 49.075 108.885 ; - RECT 48.445 108.715 48.615 108.885 ; - RECT 47.985 108.715 48.155 108.885 ; - RECT 47.525 108.715 47.695 108.885 ; - RECT 47.065 108.715 47.235 108.885 ; - RECT 46.605 108.715 46.775 108.885 ; - RECT 46.145 108.715 46.315 108.885 ; - RECT 45.685 108.715 45.855 108.885 ; - RECT 45.225 108.715 45.395 108.885 ; - RECT 44.765 108.715 44.935 108.885 ; - RECT 44.305 108.715 44.475 108.885 ; - RECT 43.845 108.715 44.015 108.885 ; - RECT 43.385 108.715 43.555 108.885 ; - RECT 42.925 108.715 43.095 108.885 ; - RECT 42.465 108.715 42.635 108.885 ; - RECT 42.005 108.715 42.175 108.885 ; - RECT 41.545 108.715 41.715 108.885 ; - RECT 41.085 108.715 41.255 108.885 ; - RECT 40.625 108.715 40.795 108.885 ; - RECT 40.165 108.715 40.335 108.885 ; - RECT 39.705 108.715 39.875 108.885 ; - RECT 39.245 108.715 39.415 108.885 ; - RECT 38.785 108.715 38.955 108.885 ; - RECT 38.325 108.715 38.495 108.885 ; - RECT 37.865 108.715 38.035 108.885 ; - RECT 37.405 108.715 37.575 108.885 ; - RECT 36.945 108.715 37.115 108.885 ; - RECT 36.485 108.715 36.655 108.885 ; - RECT 36.025 108.715 36.195 108.885 ; - RECT 35.565 108.715 35.735 108.885 ; - RECT 35.105 108.715 35.275 108.885 ; - RECT 34.645 108.715 34.815 108.885 ; - RECT 34.185 108.715 34.355 108.885 ; - RECT 33.725 108.715 33.895 108.885 ; - RECT 33.265 108.715 33.435 108.885 ; - RECT 32.805 108.715 32.975 108.885 ; - RECT 32.345 108.715 32.515 108.885 ; - RECT 31.885 108.715 32.055 108.885 ; - RECT 31.425 108.715 31.595 108.885 ; - RECT 30.965 108.715 31.135 108.885 ; - RECT 30.505 108.715 30.675 108.885 ; - RECT 30.045 108.715 30.215 108.885 ; - RECT 29.585 108.715 29.755 108.885 ; - RECT 29.125 108.715 29.295 108.885 ; - RECT 28.665 108.715 28.835 108.885 ; - RECT 28.205 108.715 28.375 108.885 ; - RECT 27.745 108.715 27.915 108.885 ; - RECT 27.285 108.715 27.455 108.885 ; - RECT 26.825 108.715 26.995 108.885 ; - RECT 26.365 108.715 26.535 108.885 ; - RECT 25.905 108.715 26.075 108.885 ; - RECT 91.685 105.995 91.855 106.165 ; - RECT 91.225 105.995 91.395 106.165 ; - RECT 26.365 105.995 26.535 106.165 ; - RECT 25.905 105.995 26.075 106.165 ; - RECT 91.685 103.275 91.855 103.445 ; - RECT 91.225 103.275 91.395 103.445 ; - RECT 26.365 103.275 26.535 103.445 ; - RECT 25.905 103.275 26.075 103.445 ; - RECT 91.685 100.555 91.855 100.725 ; - RECT 91.225 100.555 91.395 100.725 ; - RECT 26.365 100.555 26.535 100.725 ; - RECT 25.905 100.555 26.075 100.725 ; - RECT 91.685 97.835 91.855 98.005 ; - RECT 91.225 97.835 91.395 98.005 ; - RECT 90.765 97.835 90.935 98.005 ; - RECT 90.305 97.835 90.475 98.005 ; - RECT 89.845 97.835 90.015 98.005 ; - RECT 89.385 97.835 89.555 98.005 ; - RECT 88.925 97.835 89.095 98.005 ; - RECT 88.465 97.835 88.635 98.005 ; - RECT 88.005 97.835 88.175 98.005 ; - RECT 87.545 97.835 87.715 98.005 ; - RECT 87.085 97.835 87.255 98.005 ; - RECT 86.625 97.835 86.795 98.005 ; - RECT 86.165 97.835 86.335 98.005 ; - RECT 85.705 97.835 85.875 98.005 ; - RECT 85.245 97.835 85.415 98.005 ; - RECT 84.785 97.835 84.955 98.005 ; - RECT 84.325 97.835 84.495 98.005 ; - RECT 83.865 97.835 84.035 98.005 ; - RECT 83.405 97.835 83.575 98.005 ; - RECT 82.945 97.835 83.115 98.005 ; - RECT 82.485 97.835 82.655 98.005 ; - RECT 82.025 97.835 82.195 98.005 ; - RECT 81.565 97.835 81.735 98.005 ; - RECT 81.105 97.835 81.275 98.005 ; - RECT 80.645 97.835 80.815 98.005 ; - RECT 80.185 97.835 80.355 98.005 ; - RECT 79.725 97.835 79.895 98.005 ; - RECT 79.265 97.835 79.435 98.005 ; - RECT 78.805 97.835 78.975 98.005 ; - RECT 78.345 97.835 78.515 98.005 ; - RECT 77.885 97.835 78.055 98.005 ; - RECT 77.425 97.835 77.595 98.005 ; - RECT 76.965 97.835 77.135 98.005 ; - RECT 76.505 97.835 76.675 98.005 ; - RECT 76.045 97.835 76.215 98.005 ; - RECT 75.585 97.835 75.755 98.005 ; - RECT 75.125 97.835 75.295 98.005 ; - RECT 74.665 97.835 74.835 98.005 ; - RECT 74.205 97.835 74.375 98.005 ; - RECT 73.745 97.835 73.915 98.005 ; - RECT 73.285 97.835 73.455 98.005 ; - RECT 72.825 97.835 72.995 98.005 ; - RECT 72.365 97.835 72.535 98.005 ; - RECT 71.905 97.835 72.075 98.005 ; - RECT 71.445 97.835 71.615 98.005 ; - RECT 70.985 97.835 71.155 98.005 ; - RECT 70.525 97.835 70.695 98.005 ; - RECT 70.065 97.835 70.235 98.005 ; - RECT 69.605 97.835 69.775 98.005 ; - RECT 69.145 97.835 69.315 98.005 ; - RECT 68.685 97.835 68.855 98.005 ; - RECT 68.225 97.835 68.395 98.005 ; - RECT 67.765 97.835 67.935 98.005 ; - RECT 67.305 97.835 67.475 98.005 ; - RECT 66.845 97.835 67.015 98.005 ; - RECT 66.385 97.835 66.555 98.005 ; - RECT 65.925 97.835 66.095 98.005 ; - RECT 65.465 97.835 65.635 98.005 ; - RECT 65.005 97.835 65.175 98.005 ; - RECT 64.545 97.835 64.715 98.005 ; - RECT 64.085 97.835 64.255 98.005 ; - RECT 63.625 97.835 63.795 98.005 ; - RECT 63.165 97.835 63.335 98.005 ; - RECT 62.705 97.835 62.875 98.005 ; - RECT 62.245 97.835 62.415 98.005 ; - RECT 61.785 97.835 61.955 98.005 ; - RECT 61.325 97.835 61.495 98.005 ; - RECT 60.865 97.835 61.035 98.005 ; - RECT 60.405 97.835 60.575 98.005 ; - RECT 59.945 97.835 60.115 98.005 ; - RECT 59.485 97.835 59.655 98.005 ; - RECT 59.025 97.835 59.195 98.005 ; - RECT 58.565 97.835 58.735 98.005 ; - RECT 58.105 97.835 58.275 98.005 ; - RECT 57.645 97.835 57.815 98.005 ; - RECT 57.185 97.835 57.355 98.005 ; - RECT 56.725 97.835 56.895 98.005 ; - RECT 56.265 97.835 56.435 98.005 ; - RECT 55.805 97.835 55.975 98.005 ; - RECT 55.345 97.835 55.515 98.005 ; - RECT 54.885 97.835 55.055 98.005 ; - RECT 54.425 97.835 54.595 98.005 ; - RECT 53.965 97.835 54.135 98.005 ; - RECT 53.505 97.835 53.675 98.005 ; - RECT 53.045 97.835 53.215 98.005 ; - RECT 52.585 97.835 52.755 98.005 ; - RECT 52.125 97.835 52.295 98.005 ; - RECT 51.665 97.835 51.835 98.005 ; - RECT 51.205 97.835 51.375 98.005 ; - RECT 50.745 97.835 50.915 98.005 ; - RECT 50.285 97.835 50.455 98.005 ; - RECT 49.825 97.835 49.995 98.005 ; - RECT 49.365 97.835 49.535 98.005 ; - RECT 48.905 97.835 49.075 98.005 ; - RECT 48.445 97.835 48.615 98.005 ; - RECT 47.985 97.835 48.155 98.005 ; - RECT 47.525 97.835 47.695 98.005 ; - RECT 47.065 97.835 47.235 98.005 ; - RECT 46.605 97.835 46.775 98.005 ; - RECT 46.145 97.835 46.315 98.005 ; - RECT 45.685 97.835 45.855 98.005 ; - RECT 45.225 97.835 45.395 98.005 ; - RECT 44.765 97.835 44.935 98.005 ; - RECT 44.305 97.835 44.475 98.005 ; - RECT 43.845 97.835 44.015 98.005 ; - RECT 43.385 97.835 43.555 98.005 ; - RECT 42.925 97.835 43.095 98.005 ; - RECT 42.465 97.835 42.635 98.005 ; - RECT 42.005 97.835 42.175 98.005 ; - RECT 41.545 97.835 41.715 98.005 ; - RECT 41.085 97.835 41.255 98.005 ; - RECT 40.625 97.835 40.795 98.005 ; - RECT 40.165 97.835 40.335 98.005 ; - RECT 39.705 97.835 39.875 98.005 ; - RECT 39.245 97.835 39.415 98.005 ; - RECT 38.785 97.835 38.955 98.005 ; - RECT 38.325 97.835 38.495 98.005 ; - RECT 37.865 97.835 38.035 98.005 ; - RECT 37.405 97.835 37.575 98.005 ; - RECT 36.945 97.835 37.115 98.005 ; - RECT 36.485 97.835 36.655 98.005 ; - RECT 36.025 97.835 36.195 98.005 ; - RECT 35.565 97.835 35.735 98.005 ; - RECT 35.105 97.835 35.275 98.005 ; - RECT 34.645 97.835 34.815 98.005 ; - RECT 34.185 97.835 34.355 98.005 ; - RECT 33.725 97.835 33.895 98.005 ; - RECT 33.265 97.835 33.435 98.005 ; - RECT 32.805 97.835 32.975 98.005 ; - RECT 32.345 97.835 32.515 98.005 ; - RECT 31.885 97.835 32.055 98.005 ; - RECT 31.425 97.835 31.595 98.005 ; - RECT 30.965 97.835 31.135 98.005 ; - RECT 30.505 97.835 30.675 98.005 ; - RECT 30.045 97.835 30.215 98.005 ; - RECT 29.585 97.835 29.755 98.005 ; - RECT 29.125 97.835 29.295 98.005 ; - RECT 28.665 97.835 28.835 98.005 ; - RECT 28.205 97.835 28.375 98.005 ; - RECT 27.745 97.835 27.915 98.005 ; - RECT 27.285 97.835 27.455 98.005 ; - RECT 26.825 97.835 26.995 98.005 ; - RECT 26.365 97.835 26.535 98.005 ; - RECT 25.905 97.835 26.075 98.005 ; - RECT 25.445 97.835 25.615 98.005 ; - RECT 24.985 97.835 25.155 98.005 ; - RECT 24.525 97.835 24.695 98.005 ; - RECT 24.065 97.835 24.235 98.005 ; - RECT 23.605 97.835 23.775 98.005 ; - RECT 23.145 97.835 23.315 98.005 ; - RECT 22.685 97.835 22.855 98.005 ; - RECT 22.225 97.835 22.395 98.005 ; - RECT 21.765 97.835 21.935 98.005 ; - RECT 21.305 97.835 21.475 98.005 ; - RECT 20.845 97.835 21.015 98.005 ; - RECT 20.385 97.835 20.555 98.005 ; - RECT 19.925 97.835 20.095 98.005 ; - RECT 19.465 97.835 19.635 98.005 ; - RECT 19.005 97.835 19.175 98.005 ; - RECT 18.545 97.835 18.715 98.005 ; - RECT 18.085 97.835 18.255 98.005 ; - RECT 17.625 97.835 17.795 98.005 ; - RECT 17.165 97.835 17.335 98.005 ; - RECT 16.705 97.835 16.875 98.005 ; - RECT 16.245 97.835 16.415 98.005 ; - RECT 15.785 97.835 15.955 98.005 ; - RECT 15.325 97.835 15.495 98.005 ; - RECT 14.865 97.835 15.035 98.005 ; - RECT 14.405 97.835 14.575 98.005 ; - RECT 13.945 97.835 14.115 98.005 ; - RECT 13.485 97.835 13.655 98.005 ; - RECT 13.025 97.835 13.195 98.005 ; - RECT 12.565 97.835 12.735 98.005 ; - RECT 12.105 97.835 12.275 98.005 ; - RECT 11.645 97.835 11.815 98.005 ; - RECT 11.185 97.835 11.355 98.005 ; - RECT 10.725 97.835 10.895 98.005 ; - RECT 10.265 97.835 10.435 98.005 ; - RECT 9.805 97.835 9.975 98.005 ; - RECT 9.345 97.835 9.515 98.005 ; - RECT 8.885 97.835 9.055 98.005 ; - RECT 8.425 97.835 8.595 98.005 ; - RECT 7.965 97.835 8.135 98.005 ; - RECT 7.505 97.835 7.675 98.005 ; - RECT 7.045 97.835 7.215 98.005 ; - RECT 6.585 97.835 6.755 98.005 ; - RECT 6.125 97.835 6.295 98.005 ; - RECT 5.665 97.835 5.835 98.005 ; - RECT 5.205 97.835 5.375 98.005 ; - RECT 4.745 97.835 4.915 98.005 ; - RECT 4.285 97.835 4.455 98.005 ; - RECT 3.825 97.835 3.995 98.005 ; - RECT 3.365 97.835 3.535 98.005 ; - RECT 2.905 97.835 3.075 98.005 ; - RECT 2.445 97.835 2.615 98.005 ; - RECT 1.985 97.835 2.155 98.005 ; - RECT 1.525 97.835 1.695 98.005 ; - RECT 1.065 97.835 1.235 98.005 ; - RECT 0.605 97.835 0.775 98.005 ; - RECT 0.145 97.835 0.315 98.005 ; - RECT 91.685 95.115 91.855 95.285 ; - RECT 91.225 95.115 91.395 95.285 ; - RECT 0.605 95.115 0.775 95.285 ; - RECT 0.145 95.115 0.315 95.285 ; - RECT 91.685 92.395 91.855 92.565 ; - RECT 91.225 92.395 91.395 92.565 ; - RECT 0.605 92.395 0.775 92.565 ; - RECT 0.145 92.395 0.315 92.565 ; - RECT 91.685 89.675 91.855 89.845 ; - RECT 91.225 89.675 91.395 89.845 ; - RECT 0.605 89.675 0.775 89.845 ; - RECT 0.145 89.675 0.315 89.845 ; - RECT 91.685 86.955 91.855 87.125 ; - RECT 91.225 86.955 91.395 87.125 ; - RECT 0.605 86.955 0.775 87.125 ; - RECT 0.145 86.955 0.315 87.125 ; - RECT 91.685 84.235 91.855 84.405 ; - RECT 91.225 84.235 91.395 84.405 ; - RECT 0.605 84.235 0.775 84.405 ; - RECT 0.145 84.235 0.315 84.405 ; - RECT 91.685 81.515 91.855 81.685 ; - RECT 91.225 81.515 91.395 81.685 ; - RECT 0.605 81.515 0.775 81.685 ; - RECT 0.145 81.515 0.315 81.685 ; - RECT 91.685 78.795 91.855 78.965 ; - RECT 91.225 78.795 91.395 78.965 ; - RECT 0.605 78.795 0.775 78.965 ; - RECT 0.145 78.795 0.315 78.965 ; - RECT 91.685 76.075 91.855 76.245 ; - RECT 91.225 76.075 91.395 76.245 ; - RECT 0.605 76.075 0.775 76.245 ; - RECT 0.145 76.075 0.315 76.245 ; - RECT 91.685 73.355 91.855 73.525 ; - RECT 91.225 73.355 91.395 73.525 ; - RECT 0.605 73.355 0.775 73.525 ; - RECT 0.145 73.355 0.315 73.525 ; - RECT 91.685 70.635 91.855 70.805 ; - RECT 91.225 70.635 91.395 70.805 ; - RECT 0.605 70.635 0.775 70.805 ; - RECT 0.145 70.635 0.315 70.805 ; - RECT 91.685 67.915 91.855 68.085 ; - RECT 91.225 67.915 91.395 68.085 ; - RECT 0.605 67.915 0.775 68.085 ; - RECT 0.145 67.915 0.315 68.085 ; - RECT 91.685 65.195 91.855 65.365 ; - RECT 91.225 65.195 91.395 65.365 ; - RECT 0.605 65.195 0.775 65.365 ; - RECT 0.145 65.195 0.315 65.365 ; - RECT 91.685 62.475 91.855 62.645 ; - RECT 91.225 62.475 91.395 62.645 ; - RECT 0.605 62.475 0.775 62.645 ; - RECT 0.145 62.475 0.315 62.645 ; - RECT 91.685 59.755 91.855 59.925 ; - RECT 91.225 59.755 91.395 59.925 ; - RECT 0.605 59.755 0.775 59.925 ; - RECT 0.145 59.755 0.315 59.925 ; - RECT 91.685 57.035 91.855 57.205 ; - RECT 91.225 57.035 91.395 57.205 ; - RECT 0.605 57.035 0.775 57.205 ; - RECT 0.145 57.035 0.315 57.205 ; - RECT 91.685 54.315 91.855 54.485 ; - RECT 91.225 54.315 91.395 54.485 ; - RECT 0.605 54.315 0.775 54.485 ; - RECT 0.145 54.315 0.315 54.485 ; - RECT 91.685 51.595 91.855 51.765 ; - RECT 91.225 51.595 91.395 51.765 ; - RECT 0.605 51.595 0.775 51.765 ; - RECT 0.145 51.595 0.315 51.765 ; - RECT 91.685 48.875 91.855 49.045 ; - RECT 91.225 48.875 91.395 49.045 ; - RECT 0.605 48.875 0.775 49.045 ; - RECT 0.145 48.875 0.315 49.045 ; - RECT 91.685 46.155 91.855 46.325 ; - RECT 91.225 46.155 91.395 46.325 ; - RECT 0.605 46.155 0.775 46.325 ; - RECT 0.145 46.155 0.315 46.325 ; - RECT 91.685 43.435 91.855 43.605 ; - RECT 91.225 43.435 91.395 43.605 ; - RECT 0.605 43.435 0.775 43.605 ; - RECT 0.145 43.435 0.315 43.605 ; - RECT 91.685 40.715 91.855 40.885 ; - RECT 91.225 40.715 91.395 40.885 ; - RECT 0.605 40.715 0.775 40.885 ; - RECT 0.145 40.715 0.315 40.885 ; - RECT 91.685 37.995 91.855 38.165 ; - RECT 91.225 37.995 91.395 38.165 ; - RECT 0.605 37.995 0.775 38.165 ; - RECT 0.145 37.995 0.315 38.165 ; - RECT 91.685 35.275 91.855 35.445 ; - RECT 91.225 35.275 91.395 35.445 ; - RECT 0.605 35.275 0.775 35.445 ; - RECT 0.145 35.275 0.315 35.445 ; - RECT 91.685 32.555 91.855 32.725 ; - RECT 91.225 32.555 91.395 32.725 ; - RECT 0.605 32.555 0.775 32.725 ; - RECT 0.145 32.555 0.315 32.725 ; - RECT 91.685 29.835 91.855 30.005 ; - RECT 91.225 29.835 91.395 30.005 ; - RECT 0.605 29.835 0.775 30.005 ; - RECT 0.145 29.835 0.315 30.005 ; - RECT 91.685 27.115 91.855 27.285 ; - RECT 91.225 27.115 91.395 27.285 ; - RECT 0.605 27.115 0.775 27.285 ; - RECT 0.145 27.115 0.315 27.285 ; - RECT 91.685 24.395 91.855 24.565 ; - RECT 91.225 24.395 91.395 24.565 ; - RECT 0.605 24.395 0.775 24.565 ; - RECT 0.145 24.395 0.315 24.565 ; - RECT 91.685 21.675 91.855 21.845 ; - RECT 91.225 21.675 91.395 21.845 ; - RECT 0.605 21.675 0.775 21.845 ; - RECT 0.145 21.675 0.315 21.845 ; - RECT 91.685 18.955 91.855 19.125 ; - RECT 91.225 18.955 91.395 19.125 ; - RECT 0.605 18.955 0.775 19.125 ; - RECT 0.145 18.955 0.315 19.125 ; - RECT 91.685 16.235 91.855 16.405 ; - RECT 91.225 16.235 91.395 16.405 ; - RECT 0.605 16.235 0.775 16.405 ; - RECT 0.145 16.235 0.315 16.405 ; - RECT 91.685 13.515 91.855 13.685 ; - RECT 91.225 13.515 91.395 13.685 ; - RECT 0.605 13.515 0.775 13.685 ; - RECT 0.145 13.515 0.315 13.685 ; - RECT 91.685 10.795 91.855 10.965 ; - RECT 91.225 10.795 91.395 10.965 ; - RECT 90.765 10.795 90.935 10.965 ; - RECT 90.305 10.795 90.475 10.965 ; - RECT 89.845 10.795 90.015 10.965 ; - RECT 89.385 10.795 89.555 10.965 ; - RECT 88.925 10.795 89.095 10.965 ; - RECT 88.465 10.795 88.635 10.965 ; - RECT 88.005 10.795 88.175 10.965 ; - RECT 87.545 10.795 87.715 10.965 ; - RECT 87.085 10.795 87.255 10.965 ; - RECT 86.625 10.795 86.795 10.965 ; - RECT 86.165 10.795 86.335 10.965 ; - RECT 85.705 10.795 85.875 10.965 ; - RECT 85.245 10.795 85.415 10.965 ; - RECT 84.785 10.795 84.955 10.965 ; - RECT 84.325 10.795 84.495 10.965 ; - RECT 83.865 10.795 84.035 10.965 ; - RECT 83.405 10.795 83.575 10.965 ; - RECT 82.945 10.795 83.115 10.965 ; - RECT 82.485 10.795 82.655 10.965 ; - RECT 82.025 10.795 82.195 10.965 ; - RECT 81.565 10.795 81.735 10.965 ; - RECT 81.105 10.795 81.275 10.965 ; - RECT 80.645 10.795 80.815 10.965 ; - RECT 80.185 10.795 80.355 10.965 ; - RECT 79.725 10.795 79.895 10.965 ; - RECT 79.265 10.795 79.435 10.965 ; - RECT 78.805 10.795 78.975 10.965 ; - RECT 78.345 10.795 78.515 10.965 ; - RECT 77.885 10.795 78.055 10.965 ; - RECT 77.425 10.795 77.595 10.965 ; - RECT 76.965 10.795 77.135 10.965 ; - RECT 76.505 10.795 76.675 10.965 ; - RECT 76.045 10.795 76.215 10.965 ; - RECT 75.585 10.795 75.755 10.965 ; - RECT 75.125 10.795 75.295 10.965 ; - RECT 74.665 10.795 74.835 10.965 ; - RECT 74.205 10.795 74.375 10.965 ; - RECT 73.745 10.795 73.915 10.965 ; - RECT 73.285 10.795 73.455 10.965 ; - RECT 72.825 10.795 72.995 10.965 ; - RECT 72.365 10.795 72.535 10.965 ; - RECT 71.905 10.795 72.075 10.965 ; - RECT 71.445 10.795 71.615 10.965 ; - RECT 70.985 10.795 71.155 10.965 ; - RECT 70.525 10.795 70.695 10.965 ; - RECT 70.065 10.795 70.235 10.965 ; - RECT 69.605 10.795 69.775 10.965 ; - RECT 69.145 10.795 69.315 10.965 ; - RECT 68.685 10.795 68.855 10.965 ; - RECT 68.225 10.795 68.395 10.965 ; - RECT 67.765 10.795 67.935 10.965 ; - RECT 67.305 10.795 67.475 10.965 ; - RECT 66.845 10.795 67.015 10.965 ; - RECT 66.385 10.795 66.555 10.965 ; - RECT 65.925 10.795 66.095 10.965 ; - RECT 65.465 10.795 65.635 10.965 ; - RECT 65.005 10.795 65.175 10.965 ; - RECT 64.545 10.795 64.715 10.965 ; - RECT 64.085 10.795 64.255 10.965 ; - RECT 63.625 10.795 63.795 10.965 ; - RECT 63.165 10.795 63.335 10.965 ; - RECT 62.705 10.795 62.875 10.965 ; - RECT 62.245 10.795 62.415 10.965 ; - RECT 61.785 10.795 61.955 10.965 ; - RECT 61.325 10.795 61.495 10.965 ; - RECT 60.865 10.795 61.035 10.965 ; - RECT 60.405 10.795 60.575 10.965 ; - RECT 59.945 10.795 60.115 10.965 ; - RECT 59.485 10.795 59.655 10.965 ; - RECT 59.025 10.795 59.195 10.965 ; - RECT 58.565 10.795 58.735 10.965 ; - RECT 58.105 10.795 58.275 10.965 ; - RECT 57.645 10.795 57.815 10.965 ; - RECT 57.185 10.795 57.355 10.965 ; - RECT 56.725 10.795 56.895 10.965 ; - RECT 56.265 10.795 56.435 10.965 ; - RECT 55.805 10.795 55.975 10.965 ; - RECT 55.345 10.795 55.515 10.965 ; - RECT 54.885 10.795 55.055 10.965 ; - RECT 54.425 10.795 54.595 10.965 ; - RECT 53.965 10.795 54.135 10.965 ; - RECT 53.505 10.795 53.675 10.965 ; - RECT 53.045 10.795 53.215 10.965 ; - RECT 52.585 10.795 52.755 10.965 ; - RECT 52.125 10.795 52.295 10.965 ; - RECT 51.665 10.795 51.835 10.965 ; - RECT 51.205 10.795 51.375 10.965 ; - RECT 50.745 10.795 50.915 10.965 ; - RECT 50.285 10.795 50.455 10.965 ; - RECT 49.825 10.795 49.995 10.965 ; - RECT 49.365 10.795 49.535 10.965 ; - RECT 48.905 10.795 49.075 10.965 ; - RECT 48.445 10.795 48.615 10.965 ; - RECT 47.985 10.795 48.155 10.965 ; - RECT 47.525 10.795 47.695 10.965 ; - RECT 47.065 10.795 47.235 10.965 ; - RECT 46.605 10.795 46.775 10.965 ; - RECT 46.145 10.795 46.315 10.965 ; - RECT 45.685 10.795 45.855 10.965 ; - RECT 45.225 10.795 45.395 10.965 ; - RECT 44.765 10.795 44.935 10.965 ; - RECT 44.305 10.795 44.475 10.965 ; - RECT 43.845 10.795 44.015 10.965 ; - RECT 43.385 10.795 43.555 10.965 ; - RECT 42.925 10.795 43.095 10.965 ; - RECT 42.465 10.795 42.635 10.965 ; - RECT 42.005 10.795 42.175 10.965 ; - RECT 41.545 10.795 41.715 10.965 ; - RECT 41.085 10.795 41.255 10.965 ; - RECT 40.625 10.795 40.795 10.965 ; - RECT 40.165 10.795 40.335 10.965 ; - RECT 39.705 10.795 39.875 10.965 ; - RECT 39.245 10.795 39.415 10.965 ; - RECT 38.785 10.795 38.955 10.965 ; - RECT 38.325 10.795 38.495 10.965 ; - RECT 37.865 10.795 38.035 10.965 ; - RECT 37.405 10.795 37.575 10.965 ; - RECT 36.945 10.795 37.115 10.965 ; - RECT 36.485 10.795 36.655 10.965 ; - RECT 36.025 10.795 36.195 10.965 ; - RECT 35.565 10.795 35.735 10.965 ; - RECT 35.105 10.795 35.275 10.965 ; - RECT 34.645 10.795 34.815 10.965 ; - RECT 34.185 10.795 34.355 10.965 ; - RECT 33.725 10.795 33.895 10.965 ; - RECT 33.265 10.795 33.435 10.965 ; - RECT 32.805 10.795 32.975 10.965 ; - RECT 32.345 10.795 32.515 10.965 ; - RECT 31.885 10.795 32.055 10.965 ; - RECT 31.425 10.795 31.595 10.965 ; - RECT 30.965 10.795 31.135 10.965 ; - RECT 30.505 10.795 30.675 10.965 ; - RECT 30.045 10.795 30.215 10.965 ; - RECT 29.585 10.795 29.755 10.965 ; - RECT 29.125 10.795 29.295 10.965 ; - RECT 28.665 10.795 28.835 10.965 ; - RECT 28.205 10.795 28.375 10.965 ; - RECT 27.745 10.795 27.915 10.965 ; - RECT 27.285 10.795 27.455 10.965 ; - RECT 26.825 10.795 26.995 10.965 ; - RECT 26.365 10.795 26.535 10.965 ; - RECT 25.905 10.795 26.075 10.965 ; - RECT 25.445 10.795 25.615 10.965 ; - RECT 24.985 10.795 25.155 10.965 ; - RECT 24.525 10.795 24.695 10.965 ; - RECT 24.065 10.795 24.235 10.965 ; - RECT 23.605 10.795 23.775 10.965 ; - RECT 23.145 10.795 23.315 10.965 ; - RECT 22.685 10.795 22.855 10.965 ; - RECT 22.225 10.795 22.395 10.965 ; - RECT 21.765 10.795 21.935 10.965 ; - RECT 21.305 10.795 21.475 10.965 ; - RECT 20.845 10.795 21.015 10.965 ; - RECT 20.385 10.795 20.555 10.965 ; - RECT 19.925 10.795 20.095 10.965 ; - RECT 19.465 10.795 19.635 10.965 ; - RECT 19.005 10.795 19.175 10.965 ; - RECT 18.545 10.795 18.715 10.965 ; - RECT 18.085 10.795 18.255 10.965 ; - RECT 17.625 10.795 17.795 10.965 ; - RECT 17.165 10.795 17.335 10.965 ; - RECT 16.705 10.795 16.875 10.965 ; - RECT 16.245 10.795 16.415 10.965 ; - RECT 15.785 10.795 15.955 10.965 ; - RECT 15.325 10.795 15.495 10.965 ; - RECT 14.865 10.795 15.035 10.965 ; - RECT 14.405 10.795 14.575 10.965 ; - RECT 13.945 10.795 14.115 10.965 ; - RECT 13.485 10.795 13.655 10.965 ; - RECT 13.025 10.795 13.195 10.965 ; - RECT 12.565 10.795 12.735 10.965 ; - RECT 12.105 10.795 12.275 10.965 ; - RECT 11.645 10.795 11.815 10.965 ; - RECT 11.185 10.795 11.355 10.965 ; - RECT 10.725 10.795 10.895 10.965 ; - RECT 10.265 10.795 10.435 10.965 ; - RECT 9.805 10.795 9.975 10.965 ; - RECT 9.345 10.795 9.515 10.965 ; - RECT 8.885 10.795 9.055 10.965 ; - RECT 8.425 10.795 8.595 10.965 ; - RECT 7.965 10.795 8.135 10.965 ; - RECT 7.505 10.795 7.675 10.965 ; - RECT 7.045 10.795 7.215 10.965 ; - RECT 6.585 10.795 6.755 10.965 ; - RECT 6.125 10.795 6.295 10.965 ; - RECT 5.665 10.795 5.835 10.965 ; - RECT 5.205 10.795 5.375 10.965 ; - RECT 4.745 10.795 4.915 10.965 ; - RECT 4.285 10.795 4.455 10.965 ; - RECT 3.825 10.795 3.995 10.965 ; - RECT 3.365 10.795 3.535 10.965 ; - RECT 2.905 10.795 3.075 10.965 ; - RECT 2.445 10.795 2.615 10.965 ; - RECT 1.985 10.795 2.155 10.965 ; - RECT 1.525 10.795 1.695 10.965 ; - RECT 1.065 10.795 1.235 10.965 ; - RECT 0.605 10.795 0.775 10.965 ; - RECT 0.145 10.795 0.315 10.965 ; - RECT 91.685 8.075 91.855 8.245 ; - RECT 91.225 8.075 91.395 8.245 ; - RECT 26.365 8.075 26.535 8.245 ; - RECT 25.905 8.075 26.075 8.245 ; - RECT 91.685 5.355 91.855 5.525 ; - RECT 91.225 5.355 91.395 5.525 ; - RECT 26.365 5.355 26.535 5.525 ; - RECT 25.905 5.355 26.075 5.525 ; - RECT 91.685 2.635 91.855 2.805 ; - RECT 91.225 2.635 91.395 2.805 ; - RECT 26.365 2.635 26.535 2.805 ; - RECT 25.905 2.635 26.075 2.805 ; - RECT 91.685 -0.085 91.855 0.085 ; - RECT 91.225 -0.085 91.395 0.085 ; - RECT 90.765 -0.085 90.935 0.085 ; - RECT 90.305 -0.085 90.475 0.085 ; - RECT 89.845 -0.085 90.015 0.085 ; - RECT 89.385 -0.085 89.555 0.085 ; - RECT 88.925 -0.085 89.095 0.085 ; - RECT 88.465 -0.085 88.635 0.085 ; - RECT 88.005 -0.085 88.175 0.085 ; - RECT 87.545 -0.085 87.715 0.085 ; - RECT 87.085 -0.085 87.255 0.085 ; - RECT 86.625 -0.085 86.795 0.085 ; - RECT 86.165 -0.085 86.335 0.085 ; - RECT 85.705 -0.085 85.875 0.085 ; - RECT 85.245 -0.085 85.415 0.085 ; - RECT 84.785 -0.085 84.955 0.085 ; - RECT 84.325 -0.085 84.495 0.085 ; - RECT 83.865 -0.085 84.035 0.085 ; - RECT 83.405 -0.085 83.575 0.085 ; - RECT 82.945 -0.085 83.115 0.085 ; - RECT 82.485 -0.085 82.655 0.085 ; - RECT 82.025 -0.085 82.195 0.085 ; - RECT 81.565 -0.085 81.735 0.085 ; - RECT 81.105 -0.085 81.275 0.085 ; - RECT 80.645 -0.085 80.815 0.085 ; - RECT 80.185 -0.085 80.355 0.085 ; - RECT 79.725 -0.085 79.895 0.085 ; - RECT 79.265 -0.085 79.435 0.085 ; - RECT 78.805 -0.085 78.975 0.085 ; - RECT 78.345 -0.085 78.515 0.085 ; - RECT 77.885 -0.085 78.055 0.085 ; - RECT 77.425 -0.085 77.595 0.085 ; - RECT 76.965 -0.085 77.135 0.085 ; - RECT 76.505 -0.085 76.675 0.085 ; - RECT 76.045 -0.085 76.215 0.085 ; - RECT 75.585 -0.085 75.755 0.085 ; - RECT 75.125 -0.085 75.295 0.085 ; - RECT 74.665 -0.085 74.835 0.085 ; - RECT 74.205 -0.085 74.375 0.085 ; - RECT 73.745 -0.085 73.915 0.085 ; - RECT 73.285 -0.085 73.455 0.085 ; - RECT 72.825 -0.085 72.995 0.085 ; - RECT 72.365 -0.085 72.535 0.085 ; - RECT 71.905 -0.085 72.075 0.085 ; - RECT 71.445 -0.085 71.615 0.085 ; - RECT 70.985 -0.085 71.155 0.085 ; - RECT 70.525 -0.085 70.695 0.085 ; - RECT 70.065 -0.085 70.235 0.085 ; - RECT 69.605 -0.085 69.775 0.085 ; - RECT 69.145 -0.085 69.315 0.085 ; - RECT 68.685 -0.085 68.855 0.085 ; - RECT 68.225 -0.085 68.395 0.085 ; - RECT 67.765 -0.085 67.935 0.085 ; - RECT 67.305 -0.085 67.475 0.085 ; - RECT 66.845 -0.085 67.015 0.085 ; - RECT 66.385 -0.085 66.555 0.085 ; - RECT 65.925 -0.085 66.095 0.085 ; - RECT 65.465 -0.085 65.635 0.085 ; - RECT 65.005 -0.085 65.175 0.085 ; - RECT 64.545 -0.085 64.715 0.085 ; - RECT 64.085 -0.085 64.255 0.085 ; - RECT 63.625 -0.085 63.795 0.085 ; - RECT 63.165 -0.085 63.335 0.085 ; - RECT 62.705 -0.085 62.875 0.085 ; - RECT 62.245 -0.085 62.415 0.085 ; - RECT 61.785 -0.085 61.955 0.085 ; - RECT 61.325 -0.085 61.495 0.085 ; - RECT 60.865 -0.085 61.035 0.085 ; - RECT 60.405 -0.085 60.575 0.085 ; - RECT 59.945 -0.085 60.115 0.085 ; - RECT 59.485 -0.085 59.655 0.085 ; - RECT 59.025 -0.085 59.195 0.085 ; - RECT 58.565 -0.085 58.735 0.085 ; - RECT 58.105 -0.085 58.275 0.085 ; - RECT 57.645 -0.085 57.815 0.085 ; - RECT 57.185 -0.085 57.355 0.085 ; - RECT 56.725 -0.085 56.895 0.085 ; - RECT 56.265 -0.085 56.435 0.085 ; - RECT 55.805 -0.085 55.975 0.085 ; - RECT 55.345 -0.085 55.515 0.085 ; - RECT 54.885 -0.085 55.055 0.085 ; - RECT 54.425 -0.085 54.595 0.085 ; - RECT 53.965 -0.085 54.135 0.085 ; - RECT 53.505 -0.085 53.675 0.085 ; - RECT 53.045 -0.085 53.215 0.085 ; - RECT 52.585 -0.085 52.755 0.085 ; - RECT 52.125 -0.085 52.295 0.085 ; - RECT 51.665 -0.085 51.835 0.085 ; - RECT 51.205 -0.085 51.375 0.085 ; - RECT 50.745 -0.085 50.915 0.085 ; - RECT 50.285 -0.085 50.455 0.085 ; - RECT 49.825 -0.085 49.995 0.085 ; - RECT 49.365 -0.085 49.535 0.085 ; - RECT 48.905 -0.085 49.075 0.085 ; - RECT 48.445 -0.085 48.615 0.085 ; - RECT 47.985 -0.085 48.155 0.085 ; - RECT 47.525 -0.085 47.695 0.085 ; - RECT 47.065 -0.085 47.235 0.085 ; - RECT 46.605 -0.085 46.775 0.085 ; - RECT 46.145 -0.085 46.315 0.085 ; - RECT 45.685 -0.085 45.855 0.085 ; - RECT 45.225 -0.085 45.395 0.085 ; - RECT 44.765 -0.085 44.935 0.085 ; - RECT 44.305 -0.085 44.475 0.085 ; - RECT 43.845 -0.085 44.015 0.085 ; - RECT 43.385 -0.085 43.555 0.085 ; - RECT 42.925 -0.085 43.095 0.085 ; - RECT 42.465 -0.085 42.635 0.085 ; - RECT 42.005 -0.085 42.175 0.085 ; - RECT 41.545 -0.085 41.715 0.085 ; - RECT 41.085 -0.085 41.255 0.085 ; - RECT 40.625 -0.085 40.795 0.085 ; - RECT 40.165 -0.085 40.335 0.085 ; - RECT 39.705 -0.085 39.875 0.085 ; - RECT 39.245 -0.085 39.415 0.085 ; - RECT 38.785 -0.085 38.955 0.085 ; - RECT 38.325 -0.085 38.495 0.085 ; - RECT 37.865 -0.085 38.035 0.085 ; - RECT 37.405 -0.085 37.575 0.085 ; - RECT 36.945 -0.085 37.115 0.085 ; - RECT 36.485 -0.085 36.655 0.085 ; - RECT 36.025 -0.085 36.195 0.085 ; - RECT 35.565 -0.085 35.735 0.085 ; - RECT 35.105 -0.085 35.275 0.085 ; - RECT 34.645 -0.085 34.815 0.085 ; - RECT 34.185 -0.085 34.355 0.085 ; - RECT 33.725 -0.085 33.895 0.085 ; - RECT 33.265 -0.085 33.435 0.085 ; - RECT 32.805 -0.085 32.975 0.085 ; - RECT 32.345 -0.085 32.515 0.085 ; - RECT 31.885 -0.085 32.055 0.085 ; - RECT 31.425 -0.085 31.595 0.085 ; - RECT 30.965 -0.085 31.135 0.085 ; - RECT 30.505 -0.085 30.675 0.085 ; - RECT 30.045 -0.085 30.215 0.085 ; - RECT 29.585 -0.085 29.755 0.085 ; - RECT 29.125 -0.085 29.295 0.085 ; - RECT 28.665 -0.085 28.835 0.085 ; - RECT 28.205 -0.085 28.375 0.085 ; - RECT 27.745 -0.085 27.915 0.085 ; - RECT 27.285 -0.085 27.455 0.085 ; - RECT 26.825 -0.085 26.995 0.085 ; - RECT 26.365 -0.085 26.535 0.085 ; - RECT 25.905 -0.085 26.075 0.085 ; - LAYER via ; - RECT 80.885 108.725 81.035 108.875 ; - RECT 51.445 108.725 51.595 108.875 ; - RECT 62.945 107.025 63.095 107.175 ; - RECT 52.365 107.025 52.515 107.175 ; - RECT 37.645 107.025 37.795 107.175 ; - RECT 80.885 97.845 81.035 97.995 ; - RECT 51.445 97.845 51.595 97.995 ; - RECT 10.965 97.845 11.115 97.995 ; - RECT 16.025 96.145 16.175 96.295 ; - RECT 9.125 12.505 9.275 12.655 ; - RECT 80.885 10.805 81.035 10.955 ; - RECT 51.445 10.805 51.595 10.955 ; - RECT 10.965 10.805 11.115 10.955 ; - RECT 49.145 1.625 49.295 1.775 ; - RECT 41.785 1.625 41.935 1.775 ; - RECT 80.885 -0.075 81.035 0.075 ; - RECT 51.445 -0.075 51.595 0.075 ; - LAYER via2 ; - RECT 80.86 108.7 81.06 108.9 ; - RECT 51.42 108.7 51.62 108.9 ; - RECT 10.94 97.82 11.14 98.02 ; - RECT 1.28 81.5 1.48 81.7 ; - RECT 1.74 76.74 1.94 76.94 ; - RECT 1.28 57.02 1.48 57.22 ; - RECT 1.28 40.02 1.48 40.22 ; - RECT 1.28 33.22 1.48 33.42 ; - RECT 10.94 10.78 11.14 10.98 ; - RECT 80.86 -0.1 81.06 0.1 ; - RECT 51.42 -0.1 51.62 0.1 ; - LAYER via3 ; - RECT 80.86 108.7 81.06 108.9 ; - RECT 51.42 108.7 51.62 108.9 ; - RECT 10.94 97.82 11.14 98.02 ; - RECT 10.94 10.78 11.14 10.98 ; - RECT 80.86 -0.1 81.06 0.1 ; - RECT 51.42 -0.1 51.62 0.1 ; - LAYER OVERLAP ; - POLYGON 25.76 0 25.76 10.88 0 10.88 0 97.92 25.76 97.92 25.76 108.8 92 108.8 92 0 ; - END -END sb_2__1_ - -END LIBRARY diff --git a/FPGA22_HIER_SKY_PNR/modules/lef/sb_2__2__icv_in_design.lef b/FPGA22_HIER_SKY_PNR/modules/lef/sb_2__2__icv_in_design.lef deleted file mode 100644 index 1c394cc..0000000 --- a/FPGA22_HIER_SKY_PNR/modules/lef/sb_2__2__icv_in_design.lef +++ /dev/null @@ -1,2136 +0,0 @@ -VERSION 5.7 ; -BUSBITCHARS "[]" ; - -UNITS - DATABASE MICRONS 1000 ; -END UNITS - -MANUFACTURINGGRID 0.005 ; - -LAYER li1 - TYPE ROUTING ; - DIRECTION VERTICAL ; - PITCH 0.46 ; - WIDTH 0.17 ; -END li1 - -LAYER mcon - TYPE CUT ; -END mcon - -LAYER met1 - TYPE ROUTING ; - DIRECTION HORIZONTAL ; - PITCH 0.34 ; - WIDTH 0.14 ; -END met1 - -LAYER via - TYPE CUT ; -END via - -LAYER met2 - TYPE ROUTING ; - DIRECTION VERTICAL ; - PITCH 0.46 ; - WIDTH 0.14 ; -END met2 - -LAYER via2 - TYPE CUT ; -END via2 - -LAYER met3 - TYPE ROUTING ; - DIRECTION HORIZONTAL ; - PITCH 0.68 ; - WIDTH 0.3 ; -END met3 - -LAYER via3 - TYPE CUT ; -END via3 - -LAYER met4 - TYPE ROUTING ; - DIRECTION VERTICAL ; - PITCH 0.92 ; - WIDTH 0.3 ; -END met4 - -LAYER via4 - TYPE CUT ; -END via4 - -LAYER met5 - TYPE ROUTING ; - DIRECTION HORIZONTAL ; - PITCH 3.4 ; - WIDTH 1.6 ; -END met5 - -LAYER nwell - TYPE MASTERSLICE ; -END nwell - -LAYER pwell - TYPE MASTERSLICE ; -END pwell - -LAYER OVERLAP - TYPE OVERLAP ; -END OVERLAP - -VIA L1M1_PR - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.145 -0.115 0.145 0.115 ; -END L1M1_PR - -VIA L1M1_PR_R - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.115 -0.145 0.115 0.145 ; -END L1M1_PR_R - -VIA L1M1_PR_M - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.115 -0.145 0.115 0.145 ; -END L1M1_PR_M - -VIA L1M1_PR_MR - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.145 -0.115 0.145 0.115 ; -END L1M1_PR_MR - -VIA L1M1_PR_C - LAYER li1 ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER mcon ; - RECT -0.085 -0.085 0.085 0.085 ; - LAYER met1 ; - RECT -0.145 -0.145 0.145 0.145 ; -END L1M1_PR_C - -VIA M1M2_PR - LAYER met1 ; - RECT -0.16 -0.13 0.16 0.13 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.13 -0.16 0.13 0.16 ; -END M1M2_PR - -VIA M1M2_PR_Enc - LAYER met1 ; - RECT -0.16 -0.13 0.16 0.13 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.16 -0.13 0.16 0.13 ; -END M1M2_PR_Enc - -VIA M1M2_PR_R - LAYER met1 ; - RECT -0.13 -0.16 0.13 0.16 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.16 -0.13 0.16 0.13 ; -END M1M2_PR_R - -VIA M1M2_PR_R_Enc - LAYER met1 ; - RECT -0.13 -0.16 0.13 0.16 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.13 -0.16 0.13 0.16 ; -END M1M2_PR_R_Enc - -VIA M1M2_PR_M - LAYER met1 ; - RECT -0.16 -0.13 0.16 0.13 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.16 -0.13 0.16 0.13 ; -END M1M2_PR_M - -VIA M1M2_PR_M_Enc - LAYER met1 ; - RECT -0.16 -0.13 0.16 0.13 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.13 -0.16 0.13 0.16 ; -END M1M2_PR_M_Enc - -VIA M1M2_PR_MR - LAYER met1 ; - RECT -0.13 -0.16 0.13 0.16 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.13 -0.16 0.13 0.16 ; -END M1M2_PR_MR - -VIA M1M2_PR_MR_Enc - LAYER met1 ; - RECT -0.13 -0.16 0.13 0.16 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.16 -0.13 0.16 0.13 ; -END M1M2_PR_MR_Enc - -VIA M1M2_PR_C - LAYER met1 ; - RECT -0.16 -0.16 0.16 0.16 ; - LAYER via ; - RECT -0.075 -0.075 0.075 0.075 ; - LAYER met2 ; - RECT -0.16 -0.16 0.16 0.16 ; -END M1M2_PR_C - -VIA M2M3_PR - LAYER met2 ; - RECT -0.14 -0.185 0.14 0.185 ; - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met3 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M2M3_PR - -VIA M2M3_PR_R - LAYER met2 ; - RECT -0.185 -0.14 0.185 0.14 ; - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met3 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M2M3_PR_R - -VIA M2M3_PR_M - LAYER met2 ; - RECT -0.14 -0.185 0.14 0.185 ; - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met3 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M2M3_PR_M - -VIA M2M3_PR_MR - LAYER met2 ; - RECT -0.185 -0.14 0.185 0.14 ; - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met3 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M2M3_PR_MR - -VIA M2M3_PR_C - LAYER met2 ; - RECT -0.185 -0.185 0.185 0.185 ; - LAYER via2 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met3 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M2M3_PR_C - -VIA M3M4_PR - LAYER met3 ; - RECT -0.19 -0.16 0.19 0.16 ; - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR - -VIA M3M4_PR_R - LAYER met3 ; - RECT -0.16 -0.19 0.16 0.19 ; - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR_R - -VIA M3M4_PR_M - LAYER met3 ; - RECT -0.19 -0.16 0.19 0.16 ; - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR_M - -VIA M3M4_PR_MR - LAYER met3 ; - RECT -0.16 -0.19 0.16 0.19 ; - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR_MR - -VIA M3M4_PR_C - LAYER met3 ; - RECT -0.19 -0.19 0.19 0.19 ; - LAYER via3 ; - RECT -0.1 -0.1 0.1 0.1 ; - LAYER met4 ; - RECT -0.165 -0.165 0.165 0.165 ; -END M3M4_PR_C - -VIA M4M5_PR - LAYER met4 ; - RECT -0.59 -0.59 0.59 0.59 ; - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - LAYER met5 ; - RECT -0.71 -0.71 0.71 0.71 ; -END M4M5_PR - -VIA M4M5_PR_R - LAYER met4 ; - RECT -0.59 -0.59 0.59 0.59 ; - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - LAYER met5 ; - RECT -0.71 -0.71 0.71 0.71 ; -END M4M5_PR_R - -VIA M4M5_PR_M - LAYER met4 ; - RECT -0.59 -0.59 0.59 0.59 ; - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - LAYER met5 ; - RECT -0.71 -0.71 0.71 0.71 ; -END M4M5_PR_M - -VIA M4M5_PR_MR - LAYER met4 ; - RECT -0.59 -0.59 0.59 0.59 ; - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - LAYER met5 ; - RECT -0.71 -0.71 0.71 0.71 ; -END M4M5_PR_MR - -VIA M4M5_PR_C - LAYER met4 ; - RECT -0.59 -0.59 0.59 0.59 ; - LAYER via4 ; - RECT -0.4 -0.4 0.4 0.4 ; - LAYER met5 ; - RECT -0.71 -0.71 0.71 0.71 ; -END M4M5_PR_C - -SITE unit - CLASS CORE ; - SYMMETRY Y ; - SIZE 0.46 BY 2.72 ; -END unit - -SITE unithddbl - CLASS CORE ; - SIZE 0.46 BY 5.44 ; -END unithddbl - -MACRO sb_2__2_ - CLASS BLOCK ; - ORIGIN 0 0 ; - SIZE 92 BY 97.92 ; - SYMMETRY X Y ; - PIN prog_clk[0] - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER met3 ; - RECT 0 35.21 1.38 35.51 ; - END - END prog_clk[0] - PIN chany_bottom_in[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 55.59 0 55.73 1.36 ; - END - END chany_bottom_in[0] - PIN chany_bottom_in[1] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 50.53 0 50.67 1.36 ; - END - END chany_bottom_in[1] - PIN chany_bottom_in[2] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 56.89 0 57.19 1.36 ; - END - END chany_bottom_in[2] - PIN chany_bottom_in[3] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 46.85 0 46.99 1.36 ; - END - END chany_bottom_in[3] - PIN chany_bottom_in[4] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 54.21 0 54.35 1.36 ; - END - END chany_bottom_in[4] - PIN chany_bottom_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 53.29 0 53.43 1.36 ; - END - END chany_bottom_in[5] - PIN chany_bottom_in[6] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 69.39 0 69.53 1.36 ; - END - END chany_bottom_in[6] - PIN chany_bottom_in[7] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 62.95 0 63.09 1.36 ; - END - END chany_bottom_in[7] - PIN chany_bottom_in[8] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 72.61 0 72.75 1.36 ; - END - END chany_bottom_in[8] - PIN chany_bottom_in[9] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 64.79 0 64.93 1.36 ; - END - END chany_bottom_in[9] - PIN chany_bottom_in[10] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 39.95 0 40.09 1.36 ; - END - END chany_bottom_in[10] - PIN chany_bottom_in[11] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 62.03 0 62.17 1.36 ; - END - END chany_bottom_in[11] - PIN chany_bottom_in[12] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 42.71 0 42.85 1.36 ; - END - END chany_bottom_in[12] - PIN chany_bottom_in[13] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 44.09 0 44.23 1.36 ; - END - END chany_bottom_in[13] - PIN chany_bottom_in[14] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 56.51 0 56.65 1.36 ; - END - END chany_bottom_in[14] - PIN chany_bottom_in[15] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 60.19 0 60.33 1.36 ; - END - END chany_bottom_in[15] - PIN chany_bottom_in[16] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 68.47 0 68.61 1.36 ; - END - END chany_bottom_in[16] - PIN chany_bottom_in[17] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 73.53 0 73.67 1.36 ; - END - END chany_bottom_in[17] - PIN chany_bottom_in[18] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 74.45 0 74.59 1.36 ; - END - END chany_bottom_in[18] - PIN chany_bottom_in[19] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 61.11 0 61.25 1.36 ; - END - END chany_bottom_in[19] - PIN bottom_right_grid_pin_1_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 39.03 0 39.17 1.36 ; - END - END bottom_right_grid_pin_1_[0] - PIN bottom_left_grid_pin_42_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 12.73 10.88 13.03 12.24 ; - END - END bottom_left_grid_pin_42_[0] - PIN bottom_left_grid_pin_43_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 9.05 10.88 9.35 12.24 ; - END - END bottom_left_grid_pin_43_[0] - PIN bottom_left_grid_pin_44_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 18.33 10.88 18.47 12.24 ; - END - END bottom_left_grid_pin_44_[0] - PIN bottom_left_grid_pin_45_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 7.29 10.88 7.43 12.24 ; - END - END bottom_left_grid_pin_45_[0] - PIN bottom_left_grid_pin_46_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 9.13 10.88 9.27 12.24 ; - END - END bottom_left_grid_pin_46_[0] - PIN bottom_left_grid_pin_47_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 15.11 10.88 15.25 12.24 ; - END - END bottom_left_grid_pin_47_[0] - PIN bottom_left_grid_pin_48_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 8.21 10.88 8.35 12.24 ; - END - END bottom_left_grid_pin_48_[0] - PIN bottom_left_grid_pin_49_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 10.05 10.88 10.19 12.24 ; - END - END bottom_left_grid_pin_49_[0] - PIN chanx_left_in[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 42.69 1.38 42.99 ; - END - END chanx_left_in[0] - PIN chanx_left_in[1] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 54.93 1.38 55.23 ; - END - END chanx_left_in[1] - PIN chanx_left_in[2] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 49.49 1.38 49.79 ; - END - END chanx_left_in[2] - PIN chanx_left_in[3] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 21.61 1.38 21.91 ; - END - END chanx_left_in[3] - PIN chanx_left_in[4] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 22.97 1.38 23.27 ; - END - END chanx_left_in[4] - PIN chanx_left_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 33.17 1.38 33.47 ; - END - END chanx_left_in[5] - PIN chanx_left_in[6] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 26.37 1.38 26.67 ; - END - END chanx_left_in[6] - PIN chanx_left_in[7] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 29.09 1.38 29.39 ; - END - END chanx_left_in[7] - PIN chanx_left_in[8] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 41.33 1.38 41.63 ; - END - END chanx_left_in[8] - PIN chanx_left_in[9] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 56.29 1.38 56.59 ; - END - END chanx_left_in[9] - PIN chanx_left_in[10] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 57.65 1.38 57.95 ; - END - END chanx_left_in[10] - PIN chanx_left_in[11] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 59.01 1.38 59.31 ; - END - END chanx_left_in[11] - PIN chanx_left_in[12] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 18.89 1.38 19.19 ; - END - END chanx_left_in[12] - PIN chanx_left_in[13] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 20.25 1.38 20.55 ; - END - END chanx_left_in[13] - PIN chanx_left_in[14] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 17.53 1.38 17.83 ; - END - END chanx_left_in[14] - PIN chanx_left_in[15] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 30.45 1.38 30.75 ; - END - END chanx_left_in[15] - PIN chanx_left_in[16] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 64.45 1.38 64.75 ; - END - END chanx_left_in[16] - PIN chanx_left_in[17] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 50.85 1.38 51.15 ; - END - END chanx_left_in[17] - PIN chanx_left_in[18] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 69.21 1.38 69.51 ; - END - END chanx_left_in[18] - PIN chanx_left_in[19] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 38.61 1.38 38.91 ; - END - END chanx_left_in[19] - PIN left_top_grid_pin_1_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 61.05 1.38 61.35 ; - END - END left_top_grid_pin_1_[0] - PIN left_bottom_grid_pin_34_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 27.99 0 28.13 1.36 ; - END - END left_bottom_grid_pin_34_[0] - PIN left_bottom_grid_pin_35_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 12.81 10.88 12.95 12.24 ; - END - END left_bottom_grid_pin_35_[0] - PIN left_bottom_grid_pin_36_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 4.99 10.88 5.13 12.24 ; - END - END left_bottom_grid_pin_36_[0] - PIN left_bottom_grid_pin_37_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 4.07 10.88 4.21 12.24 ; - END - END left_bottom_grid_pin_37_[0] - PIN left_bottom_grid_pin_38_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 6.37 10.88 6.51 12.24 ; - END - END left_bottom_grid_pin_38_[0] - PIN left_bottom_grid_pin_39_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 4.45 10.88 4.75 12.24 ; - END - END left_bottom_grid_pin_39_[0] - PIN left_bottom_grid_pin_40_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 11.89 10.88 12.03 12.24 ; - END - END left_bottom_grid_pin_40_[0] - PIN left_bottom_grid_pin_41_[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 16.03 10.88 16.17 12.24 ; - END - END left_bottom_grid_pin_41_[0] - PIN ccff_head[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 2.23 96.56 2.37 97.92 ; - END - END ccff_head[0] - PIN chany_bottom_out[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 63.87 0 64.01 1.36 ; - END - END chany_bottom_out[0] - PIN chany_bottom_out[1] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met4 ; - RECT 58.73 0 59.03 1.36 ; - END - END chany_bottom_out[1] - PIN chany_bottom_out[2] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 81.81 0 81.95 1.36 ; - END - END chany_bottom_out[2] - PIN chany_bottom_out[3] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 40.87 0 41.01 1.36 ; - END - END chany_bottom_out[3] - PIN chany_bottom_out[4] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 37.19 0 37.33 1.36 ; - END - END chany_bottom_out[4] - PIN chany_bottom_out[5] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 41.79 0 41.93 1.36 ; - END - END chany_bottom_out[5] - PIN chany_bottom_out[6] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 66.17 0 66.31 1.36 ; - END - END chany_bottom_out[6] - PIN chany_bottom_out[7] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 47.77 0 47.91 1.36 ; - END - END chany_bottom_out[7] - PIN chany_bottom_out[8] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 57.43 0 57.57 1.36 ; - END - END chany_bottom_out[8] - PIN chany_bottom_out[9] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 38.11 0 38.25 1.36 ; - END - END chany_bottom_out[9] - PIN chany_bottom_out[10] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 71.69 0 71.83 1.36 ; - END - END chany_bottom_out[10] - PIN chany_bottom_out[11] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 33.97 0 34.11 1.36 ; - END - END chany_bottom_out[11] - PIN chany_bottom_out[12] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 58.81 0 58.95 1.36 ; - END - END chany_bottom_out[12] - PIN chany_bottom_out[13] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 32.13 0 32.27 1.36 ; - END - END chany_bottom_out[13] - PIN chany_bottom_out[14] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 67.09 0 67.23 1.36 ; - END - END chany_bottom_out[14] - PIN chany_bottom_out[15] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 49.15 0 49.29 1.36 ; - END - END chany_bottom_out[15] - PIN chany_bottom_out[16] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 52.37 0 52.51 1.36 ; - END - END chany_bottom_out[16] - PIN chany_bottom_out[17] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 45.47 0 45.61 1.36 ; - END - END chany_bottom_out[17] - PIN chany_bottom_out[18] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 70.77 0 70.91 1.36 ; - END - END chany_bottom_out[18] - PIN chany_bottom_out[19] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 31.21 0 31.35 1.36 ; - END - END chany_bottom_out[19] - PIN chanx_left_out[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 71.93 1.38 72.23 ; - END - END chanx_left_out[0] - PIN chanx_left_out[1] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 89.61 1.38 89.91 ; - END - END chanx_left_out[1] - PIN chanx_left_out[2] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 73.29 1.38 73.59 ; - END - END chanx_left_out[2] - PIN chanx_left_out[3] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 52.21 1.38 52.51 ; - END - END chanx_left_out[3] - PIN chanx_left_out[4] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 70.57 1.38 70.87 ; - END - END chanx_left_out[4] - PIN chanx_left_out[5] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 67.85 1.38 68.15 ; - END - END chanx_left_out[5] - PIN chanx_left_out[6] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 46.77 1.38 47.07 ; - END - END chanx_left_out[6] - PIN chanx_left_out[7] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 48.13 1.38 48.43 ; - END - END chanx_left_out[7] - PIN chanx_left_out[8] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 77.37 1.38 77.67 ; - END - END chanx_left_out[8] - PIN chanx_left_out[9] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 44.05 1.38 44.35 ; - END - END chanx_left_out[9] - PIN chanx_left_out[10] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 53.57 1.38 53.87 ; - END - END chanx_left_out[10] - PIN chanx_left_out[11] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 37.25 1.38 37.55 ; - END - END chanx_left_out[11] - PIN chanx_left_out[12] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 74.65 1.38 74.95 ; - END - END chanx_left_out[12] - PIN chanx_left_out[13] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 27.73 1.38 28.03 ; - END - END chanx_left_out[13] - PIN chanx_left_out[14] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 63.09 1.38 63.39 ; - END - END chanx_left_out[14] - PIN chanx_left_out[15] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 39.97 1.38 40.27 ; - END - END chanx_left_out[15] - PIN chanx_left_out[16] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 24.33 1.38 24.63 ; - END - END chanx_left_out[16] - PIN chanx_left_out[17] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 31.81 1.38 32.11 ; - END - END chanx_left_out[17] - PIN chanx_left_out[18] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 45.41 1.38 45.71 ; - END - END chanx_left_out[18] - PIN chanx_left_out[19] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 65.81 1.38 66.11 ; - END - END chanx_left_out[19] - PIN ccff_tail[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 14.81 1.38 15.11 ; - END - END ccff_tail[0] - PIN SC_IN_TOP - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 16.17 1.38 16.47 ; - END - END SC_IN_TOP - PIN SC_IN_BOT - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 78.73 1.38 79.03 ; - END - END SC_IN_BOT - PIN SC_OUT_TOP - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 31.21 96.56 31.35 97.92 ; - END - END SC_OUT_TOP - PIN SC_OUT_BOT - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met3 ; - RECT 0 76.01 1.38 76.31 ; - END - END SC_OUT_BOT - PIN VDD - DIRECTION INPUT ; - USE POWER ; - PORT - LAYER met1 ; - RECT 25.76 2.48 26.24 2.96 ; - RECT 91.52 2.48 92 2.96 ; - RECT 25.76 7.92 26.24 8.4 ; - RECT 91.52 7.92 92 8.4 ; - RECT 0 13.36 0.48 13.84 ; - RECT 91.52 13.36 92 13.84 ; - RECT 0 18.8 0.48 19.28 ; - RECT 91.52 18.8 92 19.28 ; - RECT 0 24.24 0.48 24.72 ; - RECT 91.52 24.24 92 24.72 ; - RECT 0 29.68 0.48 30.16 ; - RECT 91.52 29.68 92 30.16 ; - RECT 0 35.12 0.48 35.6 ; - RECT 91.52 35.12 92 35.6 ; - RECT 0 40.56 0.48 41.04 ; - RECT 91.52 40.56 92 41.04 ; - RECT 0 46 0.48 46.48 ; - RECT 91.52 46 92 46.48 ; - RECT 0 51.44 0.48 51.92 ; - RECT 91.52 51.44 92 51.92 ; - RECT 0 56.88 0.48 57.36 ; - RECT 91.52 56.88 92 57.36 ; - RECT 0 62.32 0.48 62.8 ; - RECT 91.52 62.32 92 62.8 ; - RECT 0 67.76 0.48 68.24 ; - RECT 91.52 67.76 92 68.24 ; - RECT 0 73.2 0.48 73.68 ; - RECT 91.52 73.2 92 73.68 ; - RECT 0 78.64 0.48 79.12 ; - RECT 91.52 78.64 92 79.12 ; - RECT 0 84.08 0.48 84.56 ; - RECT 91.52 84.08 92 84.56 ; - RECT 0 89.52 0.48 90 ; - RECT 91.52 89.52 92 90 ; - RECT 0 94.96 0.48 95.44 ; - RECT 91.52 94.96 92 95.44 ; - LAYER met4 ; - RECT 36.5 0 37.1 0.6 ; - RECT 65.94 0 66.54 0.6 ; - RECT 36.5 97.32 37.1 97.92 ; - RECT 65.94 97.32 66.54 97.92 ; - LAYER met5 ; - RECT 0 22.2 3.2 25.4 ; - RECT 88.8 22.2 92 25.4 ; - RECT 0 63 3.2 66.2 ; - RECT 88.8 63 92 66.2 ; - END - END VDD - PIN VSS - DIRECTION INPUT ; - USE GROUND ; - PORT - LAYER met1 ; - RECT 25.76 0 92 0.24 ; - RECT 25.76 5.2 26.24 5.68 ; - RECT 91.52 5.2 92 5.68 ; - RECT 0 10.64 92 11.12 ; - RECT 0 16.08 0.48 16.56 ; - RECT 91.52 16.08 92 16.56 ; - RECT 0 21.52 0.48 22 ; - RECT 91.52 21.52 92 22 ; - RECT 0 26.96 0.48 27.44 ; - RECT 91.52 26.96 92 27.44 ; - RECT 0 32.4 0.48 32.88 ; - RECT 91.52 32.4 92 32.88 ; - RECT 0 37.84 0.48 38.32 ; - RECT 91.52 37.84 92 38.32 ; - RECT 0 43.28 0.48 43.76 ; - RECT 91.52 43.28 92 43.76 ; - RECT 0 48.72 0.48 49.2 ; - RECT 91.52 48.72 92 49.2 ; - RECT 0 54.16 0.48 54.64 ; - RECT 91.52 54.16 92 54.64 ; - RECT 0 59.6 0.48 60.08 ; - RECT 91.52 59.6 92 60.08 ; - RECT 0 65.04 0.48 65.52 ; - RECT 91.52 65.04 92 65.52 ; - RECT 0 70.48 0.48 70.96 ; - RECT 91.52 70.48 92 70.96 ; - RECT 0 75.92 0.48 76.4 ; - RECT 91.52 75.92 92 76.4 ; - RECT 0 81.36 0.48 81.84 ; - RECT 91.52 81.36 92 81.84 ; - RECT 0 86.8 0.48 87.28 ; - RECT 91.52 86.8 92 87.28 ; - RECT 0 92.24 0.48 92.72 ; - RECT 91.52 92.24 92 92.72 ; - RECT 0 97.68 92 97.92 ; - LAYER met4 ; - RECT 51.22 0 51.82 0.6 ; - RECT 80.66 0 81.26 0.6 ; - RECT 10.74 10.88 11.34 11.48 ; - RECT 10.74 97.32 11.34 97.92 ; - RECT 51.22 97.32 51.82 97.92 ; - RECT 80.66 97.32 81.26 97.92 ; - LAYER met5 ; - RECT 0 42.6 3.2 45.8 ; - RECT 88.8 42.6 92 45.8 ; - RECT 0 83.4 3.2 86.6 ; - RECT 88.8 83.4 92 86.6 ; - END - END VSS - OBS - LAYER li1 ; - RECT 0 97.835 92 98.005 ; - RECT 91.54 95.115 92 95.285 ; - RECT 0 95.115 3.68 95.285 ; - RECT 91.54 92.395 92 92.565 ; - RECT 0 92.395 3.68 92.565 ; - RECT 91.54 89.675 92 89.845 ; - RECT 0 89.675 3.68 89.845 ; - RECT 91.54 86.955 92 87.125 ; - RECT 0 86.955 3.68 87.125 ; - RECT 91.54 84.235 92 84.405 ; - RECT 0 84.235 3.68 84.405 ; - RECT 91.54 81.515 92 81.685 ; - RECT 0 81.515 3.68 81.685 ; - RECT 91.54 78.795 92 78.965 ; - RECT 0 78.795 3.68 78.965 ; - RECT 88.32 76.075 92 76.245 ; - RECT 0 76.075 1.84 76.245 ; - RECT 88.32 73.355 92 73.525 ; - RECT 0 73.355 1.84 73.525 ; - RECT 88.32 70.635 92 70.805 ; - RECT 0 70.635 1.84 70.805 ; - RECT 88.32 67.915 92 68.085 ; - RECT 0 67.915 1.84 68.085 ; - RECT 91.54 65.195 92 65.365 ; - RECT 0 65.195 3.68 65.365 ; - RECT 91.54 62.475 92 62.645 ; - RECT 0 62.475 3.68 62.645 ; - RECT 91.08 59.755 92 59.925 ; - RECT 0 59.755 3.68 59.925 ; - RECT 91.08 57.035 92 57.205 ; - RECT 0 57.035 3.68 57.205 ; - RECT 90.16 54.315 92 54.485 ; - RECT 0 54.315 3.68 54.485 ; - RECT 90.16 51.595 92 51.765 ; - RECT 0 51.595 3.68 51.765 ; - RECT 90.16 48.875 92 49.045 ; - RECT 0 48.875 1.84 49.045 ; - RECT 90.16 46.155 92 46.325 ; - RECT 0 46.155 3.68 46.325 ; - RECT 91.54 43.435 92 43.605 ; - RECT 0 43.435 3.68 43.605 ; - RECT 91.54 40.715 92 40.885 ; - RECT 0 40.715 3.68 40.885 ; - RECT 91.08 37.995 92 38.165 ; - RECT 0 37.995 3.68 38.165 ; - RECT 91.08 35.275 92 35.445 ; - RECT 0 35.275 3.68 35.445 ; - RECT 91.54 32.555 92 32.725 ; - RECT 0 32.555 3.68 32.725 ; - RECT 91.54 29.835 92 30.005 ; - RECT 0 29.835 1.84 30.005 ; - RECT 91.54 27.115 92 27.285 ; - RECT 0 27.115 1.84 27.285 ; - RECT 91.54 24.395 92 24.565 ; - RECT 0 24.395 1.84 24.565 ; - RECT 91.08 21.675 92 21.845 ; - RECT 0 21.675 1.84 21.845 ; - RECT 91.08 18.955 92 19.125 ; - RECT 0 18.955 1.84 19.125 ; - RECT 91.54 16.235 92 16.405 ; - RECT 0 16.235 3.68 16.405 ; - RECT 91.54 13.515 92 13.685 ; - RECT 0 13.515 3.68 13.685 ; - RECT 91.08 10.795 92 10.965 ; - RECT 0 10.795 29.44 10.965 ; - RECT 91.08 8.075 92 8.245 ; - RECT 25.76 8.075 29.44 8.245 ; - RECT 88.32 5.355 92 5.525 ; - RECT 25.76 5.355 27.6 5.525 ; - RECT 88.32 2.635 92 2.805 ; - RECT 25.76 2.635 29.44 2.805 ; - RECT 25.76 -0.085 92 0.085 ; - LAYER met3 ; - POLYGON 81.125 98.085 81.125 98.08 81.34 98.08 81.34 97.76 81.125 97.76 81.125 97.755 80.795 97.755 80.795 97.76 80.58 97.76 80.58 98.08 80.795 98.08 80.795 98.085 ; - POLYGON 51.685 98.085 51.685 98.08 51.9 98.08 51.9 97.76 51.685 97.76 51.685 97.755 51.355 97.755 51.355 97.76 51.14 97.76 51.14 98.08 51.355 98.08 51.355 98.085 ; - POLYGON 11.205 98.085 11.205 98.08 11.42 98.08 11.42 97.76 11.205 97.76 11.205 97.755 10.875 97.755 10.875 97.76 10.66 97.76 10.66 98.08 10.875 98.08 10.875 98.085 ; - POLYGON 28.67 68.83 28.67 68.53 1.23 68.53 1.23 68.81 1.78 68.81 1.78 68.83 ; - POLYGON 2.03 18.52 2.03 18.51 6.13 18.51 6.13 18.21 2.03 18.21 2.03 18.2 1.65 18.2 1.65 18.52 ; - POLYGON 24.53 17.15 24.53 16.85 1.23 16.85 1.23 17.13 1.78 17.13 1.78 17.15 ; - POLYGON 11.205 11.045 11.205 11.04 11.42 11.04 11.42 10.72 11.205 10.72 11.205 10.715 10.875 10.715 10.875 10.72 10.66 10.72 10.66 11.04 10.875 11.04 10.875 11.045 ; - POLYGON 81.125 0.165 81.125 0.16 81.34 0.16 81.34 -0.16 81.125 -0.16 81.125 -0.165 80.795 -0.165 80.795 -0.16 80.58 -0.16 80.58 0.16 80.795 0.16 80.795 0.165 ; - POLYGON 51.685 0.165 51.685 0.16 51.9 0.16 51.9 -0.16 51.685 -0.16 51.685 -0.165 51.355 -0.165 51.355 -0.16 51.14 -0.16 51.14 0.16 51.355 0.16 51.355 0.165 ; - POLYGON 91.6 97.52 91.6 0.4 26.16 0.4 26.16 11.28 0.4 11.28 0.4 14.41 1.78 14.41 1.78 15.51 0.4 15.51 0.4 15.77 1.78 15.77 1.78 16.87 0.4 16.87 0.4 17.13 1.78 17.13 1.78 18.23 0.4 18.23 0.4 18.49 1.78 18.49 1.78 19.59 0.4 19.59 0.4 19.85 1.78 19.85 1.78 20.95 0.4 20.95 0.4 21.21 1.78 21.21 1.78 22.31 0.4 22.31 0.4 22.57 1.78 22.57 1.78 23.67 0.4 23.67 0.4 23.93 1.78 23.93 1.78 25.03 0.4 25.03 0.4 25.97 1.78 25.97 1.78 27.07 0.4 27.07 0.4 27.33 1.78 27.33 1.78 28.43 0.4 28.43 0.4 28.69 1.78 28.69 1.78 29.79 0.4 29.79 0.4 30.05 1.78 30.05 1.78 31.15 0.4 31.15 0.4 31.41 1.78 31.41 1.78 32.51 0.4 32.51 0.4 32.77 1.78 32.77 1.78 33.87 0.4 33.87 0.4 34.81 1.78 34.81 1.78 35.91 0.4 35.91 0.4 36.85 1.78 36.85 1.78 37.95 0.4 37.95 0.4 38.21 1.78 38.21 1.78 39.31 0.4 39.31 0.4 39.57 1.78 39.57 1.78 40.67 0.4 40.67 0.4 40.93 1.78 40.93 1.78 42.03 0.4 42.03 0.4 42.29 1.78 42.29 1.78 43.39 0.4 43.39 0.4 43.65 1.78 43.65 1.78 44.75 0.4 44.75 0.4 45.01 1.78 45.01 1.78 46.11 0.4 46.11 0.4 46.37 1.78 46.37 1.78 47.47 0.4 47.47 0.4 47.73 1.78 47.73 1.78 48.83 0.4 48.83 0.4 49.09 1.78 49.09 1.78 50.19 0.4 50.19 0.4 50.45 1.78 50.45 1.78 51.55 0.4 51.55 0.4 51.81 1.78 51.81 1.78 52.91 0.4 52.91 0.4 53.17 1.78 53.17 1.78 54.27 0.4 54.27 0.4 54.53 1.78 54.53 1.78 55.63 0.4 55.63 0.4 55.89 1.78 55.89 1.78 56.99 0.4 56.99 0.4 57.25 1.78 57.25 1.78 58.35 0.4 58.35 0.4 58.61 1.78 58.61 1.78 59.71 0.4 59.71 0.4 60.65 1.78 60.65 1.78 61.75 0.4 61.75 0.4 62.69 1.78 62.69 1.78 63.79 0.4 63.79 0.4 64.05 1.78 64.05 1.78 65.15 0.4 65.15 0.4 65.41 1.78 65.41 1.78 66.51 0.4 66.51 0.4 67.45 1.78 67.45 1.78 68.55 0.4 68.55 0.4 68.81 1.78 68.81 1.78 69.91 0.4 69.91 0.4 70.17 1.78 70.17 1.78 71.27 0.4 71.27 0.4 71.53 1.78 71.53 1.78 72.63 0.4 72.63 0.4 72.89 1.78 72.89 1.78 73.99 0.4 73.99 0.4 74.25 1.78 74.25 1.78 75.35 0.4 75.35 0.4 75.61 1.78 75.61 1.78 76.71 0.4 76.71 0.4 76.97 1.78 76.97 1.78 78.07 0.4 78.07 0.4 78.33 1.78 78.33 1.78 79.43 0.4 79.43 0.4 89.21 1.78 89.21 1.78 90.31 0.4 90.31 0.4 97.52 ; - LAYER met2 ; - RECT 80.82 97.735 81.1 98.105 ; - RECT 51.38 97.735 51.66 98.105 ; - RECT 10.9 97.735 11.18 98.105 ; - RECT 15.51 12.42 15.77 12.74 ; - RECT 10.9 10.695 11.18 11.065 ; - RECT 56.91 1.54 57.17 1.86 ; - RECT 51.85 1.54 52.11 1.86 ; - RECT 48.17 1.54 48.43 1.86 ; - RECT 80.82 -0.185 81.1 0.185 ; - RECT 51.38 -0.185 51.66 0.185 ; - POLYGON 91.72 97.64 91.72 0.28 82.23 0.28 82.23 1.64 81.53 1.64 81.53 0.28 74.87 0.28 74.87 1.64 74.17 1.64 74.17 0.28 73.95 0.28 73.95 1.64 73.25 1.64 73.25 0.28 73.03 0.28 73.03 1.64 72.33 1.64 72.33 0.28 72.11 0.28 72.11 1.64 71.41 1.64 71.41 0.28 71.19 0.28 71.19 1.64 70.49 1.64 70.49 0.28 69.81 0.28 69.81 1.64 69.11 1.64 69.11 0.28 68.89 0.28 68.89 1.64 68.19 1.64 68.19 0.28 67.51 0.28 67.51 1.64 66.81 1.64 66.81 0.28 66.59 0.28 66.59 1.64 65.89 1.64 65.89 0.28 65.21 0.28 65.21 1.64 64.51 1.64 64.51 0.28 64.29 0.28 64.29 1.64 63.59 1.64 63.59 0.28 63.37 0.28 63.37 1.64 62.67 1.64 62.67 0.28 62.45 0.28 62.45 1.64 61.75 1.64 61.75 0.28 61.53 0.28 61.53 1.64 60.83 1.64 60.83 0.28 60.61 0.28 60.61 1.64 59.91 1.64 59.91 0.28 59.23 0.28 59.23 1.64 58.53 1.64 58.53 0.28 57.85 0.28 57.85 1.64 57.15 1.64 57.15 0.28 56.93 0.28 56.93 1.64 56.23 1.64 56.23 0.28 56.01 0.28 56.01 1.64 55.31 1.64 55.31 0.28 54.63 0.28 54.63 1.64 53.93 1.64 53.93 0.28 53.71 0.28 53.71 1.64 53.01 1.64 53.01 0.28 52.79 0.28 52.79 1.64 52.09 1.64 52.09 0.28 50.95 0.28 50.95 1.64 50.25 1.64 50.25 0.28 49.57 0.28 49.57 1.64 48.87 1.64 48.87 0.28 48.19 0.28 48.19 1.64 47.49 1.64 47.49 0.28 47.27 0.28 47.27 1.64 46.57 1.64 46.57 0.28 45.89 0.28 45.89 1.64 45.19 1.64 45.19 0.28 44.51 0.28 44.51 1.64 43.81 1.64 43.81 0.28 43.13 0.28 43.13 1.64 42.43 1.64 42.43 0.28 42.21 0.28 42.21 1.64 41.51 1.64 41.51 0.28 41.29 0.28 41.29 1.64 40.59 1.64 40.59 0.28 40.37 0.28 40.37 1.64 39.67 1.64 39.67 0.28 39.45 0.28 39.45 1.64 38.75 1.64 38.75 0.28 38.53 0.28 38.53 1.64 37.83 1.64 37.83 0.28 37.61 0.28 37.61 1.64 36.91 1.64 36.91 0.28 34.39 0.28 34.39 1.64 33.69 1.64 33.69 0.28 32.55 0.28 32.55 1.64 31.85 1.64 31.85 0.28 31.63 0.28 31.63 1.64 30.93 1.64 30.93 0.28 28.41 0.28 28.41 1.64 27.71 1.64 27.71 0.28 26.04 0.28 26.04 11.16 18.75 11.16 18.75 12.52 18.05 12.52 18.05 11.16 16.45 11.16 16.45 12.52 15.75 12.52 15.75 11.16 15.53 11.16 15.53 12.52 14.83 12.52 14.83 11.16 13.23 11.16 13.23 12.52 12.53 12.52 12.53 11.16 12.31 11.16 12.31 12.52 11.61 12.52 11.61 11.16 10.47 11.16 10.47 12.52 9.77 12.52 9.77 11.16 9.55 11.16 9.55 12.52 8.85 12.52 8.85 11.16 8.63 11.16 8.63 12.52 7.93 12.52 7.93 11.16 7.71 11.16 7.71 12.52 7.01 12.52 7.01 11.16 6.79 11.16 6.79 12.52 6.09 12.52 6.09 11.16 5.41 11.16 5.41 12.52 4.71 12.52 4.71 11.16 4.49 11.16 4.49 12.52 3.79 12.52 3.79 11.16 0.28 11.16 0.28 97.64 1.95 97.64 1.95 96.28 2.65 96.28 2.65 97.64 30.93 97.64 30.93 96.28 31.63 96.28 31.63 97.64 ; - LAYER met4 ; - POLYGON 91.6 97.52 91.6 0.4 81.66 0.4 81.66 1 80.26 1 80.26 0.4 66.94 0.4 66.94 1 65.54 1 65.54 0.4 59.43 0.4 59.43 1.76 58.33 1.76 58.33 0.4 57.59 0.4 57.59 1.76 56.49 1.76 56.49 0.4 52.22 0.4 52.22 1 50.82 1 50.82 0.4 37.5 0.4 37.5 1 36.1 1 36.1 0.4 26.16 0.4 26.16 11.28 13.43 11.28 13.43 12.64 12.33 12.64 12.33 11.28 11.74 11.28 11.74 11.88 10.34 11.88 10.34 11.28 9.75 11.28 9.75 12.64 8.65 12.64 8.65 11.28 5.15 11.28 5.15 12.64 4.05 12.64 4.05 11.28 0.4 11.28 0.4 97.52 10.34 97.52 10.34 96.92 11.74 96.92 11.74 97.52 36.1 97.52 36.1 96.92 37.5 96.92 37.5 97.52 50.82 97.52 50.82 96.92 52.22 96.92 52.22 97.52 65.54 97.52 65.54 96.92 66.94 96.92 66.94 97.52 80.26 97.52 80.26 96.92 81.66 96.92 81.66 97.52 ; - LAYER met5 ; - POLYGON 90.4 96.32 90.4 88.2 87.2 88.2 87.2 81.8 90.4 81.8 90.4 67.8 87.2 67.8 87.2 61.4 90.4 61.4 90.4 47.4 87.2 47.4 87.2 41 90.4 41 90.4 27 87.2 27 87.2 20.6 90.4 20.6 90.4 1.6 27.36 1.6 27.36 12.48 1.6 12.48 1.6 20.6 4.8 20.6 4.8 27 1.6 27 1.6 41 4.8 41 4.8 47.4 1.6 47.4 1.6 61.4 4.8 61.4 4.8 67.8 1.6 67.8 1.6 81.8 4.8 81.8 4.8 88.2 1.6 88.2 1.6 96.32 ; - LAYER met1 ; - POLYGON 91.72 97.4 91.72 95.72 91.24 95.72 91.24 94.68 91.72 94.68 91.72 93 91.24 93 91.24 91.96 91.72 91.96 91.72 90.28 91.24 90.28 91.24 89.24 91.72 89.24 91.72 87.56 91.24 87.56 91.24 86.52 91.72 86.52 91.72 84.84 91.24 84.84 91.24 83.8 91.72 83.8 91.72 82.12 91.24 82.12 91.24 81.08 91.72 81.08 91.72 79.4 91.24 79.4 91.24 78.36 91.72 78.36 91.72 76.68 91.24 76.68 91.24 75.64 91.72 75.64 91.72 73.96 91.24 73.96 91.24 72.92 91.72 72.92 91.72 71.24 91.24 71.24 91.24 70.2 91.72 70.2 91.72 68.52 91.24 68.52 91.24 67.48 91.72 67.48 91.72 65.8 91.24 65.8 91.24 64.76 91.72 64.76 91.72 63.08 91.24 63.08 91.24 62.04 91.72 62.04 91.72 60.36 91.24 60.36 91.24 59.32 91.72 59.32 91.72 57.64 91.24 57.64 91.24 56.6 91.72 56.6 91.72 54.92 91.24 54.92 91.24 53.88 91.72 53.88 91.72 52.2 91.24 52.2 91.24 51.16 91.72 51.16 91.72 49.48 91.24 49.48 91.24 48.44 91.72 48.44 91.72 46.76 91.24 46.76 91.24 45.72 91.72 45.72 91.72 44.04 91.24 44.04 91.24 43 91.72 43 91.72 41.32 91.24 41.32 91.24 40.28 91.72 40.28 91.72 38.6 91.24 38.6 91.24 37.56 91.72 37.56 91.72 35.88 91.24 35.88 91.24 34.84 91.72 34.84 91.72 33.16 91.24 33.16 91.24 32.12 91.72 32.12 91.72 30.44 91.24 30.44 91.24 29.4 91.72 29.4 91.72 27.72 91.24 27.72 91.24 26.68 91.72 26.68 91.72 25 91.24 25 91.24 23.96 91.72 23.96 91.72 22.28 91.24 22.28 91.24 21.24 91.72 21.24 91.72 19.56 91.24 19.56 91.24 18.52 91.72 18.52 91.72 16.84 91.24 16.84 91.24 15.8 91.72 15.8 91.72 14.12 91.24 14.12 91.24 13.08 91.72 13.08 91.72 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 0.76 81.08 0.76 82.12 0.28 82.12 0.28 83.8 0.76 83.8 0.76 84.84 0.28 84.84 0.28 86.52 0.76 86.52 0.76 87.56 0.28 87.56 0.28 89.24 0.76 89.24 0.76 90.28 0.28 90.28 0.28 91.96 0.76 91.96 0.76 93 0.28 93 0.28 94.68 0.76 94.68 0.76 95.72 0.28 95.72 0.28 97.4 ; - POLYGON 91.72 10.36 91.72 8.68 91.24 8.68 91.24 7.64 91.72 7.64 91.72 5.96 91.24 5.96 91.24 4.92 91.72 4.92 91.72 3.24 91.24 3.24 91.24 2.2 91.72 2.2 91.72 0.52 26.04 0.52 26.04 2.2 26.52 2.2 26.52 3.24 26.04 3.24 26.04 4.92 26.52 4.92 26.52 5.96 26.04 5.96 26.04 7.64 26.52 7.64 26.52 8.68 26.04 8.68 26.04 10.36 ; - LAYER li1 ; - POLYGON 91.83 97.75 91.83 0.17 25.93 0.17 25.93 11.05 0.17 11.05 0.17 97.75 ; - LAYER mcon ; - RECT 91.685 97.835 91.855 98.005 ; - RECT 91.225 97.835 91.395 98.005 ; - RECT 90.765 97.835 90.935 98.005 ; - RECT 90.305 97.835 90.475 98.005 ; - RECT 89.845 97.835 90.015 98.005 ; - RECT 89.385 97.835 89.555 98.005 ; - RECT 88.925 97.835 89.095 98.005 ; - RECT 88.465 97.835 88.635 98.005 ; - RECT 88.005 97.835 88.175 98.005 ; - RECT 87.545 97.835 87.715 98.005 ; - RECT 87.085 97.835 87.255 98.005 ; - RECT 86.625 97.835 86.795 98.005 ; - RECT 86.165 97.835 86.335 98.005 ; - RECT 85.705 97.835 85.875 98.005 ; - RECT 85.245 97.835 85.415 98.005 ; - RECT 84.785 97.835 84.955 98.005 ; - RECT 84.325 97.835 84.495 98.005 ; - RECT 83.865 97.835 84.035 98.005 ; - RECT 83.405 97.835 83.575 98.005 ; - RECT 82.945 97.835 83.115 98.005 ; - RECT 82.485 97.835 82.655 98.005 ; - RECT 82.025 97.835 82.195 98.005 ; - RECT 81.565 97.835 81.735 98.005 ; - RECT 81.105 97.835 81.275 98.005 ; - RECT 80.645 97.835 80.815 98.005 ; - RECT 80.185 97.835 80.355 98.005 ; - RECT 79.725 97.835 79.895 98.005 ; - RECT 79.265 97.835 79.435 98.005 ; - RECT 78.805 97.835 78.975 98.005 ; - RECT 78.345 97.835 78.515 98.005 ; - RECT 77.885 97.835 78.055 98.005 ; - RECT 77.425 97.835 77.595 98.005 ; - RECT 76.965 97.835 77.135 98.005 ; - RECT 76.505 97.835 76.675 98.005 ; - RECT 76.045 97.835 76.215 98.005 ; - RECT 75.585 97.835 75.755 98.005 ; - RECT 75.125 97.835 75.295 98.005 ; - RECT 74.665 97.835 74.835 98.005 ; - RECT 74.205 97.835 74.375 98.005 ; - RECT 73.745 97.835 73.915 98.005 ; - RECT 73.285 97.835 73.455 98.005 ; - RECT 72.825 97.835 72.995 98.005 ; - RECT 72.365 97.835 72.535 98.005 ; - RECT 71.905 97.835 72.075 98.005 ; - RECT 71.445 97.835 71.615 98.005 ; - RECT 70.985 97.835 71.155 98.005 ; - RECT 70.525 97.835 70.695 98.005 ; - RECT 70.065 97.835 70.235 98.005 ; - RECT 69.605 97.835 69.775 98.005 ; - RECT 69.145 97.835 69.315 98.005 ; - RECT 68.685 97.835 68.855 98.005 ; - RECT 68.225 97.835 68.395 98.005 ; - RECT 67.765 97.835 67.935 98.005 ; - RECT 67.305 97.835 67.475 98.005 ; - RECT 66.845 97.835 67.015 98.005 ; - RECT 66.385 97.835 66.555 98.005 ; - RECT 65.925 97.835 66.095 98.005 ; - RECT 65.465 97.835 65.635 98.005 ; - RECT 65.005 97.835 65.175 98.005 ; - RECT 64.545 97.835 64.715 98.005 ; - RECT 64.085 97.835 64.255 98.005 ; - RECT 63.625 97.835 63.795 98.005 ; - RECT 63.165 97.835 63.335 98.005 ; - RECT 62.705 97.835 62.875 98.005 ; - RECT 62.245 97.835 62.415 98.005 ; - RECT 61.785 97.835 61.955 98.005 ; - RECT 61.325 97.835 61.495 98.005 ; - RECT 60.865 97.835 61.035 98.005 ; - RECT 60.405 97.835 60.575 98.005 ; - RECT 59.945 97.835 60.115 98.005 ; - RECT 59.485 97.835 59.655 98.005 ; - RECT 59.025 97.835 59.195 98.005 ; - RECT 58.565 97.835 58.735 98.005 ; - RECT 58.105 97.835 58.275 98.005 ; - RECT 57.645 97.835 57.815 98.005 ; - RECT 57.185 97.835 57.355 98.005 ; - RECT 56.725 97.835 56.895 98.005 ; - RECT 56.265 97.835 56.435 98.005 ; - RECT 55.805 97.835 55.975 98.005 ; - RECT 55.345 97.835 55.515 98.005 ; - RECT 54.885 97.835 55.055 98.005 ; - RECT 54.425 97.835 54.595 98.005 ; - RECT 53.965 97.835 54.135 98.005 ; - RECT 53.505 97.835 53.675 98.005 ; - RECT 53.045 97.835 53.215 98.005 ; - RECT 52.585 97.835 52.755 98.005 ; - RECT 52.125 97.835 52.295 98.005 ; - RECT 51.665 97.835 51.835 98.005 ; - RECT 51.205 97.835 51.375 98.005 ; - RECT 50.745 97.835 50.915 98.005 ; - RECT 50.285 97.835 50.455 98.005 ; - RECT 49.825 97.835 49.995 98.005 ; - RECT 49.365 97.835 49.535 98.005 ; - RECT 48.905 97.835 49.075 98.005 ; - RECT 48.445 97.835 48.615 98.005 ; - RECT 47.985 97.835 48.155 98.005 ; - RECT 47.525 97.835 47.695 98.005 ; - RECT 47.065 97.835 47.235 98.005 ; - RECT 46.605 97.835 46.775 98.005 ; - RECT 46.145 97.835 46.315 98.005 ; - RECT 45.685 97.835 45.855 98.005 ; - RECT 45.225 97.835 45.395 98.005 ; - RECT 44.765 97.835 44.935 98.005 ; - RECT 44.305 97.835 44.475 98.005 ; - RECT 43.845 97.835 44.015 98.005 ; - RECT 43.385 97.835 43.555 98.005 ; - RECT 42.925 97.835 43.095 98.005 ; - RECT 42.465 97.835 42.635 98.005 ; - RECT 42.005 97.835 42.175 98.005 ; - RECT 41.545 97.835 41.715 98.005 ; - RECT 41.085 97.835 41.255 98.005 ; - RECT 40.625 97.835 40.795 98.005 ; - RECT 40.165 97.835 40.335 98.005 ; - RECT 39.705 97.835 39.875 98.005 ; - RECT 39.245 97.835 39.415 98.005 ; - RECT 38.785 97.835 38.955 98.005 ; - RECT 38.325 97.835 38.495 98.005 ; - RECT 37.865 97.835 38.035 98.005 ; - RECT 37.405 97.835 37.575 98.005 ; - RECT 36.945 97.835 37.115 98.005 ; - RECT 36.485 97.835 36.655 98.005 ; - RECT 36.025 97.835 36.195 98.005 ; - RECT 35.565 97.835 35.735 98.005 ; - RECT 35.105 97.835 35.275 98.005 ; - RECT 34.645 97.835 34.815 98.005 ; - RECT 34.185 97.835 34.355 98.005 ; - RECT 33.725 97.835 33.895 98.005 ; - RECT 33.265 97.835 33.435 98.005 ; - RECT 32.805 97.835 32.975 98.005 ; - RECT 32.345 97.835 32.515 98.005 ; - RECT 31.885 97.835 32.055 98.005 ; - RECT 31.425 97.835 31.595 98.005 ; - RECT 30.965 97.835 31.135 98.005 ; - RECT 30.505 97.835 30.675 98.005 ; - RECT 30.045 97.835 30.215 98.005 ; - RECT 29.585 97.835 29.755 98.005 ; - RECT 29.125 97.835 29.295 98.005 ; - RECT 28.665 97.835 28.835 98.005 ; - RECT 28.205 97.835 28.375 98.005 ; - RECT 27.745 97.835 27.915 98.005 ; - RECT 27.285 97.835 27.455 98.005 ; - RECT 26.825 97.835 26.995 98.005 ; - RECT 26.365 97.835 26.535 98.005 ; - RECT 25.905 97.835 26.075 98.005 ; - RECT 25.445 97.835 25.615 98.005 ; - RECT 24.985 97.835 25.155 98.005 ; - RECT 24.525 97.835 24.695 98.005 ; - RECT 24.065 97.835 24.235 98.005 ; - RECT 23.605 97.835 23.775 98.005 ; - RECT 23.145 97.835 23.315 98.005 ; - RECT 22.685 97.835 22.855 98.005 ; - RECT 22.225 97.835 22.395 98.005 ; - RECT 21.765 97.835 21.935 98.005 ; - RECT 21.305 97.835 21.475 98.005 ; - RECT 20.845 97.835 21.015 98.005 ; - RECT 20.385 97.835 20.555 98.005 ; - RECT 19.925 97.835 20.095 98.005 ; - RECT 19.465 97.835 19.635 98.005 ; - RECT 19.005 97.835 19.175 98.005 ; - RECT 18.545 97.835 18.715 98.005 ; - RECT 18.085 97.835 18.255 98.005 ; - RECT 17.625 97.835 17.795 98.005 ; - RECT 17.165 97.835 17.335 98.005 ; - RECT 16.705 97.835 16.875 98.005 ; - RECT 16.245 97.835 16.415 98.005 ; - RECT 15.785 97.835 15.955 98.005 ; - RECT 15.325 97.835 15.495 98.005 ; - RECT 14.865 97.835 15.035 98.005 ; - RECT 14.405 97.835 14.575 98.005 ; - RECT 13.945 97.835 14.115 98.005 ; - RECT 13.485 97.835 13.655 98.005 ; - RECT 13.025 97.835 13.195 98.005 ; - RECT 12.565 97.835 12.735 98.005 ; - RECT 12.105 97.835 12.275 98.005 ; - RECT 11.645 97.835 11.815 98.005 ; - RECT 11.185 97.835 11.355 98.005 ; - RECT 10.725 97.835 10.895 98.005 ; - RECT 10.265 97.835 10.435 98.005 ; - RECT 9.805 97.835 9.975 98.005 ; - RECT 9.345 97.835 9.515 98.005 ; - RECT 8.885 97.835 9.055 98.005 ; - RECT 8.425 97.835 8.595 98.005 ; - RECT 7.965 97.835 8.135 98.005 ; - RECT 7.505 97.835 7.675 98.005 ; - RECT 7.045 97.835 7.215 98.005 ; - RECT 6.585 97.835 6.755 98.005 ; - RECT 6.125 97.835 6.295 98.005 ; - RECT 5.665 97.835 5.835 98.005 ; - RECT 5.205 97.835 5.375 98.005 ; - RECT 4.745 97.835 4.915 98.005 ; - RECT 4.285 97.835 4.455 98.005 ; - RECT 3.825 97.835 3.995 98.005 ; - RECT 3.365 97.835 3.535 98.005 ; - RECT 2.905 97.835 3.075 98.005 ; - RECT 2.445 97.835 2.615 98.005 ; - RECT 1.985 97.835 2.155 98.005 ; - RECT 1.525 97.835 1.695 98.005 ; - RECT 1.065 97.835 1.235 98.005 ; - RECT 0.605 97.835 0.775 98.005 ; - RECT 0.145 97.835 0.315 98.005 ; - RECT 91.685 95.115 91.855 95.285 ; - RECT 91.225 95.115 91.395 95.285 ; - RECT 0.605 95.115 0.775 95.285 ; - RECT 0.145 95.115 0.315 95.285 ; - RECT 91.685 92.395 91.855 92.565 ; - RECT 91.225 92.395 91.395 92.565 ; - RECT 0.605 92.395 0.775 92.565 ; - RECT 0.145 92.395 0.315 92.565 ; - RECT 91.685 89.675 91.855 89.845 ; - RECT 91.225 89.675 91.395 89.845 ; - RECT 0.605 89.675 0.775 89.845 ; - RECT 0.145 89.675 0.315 89.845 ; - RECT 91.685 86.955 91.855 87.125 ; - RECT 91.225 86.955 91.395 87.125 ; - RECT 0.605 86.955 0.775 87.125 ; - RECT 0.145 86.955 0.315 87.125 ; - RECT 91.685 84.235 91.855 84.405 ; - RECT 91.225 84.235 91.395 84.405 ; - RECT 0.605 84.235 0.775 84.405 ; - RECT 0.145 84.235 0.315 84.405 ; - RECT 91.685 81.515 91.855 81.685 ; - RECT 91.225 81.515 91.395 81.685 ; - RECT 0.605 81.515 0.775 81.685 ; - RECT 0.145 81.515 0.315 81.685 ; - RECT 91.685 78.795 91.855 78.965 ; - RECT 91.225 78.795 91.395 78.965 ; - RECT 0.605 78.795 0.775 78.965 ; - RECT 0.145 78.795 0.315 78.965 ; - RECT 91.685 76.075 91.855 76.245 ; - RECT 91.225 76.075 91.395 76.245 ; - RECT 0.605 76.075 0.775 76.245 ; - RECT 0.145 76.075 0.315 76.245 ; - RECT 91.685 73.355 91.855 73.525 ; - RECT 91.225 73.355 91.395 73.525 ; - RECT 0.605 73.355 0.775 73.525 ; - RECT 0.145 73.355 0.315 73.525 ; - RECT 91.685 70.635 91.855 70.805 ; - RECT 91.225 70.635 91.395 70.805 ; - RECT 0.605 70.635 0.775 70.805 ; - RECT 0.145 70.635 0.315 70.805 ; - RECT 91.685 67.915 91.855 68.085 ; - RECT 91.225 67.915 91.395 68.085 ; - RECT 0.605 67.915 0.775 68.085 ; - RECT 0.145 67.915 0.315 68.085 ; - RECT 91.685 65.195 91.855 65.365 ; - RECT 91.225 65.195 91.395 65.365 ; - RECT 0.605 65.195 0.775 65.365 ; - RECT 0.145 65.195 0.315 65.365 ; - RECT 91.685 62.475 91.855 62.645 ; - RECT 91.225 62.475 91.395 62.645 ; - RECT 0.605 62.475 0.775 62.645 ; - RECT 0.145 62.475 0.315 62.645 ; - RECT 91.685 59.755 91.855 59.925 ; - RECT 91.225 59.755 91.395 59.925 ; - RECT 0.605 59.755 0.775 59.925 ; - RECT 0.145 59.755 0.315 59.925 ; - RECT 91.685 57.035 91.855 57.205 ; - RECT 91.225 57.035 91.395 57.205 ; - RECT 0.605 57.035 0.775 57.205 ; - RECT 0.145 57.035 0.315 57.205 ; - RECT 91.685 54.315 91.855 54.485 ; - RECT 91.225 54.315 91.395 54.485 ; - RECT 0.605 54.315 0.775 54.485 ; - RECT 0.145 54.315 0.315 54.485 ; - RECT 91.685 51.595 91.855 51.765 ; - RECT 91.225 51.595 91.395 51.765 ; - RECT 0.605 51.595 0.775 51.765 ; - RECT 0.145 51.595 0.315 51.765 ; - RECT 91.685 48.875 91.855 49.045 ; - RECT 91.225 48.875 91.395 49.045 ; - RECT 0.605 48.875 0.775 49.045 ; - RECT 0.145 48.875 0.315 49.045 ; - RECT 91.685 46.155 91.855 46.325 ; - RECT 91.225 46.155 91.395 46.325 ; - RECT 0.605 46.155 0.775 46.325 ; - RECT 0.145 46.155 0.315 46.325 ; - RECT 91.685 43.435 91.855 43.605 ; - RECT 91.225 43.435 91.395 43.605 ; - RECT 0.605 43.435 0.775 43.605 ; - RECT 0.145 43.435 0.315 43.605 ; - RECT 91.685 40.715 91.855 40.885 ; - RECT 91.225 40.715 91.395 40.885 ; - RECT 0.605 40.715 0.775 40.885 ; - RECT 0.145 40.715 0.315 40.885 ; - RECT 91.685 37.995 91.855 38.165 ; - RECT 91.225 37.995 91.395 38.165 ; - RECT 0.605 37.995 0.775 38.165 ; - RECT 0.145 37.995 0.315 38.165 ; - RECT 91.685 35.275 91.855 35.445 ; - RECT 91.225 35.275 91.395 35.445 ; - RECT 0.605 35.275 0.775 35.445 ; - RECT 0.145 35.275 0.315 35.445 ; - RECT 91.685 32.555 91.855 32.725 ; - RECT 91.225 32.555 91.395 32.725 ; - RECT 0.605 32.555 0.775 32.725 ; - RECT 0.145 32.555 0.315 32.725 ; - RECT 91.685 29.835 91.855 30.005 ; - RECT 91.225 29.835 91.395 30.005 ; - RECT 0.605 29.835 0.775 30.005 ; - RECT 0.145 29.835 0.315 30.005 ; - RECT 91.685 27.115 91.855 27.285 ; - RECT 91.225 27.115 91.395 27.285 ; - RECT 0.605 27.115 0.775 27.285 ; - RECT 0.145 27.115 0.315 27.285 ; - RECT 91.685 24.395 91.855 24.565 ; - RECT 91.225 24.395 91.395 24.565 ; - RECT 0.605 24.395 0.775 24.565 ; - RECT 0.145 24.395 0.315 24.565 ; - RECT 91.685 21.675 91.855 21.845 ; - RECT 91.225 21.675 91.395 21.845 ; - RECT 0.605 21.675 0.775 21.845 ; - RECT 0.145 21.675 0.315 21.845 ; - RECT 91.685 18.955 91.855 19.125 ; - RECT 91.225 18.955 91.395 19.125 ; - RECT 0.605 18.955 0.775 19.125 ; - RECT 0.145 18.955 0.315 19.125 ; - RECT 91.685 16.235 91.855 16.405 ; - RECT 91.225 16.235 91.395 16.405 ; - RECT 0.605 16.235 0.775 16.405 ; - RECT 0.145 16.235 0.315 16.405 ; - RECT 91.685 13.515 91.855 13.685 ; - RECT 91.225 13.515 91.395 13.685 ; - RECT 0.605 13.515 0.775 13.685 ; - RECT 0.145 13.515 0.315 13.685 ; - RECT 91.685 10.795 91.855 10.965 ; - RECT 91.225 10.795 91.395 10.965 ; - RECT 90.765 10.795 90.935 10.965 ; - RECT 90.305 10.795 90.475 10.965 ; - RECT 89.845 10.795 90.015 10.965 ; - RECT 89.385 10.795 89.555 10.965 ; - RECT 88.925 10.795 89.095 10.965 ; - RECT 88.465 10.795 88.635 10.965 ; - RECT 88.005 10.795 88.175 10.965 ; - RECT 87.545 10.795 87.715 10.965 ; - RECT 87.085 10.795 87.255 10.965 ; - RECT 86.625 10.795 86.795 10.965 ; - RECT 86.165 10.795 86.335 10.965 ; - RECT 85.705 10.795 85.875 10.965 ; - RECT 85.245 10.795 85.415 10.965 ; - RECT 84.785 10.795 84.955 10.965 ; - RECT 84.325 10.795 84.495 10.965 ; - RECT 83.865 10.795 84.035 10.965 ; - RECT 83.405 10.795 83.575 10.965 ; - RECT 82.945 10.795 83.115 10.965 ; - RECT 82.485 10.795 82.655 10.965 ; - RECT 82.025 10.795 82.195 10.965 ; - RECT 81.565 10.795 81.735 10.965 ; - RECT 81.105 10.795 81.275 10.965 ; - RECT 80.645 10.795 80.815 10.965 ; - RECT 80.185 10.795 80.355 10.965 ; - RECT 79.725 10.795 79.895 10.965 ; - RECT 79.265 10.795 79.435 10.965 ; - RECT 78.805 10.795 78.975 10.965 ; - RECT 78.345 10.795 78.515 10.965 ; - RECT 77.885 10.795 78.055 10.965 ; - RECT 77.425 10.795 77.595 10.965 ; - RECT 76.965 10.795 77.135 10.965 ; - RECT 76.505 10.795 76.675 10.965 ; - RECT 76.045 10.795 76.215 10.965 ; - RECT 75.585 10.795 75.755 10.965 ; - RECT 75.125 10.795 75.295 10.965 ; - RECT 74.665 10.795 74.835 10.965 ; - RECT 74.205 10.795 74.375 10.965 ; - RECT 73.745 10.795 73.915 10.965 ; - RECT 73.285 10.795 73.455 10.965 ; - RECT 72.825 10.795 72.995 10.965 ; - RECT 72.365 10.795 72.535 10.965 ; - RECT 71.905 10.795 72.075 10.965 ; - RECT 71.445 10.795 71.615 10.965 ; - RECT 70.985 10.795 71.155 10.965 ; - RECT 70.525 10.795 70.695 10.965 ; - RECT 70.065 10.795 70.235 10.965 ; - RECT 69.605 10.795 69.775 10.965 ; - RECT 69.145 10.795 69.315 10.965 ; - RECT 68.685 10.795 68.855 10.965 ; - RECT 68.225 10.795 68.395 10.965 ; - RECT 67.765 10.795 67.935 10.965 ; - RECT 67.305 10.795 67.475 10.965 ; - RECT 66.845 10.795 67.015 10.965 ; - RECT 66.385 10.795 66.555 10.965 ; - RECT 65.925 10.795 66.095 10.965 ; - RECT 65.465 10.795 65.635 10.965 ; - RECT 65.005 10.795 65.175 10.965 ; - RECT 64.545 10.795 64.715 10.965 ; - RECT 64.085 10.795 64.255 10.965 ; - RECT 63.625 10.795 63.795 10.965 ; - RECT 63.165 10.795 63.335 10.965 ; - RECT 62.705 10.795 62.875 10.965 ; - RECT 62.245 10.795 62.415 10.965 ; - RECT 61.785 10.795 61.955 10.965 ; - RECT 61.325 10.795 61.495 10.965 ; - RECT 60.865 10.795 61.035 10.965 ; - RECT 60.405 10.795 60.575 10.965 ; - RECT 59.945 10.795 60.115 10.965 ; - RECT 59.485 10.795 59.655 10.965 ; - RECT 59.025 10.795 59.195 10.965 ; - RECT 58.565 10.795 58.735 10.965 ; - RECT 58.105 10.795 58.275 10.965 ; - RECT 57.645 10.795 57.815 10.965 ; - RECT 57.185 10.795 57.355 10.965 ; - RECT 56.725 10.795 56.895 10.965 ; - RECT 56.265 10.795 56.435 10.965 ; - RECT 55.805 10.795 55.975 10.965 ; - RECT 55.345 10.795 55.515 10.965 ; - RECT 54.885 10.795 55.055 10.965 ; - RECT 54.425 10.795 54.595 10.965 ; - RECT 53.965 10.795 54.135 10.965 ; - RECT 53.505 10.795 53.675 10.965 ; - RECT 53.045 10.795 53.215 10.965 ; - RECT 52.585 10.795 52.755 10.965 ; - RECT 52.125 10.795 52.295 10.965 ; - RECT 51.665 10.795 51.835 10.965 ; - RECT 51.205 10.795 51.375 10.965 ; - RECT 50.745 10.795 50.915 10.965 ; - RECT 50.285 10.795 50.455 10.965 ; - RECT 49.825 10.795 49.995 10.965 ; - RECT 49.365 10.795 49.535 10.965 ; - RECT 48.905 10.795 49.075 10.965 ; - RECT 48.445 10.795 48.615 10.965 ; - RECT 47.985 10.795 48.155 10.965 ; - RECT 47.525 10.795 47.695 10.965 ; - RECT 47.065 10.795 47.235 10.965 ; - RECT 46.605 10.795 46.775 10.965 ; - RECT 46.145 10.795 46.315 10.965 ; - RECT 45.685 10.795 45.855 10.965 ; - RECT 45.225 10.795 45.395 10.965 ; - RECT 44.765 10.795 44.935 10.965 ; - RECT 44.305 10.795 44.475 10.965 ; - RECT 43.845 10.795 44.015 10.965 ; - RECT 43.385 10.795 43.555 10.965 ; - RECT 42.925 10.795 43.095 10.965 ; - RECT 42.465 10.795 42.635 10.965 ; - RECT 42.005 10.795 42.175 10.965 ; - RECT 41.545 10.795 41.715 10.965 ; - RECT 41.085 10.795 41.255 10.965 ; - RECT 40.625 10.795 40.795 10.965 ; - RECT 40.165 10.795 40.335 10.965 ; - RECT 39.705 10.795 39.875 10.965 ; - RECT 39.245 10.795 39.415 10.965 ; - RECT 38.785 10.795 38.955 10.965 ; - RECT 38.325 10.795 38.495 10.965 ; - RECT 37.865 10.795 38.035 10.965 ; - RECT 37.405 10.795 37.575 10.965 ; - RECT 36.945 10.795 37.115 10.965 ; - RECT 36.485 10.795 36.655 10.965 ; - RECT 36.025 10.795 36.195 10.965 ; - RECT 35.565 10.795 35.735 10.965 ; - RECT 35.105 10.795 35.275 10.965 ; - RECT 34.645 10.795 34.815 10.965 ; - RECT 34.185 10.795 34.355 10.965 ; - RECT 33.725 10.795 33.895 10.965 ; - RECT 33.265 10.795 33.435 10.965 ; - RECT 32.805 10.795 32.975 10.965 ; - RECT 32.345 10.795 32.515 10.965 ; - RECT 31.885 10.795 32.055 10.965 ; - RECT 31.425 10.795 31.595 10.965 ; - RECT 30.965 10.795 31.135 10.965 ; - RECT 30.505 10.795 30.675 10.965 ; - RECT 30.045 10.795 30.215 10.965 ; - RECT 29.585 10.795 29.755 10.965 ; - RECT 29.125 10.795 29.295 10.965 ; - RECT 28.665 10.795 28.835 10.965 ; - RECT 28.205 10.795 28.375 10.965 ; - RECT 27.745 10.795 27.915 10.965 ; - RECT 27.285 10.795 27.455 10.965 ; - RECT 26.825 10.795 26.995 10.965 ; - RECT 26.365 10.795 26.535 10.965 ; - RECT 25.905 10.795 26.075 10.965 ; - RECT 25.445 10.795 25.615 10.965 ; - RECT 24.985 10.795 25.155 10.965 ; - RECT 24.525 10.795 24.695 10.965 ; - RECT 24.065 10.795 24.235 10.965 ; - RECT 23.605 10.795 23.775 10.965 ; - RECT 23.145 10.795 23.315 10.965 ; - RECT 22.685 10.795 22.855 10.965 ; - RECT 22.225 10.795 22.395 10.965 ; - RECT 21.765 10.795 21.935 10.965 ; - RECT 21.305 10.795 21.475 10.965 ; - RECT 20.845 10.795 21.015 10.965 ; - RECT 20.385 10.795 20.555 10.965 ; - RECT 19.925 10.795 20.095 10.965 ; - RECT 19.465 10.795 19.635 10.965 ; - RECT 19.005 10.795 19.175 10.965 ; - RECT 18.545 10.795 18.715 10.965 ; - RECT 18.085 10.795 18.255 10.965 ; - RECT 17.625 10.795 17.795 10.965 ; - RECT 17.165 10.795 17.335 10.965 ; - RECT 16.705 10.795 16.875 10.965 ; - RECT 16.245 10.795 16.415 10.965 ; - RECT 15.785 10.795 15.955 10.965 ; - RECT 15.325 10.795 15.495 10.965 ; - RECT 14.865 10.795 15.035 10.965 ; - RECT 14.405 10.795 14.575 10.965 ; - RECT 13.945 10.795 14.115 10.965 ; - RECT 13.485 10.795 13.655 10.965 ; - RECT 13.025 10.795 13.195 10.965 ; - RECT 12.565 10.795 12.735 10.965 ; - RECT 12.105 10.795 12.275 10.965 ; - RECT 11.645 10.795 11.815 10.965 ; - RECT 11.185 10.795 11.355 10.965 ; - RECT 10.725 10.795 10.895 10.965 ; - RECT 10.265 10.795 10.435 10.965 ; - RECT 9.805 10.795 9.975 10.965 ; - RECT 9.345 10.795 9.515 10.965 ; - RECT 8.885 10.795 9.055 10.965 ; - RECT 8.425 10.795 8.595 10.965 ; - RECT 7.965 10.795 8.135 10.965 ; - RECT 7.505 10.795 7.675 10.965 ; - RECT 7.045 10.795 7.215 10.965 ; - RECT 6.585 10.795 6.755 10.965 ; - RECT 6.125 10.795 6.295 10.965 ; - RECT 5.665 10.795 5.835 10.965 ; - RECT 5.205 10.795 5.375 10.965 ; - RECT 4.745 10.795 4.915 10.965 ; - RECT 4.285 10.795 4.455 10.965 ; - RECT 3.825 10.795 3.995 10.965 ; - RECT 3.365 10.795 3.535 10.965 ; - RECT 2.905 10.795 3.075 10.965 ; - RECT 2.445 10.795 2.615 10.965 ; - RECT 1.985 10.795 2.155 10.965 ; - RECT 1.525 10.795 1.695 10.965 ; - RECT 1.065 10.795 1.235 10.965 ; - RECT 0.605 10.795 0.775 10.965 ; - RECT 0.145 10.795 0.315 10.965 ; - RECT 91.685 8.075 91.855 8.245 ; - RECT 91.225 8.075 91.395 8.245 ; - RECT 26.365 8.075 26.535 8.245 ; - RECT 25.905 8.075 26.075 8.245 ; - RECT 91.685 5.355 91.855 5.525 ; - RECT 91.225 5.355 91.395 5.525 ; - RECT 26.365 5.355 26.535 5.525 ; - RECT 25.905 5.355 26.075 5.525 ; - RECT 91.685 2.635 91.855 2.805 ; - RECT 91.225 2.635 91.395 2.805 ; - RECT 26.365 2.635 26.535 2.805 ; - RECT 25.905 2.635 26.075 2.805 ; - RECT 91.685 -0.085 91.855 0.085 ; - RECT 91.225 -0.085 91.395 0.085 ; - RECT 90.765 -0.085 90.935 0.085 ; - RECT 90.305 -0.085 90.475 0.085 ; - RECT 89.845 -0.085 90.015 0.085 ; - RECT 89.385 -0.085 89.555 0.085 ; - RECT 88.925 -0.085 89.095 0.085 ; - RECT 88.465 -0.085 88.635 0.085 ; - RECT 88.005 -0.085 88.175 0.085 ; - RECT 87.545 -0.085 87.715 0.085 ; - RECT 87.085 -0.085 87.255 0.085 ; - RECT 86.625 -0.085 86.795 0.085 ; - RECT 86.165 -0.085 86.335 0.085 ; - RECT 85.705 -0.085 85.875 0.085 ; - RECT 85.245 -0.085 85.415 0.085 ; - RECT 84.785 -0.085 84.955 0.085 ; - RECT 84.325 -0.085 84.495 0.085 ; - RECT 83.865 -0.085 84.035 0.085 ; - RECT 83.405 -0.085 83.575 0.085 ; - RECT 82.945 -0.085 83.115 0.085 ; - RECT 82.485 -0.085 82.655 0.085 ; - RECT 82.025 -0.085 82.195 0.085 ; - RECT 81.565 -0.085 81.735 0.085 ; - RECT 81.105 -0.085 81.275 0.085 ; - RECT 80.645 -0.085 80.815 0.085 ; - RECT 80.185 -0.085 80.355 0.085 ; - RECT 79.725 -0.085 79.895 0.085 ; - RECT 79.265 -0.085 79.435 0.085 ; - RECT 78.805 -0.085 78.975 0.085 ; - RECT 78.345 -0.085 78.515 0.085 ; - RECT 77.885 -0.085 78.055 0.085 ; - RECT 77.425 -0.085 77.595 0.085 ; - RECT 76.965 -0.085 77.135 0.085 ; - RECT 76.505 -0.085 76.675 0.085 ; - RECT 76.045 -0.085 76.215 0.085 ; - RECT 75.585 -0.085 75.755 0.085 ; - RECT 75.125 -0.085 75.295 0.085 ; - RECT 74.665 -0.085 74.835 0.085 ; - RECT 74.205 -0.085 74.375 0.085 ; - RECT 73.745 -0.085 73.915 0.085 ; - RECT 73.285 -0.085 73.455 0.085 ; - RECT 72.825 -0.085 72.995 0.085 ; - RECT 72.365 -0.085 72.535 0.085 ; - RECT 71.905 -0.085 72.075 0.085 ; - RECT 71.445 -0.085 71.615 0.085 ; - RECT 70.985 -0.085 71.155 0.085 ; - RECT 70.525 -0.085 70.695 0.085 ; - RECT 70.065 -0.085 70.235 0.085 ; - RECT 69.605 -0.085 69.775 0.085 ; - RECT 69.145 -0.085 69.315 0.085 ; - RECT 68.685 -0.085 68.855 0.085 ; - RECT 68.225 -0.085 68.395 0.085 ; - RECT 67.765 -0.085 67.935 0.085 ; - RECT 67.305 -0.085 67.475 0.085 ; - RECT 66.845 -0.085 67.015 0.085 ; - RECT 66.385 -0.085 66.555 0.085 ; - RECT 65.925 -0.085 66.095 0.085 ; - RECT 65.465 -0.085 65.635 0.085 ; - RECT 65.005 -0.085 65.175 0.085 ; - RECT 64.545 -0.085 64.715 0.085 ; - RECT 64.085 -0.085 64.255 0.085 ; - RECT 63.625 -0.085 63.795 0.085 ; - RECT 63.165 -0.085 63.335 0.085 ; - RECT 62.705 -0.085 62.875 0.085 ; - RECT 62.245 -0.085 62.415 0.085 ; - RECT 61.785 -0.085 61.955 0.085 ; - RECT 61.325 -0.085 61.495 0.085 ; - RECT 60.865 -0.085 61.035 0.085 ; - RECT 60.405 -0.085 60.575 0.085 ; - RECT 59.945 -0.085 60.115 0.085 ; - RECT 59.485 -0.085 59.655 0.085 ; - RECT 59.025 -0.085 59.195 0.085 ; - RECT 58.565 -0.085 58.735 0.085 ; - RECT 58.105 -0.085 58.275 0.085 ; - RECT 57.645 -0.085 57.815 0.085 ; - RECT 57.185 -0.085 57.355 0.085 ; - RECT 56.725 -0.085 56.895 0.085 ; - RECT 56.265 -0.085 56.435 0.085 ; - RECT 55.805 -0.085 55.975 0.085 ; - RECT 55.345 -0.085 55.515 0.085 ; - RECT 54.885 -0.085 55.055 0.085 ; - RECT 54.425 -0.085 54.595 0.085 ; - RECT 53.965 -0.085 54.135 0.085 ; - RECT 53.505 -0.085 53.675 0.085 ; - RECT 53.045 -0.085 53.215 0.085 ; - RECT 52.585 -0.085 52.755 0.085 ; - RECT 52.125 -0.085 52.295 0.085 ; - RECT 51.665 -0.085 51.835 0.085 ; - RECT 51.205 -0.085 51.375 0.085 ; - RECT 50.745 -0.085 50.915 0.085 ; - RECT 50.285 -0.085 50.455 0.085 ; - RECT 49.825 -0.085 49.995 0.085 ; - RECT 49.365 -0.085 49.535 0.085 ; - RECT 48.905 -0.085 49.075 0.085 ; - RECT 48.445 -0.085 48.615 0.085 ; - RECT 47.985 -0.085 48.155 0.085 ; - RECT 47.525 -0.085 47.695 0.085 ; - RECT 47.065 -0.085 47.235 0.085 ; - RECT 46.605 -0.085 46.775 0.085 ; - RECT 46.145 -0.085 46.315 0.085 ; - RECT 45.685 -0.085 45.855 0.085 ; - RECT 45.225 -0.085 45.395 0.085 ; - RECT 44.765 -0.085 44.935 0.085 ; - RECT 44.305 -0.085 44.475 0.085 ; - RECT 43.845 -0.085 44.015 0.085 ; - RECT 43.385 -0.085 43.555 0.085 ; - RECT 42.925 -0.085 43.095 0.085 ; - RECT 42.465 -0.085 42.635 0.085 ; - RECT 42.005 -0.085 42.175 0.085 ; - RECT 41.545 -0.085 41.715 0.085 ; - RECT 41.085 -0.085 41.255 0.085 ; - RECT 40.625 -0.085 40.795 0.085 ; - RECT 40.165 -0.085 40.335 0.085 ; - RECT 39.705 -0.085 39.875 0.085 ; - RECT 39.245 -0.085 39.415 0.085 ; - RECT 38.785 -0.085 38.955 0.085 ; - RECT 38.325 -0.085 38.495 0.085 ; - RECT 37.865 -0.085 38.035 0.085 ; - RECT 37.405 -0.085 37.575 0.085 ; - RECT 36.945 -0.085 37.115 0.085 ; - RECT 36.485 -0.085 36.655 0.085 ; - RECT 36.025 -0.085 36.195 0.085 ; - RECT 35.565 -0.085 35.735 0.085 ; - RECT 35.105 -0.085 35.275 0.085 ; - RECT 34.645 -0.085 34.815 0.085 ; - RECT 34.185 -0.085 34.355 0.085 ; - RECT 33.725 -0.085 33.895 0.085 ; - RECT 33.265 -0.085 33.435 0.085 ; - RECT 32.805 -0.085 32.975 0.085 ; - RECT 32.345 -0.085 32.515 0.085 ; - RECT 31.885 -0.085 32.055 0.085 ; - RECT 31.425 -0.085 31.595 0.085 ; - RECT 30.965 -0.085 31.135 0.085 ; - RECT 30.505 -0.085 30.675 0.085 ; - RECT 30.045 -0.085 30.215 0.085 ; - RECT 29.585 -0.085 29.755 0.085 ; - RECT 29.125 -0.085 29.295 0.085 ; - RECT 28.665 -0.085 28.835 0.085 ; - RECT 28.205 -0.085 28.375 0.085 ; - RECT 27.745 -0.085 27.915 0.085 ; - RECT 27.285 -0.085 27.455 0.085 ; - RECT 26.825 -0.085 26.995 0.085 ; - RECT 26.365 -0.085 26.535 0.085 ; - RECT 25.905 -0.085 26.075 0.085 ; - LAYER via ; - RECT 80.885 97.845 81.035 97.995 ; - RECT 51.445 97.845 51.595 97.995 ; - RECT 10.965 97.845 11.115 97.995 ; - RECT 31.205 96.145 31.355 96.295 ; - RECT 9.125 12.505 9.275 12.655 ; - RECT 80.885 10.805 81.035 10.955 ; - RECT 51.445 10.805 51.595 10.955 ; - RECT 10.965 10.805 11.115 10.955 ; - RECT 52.365 1.625 52.515 1.775 ; - RECT 49.145 1.625 49.295 1.775 ; - RECT 45.465 1.625 45.615 1.775 ; - RECT 39.945 1.625 40.095 1.775 ; - RECT 80.885 -0.075 81.035 0.075 ; - RECT 51.445 -0.075 51.595 0.075 ; - LAYER via2 ; - RECT 80.86 97.82 81.06 98.02 ; - RECT 51.42 97.82 51.62 98.02 ; - RECT 10.94 97.82 11.14 98.02 ; - RECT 1.28 78.78 1.48 78.98 ; - RECT 1.74 70.62 1.94 70.82 ; - RECT 1.28 37.3 1.48 37.5 ; - RECT 1.28 33.22 1.48 33.42 ; - RECT 1.28 16.22 1.48 16.42 ; - RECT 1.28 14.86 1.48 15.06 ; - RECT 10.94 10.78 11.14 10.98 ; - RECT 80.86 -0.1 81.06 0.1 ; - RECT 51.42 -0.1 51.62 0.1 ; - LAYER via3 ; - RECT 80.86 97.82 81.06 98.02 ; - RECT 51.42 97.82 51.62 98.02 ; - RECT 10.94 97.82 11.14 98.02 ; - RECT 1.74 59.06 1.94 59.26 ; - RECT 10.94 10.78 11.14 10.98 ; - RECT 80.86 -0.1 81.06 0.1 ; - RECT 51.42 -0.1 51.62 0.1 ; - LAYER OVERLAP ; - POLYGON 25.76 0 25.76 10.88 0 10.88 0 97.92 92 97.92 92 0 ; - END -END sb_2__2_ - -END LIBRARY diff --git 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a/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__0__icv_in_design.fm.v b/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__0__icv_in_design.fm.v deleted file mode 100644 index 261fb17..0000000 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__0__icv_in_design.fm.v +++ /dev/null @@ -1,1560 +0,0 @@ -// -// -// -// -// -// -module cbx_1__0__direct_interc_3 ( in , out ) ; -input [0:0] in ; -output [0:0] out ; -endmodule - - -module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( prog_clk , - ccff_head , ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:0] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_24__70 ( .A ( mem_out[0] ) , - .X ( net_net_108 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_163 ( .A ( net_net_108 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__0__EMBEDDED_IO ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , - FPGA_OUT , FPGA_DIR , p_abuf0 ) ; -input SOC_IN ; -output SOC_OUT ; -output SOC_DIR ; -output FPGA_IN ; -input FPGA_OUT ; -input FPGA_DIR ; -output p_abuf0 ; - -assign SOC_OUT = FPGA_OUT ; - -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__68 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 FTB_23__69 ( .A ( FPGA_DIR ) , - .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_82 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; -endmodule - - -module cbx_1__0__logical_tile_io_mode_physical__iopad ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] iopad_outpad ; -input [0:0] ccff_head ; -output [0:0] iopad_inpad ; -output [0:0] ccff_tail ; -output p_abuf0 ; - -wire [0:0] EMBEDDED_IO_0_en ; - -cbx_1__0__EMBEDDED_IO EMBEDDED_IO_0_ ( - .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , - .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , - .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , - .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) ) ; -endmodule - - -module cbx_1__0__logical_tile_io_mode_io_ ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , - ccff_tail , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] io_outpad ; -input [0:0] ccff_head ; -output [0:0] io_inpad ; -output [0:0] ccff_tail ; -output p_abuf0 ; - -cbx_1__0__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , - .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , - .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__0__direct_interc_3 direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; -cbx_1__0__direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( io_outpad ) ) ; -endmodule - - -module cbx_1__0__direct_interc_2 ( in , out ) ; -input [0:0] in ; -output [0:0] out ; -endmodule - - -module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_4 ( prog_clk , - ccff_head , ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:0] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__67 ( .A ( mem_out[0] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__0__EMBEDDED_IO_4 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , - FPGA_OUT , FPGA_DIR , p_abuf0 ) ; -input SOC_IN ; -output SOC_OUT ; -output SOC_DIR ; -output FPGA_IN ; -input FPGA_OUT ; -input FPGA_DIR ; -output p_abuf0 ; - -assign SOC_OUT = FPGA_OUT ; - -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__65 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 FTB_20__66 ( .A ( FPGA_DIR ) , - .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_150 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; -endmodule - - -module cbx_1__0__logical_tile_io_mode_physical__iopad_4 ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] iopad_outpad ; -input [0:0] ccff_head ; -output [0:0] iopad_inpad ; -output [0:0] ccff_tail ; -output p_abuf0 ; - -wire [0:0] EMBEDDED_IO_0_en ; - -cbx_1__0__EMBEDDED_IO_4 EMBEDDED_IO_0_ ( - .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , - .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , - .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , - .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_4 EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) ) ; -endmodule - - -module cbx_1__0__logical_tile_io_mode_io__4 ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , - ccff_tail , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] io_outpad ; -input [0:0] ccff_head ; -output [0:0] io_inpad ; -output [0:0] ccff_tail ; -output p_abuf0 ; - -cbx_1__0__logical_tile_io_mode_physical__iopad_4 logical_tile_io_mode_physical__iopad_0 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , - .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , - .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__0__direct_interc_2 direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; -cbx_1__0__direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( io_outpad ) ) ; -endmodule - - -module cbx_1__0__direct_interc_1 ( in , out ) ; -input [0:0] in ; -output [0:0] out ; -endmodule - - -module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_3 ( prog_clk , - ccff_head , ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:0] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__64 ( .A ( mem_out[0] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__0__EMBEDDED_IO_3 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , - FPGA_OUT , FPGA_DIR , p_abuf0 ) ; -input SOC_IN ; -output SOC_OUT ; -output SOC_DIR ; -output FPGA_IN ; -input FPGA_OUT ; -input FPGA_DIR ; -output p_abuf0 ; - -wire aps_rename_3_ ; - -assign SOC_OUT = FPGA_OUT ; - -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__62 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__63 ( .A ( FPGA_DIR ) , - .X ( aps_rename_3_ ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_78 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_162 ( .A ( aps_rename_3_ ) , - .X ( SOC_DIR ) ) ; -endmodule - - -module cbx_1__0__logical_tile_io_mode_physical__iopad_3 ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] iopad_outpad ; -input [0:0] ccff_head ; -output [0:0] iopad_inpad ; -output [0:0] ccff_tail ; -output p_abuf0 ; - -wire [0:0] EMBEDDED_IO_0_en ; - -cbx_1__0__EMBEDDED_IO_3 EMBEDDED_IO_0_ ( - .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , - .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , - .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , - .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_3 EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) ) ; -endmodule - - -module cbx_1__0__logical_tile_io_mode_io__3 ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , - ccff_tail , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] io_outpad ; -input [0:0] ccff_head ; -output [0:0] io_inpad ; -output [0:0] ccff_tail ; -output p_abuf0 ; - -cbx_1__0__logical_tile_io_mode_physical__iopad_3 logical_tile_io_mode_physical__iopad_0 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , - .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , - .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__0__direct_interc_1 direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; -cbx_1__0__direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( io_outpad ) ) ; -endmodule - - -module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_2 ( prog_clk , - ccff_head , ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:0] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__61 ( .A ( mem_out[0] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__0__EMBEDDED_IO_2 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , - FPGA_OUT , FPGA_DIR , p_abuf0 , p_abuf1 ) ; -input SOC_IN ; -output SOC_OUT ; -output SOC_DIR ; -output FPGA_IN ; -input FPGA_OUT ; -input FPGA_DIR ; -output p_abuf0 ; -output p_abuf1 ; - -assign SOC_OUT = FPGA_OUT ; - -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__59 ( .A ( SOC_IN ) , .X ( p_abuf1 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__60 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_75 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_76 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; -endmodule - - -module cbx_1__0__logical_tile_io_mode_physical__iopad_2 ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , p_abuf0 , p_abuf1 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] iopad_outpad ; -input [0:0] ccff_head ; -output [0:0] iopad_inpad ; -output [0:0] ccff_tail ; -output p_abuf0 ; -output p_abuf1 ; - -wire [0:0] EMBEDDED_IO_0_en ; - -cbx_1__0__EMBEDDED_IO_2 EMBEDDED_IO_0_ ( - .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , - .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , - .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , - .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , - .p_abuf1 ( p_abuf1 ) ) ; -cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_2 EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) ) ; -endmodule - - -module cbx_1__0__logical_tile_io_mode_io__2 ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , - ccff_tail , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] io_outpad ; -input [0:0] ccff_head ; -output [0:0] io_inpad ; -output [0:0] ccff_tail ; -output p_abuf0 ; - -cbx_1__0__logical_tile_io_mode_physical__iopad_2 logical_tile_io_mode_physical__iopad_0 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , - .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , - .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; -cbx_1__0__direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( { p_abuf1 } ) ) ; -cbx_1__0__direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( io_outpad ) ) ; -endmodule - - -module cbx_1__0__direct_interc_0 ( in , out ) ; -input [0:0] in ; -output [0:0] out ; -endmodule - - -module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_1 ( prog_clk , - ccff_head , ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:0] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__58 ( .A ( mem_out[0] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__0__EMBEDDED_IO_1 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , - FPGA_OUT , FPGA_DIR , p_abuf0 ) ; -input SOC_IN ; -output SOC_OUT ; -output SOC_DIR ; -output FPGA_IN ; -input FPGA_OUT ; -input FPGA_DIR ; -output p_abuf0 ; - -assign SOC_OUT = FPGA_OUT ; - -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__56 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__57 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_141 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; -endmodule - - -module cbx_1__0__logical_tile_io_mode_physical__iopad_1 ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] iopad_outpad ; -input [0:0] ccff_head ; -output [0:0] iopad_inpad ; -output [0:0] ccff_tail ; -output p_abuf0 ; - -wire [0:0] EMBEDDED_IO_0_en ; - -cbx_1__0__EMBEDDED_IO_1 EMBEDDED_IO_0_ ( - .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , - .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , - .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , - .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_1 EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) ) ; -endmodule - - -module cbx_1__0__logical_tile_io_mode_io__1 ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , - ccff_tail , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] io_outpad ; -input [0:0] ccff_head ; -output [0:0] io_inpad ; -output [0:0] ccff_tail ; -output p_abuf0 ; - -cbx_1__0__logical_tile_io_mode_physical__iopad_1 logical_tile_io_mode_physical__iopad_0 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , - .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , - .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__0__direct_interc_0 direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; -cbx_1__0__direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( io_outpad ) ) ; -endmodule - - -module cbx_1__0__direct_interc ( in , out ) ; -input [0:0] in ; -output [0:0] out ; - -assign out[0] = in[0] ; -endmodule - - -module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_0 ( prog_clk , - ccff_head , ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:0] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__55 ( .A ( mem_out[0] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__0__EMBEDDED_IO_0 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , - FPGA_OUT , FPGA_DIR , p_abuf0 , p_abuf1 ) ; -input SOC_IN ; -output SOC_OUT ; -output SOC_DIR ; -output FPGA_IN ; -input FPGA_OUT ; -input FPGA_DIR ; -output p_abuf0 ; -output p_abuf1 ; - -assign SOC_OUT = FPGA_OUT ; - -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__53 ( .A ( SOC_IN ) , .X ( p_abuf1 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__54 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_71 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_146 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; -endmodule - - -module cbx_1__0__logical_tile_io_mode_physical__iopad_0 ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , p_abuf0 , p_abuf1 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] iopad_outpad ; -input [0:0] ccff_head ; -output [0:0] iopad_inpad ; -output [0:0] ccff_tail ; -output p_abuf0 ; -output p_abuf1 ; - -wire [0:0] EMBEDDED_IO_0_en ; - -cbx_1__0__EMBEDDED_IO_0 EMBEDDED_IO_0_ ( - .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , - .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , - .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , - .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , - .p_abuf1 ( p_abuf1 ) ) ; -cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_0 EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) ) ; -endmodule - - -module cbx_1__0__logical_tile_io_mode_io__0 ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , - ccff_tail , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] io_outpad ; -input [0:0] ccff_head ; -output [0:0] io_inpad ; -output [0:0] ccff_tail ; -output p_abuf0 ; - -cbx_1__0__logical_tile_io_mode_physical__iopad_0 logical_tile_io_mode_physical__iopad_0 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , - .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , - .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; -cbx_1__0__direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( { p_abuf1 } ) ) ; -cbx_1__0__direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( io_outpad ) ) ; -endmodule - - -module cbx_1__0__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__52 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__0__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__51 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__0__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__50 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__0__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__49 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__0__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__48 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__0__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__47 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__0__const1 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cbx_1__0__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; - -cbx_1__0__const1 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; -endmodule - - -module cbx_1__0__const1_4 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cbx_1__0__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -cbx_1__0__const1_4 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cbx_1__0__const1_3 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cbx_1__0__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -cbx_1__0__const1_3 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cbx_1__0__const1_2 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cbx_1__0__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -cbx_1__0__const1_2 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cbx_1__0__const1_1 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cbx_1__0__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; - -cbx_1__0__const1_1 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; -endmodule - - -module cbx_1__0__const1_0 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cbx_1__0__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -cbx_1__0__const1_0 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cbx_1__0_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , - chanx_left_out , chanx_right_out , bottom_grid_pin_0_ , - bottom_grid_pin_2_ , bottom_grid_pin_4_ , bottom_grid_pin_6_ , - bottom_grid_pin_8_ , bottom_grid_pin_10_ , ccff_tail , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , top_width_0_height_0__pin_0_ , - top_width_0_height_0__pin_2_ , top_width_0_height_0__pin_4_ , - top_width_0_height_0__pin_6_ , top_width_0_height_0__pin_8_ , - top_width_0_height_0__pin_10_ , top_width_0_height_0__pin_1_upper , - top_width_0_height_0__pin_1_lower , top_width_0_height_0__pin_3_upper , - top_width_0_height_0__pin_3_lower , top_width_0_height_0__pin_5_upper , - top_width_0_height_0__pin_5_lower , top_width_0_height_0__pin_7_upper , - top_width_0_height_0__pin_7_lower , top_width_0_height_0__pin_9_upper , - top_width_0_height_0__pin_9_lower , top_width_0_height_0__pin_11_upper , - top_width_0_height_0__pin_11_lower , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , - SC_OUT_BOT , prog_clk__FEEDTHRU_1 ) ; -input [0:0] prog_clk ; -input [0:19] chanx_left_in ; -input [0:19] chanx_right_in ; -input [0:0] ccff_head ; -output [0:19] chanx_left_out ; -output [0:19] chanx_right_out ; -output [0:0] bottom_grid_pin_0_ ; -output [0:0] bottom_grid_pin_2_ ; -output [0:0] bottom_grid_pin_4_ ; -output [0:0] bottom_grid_pin_6_ ; -output [0:0] bottom_grid_pin_8_ ; -output [0:0] bottom_grid_pin_10_ ; -output [0:0] ccff_tail ; -input [0:5] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:5] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:5] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] top_width_0_height_0__pin_0_ ; -input [0:0] top_width_0_height_0__pin_2_ ; -input [0:0] top_width_0_height_0__pin_4_ ; -input [0:0] top_width_0_height_0__pin_6_ ; -input [0:0] top_width_0_height_0__pin_8_ ; -input [0:0] top_width_0_height_0__pin_10_ ; -output [0:0] top_width_0_height_0__pin_1_upper ; -output [0:0] top_width_0_height_0__pin_1_lower ; -output [0:0] top_width_0_height_0__pin_3_upper ; -output [0:0] top_width_0_height_0__pin_3_lower ; -output [0:0] top_width_0_height_0__pin_5_upper ; -output [0:0] top_width_0_height_0__pin_5_lower ; -output [0:0] top_width_0_height_0__pin_7_upper ; -output [0:0] top_width_0_height_0__pin_7_lower ; -output [0:0] top_width_0_height_0__pin_9_upper ; -output [0:0] top_width_0_height_0__pin_9_lower ; -output [0:0] top_width_0_height_0__pin_11_upper ; -output [0:0] top_width_0_height_0__pin_11_lower ; -input SC_IN_TOP ; -input SC_IN_BOT ; -output SC_OUT_TOP ; -output SC_OUT_BOT ; -output [0:0] prog_clk__FEEDTHRU_1 ; - -wire ropt_net_191 ; -wire ropt_net_197 ; -wire ropt_net_179 ; -wire ropt_net_177 ; -wire ropt_net_190 ; -wire ropt_net_178 ; -wire [0:3] mux_top_ipin_0_undriven_sram_inv ; -wire [0:3] mux_top_ipin_1_undriven_sram_inv ; -wire [0:3] mux_top_ipin_2_undriven_sram_inv ; -wire [0:3] mux_top_ipin_3_undriven_sram_inv ; -wire [0:3] mux_top_ipin_4_undriven_sram_inv ; -wire [0:3] mux_top_ipin_5_undriven_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:3] mux_tree_tapbuf_size10_2_sram ; -wire [0:3] mux_tree_tapbuf_size10_3_sram ; -wire [0:3] mux_tree_tapbuf_size10_4_sram ; -wire [0:3] mux_tree_tapbuf_size10_5_sram ; -wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; -wire [0:0] logical_tile_io_mode_io__0_ccff_tail ; -wire [0:0] logical_tile_io_mode_io__1_ccff_tail ; -wire [0:0] logical_tile_io_mode_io__2_ccff_tail ; -wire [0:0] logical_tile_io_mode_io__3_ccff_tail ; -wire [0:0] logical_tile_io_mode_io__4_ccff_tail ; -// - -assign SC_IN_TOP = SC_IN_BOT ; - -cbx_1__0__mux_tree_tapbuf_size10_0 mux_top_ipin_0 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , - chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , - chanx_right_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_top_ipin_0_undriven_sram_inv ) , - .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_174 ) ) ; -cbx_1__0__mux_tree_tapbuf_size10_1 mux_top_ipin_1 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , - chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , - chanx_right_in[17] } ) , - .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_top_ipin_1_undriven_sram_inv ) , - .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_173 ) ) ; -cbx_1__0__mux_tree_tapbuf_size10_2 mux_top_ipin_2 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , - chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , - chanx_right_in[18] } ) , - .sram ( mux_tree_tapbuf_size10_2_sram ) , - .sram_inv ( mux_top_ipin_2_undriven_sram_inv ) , - .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_173 ) ) ; -cbx_1__0__mux_tree_tapbuf_size10_3 mux_top_ipin_3 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , - chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , - chanx_right_in[19] } ) , - .sram ( mux_tree_tapbuf_size10_3_sram ) , - .sram_inv ( mux_top_ipin_3_undriven_sram_inv ) , - .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_173 ) ) ; -cbx_1__0__mux_tree_tapbuf_size10_4 mux_top_ipin_4 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , - chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[14] , - chanx_right_in[14] } ) , - .sram ( mux_tree_tapbuf_size10_4_sram ) , - .sram_inv ( mux_top_ipin_4_undriven_sram_inv ) , - .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_174 ) ) ; -cbx_1__0__mux_tree_tapbuf_size10 mux_top_ipin_5 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , - chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[15] , - chanx_right_in[15] } ) , - .sram ( mux_tree_tapbuf_size10_5_sram ) , - .sram_inv ( mux_top_ipin_5_undriven_sram_inv ) , - .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_174 ) ) ; -cbx_1__0__mux_tree_tapbuf_size10_mem_0 mem_top_ipin_0 ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; -cbx_1__0__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ; -cbx_1__0__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_2 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ; -cbx_1__0__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ; -cbx_1__0__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_4 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ; -cbx_1__0__mux_tree_tapbuf_size10_mem mem_top_ipin_5 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , - .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ; -cbx_1__0__logical_tile_io_mode_io__0 logical_tile_io_mode_io__0 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_196 } ) , - .io_outpad ( top_width_0_height_0__pin_0_ ) , - .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_8_ } ) , - .ccff_tail ( logical_tile_io_mode_io__0_ccff_tail ) , - .p_abuf0 ( ropt_net_191 ) ) ; -cbx_1__0__logical_tile_io_mode_io__1 logical_tile_io_mode_io__1 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[1] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[1] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_200 } ) , - .io_outpad ( top_width_0_height_0__pin_2_ ) , - .ccff_head ( logical_tile_io_mode_io__0_ccff_tail ) , - .io_inpad ( { aps_rename_10_ } ) , - .ccff_tail ( logical_tile_io_mode_io__1_ccff_tail ) , - .p_abuf0 ( ropt_net_197 ) ) ; -cbx_1__0__logical_tile_io_mode_io__2 logical_tile_io_mode_io__2 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[2] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[2] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_198 } ) , - .io_outpad ( top_width_0_height_0__pin_4_ ) , - .ccff_head ( logical_tile_io_mode_io__1_ccff_tail ) , - .io_inpad ( { aps_rename_12_ } ) , - .ccff_tail ( logical_tile_io_mode_io__2_ccff_tail ) , - .p_abuf0 ( ropt_net_179 ) ) ; -cbx_1__0__logical_tile_io_mode_io__3 logical_tile_io_mode_io__3 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[3] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[3] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_193 } ) , - .io_outpad ( top_width_0_height_0__pin_6_ ) , - .ccff_head ( logical_tile_io_mode_io__2_ccff_tail ) , - .io_inpad ( { aps_rename_13_ } ) , - .ccff_tail ( logical_tile_io_mode_io__3_ccff_tail ) , - .p_abuf0 ( ropt_net_177 ) ) ; -cbx_1__0__logical_tile_io_mode_io__4 logical_tile_io_mode_io__4 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[4] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[4] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_201 } ) , - .io_outpad ( top_width_0_height_0__pin_8_ ) , - .ccff_head ( logical_tile_io_mode_io__3_ccff_tail ) , - .io_inpad ( { aps_rename_14_ } ) , - .ccff_tail ( logical_tile_io_mode_io__4_ccff_tail ) , - .p_abuf0 ( ropt_net_190 ) ) ; -cbx_1__0__logical_tile_io_mode_io_ logical_tile_io_mode_io__5 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[5] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[5] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[5] ) , - .io_outpad ( top_width_0_height_0__pin_10_ ) , - .ccff_head ( logical_tile_io_mode_io__4_ccff_tail ) , - .io_inpad ( { aps_rename_15_ } ) , - .ccff_tail ( { ropt_net_212 } ) , - .p_abuf0 ( ropt_net_178 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_166 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_173 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_168 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_174 ) ) ; -sky130_fd_sc_hd__clkbuf_1 prog_clk_0__bip435 ( .A ( prog_clk[0] ) , - .X ( ctsbuf_net_1176 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , - .X ( ropt_net_207 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_177 ) , - .X ( ropt_net_243 ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_326761 ( .A ( ctsbuf_net_1176 ) , - .X ( prog_clk__FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_849 ( .A ( ropt_net_239 ) , - .X ( chanx_left_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_178 ) , - .X ( ropt_net_247 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_266 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chanx_left_in[9] ) , - .X ( ropt_net_208 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_179 ) , - .X ( ropt_net_249 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( ropt_net_180 ) , - .X ( ropt_net_245 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_792 ( .A ( ropt_net_181 ) , - .X ( top_width_0_height_0__pin_11_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( ropt_net_182 ) , - .X ( ropt_net_270 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_244 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__15 ( .A ( chanx_left_in[15] ) , - .X ( ropt_net_222 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_184 ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( chanx_right_in[5] ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_233 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( chanx_right_in[7] ) , - .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_187 ) , - .X ( top_width_0_height_0__pin_3_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , - .X ( ropt_net_219 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_850 ( .A ( ropt_net_240 ) , - .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_188 ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_246 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_190 ) , - .X ( ropt_net_250 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_224 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_191 ) , - .X ( top_width_0_height_0__pin_1_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_192 ) , - .X ( ropt_net_240 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__29 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_221 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__30 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_223 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_851 ( .A ( ropt_net_241 ) , - .X ( chanx_left_out[12] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__32 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_216 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_193 ) , - .X ( ropt_net_262 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_194 ) , - .X ( top_width_0_height_0__pin_1_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_36__35 ( .A ( chanx_right_in[15] ) , - .X ( ropt_net_226 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_37__36 ( .A ( chanx_right_in[16] ) , - .X ( ropt_net_229 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( ropt_net_195 ) , - .X ( ropt_net_264 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_39__38 ( .A ( chanx_right_in[18] ) , - .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_852 ( .A ( ropt_net_242 ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_41__40 ( .A ( aps_rename_8_ ) , - .X ( aps_rename_9_ ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_853 ( .A ( ropt_net_243 ) , - .X ( top_width_0_height_0__pin_7_upper[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_43__42 ( .A ( aps_rename_12_ ) , - .X ( ropt_net_182 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_196 ) , - .X ( ropt_net_254 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_197 ) , - .X ( top_width_0_height_0__pin_3_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_46__45 ( .A ( aps_rename_15_ ) , - .X ( ropt_net_181 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_47__46 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_180 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_85 ( .A ( chanx_left_in[0] ) , - .X ( ropt_net_209 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_86 ( .A ( chanx_left_in[1] ) , - .X ( ropt_net_225 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_87 ( .A ( chanx_left_in[4] ) , - .X ( ropt_net_214 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_88 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_184 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_809 ( .A ( ropt_net_198 ) , - .X ( ropt_net_268 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_90 ( .A ( chanx_left_in[11] ) , - .X ( ropt_net_227 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_810 ( .A ( ropt_net_199 ) , - .X ( ropt_net_265 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_92 ( .A ( chanx_left_in[16] ) , - .X ( ropt_net_213 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_93 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_210 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_94 ( .A ( chanx_right_in[3] ) , - .X ( ropt_net_220 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_854 ( .A ( ropt_net_244 ) , - .X ( chanx_left_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_857 ( .A ( ropt_net_245 ) , - .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_858 ( .A ( ropt_net_246 ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_811 ( .A ( ropt_net_200 ) , - .X ( ropt_net_267 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_860 ( .A ( ropt_net_247 ) , - .X ( top_width_0_height_0__pin_11_upper[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_100 ( .A ( chanx_right_in[14] ) , - .X ( ropt_net_231 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_862 ( .A ( ropt_net_248 ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_812 ( .A ( ropt_net_201 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_103 ( .A ( aps_rename_9_ ) , - .X ( ropt_net_194 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_104 ( .A ( aps_rename_10_ ) , - .X ( ropt_net_187 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_864 ( .A ( ropt_net_249 ) , - .X ( top_width_0_height_0__pin_5_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_865 ( .A ( ropt_net_250 ) , - .X ( top_width_0_height_0__pin_9_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( chanx_right_in[2] ) , - .X ( chanx_left_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_814 ( .A ( chanx_left_in[5] ) , - .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_815 ( .A ( chanx_left_in[7] ) , - .X ( ropt_net_269 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_205 ) , - .X ( ropt_net_256 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_817 ( .A ( chanx_right_in[13] ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_207 ) , - .X ( ropt_net_248 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_208 ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_209 ) , - .X ( ropt_net_260 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_210 ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_211 ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_212 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_213 ) , - .X ( chanx_right_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_131 ( .A ( chanx_left_in[2] ) , - .X ( ropt_net_228 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_866 ( .A ( ropt_net_251 ) , - .X ( chanx_left_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_133 ( .A ( chanx_left_in[10] ) , - .X ( ropt_net_211 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_134 ( .A ( chanx_left_in[12] ) , - .X ( ropt_net_205 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_135 ( .A ( chanx_left_in[13] ) , - .X ( ropt_net_217 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_136 ( .A ( chanx_left_in[19] ) , - .X ( ropt_net_215 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_137 ( .A ( chanx_right_in[0] ) , - .X ( ropt_net_232 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_138 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_218 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( ropt_net_214 ) , - .X ( ropt_net_259 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_144 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_188 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_145 ( .A ( chanx_right_in[19] ) , - .X ( ropt_net_192 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_826 ( .A ( ropt_net_215 ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_867 ( .A ( ropt_net_252 ) , - .X ( chanx_left_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_154 ( .A ( chanx_left_in[14] ) , - .X ( ropt_net_230 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_827 ( .A ( ropt_net_216 ) , - .X ( ropt_net_241 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_217 ) , - .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_829 ( .A ( ropt_net_218 ) , - .X ( ropt_net_252 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_219 ) , - .X ( ropt_net_239 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_220 ) , - .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_160 ( .A ( aps_rename_13_ ) , - .X ( ropt_net_199 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_161 ( .A ( aps_rename_14_ ) , - .X ( ropt_net_195 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_832 ( .A ( ropt_net_221 ) , - .X ( ropt_net_242 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_833 ( .A ( ropt_net_222 ) , - .X ( ropt_net_255 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_834 ( .A ( ropt_net_223 ) , - .X ( ropt_net_257 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_835 ( .A ( ropt_net_224 ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_836 ( .A ( ropt_net_225 ) , - .X ( ropt_net_258 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_838 ( .A ( ropt_net_226 ) , - .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_839 ( .A ( ropt_net_227 ) , - .X ( ropt_net_261 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_840 ( .A ( ropt_net_228 ) , - .X ( chanx_right_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_841 ( .A ( ropt_net_229 ) , - .X ( ropt_net_263 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_843 ( .A ( ropt_net_230 ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_844 ( .A ( ropt_net_231 ) , - .X ( ropt_net_253 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_845 ( .A ( ropt_net_232 ) , - .X ( ropt_net_251 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_847 ( .A ( ropt_net_233 ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_868 ( .A ( ropt_net_253 ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_871 ( .A ( ropt_net_254 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_873 ( .A ( ropt_net_255 ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_874 ( .A ( ropt_net_256 ) , - .X ( chanx_right_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_875 ( .A ( ropt_net_257 ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_876 ( .A ( ropt_net_258 ) , - .X ( chanx_right_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_877 ( .A ( ropt_net_259 ) , - .X ( chanx_right_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_878 ( .A ( ropt_net_260 ) , - .X ( chanx_right_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_879 ( .A ( ropt_net_261 ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_880 ( .A ( ropt_net_262 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_882 ( .A ( ropt_net_263 ) , - .X ( chanx_left_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_889 ( .A ( ropt_net_264 ) , - .X ( top_width_0_height_0__pin_9_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_890 ( .A ( ropt_net_265 ) , - .X ( top_width_0_height_0__pin_7_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_892 ( .A ( ropt_net_266 ) , - .X ( chanx_right_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_893 ( .A ( ropt_net_267 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_894 ( .A ( ropt_net_268 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_896 ( .A ( ropt_net_269 ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_899 ( .A ( ropt_net_270 ) , - .X ( top_width_0_height_0__pin_5_lower[0] ) ) ; -endmodule - - diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__0__icv_in_design.lvs.v b/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__0__icv_in_design.lvs.v deleted file mode 100644 index daa2237..0000000 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__0__icv_in_design.lvs.v +++ /dev/null @@ -1,2648 +0,0 @@ -// -// -// -// -// -// -module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( prog_clk , - ccff_head , ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:0] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_24__70 ( .A ( mem_out[0] ) , - .X ( net_net_108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_163 ( .A ( net_net_108 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__0__EMBEDDED_IO ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , - FPGA_OUT , FPGA_DIR , p_abuf0 , VDD , VSS ) ; -input SOC_IN ; -output SOC_OUT ; -output SOC_DIR ; -output FPGA_IN ; -input FPGA_OUT ; -input FPGA_DIR ; -output p_abuf0 ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -assign SOC_OUT = FPGA_OUT ; - -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__68 ( .A ( SOC_IN ) , .X ( FPGA_IN ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 FTB_23__69 ( .A ( FPGA_DIR ) , - .X ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_82 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__0__logical_tile_io_mode_physical__iopad ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , VDD , VSS , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] iopad_outpad ; -input [0:0] ccff_head ; -output [0:0] iopad_inpad ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; -output p_abuf0 ; - -wire [0:0] EMBEDDED_IO_0_en ; -supply1 VDD ; -supply0 VSS ; - -cbx_1__0__EMBEDDED_IO EMBEDDED_IO_0_ ( - .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , - .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , - .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , - .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -endmodule - - -module cbx_1__0__logical_tile_io_mode_io_ ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , - ccff_tail , VDD , VSS , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] io_outpad ; -input [0:0] ccff_head ; -output [0:0] io_inpad ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; -output p_abuf0 ; - -supply1 VDD ; -supply0 VSS ; - -cbx_1__0__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , - .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , - .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__0__direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( io_outpad ) ) ; -endmodule - - -module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_4 ( prog_clk , - ccff_head , ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:0] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__67 ( .A ( mem_out[0] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__0__EMBEDDED_IO_4 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , - FPGA_OUT , FPGA_DIR , p_abuf0 , VDD , VSS ) ; -input SOC_IN ; -output SOC_OUT ; -output SOC_DIR ; -output FPGA_IN ; -input FPGA_OUT ; -input FPGA_DIR ; -output p_abuf0 ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -assign SOC_OUT = FPGA_OUT ; - -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__65 ( .A ( SOC_IN ) , .X ( FPGA_IN ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 FTB_20__66 ( .A ( FPGA_DIR ) , - .X ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_150 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__0__logical_tile_io_mode_physical__iopad_4 ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , VDD , VSS , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] iopad_outpad ; -input [0:0] ccff_head ; -output [0:0] iopad_inpad ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; -output p_abuf0 ; - -wire [0:0] EMBEDDED_IO_0_en ; -supply1 VDD ; -supply0 VSS ; - -cbx_1__0__EMBEDDED_IO_4 EMBEDDED_IO_0_ ( - .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , - .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , - .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , - .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_4 EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -endmodule - - -module cbx_1__0__logical_tile_io_mode_io__4 ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , - ccff_tail , VDD , VSS , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] io_outpad ; -input [0:0] ccff_head ; -output [0:0] io_inpad ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; -output p_abuf0 ; - -supply1 VDD ; -supply0 VSS ; - -cbx_1__0__logical_tile_io_mode_physical__iopad_4 logical_tile_io_mode_physical__iopad_0 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , - .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , - .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__0__direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( io_outpad ) ) ; -endmodule - - -module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_3 ( prog_clk , - ccff_head , ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:0] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__64 ( .A ( mem_out[0] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__0__EMBEDDED_IO_3 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , - FPGA_OUT , FPGA_DIR , p_abuf0 , VDD , VSS ) ; -input SOC_IN ; -output SOC_OUT ; -output SOC_DIR ; -output FPGA_IN ; -input FPGA_OUT ; -input FPGA_DIR ; -output p_abuf0 ; -input VDD ; -input VSS ; - -supply1 VDD ; -wire aps_rename_3_ ; -supply0 VSS ; - -assign SOC_OUT = FPGA_OUT ; - -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__62 ( .A ( SOC_IN ) , .X ( FPGA_IN ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__63 ( .A ( FPGA_DIR ) , - .X ( aps_rename_3_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_78 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_162 ( .A ( aps_rename_3_ ) , - .X ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__0__logical_tile_io_mode_physical__iopad_3 ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , VDD , VSS , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] iopad_outpad ; -input [0:0] ccff_head ; -output [0:0] iopad_inpad ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; -output p_abuf0 ; - -wire [0:0] EMBEDDED_IO_0_en ; -supply1 VDD ; -supply0 VSS ; - -cbx_1__0__EMBEDDED_IO_3 EMBEDDED_IO_0_ ( - .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , - .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , - .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , - .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_3 EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -endmodule - - -module cbx_1__0__logical_tile_io_mode_io__3 ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , - ccff_tail , VDD , VSS , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] io_outpad ; -input [0:0] ccff_head ; -output [0:0] io_inpad ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; -output p_abuf0 ; - -supply1 VDD ; -supply0 VSS ; - -cbx_1__0__logical_tile_io_mode_physical__iopad_3 logical_tile_io_mode_physical__iopad_0 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , - .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , - .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__0__direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( io_outpad ) ) ; -endmodule - - -module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_2 ( prog_clk , - ccff_head , ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:0] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__61 ( .A ( mem_out[0] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__0__EMBEDDED_IO_2 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , - FPGA_OUT , FPGA_DIR , p_abuf0 , p_abuf1 , VDD , VSS ) ; -input SOC_IN ; -output SOC_OUT ; -output SOC_DIR ; -output FPGA_IN ; -input FPGA_OUT ; -input FPGA_DIR ; -output p_abuf0 ; -output p_abuf1 ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -assign SOC_OUT = FPGA_OUT ; - -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__59 ( .A ( SOC_IN ) , .X ( p_abuf1 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__60 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_75 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_76 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__0__logical_tile_io_mode_physical__iopad_2 ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] iopad_outpad ; -input [0:0] ccff_head ; -output [0:0] iopad_inpad ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; -output p_abuf0 ; -output p_abuf1 ; - -wire [0:0] EMBEDDED_IO_0_en ; -supply1 VDD ; -supply0 VSS ; - -cbx_1__0__EMBEDDED_IO_2 EMBEDDED_IO_0_ ( - .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , - .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , - .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , - .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , - .p_abuf1 ( p_abuf1 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_2 EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -endmodule - - -module cbx_1__0__logical_tile_io_mode_io__2 ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , - ccff_tail , VDD , VSS , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] io_outpad ; -input [0:0] ccff_head ; -output [0:0] io_inpad ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; -output p_abuf0 ; - -supply1 VDD ; -supply0 VSS ; - -cbx_1__0__logical_tile_io_mode_physical__iopad_2 logical_tile_io_mode_physical__iopad_0 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , - .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , - .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; -cbx_1__0__direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( { p_abuf1 } ) ) ; -cbx_1__0__direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( io_outpad ) ) ; -endmodule - - -module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_1 ( prog_clk , - ccff_head , ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:0] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__58 ( .A ( mem_out[0] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__0__EMBEDDED_IO_1 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , - FPGA_OUT , FPGA_DIR , p_abuf0 , VDD , VSS ) ; -input SOC_IN ; -output SOC_OUT ; -output SOC_DIR ; -output FPGA_IN ; -input FPGA_OUT ; -input FPGA_DIR ; -output p_abuf0 ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -assign SOC_OUT = FPGA_OUT ; - -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__56 ( .A ( SOC_IN ) , .X ( FPGA_IN ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__57 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_141 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__0__logical_tile_io_mode_physical__iopad_1 ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , VDD , VSS , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] iopad_outpad ; -input [0:0] ccff_head ; -output [0:0] iopad_inpad ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; -output p_abuf0 ; - -wire [0:0] EMBEDDED_IO_0_en ; -supply1 VDD ; -supply0 VSS ; - -cbx_1__0__EMBEDDED_IO_1 EMBEDDED_IO_0_ ( - .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , - .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , - .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , - .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_1 EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -endmodule - - -module cbx_1__0__logical_tile_io_mode_io__1 ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , - ccff_tail , VDD , VSS , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] io_outpad ; -input [0:0] ccff_head ; -output [0:0] io_inpad ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; -output p_abuf0 ; - -supply1 VDD ; -supply0 VSS ; - -cbx_1__0__logical_tile_io_mode_physical__iopad_1 logical_tile_io_mode_physical__iopad_0 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , - .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , - .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__0__direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( io_outpad ) ) ; -endmodule - - -module cbx_1__0__direct_interc ( in , out ) ; -input [0:0] in ; -output [0:0] out ; - -assign out[0] = in[0] ; -endmodule - - -module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_0 ( prog_clk , - ccff_head , ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:0] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__55 ( .A ( mem_out[0] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__0__EMBEDDED_IO_0 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , - FPGA_OUT , FPGA_DIR , p_abuf0 , p_abuf1 , VDD , VSS ) ; -input SOC_IN ; -output SOC_OUT ; -output SOC_DIR ; -output FPGA_IN ; -input FPGA_OUT ; -input FPGA_DIR ; -output p_abuf0 ; -output p_abuf1 ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -assign SOC_OUT = FPGA_OUT ; - -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__53 ( .A ( SOC_IN ) , .X ( p_abuf1 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__54 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_71 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_146 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__0__logical_tile_io_mode_physical__iopad_0 ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] iopad_outpad ; -input [0:0] ccff_head ; -output [0:0] iopad_inpad ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; -output p_abuf0 ; -output p_abuf1 ; - -wire [0:0] EMBEDDED_IO_0_en ; -supply1 VDD ; -supply0 VSS ; - -cbx_1__0__EMBEDDED_IO_0 EMBEDDED_IO_0_ ( - .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , - .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , - .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , - .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , - .p_abuf1 ( p_abuf1 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_0 EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -endmodule - - -module cbx_1__0__logical_tile_io_mode_io__0 ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , - ccff_tail , VDD , VSS , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] io_outpad ; -input [0:0] ccff_head ; -output [0:0] io_inpad ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; -output p_abuf0 ; - -supply1 VDD ; -supply0 VSS ; - -cbx_1__0__logical_tile_io_mode_physical__iopad_0 logical_tile_io_mode_physical__iopad_0 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , - .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , - .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; -cbx_1__0__direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( { p_abuf1 } ) ) ; -cbx_1__0__direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( io_outpad ) ) ; -endmodule - - -module cbx_1__0__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__52 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__0__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__51 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__0__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__50 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__0__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__49 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__0__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__48 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__0__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__47 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__0__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__0__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__0__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__0__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__0__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__0__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__0_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , - chanx_left_out , chanx_right_out , bottom_grid_pin_0_ , - bottom_grid_pin_2_ , bottom_grid_pin_4_ , bottom_grid_pin_6_ , - bottom_grid_pin_8_ , bottom_grid_pin_10_ , ccff_tail , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , top_width_0_height_0__pin_0_ , - top_width_0_height_0__pin_2_ , top_width_0_height_0__pin_4_ , - top_width_0_height_0__pin_6_ , top_width_0_height_0__pin_8_ , - top_width_0_height_0__pin_10_ , top_width_0_height_0__pin_1_upper , - top_width_0_height_0__pin_1_lower , top_width_0_height_0__pin_3_upper , - top_width_0_height_0__pin_3_lower , top_width_0_height_0__pin_5_upper , - top_width_0_height_0__pin_5_lower , top_width_0_height_0__pin_7_upper , - top_width_0_height_0__pin_7_lower , top_width_0_height_0__pin_9_upper , - top_width_0_height_0__pin_9_lower , top_width_0_height_0__pin_11_upper , - top_width_0_height_0__pin_11_lower , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , - SC_OUT_BOT , VDD , VSS , prog_clk__FEEDTHRU_1 ) ; -input [0:0] prog_clk ; -input [0:19] chanx_left_in ; -input [0:19] chanx_right_in ; -input [0:0] ccff_head ; -output [0:19] chanx_left_out ; -output [0:19] chanx_right_out ; -output [0:0] bottom_grid_pin_0_ ; -output [0:0] bottom_grid_pin_2_ ; -output [0:0] bottom_grid_pin_4_ ; -output [0:0] bottom_grid_pin_6_ ; -output [0:0] bottom_grid_pin_8_ ; -output [0:0] bottom_grid_pin_10_ ; -output [0:0] ccff_tail ; -input [0:5] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:5] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:5] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] top_width_0_height_0__pin_0_ ; -input [0:0] top_width_0_height_0__pin_2_ ; -input [0:0] top_width_0_height_0__pin_4_ ; -input [0:0] top_width_0_height_0__pin_6_ ; -input [0:0] top_width_0_height_0__pin_8_ ; -input [0:0] top_width_0_height_0__pin_10_ ; -output [0:0] top_width_0_height_0__pin_1_upper ; -output [0:0] top_width_0_height_0__pin_1_lower ; -output [0:0] top_width_0_height_0__pin_3_upper ; -output [0:0] top_width_0_height_0__pin_3_lower ; -output [0:0] top_width_0_height_0__pin_5_upper ; -output [0:0] top_width_0_height_0__pin_5_lower ; -output [0:0] top_width_0_height_0__pin_7_upper ; -output [0:0] top_width_0_height_0__pin_7_lower ; -output [0:0] top_width_0_height_0__pin_9_upper ; -output [0:0] top_width_0_height_0__pin_9_lower ; -output [0:0] top_width_0_height_0__pin_11_upper ; -output [0:0] top_width_0_height_0__pin_11_lower ; -input SC_IN_TOP ; -input SC_IN_BOT ; -output SC_OUT_TOP ; -output SC_OUT_BOT ; -input VDD ; -input VSS ; -output [0:0] prog_clk__FEEDTHRU_1 ; - -wire ropt_net_191 ; -wire ropt_net_197 ; -wire ropt_net_179 ; -wire ropt_net_177 ; -wire ropt_net_190 ; -wire ropt_net_178 ; -wire [0:3] mux_top_ipin_0_undriven_sram_inv ; -wire [0:3] mux_top_ipin_1_undriven_sram_inv ; -wire [0:3] mux_top_ipin_2_undriven_sram_inv ; -wire [0:3] mux_top_ipin_3_undriven_sram_inv ; -wire [0:3] mux_top_ipin_4_undriven_sram_inv ; -wire [0:3] mux_top_ipin_5_undriven_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:3] mux_tree_tapbuf_size10_2_sram ; -wire [0:3] mux_tree_tapbuf_size10_3_sram ; -wire [0:3] mux_tree_tapbuf_size10_4_sram ; -wire [0:3] mux_tree_tapbuf_size10_5_sram ; -wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; -wire [0:0] logical_tile_io_mode_io__0_ccff_tail ; -wire [0:0] logical_tile_io_mode_io__1_ccff_tail ; -wire [0:0] logical_tile_io_mode_io__2_ccff_tail ; -wire [0:0] logical_tile_io_mode_io__3_ccff_tail ; -wire [0:0] logical_tile_io_mode_io__4_ccff_tail ; -supply1 VDD ; -supply0 VSS ; -// - -assign SC_IN_TOP = SC_IN_BOT ; - -cbx_1__0__mux_tree_tapbuf_size10_0 mux_top_ipin_0 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , - chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , - chanx_right_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_top_ipin_0_undriven_sram_inv ) , - .out ( bottom_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_174 ) ) ; -cbx_1__0__mux_tree_tapbuf_size10_1 mux_top_ipin_1 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , - chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , - chanx_right_in[17] } ) , - .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_top_ipin_1_undriven_sram_inv ) , - .out ( bottom_grid_pin_2_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_173 ) ) ; -cbx_1__0__mux_tree_tapbuf_size10_2 mux_top_ipin_2 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , - chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , - chanx_right_in[18] } ) , - .sram ( mux_tree_tapbuf_size10_2_sram ) , - .sram_inv ( mux_top_ipin_2_undriven_sram_inv ) , - .out ( bottom_grid_pin_4_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_173 ) ) ; -cbx_1__0__mux_tree_tapbuf_size10_3 mux_top_ipin_3 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , - chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , - chanx_right_in[19] } ) , - .sram ( mux_tree_tapbuf_size10_3_sram ) , - .sram_inv ( mux_top_ipin_3_undriven_sram_inv ) , - .out ( bottom_grid_pin_6_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_173 ) ) ; -cbx_1__0__mux_tree_tapbuf_size10_4 mux_top_ipin_4 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , - chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[14] , - chanx_right_in[14] } ) , - .sram ( mux_tree_tapbuf_size10_4_sram ) , - .sram_inv ( mux_top_ipin_4_undriven_sram_inv ) , - .out ( bottom_grid_pin_8_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_174 ) ) ; -cbx_1__0__mux_tree_tapbuf_size10 mux_top_ipin_5 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , - chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[15] , - chanx_right_in[15] } ) , - .sram ( mux_tree_tapbuf_size10_5_sram ) , - .sram_inv ( mux_top_ipin_5_undriven_sram_inv ) , - .out ( bottom_grid_pin_10_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_174 ) ) ; -cbx_1__0__mux_tree_tapbuf_size10_mem_0 mem_top_ipin_0 ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__0__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__0__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_2 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__0__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__0__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_4 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__0__mux_tree_tapbuf_size10_mem mem_top_ipin_5 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , - .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__0__logical_tile_io_mode_io__0 logical_tile_io_mode_io__0 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_196 } ) , - .io_outpad ( top_width_0_height_0__pin_0_ ) , - .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_8_ } ) , - .ccff_tail ( logical_tile_io_mode_io__0_ccff_tail ) , .VDD ( VDD ) , - .VSS ( VSS ) , .p_abuf0 ( ropt_net_191 ) ) ; -cbx_1__0__logical_tile_io_mode_io__1 logical_tile_io_mode_io__1 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[1] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[1] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_200 } ) , - .io_outpad ( top_width_0_height_0__pin_2_ ) , - .ccff_head ( logical_tile_io_mode_io__0_ccff_tail ) , - .io_inpad ( { aps_rename_10_ } ) , - .ccff_tail ( logical_tile_io_mode_io__1_ccff_tail ) , .VDD ( VDD ) , - .VSS ( VSS ) , .p_abuf0 ( ropt_net_197 ) ) ; -cbx_1__0__logical_tile_io_mode_io__2 logical_tile_io_mode_io__2 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[2] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[2] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_198 } ) , - .io_outpad ( top_width_0_height_0__pin_4_ ) , - .ccff_head ( logical_tile_io_mode_io__1_ccff_tail ) , - .io_inpad ( { aps_rename_12_ } ) , - .ccff_tail ( logical_tile_io_mode_io__2_ccff_tail ) , .VDD ( VDD ) , - .VSS ( VSS ) , .p_abuf0 ( ropt_net_179 ) ) ; -cbx_1__0__logical_tile_io_mode_io__3 logical_tile_io_mode_io__3 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[3] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[3] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_193 } ) , - .io_outpad ( top_width_0_height_0__pin_6_ ) , - .ccff_head ( logical_tile_io_mode_io__2_ccff_tail ) , - .io_inpad ( { aps_rename_13_ } ) , - .ccff_tail ( logical_tile_io_mode_io__3_ccff_tail ) , .VDD ( VDD ) , - .VSS ( VSS ) , .p_abuf0 ( ropt_net_177 ) ) ; -cbx_1__0__logical_tile_io_mode_io__4 logical_tile_io_mode_io__4 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[4] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[4] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_201 } ) , - .io_outpad ( top_width_0_height_0__pin_8_ ) , - .ccff_head ( logical_tile_io_mode_io__3_ccff_tail ) , - .io_inpad ( { aps_rename_14_ } ) , - .ccff_tail ( logical_tile_io_mode_io__4_ccff_tail ) , .VDD ( VDD ) , - .VSS ( VSS ) , .p_abuf0 ( ropt_net_190 ) ) ; -cbx_1__0__logical_tile_io_mode_io_ logical_tile_io_mode_io__5 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[5] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[5] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[5] ) , - .io_outpad ( top_width_0_height_0__pin_10_ ) , - .ccff_head ( logical_tile_io_mode_io__4_ccff_tail ) , - .io_inpad ( { aps_rename_15_ } ) , - .ccff_tail ( { ropt_net_212 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( ropt_net_178 ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1582 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1583 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1584 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1585 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1586 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1587 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1588 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1589 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1590 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1591 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1592 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1593 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1594 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1595 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1596 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1597 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1598 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__conb_1 optlc_166 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_173 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_168 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_174 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__clkbuf_1 prog_clk_0__bip435 ( .A ( prog_clk[0] ) , - .X ( ctsbuf_net_1176 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , - .X ( ropt_net_207 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_177 ) , - .X ( ropt_net_243 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_326761 ( .A ( ctsbuf_net_1176 ) , - .X ( prog_clk__FEEDTHRU_1[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_849 ( .A ( ropt_net_239 ) , - .X ( chanx_left_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_178 ) , - .X ( ropt_net_247 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_266 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chanx_left_in[9] ) , - .X ( ropt_net_208 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_179 ) , - .X ( ropt_net_249 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( ropt_net_180 ) , - .X ( ropt_net_245 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_792 ( .A ( ropt_net_181 ) , - .X ( top_width_0_height_0__pin_11_lower[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( ropt_net_182 ) , - .X ( ropt_net_270 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_244 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__15 ( .A ( chanx_left_in[15] ) , - .X ( ropt_net_222 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_184 ) , - .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( chanx_right_in[5] ) , - .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_233 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( chanx_right_in[7] ) , - .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_187 ) , - .X ( top_width_0_height_0__pin_3_lower[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , - .X ( ropt_net_219 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_850 ( .A ( ropt_net_240 ) , - .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_188 ) , - .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_246 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_190 ) , - .X ( ropt_net_250 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_224 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_191 ) , - .X ( top_width_0_height_0__pin_1_upper[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_192 ) , - .X ( ropt_net_240 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__29 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_221 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__30 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_223 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_851 ( .A ( ropt_net_241 ) , - .X ( chanx_left_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__32 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_216 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_193 ) , - .X ( ropt_net_262 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_194 ) , - .X ( top_width_0_height_0__pin_1_lower[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_36__35 ( .A ( chanx_right_in[15] ) , - .X ( ropt_net_226 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_37__36 ( .A ( chanx_right_in[16] ) , - .X ( ropt_net_229 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( ropt_net_195 ) , - .X ( ropt_net_264 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_39__38 ( .A ( chanx_right_in[18] ) , - .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_852 ( .A ( ropt_net_242 ) , - .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_41__40 ( .A ( aps_rename_8_ ) , - .X ( aps_rename_9_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_853 ( .A ( ropt_net_243 ) , - .X ( top_width_0_height_0__pin_7_upper[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_43__42 ( .A ( aps_rename_12_ ) , - .X ( ropt_net_182 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_196 ) , - .X ( ropt_net_254 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_197 ) , - .X ( top_width_0_height_0__pin_3_upper[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_46__45 ( .A ( aps_rename_15_ ) , - .X ( ropt_net_181 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_47__46 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_180 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_85 ( .A ( chanx_left_in[0] ) , - .X ( ropt_net_209 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_86 ( .A ( chanx_left_in[1] ) , - .X ( ropt_net_225 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_87 ( .A ( chanx_left_in[4] ) , - .X ( ropt_net_214 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_88 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_184 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_809 ( .A ( ropt_net_198 ) , - .X ( ropt_net_268 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_90 ( .A ( chanx_left_in[11] ) , - .X ( ropt_net_227 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_810 ( .A ( ropt_net_199 ) , - .X ( ropt_net_265 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_92 ( .A ( chanx_left_in[16] ) , - .X ( ropt_net_213 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_93 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_210 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_94 ( .A ( chanx_right_in[3] ) , - .X ( ropt_net_220 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_854 ( .A ( ropt_net_244 ) , - .X ( chanx_left_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_857 ( .A ( ropt_net_245 ) , - .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_858 ( .A ( ropt_net_246 ) , - .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_811 ( .A ( ropt_net_200 ) , - .X ( ropt_net_267 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_860 ( .A ( ropt_net_247 ) , - .X ( top_width_0_height_0__pin_11_upper[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_100 ( .A ( chanx_right_in[14] ) , - .X ( ropt_net_231 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_862 ( .A ( ropt_net_248 ) , - .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_812 ( .A ( ropt_net_201 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_103 ( .A ( aps_rename_9_ ) , - .X ( ropt_net_194 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_104 ( .A ( aps_rename_10_ ) , - .X ( ropt_net_187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_864 ( .A ( ropt_net_249 ) , - .X ( top_width_0_height_0__pin_5_upper[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_865 ( .A ( ropt_net_250 ) , - .X ( top_width_0_height_0__pin_9_upper[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( chanx_right_in[2] ) , - .X ( chanx_left_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_814 ( .A ( chanx_left_in[5] ) , - .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_815 ( .A ( chanx_left_in[7] ) , - .X ( ropt_net_269 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_205 ) , - .X ( ropt_net_256 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_817 ( .A ( chanx_right_in[13] ) , - .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_207 ) , - .X ( ropt_net_248 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_208 ) , - .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_209 ) , - .X ( ropt_net_260 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_210 ) , - .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_211 ) , - .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_212 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_213 ) , - .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_131 ( .A ( chanx_left_in[2] ) , - .X ( ropt_net_228 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_866 ( .A ( ropt_net_251 ) , - .X ( chanx_left_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_133 ( .A ( chanx_left_in[10] ) , - .X ( ropt_net_211 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_134 ( .A ( chanx_left_in[12] ) , - .X ( ropt_net_205 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_135 ( .A ( chanx_left_in[13] ) , - .X ( ropt_net_217 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_136 ( .A ( chanx_left_in[19] ) , - .X ( ropt_net_215 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_137 ( .A ( chanx_right_in[0] ) , - .X ( ropt_net_232 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_138 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_218 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( ropt_net_214 ) , - .X ( ropt_net_259 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_144 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_188 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_145 ( .A ( chanx_right_in[19] ) , - .X ( ropt_net_192 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_826 ( .A ( ropt_net_215 ) , - .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_867 ( .A ( ropt_net_252 ) , - .X ( chanx_left_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_154 ( .A ( chanx_left_in[14] ) , - .X ( ropt_net_230 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_827 ( .A ( ropt_net_216 ) , - .X ( ropt_net_241 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_217 ) , - .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_829 ( .A ( ropt_net_218 ) , - .X ( ropt_net_252 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_219 ) , - .X ( ropt_net_239 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_220 ) , - .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_160 ( .A ( aps_rename_13_ ) , - .X ( ropt_net_199 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_161 ( .A ( aps_rename_14_ ) , - .X ( ropt_net_195 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_832 ( .A ( ropt_net_221 ) , - .X ( ropt_net_242 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_833 ( .A ( ropt_net_222 ) , - .X ( ropt_net_255 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_834 ( .A ( ropt_net_223 ) , - .X ( ropt_net_257 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_835 ( .A ( ropt_net_224 ) , - .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_836 ( .A ( ropt_net_225 ) , - .X ( ropt_net_258 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_838 ( .A ( ropt_net_226 ) , - .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_839 ( .A ( ropt_net_227 ) , - .X ( ropt_net_261 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_840 ( .A ( ropt_net_228 ) , - .X ( chanx_right_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_841 ( .A ( ropt_net_229 ) , - .X ( ropt_net_263 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_843 ( .A ( ropt_net_230 ) , - .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_844 ( .A ( ropt_net_231 ) , - .X ( ropt_net_253 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_845 ( .A ( ropt_net_232 ) , - .X ( ropt_net_251 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_847 ( .A ( ropt_net_233 ) , - .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_868 ( .A ( ropt_net_253 ) , - .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_871 ( .A ( ropt_net_254 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_873 ( .A ( ropt_net_255 ) , - .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_874 ( .A ( ropt_net_256 ) , - .X ( chanx_right_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_875 ( .A ( ropt_net_257 ) , - .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_876 ( .A ( ropt_net_258 ) , - .X ( chanx_right_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_877 ( .A ( ropt_net_259 ) , - .X ( chanx_right_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_878 ( .A ( ropt_net_260 ) , - .X ( chanx_right_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_879 ( .A ( ropt_net_261 ) , - .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_880 ( .A ( ropt_net_262 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_882 ( .A ( ropt_net_263 ) , - .X ( chanx_left_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_889 ( .A ( ropt_net_264 ) , - .X ( top_width_0_height_0__pin_9_lower[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_890 ( .A ( ropt_net_265 ) , - .X ( top_width_0_height_0__pin_7_lower[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_892 ( .A ( ropt_net_266 ) , - .X ( chanx_right_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_893 ( .A ( ropt_net_267 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_894 ( .A ( ropt_net_268 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_896 ( .A ( ropt_net_269 ) , - .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_899 ( .A ( ropt_net_270 ) , - .X ( top_width_0_height_0__pin_5_lower[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y0 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y0 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x82800y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x179400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x197800y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x552000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x561200y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x184000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x193200y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x538200y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x119600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x128800y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x538200y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x105800y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x303600y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x345000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x427800y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x506000y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x644000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x165600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x202400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x239200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x276000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x165600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x202400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x239200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x276000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x312800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x349600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x409400y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x496800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x119600y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x197800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x234600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x271400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x386400y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x427800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x455400y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x161000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x197800y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x276000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x464600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x483000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x492200y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x276000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x312800y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x368000y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x446200y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x234600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x253000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x345000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x464600y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x165600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x253000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x289800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x326600y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x460000y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x506000y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x115000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x211600y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x331200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x427800y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x473800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x161000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x197800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x253000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x271400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x358800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x395600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x414000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x151800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x188600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x262200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x322000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x409400y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x455400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x533600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x115000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x151800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x188600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x225400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x262200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x299000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x335800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x372600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x409400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x469200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x487600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x533600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x119600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x128800y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x174800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x211600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x248400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x266800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x317400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x335800y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x161000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x179400y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x294400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x391000y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x156400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x193200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x202400y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x354200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x450800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x119600y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x165600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x202400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x239200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x276000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x312800y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x358800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x395600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x455400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x492200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x501400y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x202400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x220800y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x299000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x317400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x326600y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x547400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x584200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x36800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x156400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x193200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x211600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x220800y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x262200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x299000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x335800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x354200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x363400y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x418600y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x326600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x363400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x418600y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x538200y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x147200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x165600y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x211600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x262200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x294400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x312800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x322000y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x409400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x524400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x533600y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x575000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x230000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x358800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x418600y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x496800y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x225400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x243800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x253000y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x340400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x423200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x441600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x450800y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x496800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x119600y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x262200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x464600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x483000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x492200y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x533600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x579600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x193200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x211600y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x289800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x326600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x363400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x400200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x437000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x473800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x510600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x529000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x538200y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x156400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x538200y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x165600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x243800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x538200y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__0__icv_in_design.pt.v b/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__0__icv_in_design.pt.v deleted file mode 100644 index a7d62d2..0000000 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__0__icv_in_design.pt.v +++ /dev/null @@ -1,1482 +0,0 @@ -// -// -// -// -// -// -module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( prog_clk , - ccff_head , ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:0] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_24__70 ( .A ( mem_out[0] ) , - .X ( net_net_108 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_163 ( .A ( net_net_108 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__0__EMBEDDED_IO ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , - FPGA_OUT , FPGA_DIR , p_abuf0 ) ; -input SOC_IN ; -output SOC_OUT ; -output SOC_DIR ; -output FPGA_IN ; -input FPGA_OUT ; -input FPGA_DIR ; -output p_abuf0 ; - -assign SOC_OUT = FPGA_OUT ; - -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__68 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 FTB_23__69 ( .A ( FPGA_DIR ) , - .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_82 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; -endmodule - - -module cbx_1__0__logical_tile_io_mode_physical__iopad ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] iopad_outpad ; -input [0:0] ccff_head ; -output [0:0] iopad_inpad ; -output [0:0] ccff_tail ; -output p_abuf0 ; - -wire [0:0] EMBEDDED_IO_0_en ; - -cbx_1__0__EMBEDDED_IO EMBEDDED_IO_0_ ( - .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , - .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , - .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , - .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) ) ; -endmodule - - -module cbx_1__0__logical_tile_io_mode_io_ ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , - ccff_tail , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] io_outpad ; -input [0:0] ccff_head ; -output [0:0] io_inpad ; -output [0:0] ccff_tail ; -output p_abuf0 ; - -cbx_1__0__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , - .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , - .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__0__direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( io_outpad ) ) ; -endmodule - - -module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_4 ( prog_clk , - ccff_head , ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:0] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__67 ( .A ( mem_out[0] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__0__EMBEDDED_IO_4 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , - FPGA_OUT , FPGA_DIR , p_abuf0 ) ; -input SOC_IN ; -output SOC_OUT ; -output SOC_DIR ; -output FPGA_IN ; -input FPGA_OUT ; -input FPGA_DIR ; -output p_abuf0 ; - -assign SOC_OUT = FPGA_OUT ; - -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__65 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 FTB_20__66 ( .A ( FPGA_DIR ) , - .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_150 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; -endmodule - - -module cbx_1__0__logical_tile_io_mode_physical__iopad_4 ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] iopad_outpad ; -input [0:0] ccff_head ; -output [0:0] iopad_inpad ; -output [0:0] ccff_tail ; -output p_abuf0 ; - -wire [0:0] EMBEDDED_IO_0_en ; - -cbx_1__0__EMBEDDED_IO_4 EMBEDDED_IO_0_ ( - .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , - .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , - .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , - .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_4 EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) ) ; -endmodule - - -module cbx_1__0__logical_tile_io_mode_io__4 ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , - ccff_tail , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] io_outpad ; -input [0:0] ccff_head ; -output [0:0] io_inpad ; -output [0:0] ccff_tail ; -output p_abuf0 ; - -cbx_1__0__logical_tile_io_mode_physical__iopad_4 logical_tile_io_mode_physical__iopad_0 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , - .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , - .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__0__direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( io_outpad ) ) ; -endmodule - - -module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_3 ( prog_clk , - ccff_head , ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:0] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__64 ( .A ( mem_out[0] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__0__EMBEDDED_IO_3 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , - FPGA_OUT , FPGA_DIR , p_abuf0 ) ; -input SOC_IN ; -output SOC_OUT ; -output SOC_DIR ; -output FPGA_IN ; -input FPGA_OUT ; -input FPGA_DIR ; -output p_abuf0 ; - -wire aps_rename_3_ ; - -assign SOC_OUT = FPGA_OUT ; - -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__62 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__63 ( .A ( FPGA_DIR ) , - .X ( aps_rename_3_ ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_78 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_162 ( .A ( aps_rename_3_ ) , - .X ( SOC_DIR ) ) ; -endmodule - - -module cbx_1__0__logical_tile_io_mode_physical__iopad_3 ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] iopad_outpad ; -input [0:0] ccff_head ; -output [0:0] iopad_inpad ; -output [0:0] ccff_tail ; -output p_abuf0 ; - -wire [0:0] EMBEDDED_IO_0_en ; - -cbx_1__0__EMBEDDED_IO_3 EMBEDDED_IO_0_ ( - .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , - .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , - .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , - .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_3 EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) ) ; -endmodule - - -module cbx_1__0__logical_tile_io_mode_io__3 ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , - ccff_tail , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] io_outpad ; -input [0:0] ccff_head ; -output [0:0] io_inpad ; -output [0:0] ccff_tail ; -output p_abuf0 ; - -cbx_1__0__logical_tile_io_mode_physical__iopad_3 logical_tile_io_mode_physical__iopad_0 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , - .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , - .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__0__direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( io_outpad ) ) ; -endmodule - - -module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_2 ( prog_clk , - ccff_head , ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:0] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__61 ( .A ( mem_out[0] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__0__EMBEDDED_IO_2 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , - FPGA_OUT , FPGA_DIR , p_abuf0 , p_abuf1 ) ; -input SOC_IN ; -output SOC_OUT ; -output SOC_DIR ; -output FPGA_IN ; -input FPGA_OUT ; -input FPGA_DIR ; -output p_abuf0 ; -output p_abuf1 ; - -assign SOC_OUT = FPGA_OUT ; - -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__59 ( .A ( SOC_IN ) , .X ( p_abuf1 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__60 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_75 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_76 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; -endmodule - - -module cbx_1__0__logical_tile_io_mode_physical__iopad_2 ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , p_abuf0 , p_abuf1 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] iopad_outpad ; -input [0:0] ccff_head ; -output [0:0] iopad_inpad ; -output [0:0] ccff_tail ; -output p_abuf0 ; -output p_abuf1 ; - -wire [0:0] EMBEDDED_IO_0_en ; - -cbx_1__0__EMBEDDED_IO_2 EMBEDDED_IO_0_ ( - .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , - .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , - .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , - .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , - .p_abuf1 ( p_abuf1 ) ) ; -cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_2 EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) ) ; -endmodule - - -module cbx_1__0__logical_tile_io_mode_io__2 ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , - ccff_tail , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] io_outpad ; -input [0:0] ccff_head ; -output [0:0] io_inpad ; -output [0:0] ccff_tail ; -output p_abuf0 ; - -cbx_1__0__logical_tile_io_mode_physical__iopad_2 logical_tile_io_mode_physical__iopad_0 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , - .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , - .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; -cbx_1__0__direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( { p_abuf1 } ) ) ; -cbx_1__0__direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( io_outpad ) ) ; -endmodule - - -module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_1 ( prog_clk , - ccff_head , ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:0] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__58 ( .A ( mem_out[0] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__0__EMBEDDED_IO_1 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , - FPGA_OUT , FPGA_DIR , p_abuf0 ) ; -input SOC_IN ; -output SOC_OUT ; -output SOC_DIR ; -output FPGA_IN ; -input FPGA_OUT ; -input FPGA_DIR ; -output p_abuf0 ; - -assign SOC_OUT = FPGA_OUT ; - -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__56 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__57 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_141 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; -endmodule - - -module cbx_1__0__logical_tile_io_mode_physical__iopad_1 ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] iopad_outpad ; -input [0:0] ccff_head ; -output [0:0] iopad_inpad ; -output [0:0] ccff_tail ; -output p_abuf0 ; - -wire [0:0] EMBEDDED_IO_0_en ; - -cbx_1__0__EMBEDDED_IO_1 EMBEDDED_IO_0_ ( - .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , - .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , - .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , - .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_1 EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) ) ; -endmodule - - -module cbx_1__0__logical_tile_io_mode_io__1 ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , - ccff_tail , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] io_outpad ; -input [0:0] ccff_head ; -output [0:0] io_inpad ; -output [0:0] ccff_tail ; -output p_abuf0 ; - -cbx_1__0__logical_tile_io_mode_physical__iopad_1 logical_tile_io_mode_physical__iopad_0 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , - .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , - .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__0__direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( io_outpad ) ) ; -endmodule - - -module cbx_1__0__direct_interc ( in , out ) ; -input [0:0] in ; -output [0:0] out ; - -assign out[0] = in[0] ; -endmodule - - -module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_0 ( prog_clk , - ccff_head , ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:0] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__55 ( .A ( mem_out[0] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__0__EMBEDDED_IO_0 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , - FPGA_OUT , FPGA_DIR , p_abuf0 , p_abuf1 ) ; -input SOC_IN ; -output SOC_OUT ; -output SOC_DIR ; -output FPGA_IN ; -input FPGA_OUT ; -input FPGA_DIR ; -output p_abuf0 ; -output p_abuf1 ; - -assign SOC_OUT = FPGA_OUT ; - -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__53 ( .A ( SOC_IN ) , .X ( p_abuf1 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__54 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_71 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_146 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; -endmodule - - -module cbx_1__0__logical_tile_io_mode_physical__iopad_0 ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , p_abuf0 , p_abuf1 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] iopad_outpad ; -input [0:0] ccff_head ; -output [0:0] iopad_inpad ; -output [0:0] ccff_tail ; -output p_abuf0 ; -output p_abuf1 ; - -wire [0:0] EMBEDDED_IO_0_en ; - -cbx_1__0__EMBEDDED_IO_0 EMBEDDED_IO_0_ ( - .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , - .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , - .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , - .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , - .p_abuf1 ( p_abuf1 ) ) ; -cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem_0 EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) ) ; -endmodule - - -module cbx_1__0__logical_tile_io_mode_io__0 ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , - ccff_tail , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] io_outpad ; -input [0:0] ccff_head ; -output [0:0] io_inpad ; -output [0:0] ccff_tail ; -output p_abuf0 ; - -cbx_1__0__logical_tile_io_mode_physical__iopad_0 logical_tile_io_mode_physical__iopad_0 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , - .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , - .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; -cbx_1__0__direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( { p_abuf1 } ) ) ; -cbx_1__0__direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( io_outpad ) ) ; -endmodule - - -module cbx_1__0__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__52 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__0__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__51 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__0__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__50 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__0__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__49 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__0__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__48 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__0__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__47 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__0__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; -endmodule - - -module cbx_1__0__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cbx_1__0__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cbx_1__0__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cbx_1__0__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; -endmodule - - -module cbx_1__0__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cbx_1__0_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , - chanx_left_out , chanx_right_out , bottom_grid_pin_0_ , - bottom_grid_pin_2_ , bottom_grid_pin_4_ , bottom_grid_pin_6_ , - bottom_grid_pin_8_ , bottom_grid_pin_10_ , ccff_tail , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , top_width_0_height_0__pin_0_ , - top_width_0_height_0__pin_2_ , top_width_0_height_0__pin_4_ , - top_width_0_height_0__pin_6_ , top_width_0_height_0__pin_8_ , - top_width_0_height_0__pin_10_ , top_width_0_height_0__pin_1_upper , - top_width_0_height_0__pin_1_lower , top_width_0_height_0__pin_3_upper , - top_width_0_height_0__pin_3_lower , top_width_0_height_0__pin_5_upper , - top_width_0_height_0__pin_5_lower , top_width_0_height_0__pin_7_upper , - top_width_0_height_0__pin_7_lower , top_width_0_height_0__pin_9_upper , - top_width_0_height_0__pin_9_lower , top_width_0_height_0__pin_11_upper , - top_width_0_height_0__pin_11_lower , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , - SC_OUT_BOT , prog_clk__FEEDTHRU_1 ) ; -input [0:0] prog_clk ; -input [0:19] chanx_left_in ; -input [0:19] chanx_right_in ; -input [0:0] ccff_head ; -output [0:19] chanx_left_out ; -output [0:19] chanx_right_out ; -output [0:0] bottom_grid_pin_0_ ; -output [0:0] bottom_grid_pin_2_ ; -output [0:0] bottom_grid_pin_4_ ; -output [0:0] bottom_grid_pin_6_ ; -output [0:0] bottom_grid_pin_8_ ; -output [0:0] bottom_grid_pin_10_ ; -output [0:0] ccff_tail ; -input [0:5] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:5] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:5] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] top_width_0_height_0__pin_0_ ; -input [0:0] top_width_0_height_0__pin_2_ ; -input [0:0] top_width_0_height_0__pin_4_ ; -input [0:0] top_width_0_height_0__pin_6_ ; -input [0:0] top_width_0_height_0__pin_8_ ; -input [0:0] top_width_0_height_0__pin_10_ ; -output [0:0] top_width_0_height_0__pin_1_upper ; -output [0:0] top_width_0_height_0__pin_1_lower ; -output [0:0] top_width_0_height_0__pin_3_upper ; -output [0:0] top_width_0_height_0__pin_3_lower ; -output [0:0] top_width_0_height_0__pin_5_upper ; -output [0:0] top_width_0_height_0__pin_5_lower ; -output [0:0] top_width_0_height_0__pin_7_upper ; -output [0:0] top_width_0_height_0__pin_7_lower ; -output [0:0] top_width_0_height_0__pin_9_upper ; -output [0:0] top_width_0_height_0__pin_9_lower ; -output [0:0] top_width_0_height_0__pin_11_upper ; -output [0:0] top_width_0_height_0__pin_11_lower ; -input SC_IN_TOP ; -input SC_IN_BOT ; -output SC_OUT_TOP ; -output SC_OUT_BOT ; -output [0:0] prog_clk__FEEDTHRU_1 ; - -wire ropt_net_191 ; -wire ropt_net_197 ; -wire ropt_net_179 ; -wire ropt_net_177 ; -wire ropt_net_190 ; -wire ropt_net_178 ; -wire [0:3] mux_top_ipin_0_undriven_sram_inv ; -wire [0:3] mux_top_ipin_1_undriven_sram_inv ; -wire [0:3] mux_top_ipin_2_undriven_sram_inv ; -wire [0:3] mux_top_ipin_3_undriven_sram_inv ; -wire [0:3] mux_top_ipin_4_undriven_sram_inv ; -wire [0:3] mux_top_ipin_5_undriven_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:3] mux_tree_tapbuf_size10_2_sram ; -wire [0:3] mux_tree_tapbuf_size10_3_sram ; -wire [0:3] mux_tree_tapbuf_size10_4_sram ; -wire [0:3] mux_tree_tapbuf_size10_5_sram ; -wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; -wire [0:0] logical_tile_io_mode_io__0_ccff_tail ; -wire [0:0] logical_tile_io_mode_io__1_ccff_tail ; -wire [0:0] logical_tile_io_mode_io__2_ccff_tail ; -wire [0:0] logical_tile_io_mode_io__3_ccff_tail ; -wire [0:0] logical_tile_io_mode_io__4_ccff_tail ; -// - -assign SC_IN_TOP = SC_IN_BOT ; - -cbx_1__0__mux_tree_tapbuf_size10_0 mux_top_ipin_0 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , - chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , - chanx_right_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_top_ipin_0_undriven_sram_inv ) , - .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_174 ) ) ; -cbx_1__0__mux_tree_tapbuf_size10_1 mux_top_ipin_1 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , - chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , - chanx_right_in[17] } ) , - .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_top_ipin_1_undriven_sram_inv ) , - .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_173 ) ) ; -cbx_1__0__mux_tree_tapbuf_size10_2 mux_top_ipin_2 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , - chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , - chanx_right_in[18] } ) , - .sram ( mux_tree_tapbuf_size10_2_sram ) , - .sram_inv ( mux_top_ipin_2_undriven_sram_inv ) , - .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_173 ) ) ; -cbx_1__0__mux_tree_tapbuf_size10_3 mux_top_ipin_3 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , - chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , - chanx_right_in[19] } ) , - .sram ( mux_tree_tapbuf_size10_3_sram ) , - .sram_inv ( mux_top_ipin_3_undriven_sram_inv ) , - .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_173 ) ) ; -cbx_1__0__mux_tree_tapbuf_size10_4 mux_top_ipin_4 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , - chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[14] , - chanx_right_in[14] } ) , - .sram ( mux_tree_tapbuf_size10_4_sram ) , - .sram_inv ( mux_top_ipin_4_undriven_sram_inv ) , - .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_174 ) ) ; -cbx_1__0__mux_tree_tapbuf_size10 mux_top_ipin_5 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , - chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[15] , - chanx_right_in[15] } ) , - .sram ( mux_tree_tapbuf_size10_5_sram ) , - .sram_inv ( mux_top_ipin_5_undriven_sram_inv ) , - .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_174 ) ) ; -cbx_1__0__mux_tree_tapbuf_size10_mem_0 mem_top_ipin_0 ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; -cbx_1__0__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ; -cbx_1__0__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_2 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ; -cbx_1__0__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ; -cbx_1__0__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_4 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ; -cbx_1__0__mux_tree_tapbuf_size10_mem mem_top_ipin_5 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , - .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ; -cbx_1__0__logical_tile_io_mode_io__0 logical_tile_io_mode_io__0 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_196 } ) , - .io_outpad ( top_width_0_height_0__pin_0_ ) , - .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_8_ } ) , - .ccff_tail ( logical_tile_io_mode_io__0_ccff_tail ) , - .p_abuf0 ( ropt_net_191 ) ) ; -cbx_1__0__logical_tile_io_mode_io__1 logical_tile_io_mode_io__1 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[1] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[1] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_200 } ) , - .io_outpad ( top_width_0_height_0__pin_2_ ) , - .ccff_head ( logical_tile_io_mode_io__0_ccff_tail ) , - .io_inpad ( { aps_rename_10_ } ) , - .ccff_tail ( logical_tile_io_mode_io__1_ccff_tail ) , - .p_abuf0 ( ropt_net_197 ) ) ; -cbx_1__0__logical_tile_io_mode_io__2 logical_tile_io_mode_io__2 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[2] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[2] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_198 } ) , - .io_outpad ( top_width_0_height_0__pin_4_ ) , - .ccff_head ( logical_tile_io_mode_io__1_ccff_tail ) , - .io_inpad ( { aps_rename_12_ } ) , - .ccff_tail ( logical_tile_io_mode_io__2_ccff_tail ) , - .p_abuf0 ( ropt_net_179 ) ) ; -cbx_1__0__logical_tile_io_mode_io__3 logical_tile_io_mode_io__3 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[3] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[3] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_193 } ) , - .io_outpad ( top_width_0_height_0__pin_6_ ) , - .ccff_head ( logical_tile_io_mode_io__2_ccff_tail ) , - .io_inpad ( { aps_rename_13_ } ) , - .ccff_tail ( logical_tile_io_mode_io__3_ccff_tail ) , - .p_abuf0 ( ropt_net_177 ) ) ; -cbx_1__0__logical_tile_io_mode_io__4 logical_tile_io_mode_io__4 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[4] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[4] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_201 } ) , - .io_outpad ( top_width_0_height_0__pin_8_ ) , - .ccff_head ( logical_tile_io_mode_io__3_ccff_tail ) , - .io_inpad ( { aps_rename_14_ } ) , - .ccff_tail ( logical_tile_io_mode_io__4_ccff_tail ) , - .p_abuf0 ( ropt_net_190 ) ) ; -cbx_1__0__logical_tile_io_mode_io_ logical_tile_io_mode_io__5 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[5] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[5] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[5] ) , - .io_outpad ( top_width_0_height_0__pin_10_ ) , - .ccff_head ( logical_tile_io_mode_io__4_ccff_tail ) , - .io_inpad ( { aps_rename_15_ } ) , - .ccff_tail ( { ropt_net_212 } ) , - .p_abuf0 ( ropt_net_178 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_166 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_173 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_168 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_174 ) ) ; -sky130_fd_sc_hd__clkbuf_1 prog_clk_0__bip435 ( .A ( prog_clk[0] ) , - .X ( ctsbuf_net_1176 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , - .X ( ropt_net_207 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_177 ) , - .X ( ropt_net_243 ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_326761 ( .A ( ctsbuf_net_1176 ) , - .X ( prog_clk__FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_849 ( .A ( ropt_net_239 ) , - .X ( chanx_left_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_178 ) , - .X ( ropt_net_247 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_266 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chanx_left_in[9] ) , - .X ( ropt_net_208 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_179 ) , - .X ( ropt_net_249 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( ropt_net_180 ) , - .X ( ropt_net_245 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_792 ( .A ( ropt_net_181 ) , - .X ( top_width_0_height_0__pin_11_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( ropt_net_182 ) , - .X ( ropt_net_270 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_244 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__15 ( .A ( chanx_left_in[15] ) , - .X ( ropt_net_222 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_184 ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( chanx_right_in[5] ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_233 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( chanx_right_in[7] ) , - .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_187 ) , - .X ( top_width_0_height_0__pin_3_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , - .X ( ropt_net_219 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_850 ( .A ( ropt_net_240 ) , - .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_188 ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_246 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_190 ) , - .X ( ropt_net_250 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_224 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_191 ) , - .X ( top_width_0_height_0__pin_1_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_192 ) , - .X ( ropt_net_240 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__29 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_221 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__30 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_223 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_851 ( .A ( ropt_net_241 ) , - .X ( chanx_left_out[12] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__32 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_216 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_193 ) , - .X ( ropt_net_262 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_194 ) , - .X ( top_width_0_height_0__pin_1_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_36__35 ( .A ( chanx_right_in[15] ) , - .X ( ropt_net_226 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_37__36 ( .A ( chanx_right_in[16] ) , - .X ( ropt_net_229 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( ropt_net_195 ) , - .X ( ropt_net_264 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_39__38 ( .A ( chanx_right_in[18] ) , - .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_852 ( .A ( ropt_net_242 ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_41__40 ( .A ( aps_rename_8_ ) , - .X ( aps_rename_9_ ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_853 ( .A ( ropt_net_243 ) , - .X ( top_width_0_height_0__pin_7_upper[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_43__42 ( .A ( aps_rename_12_ ) , - .X ( ropt_net_182 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_196 ) , - .X ( ropt_net_254 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_197 ) , - .X ( top_width_0_height_0__pin_3_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_46__45 ( .A ( aps_rename_15_ ) , - .X ( ropt_net_181 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_47__46 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_180 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_85 ( .A ( chanx_left_in[0] ) , - .X ( ropt_net_209 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_86 ( .A ( chanx_left_in[1] ) , - .X ( ropt_net_225 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_87 ( .A ( chanx_left_in[4] ) , - .X ( ropt_net_214 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_88 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_184 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_809 ( .A ( ropt_net_198 ) , - .X ( ropt_net_268 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_90 ( .A ( chanx_left_in[11] ) , - .X ( ropt_net_227 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_810 ( .A ( ropt_net_199 ) , - .X ( ropt_net_265 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_92 ( .A ( chanx_left_in[16] ) , - .X ( ropt_net_213 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_93 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_210 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_94 ( .A ( chanx_right_in[3] ) , - .X ( ropt_net_220 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_854 ( .A ( ropt_net_244 ) , - .X ( chanx_left_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_857 ( .A ( ropt_net_245 ) , - .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_858 ( .A ( ropt_net_246 ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_811 ( .A ( ropt_net_200 ) , - .X ( ropt_net_267 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_860 ( .A ( ropt_net_247 ) , - .X ( top_width_0_height_0__pin_11_upper[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_100 ( .A ( chanx_right_in[14] ) , - .X ( ropt_net_231 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_862 ( .A ( ropt_net_248 ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_812 ( .A ( ropt_net_201 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_103 ( .A ( aps_rename_9_ ) , - .X ( ropt_net_194 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_104 ( .A ( aps_rename_10_ ) , - .X ( ropt_net_187 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_864 ( .A ( ropt_net_249 ) , - .X ( top_width_0_height_0__pin_5_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_865 ( .A ( ropt_net_250 ) , - .X ( top_width_0_height_0__pin_9_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( chanx_right_in[2] ) , - .X ( chanx_left_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_814 ( .A ( chanx_left_in[5] ) , - .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_815 ( .A ( chanx_left_in[7] ) , - .X ( ropt_net_269 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_205 ) , - .X ( ropt_net_256 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_817 ( .A ( chanx_right_in[13] ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_207 ) , - .X ( ropt_net_248 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_208 ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_209 ) , - .X ( ropt_net_260 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_210 ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_211 ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_212 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_213 ) , - .X ( chanx_right_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_131 ( .A ( chanx_left_in[2] ) , - .X ( ropt_net_228 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_866 ( .A ( ropt_net_251 ) , - .X ( chanx_left_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_133 ( .A ( chanx_left_in[10] ) , - .X ( ropt_net_211 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_134 ( .A ( chanx_left_in[12] ) , - .X ( ropt_net_205 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_135 ( .A ( chanx_left_in[13] ) , - .X ( ropt_net_217 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_136 ( .A ( chanx_left_in[19] ) , - .X ( ropt_net_215 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_137 ( .A ( chanx_right_in[0] ) , - .X ( ropt_net_232 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_138 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_218 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( ropt_net_214 ) , - .X ( ropt_net_259 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_144 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_188 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_145 ( .A ( chanx_right_in[19] ) , - .X ( ropt_net_192 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_826 ( .A ( ropt_net_215 ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_867 ( .A ( ropt_net_252 ) , - .X ( chanx_left_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_154 ( .A ( chanx_left_in[14] ) , - .X ( ropt_net_230 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_827 ( .A ( ropt_net_216 ) , - .X ( ropt_net_241 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_217 ) , - .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_829 ( .A ( ropt_net_218 ) , - .X ( ropt_net_252 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_219 ) , - .X ( ropt_net_239 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_220 ) , - .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_160 ( .A ( aps_rename_13_ ) , - .X ( ropt_net_199 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_161 ( .A ( aps_rename_14_ ) , - .X ( ropt_net_195 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_832 ( .A ( ropt_net_221 ) , - .X ( ropt_net_242 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_833 ( .A ( ropt_net_222 ) , - .X ( ropt_net_255 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_834 ( .A ( ropt_net_223 ) , - .X ( ropt_net_257 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_835 ( .A ( ropt_net_224 ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_836 ( .A ( ropt_net_225 ) , - .X ( ropt_net_258 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_838 ( .A ( ropt_net_226 ) , - .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_839 ( .A ( ropt_net_227 ) , - .X ( ropt_net_261 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_840 ( .A ( ropt_net_228 ) , - .X ( chanx_right_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_841 ( .A ( ropt_net_229 ) , - .X ( ropt_net_263 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_843 ( .A ( ropt_net_230 ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_844 ( .A ( ropt_net_231 ) , - .X ( ropt_net_253 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_845 ( .A ( ropt_net_232 ) , - .X ( ropt_net_251 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_847 ( .A ( ropt_net_233 ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_868 ( .A ( ropt_net_253 ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_871 ( .A ( ropt_net_254 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_873 ( .A ( ropt_net_255 ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_874 ( .A ( ropt_net_256 ) , - .X ( chanx_right_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_875 ( .A ( ropt_net_257 ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_876 ( .A ( ropt_net_258 ) , - .X ( chanx_right_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_877 ( .A ( ropt_net_259 ) , - .X ( chanx_right_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_878 ( .A ( ropt_net_260 ) , - .X ( chanx_right_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_879 ( .A ( ropt_net_261 ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_880 ( .A ( ropt_net_262 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_882 ( .A ( ropt_net_263 ) , - .X ( chanx_left_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_889 ( .A ( ropt_net_264 ) , - .X ( top_width_0_height_0__pin_9_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_890 ( .A ( ropt_net_265 ) , - .X ( top_width_0_height_0__pin_7_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_892 ( .A ( ropt_net_266 ) , - .X ( chanx_right_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_893 ( .A ( ropt_net_267 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_894 ( .A ( ropt_net_268 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_896 ( .A ( ropt_net_269 ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_899 ( .A ( ropt_net_270 ) , - .X ( top_width_0_height_0__pin_5_lower[0] ) ) ; -endmodule - - diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__1__icv_in_design.fm.v b/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__1__icv_in_design.fm.v deleted file mode 100644 index 262dc60..0000000 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__1__icv_in_design.fm.v +++ /dev/null @@ -1,1653 +0,0 @@ -// -// -// -// -// -// -module cbx_1__1__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__56 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__55 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__54 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__53 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__52 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__51 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__50 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__49 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__1__const1 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -cbx_1__1__const1 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cbx_1__1__const1_14 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -cbx_1__1__const1_14 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cbx_1__1__const1_13 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -cbx_1__1__const1_13 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cbx_1__1__const1_12 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -cbx_1__1__const1_12 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cbx_1__1__const1_11 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -cbx_1__1__const1_11 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cbx_1__1__const1_10 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -cbx_1__1__const1_10 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cbx_1__1__const1_9 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -cbx_1__1__const1_9 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cbx_1__1__const1_8 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -cbx_1__1__const1_8 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__48 ( .A ( mem_out[3] ) , - .X ( net_net_72 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_90 ( .A ( net_net_72 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__47 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__46 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__45 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__44 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__43 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__42 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__41 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__1__const1_7 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -cbx_1__1__const1_7 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cbx_1__1__const1_6 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -cbx_1__1__const1_6 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cbx_1__1__const1_5 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -cbx_1__1__const1_5 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cbx_1__1__const1_4 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -cbx_1__1__const1_4 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cbx_1__1__const1_3 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -cbx_1__1__const1_3 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cbx_1__1__const1_2 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -cbx_1__1__const1_2 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cbx_1__1__const1_1 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -cbx_1__1__const1_1 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cbx_1__1__const1_0 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -cbx_1__1__const1_0 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cbx_1__1_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , - chanx_left_out , chanx_right_out , bottom_grid_pin_0_ , - bottom_grid_pin_1_ , bottom_grid_pin_2_ , bottom_grid_pin_3_ , - bottom_grid_pin_4_ , bottom_grid_pin_5_ , bottom_grid_pin_6_ , - bottom_grid_pin_7_ , bottom_grid_pin_8_ , bottom_grid_pin_9_ , - bottom_grid_pin_10_ , bottom_grid_pin_11_ , bottom_grid_pin_12_ , - bottom_grid_pin_13_ , bottom_grid_pin_14_ , bottom_grid_pin_15_ , - ccff_tail , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , SC_OUT_BOT , - prog_clk__FEEDTHRU_1 ) ; -input [0:0] prog_clk ; -input [0:19] chanx_left_in ; -input [0:19] chanx_right_in ; -input [0:0] ccff_head ; -output [0:19] chanx_left_out ; -output [0:19] chanx_right_out ; -output [0:0] bottom_grid_pin_0_ ; -output [0:0] bottom_grid_pin_1_ ; -output [0:0] bottom_grid_pin_2_ ; -output [0:0] bottom_grid_pin_3_ ; -output [0:0] bottom_grid_pin_4_ ; -output [0:0] bottom_grid_pin_5_ ; -output [0:0] bottom_grid_pin_6_ ; -output [0:0] bottom_grid_pin_7_ ; -output [0:0] bottom_grid_pin_8_ ; -output [0:0] bottom_grid_pin_9_ ; -output [0:0] bottom_grid_pin_10_ ; -output [0:0] bottom_grid_pin_11_ ; -output [0:0] bottom_grid_pin_12_ ; -output [0:0] bottom_grid_pin_13_ ; -output [0:0] bottom_grid_pin_14_ ; -output [0:0] bottom_grid_pin_15_ ; -output [0:0] ccff_tail ; -input SC_IN_TOP ; -input SC_IN_BOT ; -output SC_OUT_TOP ; -output SC_OUT_BOT ; -output [0:0] prog_clk__FEEDTHRU_1 ; - -wire [0:3] mux_top_ipin_0_undriven_sram_inv ; -wire [0:3] mux_top_ipin_10_undriven_sram_inv ; -wire [0:3] mux_top_ipin_11_undriven_sram_inv ; -wire [0:3] mux_top_ipin_12_undriven_sram_inv ; -wire [0:3] mux_top_ipin_13_undriven_sram_inv ; -wire [0:3] mux_top_ipin_14_undriven_sram_inv ; -wire [0:3] mux_top_ipin_15_undriven_sram_inv ; -wire [0:3] mux_top_ipin_1_undriven_sram_inv ; -wire [0:3] mux_top_ipin_2_undriven_sram_inv ; -wire [0:3] mux_top_ipin_3_undriven_sram_inv ; -wire [0:3] mux_top_ipin_4_undriven_sram_inv ; -wire [0:3] mux_top_ipin_5_undriven_sram_inv ; -wire [0:3] mux_top_ipin_6_undriven_sram_inv ; -wire [0:3] mux_top_ipin_7_undriven_sram_inv ; -wire [0:3] mux_top_ipin_8_undriven_sram_inv ; -wire [0:3] mux_top_ipin_9_undriven_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:3] mux_tree_tapbuf_size10_2_sram ; -wire [0:3] mux_tree_tapbuf_size10_3_sram ; -wire [0:3] mux_tree_tapbuf_size10_4_sram ; -wire [0:3] mux_tree_tapbuf_size10_5_sram ; -wire [0:3] mux_tree_tapbuf_size10_6_sram ; -wire [0:3] mux_tree_tapbuf_size10_7_sram ; -wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:3] mux_tree_tapbuf_size8_2_sram ; -wire [0:3] mux_tree_tapbuf_size8_3_sram ; -wire [0:3] mux_tree_tapbuf_size8_4_sram ; -wire [0:3] mux_tree_tapbuf_size8_5_sram ; -wire [0:3] mux_tree_tapbuf_size8_6_sram ; -wire [0:3] mux_tree_tapbuf_size8_7_sram ; -wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ; -// - -assign SC_IN_TOP = SC_IN_BOT ; - -cbx_1__1__mux_tree_tapbuf_size10_0 mux_top_ipin_0 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , - chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , - chanx_right_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_top_ipin_0_undriven_sram_inv ) , - .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_104 ) ) ; -cbx_1__1__mux_tree_tapbuf_size10_4 mux_top_ipin_3 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , - chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , - chanx_right_in[19] } ) , - .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_top_ipin_3_undriven_sram_inv ) , - .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_105 ) ) ; -cbx_1__1__mux_tree_tapbuf_size10_5 mux_top_ipin_4 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , - chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[14] , - chanx_right_in[14] } ) , - .sram ( mux_tree_tapbuf_size10_2_sram ) , - .sram_inv ( mux_top_ipin_4_undriven_sram_inv ) , - .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_102 ) ) ; -cbx_1__1__mux_tree_tapbuf_size10_6 mux_top_ipin_7 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , - chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , - chanx_right_in[17] } ) , - .sram ( mux_tree_tapbuf_size10_3_sram ) , - .sram_inv ( mux_top_ipin_7_undriven_sram_inv ) , - .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_104 ) ) ; -cbx_1__1__mux_tree_tapbuf_size10 mux_top_ipin_8 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[8] , chanx_right_in[8] , - chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , - chanx_right_in[18] } ) , - .sram ( mux_tree_tapbuf_size10_4_sram ) , - .sram_inv ( mux_top_ipin_8_undriven_sram_inv ) , - .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_103 ) ) ; -cbx_1__1__mux_tree_tapbuf_size10_1 mux_top_ipin_11 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , - chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[15] , - chanx_right_in[15] } ) , - .sram ( mux_tree_tapbuf_size10_5_sram ) , - .sram_inv ( mux_top_ipin_11_undriven_sram_inv ) , - .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_105 ) ) ; -cbx_1__1__mux_tree_tapbuf_size10_2 mux_top_ipin_12 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , - chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[16] , - chanx_right_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_6_sram ) , - .sram_inv ( mux_top_ipin_12_undriven_sram_inv ) , - .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_103 ) ) ; -cbx_1__1__mux_tree_tapbuf_size10_3 mux_top_ipin_15 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , - chanx_left_in[15] , chanx_right_in[15] , chanx_left_in[19] , - chanx_right_in[19] } ) , - .sram ( mux_tree_tapbuf_size10_7_sram ) , - .sram_inv ( mux_top_ipin_15_undriven_sram_inv ) , - .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_105 ) ) ; -cbx_1__1__mux_tree_tapbuf_size10_mem_0 mem_top_ipin_0 ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; -cbx_1__1__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ; -cbx_1__1__mux_tree_tapbuf_size10_mem_5 mem_top_ipin_4 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ; -cbx_1__1__mux_tree_tapbuf_size10_mem_6 mem_top_ipin_7 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ; -cbx_1__1__mux_tree_tapbuf_size10_mem mem_top_ipin_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ; -cbx_1__1__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_11 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ; -cbx_1__1__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_12 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ; -cbx_1__1__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_15 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .ccff_tail ( { ropt_net_124 } ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_0 mux_top_ipin_1 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , - chanx_left_in[13] , chanx_right_in[13] } ) , - .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_top_ipin_1_undriven_sram_inv ) , - .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_105 ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_4 mux_top_ipin_2 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , - chanx_left_in[14] , chanx_right_in[14] } ) , - .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_top_ipin_2_undriven_sram_inv ) , - .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_102 ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_5 mux_top_ipin_5 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , - chanx_left_in[17] , chanx_right_in[17] } ) , - .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_top_ipin_5_undriven_sram_inv ) , - .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_104 ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_6 mux_top_ipin_6 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , - chanx_left_in[18] , chanx_right_in[18] } ) , - .sram ( mux_tree_tapbuf_size8_3_sram ) , - .sram_inv ( mux_top_ipin_6_undriven_sram_inv ) , - .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_103 ) ) ; -cbx_1__1__mux_tree_tapbuf_size8 mux_top_ipin_9 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , - chanx_left_in[13] , chanx_right_in[13] } ) , - .sram ( mux_tree_tapbuf_size8_4_sram ) , - .sram_inv ( mux_top_ipin_9_undriven_sram_inv ) , - .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_103 ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_1 mux_top_ipin_10 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , - chanx_left_in[14] , chanx_right_in[14] } ) , - .sram ( mux_tree_tapbuf_size8_5_sram ) , - .sram_inv ( mux_top_ipin_10_undriven_sram_inv ) , - .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_102 ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_2 mux_top_ipin_13 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , - chanx_left_in[17] , chanx_right_in[17] } ) , - .sram ( mux_tree_tapbuf_size8_6_sram ) , - .sram_inv ( mux_top_ipin_13_undriven_sram_inv ) , - .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_104 ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_3 mux_top_ipin_14 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , - chanx_left_in[18] , chanx_right_in[18] } ) , - .sram ( mux_tree_tapbuf_size8_7_sram ) , - .sram_inv ( mux_top_ipin_14_undriven_sram_inv ) , - .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_103 ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_mem_0 mem_top_ipin_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_mem_4 mem_top_ipin_2 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_mem_5 mem_top_ipin_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_mem_6 mem_top_ipin_6 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_3_sram ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_mem mem_top_ipin_9 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_4_sram ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_mem_1 mem_top_ipin_10 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_5_sram ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_mem_2 mem_top_ipin_13 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_6_sram ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_mem_3 mem_top_ipin_14 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_7_sram ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chanx_left_in[0] ) , - .X ( chanx_right_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_134 ) , - .X ( chanx_left_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chanx_left_in[2] ) , - .X ( chanx_right_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__4 ( .A ( chanx_left_in[4] ) , - .X ( ropt_net_128 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_102 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_103 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__7 ( .A ( chanx_left_in[7] ) , - .X ( ropt_net_130 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_104 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_105 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chanx_left_in[10] ) , - .X ( ropt_net_133 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( ropt_net_135 ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__clkbuf_1 prog_clk_0__bip373 ( .A ( prog_clk[0] ) , - .X ( ctsbuf_net_1106 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( chanx_right_in[4] ) , - .X ( chanx_left_out[4] ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_326699 ( .A ( ctsbuf_net_1106 ) , - .X ( prog_clk__FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_136 ) , - .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( ropt_net_108 ) , - .X ( ropt_net_146 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chanx_left_in[17] ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_137 ) , - .X ( chanx_left_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_138 ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_right_in[0] ) , - .X ( chanx_left_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , - .X ( ropt_net_123 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chanx_right_in[2] ) , - .X ( chanx_left_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chanx_right_in[3] ) , - .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_728 ( .A ( chanx_left_in[13] ) , - .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chanx_right_in[5] ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_148 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chanx_right_in[7] ) , - .X ( ropt_net_145 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_110 ) , - .X ( ropt_net_141 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chanx_right_in[9] ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( chanx_right_in[15] ) , - .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_32__31 ( .A ( chanx_right_in[11] ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_134 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_126 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_35__34 ( .A ( chanx_right_in[14] ) , - .X ( ropt_net_132 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( chanx_left_in[9] ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_37__36 ( .A ( chanx_right_in[16] ) , - .X ( ropt_net_129 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_38__37 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_121 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_39__38 ( .A ( chanx_right_in[18] ) , - .X ( ropt_net_125 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( chanx_left_in[5] ) , - .X ( ropt_net_149 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_41__40 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_108 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_770 ( .A ( ropt_net_139 ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_59 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_131 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( chanx_left_in[18] ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_772 ( .A ( ropt_net_140 ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_774 ( .A ( ropt_net_141 ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_63 ( .A ( chanx_left_in[14] ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_64 ( .A ( chanx_left_in[15] ) , - .X ( ropt_net_110 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_116 ) , - .X ( ropt_net_135 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( .A ( ropt_net_142 ) , - .X ( chanx_right_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( ropt_net_143 ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_777 ( .A ( ropt_net_144 ) , - .X ( chanx_left_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( chanx_left_in[11] ) , - .X ( ropt_net_139 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_70 ( .A ( chanx_right_in[19] ) , - .X ( ropt_net_127 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( chanx_left_in[8] ) , - .X ( chanx_right_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( chanx_left_in[16] ) , - .X ( ropt_net_147 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_739 ( .A ( chanx_left_in[1] ) , - .X ( chanx_right_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_121 ) , - .X ( ropt_net_138 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( .A ( chanx_right_in[12] ) , - .X ( chanx_left_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_145 ) , - .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_79 ( .A ( chanx_left_in[19] ) , - .X ( ropt_net_116 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_123 ) , - .X ( ropt_net_137 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_124 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_125 ) , - .X ( ropt_net_136 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( chanx_left_in[12] ) , - .X ( chanx_right_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_146 ) , - .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_88 ( .A ( chanx_right_in[10] ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_147 ) , - .X ( chanx_right_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_148 ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_149 ) , - .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_126 ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( .A ( ropt_net_127 ) , - .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_128 ) , - .X ( ropt_net_142 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_129 ) , - .X ( ropt_net_144 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_130 ) , - .X ( ropt_net_143 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_131 ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_132 ) , - .X ( ropt_net_140 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_133 ) , - .X ( chanx_right_out[10] ) ) ; -endmodule - - diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__1__icv_in_design.lvs.v b/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__1__icv_in_design.lvs.v deleted file mode 100644 index 52cd0d2..0000000 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__1__icv_in_design.lvs.v +++ /dev/null @@ -1,2601 +0,0 @@ -// -// -// -// -// -// -module cbx_1__1__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__56 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__55 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__54 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__53 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__52 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__51 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__50 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__49 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__48 ( .A ( mem_out[3] ) , - .X ( net_net_72 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_90 ( .A ( net_net_72 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__47 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__46 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__45 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__44 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__43 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__42 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__41 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__1_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , - chanx_left_out , chanx_right_out , bottom_grid_pin_0_ , - bottom_grid_pin_1_ , bottom_grid_pin_2_ , bottom_grid_pin_3_ , - bottom_grid_pin_4_ , bottom_grid_pin_5_ , bottom_grid_pin_6_ , - bottom_grid_pin_7_ , bottom_grid_pin_8_ , bottom_grid_pin_9_ , - bottom_grid_pin_10_ , bottom_grid_pin_11_ , bottom_grid_pin_12_ , - bottom_grid_pin_13_ , bottom_grid_pin_14_ , bottom_grid_pin_15_ , - ccff_tail , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , SC_OUT_BOT , VDD , VSS , - prog_clk__FEEDTHRU_1 ) ; -input [0:0] prog_clk ; -input [0:19] chanx_left_in ; -input [0:19] chanx_right_in ; -input [0:0] ccff_head ; -output [0:19] chanx_left_out ; -output [0:19] chanx_right_out ; -output [0:0] bottom_grid_pin_0_ ; -output [0:0] bottom_grid_pin_1_ ; -output [0:0] bottom_grid_pin_2_ ; -output [0:0] bottom_grid_pin_3_ ; -output [0:0] bottom_grid_pin_4_ ; -output [0:0] bottom_grid_pin_5_ ; -output [0:0] bottom_grid_pin_6_ ; -output [0:0] bottom_grid_pin_7_ ; -output [0:0] bottom_grid_pin_8_ ; -output [0:0] bottom_grid_pin_9_ ; -output [0:0] bottom_grid_pin_10_ ; -output [0:0] bottom_grid_pin_11_ ; -output [0:0] bottom_grid_pin_12_ ; -output [0:0] bottom_grid_pin_13_ ; -output [0:0] bottom_grid_pin_14_ ; -output [0:0] bottom_grid_pin_15_ ; -output [0:0] ccff_tail ; -input SC_IN_TOP ; -input SC_IN_BOT ; -output SC_OUT_TOP ; -output SC_OUT_BOT ; -input VDD ; -input VSS ; -output [0:0] prog_clk__FEEDTHRU_1 ; - -wire [0:3] mux_top_ipin_0_undriven_sram_inv ; -wire [0:3] mux_top_ipin_10_undriven_sram_inv ; -wire [0:3] mux_top_ipin_11_undriven_sram_inv ; -wire [0:3] mux_top_ipin_12_undriven_sram_inv ; -wire [0:3] mux_top_ipin_13_undriven_sram_inv ; -wire [0:3] mux_top_ipin_14_undriven_sram_inv ; -wire [0:3] mux_top_ipin_15_undriven_sram_inv ; -wire [0:3] mux_top_ipin_1_undriven_sram_inv ; -wire [0:3] mux_top_ipin_2_undriven_sram_inv ; -wire [0:3] mux_top_ipin_3_undriven_sram_inv ; -wire [0:3] mux_top_ipin_4_undriven_sram_inv ; -wire [0:3] mux_top_ipin_5_undriven_sram_inv ; -wire [0:3] mux_top_ipin_6_undriven_sram_inv ; -wire [0:3] mux_top_ipin_7_undriven_sram_inv ; -wire [0:3] mux_top_ipin_8_undriven_sram_inv ; -wire [0:3] mux_top_ipin_9_undriven_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:3] mux_tree_tapbuf_size10_2_sram ; -wire [0:3] mux_tree_tapbuf_size10_3_sram ; -wire [0:3] mux_tree_tapbuf_size10_4_sram ; -wire [0:3] mux_tree_tapbuf_size10_5_sram ; -wire [0:3] mux_tree_tapbuf_size10_6_sram ; -wire [0:3] mux_tree_tapbuf_size10_7_sram ; -wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:3] mux_tree_tapbuf_size8_2_sram ; -wire [0:3] mux_tree_tapbuf_size8_3_sram ; -wire [0:3] mux_tree_tapbuf_size8_4_sram ; -wire [0:3] mux_tree_tapbuf_size8_5_sram ; -wire [0:3] mux_tree_tapbuf_size8_6_sram ; -wire [0:3] mux_tree_tapbuf_size8_7_sram ; -wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ; -supply1 VDD ; -supply0 VSS ; -// - -assign SC_IN_TOP = SC_IN_BOT ; - -cbx_1__1__mux_tree_tapbuf_size10_0 mux_top_ipin_0 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , - chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , - chanx_right_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_top_ipin_0_undriven_sram_inv ) , - .out ( bottom_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_104 ) ) ; -cbx_1__1__mux_tree_tapbuf_size10_4 mux_top_ipin_3 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , - chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , - chanx_right_in[19] } ) , - .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_top_ipin_3_undriven_sram_inv ) , - .out ( bottom_grid_pin_3_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_105 ) ) ; -cbx_1__1__mux_tree_tapbuf_size10_5 mux_top_ipin_4 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , - chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[14] , - chanx_right_in[14] } ) , - .sram ( mux_tree_tapbuf_size10_2_sram ) , - .sram_inv ( mux_top_ipin_4_undriven_sram_inv ) , - .out ( bottom_grid_pin_4_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_102 ) ) ; -cbx_1__1__mux_tree_tapbuf_size10_6 mux_top_ipin_7 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , - chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , - chanx_right_in[17] } ) , - .sram ( mux_tree_tapbuf_size10_3_sram ) , - .sram_inv ( mux_top_ipin_7_undriven_sram_inv ) , - .out ( bottom_grid_pin_7_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_104 ) ) ; -cbx_1__1__mux_tree_tapbuf_size10 mux_top_ipin_8 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[8] , chanx_right_in[8] , - chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , - chanx_right_in[18] } ) , - .sram ( mux_tree_tapbuf_size10_4_sram ) , - .sram_inv ( mux_top_ipin_8_undriven_sram_inv ) , - .out ( bottom_grid_pin_8_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_103 ) ) ; -cbx_1__1__mux_tree_tapbuf_size10_1 mux_top_ipin_11 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , - chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[15] , - chanx_right_in[15] } ) , - .sram ( mux_tree_tapbuf_size10_5_sram ) , - .sram_inv ( mux_top_ipin_11_undriven_sram_inv ) , - .out ( bottom_grid_pin_11_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_105 ) ) ; -cbx_1__1__mux_tree_tapbuf_size10_2 mux_top_ipin_12 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , - chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[16] , - chanx_right_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_6_sram ) , - .sram_inv ( mux_top_ipin_12_undriven_sram_inv ) , - .out ( bottom_grid_pin_12_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_103 ) ) ; -cbx_1__1__mux_tree_tapbuf_size10_3 mux_top_ipin_15 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , - chanx_left_in[15] , chanx_right_in[15] , chanx_left_in[19] , - chanx_right_in[19] } ) , - .sram ( mux_tree_tapbuf_size10_7_sram ) , - .sram_inv ( mux_top_ipin_15_undriven_sram_inv ) , - .out ( bottom_grid_pin_15_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_105 ) ) ; -cbx_1__1__mux_tree_tapbuf_size10_mem_0 mem_top_ipin_0 ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__1__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__1__mux_tree_tapbuf_size10_mem_5 mem_top_ipin_4 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__1__mux_tree_tapbuf_size10_mem_6 mem_top_ipin_7 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__1__mux_tree_tapbuf_size10_mem mem_top_ipin_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__1__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_11 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__1__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_12 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__1__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_15 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .ccff_tail ( { ropt_net_124 } ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_0 mux_top_ipin_1 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , - chanx_left_in[13] , chanx_right_in[13] } ) , - .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_top_ipin_1_undriven_sram_inv ) , - .out ( bottom_grid_pin_1_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_105 ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_4 mux_top_ipin_2 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , - chanx_left_in[14] , chanx_right_in[14] } ) , - .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_top_ipin_2_undriven_sram_inv ) , - .out ( bottom_grid_pin_2_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_102 ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_5 mux_top_ipin_5 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , - chanx_left_in[17] , chanx_right_in[17] } ) , - .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_top_ipin_5_undriven_sram_inv ) , - .out ( bottom_grid_pin_5_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_104 ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_6 mux_top_ipin_6 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , - chanx_left_in[18] , chanx_right_in[18] } ) , - .sram ( mux_tree_tapbuf_size8_3_sram ) , - .sram_inv ( mux_top_ipin_6_undriven_sram_inv ) , - .out ( bottom_grid_pin_6_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_103 ) ) ; -cbx_1__1__mux_tree_tapbuf_size8 mux_top_ipin_9 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , - chanx_left_in[13] , chanx_right_in[13] } ) , - .sram ( mux_tree_tapbuf_size8_4_sram ) , - .sram_inv ( mux_top_ipin_9_undriven_sram_inv ) , - .out ( bottom_grid_pin_9_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_103 ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_1 mux_top_ipin_10 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , - chanx_left_in[14] , chanx_right_in[14] } ) , - .sram ( mux_tree_tapbuf_size8_5_sram ) , - .sram_inv ( mux_top_ipin_10_undriven_sram_inv ) , - .out ( bottom_grid_pin_10_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_102 ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_2 mux_top_ipin_13 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , - chanx_left_in[17] , chanx_right_in[17] } ) , - .sram ( mux_tree_tapbuf_size8_6_sram ) , - .sram_inv ( mux_top_ipin_13_undriven_sram_inv ) , - .out ( bottom_grid_pin_13_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_104 ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_3 mux_top_ipin_14 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , - chanx_left_in[18] , chanx_right_in[18] } ) , - .sram ( mux_tree_tapbuf_size8_7_sram ) , - .sram_inv ( mux_top_ipin_14_undriven_sram_inv ) , - .out ( bottom_grid_pin_14_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_103 ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_mem_0 mem_top_ipin_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_mem_4 mem_top_ipin_2 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_mem_5 mem_top_ipin_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_mem_6 mem_top_ipin_6 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_mem mem_top_ipin_9 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_mem_1 mem_top_ipin_10 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_mem_2 mem_top_ipin_13 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_mem_3 mem_top_ipin_14 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1600 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1601 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1602 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1603 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1604 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1605 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1606 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1607 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1608 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1609 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1610 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1611 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1612 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1613 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1614 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1615 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1616 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chanx_left_in[0] ) , - .X ( chanx_right_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_134 ) , - .X ( chanx_left_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chanx_left_in[2] ) , - .X ( chanx_right_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , - .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__4 ( .A ( chanx_left_in[4] ) , - .X ( ropt_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__7 ( .A ( chanx_left_in[7] ) , - .X ( ropt_net_130 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chanx_left_in[10] ) , - .X ( ropt_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( ropt_net_135 ) , - .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__clkbuf_1 prog_clk_0__bip373 ( .A ( prog_clk[0] ) , - .X ( ctsbuf_net_1106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( chanx_right_in[4] ) , - .X ( chanx_left_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_326699 ( .A ( ctsbuf_net_1106 ) , - .X ( prog_clk__FEEDTHRU_1[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_136 ) , - .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( ropt_net_108 ) , - .X ( ropt_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chanx_left_in[17] ) , - .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_137 ) , - .X ( chanx_left_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_138 ) , - .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_right_in[0] ) , - .X ( chanx_left_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , - .X ( ropt_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chanx_right_in[2] ) , - .X ( chanx_left_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chanx_right_in[3] ) , - .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_728 ( .A ( chanx_left_in[13] ) , - .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chanx_right_in[5] ) , - .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chanx_right_in[7] ) , - .X ( ropt_net_145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_110 ) , - .X ( ropt_net_141 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chanx_right_in[9] ) , - .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( chanx_right_in[15] ) , - .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_32__31 ( .A ( chanx_right_in[11] ) , - .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_126 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_35__34 ( .A ( chanx_right_in[14] ) , - .X ( ropt_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( chanx_left_in[9] ) , - .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_37__36 ( .A ( chanx_right_in[16] ) , - .X ( ropt_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_38__37 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_39__38 ( .A ( chanx_right_in[18] ) , - .X ( ropt_net_125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( chanx_left_in[5] ) , - .X ( ropt_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_41__40 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_770 ( .A ( ropt_net_139 ) , - .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_59 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( chanx_left_in[18] ) , - .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_772 ( .A ( ropt_net_140 ) , - .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_774 ( .A ( ropt_net_141 ) , - .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_63 ( .A ( chanx_left_in[14] ) , - .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_64 ( .A ( chanx_left_in[15] ) , - .X ( ropt_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_116 ) , - .X ( ropt_net_135 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( .A ( ropt_net_142 ) , - .X ( chanx_right_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( ropt_net_143 ) , - .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_777 ( .A ( ropt_net_144 ) , - .X ( chanx_left_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( chanx_left_in[11] ) , - .X ( ropt_net_139 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_70 ( .A ( chanx_right_in[19] ) , - .X ( ropt_net_127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( chanx_left_in[8] ) , - .X ( chanx_right_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( chanx_left_in[16] ) , - .X ( ropt_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_739 ( .A ( chanx_left_in[1] ) , - .X ( chanx_right_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_121 ) , - .X ( ropt_net_138 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( .A ( chanx_right_in[12] ) , - .X ( chanx_left_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_145 ) , - .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_79 ( .A ( chanx_left_in[19] ) , - .X ( ropt_net_116 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_123 ) , - .X ( ropt_net_137 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_124 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_125 ) , - .X ( ropt_net_136 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( chanx_left_in[12] ) , - .X ( chanx_right_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_146 ) , - .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_88 ( .A ( chanx_right_in[10] ) , - .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_147 ) , - .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_148 ) , - .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_149 ) , - .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_126 ) , - .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( .A ( ropt_net_127 ) , - .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_128 ) , - .X ( ropt_net_142 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_129 ) , - .X ( ropt_net_144 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_130 ) , - .X ( ropt_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_131 ) , - .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_132 ) , - .X ( ropt_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_133 ) , - .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y0 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y0 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x82800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x128800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x138000y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x317400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x437000y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x506000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x542800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x552000y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x36800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x368000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x414000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x450800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x547400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x556600y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x101200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x248400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x331200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x446200y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x478400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x496800y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x69000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x78200y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x124200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x142600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x151800y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x197800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x207000y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x253000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x312800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x349600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x55200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x105800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x230000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x239200y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x285200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x437000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x570400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x588800y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x193200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x211600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x271400y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x243800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x303600y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x358800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x538200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x161000y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x280600y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x326600y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x372600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x450800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x515200y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x561200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x579600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x216200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x234600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x243800y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x322000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x331200y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x427800y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x147200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x165600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x174800y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x253000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x289800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x299000y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x110400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x193200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x317400y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x363400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x400200y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x460000y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x354200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x404800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x487600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x496800y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x165600y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x322000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x432400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x450800y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x188600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x225400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x243800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x326600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x335800y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x414000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x450800y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x575000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x285200y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x363400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x243800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x262200y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x308200y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x354200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x423200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x460000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x579600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x492200y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x570400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x188600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x317400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x335800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x588800y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x354200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x391000y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x478400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x496800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x220800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x303600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x312800y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x400200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x437000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x473800y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x515200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x533600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x542800y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x73600y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x161000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x197800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x234600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x253000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x262200y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x340400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x391000y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x478400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x496800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x202400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x239200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x285200y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x326600y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x414000y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x460000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x496800y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x538200y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x110400y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x156400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x174800y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x220800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x230000y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x276000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x473800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x492200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x82800y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x128800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x138000y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x312800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x349600y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x437000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x455400y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x239200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x473800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x492200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x165600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x202400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x262200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x280600y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x326600y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x147200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x289800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x308200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x317400y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x363400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x538200y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x188600y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x271400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x280600y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x326600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x386400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x404800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x414000y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x538200y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x239200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x345000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x501400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x510600y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__1__icv_in_design.pt.v b/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__1__icv_in_design.pt.v deleted file mode 100644 index 03a2b22..0000000 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__1__icv_in_design.pt.v +++ /dev/null @@ -1,1541 +0,0 @@ -// -// -// -// -// -// -module cbx_1__1__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__56 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__55 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__54 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__53 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__52 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__51 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__50 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__49 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__48 ( .A ( mem_out[3] ) , - .X ( net_net_72 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_90 ( .A ( net_net_72 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__47 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__46 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__45 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__44 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__43 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__42 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__41 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cbx_1__1_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , - chanx_left_out , chanx_right_out , bottom_grid_pin_0_ , - bottom_grid_pin_1_ , bottom_grid_pin_2_ , bottom_grid_pin_3_ , - bottom_grid_pin_4_ , bottom_grid_pin_5_ , bottom_grid_pin_6_ , - bottom_grid_pin_7_ , bottom_grid_pin_8_ , bottom_grid_pin_9_ , - bottom_grid_pin_10_ , bottom_grid_pin_11_ , bottom_grid_pin_12_ , - bottom_grid_pin_13_ , bottom_grid_pin_14_ , bottom_grid_pin_15_ , - ccff_tail , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , SC_OUT_BOT , - prog_clk__FEEDTHRU_1 ) ; -input [0:0] prog_clk ; -input [0:19] chanx_left_in ; -input [0:19] chanx_right_in ; -input [0:0] ccff_head ; -output [0:19] chanx_left_out ; -output [0:19] chanx_right_out ; -output [0:0] bottom_grid_pin_0_ ; -output [0:0] bottom_grid_pin_1_ ; -output [0:0] bottom_grid_pin_2_ ; -output [0:0] bottom_grid_pin_3_ ; -output [0:0] bottom_grid_pin_4_ ; -output [0:0] bottom_grid_pin_5_ ; -output [0:0] bottom_grid_pin_6_ ; -output [0:0] bottom_grid_pin_7_ ; -output [0:0] bottom_grid_pin_8_ ; -output [0:0] bottom_grid_pin_9_ ; -output [0:0] bottom_grid_pin_10_ ; -output [0:0] bottom_grid_pin_11_ ; -output [0:0] bottom_grid_pin_12_ ; -output [0:0] bottom_grid_pin_13_ ; -output [0:0] bottom_grid_pin_14_ ; -output [0:0] bottom_grid_pin_15_ ; -output [0:0] ccff_tail ; -input SC_IN_TOP ; -input SC_IN_BOT ; -output SC_OUT_TOP ; -output SC_OUT_BOT ; -output [0:0] prog_clk__FEEDTHRU_1 ; - -wire [0:3] mux_top_ipin_0_undriven_sram_inv ; -wire [0:3] mux_top_ipin_10_undriven_sram_inv ; -wire [0:3] mux_top_ipin_11_undriven_sram_inv ; -wire [0:3] mux_top_ipin_12_undriven_sram_inv ; -wire [0:3] mux_top_ipin_13_undriven_sram_inv ; -wire [0:3] mux_top_ipin_14_undriven_sram_inv ; -wire [0:3] mux_top_ipin_15_undriven_sram_inv ; -wire [0:3] mux_top_ipin_1_undriven_sram_inv ; -wire [0:3] mux_top_ipin_2_undriven_sram_inv ; -wire [0:3] mux_top_ipin_3_undriven_sram_inv ; -wire [0:3] mux_top_ipin_4_undriven_sram_inv ; -wire [0:3] mux_top_ipin_5_undriven_sram_inv ; -wire [0:3] mux_top_ipin_6_undriven_sram_inv ; -wire [0:3] mux_top_ipin_7_undriven_sram_inv ; -wire [0:3] mux_top_ipin_8_undriven_sram_inv ; -wire [0:3] mux_top_ipin_9_undriven_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:3] mux_tree_tapbuf_size10_2_sram ; -wire [0:3] mux_tree_tapbuf_size10_3_sram ; -wire [0:3] mux_tree_tapbuf_size10_4_sram ; -wire [0:3] mux_tree_tapbuf_size10_5_sram ; -wire [0:3] mux_tree_tapbuf_size10_6_sram ; -wire [0:3] mux_tree_tapbuf_size10_7_sram ; -wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:3] mux_tree_tapbuf_size8_2_sram ; -wire [0:3] mux_tree_tapbuf_size8_3_sram ; -wire [0:3] mux_tree_tapbuf_size8_4_sram ; -wire [0:3] mux_tree_tapbuf_size8_5_sram ; -wire [0:3] mux_tree_tapbuf_size8_6_sram ; -wire [0:3] mux_tree_tapbuf_size8_7_sram ; -wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ; -// - -assign SC_IN_TOP = SC_IN_BOT ; - -cbx_1__1__mux_tree_tapbuf_size10_0 mux_top_ipin_0 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , - chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , - chanx_right_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_top_ipin_0_undriven_sram_inv ) , - .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_104 ) ) ; -cbx_1__1__mux_tree_tapbuf_size10_4 mux_top_ipin_3 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , - chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , - chanx_right_in[19] } ) , - .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_top_ipin_3_undriven_sram_inv ) , - .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_105 ) ) ; -cbx_1__1__mux_tree_tapbuf_size10_5 mux_top_ipin_4 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , - chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[14] , - chanx_right_in[14] } ) , - .sram ( mux_tree_tapbuf_size10_2_sram ) , - .sram_inv ( mux_top_ipin_4_undriven_sram_inv ) , - .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_102 ) ) ; -cbx_1__1__mux_tree_tapbuf_size10_6 mux_top_ipin_7 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , - chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , - chanx_right_in[17] } ) , - .sram ( mux_tree_tapbuf_size10_3_sram ) , - .sram_inv ( mux_top_ipin_7_undriven_sram_inv ) , - .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_104 ) ) ; -cbx_1__1__mux_tree_tapbuf_size10 mux_top_ipin_8 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[8] , chanx_right_in[8] , - chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , - chanx_right_in[18] } ) , - .sram ( mux_tree_tapbuf_size10_4_sram ) , - .sram_inv ( mux_top_ipin_8_undriven_sram_inv ) , - .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_103 ) ) ; -cbx_1__1__mux_tree_tapbuf_size10_1 mux_top_ipin_11 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , - chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[15] , - chanx_right_in[15] } ) , - .sram ( mux_tree_tapbuf_size10_5_sram ) , - .sram_inv ( mux_top_ipin_11_undriven_sram_inv ) , - .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_105 ) ) ; -cbx_1__1__mux_tree_tapbuf_size10_2 mux_top_ipin_12 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , - chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[16] , - chanx_right_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_6_sram ) , - .sram_inv ( mux_top_ipin_12_undriven_sram_inv ) , - .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_103 ) ) ; -cbx_1__1__mux_tree_tapbuf_size10_3 mux_top_ipin_15 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , - chanx_left_in[15] , chanx_right_in[15] , chanx_left_in[19] , - chanx_right_in[19] } ) , - .sram ( mux_tree_tapbuf_size10_7_sram ) , - .sram_inv ( mux_top_ipin_15_undriven_sram_inv ) , - .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_105 ) ) ; -cbx_1__1__mux_tree_tapbuf_size10_mem_0 mem_top_ipin_0 ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; -cbx_1__1__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ; -cbx_1__1__mux_tree_tapbuf_size10_mem_5 mem_top_ipin_4 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ; -cbx_1__1__mux_tree_tapbuf_size10_mem_6 mem_top_ipin_7 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ; -cbx_1__1__mux_tree_tapbuf_size10_mem mem_top_ipin_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ; -cbx_1__1__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_11 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ; -cbx_1__1__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_12 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ; -cbx_1__1__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_15 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .ccff_tail ( { ropt_net_124 } ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_0 mux_top_ipin_1 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , - chanx_left_in[13] , chanx_right_in[13] } ) , - .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_top_ipin_1_undriven_sram_inv ) , - .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_105 ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_4 mux_top_ipin_2 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , - chanx_left_in[14] , chanx_right_in[14] } ) , - .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_top_ipin_2_undriven_sram_inv ) , - .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_102 ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_5 mux_top_ipin_5 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , - chanx_left_in[17] , chanx_right_in[17] } ) , - .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_top_ipin_5_undriven_sram_inv ) , - .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_104 ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_6 mux_top_ipin_6 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , - chanx_left_in[18] , chanx_right_in[18] } ) , - .sram ( mux_tree_tapbuf_size8_3_sram ) , - .sram_inv ( mux_top_ipin_6_undriven_sram_inv ) , - .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_103 ) ) ; -cbx_1__1__mux_tree_tapbuf_size8 mux_top_ipin_9 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , - chanx_left_in[13] , chanx_right_in[13] } ) , - .sram ( mux_tree_tapbuf_size8_4_sram ) , - .sram_inv ( mux_top_ipin_9_undriven_sram_inv ) , - .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_103 ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_1 mux_top_ipin_10 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , - chanx_left_in[14] , chanx_right_in[14] } ) , - .sram ( mux_tree_tapbuf_size8_5_sram ) , - .sram_inv ( mux_top_ipin_10_undriven_sram_inv ) , - .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_102 ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_2 mux_top_ipin_13 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , - chanx_left_in[17] , chanx_right_in[17] } ) , - .sram ( mux_tree_tapbuf_size8_6_sram ) , - .sram_inv ( mux_top_ipin_13_undriven_sram_inv ) , - .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_104 ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_3 mux_top_ipin_14 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , - chanx_left_in[18] , chanx_right_in[18] } ) , - .sram ( mux_tree_tapbuf_size8_7_sram ) , - .sram_inv ( mux_top_ipin_14_undriven_sram_inv ) , - .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_103 ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_mem_0 mem_top_ipin_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_mem_4 mem_top_ipin_2 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_mem_5 mem_top_ipin_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_mem_6 mem_top_ipin_6 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_3_sram ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_mem mem_top_ipin_9 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_4_sram ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_mem_1 mem_top_ipin_10 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_5_sram ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_mem_2 mem_top_ipin_13 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_6_sram ) ) ; -cbx_1__1__mux_tree_tapbuf_size8_mem_3 mem_top_ipin_14 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_7_sram ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chanx_left_in[0] ) , - .X ( chanx_right_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_134 ) , - .X ( chanx_left_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chanx_left_in[2] ) , - .X ( chanx_right_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__4 ( .A ( chanx_left_in[4] ) , - .X ( ropt_net_128 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_102 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_103 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__7 ( .A ( chanx_left_in[7] ) , - .X ( ropt_net_130 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_104 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_105 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chanx_left_in[10] ) , - .X ( ropt_net_133 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( ropt_net_135 ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__clkbuf_1 prog_clk_0__bip373 ( .A ( prog_clk[0] ) , - .X ( ctsbuf_net_1106 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( chanx_right_in[4] ) , - .X ( chanx_left_out[4] ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_326699 ( .A ( ctsbuf_net_1106 ) , - .X ( prog_clk__FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_136 ) , - .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( ropt_net_108 ) , - .X ( ropt_net_146 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chanx_left_in[17] ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_137 ) , - .X ( chanx_left_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_138 ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_right_in[0] ) , - .X ( chanx_left_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , - .X ( ropt_net_123 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chanx_right_in[2] ) , - .X ( chanx_left_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chanx_right_in[3] ) , - .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_728 ( .A ( chanx_left_in[13] ) , - .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chanx_right_in[5] ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_148 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chanx_right_in[7] ) , - .X ( ropt_net_145 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_110 ) , - .X ( ropt_net_141 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chanx_right_in[9] ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( chanx_right_in[15] ) , - .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_32__31 ( .A ( chanx_right_in[11] ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_134 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_126 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_35__34 ( .A ( chanx_right_in[14] ) , - .X ( ropt_net_132 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( chanx_left_in[9] ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_37__36 ( .A ( chanx_right_in[16] ) , - .X ( ropt_net_129 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_38__37 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_121 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_39__38 ( .A ( chanx_right_in[18] ) , - .X ( ropt_net_125 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( chanx_left_in[5] ) , - .X ( ropt_net_149 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_41__40 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_108 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_770 ( .A ( ropt_net_139 ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_59 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_131 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( chanx_left_in[18] ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_772 ( .A ( ropt_net_140 ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_774 ( .A ( ropt_net_141 ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_63 ( .A ( chanx_left_in[14] ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_64 ( .A ( chanx_left_in[15] ) , - .X ( ropt_net_110 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_116 ) , - .X ( ropt_net_135 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( .A ( ropt_net_142 ) , - .X ( chanx_right_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( ropt_net_143 ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_777 ( .A ( ropt_net_144 ) , - .X ( chanx_left_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( chanx_left_in[11] ) , - .X ( ropt_net_139 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_70 ( .A ( chanx_right_in[19] ) , - .X ( ropt_net_127 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( chanx_left_in[8] ) , - .X ( chanx_right_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( chanx_left_in[16] ) , - .X ( ropt_net_147 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_739 ( .A ( chanx_left_in[1] ) , - .X ( chanx_right_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_121 ) , - .X ( ropt_net_138 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( .A ( chanx_right_in[12] ) , - .X ( chanx_left_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_145 ) , - .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_79 ( .A ( chanx_left_in[19] ) , - .X ( ropt_net_116 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_123 ) , - .X ( ropt_net_137 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_124 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_125 ) , - .X ( ropt_net_136 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( chanx_left_in[12] ) , - .X ( chanx_right_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_146 ) , - .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_88 ( .A ( chanx_right_in[10] ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_147 ) , - .X ( chanx_right_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_148 ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_149 ) , - .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_126 ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( .A ( ropt_net_127 ) , - .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_128 ) , - .X ( ropt_net_142 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_129 ) , - .X ( ropt_net_144 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_130 ) , - .X ( ropt_net_143 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_131 ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_132 ) , - .X ( ropt_net_140 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_133 ) , - .X ( chanx_right_out[10] ) ) ; -endmodule - - diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__2__icv_in_design.fm.v b/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__2__icv_in_design.fm.v deleted file mode 100644 index d0ac78c..0000000 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__2__icv_in_design.fm.v +++ /dev/null @@ -1,1876 +0,0 @@ -// -// -// -// -// -// -module cbx_1__2__direct_interc ( in , out ) ; -input [0:0] in ; -output [0:0] out ; - -assign out[0] = in[0] ; -endmodule - - -module cbx_1__2__direct_interc_0 ( in , out ) ; -input [0:0] in ; -output [0:0] out ; -endmodule - - -module cbx_1__2__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( prog_clk , - ccff_head , ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:0] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_20__61 ( .A ( mem_out[0] ) , - .X ( net_net_76 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_76 ( .A ( net_net_76 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__2__EMBEDDED_IO ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , - FPGA_OUT , FPGA_DIR , p_abuf0 ) ; -input SOC_IN ; -output SOC_OUT ; -output SOC_DIR ; -output FPGA_IN ; -input FPGA_OUT ; -input FPGA_DIR ; -output p_abuf0 ; - -wire aps_rename_1_ ; - -assign SOC_OUT = FPGA_OUT ; - -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__59 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__60 ( .A ( FPGA_DIR ) , - .X ( aps_rename_1_ ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_75 ( .A ( aps_rename_1_ ) , - .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_63 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; -endmodule - - -module cbx_1__2__logical_tile_io_mode_physical__iopad ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] iopad_outpad ; -input [0:0] ccff_head ; -output [0:0] iopad_inpad ; -output [0:0] ccff_tail ; -output p_abuf0 ; - -wire [0:0] EMBEDDED_IO_0_en ; - -cbx_1__2__EMBEDDED_IO EMBEDDED_IO_0_ ( - .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , - .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , - .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , - .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__2__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) ) ; -endmodule - - -module cbx_1__2__logical_tile_io_mode_io_ ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , - ccff_tail , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] io_outpad ; -input [0:0] ccff_head ; -output [0:0] io_inpad ; -output [0:0] ccff_tail ; -output p_abuf0 ; - -cbx_1__2__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , - .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , - .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__2__direct_interc_0 direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; -cbx_1__2__direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( io_outpad ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__58 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__57 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__56 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__55 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__54 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__53 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__52 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__51 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__2__const1 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -cbx_1__2__const1 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cbx_1__2__const1_15 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -cbx_1__2__const1_15 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cbx_1__2__const1_14 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -cbx_1__2__const1_14 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cbx_1__2__const1_13 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -cbx_1__2__const1_13 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cbx_1__2__const1_12 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -cbx_1__2__const1_12 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cbx_1__2__const1_11 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -cbx_1__2__const1_11 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cbx_1__2__const1_10 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -cbx_1__2__const1_10 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cbx_1__2__const1_9 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -cbx_1__2__const1_9 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__50 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__49 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__48 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__47 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__46 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__45 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__44 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__43 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__42 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__2__const1_8 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -cbx_1__2__const1_8 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cbx_1__2__const1_7 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -cbx_1__2__const1_7 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cbx_1__2__const1_6 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -cbx_1__2__const1_6 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cbx_1__2__const1_5 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -cbx_1__2__const1_5 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cbx_1__2__const1_4 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -cbx_1__2__const1_4 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cbx_1__2__const1_3 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -cbx_1__2__const1_3 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cbx_1__2__const1_2 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -cbx_1__2__const1_2 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_64 ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module cbx_1__2__const1_1 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -cbx_1__2__const1_1 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cbx_1__2__const1_0 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -cbx_1__2__const1_0 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cbx_1__2_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , - chanx_left_out , chanx_right_out , top_grid_pin_0_ , bottom_grid_pin_0_ , - bottom_grid_pin_1_ , bottom_grid_pin_2_ , bottom_grid_pin_3_ , - bottom_grid_pin_4_ , bottom_grid_pin_5_ , bottom_grid_pin_6_ , - bottom_grid_pin_7_ , bottom_grid_pin_8_ , bottom_grid_pin_9_ , - bottom_grid_pin_10_ , bottom_grid_pin_11_ , bottom_grid_pin_12_ , - bottom_grid_pin_13_ , bottom_grid_pin_14_ , bottom_grid_pin_15_ , - ccff_tail , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , bottom_width_0_height_0__pin_0_ , - bottom_width_0_height_0__pin_1_upper , - bottom_width_0_height_0__pin_1_lower , SC_IN_TOP , SC_IN_BOT , - SC_OUT_TOP , SC_OUT_BOT , prog_clk__FEEDTHRU_1 , prog_clk__FEEDTHRU_2 ) ; -input [0:0] prog_clk ; -input [0:19] chanx_left_in ; -input [0:19] chanx_right_in ; -input [0:0] ccff_head ; -output [0:19] chanx_left_out ; -output [0:19] chanx_right_out ; -output [0:0] top_grid_pin_0_ ; -output [0:0] bottom_grid_pin_0_ ; -output [0:0] bottom_grid_pin_1_ ; -output [0:0] bottom_grid_pin_2_ ; -output [0:0] bottom_grid_pin_3_ ; -output [0:0] bottom_grid_pin_4_ ; -output [0:0] bottom_grid_pin_5_ ; -output [0:0] bottom_grid_pin_6_ ; -output [0:0] bottom_grid_pin_7_ ; -output [0:0] bottom_grid_pin_8_ ; -output [0:0] bottom_grid_pin_9_ ; -output [0:0] bottom_grid_pin_10_ ; -output [0:0] bottom_grid_pin_11_ ; -output [0:0] bottom_grid_pin_12_ ; -output [0:0] bottom_grid_pin_13_ ; -output [0:0] bottom_grid_pin_14_ ; -output [0:0] bottom_grid_pin_15_ ; -output [0:0] ccff_tail ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] bottom_width_0_height_0__pin_0_ ; -output [0:0] bottom_width_0_height_0__pin_1_upper ; -output [0:0] bottom_width_0_height_0__pin_1_lower ; -input SC_IN_TOP ; -input SC_IN_BOT ; -output SC_OUT_TOP ; -output SC_OUT_BOT ; -output [0:0] prog_clk__FEEDTHRU_1 ; -output [0:0] prog_clk__FEEDTHRU_2 ; - -wire ropt_net_112 ; -wire [0:3] mux_bottom_ipin_0_undriven_sram_inv ; -wire [0:3] mux_top_ipin_0_undriven_sram_inv ; -wire [0:3] mux_top_ipin_10_undriven_sram_inv ; -wire [0:3] mux_top_ipin_11_undriven_sram_inv ; -wire [0:3] mux_top_ipin_12_undriven_sram_inv ; -wire [0:3] mux_top_ipin_13_undriven_sram_inv ; -wire [0:3] mux_top_ipin_14_undriven_sram_inv ; -wire [0:3] mux_top_ipin_15_undriven_sram_inv ; -wire [0:3] mux_top_ipin_1_undriven_sram_inv ; -wire [0:3] mux_top_ipin_2_undriven_sram_inv ; -wire [0:3] mux_top_ipin_3_undriven_sram_inv ; -wire [0:3] mux_top_ipin_4_undriven_sram_inv ; -wire [0:3] mux_top_ipin_5_undriven_sram_inv ; -wire [0:3] mux_top_ipin_6_undriven_sram_inv ; -wire [0:3] mux_top_ipin_7_undriven_sram_inv ; -wire [0:3] mux_top_ipin_8_undriven_sram_inv ; -wire [0:3] mux_top_ipin_9_undriven_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:3] mux_tree_tapbuf_size10_2_sram ; -wire [0:3] mux_tree_tapbuf_size10_3_sram ; -wire [0:3] mux_tree_tapbuf_size10_4_sram ; -wire [0:3] mux_tree_tapbuf_size10_5_sram ; -wire [0:3] mux_tree_tapbuf_size10_6_sram ; -wire [0:3] mux_tree_tapbuf_size10_7_sram ; -wire [0:3] mux_tree_tapbuf_size10_8_sram ; -wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:3] mux_tree_tapbuf_size8_2_sram ; -wire [0:3] mux_tree_tapbuf_size8_3_sram ; -wire [0:3] mux_tree_tapbuf_size8_4_sram ; -wire [0:3] mux_tree_tapbuf_size8_5_sram ; -wire [0:3] mux_tree_tapbuf_size8_6_sram ; -wire [0:3] mux_tree_tapbuf_size8_7_sram ; -wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ; -// - -assign SC_IN_TOP = SC_IN_BOT ; - -cbx_1__2__mux_tree_tapbuf_size10_0 mux_bottom_ipin_0 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , - chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , - chanx_right_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_bottom_ipin_0_undriven_sram_inv ) , - .out ( top_grid_pin_0_ ) , .p0 ( optlc_net_108 ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_1 mux_top_ipin_0 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , - chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , - chanx_right_in[17] } ) , - .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_top_ipin_0_undriven_sram_inv ) , - .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_108 ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_5 mux_top_ipin_3 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , - chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[14] , - chanx_right_in[14] } ) , - .sram ( mux_tree_tapbuf_size10_2_sram ) , - .sram_inv ( mux_top_ipin_3_undriven_sram_inv ) , - .out ( { ropt_net_117 } ) , - .p0 ( optlc_net_107 ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_6 mux_top_ipin_4 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , - chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[15] , - chanx_right_in[15] } ) , - .sram ( mux_tree_tapbuf_size10_3_sram ) , - .sram_inv ( mux_top_ipin_4_undriven_sram_inv ) , - .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_108 ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_7 mux_top_ipin_7 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[8] , chanx_right_in[8] , - chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , - chanx_right_in[18] } ) , - .sram ( mux_tree_tapbuf_size10_4_sram ) , - .sram_inv ( mux_top_ipin_7_undriven_sram_inv ) , - .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_107 ) ) ; -cbx_1__2__mux_tree_tapbuf_size10 mux_top_ipin_8 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , - chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , - chanx_right_in[19] } ) , - .sram ( mux_tree_tapbuf_size10_5_sram ) , - .sram_inv ( mux_top_ipin_8_undriven_sram_inv ) , - .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_106 ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_2 mux_top_ipin_11 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , - chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[16] , - chanx_right_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_6_sram ) , - .sram_inv ( mux_top_ipin_11_undriven_sram_inv ) , - .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_106 ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_3 mux_top_ipin_12 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , - chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[17] , - chanx_right_in[17] } ) , - .sram ( mux_tree_tapbuf_size10_7_sram ) , - .sram_inv ( mux_top_ipin_12_undriven_sram_inv ) , - .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_108 ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_4 mux_top_ipin_15 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , - chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , - chanx_right_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_8_sram ) , - .sram_inv ( mux_top_ipin_15_undriven_sram_inv ) , - .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_108 ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_mem_0 mem_bottom_ipin_0 ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_0 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_mem_5 mem_top_ipin_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_mem_6 mem_top_ipin_4 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_mem_7 mem_top_ipin_7 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_mem mem_top_ipin_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_11 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_12 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_15 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , - .mem_out ( mux_tree_tapbuf_size10_8_sram ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_0 mux_top_ipin_1 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , - chanx_left_in[14] , chanx_right_in[14] } ) , - .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_top_ipin_1_undriven_sram_inv ) , - .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_109 ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_4 mux_top_ipin_2 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , - chanx_left_in[15] , chanx_right_in[15] } ) , - .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_top_ipin_2_undriven_sram_inv ) , - .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_106 ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_5 mux_top_ipin_5 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , - chanx_left_in[18] , chanx_right_in[18] } ) , - .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_top_ipin_5_undriven_sram_inv ) , - .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_107 ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_6 mux_top_ipin_6 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , - chanx_left_in[19] , chanx_right_in[19] } ) , - .sram ( mux_tree_tapbuf_size8_3_sram ) , - .sram_inv ( mux_top_ipin_6_undriven_sram_inv ) , - .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_107 ) ) ; -cbx_1__2__mux_tree_tapbuf_size8 mux_top_ipin_9 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , - chanx_left_in[14] , chanx_right_in[14] } ) , - .sram ( mux_tree_tapbuf_size8_4_sram ) , - .sram_inv ( mux_top_ipin_9_undriven_sram_inv ) , - .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_109 ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_1 mux_top_ipin_10 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , - chanx_left_in[15] , chanx_right_in[15] } ) , - .sram ( mux_tree_tapbuf_size8_5_sram ) , - .sram_inv ( mux_top_ipin_10_undriven_sram_inv ) , - .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_106 ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_2 mux_top_ipin_13 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , - chanx_left_in[18] , chanx_right_in[18] } ) , - .sram ( mux_tree_tapbuf_size8_6_sram ) , - .sram_inv ( mux_top_ipin_13_undriven_sram_inv ) , - .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_107 ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_3 mux_top_ipin_14 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , - chanx_left_in[19] , chanx_right_in[19] } ) , - .sram ( mux_tree_tapbuf_size8_7_sram ) , - .sram_inv ( mux_top_ipin_14_undriven_sram_inv ) , - .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_106 ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_mem_0 mem_top_ipin_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_mem_4 mem_top_ipin_2 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_mem_5 mem_top_ipin_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_mem_6 mem_top_ipin_6 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_3_sram ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_mem mem_top_ipin_9 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_4_sram ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_mem_1 mem_top_ipin_10 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_5_sram ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_mem_2 mem_top_ipin_13 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_6_sram ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_mem_3 mem_top_ipin_14 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_7_sram ) ) ; -cbx_1__2__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_114 } ) , - .io_outpad ( bottom_width_0_height_0__pin_0_ ) , - .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_3_ } ) , - .ccff_tail ( ccff_tail ) , .p_abuf0 ( ropt_net_112 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_106 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chanx_left_in[1] ) , - .X ( chanx_right_out[1] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_107 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chanx_left_in[4] ) , - .X ( chanx_right_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chanx_left_in[5] ) , - .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chanx_left_in[6] ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chanx_left_in[7] ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_108 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chanx_left_in[9] ) , - .X ( ropt_net_130 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_109 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_12__11 ( .A ( chanx_left_in[11] ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chanx_left_in[12] ) , - .X ( chanx_right_out[12] ) ) ; -sky130_fd_sc_hd__buf_2 prog_clk_0__bip377 ( .A ( prog_clk[0] ) , - .X ( ctsbuf_net_2111 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chanx_left_in[14] ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_112 ) , - .X ( ropt_net_137 ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_330707 ( .A ( ctsbuf_net_2111 ) , - .X ( prog_clk__FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chanx_left_in[17] ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_132 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_20__19 ( .A ( chanx_left_in[19] ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_right_in[0] ) , - .X ( ropt_net_131 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , - .X ( ropt_net_134 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chanx_right_in[2] ) , - .X ( ropt_net_147 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chanx_right_in[3] ) , - .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__24 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_129 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chanx_right_in[5] ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_331708 ( .A ( ctsbuf_net_2111 ) , - .X ( prog_clk__FEEDTHRU_2[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chanx_right_in[7] ) , - .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( .A ( chanx_right_in[6] ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_114 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( ropt_net_115 ) , - .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_138 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_33__32 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_127 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_117 ) , - .X ( ropt_net_141 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_137 ) , - .X ( bottom_width_0_height_0__pin_1_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_741 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_146 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_37__36 ( .A ( chanx_right_in[16] ) , - .X ( chanx_left_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_119 ) , - .X ( chanx_right_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_39__38 ( .A ( chanx_right_in[18] ) , - .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_40__39 ( .A ( chanx_right_in[19] ) , - .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_41__40 ( .A ( aps_rename_3_ ) , - .X ( ropt_net_121 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_42__41 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_115 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_66 ( .A ( chanx_left_in[0] ) , - .X ( chanx_right_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_744 ( .A ( chanx_right_in[14] ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_138 ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( ropt_net_139 ) , - .X ( chanx_left_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_121 ) , - .X ( ropt_net_142 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_780 ( .A ( ropt_net_140 ) , - .X ( chanx_left_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_785 ( .A ( ropt_net_141 ) , - .X ( bottom_grid_pin_3_[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_786 ( .A ( ropt_net_142 ) , - .X ( bottom_width_0_height_0__pin_1_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_143 ) , - .X ( chanx_left_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_139 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_79 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_119 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_750 ( .A ( chanx_left_in[13] ) , - .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_124 ) , - .X ( ropt_net_145 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_752 ( .A ( chanx_left_in[16] ) , - .X ( chanx_right_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( ropt_net_144 ) , - .X ( chanx_right_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_753 ( .A ( chanx_left_in[10] ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_88 ( .A ( chanx_left_in[15] ) , - .X ( ropt_net_124 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( ropt_net_145 ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_90 ( .A ( chanx_right_in[9] ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_146 ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_92 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_133 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_93 ( .A ( chanx_right_in[13] ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_94 ( .A ( chanx_right_in[15] ) , - .X ( ropt_net_135 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_96 ( .A ( chanx_left_in[2] ) , - .X ( ropt_net_128 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_754 ( .A ( ropt_net_127 ) , - .X ( chanx_left_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_147 ) , - .X ( chanx_left_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_128 ) , - .X ( ropt_net_144 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_129 ) , - .X ( ropt_net_143 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_130 ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_131 ) , - .X ( chanx_left_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_132 ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_133 ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_134 ) , - .X ( ropt_net_140 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_135 ) , - .X ( chanx_left_out[15] ) ) ; -endmodule - - diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__2__icv_in_design.lvs.v b/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__2__icv_in_design.lvs.v deleted file mode 100644 index 9f421da..0000000 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__2__icv_in_design.lvs.v +++ /dev/null @@ -1,2756 +0,0 @@ -// -// -// -// -// -// -module cbx_1__2__direct_interc ( in , out ) ; -input [0:0] in ; -output [0:0] out ; - -assign out[0] = in[0] ; -endmodule - - -module cbx_1__2__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( prog_clk , - ccff_head , ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:0] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_20__61 ( .A ( mem_out[0] ) , - .X ( net_net_76 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_76 ( .A ( net_net_76 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__2__EMBEDDED_IO ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , - FPGA_OUT , FPGA_DIR , p_abuf0 , VDD , VSS ) ; -input SOC_IN ; -output SOC_OUT ; -output SOC_DIR ; -output FPGA_IN ; -input FPGA_OUT ; -input FPGA_DIR ; -output p_abuf0 ; -input VDD ; -input VSS ; - -supply1 VDD ; -wire aps_rename_1_ ; -supply0 VSS ; - -assign SOC_OUT = FPGA_OUT ; - -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__59 ( .A ( SOC_IN ) , .X ( FPGA_IN ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__60 ( .A ( FPGA_DIR ) , - .X ( aps_rename_1_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_75 ( .A ( aps_rename_1_ ) , - .X ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_63 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__2__logical_tile_io_mode_physical__iopad ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , VDD , VSS , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] iopad_outpad ; -input [0:0] ccff_head ; -output [0:0] iopad_inpad ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; -output p_abuf0 ; - -wire [0:0] EMBEDDED_IO_0_en ; -supply1 VDD ; -supply0 VSS ; - -cbx_1__2__EMBEDDED_IO EMBEDDED_IO_0_ ( - .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , - .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , - .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , - .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -cbx_1__2__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -endmodule - - -module cbx_1__2__logical_tile_io_mode_io_ ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , - ccff_tail , VDD , VSS , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] io_outpad ; -input [0:0] ccff_head ; -output [0:0] io_inpad ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; -output p_abuf0 ; - -supply1 VDD ; -supply0 VSS ; - -cbx_1__2__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , - .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , - .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__2__direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( io_outpad ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__58 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__57 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__56 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__55 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__54 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__53 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__52 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__51 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__50 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__49 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__48 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__47 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__46 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__45 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__44 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__43 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__42 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_64 ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__2_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , - chanx_left_out , chanx_right_out , top_grid_pin_0_ , bottom_grid_pin_0_ , - bottom_grid_pin_1_ , bottom_grid_pin_2_ , bottom_grid_pin_3_ , - bottom_grid_pin_4_ , bottom_grid_pin_5_ , bottom_grid_pin_6_ , - bottom_grid_pin_7_ , bottom_grid_pin_8_ , bottom_grid_pin_9_ , - bottom_grid_pin_10_ , bottom_grid_pin_11_ , bottom_grid_pin_12_ , - bottom_grid_pin_13_ , bottom_grid_pin_14_ , bottom_grid_pin_15_ , - ccff_tail , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , bottom_width_0_height_0__pin_0_ , - bottom_width_0_height_0__pin_1_upper , - bottom_width_0_height_0__pin_1_lower , SC_IN_TOP , SC_IN_BOT , - SC_OUT_TOP , SC_OUT_BOT , VDD , VSS , prog_clk__FEEDTHRU_1 , - prog_clk__FEEDTHRU_2 ) ; -input [0:0] prog_clk ; -input [0:19] chanx_left_in ; -input [0:19] chanx_right_in ; -input [0:0] ccff_head ; -output [0:19] chanx_left_out ; -output [0:19] chanx_right_out ; -output [0:0] top_grid_pin_0_ ; -output [0:0] bottom_grid_pin_0_ ; -output [0:0] bottom_grid_pin_1_ ; -output [0:0] bottom_grid_pin_2_ ; -output [0:0] bottom_grid_pin_3_ ; -output [0:0] bottom_grid_pin_4_ ; -output [0:0] bottom_grid_pin_5_ ; -output [0:0] bottom_grid_pin_6_ ; -output [0:0] bottom_grid_pin_7_ ; -output [0:0] bottom_grid_pin_8_ ; -output [0:0] bottom_grid_pin_9_ ; -output [0:0] bottom_grid_pin_10_ ; -output [0:0] bottom_grid_pin_11_ ; -output [0:0] bottom_grid_pin_12_ ; -output [0:0] bottom_grid_pin_13_ ; -output [0:0] bottom_grid_pin_14_ ; -output [0:0] bottom_grid_pin_15_ ; -output [0:0] ccff_tail ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] bottom_width_0_height_0__pin_0_ ; -output [0:0] bottom_width_0_height_0__pin_1_upper ; -output [0:0] bottom_width_0_height_0__pin_1_lower ; -input SC_IN_TOP ; -input SC_IN_BOT ; -output SC_OUT_TOP ; -output SC_OUT_BOT ; -input VDD ; -input VSS ; -output [0:0] prog_clk__FEEDTHRU_1 ; -output [0:0] prog_clk__FEEDTHRU_2 ; - -wire ropt_net_112 ; -wire [0:3] mux_bottom_ipin_0_undriven_sram_inv ; -wire [0:3] mux_top_ipin_0_undriven_sram_inv ; -wire [0:3] mux_top_ipin_10_undriven_sram_inv ; -wire [0:3] mux_top_ipin_11_undriven_sram_inv ; -wire [0:3] mux_top_ipin_12_undriven_sram_inv ; -wire [0:3] mux_top_ipin_13_undriven_sram_inv ; -wire [0:3] mux_top_ipin_14_undriven_sram_inv ; -wire [0:3] mux_top_ipin_15_undriven_sram_inv ; -wire [0:3] mux_top_ipin_1_undriven_sram_inv ; -wire [0:3] mux_top_ipin_2_undriven_sram_inv ; -wire [0:3] mux_top_ipin_3_undriven_sram_inv ; -wire [0:3] mux_top_ipin_4_undriven_sram_inv ; -wire [0:3] mux_top_ipin_5_undriven_sram_inv ; -wire [0:3] mux_top_ipin_6_undriven_sram_inv ; -wire [0:3] mux_top_ipin_7_undriven_sram_inv ; -wire [0:3] mux_top_ipin_8_undriven_sram_inv ; -wire [0:3] mux_top_ipin_9_undriven_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:3] mux_tree_tapbuf_size10_2_sram ; -wire [0:3] mux_tree_tapbuf_size10_3_sram ; -wire [0:3] mux_tree_tapbuf_size10_4_sram ; -wire [0:3] mux_tree_tapbuf_size10_5_sram ; -wire [0:3] mux_tree_tapbuf_size10_6_sram ; -wire [0:3] mux_tree_tapbuf_size10_7_sram ; -wire [0:3] mux_tree_tapbuf_size10_8_sram ; -wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:3] mux_tree_tapbuf_size8_2_sram ; -wire [0:3] mux_tree_tapbuf_size8_3_sram ; -wire [0:3] mux_tree_tapbuf_size8_4_sram ; -wire [0:3] mux_tree_tapbuf_size8_5_sram ; -wire [0:3] mux_tree_tapbuf_size8_6_sram ; -wire [0:3] mux_tree_tapbuf_size8_7_sram ; -wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ; -supply1 VDD ; -supply0 VSS ; -// - -assign SC_IN_TOP = SC_IN_BOT ; - -cbx_1__2__mux_tree_tapbuf_size10_0 mux_bottom_ipin_0 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , - chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , - chanx_right_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_bottom_ipin_0_undriven_sram_inv ) , - .out ( top_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_108 ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_1 mux_top_ipin_0 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , - chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , - chanx_right_in[17] } ) , - .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_top_ipin_0_undriven_sram_inv ) , - .out ( bottom_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_108 ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_5 mux_top_ipin_3 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , - chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[14] , - chanx_right_in[14] } ) , - .sram ( mux_tree_tapbuf_size10_2_sram ) , - .sram_inv ( mux_top_ipin_3_undriven_sram_inv ) , - .out ( { ropt_net_117 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_107 ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_6 mux_top_ipin_4 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , - chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[15] , - chanx_right_in[15] } ) , - .sram ( mux_tree_tapbuf_size10_3_sram ) , - .sram_inv ( mux_top_ipin_4_undriven_sram_inv ) , - .out ( bottom_grid_pin_4_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_108 ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_7 mux_top_ipin_7 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[8] , chanx_right_in[8] , - chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , - chanx_right_in[18] } ) , - .sram ( mux_tree_tapbuf_size10_4_sram ) , - .sram_inv ( mux_top_ipin_7_undriven_sram_inv ) , - .out ( bottom_grid_pin_7_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_107 ) ) ; -cbx_1__2__mux_tree_tapbuf_size10 mux_top_ipin_8 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , - chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , - chanx_right_in[19] } ) , - .sram ( mux_tree_tapbuf_size10_5_sram ) , - .sram_inv ( mux_top_ipin_8_undriven_sram_inv ) , - .out ( bottom_grid_pin_8_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_106 ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_2 mux_top_ipin_11 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , - chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[16] , - chanx_right_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_6_sram ) , - .sram_inv ( mux_top_ipin_11_undriven_sram_inv ) , - .out ( bottom_grid_pin_11_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_106 ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_3 mux_top_ipin_12 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , - chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[17] , - chanx_right_in[17] } ) , - .sram ( mux_tree_tapbuf_size10_7_sram ) , - .sram_inv ( mux_top_ipin_12_undriven_sram_inv ) , - .out ( bottom_grid_pin_12_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_108 ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_4 mux_top_ipin_15 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , - chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , - chanx_right_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_8_sram ) , - .sram_inv ( mux_top_ipin_15_undriven_sram_inv ) , - .out ( bottom_grid_pin_15_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_108 ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_mem_0 mem_bottom_ipin_0 ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_0 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_mem_5 mem_top_ipin_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_mem_6 mem_top_ipin_4 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_mem_7 mem_top_ipin_7 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_mem mem_top_ipin_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_11 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_12 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_15 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , - .mem_out ( mux_tree_tapbuf_size10_8_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_0 mux_top_ipin_1 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , - chanx_left_in[14] , chanx_right_in[14] } ) , - .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_top_ipin_1_undriven_sram_inv ) , - .out ( bottom_grid_pin_1_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_109 ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_4 mux_top_ipin_2 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , - chanx_left_in[15] , chanx_right_in[15] } ) , - .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_top_ipin_2_undriven_sram_inv ) , - .out ( bottom_grid_pin_2_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_106 ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_5 mux_top_ipin_5 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , - chanx_left_in[18] , chanx_right_in[18] } ) , - .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_top_ipin_5_undriven_sram_inv ) , - .out ( bottom_grid_pin_5_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_107 ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_6 mux_top_ipin_6 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , - chanx_left_in[19] , chanx_right_in[19] } ) , - .sram ( mux_tree_tapbuf_size8_3_sram ) , - .sram_inv ( mux_top_ipin_6_undriven_sram_inv ) , - .out ( bottom_grid_pin_6_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_107 ) ) ; -cbx_1__2__mux_tree_tapbuf_size8 mux_top_ipin_9 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , - chanx_left_in[14] , chanx_right_in[14] } ) , - .sram ( mux_tree_tapbuf_size8_4_sram ) , - .sram_inv ( mux_top_ipin_9_undriven_sram_inv ) , - .out ( bottom_grid_pin_9_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_109 ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_1 mux_top_ipin_10 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , - chanx_left_in[15] , chanx_right_in[15] } ) , - .sram ( mux_tree_tapbuf_size8_5_sram ) , - .sram_inv ( mux_top_ipin_10_undriven_sram_inv ) , - .out ( bottom_grid_pin_10_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_106 ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_2 mux_top_ipin_13 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , - chanx_left_in[18] , chanx_right_in[18] } ) , - .sram ( mux_tree_tapbuf_size8_6_sram ) , - .sram_inv ( mux_top_ipin_13_undriven_sram_inv ) , - .out ( bottom_grid_pin_13_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_107 ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_3 mux_top_ipin_14 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , - chanx_left_in[19] , chanx_right_in[19] } ) , - .sram ( mux_tree_tapbuf_size8_7_sram ) , - .sram_inv ( mux_top_ipin_14_undriven_sram_inv ) , - .out ( bottom_grid_pin_14_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_106 ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_mem_0 mem_top_ipin_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_mem_4 mem_top_ipin_2 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_mem_5 mem_top_ipin_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_mem_6 mem_top_ipin_6 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_mem mem_top_ipin_9 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_mem_1 mem_top_ipin_10 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_mem_2 mem_top_ipin_13 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_mem_3 mem_top_ipin_14 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__2__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_114 } ) , - .io_outpad ( bottom_width_0_height_0__pin_0_ ) , - .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_3_ } ) , - .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf0 ( ropt_net_112 ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1618 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1619 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1620 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1621 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1622 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1623 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1624 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1625 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1626 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1627 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1628 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1629 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1630 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1631 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1632 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1633 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1634 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chanx_left_in[1] ) , - .X ( chanx_right_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , - .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chanx_left_in[4] ) , - .X ( chanx_right_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chanx_left_in[5] ) , - .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chanx_left_in[6] ) , - .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chanx_left_in[7] ) , - .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chanx_left_in[9] ) , - .X ( ropt_net_130 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_12__11 ( .A ( chanx_left_in[11] ) , - .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chanx_left_in[12] ) , - .X ( chanx_right_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_2 prog_clk_0__bip377 ( .A ( prog_clk[0] ) , - .X ( ctsbuf_net_2111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chanx_left_in[14] ) , - .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_112 ) , - .X ( ropt_net_137 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_330707 ( .A ( ctsbuf_net_2111 ) , - .X ( prog_clk__FEEDTHRU_1[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chanx_left_in[17] ) , - .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_20__19 ( .A ( chanx_left_in[19] ) , - .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_right_in[0] ) , - .X ( ropt_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , - .X ( ropt_net_134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chanx_right_in[2] ) , - .X ( ropt_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chanx_right_in[3] ) , - .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__24 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chanx_right_in[5] ) , - .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_331708 ( .A ( ctsbuf_net_2111 ) , - .X ( prog_clk__FEEDTHRU_2[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chanx_right_in[7] ) , - .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( .A ( chanx_right_in[6] ) , - .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_114 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( ropt_net_115 ) , - .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_138 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_33__32 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_117 ) , - .X ( ropt_net_141 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_137 ) , - .X ( bottom_width_0_height_0__pin_1_upper[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_741 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_37__36 ( .A ( chanx_right_in[16] ) , - .X ( chanx_left_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_119 ) , - .X ( chanx_right_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_39__38 ( .A ( chanx_right_in[18] ) , - .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_40__39 ( .A ( chanx_right_in[19] ) , - .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_41__40 ( .A ( aps_rename_3_ ) , - .X ( ropt_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_42__41 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_115 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_66 ( .A ( chanx_left_in[0] ) , - .X ( chanx_right_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_744 ( .A ( chanx_right_in[14] ) , - .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_138 ) , - .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( ropt_net_139 ) , - .X ( chanx_left_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_121 ) , - .X ( ropt_net_142 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_780 ( .A ( ropt_net_140 ) , - .X ( chanx_left_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_785 ( .A ( ropt_net_141 ) , - .X ( bottom_grid_pin_3_[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_786 ( .A ( ropt_net_142 ) , - .X ( bottom_width_0_height_0__pin_1_lower[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_143 ) , - .X ( chanx_left_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_139 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_79 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_119 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_750 ( .A ( chanx_left_in[13] ) , - .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_124 ) , - .X ( ropt_net_145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_752 ( .A ( chanx_left_in[16] ) , - .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( ropt_net_144 ) , - .X ( chanx_right_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_753 ( .A ( chanx_left_in[10] ) , - .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_88 ( .A ( chanx_left_in[15] ) , - .X ( ropt_net_124 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( ropt_net_145 ) , - .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_90 ( .A ( chanx_right_in[9] ) , - .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_146 ) , - .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_92 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_93 ( .A ( chanx_right_in[13] ) , - .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_94 ( .A ( chanx_right_in[15] ) , - .X ( ropt_net_135 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_96 ( .A ( chanx_left_in[2] ) , - .X ( ropt_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_754 ( .A ( ropt_net_127 ) , - .X ( chanx_left_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_147 ) , - .X ( chanx_left_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_128 ) , - .X ( ropt_net_144 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_129 ) , - .X ( ropt_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_130 ) , - .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_131 ) , - .X ( chanx_left_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_132 ) , - .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_133 ) , - .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_134 ) , - .X ( ropt_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_135 ) , - .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y0 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y0 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x266800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x303600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x349600y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x437000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x483000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x243800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x368000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x414000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x460000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x496800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x515200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x524400y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x170200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x188600y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x391000y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x147200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x207000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x308200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x317400y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x478400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x538200y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x73600y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x225400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x285200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x294400y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x400200y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x455400y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x193200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x253000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x335800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x193200y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x271400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x234600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x575000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x262200y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x303600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x322000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x202400y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x579600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x73600y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x119600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x211600y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x561200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x579600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x197800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x234600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x441600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x492200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x510600y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x529000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x538200y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x161000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x179400y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x575000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x73600y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x253000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x271400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x322000y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x455400y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x579600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x326600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x243800y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x289800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x432400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x119600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x156400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x239200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x82800y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x234600y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x542800y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x151800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x161000y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x358800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x400200y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x441600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x450800y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x496800y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x193200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x202400y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x478400y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x225400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x404800y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x455400y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x501400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x519800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x529000y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x225400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x271400y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x354200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x363400y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x409400y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x487600y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x119600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x506000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x515200y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x561200y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x644000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x202400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x220800y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x266800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x358800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x423200y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x469200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x570400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x588800y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x184000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x234600y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x312800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x331200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x432400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x552000y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x285200y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x423200y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x542800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x243800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x253000y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x400200y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x515200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x524400y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x602600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x639400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x593400y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__2__icv_in_design.pt.v b/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__2__icv_in_design.pt.v deleted file mode 100644 index 90762f8..0000000 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__2__icv_in_design.pt.v +++ /dev/null @@ -1,1748 +0,0 @@ -// -// -// -// -// -// -module cbx_1__2__direct_interc ( in , out ) ; -input [0:0] in ; -output [0:0] out ; - -assign out[0] = in[0] ; -endmodule - - -module cbx_1__2__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( prog_clk , - ccff_head , ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:0] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_20__61 ( .A ( mem_out[0] ) , - .X ( net_net_76 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_76 ( .A ( net_net_76 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__2__EMBEDDED_IO ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , - FPGA_OUT , FPGA_DIR , p_abuf0 ) ; -input SOC_IN ; -output SOC_OUT ; -output SOC_DIR ; -output FPGA_IN ; -input FPGA_OUT ; -input FPGA_DIR ; -output p_abuf0 ; - -wire aps_rename_1_ ; - -assign SOC_OUT = FPGA_OUT ; - -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__59 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__60 ( .A ( FPGA_DIR ) , - .X ( aps_rename_1_ ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_75 ( .A ( aps_rename_1_ ) , - .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_63 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; -endmodule - - -module cbx_1__2__logical_tile_io_mode_physical__iopad ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] iopad_outpad ; -input [0:0] ccff_head ; -output [0:0] iopad_inpad ; -output [0:0] ccff_tail ; -output p_abuf0 ; - -wire [0:0] EMBEDDED_IO_0_en ; - -cbx_1__2__EMBEDDED_IO EMBEDDED_IO_0_ ( - .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , - .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , - .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , - .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__2__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) ) ; -endmodule - - -module cbx_1__2__logical_tile_io_mode_io_ ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , - ccff_tail , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] io_outpad ; -input [0:0] ccff_head ; -output [0:0] io_inpad ; -output [0:0] ccff_tail ; -output p_abuf0 ; - -cbx_1__2__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , - .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , - .p_abuf0 ( p_abuf0 ) ) ; -cbx_1__2__direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( io_outpad ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__58 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__57 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__56 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__55 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__54 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__53 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__52 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__51 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__50 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__49 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__48 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__47 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__46 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__45 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__44 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__43 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__42 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_64 ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cbx_1__2__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cbx_1__2_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , - chanx_left_out , chanx_right_out , top_grid_pin_0_ , bottom_grid_pin_0_ , - bottom_grid_pin_1_ , bottom_grid_pin_2_ , bottom_grid_pin_3_ , - bottom_grid_pin_4_ , bottom_grid_pin_5_ , bottom_grid_pin_6_ , - bottom_grid_pin_7_ , bottom_grid_pin_8_ , bottom_grid_pin_9_ , - bottom_grid_pin_10_ , bottom_grid_pin_11_ , bottom_grid_pin_12_ , - bottom_grid_pin_13_ , bottom_grid_pin_14_ , bottom_grid_pin_15_ , - ccff_tail , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , bottom_width_0_height_0__pin_0_ , - bottom_width_0_height_0__pin_1_upper , - bottom_width_0_height_0__pin_1_lower , SC_IN_TOP , SC_IN_BOT , - SC_OUT_TOP , SC_OUT_BOT , prog_clk__FEEDTHRU_1 , prog_clk__FEEDTHRU_2 ) ; -input [0:0] prog_clk ; -input [0:19] chanx_left_in ; -input [0:19] chanx_right_in ; -input [0:0] ccff_head ; -output [0:19] chanx_left_out ; -output [0:19] chanx_right_out ; -output [0:0] top_grid_pin_0_ ; -output [0:0] bottom_grid_pin_0_ ; -output [0:0] bottom_grid_pin_1_ ; -output [0:0] bottom_grid_pin_2_ ; -output [0:0] bottom_grid_pin_3_ ; -output [0:0] bottom_grid_pin_4_ ; -output [0:0] bottom_grid_pin_5_ ; -output [0:0] bottom_grid_pin_6_ ; -output [0:0] bottom_grid_pin_7_ ; -output [0:0] bottom_grid_pin_8_ ; -output [0:0] bottom_grid_pin_9_ ; -output [0:0] bottom_grid_pin_10_ ; -output [0:0] bottom_grid_pin_11_ ; -output [0:0] bottom_grid_pin_12_ ; -output [0:0] bottom_grid_pin_13_ ; -output [0:0] bottom_grid_pin_14_ ; -output [0:0] bottom_grid_pin_15_ ; -output [0:0] ccff_tail ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] bottom_width_0_height_0__pin_0_ ; -output [0:0] bottom_width_0_height_0__pin_1_upper ; -output [0:0] bottom_width_0_height_0__pin_1_lower ; -input SC_IN_TOP ; -input SC_IN_BOT ; -output SC_OUT_TOP ; -output SC_OUT_BOT ; -output [0:0] prog_clk__FEEDTHRU_1 ; -output [0:0] prog_clk__FEEDTHRU_2 ; - -wire ropt_net_112 ; -wire [0:3] mux_bottom_ipin_0_undriven_sram_inv ; -wire [0:3] mux_top_ipin_0_undriven_sram_inv ; -wire [0:3] mux_top_ipin_10_undriven_sram_inv ; -wire [0:3] mux_top_ipin_11_undriven_sram_inv ; -wire [0:3] mux_top_ipin_12_undriven_sram_inv ; -wire [0:3] mux_top_ipin_13_undriven_sram_inv ; -wire [0:3] mux_top_ipin_14_undriven_sram_inv ; -wire [0:3] mux_top_ipin_15_undriven_sram_inv ; -wire [0:3] mux_top_ipin_1_undriven_sram_inv ; -wire [0:3] mux_top_ipin_2_undriven_sram_inv ; -wire [0:3] mux_top_ipin_3_undriven_sram_inv ; -wire [0:3] mux_top_ipin_4_undriven_sram_inv ; -wire [0:3] mux_top_ipin_5_undriven_sram_inv ; -wire [0:3] mux_top_ipin_6_undriven_sram_inv ; -wire [0:3] mux_top_ipin_7_undriven_sram_inv ; -wire [0:3] mux_top_ipin_8_undriven_sram_inv ; -wire [0:3] mux_top_ipin_9_undriven_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:3] mux_tree_tapbuf_size10_2_sram ; -wire [0:3] mux_tree_tapbuf_size10_3_sram ; -wire [0:3] mux_tree_tapbuf_size10_4_sram ; -wire [0:3] mux_tree_tapbuf_size10_5_sram ; -wire [0:3] mux_tree_tapbuf_size10_6_sram ; -wire [0:3] mux_tree_tapbuf_size10_7_sram ; -wire [0:3] mux_tree_tapbuf_size10_8_sram ; -wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:3] mux_tree_tapbuf_size8_2_sram ; -wire [0:3] mux_tree_tapbuf_size8_3_sram ; -wire [0:3] mux_tree_tapbuf_size8_4_sram ; -wire [0:3] mux_tree_tapbuf_size8_5_sram ; -wire [0:3] mux_tree_tapbuf_size8_6_sram ; -wire [0:3] mux_tree_tapbuf_size8_7_sram ; -wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ; -// - -assign SC_IN_TOP = SC_IN_BOT ; - -cbx_1__2__mux_tree_tapbuf_size10_0 mux_bottom_ipin_0 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , - chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , - chanx_right_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_bottom_ipin_0_undriven_sram_inv ) , - .out ( top_grid_pin_0_ ) , .p0 ( optlc_net_108 ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_1 mux_top_ipin_0 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , - chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , - chanx_right_in[17] } ) , - .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_top_ipin_0_undriven_sram_inv ) , - .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_108 ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_5 mux_top_ipin_3 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , - chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[14] , - chanx_right_in[14] } ) , - .sram ( mux_tree_tapbuf_size10_2_sram ) , - .sram_inv ( mux_top_ipin_3_undriven_sram_inv ) , - .out ( { ropt_net_117 } ) , - .p0 ( optlc_net_107 ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_6 mux_top_ipin_4 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , - chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[15] , - chanx_right_in[15] } ) , - .sram ( mux_tree_tapbuf_size10_3_sram ) , - .sram_inv ( mux_top_ipin_4_undriven_sram_inv ) , - .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_108 ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_7 mux_top_ipin_7 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[8] , chanx_right_in[8] , - chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , - chanx_right_in[18] } ) , - .sram ( mux_tree_tapbuf_size10_4_sram ) , - .sram_inv ( mux_top_ipin_7_undriven_sram_inv ) , - .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_107 ) ) ; -cbx_1__2__mux_tree_tapbuf_size10 mux_top_ipin_8 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , - chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , - chanx_right_in[19] } ) , - .sram ( mux_tree_tapbuf_size10_5_sram ) , - .sram_inv ( mux_top_ipin_8_undriven_sram_inv ) , - .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_106 ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_2 mux_top_ipin_11 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , - chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[16] , - chanx_right_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_6_sram ) , - .sram_inv ( mux_top_ipin_11_undriven_sram_inv ) , - .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_106 ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_3 mux_top_ipin_12 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , - chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[17] , - chanx_right_in[17] } ) , - .sram ( mux_tree_tapbuf_size10_7_sram ) , - .sram_inv ( mux_top_ipin_12_undriven_sram_inv ) , - .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_108 ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_4 mux_top_ipin_15 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , - chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , - chanx_right_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_8_sram ) , - .sram_inv ( mux_top_ipin_15_undriven_sram_inv ) , - .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_108 ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_mem_0 mem_bottom_ipin_0 ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_0 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_mem_5 mem_top_ipin_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_mem_6 mem_top_ipin_4 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_mem_7 mem_top_ipin_7 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_mem mem_top_ipin_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_11 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_12 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ; -cbx_1__2__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_15 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , - .mem_out ( mux_tree_tapbuf_size10_8_sram ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_0 mux_top_ipin_1 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , - chanx_left_in[14] , chanx_right_in[14] } ) , - .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_top_ipin_1_undriven_sram_inv ) , - .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_109 ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_4 mux_top_ipin_2 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , - chanx_left_in[15] , chanx_right_in[15] } ) , - .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_top_ipin_2_undriven_sram_inv ) , - .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_106 ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_5 mux_top_ipin_5 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , - chanx_left_in[18] , chanx_right_in[18] } ) , - .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_top_ipin_5_undriven_sram_inv ) , - .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_107 ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_6 mux_top_ipin_6 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , - chanx_left_in[19] , chanx_right_in[19] } ) , - .sram ( mux_tree_tapbuf_size8_3_sram ) , - .sram_inv ( mux_top_ipin_6_undriven_sram_inv ) , - .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_107 ) ) ; -cbx_1__2__mux_tree_tapbuf_size8 mux_top_ipin_9 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , - chanx_left_in[14] , chanx_right_in[14] } ) , - .sram ( mux_tree_tapbuf_size8_4_sram ) , - .sram_inv ( mux_top_ipin_9_undriven_sram_inv ) , - .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_109 ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_1 mux_top_ipin_10 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , - chanx_left_in[15] , chanx_right_in[15] } ) , - .sram ( mux_tree_tapbuf_size8_5_sram ) , - .sram_inv ( mux_top_ipin_10_undriven_sram_inv ) , - .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_106 ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_2 mux_top_ipin_13 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , - chanx_left_in[18] , chanx_right_in[18] } ) , - .sram ( mux_tree_tapbuf_size8_6_sram ) , - .sram_inv ( mux_top_ipin_13_undriven_sram_inv ) , - .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_107 ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_3 mux_top_ipin_14 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , - chanx_left_in[19] , chanx_right_in[19] } ) , - .sram ( mux_tree_tapbuf_size8_7_sram ) , - .sram_inv ( mux_top_ipin_14_undriven_sram_inv ) , - .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_106 ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_mem_0 mem_top_ipin_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_mem_4 mem_top_ipin_2 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_mem_5 mem_top_ipin_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_mem_6 mem_top_ipin_6 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_3_sram ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_mem mem_top_ipin_9 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_4_sram ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_mem_1 mem_top_ipin_10 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_5_sram ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_mem_2 mem_top_ipin_13 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_6_sram ) ) ; -cbx_1__2__mux_tree_tapbuf_size8_mem_3 mem_top_ipin_14 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_7_sram ) ) ; -cbx_1__2__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_114 } ) , - .io_outpad ( bottom_width_0_height_0__pin_0_ ) , - .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_3_ } ) , - .ccff_tail ( ccff_tail ) , .p_abuf0 ( ropt_net_112 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_106 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chanx_left_in[1] ) , - .X ( chanx_right_out[1] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_107 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chanx_left_in[4] ) , - .X ( chanx_right_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chanx_left_in[5] ) , - .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chanx_left_in[6] ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chanx_left_in[7] ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_108 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chanx_left_in[9] ) , - .X ( ropt_net_130 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_109 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_12__11 ( .A ( chanx_left_in[11] ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chanx_left_in[12] ) , - .X ( chanx_right_out[12] ) ) ; -sky130_fd_sc_hd__buf_2 prog_clk_0__bip377 ( .A ( prog_clk[0] ) , - .X ( ctsbuf_net_2111 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chanx_left_in[14] ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_112 ) , - .X ( ropt_net_137 ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_330707 ( .A ( ctsbuf_net_2111 ) , - .X ( prog_clk__FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chanx_left_in[17] ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_132 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_20__19 ( .A ( chanx_left_in[19] ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_right_in[0] ) , - .X ( ropt_net_131 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , - .X ( ropt_net_134 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chanx_right_in[2] ) , - .X ( ropt_net_147 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chanx_right_in[3] ) , - .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__24 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_129 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chanx_right_in[5] ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_331708 ( .A ( ctsbuf_net_2111 ) , - .X ( prog_clk__FEEDTHRU_2[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chanx_right_in[7] ) , - .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( .A ( chanx_right_in[6] ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_114 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( ropt_net_115 ) , - .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_138 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_33__32 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_127 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_117 ) , - .X ( ropt_net_141 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_137 ) , - .X ( bottom_width_0_height_0__pin_1_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_741 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_146 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_37__36 ( .A ( chanx_right_in[16] ) , - .X ( chanx_left_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_119 ) , - .X ( chanx_right_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_39__38 ( .A ( chanx_right_in[18] ) , - .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_40__39 ( .A ( chanx_right_in[19] ) , - .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_41__40 ( .A ( aps_rename_3_ ) , - .X ( ropt_net_121 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_42__41 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_115 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_66 ( .A ( chanx_left_in[0] ) , - .X ( chanx_right_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_744 ( .A ( chanx_right_in[14] ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_138 ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( ropt_net_139 ) , - .X ( chanx_left_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_121 ) , - .X ( ropt_net_142 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_780 ( .A ( ropt_net_140 ) , - .X ( chanx_left_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_785 ( .A ( ropt_net_141 ) , - .X ( bottom_grid_pin_3_[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_786 ( .A ( ropt_net_142 ) , - .X ( bottom_width_0_height_0__pin_1_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_143 ) , - .X ( chanx_left_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_139 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_79 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_119 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_750 ( .A ( chanx_left_in[13] ) , - .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_124 ) , - .X ( ropt_net_145 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_752 ( .A ( chanx_left_in[16] ) , - .X ( chanx_right_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( ropt_net_144 ) , - .X ( chanx_right_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_753 ( .A ( chanx_left_in[10] ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_88 ( .A ( chanx_left_in[15] ) , - .X ( ropt_net_124 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( ropt_net_145 ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_90 ( .A ( chanx_right_in[9] ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_146 ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_92 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_133 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_93 ( .A ( chanx_right_in[13] ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_94 ( .A ( chanx_right_in[15] ) , - .X ( ropt_net_135 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_96 ( .A ( chanx_left_in[2] ) , - .X ( ropt_net_128 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_754 ( .A ( ropt_net_127 ) , - .X ( chanx_left_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_147 ) , - .X ( chanx_left_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_128 ) , - .X ( ropt_net_144 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_129 ) , - .X ( ropt_net_143 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_130 ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_131 ) , - .X ( chanx_left_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_132 ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_133 ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_134 ) , - .X ( ropt_net_140 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_135 ) , - .X ( chanx_left_out[15] ) ) ; -endmodule - - diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/cby_0__1__icv_in_design.fm.v b/FPGA22_HIER_SKY_PNR/modules/verilog/cby_0__1__icv_in_design.fm.v deleted file mode 100644 index 5d156f0..0000000 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/cby_0__1__icv_in_design.fm.v +++ /dev/null @@ -1,449 +0,0 @@ -// -// -// -// -// -// -module cby_0__1__direct_interc ( in , out ) ; -input [0:0] in ; -output [0:0] out ; - -assign out[0] = in[0] ; -endmodule - - -module cby_0__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( prog_clk , - ccff_head , ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:0] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__44 ( .A ( mem_out[0] ) , - .X ( net_net_86 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_163 ( .A ( net_net_86 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_0__1__EMBEDDED_IO ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , - FPGA_OUT , FPGA_DIR , p_abuf0 , p_abuf1 ) ; -input SOC_IN ; -output SOC_OUT ; -output SOC_DIR ; -output FPGA_IN ; -input FPGA_OUT ; -input FPGA_DIR ; -output p_abuf0 ; -output p_abuf1 ; - -wire aps_rename_2_ ; - -assign SOC_OUT = FPGA_OUT ; - -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__42 ( .A ( SOC_IN ) , .X ( p_abuf1 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__43 ( .A ( FPGA_DIR ) , - .X ( aps_rename_2_ ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_45 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_46 ( .A ( p_abuf1 ) , - .X ( BUF_net_46 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_128 ( .A ( BUF_net_46 ) , - .X ( p_abuf0 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_162 ( .A ( aps_rename_2_ ) , - .X ( SOC_DIR ) ) ; -endmodule - - -module cby_0__1__logical_tile_io_mode_physical__iopad ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , p_abuf0 , p_abuf1 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] iopad_outpad ; -input [0:0] ccff_head ; -output [0:0] iopad_inpad ; -output [0:0] ccff_tail ; -output p_abuf0 ; -output p_abuf1 ; - -wire [0:0] EMBEDDED_IO_0_en ; - -cby_0__1__EMBEDDED_IO EMBEDDED_IO_0_ ( - .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , - .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , - .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , - .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , - .p_abuf1 ( p_abuf1 ) ) ; -cby_0__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) ) ; -endmodule - - -module cby_0__1__logical_tile_io_mode_io_ ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , - ccff_tail , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] io_outpad ; -input [0:0] ccff_head ; -output [0:0] io_inpad ; -output [0:0] ccff_tail ; -output p_abuf0 ; - -cby_0__1__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , - .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , - .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; -cby_0__1__direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( { p_abuf1 } ) ) ; -cby_0__1__direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( io_outpad ) ) ; -endmodule - - -module cby_0__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__41 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_0__1__const1 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cby_0__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -cby_0__1__const1 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cby_0__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , - chany_bottom_out , chany_top_out , left_grid_pin_0_ , ccff_tail , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , right_width_0_height_0__pin_0_ , - right_width_0_height_0__pin_1_upper , - right_width_0_height_0__pin_1_lower ) ; -input [0:0] prog_clk ; -input [0:19] chany_bottom_in ; -input [0:19] chany_top_in ; -input [0:0] ccff_head ; -output [0:19] chany_bottom_out ; -output [0:19] chany_top_out ; -output [0:0] left_grid_pin_0_ ; -output [0:0] ccff_tail ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] right_width_0_height_0__pin_0_ ; -output [0:0] right_width_0_height_0__pin_1_upper ; -output [0:0] right_width_0_height_0__pin_1_lower ; - -wire ropt_net_168 ; -wire [0:3] mux_right_ipin_0_undriven_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_0_sram ; -// - -cby_0__1__mux_tree_tapbuf_size10 mux_right_ipin_0 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , - chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , - chany_top_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_right_ipin_0_undriven_sram_inv ) , - .out ( left_grid_pin_0_ ) , .p0 ( optlc_net_164 ) ) ; -cby_0__1__mux_tree_tapbuf_size10_mem mem_right_ipin_0 ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( { ccff_tail_mid } ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; -cby_0__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_178 } ) , - .io_outpad ( right_width_0_height_0__pin_0_ ) , - .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_8_ } ) , - .ccff_tail ( { ropt_net_170 } ) , - .p_abuf0 ( ropt_net_168 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_165 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_164 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_165 ) , - .X ( ropt_net_210 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_745 ( - .A ( chany_bottom_in[10] ) , .X ( ropt_net_233 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_167 ) , - .X ( right_width_0_height_0__pin_1_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( ropt_net_168 ) , - .X ( right_width_0_height_0__pin_1_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_169 ) , - .X ( ropt_net_211 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_749 ( .A ( ropt_net_170 ) , - .X ( ropt_net_223 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_171 ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_751 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_226 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_786 ( .A ( ropt_net_205 ) , - .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_206 ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_752 ( .A ( chany_bottom_in[1] ) , - .X ( ropt_net_235 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_753 ( - .A ( chany_bottom_in[14] ) , .X ( ropt_net_231 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_754 ( .A ( chany_bottom_in[7] ) , - .X ( ropt_net_230 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_755 ( - .A ( chany_bottom_in[16] ) , .X ( ropt_net_228 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_756 ( .A ( chany_top_in[13] ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_757 ( .A ( ropt_net_178 ) , - .X ( ropt_net_224 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_758 ( - .A ( chany_bottom_in[18] ) , .X ( ropt_net_234 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_759 ( .A ( chany_top_in[18] ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_760 ( .A ( chany_top_in[9] ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chany_top_in[0] ) , - .X ( chany_bottom_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( .A ( chany_bottom_in[5] ) , - .X ( ropt_net_227 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( chany_top_in[7] ) , - .X ( ropt_net_225 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_184 ) , - .X ( ropt_net_212 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_764 ( .A ( chany_top_in[6] ) , - .X ( ropt_net_229 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_186 ) , - .X ( ropt_net_205 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_187 ) , - .X ( ropt_net_214 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_232 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_207 ) , - .X ( chany_bottom_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_189 ) , - .X ( ropt_net_215 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_31__30 ( .A ( chany_top_in[10] ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( ropt_net_208 ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( ropt_net_209 ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_190 ) , - .X ( ropt_net_209 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_191 ) , - .X ( ropt_net_220 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_192 ) , - .X ( ropt_net_213 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_37__36 ( .A ( chany_top_in[16] ) , - .X ( ropt_net_202 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_193 ) , - .X ( ropt_net_208 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_194 ) , - .X ( ropt_net_217 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_195 ) , - .X ( ropt_net_206 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_196 ) , - .X ( ropt_net_218 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_47 ( .A ( chany_bottom_in[0] ) , - .X ( ropt_net_189 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( ropt_net_210 ) , - .X ( chany_bottom_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_197 ) , - .X ( ropt_net_216 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_198 ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_51 ( .A ( chany_bottom_in[4] ) , - .X ( ropt_net_191 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( ropt_net_211 ) , - .X ( chany_bottom_out[12] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_53 ( .A ( chany_bottom_in[6] ) , - .X ( ropt_net_192 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_212 ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( ropt_net_213 ) , - .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_795 ( .A ( ropt_net_214 ) , - .X ( chany_top_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( ropt_net_215 ) , - .X ( chany_top_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_58 ( .A ( chany_bottom_in[11] ) , - .X ( ropt_net_186 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_59 ( .A ( chany_bottom_in[12] ) , - .X ( ropt_net_187 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_60 ( .A ( chany_bottom_in[13] ) , - .X ( ropt_net_196 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_216 ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_62 ( .A ( chany_bottom_in[15] ) , - .X ( ropt_net_184 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_800 ( .A ( ropt_net_217 ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_199 ) , - .X ( ropt_net_219 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_218 ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_200 ) , - .X ( chany_bottom_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_201 ) , - .X ( ropt_net_222 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_68 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_203 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_69 ( .A ( chany_top_in[3] ) , - .X ( ropt_net_201 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_802 ( .A ( ropt_net_219 ) , - .X ( chany_top_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_202 ) , - .X ( chany_bottom_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_803 ( .A ( ropt_net_220 ) , - .X ( chany_top_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_804 ( .A ( ropt_net_221 ) , - .X ( chany_bottom_out[8] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_74 ( .A ( chany_top_in[8] ) , - .X ( BUF_net_74 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_203 ) , - .X ( ropt_net_207 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( ropt_net_222 ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_223 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_224 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_79 ( .A ( chany_top_in[14] ) , - .X ( ropt_net_190 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_80 ( .A ( chany_top_in[15] ) , - .X ( ropt_net_194 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_81 ( .A ( chany_top_in[17] ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_817 ( .A ( ropt_net_225 ) , - .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_226 ) , - .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_227 ) , - .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_228 ) , - .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_229 ) , - .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_230 ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_231 ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( ropt_net_232 ) , - .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_826 ( .A ( ropt_net_233 ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_827 ( .A ( ropt_net_234 ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_235 ) , - .X ( chany_top_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_96 ( .A ( chany_bottom_in[8] ) , - .X ( BUF_net_96 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_108 ( .A ( chany_top_in[1] ) , - .X ( ropt_net_200 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_121 ( .A ( chany_top_in[19] ) , - .X ( ropt_net_198 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_122 ( .A ( aps_rename_8_ ) , - .X ( ropt_net_167 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_125 ( .A ( BUF_net_74 ) , - .X ( ropt_net_221 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_126 ( .A ( chany_top_in[11] ) , - .X ( ropt_net_171 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_127 ( .A ( chany_top_in[12] ) , - .X ( ropt_net_169 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_131 ( .A ( chany_bottom_in[2] ) , - .X ( ropt_net_199 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_132 ( .A ( chany_bottom_in[3] ) , - .X ( ropt_net_195 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_137 ( .A ( BUF_net_96 ) , - .X ( chany_top_out[8] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_144 ( .A ( chany_bottom_in[17] ) , - .X ( ropt_net_193 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_146 ( .A ( chany_bottom_in[19] ) , - .X ( ropt_net_197 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_150 ( .A ( chany_top_in[4] ) , - .X ( ropt_net_165 ) ) ; -endmodule - - diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/cby_0__1__icv_in_design.lvs.v b/FPGA22_HIER_SKY_PNR/modules/verilog/cby_0__1__icv_in_design.lvs.v deleted file mode 100644 index 1417c44..0000000 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/cby_0__1__icv_in_design.lvs.v +++ /dev/null @@ -1,1422 +0,0 @@ -// -// -// -// -// -// -module cby_0__1__direct_interc ( in , out ) ; -input [0:0] in ; -output [0:0] out ; - -assign out[0] = in[0] ; -endmodule - - -module cby_0__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( prog_clk , - ccff_head , ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:0] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__44 ( .A ( mem_out[0] ) , - .X ( net_net_86 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_163 ( .A ( net_net_86 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_0__1__EMBEDDED_IO ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , - FPGA_OUT , FPGA_DIR , p_abuf0 , p_abuf1 , VDD , VSS ) ; -input SOC_IN ; -output SOC_OUT ; -output SOC_DIR ; -output FPGA_IN ; -input FPGA_OUT ; -input FPGA_DIR ; -output p_abuf0 ; -output p_abuf1 ; -input VDD ; -input VSS ; - -supply1 VDD ; -wire aps_rename_2_ ; -supply0 VSS ; - -assign SOC_OUT = FPGA_OUT ; - -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__42 ( .A ( SOC_IN ) , .X ( p_abuf1 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__43 ( .A ( FPGA_DIR ) , - .X ( aps_rename_2_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_45 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_46 ( .A ( p_abuf1 ) , - .X ( BUF_net_46 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_128 ( .A ( BUF_net_46 ) , - .X ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_162 ( .A ( aps_rename_2_ ) , - .X ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_0__1__logical_tile_io_mode_physical__iopad ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] iopad_outpad ; -input [0:0] ccff_head ; -output [0:0] iopad_inpad ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; -output p_abuf0 ; -output p_abuf1 ; - -wire [0:0] EMBEDDED_IO_0_en ; -supply1 VDD ; -supply0 VSS ; - -cby_0__1__EMBEDDED_IO EMBEDDED_IO_0_ ( - .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , - .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , - .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , - .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , - .p_abuf1 ( p_abuf1 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cby_0__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -endmodule - - -module cby_0__1__logical_tile_io_mode_io_ ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , - ccff_tail , VDD , VSS , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] io_outpad ; -input [0:0] ccff_head ; -output [0:0] io_inpad ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; -output p_abuf0 ; - -supply1 VDD ; -supply0 VSS ; - -cby_0__1__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , - .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , - .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; -cby_0__1__direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( { p_abuf1 } ) ) ; -cby_0__1__direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( io_outpad ) ) ; -endmodule - - -module cby_0__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__41 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_0__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_0__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , - chany_bottom_out , chany_top_out , left_grid_pin_0_ , ccff_tail , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , right_width_0_height_0__pin_0_ , - right_width_0_height_0__pin_1_upper , - right_width_0_height_0__pin_1_lower , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:19] chany_bottom_in ; -input [0:19] chany_top_in ; -input [0:0] ccff_head ; -output [0:19] chany_bottom_out ; -output [0:19] chany_top_out ; -output [0:0] left_grid_pin_0_ ; -output [0:0] ccff_tail ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] right_width_0_height_0__pin_0_ ; -output [0:0] right_width_0_height_0__pin_1_upper ; -output [0:0] right_width_0_height_0__pin_1_lower ; -input VDD ; -input VSS ; - -wire ropt_net_168 ; -wire [0:3] mux_right_ipin_0_undriven_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_0_sram ; -supply1 VDD ; -supply0 VSS ; -// - -cby_0__1__mux_tree_tapbuf_size10 mux_right_ipin_0 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , - chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , - chany_top_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_right_ipin_0_undriven_sram_inv ) , - .out ( left_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_164 ) ) ; -cby_0__1__mux_tree_tapbuf_size10_mem mem_right_ipin_0 ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( { ccff_tail_mid } ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cby_0__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_178 } ) , - .io_outpad ( right_width_0_height_0__pin_0_ ) , - .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_8_ } ) , - .ccff_tail ( { ropt_net_170 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( ropt_net_168 ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1636 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1637 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1638 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1639 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1640 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1641 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1642 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1643 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1644 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1645 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1646 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1647 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1648 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1649 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1650 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__conb_1 optlc_165 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_164 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_165 ) , - .X ( ropt_net_210 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_745 ( - .A ( chany_bottom_in[10] ) , .X ( ropt_net_233 ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_167 ) , - .X ( right_width_0_height_0__pin_1_lower[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( ropt_net_168 ) , - .X ( right_width_0_height_0__pin_1_upper[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_169 ) , - .X ( ropt_net_211 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_749 ( .A ( ropt_net_170 ) , - .X ( ropt_net_223 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_171 ) , - .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_751 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_226 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_786 ( .A ( ropt_net_205 ) , - .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_206 ) , - .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_752 ( .A ( chany_bottom_in[1] ) , - .X ( ropt_net_235 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_753 ( - .A ( chany_bottom_in[14] ) , .X ( ropt_net_231 ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_754 ( .A ( chany_bottom_in[7] ) , - .X ( ropt_net_230 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_755 ( - .A ( chany_bottom_in[16] ) , .X ( ropt_net_228 ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_756 ( .A ( chany_top_in[13] ) , - .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_757 ( .A ( ropt_net_178 ) , - .X ( ropt_net_224 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_758 ( - .A ( chany_bottom_in[18] ) , .X ( ropt_net_234 ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_759 ( .A ( chany_top_in[18] ) , - .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_760 ( .A ( chany_top_in[9] ) , - .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chany_top_in[0] ) , - .X ( chany_bottom_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( .A ( chany_bottom_in[5] ) , - .X ( ropt_net_227 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( chany_top_in[7] ) , - .X ( ropt_net_225 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_184 ) , - .X ( ropt_net_212 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_764 ( .A ( chany_top_in[6] ) , - .X ( ropt_net_229 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_186 ) , - .X ( ropt_net_205 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_187 ) , - .X ( ropt_net_214 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_232 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_207 ) , - .X ( chany_bottom_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_189 ) , - .X ( ropt_net_215 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_31__30 ( .A ( chany_top_in[10] ) , - .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( ropt_net_208 ) , - .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( ropt_net_209 ) , - .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_190 ) , - .X ( ropt_net_209 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_191 ) , - .X ( ropt_net_220 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_192 ) , - .X ( ropt_net_213 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_37__36 ( .A ( chany_top_in[16] ) , - .X ( ropt_net_202 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_193 ) , - .X ( ropt_net_208 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_194 ) , - .X ( ropt_net_217 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_195 ) , - .X ( ropt_net_206 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_196 ) , - .X ( ropt_net_218 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_47 ( .A ( chany_bottom_in[0] ) , - .X ( ropt_net_189 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( ropt_net_210 ) , - .X ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_197 ) , - .X ( ropt_net_216 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_198 ) , - .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_51 ( .A ( chany_bottom_in[4] ) , - .X ( ropt_net_191 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( ropt_net_211 ) , - .X ( chany_bottom_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_53 ( .A ( chany_bottom_in[6] ) , - .X ( ropt_net_192 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_212 ) , - .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( ropt_net_213 ) , - .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_795 ( .A ( ropt_net_214 ) , - .X ( chany_top_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( ropt_net_215 ) , - .X ( chany_top_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_58 ( .A ( chany_bottom_in[11] ) , - .X ( ropt_net_186 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_59 ( .A ( chany_bottom_in[12] ) , - .X ( ropt_net_187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_60 ( .A ( chany_bottom_in[13] ) , - .X ( ropt_net_196 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_216 ) , - .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_62 ( .A ( chany_bottom_in[15] ) , - .X ( ropt_net_184 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_800 ( .A ( ropt_net_217 ) , - .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_199 ) , - .X ( ropt_net_219 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_218 ) , - .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_200 ) , - .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_201 ) , - .X ( ropt_net_222 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_68 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_203 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_69 ( .A ( chany_top_in[3] ) , - .X ( ropt_net_201 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_802 ( .A ( ropt_net_219 ) , - .X ( chany_top_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_202 ) , - .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_803 ( .A ( ropt_net_220 ) , - .X ( chany_top_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_804 ( .A ( ropt_net_221 ) , - .X ( chany_bottom_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_74 ( .A ( chany_top_in[8] ) , - .X ( BUF_net_74 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_203 ) , - .X ( ropt_net_207 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( ropt_net_222 ) , - .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_223 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_224 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_79 ( .A ( chany_top_in[14] ) , - .X ( ropt_net_190 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_80 ( .A ( chany_top_in[15] ) , - .X ( ropt_net_194 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_81 ( .A ( chany_top_in[17] ) , - .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_817 ( .A ( ropt_net_225 ) , - .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_226 ) , - .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_227 ) , - .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_228 ) , - .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_229 ) , - .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_230 ) , - .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_231 ) , - .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( ropt_net_232 ) , - .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_826 ( .A ( ropt_net_233 ) , - .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_827 ( .A ( ropt_net_234 ) , - .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_235 ) , - .X ( chany_top_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_96 ( .A ( chany_bottom_in[8] ) , - .X ( BUF_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_108 ( .A ( chany_top_in[1] ) , - .X ( ropt_net_200 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y0 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_121 ( .A ( chany_top_in[19] ) , - .X ( ropt_net_198 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_122 ( .A ( aps_rename_8_ ) , - .X ( ropt_net_167 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_125 ( .A ( BUF_net_74 ) , - .X ( ropt_net_221 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_126 ( .A ( chany_top_in[11] ) , - .X ( ropt_net_171 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_127 ( .A ( chany_top_in[12] ) , - .X ( ropt_net_169 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y0 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_131 ( .A ( chany_bottom_in[2] ) , - .X ( ropt_net_199 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_132 ( .A ( chany_bottom_in[3] ) , - .X ( ropt_net_195 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x184000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_137 ( .A ( BUF_net_96 ) , - .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x193200y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x446200y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_144 ( .A ( chany_bottom_in[17] ) , - .X ( ropt_net_193 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_146 ( .A ( chany_bottom_in[19] ) , - .X ( ropt_net_197 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x165600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x202400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_150 ( .A ( chany_top_in[4] ) , - .X ( ropt_net_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x202400y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x400200y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x184000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x193200y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x225400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x243800y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x492200y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x294400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x354200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x441600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x570400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x588800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x294400y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x340400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x377200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x414000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x450800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x524400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x533600y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x55200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x101200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x138000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x174800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x211600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x248400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x358800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x404800y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x450800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x561200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x570400y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x276000y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x354200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x220800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x239200y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x354200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x372600y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x418600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x455400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x492200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x529000y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x92000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x128800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x165600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x202400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x239200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x285200y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x326600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x363400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x501400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x519800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x644000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x473800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x510600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x547400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x584200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x400200y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x368000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x386400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x395600y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x473800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x510600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x547400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x584200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x478400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x561200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x570400y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x455400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x492200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x565800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x294400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x349600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x464600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x556600y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x36800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x46000y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x124200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x161000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x197800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x234600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x271400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x345000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x381800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x418600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x455400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x547400y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x220800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x239200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x248400y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x538200y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x119600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x128800y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x170200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x207000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x216200y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x55200y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x437000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x446200y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x36800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/cby_0__1__icv_in_design.pt.v b/FPGA22_HIER_SKY_PNR/modules/verilog/cby_0__1__icv_in_design.pt.v deleted file mode 100644 index b5fb6fb..0000000 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/cby_0__1__icv_in_design.pt.v +++ /dev/null @@ -1,442 +0,0 @@ -// -// -// -// -// -// -module cby_0__1__direct_interc ( in , out ) ; -input [0:0] in ; -output [0:0] out ; - -assign out[0] = in[0] ; -endmodule - - -module cby_0__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( prog_clk , - ccff_head , ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:0] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__44 ( .A ( mem_out[0] ) , - .X ( net_net_86 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_163 ( .A ( net_net_86 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_0__1__EMBEDDED_IO ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , - FPGA_OUT , FPGA_DIR , p_abuf0 , p_abuf1 ) ; -input SOC_IN ; -output SOC_OUT ; -output SOC_DIR ; -output FPGA_IN ; -input FPGA_OUT ; -input FPGA_DIR ; -output p_abuf0 ; -output p_abuf1 ; - -wire aps_rename_2_ ; - -assign SOC_OUT = FPGA_OUT ; - -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__42 ( .A ( SOC_IN ) , .X ( p_abuf1 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__43 ( .A ( FPGA_DIR ) , - .X ( aps_rename_2_ ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_45 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_46 ( .A ( p_abuf1 ) , - .X ( BUF_net_46 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_128 ( .A ( BUF_net_46 ) , - .X ( p_abuf0 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_162 ( .A ( aps_rename_2_ ) , - .X ( SOC_DIR ) ) ; -endmodule - - -module cby_0__1__logical_tile_io_mode_physical__iopad ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , p_abuf0 , p_abuf1 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] iopad_outpad ; -input [0:0] ccff_head ; -output [0:0] iopad_inpad ; -output [0:0] ccff_tail ; -output p_abuf0 ; -output p_abuf1 ; - -wire [0:0] EMBEDDED_IO_0_en ; - -cby_0__1__EMBEDDED_IO EMBEDDED_IO_0_ ( - .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , - .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , - .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , - .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , - .p_abuf1 ( p_abuf1 ) ) ; -cby_0__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) ) ; -endmodule - - -module cby_0__1__logical_tile_io_mode_io_ ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , - ccff_tail , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] io_outpad ; -input [0:0] ccff_head ; -output [0:0] io_inpad ; -output [0:0] ccff_tail ; -output p_abuf0 ; - -cby_0__1__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , - .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , - .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; -cby_0__1__direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( { p_abuf1 } ) ) ; -cby_0__1__direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( io_outpad ) ) ; -endmodule - - -module cby_0__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__41 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_0__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cby_0__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , - chany_bottom_out , chany_top_out , left_grid_pin_0_ , ccff_tail , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , right_width_0_height_0__pin_0_ , - right_width_0_height_0__pin_1_upper , - right_width_0_height_0__pin_1_lower ) ; -input [0:0] prog_clk ; -input [0:19] chany_bottom_in ; -input [0:19] chany_top_in ; -input [0:0] ccff_head ; -output [0:19] chany_bottom_out ; -output [0:19] chany_top_out ; -output [0:0] left_grid_pin_0_ ; -output [0:0] ccff_tail ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] right_width_0_height_0__pin_0_ ; -output [0:0] right_width_0_height_0__pin_1_upper ; -output [0:0] right_width_0_height_0__pin_1_lower ; - -wire ropt_net_168 ; -wire [0:3] mux_right_ipin_0_undriven_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_0_sram ; -// - -cby_0__1__mux_tree_tapbuf_size10 mux_right_ipin_0 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , - chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , - chany_top_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_right_ipin_0_undriven_sram_inv ) , - .out ( left_grid_pin_0_ ) , .p0 ( optlc_net_164 ) ) ; -cby_0__1__mux_tree_tapbuf_size10_mem mem_right_ipin_0 ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( { ccff_tail_mid } ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; -cby_0__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_178 } ) , - .io_outpad ( right_width_0_height_0__pin_0_ ) , - .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_8_ } ) , - .ccff_tail ( { ropt_net_170 } ) , - .p_abuf0 ( ropt_net_168 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_165 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_164 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_165 ) , - .X ( ropt_net_210 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_745 ( - .A ( chany_bottom_in[10] ) , .X ( ropt_net_233 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_167 ) , - .X ( right_width_0_height_0__pin_1_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( ropt_net_168 ) , - .X ( right_width_0_height_0__pin_1_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_169 ) , - .X ( ropt_net_211 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_749 ( .A ( ropt_net_170 ) , - .X ( ropt_net_223 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_171 ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_751 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_226 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_786 ( .A ( ropt_net_205 ) , - .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_206 ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_752 ( .A ( chany_bottom_in[1] ) , - .X ( ropt_net_235 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_753 ( - .A ( chany_bottom_in[14] ) , .X ( ropt_net_231 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_754 ( .A ( chany_bottom_in[7] ) , - .X ( ropt_net_230 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_755 ( - .A ( chany_bottom_in[16] ) , .X ( ropt_net_228 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_756 ( .A ( chany_top_in[13] ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_757 ( .A ( ropt_net_178 ) , - .X ( ropt_net_224 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_758 ( - .A ( chany_bottom_in[18] ) , .X ( ropt_net_234 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_759 ( .A ( chany_top_in[18] ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_760 ( .A ( chany_top_in[9] ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chany_top_in[0] ) , - .X ( chany_bottom_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( .A ( chany_bottom_in[5] ) , - .X ( ropt_net_227 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( chany_top_in[7] ) , - .X ( ropt_net_225 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_184 ) , - .X ( ropt_net_212 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_764 ( .A ( chany_top_in[6] ) , - .X ( ropt_net_229 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_186 ) , - .X ( ropt_net_205 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_187 ) , - .X ( ropt_net_214 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_232 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_207 ) , - .X ( chany_bottom_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_189 ) , - .X ( ropt_net_215 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_31__30 ( .A ( chany_top_in[10] ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( ropt_net_208 ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( ropt_net_209 ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_190 ) , - .X ( ropt_net_209 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_191 ) , - .X ( ropt_net_220 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_192 ) , - .X ( ropt_net_213 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_37__36 ( .A ( chany_top_in[16] ) , - .X ( ropt_net_202 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_193 ) , - .X ( ropt_net_208 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_194 ) , - .X ( ropt_net_217 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_195 ) , - .X ( ropt_net_206 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_196 ) , - .X ( ropt_net_218 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_47 ( .A ( chany_bottom_in[0] ) , - .X ( ropt_net_189 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( ropt_net_210 ) , - .X ( chany_bottom_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_197 ) , - .X ( ropt_net_216 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_198 ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_51 ( .A ( chany_bottom_in[4] ) , - .X ( ropt_net_191 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( ropt_net_211 ) , - .X ( chany_bottom_out[12] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_53 ( .A ( chany_bottom_in[6] ) , - .X ( ropt_net_192 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_212 ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( ropt_net_213 ) , - .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_795 ( .A ( ropt_net_214 ) , - .X ( chany_top_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( ropt_net_215 ) , - .X ( chany_top_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_58 ( .A ( chany_bottom_in[11] ) , - .X ( ropt_net_186 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_59 ( .A ( chany_bottom_in[12] ) , - .X ( ropt_net_187 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_60 ( .A ( chany_bottom_in[13] ) , - .X ( ropt_net_196 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_216 ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_62 ( .A ( chany_bottom_in[15] ) , - .X ( ropt_net_184 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_800 ( .A ( ropt_net_217 ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_199 ) , - .X ( ropt_net_219 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_218 ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_200 ) , - .X ( chany_bottom_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_201 ) , - .X ( ropt_net_222 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_68 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_203 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_69 ( .A ( chany_top_in[3] ) , - .X ( ropt_net_201 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_802 ( .A ( ropt_net_219 ) , - .X ( chany_top_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_202 ) , - .X ( chany_bottom_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_803 ( .A ( ropt_net_220 ) , - .X ( chany_top_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_804 ( .A ( ropt_net_221 ) , - .X ( chany_bottom_out[8] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_74 ( .A ( chany_top_in[8] ) , - .X ( BUF_net_74 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_203 ) , - .X ( ropt_net_207 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( ropt_net_222 ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_223 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_224 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_79 ( .A ( chany_top_in[14] ) , - .X ( ropt_net_190 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_80 ( .A ( chany_top_in[15] ) , - .X ( ropt_net_194 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_81 ( .A ( chany_top_in[17] ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_817 ( .A ( ropt_net_225 ) , - .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_226 ) , - .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_227 ) , - .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_228 ) , - .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_229 ) , - .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_230 ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_231 ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( ropt_net_232 ) , - .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_826 ( .A ( ropt_net_233 ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_827 ( .A ( ropt_net_234 ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_235 ) , - .X ( chany_top_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_96 ( .A ( chany_bottom_in[8] ) , - .X ( BUF_net_96 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_108 ( .A ( chany_top_in[1] ) , - .X ( ropt_net_200 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_121 ( .A ( chany_top_in[19] ) , - .X ( ropt_net_198 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_122 ( .A ( aps_rename_8_ ) , - .X ( ropt_net_167 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_125 ( .A ( BUF_net_74 ) , - .X ( ropt_net_221 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_126 ( .A ( chany_top_in[11] ) , - .X ( ropt_net_171 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_127 ( .A ( chany_top_in[12] ) , - .X ( ropt_net_169 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_131 ( .A ( chany_bottom_in[2] ) , - .X ( ropt_net_199 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_132 ( .A ( chany_bottom_in[3] ) , - .X ( ropt_net_195 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_137 ( .A ( BUF_net_96 ) , - .X ( chany_top_out[8] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_144 ( .A ( chany_bottom_in[17] ) , - .X ( ropt_net_193 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_146 ( .A ( chany_bottom_in[19] ) , - .X ( ropt_net_197 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_150 ( .A ( chany_top_in[4] ) , - .X ( ropt_net_165 ) ) ; -endmodule - - diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/cby_1__1__icv_in_design.fm.v b/FPGA22_HIER_SKY_PNR/modules/verilog/cby_1__1__icv_in_design.fm.v deleted file mode 100644 index bbf7737..0000000 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/cby_1__1__icv_in_design.fm.v +++ /dev/null @@ -1,1615 +0,0 @@ -// -// -// -// -// -// -module cby_1__1__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__55 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__54 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__53 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__52 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__51 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__50 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__49 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__48 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_1__1__const1 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -cby_1__1__const1 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; -endmodule - - -module cby_1__1__const1_14 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -cby_1__1__const1_14 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cby_1__1__const1_13 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -cby_1__1__const1_13 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; -endmodule - - -module cby_1__1__const1_12 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -cby_1__1__const1_12 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cby_1__1__const1_11 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -cby_1__1__const1_11 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cby_1__1__const1_10 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -cby_1__1__const1_10 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cby_1__1__const1_9 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -cby_1__1__const1_9 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cby_1__1__const1_8 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -cby_1__1__const1_8 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_8__47 ( .A ( mem_out[3] ) , - .X ( net_net_72 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_96 ( .A ( net_net_72 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__46 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__45 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__44 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__43 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__42 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__41 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__40 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_1__1__const1_7 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -cby_1__1__const1_7 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cby_1__1__const1_6 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -cby_1__1__const1_6 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cby_1__1__const1_5 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -cby_1__1__const1_5 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cby_1__1__const1_4 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -cby_1__1__const1_4 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cby_1__1__const1_3 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -cby_1__1__const1_3 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cby_1__1__const1_2 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -cby_1__1__const1_2 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cby_1__1__const1_1 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -cby_1__1__const1_1 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cby_1__1__const1_0 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -cby_1__1__const1_0 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cby_1__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , - chany_bottom_out , chany_top_out , left_grid_pin_16_ , left_grid_pin_17_ , - left_grid_pin_18_ , left_grid_pin_19_ , left_grid_pin_20_ , - left_grid_pin_21_ , left_grid_pin_22_ , left_grid_pin_23_ , - left_grid_pin_24_ , left_grid_pin_25_ , left_grid_pin_26_ , - left_grid_pin_27_ , left_grid_pin_28_ , left_grid_pin_29_ , - left_grid_pin_30_ , left_grid_pin_31_ , ccff_tail , prog_clk__FEEDTHRU_1 , - prog_clk__FEEDTHRU_2 ) ; -input [0:0] prog_clk ; -input [0:19] chany_bottom_in ; -input [0:19] chany_top_in ; -input [0:0] ccff_head ; -output [0:19] chany_bottom_out ; -output [0:19] chany_top_out ; -output [0:0] left_grid_pin_16_ ; -output [0:0] left_grid_pin_17_ ; -output [0:0] left_grid_pin_18_ ; -output [0:0] left_grid_pin_19_ ; -output [0:0] left_grid_pin_20_ ; -output [0:0] left_grid_pin_21_ ; -output [0:0] left_grid_pin_22_ ; -output [0:0] left_grid_pin_23_ ; -output [0:0] left_grid_pin_24_ ; -output [0:0] left_grid_pin_25_ ; -output [0:0] left_grid_pin_26_ ; -output [0:0] left_grid_pin_27_ ; -output [0:0] left_grid_pin_28_ ; -output [0:0] left_grid_pin_29_ ; -output [0:0] left_grid_pin_30_ ; -output [0:0] left_grid_pin_31_ ; -output [0:0] ccff_tail ; -output [0:0] prog_clk__FEEDTHRU_1 ; -output [0:0] prog_clk__FEEDTHRU_2 ; - -wire [0:3] mux_right_ipin_0_undriven_sram_inv ; -wire [0:3] mux_right_ipin_10_undriven_sram_inv ; -wire [0:3] mux_right_ipin_11_undriven_sram_inv ; -wire [0:3] mux_right_ipin_12_undriven_sram_inv ; -wire [0:3] mux_right_ipin_13_undriven_sram_inv ; -wire [0:3] mux_right_ipin_14_undriven_sram_inv ; -wire [0:3] mux_right_ipin_15_undriven_sram_inv ; -wire [0:3] mux_right_ipin_1_undriven_sram_inv ; -wire [0:3] mux_right_ipin_2_undriven_sram_inv ; -wire [0:3] mux_right_ipin_3_undriven_sram_inv ; -wire [0:3] mux_right_ipin_4_undriven_sram_inv ; -wire [0:3] mux_right_ipin_5_undriven_sram_inv ; -wire [0:3] mux_right_ipin_6_undriven_sram_inv ; -wire [0:3] mux_right_ipin_7_undriven_sram_inv ; -wire [0:3] mux_right_ipin_8_undriven_sram_inv ; -wire [0:3] mux_right_ipin_9_undriven_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:3] mux_tree_tapbuf_size10_2_sram ; -wire [0:3] mux_tree_tapbuf_size10_3_sram ; -wire [0:3] mux_tree_tapbuf_size10_4_sram ; -wire [0:3] mux_tree_tapbuf_size10_5_sram ; -wire [0:3] mux_tree_tapbuf_size10_6_sram ; -wire [0:3] mux_tree_tapbuf_size10_7_sram ; -wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:3] mux_tree_tapbuf_size8_2_sram ; -wire [0:3] mux_tree_tapbuf_size8_3_sram ; -wire [0:3] mux_tree_tapbuf_size8_4_sram ; -wire [0:3] mux_tree_tapbuf_size8_5_sram ; -wire [0:3] mux_tree_tapbuf_size8_6_sram ; -wire [0:3] mux_tree_tapbuf_size8_7_sram ; -wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ; -// - -cby_1__1__mux_tree_tapbuf_size10_0 mux_right_ipin_0 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , - chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , - chany_top_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_right_ipin_0_undriven_sram_inv ) , - .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_103 ) ) ; -cby_1__1__mux_tree_tapbuf_size10_4 mux_right_ipin_3 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , - chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[19] , - chany_top_in[19] } ) , - .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_right_ipin_3_undriven_sram_inv ) , - .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_105 ) ) ; -cby_1__1__mux_tree_tapbuf_size10_5 mux_right_ipin_4 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , - chany_bottom_in[8] , chany_top_in[8] , chany_bottom_in[14] , - chany_top_in[14] } ) , - .sram ( mux_tree_tapbuf_size10_2_sram ) , - .sram_inv ( mux_right_ipin_4_undriven_sram_inv ) , - .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_103 ) ) ; -cby_1__1__mux_tree_tapbuf_size10_6 mux_right_ipin_7 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , - chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[17] , - chany_top_in[17] } ) , - .sram ( mux_tree_tapbuf_size10_3_sram ) , - .sram_inv ( mux_right_ipin_7_undriven_sram_inv ) , - .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_104 ) ) ; -cby_1__1__mux_tree_tapbuf_size10 mux_right_ipin_8 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[8] , chany_top_in[8] , - chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[18] , - chany_top_in[18] } ) , - .sram ( mux_tree_tapbuf_size10_4_sram ) , - .sram_inv ( mux_right_ipin_8_undriven_sram_inv ) , - .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_106 ) ) ; -cby_1__1__mux_tree_tapbuf_size10_1 mux_right_ipin_11 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , - chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[15] , - chany_top_in[15] } ) , - .sram ( mux_tree_tapbuf_size10_5_sram ) , - .sram_inv ( mux_right_ipin_11_undriven_sram_inv ) , - .out ( left_grid_pin_27_ ) , .p0 ( optlc_net_106 ) ) ; -cby_1__1__mux_tree_tapbuf_size10_2 mux_right_ipin_12 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , - chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[16] , - chany_top_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_6_sram ) , - .sram_inv ( mux_right_ipin_12_undriven_sram_inv ) , - .out ( left_grid_pin_28_ ) , .p0 ( optlc_net_106 ) ) ; -cby_1__1__mux_tree_tapbuf_size10_3 mux_right_ipin_15 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , - chany_bottom_in[15] , chany_top_in[15] , chany_bottom_in[19] , - chany_top_in[19] } ) , - .sram ( mux_tree_tapbuf_size10_7_sram ) , - .sram_inv ( mux_right_ipin_15_undriven_sram_inv ) , - .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_104 ) ) ; -cby_1__1__mux_tree_tapbuf_size10_mem_0 mem_right_ipin_0 ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; -cby_1__1__mux_tree_tapbuf_size10_mem_4 mem_right_ipin_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ; -cby_1__1__mux_tree_tapbuf_size10_mem_5 mem_right_ipin_4 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ; -cby_1__1__mux_tree_tapbuf_size10_mem_6 mem_right_ipin_7 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ; -cby_1__1__mux_tree_tapbuf_size10_mem mem_right_ipin_8 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ; -cby_1__1__mux_tree_tapbuf_size10_mem_1 mem_right_ipin_11 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ; -cby_1__1__mux_tree_tapbuf_size10_mem_2 mem_right_ipin_12 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ; -cby_1__1__mux_tree_tapbuf_size10_mem_3 mem_right_ipin_15 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .ccff_tail ( { ropt_net_120 } ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ; -cby_1__1__mux_tree_tapbuf_size8_0 mux_right_ipin_1 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , - chany_bottom_in[13] , chany_top_in[13] } ) , - .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_right_ipin_1_undriven_sram_inv ) , - .out ( left_grid_pin_17_ ) , .p0 ( optlc_net_105 ) ) ; -cby_1__1__mux_tree_tapbuf_size8_4 mux_right_ipin_2 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , - chany_bottom_in[14] , chany_top_in[14] } ) , - .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_right_ipin_2_undriven_sram_inv ) , - .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_103 ) ) ; -cby_1__1__mux_tree_tapbuf_size8_5 mux_right_ipin_5 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , - chany_bottom_in[17] , chany_top_in[17] } ) , - .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_right_ipin_5_undriven_sram_inv ) , - .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_105 ) ) ; -cby_1__1__mux_tree_tapbuf_size8_6 mux_right_ipin_6 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , - chany_bottom_in[18] , chany_top_in[18] } ) , - .sram ( mux_tree_tapbuf_size8_3_sram ) , - .sram_inv ( mux_right_ipin_6_undriven_sram_inv ) , - .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_103 ) ) ; -cby_1__1__mux_tree_tapbuf_size8 mux_right_ipin_9 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , - chany_bottom_in[13] , chany_top_in[13] } ) , - .sram ( mux_tree_tapbuf_size8_4_sram ) , - .sram_inv ( mux_right_ipin_9_undriven_sram_inv ) , - .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_105 ) ) ; -cby_1__1__mux_tree_tapbuf_size8_1 mux_right_ipin_10 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , - chany_bottom_in[14] , chany_top_in[14] } ) , - .sram ( mux_tree_tapbuf_size8_5_sram ) , - .sram_inv ( mux_right_ipin_10_undriven_sram_inv ) , - .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_103 ) ) ; -cby_1__1__mux_tree_tapbuf_size8_2 mux_right_ipin_13 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , - chany_bottom_in[17] , chany_top_in[17] } ) , - .sram ( mux_tree_tapbuf_size8_6_sram ) , - .sram_inv ( mux_right_ipin_13_undriven_sram_inv ) , - .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_105 ) ) ; -cby_1__1__mux_tree_tapbuf_size8_3 mux_right_ipin_14 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , - chany_bottom_in[18] , chany_top_in[18] } ) , - .sram ( mux_tree_tapbuf_size8_7_sram ) , - .sram_inv ( mux_right_ipin_14_undriven_sram_inv ) , - .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_106 ) ) ; -cby_1__1__mux_tree_tapbuf_size8_mem_0 mem_right_ipin_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ; -cby_1__1__mux_tree_tapbuf_size8_mem_4 mem_right_ipin_2 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ; -cby_1__1__mux_tree_tapbuf_size8_mem_5 mem_right_ipin_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ; -cby_1__1__mux_tree_tapbuf_size8_mem_6 mem_right_ipin_6 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_3_sram ) ) ; -cby_1__1__mux_tree_tapbuf_size8_mem mem_right_ipin_9 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_4_sram ) ) ; -cby_1__1__mux_tree_tapbuf_size8_mem_1 mem_right_ipin_10 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_5_sram ) ) ; -cby_1__1__mux_tree_tapbuf_size8_mem_2 mem_right_ipin_13 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_6_sram ) ) ; -cby_1__1__mux_tree_tapbuf_size8_mem_3 mem_right_ipin_14 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_7_sram ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_bottom_in[0] ) , - .X ( chany_top_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chany_bottom_in[1] ) , - .X ( chany_top_out[1] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_103 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_bottom_in[3] ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_104 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_757 ( .A ( ropt_net_125 ) , - .X ( chany_bottom_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_bottom_in[6] ) , - .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_758 ( .A ( ropt_net_126 ) , - .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chany_bottom_in[8] ) , - .X ( ropt_net_118 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chany_bottom_in[9] ) , - .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chany_bottom_in[10] ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_105 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chany_bottom_in[12] ) , - .X ( chany_top_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chany_bottom_in[13] ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_106 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_127 ) , - .X ( chany_bottom_out[4] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__16 ( .A ( chany_bottom_in[16] ) , - .X ( ropt_net_119 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_760 ( .A ( ropt_net_128 ) , - .X ( chany_bottom_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chany_bottom_in[18] ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_20__19 ( .A ( chany_bottom_in[19] ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chany_top_in[0] ) , - .X ( chany_bottom_out[0] ) ) ; -sky130_fd_sc_hd__buf_2 prog_clk_0__bip372 ( .A ( prog_clk[0] ) , - .X ( ctsbuf_net_1107 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( chany_top_in[11] ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chany_top_in[3] ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__24 ( .A ( chany_top_in[4] ) , - .X ( ropt_net_124 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_116 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chany_top_in[6] ) , - .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chany_top_in[7] ) , - .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_29__28 ( .A ( chany_top_in[8] ) , - .X ( chany_bottom_out[8] ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_325697 ( .A ( ctsbuf_net_1107 ) , - .X ( prog_clk__FEEDTHRU_2[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_31__30 ( .A ( chany_top_in[10] ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( ropt_net_129 ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_326698 ( .A ( ctsbuf_net_1107 ) , - .X ( prog_clk__FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_110 ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_728 ( - .A ( chany_bottom_in[17] ) , .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_729 ( .A ( chany_bottom_in[4] ) , - .X ( chany_top_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_730 ( .A ( chany_bottom_in[5] ) , - .X ( ropt_net_126 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_130 ) , - .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_39__38 ( .A ( chany_top_in[18] ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( .A ( chany_top_in[17] ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_59 ( .A ( chany_bottom_in[2] ) , - .X ( chany_top_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_766 ( .A ( ropt_net_131 ) , - .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_768 ( .A ( ropt_net_132 ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_63 ( .A ( chany_bottom_in[14] ) , - .X ( ropt_net_117 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( - .A ( chany_bottom_in[11] ) , .X ( ropt_net_130 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_116 ) , - .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_68 ( .A ( chany_top_in[13] ) , - .X ( BUF_net_68 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( .A ( chany_top_in[15] ) , - .X ( BUF_net_69 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_70 ( .A ( chany_top_in[16] ) , - .X ( chany_bottom_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_117 ) , - .X ( ropt_net_129 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_75 ( .A ( chany_bottom_in[7] ) , - .X ( ropt_net_110 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_76 ( .A ( chany_bottom_in[15] ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( ropt_net_118 ) , - .X ( chany_top_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_119 ) , - .X ( ropt_net_131 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_120 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_121 ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( chany_top_in[2] ) , - .X ( chany_bottom_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_87 ( .A ( chany_top_in[9] ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_88 ( .A ( chany_top_in[14] ) , - .X ( ropt_net_121 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_93 ( .A ( BUF_net_68 ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_94 ( .A ( BUF_net_69 ) , - .X ( ropt_net_132 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_95 ( .A ( chany_top_in[19] ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( chany_top_in[12] ) , - .X ( ropt_net_125 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( chany_top_in[1] ) , - .X ( ropt_net_128 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_124 ) , - .X ( ropt_net_127 ) ) ; -endmodule - - diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/cby_1__1__icv_in_design.lvs.v b/FPGA22_HIER_SKY_PNR/modules/verilog/cby_1__1__icv_in_design.lvs.v deleted file mode 100644 index 647c46c..0000000 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/cby_1__1__icv_in_design.lvs.v +++ /dev/null @@ -1,2287 +0,0 @@ -// -// -// -// -// -// -module cby_1__1__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__55 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__54 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__53 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__52 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__51 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__50 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__49 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__48 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_8__47 ( .A ( mem_out[3] ) , - .X ( net_net_72 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_96 ( .A ( net_net_72 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__46 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__45 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__44 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__43 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__42 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__41 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__40 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_1__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , - chany_bottom_out , chany_top_out , left_grid_pin_16_ , left_grid_pin_17_ , - left_grid_pin_18_ , left_grid_pin_19_ , left_grid_pin_20_ , - left_grid_pin_21_ , left_grid_pin_22_ , left_grid_pin_23_ , - left_grid_pin_24_ , left_grid_pin_25_ , left_grid_pin_26_ , - left_grid_pin_27_ , left_grid_pin_28_ , left_grid_pin_29_ , - left_grid_pin_30_ , left_grid_pin_31_ , ccff_tail , VDD , VSS , - prog_clk__FEEDTHRU_1 , prog_clk__FEEDTHRU_2 ) ; -input [0:0] prog_clk ; -input [0:19] chany_bottom_in ; -input [0:19] chany_top_in ; -input [0:0] ccff_head ; -output [0:19] chany_bottom_out ; -output [0:19] chany_top_out ; -output [0:0] left_grid_pin_16_ ; -output [0:0] left_grid_pin_17_ ; -output [0:0] left_grid_pin_18_ ; -output [0:0] left_grid_pin_19_ ; -output [0:0] left_grid_pin_20_ ; -output [0:0] left_grid_pin_21_ ; -output [0:0] left_grid_pin_22_ ; -output [0:0] left_grid_pin_23_ ; -output [0:0] left_grid_pin_24_ ; -output [0:0] left_grid_pin_25_ ; -output [0:0] left_grid_pin_26_ ; -output [0:0] left_grid_pin_27_ ; -output [0:0] left_grid_pin_28_ ; -output [0:0] left_grid_pin_29_ ; -output [0:0] left_grid_pin_30_ ; -output [0:0] left_grid_pin_31_ ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; -output [0:0] prog_clk__FEEDTHRU_1 ; -output [0:0] prog_clk__FEEDTHRU_2 ; - -wire [0:3] mux_right_ipin_0_undriven_sram_inv ; -wire [0:3] mux_right_ipin_10_undriven_sram_inv ; -wire [0:3] mux_right_ipin_11_undriven_sram_inv ; -wire [0:3] mux_right_ipin_12_undriven_sram_inv ; -wire [0:3] mux_right_ipin_13_undriven_sram_inv ; -wire [0:3] mux_right_ipin_14_undriven_sram_inv ; -wire [0:3] mux_right_ipin_15_undriven_sram_inv ; -wire [0:3] mux_right_ipin_1_undriven_sram_inv ; -wire [0:3] mux_right_ipin_2_undriven_sram_inv ; -wire [0:3] mux_right_ipin_3_undriven_sram_inv ; -wire [0:3] mux_right_ipin_4_undriven_sram_inv ; -wire [0:3] mux_right_ipin_5_undriven_sram_inv ; -wire [0:3] mux_right_ipin_6_undriven_sram_inv ; -wire [0:3] mux_right_ipin_7_undriven_sram_inv ; -wire [0:3] mux_right_ipin_8_undriven_sram_inv ; -wire [0:3] mux_right_ipin_9_undriven_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:3] mux_tree_tapbuf_size10_2_sram ; -wire [0:3] mux_tree_tapbuf_size10_3_sram ; -wire [0:3] mux_tree_tapbuf_size10_4_sram ; -wire [0:3] mux_tree_tapbuf_size10_5_sram ; -wire [0:3] mux_tree_tapbuf_size10_6_sram ; -wire [0:3] mux_tree_tapbuf_size10_7_sram ; -wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:3] mux_tree_tapbuf_size8_2_sram ; -wire [0:3] mux_tree_tapbuf_size8_3_sram ; -wire [0:3] mux_tree_tapbuf_size8_4_sram ; -wire [0:3] mux_tree_tapbuf_size8_5_sram ; -wire [0:3] mux_tree_tapbuf_size8_6_sram ; -wire [0:3] mux_tree_tapbuf_size8_7_sram ; -wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ; -supply1 VDD ; -supply0 VSS ; -// - -cby_1__1__mux_tree_tapbuf_size10_0 mux_right_ipin_0 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , - chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , - chany_top_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_right_ipin_0_undriven_sram_inv ) , - .out ( left_grid_pin_16_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_103 ) ) ; -cby_1__1__mux_tree_tapbuf_size10_4 mux_right_ipin_3 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , - chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[19] , - chany_top_in[19] } ) , - .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_right_ipin_3_undriven_sram_inv ) , - .out ( left_grid_pin_19_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_105 ) ) ; -cby_1__1__mux_tree_tapbuf_size10_5 mux_right_ipin_4 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , - chany_bottom_in[8] , chany_top_in[8] , chany_bottom_in[14] , - chany_top_in[14] } ) , - .sram ( mux_tree_tapbuf_size10_2_sram ) , - .sram_inv ( mux_right_ipin_4_undriven_sram_inv ) , - .out ( left_grid_pin_20_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_103 ) ) ; -cby_1__1__mux_tree_tapbuf_size10_6 mux_right_ipin_7 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , - chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[17] , - chany_top_in[17] } ) , - .sram ( mux_tree_tapbuf_size10_3_sram ) , - .sram_inv ( mux_right_ipin_7_undriven_sram_inv ) , - .out ( left_grid_pin_23_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_104 ) ) ; -cby_1__1__mux_tree_tapbuf_size10 mux_right_ipin_8 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[8] , chany_top_in[8] , - chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[18] , - chany_top_in[18] } ) , - .sram ( mux_tree_tapbuf_size10_4_sram ) , - .sram_inv ( mux_right_ipin_8_undriven_sram_inv ) , - .out ( left_grid_pin_24_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_106 ) ) ; -cby_1__1__mux_tree_tapbuf_size10_1 mux_right_ipin_11 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , - chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[15] , - chany_top_in[15] } ) , - .sram ( mux_tree_tapbuf_size10_5_sram ) , - .sram_inv ( mux_right_ipin_11_undriven_sram_inv ) , - .out ( left_grid_pin_27_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_106 ) ) ; -cby_1__1__mux_tree_tapbuf_size10_2 mux_right_ipin_12 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , - chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[16] , - chany_top_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_6_sram ) , - .sram_inv ( mux_right_ipin_12_undriven_sram_inv ) , - .out ( left_grid_pin_28_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_106 ) ) ; -cby_1__1__mux_tree_tapbuf_size10_3 mux_right_ipin_15 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , - chany_bottom_in[15] , chany_top_in[15] , chany_bottom_in[19] , - chany_top_in[19] } ) , - .sram ( mux_tree_tapbuf_size10_7_sram ) , - .sram_inv ( mux_right_ipin_15_undriven_sram_inv ) , - .out ( left_grid_pin_31_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_104 ) ) ; -cby_1__1__mux_tree_tapbuf_size10_mem_0 mem_right_ipin_0 ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cby_1__1__mux_tree_tapbuf_size10_mem_4 mem_right_ipin_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cby_1__1__mux_tree_tapbuf_size10_mem_5 mem_right_ipin_4 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cby_1__1__mux_tree_tapbuf_size10_mem_6 mem_right_ipin_7 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cby_1__1__mux_tree_tapbuf_size10_mem mem_right_ipin_8 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cby_1__1__mux_tree_tapbuf_size10_mem_1 mem_right_ipin_11 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cby_1__1__mux_tree_tapbuf_size10_mem_2 mem_right_ipin_12 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cby_1__1__mux_tree_tapbuf_size10_mem_3 mem_right_ipin_15 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .ccff_tail ( { ropt_net_120 } ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cby_1__1__mux_tree_tapbuf_size8_0 mux_right_ipin_1 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , - chany_bottom_in[13] , chany_top_in[13] } ) , - .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_right_ipin_1_undriven_sram_inv ) , - .out ( left_grid_pin_17_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_105 ) ) ; -cby_1__1__mux_tree_tapbuf_size8_4 mux_right_ipin_2 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , - chany_bottom_in[14] , chany_top_in[14] } ) , - .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_right_ipin_2_undriven_sram_inv ) , - .out ( left_grid_pin_18_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_103 ) ) ; -cby_1__1__mux_tree_tapbuf_size8_5 mux_right_ipin_5 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , - chany_bottom_in[17] , chany_top_in[17] } ) , - .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_right_ipin_5_undriven_sram_inv ) , - .out ( left_grid_pin_21_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_105 ) ) ; -cby_1__1__mux_tree_tapbuf_size8_6 mux_right_ipin_6 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , - chany_bottom_in[18] , chany_top_in[18] } ) , - .sram ( mux_tree_tapbuf_size8_3_sram ) , - .sram_inv ( mux_right_ipin_6_undriven_sram_inv ) , - .out ( left_grid_pin_22_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_103 ) ) ; -cby_1__1__mux_tree_tapbuf_size8 mux_right_ipin_9 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , - chany_bottom_in[13] , chany_top_in[13] } ) , - .sram ( mux_tree_tapbuf_size8_4_sram ) , - .sram_inv ( mux_right_ipin_9_undriven_sram_inv ) , - .out ( left_grid_pin_25_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_105 ) ) ; -cby_1__1__mux_tree_tapbuf_size8_1 mux_right_ipin_10 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , - chany_bottom_in[14] , chany_top_in[14] } ) , - .sram ( mux_tree_tapbuf_size8_5_sram ) , - .sram_inv ( mux_right_ipin_10_undriven_sram_inv ) , - .out ( left_grid_pin_26_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_103 ) ) ; -cby_1__1__mux_tree_tapbuf_size8_2 mux_right_ipin_13 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , - chany_bottom_in[17] , chany_top_in[17] } ) , - .sram ( mux_tree_tapbuf_size8_6_sram ) , - .sram_inv ( mux_right_ipin_13_undriven_sram_inv ) , - .out ( left_grid_pin_29_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_105 ) ) ; -cby_1__1__mux_tree_tapbuf_size8_3 mux_right_ipin_14 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , - chany_bottom_in[18] , chany_top_in[18] } ) , - .sram ( mux_tree_tapbuf_size8_7_sram ) , - .sram_inv ( mux_right_ipin_14_undriven_sram_inv ) , - .out ( left_grid_pin_30_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_106 ) ) ; -cby_1__1__mux_tree_tapbuf_size8_mem_0 mem_right_ipin_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cby_1__1__mux_tree_tapbuf_size8_mem_4 mem_right_ipin_2 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cby_1__1__mux_tree_tapbuf_size8_mem_5 mem_right_ipin_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cby_1__1__mux_tree_tapbuf_size8_mem_6 mem_right_ipin_6 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cby_1__1__mux_tree_tapbuf_size8_mem mem_right_ipin_9 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cby_1__1__mux_tree_tapbuf_size8_mem_1 mem_right_ipin_10 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cby_1__1__mux_tree_tapbuf_size8_mem_2 mem_right_ipin_13 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cby_1__1__mux_tree_tapbuf_size8_mem_3 mem_right_ipin_14 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1652 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1653 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1654 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1655 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1656 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1657 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1658 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1659 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1660 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1661 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1662 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1663 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1664 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1665 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1666 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_bottom_in[0] ) , - .X ( chany_top_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chany_bottom_in[1] ) , - .X ( chany_top_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_bottom_in[3] ) , - .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_757 ( .A ( ropt_net_125 ) , - .X ( chany_bottom_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_bottom_in[6] ) , - .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_758 ( .A ( ropt_net_126 ) , - .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chany_bottom_in[8] ) , - .X ( ropt_net_118 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chany_bottom_in[9] ) , - .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chany_bottom_in[10] ) , - .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chany_bottom_in[12] ) , - .X ( chany_top_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chany_bottom_in[13] ) , - .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_127 ) , - .X ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__16 ( .A ( chany_bottom_in[16] ) , - .X ( ropt_net_119 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_760 ( .A ( ropt_net_128 ) , - .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chany_bottom_in[18] ) , - .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_20__19 ( .A ( chany_bottom_in[19] ) , - .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chany_top_in[0] ) , - .X ( chany_bottom_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_2 prog_clk_0__bip372 ( .A ( prog_clk[0] ) , - .X ( ctsbuf_net_1107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( chany_top_in[11] ) , - .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chany_top_in[3] ) , - .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__24 ( .A ( chany_top_in[4] ) , - .X ( ropt_net_124 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_116 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chany_top_in[6] ) , - .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chany_top_in[7] ) , - .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_29__28 ( .A ( chany_top_in[8] ) , - .X ( chany_bottom_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_325697 ( .A ( ctsbuf_net_1107 ) , - .X ( prog_clk__FEEDTHRU_2[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_31__30 ( .A ( chany_top_in[10] ) , - .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( ropt_net_129 ) , - .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_326698 ( .A ( ctsbuf_net_1107 ) , - .X ( prog_clk__FEEDTHRU_1[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_110 ) , - .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_728 ( - .A ( chany_bottom_in[17] ) , .X ( chany_top_out[17] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_729 ( .A ( chany_bottom_in[4] ) , - .X ( chany_top_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_730 ( .A ( chany_bottom_in[5] ) , - .X ( ropt_net_126 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_130 ) , - .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_39__38 ( .A ( chany_top_in[18] ) , - .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( .A ( chany_top_in[17] ) , - .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_59 ( .A ( chany_bottom_in[2] ) , - .X ( chany_top_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_766 ( .A ( ropt_net_131 ) , - .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_768 ( .A ( ropt_net_132 ) , - .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_63 ( .A ( chany_bottom_in[14] ) , - .X ( ropt_net_117 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( - .A ( chany_bottom_in[11] ) , .X ( ropt_net_130 ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_116 ) , - .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_68 ( .A ( chany_top_in[13] ) , - .X ( BUF_net_68 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( .A ( chany_top_in[15] ) , - .X ( BUF_net_69 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_70 ( .A ( chany_top_in[16] ) , - .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_117 ) , - .X ( ropt_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_75 ( .A ( chany_bottom_in[7] ) , - .X ( ropt_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_76 ( .A ( chany_bottom_in[15] ) , - .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( ropt_net_118 ) , - .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_119 ) , - .X ( ropt_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_120 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_121 ) , - .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( chany_top_in[2] ) , - .X ( chany_bottom_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_87 ( .A ( chany_top_in[9] ) , - .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_88 ( .A ( chany_top_in[14] ) , - .X ( ropt_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_93 ( .A ( BUF_net_68 ) , - .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_94 ( .A ( BUF_net_69 ) , - .X ( ropt_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_95 ( .A ( chany_top_in[19] ) , - .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( chany_top_in[12] ) , - .X ( ropt_net_125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( chany_top_in[1] ) , - .X ( ropt_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_124 ) , - .X ( ropt_net_127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y0 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y0 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x36800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x151800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x312800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x331200y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x575000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x174800y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x225400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x211600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x230000y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x36800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x446200y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x533600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x552000y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x598000y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x450800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x501400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x510600y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x556600y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x55200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x105800y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x602600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x128800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x138000y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x368000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x386400y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x197800y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x515200y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x64400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x147200y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x193200y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x82800y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x161000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x55200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x115000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x133400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x243800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x285200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x294400y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x469200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x547400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x556600y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x36800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x87400y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x207000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x225400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x483000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x501400y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x312800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x349600y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x552000y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x184000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x234600y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x354200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x409400y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x455400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x464600y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x542800y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x588800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x607200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x616400y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x101200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x151800y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x478400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x128800y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x174800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x225400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x243800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x294400y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x36800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x455400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x174800y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x101200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x110400y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x197800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x418600y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x105800y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x326600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x575000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x101200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x119600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/cby_1__1__icv_in_design.pt.v b/FPGA22_HIER_SKY_PNR/modules/verilog/cby_1__1__icv_in_design.pt.v deleted file mode 100644 index 22cbefd..0000000 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/cby_1__1__icv_in_design.pt.v +++ /dev/null @@ -1,1503 +0,0 @@ -// -// -// -// -// -// -module cby_1__1__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__55 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__54 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__53 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__52 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__51 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__50 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__49 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__48 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_8__47 ( .A ( mem_out[3] ) , - .X ( net_net_72 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_96 ( .A ( net_net_72 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__46 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__45 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__44 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__43 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__42 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__41 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__40 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cby_1__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cby_1__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , - chany_bottom_out , chany_top_out , left_grid_pin_16_ , left_grid_pin_17_ , - left_grid_pin_18_ , left_grid_pin_19_ , left_grid_pin_20_ , - left_grid_pin_21_ , left_grid_pin_22_ , left_grid_pin_23_ , - left_grid_pin_24_ , left_grid_pin_25_ , left_grid_pin_26_ , - left_grid_pin_27_ , left_grid_pin_28_ , left_grid_pin_29_ , - left_grid_pin_30_ , left_grid_pin_31_ , ccff_tail , prog_clk__FEEDTHRU_1 , - prog_clk__FEEDTHRU_2 ) ; -input [0:0] prog_clk ; -input [0:19] chany_bottom_in ; -input [0:19] chany_top_in ; -input [0:0] ccff_head ; -output [0:19] chany_bottom_out ; -output [0:19] chany_top_out ; -output [0:0] left_grid_pin_16_ ; -output [0:0] left_grid_pin_17_ ; -output [0:0] left_grid_pin_18_ ; -output [0:0] left_grid_pin_19_ ; -output [0:0] left_grid_pin_20_ ; -output [0:0] left_grid_pin_21_ ; -output [0:0] left_grid_pin_22_ ; -output [0:0] left_grid_pin_23_ ; -output [0:0] left_grid_pin_24_ ; -output [0:0] left_grid_pin_25_ ; -output [0:0] left_grid_pin_26_ ; -output [0:0] left_grid_pin_27_ ; -output [0:0] left_grid_pin_28_ ; -output [0:0] left_grid_pin_29_ ; -output [0:0] left_grid_pin_30_ ; -output [0:0] left_grid_pin_31_ ; -output [0:0] ccff_tail ; -output [0:0] prog_clk__FEEDTHRU_1 ; -output [0:0] prog_clk__FEEDTHRU_2 ; - -wire [0:3] mux_right_ipin_0_undriven_sram_inv ; -wire [0:3] mux_right_ipin_10_undriven_sram_inv ; -wire [0:3] mux_right_ipin_11_undriven_sram_inv ; -wire [0:3] mux_right_ipin_12_undriven_sram_inv ; -wire [0:3] mux_right_ipin_13_undriven_sram_inv ; -wire [0:3] mux_right_ipin_14_undriven_sram_inv ; -wire [0:3] mux_right_ipin_15_undriven_sram_inv ; -wire [0:3] mux_right_ipin_1_undriven_sram_inv ; -wire [0:3] mux_right_ipin_2_undriven_sram_inv ; -wire [0:3] mux_right_ipin_3_undriven_sram_inv ; -wire [0:3] mux_right_ipin_4_undriven_sram_inv ; -wire [0:3] mux_right_ipin_5_undriven_sram_inv ; -wire [0:3] mux_right_ipin_6_undriven_sram_inv ; -wire [0:3] mux_right_ipin_7_undriven_sram_inv ; -wire [0:3] mux_right_ipin_8_undriven_sram_inv ; -wire [0:3] mux_right_ipin_9_undriven_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:3] mux_tree_tapbuf_size10_2_sram ; -wire [0:3] mux_tree_tapbuf_size10_3_sram ; -wire [0:3] mux_tree_tapbuf_size10_4_sram ; -wire [0:3] mux_tree_tapbuf_size10_5_sram ; -wire [0:3] mux_tree_tapbuf_size10_6_sram ; -wire [0:3] mux_tree_tapbuf_size10_7_sram ; -wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:3] mux_tree_tapbuf_size8_2_sram ; -wire [0:3] mux_tree_tapbuf_size8_3_sram ; -wire [0:3] mux_tree_tapbuf_size8_4_sram ; -wire [0:3] mux_tree_tapbuf_size8_5_sram ; -wire [0:3] mux_tree_tapbuf_size8_6_sram ; -wire [0:3] mux_tree_tapbuf_size8_7_sram ; -wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ; -// - -cby_1__1__mux_tree_tapbuf_size10_0 mux_right_ipin_0 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , - chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , - chany_top_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_right_ipin_0_undriven_sram_inv ) , - .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_103 ) ) ; -cby_1__1__mux_tree_tapbuf_size10_4 mux_right_ipin_3 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , - chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[19] , - chany_top_in[19] } ) , - .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_right_ipin_3_undriven_sram_inv ) , - .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_105 ) ) ; -cby_1__1__mux_tree_tapbuf_size10_5 mux_right_ipin_4 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , - chany_bottom_in[8] , chany_top_in[8] , chany_bottom_in[14] , - chany_top_in[14] } ) , - .sram ( mux_tree_tapbuf_size10_2_sram ) , - .sram_inv ( mux_right_ipin_4_undriven_sram_inv ) , - .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_103 ) ) ; -cby_1__1__mux_tree_tapbuf_size10_6 mux_right_ipin_7 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , - chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[17] , - chany_top_in[17] } ) , - .sram ( mux_tree_tapbuf_size10_3_sram ) , - .sram_inv ( mux_right_ipin_7_undriven_sram_inv ) , - .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_104 ) ) ; -cby_1__1__mux_tree_tapbuf_size10 mux_right_ipin_8 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[8] , chany_top_in[8] , - chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[18] , - chany_top_in[18] } ) , - .sram ( mux_tree_tapbuf_size10_4_sram ) , - .sram_inv ( mux_right_ipin_8_undriven_sram_inv ) , - .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_106 ) ) ; -cby_1__1__mux_tree_tapbuf_size10_1 mux_right_ipin_11 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , - chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[15] , - chany_top_in[15] } ) , - .sram ( mux_tree_tapbuf_size10_5_sram ) , - .sram_inv ( mux_right_ipin_11_undriven_sram_inv ) , - .out ( left_grid_pin_27_ ) , .p0 ( optlc_net_106 ) ) ; -cby_1__1__mux_tree_tapbuf_size10_2 mux_right_ipin_12 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , - chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[16] , - chany_top_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_6_sram ) , - .sram_inv ( mux_right_ipin_12_undriven_sram_inv ) , - .out ( left_grid_pin_28_ ) , .p0 ( optlc_net_106 ) ) ; -cby_1__1__mux_tree_tapbuf_size10_3 mux_right_ipin_15 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , - chany_bottom_in[15] , chany_top_in[15] , chany_bottom_in[19] , - chany_top_in[19] } ) , - .sram ( mux_tree_tapbuf_size10_7_sram ) , - .sram_inv ( mux_right_ipin_15_undriven_sram_inv ) , - .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_104 ) ) ; -cby_1__1__mux_tree_tapbuf_size10_mem_0 mem_right_ipin_0 ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; -cby_1__1__mux_tree_tapbuf_size10_mem_4 mem_right_ipin_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ; -cby_1__1__mux_tree_tapbuf_size10_mem_5 mem_right_ipin_4 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ; -cby_1__1__mux_tree_tapbuf_size10_mem_6 mem_right_ipin_7 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ; -cby_1__1__mux_tree_tapbuf_size10_mem mem_right_ipin_8 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ; -cby_1__1__mux_tree_tapbuf_size10_mem_1 mem_right_ipin_11 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ; -cby_1__1__mux_tree_tapbuf_size10_mem_2 mem_right_ipin_12 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ; -cby_1__1__mux_tree_tapbuf_size10_mem_3 mem_right_ipin_15 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .ccff_tail ( { ropt_net_120 } ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ; -cby_1__1__mux_tree_tapbuf_size8_0 mux_right_ipin_1 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , - chany_bottom_in[13] , chany_top_in[13] } ) , - .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_right_ipin_1_undriven_sram_inv ) , - .out ( left_grid_pin_17_ ) , .p0 ( optlc_net_105 ) ) ; -cby_1__1__mux_tree_tapbuf_size8_4 mux_right_ipin_2 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , - chany_bottom_in[14] , chany_top_in[14] } ) , - .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_right_ipin_2_undriven_sram_inv ) , - .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_103 ) ) ; -cby_1__1__mux_tree_tapbuf_size8_5 mux_right_ipin_5 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , - chany_bottom_in[17] , chany_top_in[17] } ) , - .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_right_ipin_5_undriven_sram_inv ) , - .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_105 ) ) ; -cby_1__1__mux_tree_tapbuf_size8_6 mux_right_ipin_6 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , - chany_bottom_in[18] , chany_top_in[18] } ) , - .sram ( mux_tree_tapbuf_size8_3_sram ) , - .sram_inv ( mux_right_ipin_6_undriven_sram_inv ) , - .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_103 ) ) ; -cby_1__1__mux_tree_tapbuf_size8 mux_right_ipin_9 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , - chany_bottom_in[13] , chany_top_in[13] } ) , - .sram ( mux_tree_tapbuf_size8_4_sram ) , - .sram_inv ( mux_right_ipin_9_undriven_sram_inv ) , - .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_105 ) ) ; -cby_1__1__mux_tree_tapbuf_size8_1 mux_right_ipin_10 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , - chany_bottom_in[14] , chany_top_in[14] } ) , - .sram ( mux_tree_tapbuf_size8_5_sram ) , - .sram_inv ( mux_right_ipin_10_undriven_sram_inv ) , - .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_103 ) ) ; -cby_1__1__mux_tree_tapbuf_size8_2 mux_right_ipin_13 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , - chany_bottom_in[17] , chany_top_in[17] } ) , - .sram ( mux_tree_tapbuf_size8_6_sram ) , - .sram_inv ( mux_right_ipin_13_undriven_sram_inv ) , - .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_105 ) ) ; -cby_1__1__mux_tree_tapbuf_size8_3 mux_right_ipin_14 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , - chany_bottom_in[18] , chany_top_in[18] } ) , - .sram ( mux_tree_tapbuf_size8_7_sram ) , - .sram_inv ( mux_right_ipin_14_undriven_sram_inv ) , - .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_106 ) ) ; -cby_1__1__mux_tree_tapbuf_size8_mem_0 mem_right_ipin_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ; -cby_1__1__mux_tree_tapbuf_size8_mem_4 mem_right_ipin_2 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ; -cby_1__1__mux_tree_tapbuf_size8_mem_5 mem_right_ipin_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ; -cby_1__1__mux_tree_tapbuf_size8_mem_6 mem_right_ipin_6 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_3_sram ) ) ; -cby_1__1__mux_tree_tapbuf_size8_mem mem_right_ipin_9 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_4_sram ) ) ; -cby_1__1__mux_tree_tapbuf_size8_mem_1 mem_right_ipin_10 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_5_sram ) ) ; -cby_1__1__mux_tree_tapbuf_size8_mem_2 mem_right_ipin_13 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_6_sram ) ) ; -cby_1__1__mux_tree_tapbuf_size8_mem_3 mem_right_ipin_14 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_7_sram ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_bottom_in[0] ) , - .X ( chany_top_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chany_bottom_in[1] ) , - .X ( chany_top_out[1] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_103 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_bottom_in[3] ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_104 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_757 ( .A ( ropt_net_125 ) , - .X ( chany_bottom_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_bottom_in[6] ) , - .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_758 ( .A ( ropt_net_126 ) , - .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chany_bottom_in[8] ) , - .X ( ropt_net_118 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chany_bottom_in[9] ) , - .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chany_bottom_in[10] ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_105 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chany_bottom_in[12] ) , - .X ( chany_top_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chany_bottom_in[13] ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_106 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_127 ) , - .X ( chany_bottom_out[4] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__16 ( .A ( chany_bottom_in[16] ) , - .X ( ropt_net_119 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_760 ( .A ( ropt_net_128 ) , - .X ( chany_bottom_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chany_bottom_in[18] ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_20__19 ( .A ( chany_bottom_in[19] ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chany_top_in[0] ) , - .X ( chany_bottom_out[0] ) ) ; -sky130_fd_sc_hd__buf_2 prog_clk_0__bip372 ( .A ( prog_clk[0] ) , - .X ( ctsbuf_net_1107 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( chany_top_in[11] ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chany_top_in[3] ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__24 ( .A ( chany_top_in[4] ) , - .X ( ropt_net_124 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_116 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chany_top_in[6] ) , - .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chany_top_in[7] ) , - .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_29__28 ( .A ( chany_top_in[8] ) , - .X ( chany_bottom_out[8] ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_325697 ( .A ( ctsbuf_net_1107 ) , - .X ( prog_clk__FEEDTHRU_2[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_31__30 ( .A ( chany_top_in[10] ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( ropt_net_129 ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_326698 ( .A ( ctsbuf_net_1107 ) , - .X ( prog_clk__FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_110 ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_728 ( - .A ( chany_bottom_in[17] ) , .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_729 ( .A ( chany_bottom_in[4] ) , - .X ( chany_top_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_730 ( .A ( chany_bottom_in[5] ) , - .X ( ropt_net_126 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_130 ) , - .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_39__38 ( .A ( chany_top_in[18] ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( .A ( chany_top_in[17] ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_59 ( .A ( chany_bottom_in[2] ) , - .X ( chany_top_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_766 ( .A ( ropt_net_131 ) , - .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_768 ( .A ( ropt_net_132 ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_63 ( .A ( chany_bottom_in[14] ) , - .X ( ropt_net_117 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( - .A ( chany_bottom_in[11] ) , .X ( ropt_net_130 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_116 ) , - .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_68 ( .A ( chany_top_in[13] ) , - .X ( BUF_net_68 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( .A ( chany_top_in[15] ) , - .X ( BUF_net_69 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_70 ( .A ( chany_top_in[16] ) , - .X ( chany_bottom_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_117 ) , - .X ( ropt_net_129 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_75 ( .A ( chany_bottom_in[7] ) , - .X ( ropt_net_110 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_76 ( .A ( chany_bottom_in[15] ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( ropt_net_118 ) , - .X ( chany_top_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_119 ) , - .X ( ropt_net_131 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_120 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_121 ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( chany_top_in[2] ) , - .X ( chany_bottom_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_87 ( .A ( chany_top_in[9] ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_88 ( .A ( chany_top_in[14] ) , - .X ( ropt_net_121 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_93 ( .A ( BUF_net_68 ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_94 ( .A ( BUF_net_69 ) , - .X ( ropt_net_132 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_95 ( .A ( chany_top_in[19] ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( chany_top_in[12] ) , - .X ( ropt_net_125 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( chany_top_in[1] ) , - .X ( ropt_net_128 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_124 ) , - .X ( ropt_net_127 ) ) ; -endmodule - - diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/cby_2__1__icv_in_design.fm.v b/FPGA22_HIER_SKY_PNR/modules/verilog/cby_2__1__icv_in_design.fm.v deleted file mode 100644 index 3fad510..0000000 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/cby_2__1__icv_in_design.fm.v +++ /dev/null @@ -1,1817 +0,0 @@ -// -// -// -// -// -// -module cby_2__1__direct_interc ( in , out ) ; -input [0:0] in ; -output [0:0] out ; - -assign out[0] = in[0] ; -endmodule - - -module cby_2__1__direct_interc_0 ( in , out ) ; -input [0:0] in ; -output [0:0] out ; -endmodule - - -module cby_2__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( prog_clk , - ccff_head , ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:0] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_20__60 ( .A ( mem_out[0] ) , - .X ( net_net_80 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_80 ( .A ( net_net_80 ) , - .X ( net_net_79 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_101 ( .A ( net_net_79 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_2__1__EMBEDDED_IO ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , - FPGA_OUT , FPGA_DIR , p_abuf0 ) ; -input SOC_IN ; -output SOC_OUT ; -output SOC_DIR ; -output FPGA_IN ; -input FPGA_OUT ; -input FPGA_DIR ; -output p_abuf0 ; - -assign SOC_OUT = FPGA_OUT ; - -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__58 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 FTB_19__59 ( .A ( FPGA_DIR ) , - .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_62 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; -endmodule - - -module cby_2__1__logical_tile_io_mode_physical__iopad ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] iopad_outpad ; -input [0:0] ccff_head ; -output [0:0] iopad_inpad ; -output [0:0] ccff_tail ; -output p_abuf0 ; - -wire [0:0] EMBEDDED_IO_0_en ; - -cby_2__1__EMBEDDED_IO EMBEDDED_IO_0_ ( - .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , - .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , - .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , - .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; -cby_2__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) ) ; -endmodule - - -module cby_2__1__logical_tile_io_mode_io_ ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , - ccff_tail , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] io_outpad ; -input [0:0] ccff_head ; -output [0:0] io_inpad ; -output [0:0] ccff_tail ; -output p_abuf0 ; - -cby_2__1__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , - .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , - .p_abuf0 ( p_abuf0 ) ) ; -cby_2__1__direct_interc_0 direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; -cby_2__1__direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( io_outpad ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__57 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__56 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__55 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__54 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__53 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__52 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__51 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__50 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_2__1__const1 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -cby_2__1__const1 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cby_2__1__const1_15 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -cby_2__1__const1_15 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cby_2__1__const1_14 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -cby_2__1__const1_14 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_4 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; -endmodule - - -module cby_2__1__const1_13 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -cby_2__1__const1_13 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cby_2__1__const1_12 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -cby_2__1__const1_12 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cby_2__1__const1_11 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -cby_2__1__const1_11 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cby_2__1__const1_10 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -cby_2__1__const1_10 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cby_2__1__const1_9 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -cby_2__1__const1_9 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__49 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__48 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__47 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__46 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__45 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__44 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__43 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__42 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__41 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_2__1__const1_8 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -cby_2__1__const1_8 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cby_2__1__const1_7 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -cby_2__1__const1_7 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cby_2__1__const1_6 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -cby_2__1__const1_6 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cby_2__1__const1_5 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -cby_2__1__const1_5 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cby_2__1__const1_4 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -cby_2__1__const1_4 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cby_2__1__const1_3 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -cby_2__1__const1_3 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cby_2__1__const1_2 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -cby_2__1__const1_2 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cby_2__1__const1_1 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -cby_2__1__const1_1 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cby_2__1__const1_0 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -cby_2__1__const1_0 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cby_2__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , - chany_bottom_out , chany_top_out , right_grid_pin_0_ , left_grid_pin_16_ , - left_grid_pin_17_ , left_grid_pin_18_ , left_grid_pin_19_ , - left_grid_pin_20_ , left_grid_pin_21_ , left_grid_pin_22_ , - left_grid_pin_23_ , left_grid_pin_24_ , left_grid_pin_25_ , - left_grid_pin_26_ , left_grid_pin_27_ , left_grid_pin_28_ , - left_grid_pin_29_ , left_grid_pin_30_ , left_grid_pin_31_ , ccff_tail , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , left_width_0_height_0__pin_0_ , - left_width_0_height_0__pin_1_upper , left_width_0_height_0__pin_1_lower ) ; -input [0:0] prog_clk ; -input [0:19] chany_bottom_in ; -input [0:19] chany_top_in ; -input [0:0] ccff_head ; -output [0:19] chany_bottom_out ; -output [0:19] chany_top_out ; -output [0:0] right_grid_pin_0_ ; -output [0:0] left_grid_pin_16_ ; -output [0:0] left_grid_pin_17_ ; -output [0:0] left_grid_pin_18_ ; -output [0:0] left_grid_pin_19_ ; -output [0:0] left_grid_pin_20_ ; -output [0:0] left_grid_pin_21_ ; -output [0:0] left_grid_pin_22_ ; -output [0:0] left_grid_pin_23_ ; -output [0:0] left_grid_pin_24_ ; -output [0:0] left_grid_pin_25_ ; -output [0:0] left_grid_pin_26_ ; -output [0:0] left_grid_pin_27_ ; -output [0:0] left_grid_pin_28_ ; -output [0:0] left_grid_pin_29_ ; -output [0:0] left_grid_pin_30_ ; -output [0:0] left_grid_pin_31_ ; -output [0:0] ccff_tail ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] left_width_0_height_0__pin_0_ ; -output [0:0] left_width_0_height_0__pin_1_upper ; -output [0:0] left_width_0_height_0__pin_1_lower ; - -wire ropt_net_114 ; -wire [0:3] mux_left_ipin_0_undriven_sram_inv ; -wire [0:3] mux_right_ipin_0_undriven_sram_inv ; -wire [0:3] mux_right_ipin_10_undriven_sram_inv ; -wire [0:3] mux_right_ipin_11_undriven_sram_inv ; -wire [0:3] mux_right_ipin_12_undriven_sram_inv ; -wire [0:3] mux_right_ipin_13_undriven_sram_inv ; -wire [0:3] mux_right_ipin_14_undriven_sram_inv ; -wire [0:3] mux_right_ipin_15_undriven_sram_inv ; -wire [0:3] mux_right_ipin_1_undriven_sram_inv ; -wire [0:3] mux_right_ipin_2_undriven_sram_inv ; -wire [0:3] mux_right_ipin_3_undriven_sram_inv ; -wire [0:3] mux_right_ipin_4_undriven_sram_inv ; -wire [0:3] mux_right_ipin_5_undriven_sram_inv ; -wire [0:3] mux_right_ipin_6_undriven_sram_inv ; -wire [0:3] mux_right_ipin_7_undriven_sram_inv ; -wire [0:3] mux_right_ipin_8_undriven_sram_inv ; -wire [0:3] mux_right_ipin_9_undriven_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:3] mux_tree_tapbuf_size10_2_sram ; -wire [0:3] mux_tree_tapbuf_size10_3_sram ; -wire [0:3] mux_tree_tapbuf_size10_4_sram ; -wire [0:3] mux_tree_tapbuf_size10_5_sram ; -wire [0:3] mux_tree_tapbuf_size10_6_sram ; -wire [0:3] mux_tree_tapbuf_size10_7_sram ; -wire [0:3] mux_tree_tapbuf_size10_8_sram ; -wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:3] mux_tree_tapbuf_size8_2_sram ; -wire [0:3] mux_tree_tapbuf_size8_3_sram ; -wire [0:3] mux_tree_tapbuf_size8_4_sram ; -wire [0:3] mux_tree_tapbuf_size8_5_sram ; -wire [0:3] mux_tree_tapbuf_size8_6_sram ; -wire [0:3] mux_tree_tapbuf_size8_7_sram ; -wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ; -// - -cby_2__1__mux_tree_tapbuf_size10_0 mux_left_ipin_0 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , - chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , - chany_top_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_left_ipin_0_undriven_sram_inv ) , - .out ( right_grid_pin_0_ ) , .p0 ( optlc_net_111 ) ) ; -cby_2__1__mux_tree_tapbuf_size10_1 mux_right_ipin_0 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , - chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[17] , - chany_top_in[17] } ) , - .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_right_ipin_0_undriven_sram_inv ) , - .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_110 ) ) ; -cby_2__1__mux_tree_tapbuf_size10_5 mux_right_ipin_3 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , - chany_bottom_in[8] , chany_top_in[8] , chany_bottom_in[14] , - chany_top_in[14] } ) , - .sram ( mux_tree_tapbuf_size10_2_sram ) , - .sram_inv ( mux_right_ipin_3_undriven_sram_inv ) , - .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_109 ) ) ; -cby_2__1__mux_tree_tapbuf_size10_6 mux_right_ipin_4 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , - chany_bottom_in[9] , chany_top_in[9] , chany_bottom_in[15] , - chany_top_in[15] } ) , - .sram ( mux_tree_tapbuf_size10_3_sram ) , - .sram_inv ( mux_right_ipin_4_undriven_sram_inv ) , - .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_108 ) ) ; -cby_2__1__mux_tree_tapbuf_size10_7 mux_right_ipin_7 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[8] , chany_top_in[8] , - chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[18] , - chany_top_in[18] } ) , - .sram ( mux_tree_tapbuf_size10_4_sram ) , - .sram_inv ( mux_right_ipin_7_undriven_sram_inv ) , - .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_109 ) ) ; -cby_2__1__mux_tree_tapbuf_size10 mux_right_ipin_8 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , - chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[19] , - chany_top_in[19] } ) , - .sram ( mux_tree_tapbuf_size10_5_sram ) , - .sram_inv ( mux_right_ipin_8_undriven_sram_inv ) , - .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_108 ) ) ; -cby_2__1__mux_tree_tapbuf_size10_2 mux_right_ipin_11 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , - chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[16] , - chany_top_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_6_sram ) , - .sram_inv ( mux_right_ipin_11_undriven_sram_inv ) , - .out ( left_grid_pin_27_ ) , .p0 ( optlc_net_109 ) ) ; -cby_2__1__mux_tree_tapbuf_size10_3 mux_right_ipin_12 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , - chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[17] , - chany_top_in[17] } ) , - .sram ( mux_tree_tapbuf_size10_7_sram ) , - .sram_inv ( mux_right_ipin_12_undriven_sram_inv ) , - .out ( left_grid_pin_28_ ) , .p0 ( optlc_net_108 ) ) ; -cby_2__1__mux_tree_tapbuf_size10_4 mux_right_ipin_15 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , - chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , - chany_top_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_8_sram ) , - .sram_inv ( mux_right_ipin_15_undriven_sram_inv ) , - .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_111 ) ) ; -cby_2__1__mux_tree_tapbuf_size10_mem_0 mem_left_ipin_0 ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; -cby_2__1__mux_tree_tapbuf_size10_mem_1 mem_right_ipin_0 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ; -cby_2__1__mux_tree_tapbuf_size10_mem_5 mem_right_ipin_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ; -cby_2__1__mux_tree_tapbuf_size10_mem_6 mem_right_ipin_4 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ; -cby_2__1__mux_tree_tapbuf_size10_mem_7 mem_right_ipin_7 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ; -cby_2__1__mux_tree_tapbuf_size10_mem mem_right_ipin_8 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ; -cby_2__1__mux_tree_tapbuf_size10_mem_2 mem_right_ipin_11 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ; -cby_2__1__mux_tree_tapbuf_size10_mem_3 mem_right_ipin_12 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ; -cby_2__1__mux_tree_tapbuf_size10_mem_4 mem_right_ipin_15 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , - .mem_out ( mux_tree_tapbuf_size10_8_sram ) ) ; -cby_2__1__mux_tree_tapbuf_size8_0 mux_right_ipin_1 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , - chany_bottom_in[14] , chany_top_in[14] } ) , - .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_right_ipin_1_undriven_sram_inv ) , - .out ( left_grid_pin_17_ ) , .p0 ( optlc_net_111 ) ) ; -cby_2__1__mux_tree_tapbuf_size8_4 mux_right_ipin_2 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , - chany_bottom_in[15] , chany_top_in[15] } ) , - .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_right_ipin_2_undriven_sram_inv ) , - .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_108 ) ) ; -cby_2__1__mux_tree_tapbuf_size8_5 mux_right_ipin_5 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , - chany_bottom_in[18] , chany_top_in[18] } ) , - .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_right_ipin_5_undriven_sram_inv ) , - .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_111 ) ) ; -cby_2__1__mux_tree_tapbuf_size8_6 mux_right_ipin_6 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[11] , chany_top_in[11] , - chany_bottom_in[19] , chany_top_in[19] } ) , - .sram ( mux_tree_tapbuf_size8_3_sram ) , - .sram_inv ( mux_right_ipin_6_undriven_sram_inv ) , - .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_110 ) ) ; -cby_2__1__mux_tree_tapbuf_size8 mux_right_ipin_9 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , - chany_bottom_in[14] , chany_top_in[14] } ) , - .sram ( mux_tree_tapbuf_size8_4_sram ) , - .sram_inv ( mux_right_ipin_9_undriven_sram_inv ) , - .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_111 ) ) ; -cby_2__1__mux_tree_tapbuf_size8_1 mux_right_ipin_10 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , - chany_bottom_in[15] , chany_top_in[15] } ) , - .sram ( mux_tree_tapbuf_size8_5_sram ) , - .sram_inv ( mux_right_ipin_10_undriven_sram_inv ) , - .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_108 ) ) ; -cby_2__1__mux_tree_tapbuf_size8_2 mux_right_ipin_13 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , - chany_bottom_in[18] , chany_top_in[18] } ) , - .sram ( mux_tree_tapbuf_size8_6_sram ) , - .sram_inv ( mux_right_ipin_13_undriven_sram_inv ) , - .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_111 ) ) ; -cby_2__1__mux_tree_tapbuf_size8_3 mux_right_ipin_14 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[11] , chany_top_in[11] , - chany_bottom_in[19] , chany_top_in[19] } ) , - .sram ( mux_tree_tapbuf_size8_7_sram ) , - .sram_inv ( mux_right_ipin_14_undriven_sram_inv ) , - .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_110 ) ) ; -cby_2__1__mux_tree_tapbuf_size8_mem_0 mem_right_ipin_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ; -cby_2__1__mux_tree_tapbuf_size8_mem_4 mem_right_ipin_2 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ; -cby_2__1__mux_tree_tapbuf_size8_mem_5 mem_right_ipin_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ; -cby_2__1__mux_tree_tapbuf_size8_mem_6 mem_right_ipin_6 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_3_sram ) ) ; -cby_2__1__mux_tree_tapbuf_size8_mem mem_right_ipin_9 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_4_sram ) ) ; -cby_2__1__mux_tree_tapbuf_size8_mem_1 mem_right_ipin_10 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_5_sram ) ) ; -cby_2__1__mux_tree_tapbuf_size8_mem_2 mem_right_ipin_13 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_6_sram ) ) ; -cby_2__1__mux_tree_tapbuf_size8_mem_3 mem_right_ipin_14 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_7_sram ) ) ; -cby_2__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , - .io_outpad ( left_width_0_height_0__pin_0_ ) , - .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_8_ } ) , - .ccff_tail ( ccff_tail ) , .p_abuf0 ( ropt_net_114 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_bottom_in[0] ) , - .X ( ropt_net_115 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chany_bottom_in[1] ) , - .X ( chany_top_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_bottom_in[2] ) , - .X ( chany_top_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_bottom_in[3] ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chany_bottom_in[4] ) , - .X ( chany_top_out[4] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_108 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_bottom_in[6] ) , - .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_109 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chany_bottom_in[8] ) , - .X ( chany_top_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_691 ( .A ( ropt_net_114 ) , - .X ( left_width_0_height_0__pin_1_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_689 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_116 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__11 ( .A ( chany_bottom_in[11] ) , - .X ( aps_rename_3_ ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__12 ( .A ( chany_bottom_in[12] ) , - .X ( aps_rename_4_ ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chany_bottom_in[13] ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__14 ( .A ( chany_bottom_in[14] ) , - .X ( aps_rename_5_ ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__15 ( .A ( chany_bottom_in[15] ) , - .X ( aps_rename_6_ ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chany_bottom_in[16] ) , - .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_692 ( .A ( ropt_net_115 ) , - .X ( chany_top_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chany_bottom_in[18] ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_110 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chany_top_in[0] ) , - .X ( chany_bottom_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chany_top_in[1] ) , - .X ( chany_bottom_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chany_top_in[2] ) , - .X ( chany_bottom_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chany_top_in[3] ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_111 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chany_top_in[5] ) , - .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_690 ( - .A ( chany_bottom_in[17] ) , .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chany_top_in[7] ) , - .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_693 ( .A ( ropt_net_116 ) , - .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chany_top_in[9] ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_694 ( .A ( ropt_net_117 ) , - .X ( left_width_0_height_0__pin_1_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_32__31 ( .A ( chany_top_in[11] ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_36__35 ( .A ( chany_top_in[15] ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_37__36 ( .A ( chany_top_in[16] ) , - .X ( chany_bottom_out[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_39__38 ( .A ( chany_top_in[18] ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_41__40 ( .A ( aps_rename_8_ ) , - .X ( aps_rename_9_ ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_66 ( .A ( chany_bottom_in[5] ) , - .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_67 ( .A ( chany_bottom_in[7] ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_74 ( .A ( chany_top_in[8] ) , - .X ( chany_bottom_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_77 ( .A ( chany_top_in[17] ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_78 ( .A ( aps_rename_9_ ) , - .X ( ropt_net_117 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_82 ( .A ( chany_bottom_in[19] ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_83 ( .A ( chany_top_in[10] ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_85 ( .A ( aps_rename_3_ ) , - .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_86 ( .A ( aps_rename_4_ ) , - .X ( chany_top_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_87 ( .A ( aps_rename_5_ ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_88 ( .A ( aps_rename_6_ ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_90 ( .A ( chany_top_in[12] ) , - .X ( chany_bottom_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_94 ( .A ( chany_top_in[4] ) , - .X ( chany_bottom_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_95 ( .A ( chany_top_in[6] ) , - .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_96 ( .A ( chany_top_in[14] ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_97 ( .A ( chany_top_in[19] ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_98 ( .A ( chany_bottom_in[10] ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_99 ( .A ( chany_top_in[13] ) , - .X ( chany_bottom_out[13] ) ) ; -endmodule - - diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/cby_2__1__icv_in_design.lvs.v b/FPGA22_HIER_SKY_PNR/modules/verilog/cby_2__1__icv_in_design.lvs.v deleted file mode 100644 index 35666d3..0000000 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/cby_2__1__icv_in_design.lvs.v +++ /dev/null @@ -1,2470 +0,0 @@ -// -// -// -// -// -// -module cby_2__1__direct_interc ( in , out ) ; -input [0:0] in ; -output [0:0] out ; - -assign out[0] = in[0] ; -endmodule - - -module cby_2__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( prog_clk , - ccff_head , ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:0] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_20__60 ( .A ( mem_out[0] ) , - .X ( net_net_80 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_80 ( .A ( net_net_80 ) , - .X ( net_net_79 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_101 ( .A ( net_net_79 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_2__1__EMBEDDED_IO ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , - FPGA_OUT , FPGA_DIR , p_abuf0 , VDD , VSS ) ; -input SOC_IN ; -output SOC_OUT ; -output SOC_DIR ; -output FPGA_IN ; -input FPGA_OUT ; -input FPGA_DIR ; -output p_abuf0 ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -assign SOC_OUT = FPGA_OUT ; - -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__58 ( .A ( SOC_IN ) , .X ( FPGA_IN ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 FTB_19__59 ( .A ( FPGA_DIR ) , - .X ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_62 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_2__1__logical_tile_io_mode_physical__iopad ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , VDD , VSS , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] iopad_outpad ; -input [0:0] ccff_head ; -output [0:0] iopad_inpad ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; -output p_abuf0 ; - -wire [0:0] EMBEDDED_IO_0_en ; -supply1 VDD ; -supply0 VSS ; - -cby_2__1__EMBEDDED_IO EMBEDDED_IO_0_ ( - .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , - .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , - .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , - .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -cby_2__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -endmodule - - -module cby_2__1__logical_tile_io_mode_io_ ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , - ccff_tail , VDD , VSS , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] io_outpad ; -input [0:0] ccff_head ; -output [0:0] io_inpad ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; -output p_abuf0 ; - -supply1 VDD ; -supply0 VSS ; - -cby_2__1__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , - .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , - .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) ) ; -cby_2__1__direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( io_outpad ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__57 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__56 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__55 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__54 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__53 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__52 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__51 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__50 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_4 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__49 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__48 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__47 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__46 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__45 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__44 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__43 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__42 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__41 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cby_2__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , - chany_bottom_out , chany_top_out , right_grid_pin_0_ , left_grid_pin_16_ , - left_grid_pin_17_ , left_grid_pin_18_ , left_grid_pin_19_ , - left_grid_pin_20_ , left_grid_pin_21_ , left_grid_pin_22_ , - left_grid_pin_23_ , left_grid_pin_24_ , left_grid_pin_25_ , - left_grid_pin_26_ , left_grid_pin_27_ , left_grid_pin_28_ , - left_grid_pin_29_ , left_grid_pin_30_ , left_grid_pin_31_ , ccff_tail , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , left_width_0_height_0__pin_0_ , - left_width_0_height_0__pin_1_upper , left_width_0_height_0__pin_1_lower , - VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:19] chany_bottom_in ; -input [0:19] chany_top_in ; -input [0:0] ccff_head ; -output [0:19] chany_bottom_out ; -output [0:19] chany_top_out ; -output [0:0] right_grid_pin_0_ ; -output [0:0] left_grid_pin_16_ ; -output [0:0] left_grid_pin_17_ ; -output [0:0] left_grid_pin_18_ ; -output [0:0] left_grid_pin_19_ ; -output [0:0] left_grid_pin_20_ ; -output [0:0] left_grid_pin_21_ ; -output [0:0] left_grid_pin_22_ ; -output [0:0] left_grid_pin_23_ ; -output [0:0] left_grid_pin_24_ ; -output [0:0] left_grid_pin_25_ ; -output [0:0] left_grid_pin_26_ ; -output [0:0] left_grid_pin_27_ ; -output [0:0] left_grid_pin_28_ ; -output [0:0] left_grid_pin_29_ ; -output [0:0] left_grid_pin_30_ ; -output [0:0] left_grid_pin_31_ ; -output [0:0] ccff_tail ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] left_width_0_height_0__pin_0_ ; -output [0:0] left_width_0_height_0__pin_1_upper ; -output [0:0] left_width_0_height_0__pin_1_lower ; -input VDD ; -input VSS ; - -wire ropt_net_114 ; -wire [0:3] mux_left_ipin_0_undriven_sram_inv ; -wire [0:3] mux_right_ipin_0_undriven_sram_inv ; -wire [0:3] mux_right_ipin_10_undriven_sram_inv ; -wire [0:3] mux_right_ipin_11_undriven_sram_inv ; -wire [0:3] mux_right_ipin_12_undriven_sram_inv ; -wire [0:3] mux_right_ipin_13_undriven_sram_inv ; -wire [0:3] mux_right_ipin_14_undriven_sram_inv ; -wire [0:3] mux_right_ipin_15_undriven_sram_inv ; -wire [0:3] mux_right_ipin_1_undriven_sram_inv ; -wire [0:3] mux_right_ipin_2_undriven_sram_inv ; -wire [0:3] mux_right_ipin_3_undriven_sram_inv ; -wire [0:3] mux_right_ipin_4_undriven_sram_inv ; -wire [0:3] mux_right_ipin_5_undriven_sram_inv ; -wire [0:3] mux_right_ipin_6_undriven_sram_inv ; -wire [0:3] mux_right_ipin_7_undriven_sram_inv ; -wire [0:3] mux_right_ipin_8_undriven_sram_inv ; -wire [0:3] mux_right_ipin_9_undriven_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:3] mux_tree_tapbuf_size10_2_sram ; -wire [0:3] mux_tree_tapbuf_size10_3_sram ; -wire [0:3] mux_tree_tapbuf_size10_4_sram ; -wire [0:3] mux_tree_tapbuf_size10_5_sram ; -wire [0:3] mux_tree_tapbuf_size10_6_sram ; -wire [0:3] mux_tree_tapbuf_size10_7_sram ; -wire [0:3] mux_tree_tapbuf_size10_8_sram ; -wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:3] mux_tree_tapbuf_size8_2_sram ; -wire [0:3] mux_tree_tapbuf_size8_3_sram ; -wire [0:3] mux_tree_tapbuf_size8_4_sram ; -wire [0:3] mux_tree_tapbuf_size8_5_sram ; -wire [0:3] mux_tree_tapbuf_size8_6_sram ; -wire [0:3] mux_tree_tapbuf_size8_7_sram ; -wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ; -supply1 VDD ; -supply0 VSS ; -// - -cby_2__1__mux_tree_tapbuf_size10_0 mux_left_ipin_0 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , - chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , - chany_top_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_left_ipin_0_undriven_sram_inv ) , - .out ( right_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_111 ) ) ; -cby_2__1__mux_tree_tapbuf_size10_1 mux_right_ipin_0 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , - chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[17] , - chany_top_in[17] } ) , - .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_right_ipin_0_undriven_sram_inv ) , - .out ( left_grid_pin_16_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_110 ) ) ; -cby_2__1__mux_tree_tapbuf_size10_5 mux_right_ipin_3 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , - chany_bottom_in[8] , chany_top_in[8] , chany_bottom_in[14] , - chany_top_in[14] } ) , - .sram ( mux_tree_tapbuf_size10_2_sram ) , - .sram_inv ( mux_right_ipin_3_undriven_sram_inv ) , - .out ( left_grid_pin_19_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_109 ) ) ; -cby_2__1__mux_tree_tapbuf_size10_6 mux_right_ipin_4 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , - chany_bottom_in[9] , chany_top_in[9] , chany_bottom_in[15] , - chany_top_in[15] } ) , - .sram ( mux_tree_tapbuf_size10_3_sram ) , - .sram_inv ( mux_right_ipin_4_undriven_sram_inv ) , - .out ( left_grid_pin_20_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_108 ) ) ; -cby_2__1__mux_tree_tapbuf_size10_7 mux_right_ipin_7 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[8] , chany_top_in[8] , - chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[18] , - chany_top_in[18] } ) , - .sram ( mux_tree_tapbuf_size10_4_sram ) , - .sram_inv ( mux_right_ipin_7_undriven_sram_inv ) , - .out ( left_grid_pin_23_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_109 ) ) ; -cby_2__1__mux_tree_tapbuf_size10 mux_right_ipin_8 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , - chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[19] , - chany_top_in[19] } ) , - .sram ( mux_tree_tapbuf_size10_5_sram ) , - .sram_inv ( mux_right_ipin_8_undriven_sram_inv ) , - .out ( left_grid_pin_24_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_108 ) ) ; -cby_2__1__mux_tree_tapbuf_size10_2 mux_right_ipin_11 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , - chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[16] , - chany_top_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_6_sram ) , - .sram_inv ( mux_right_ipin_11_undriven_sram_inv ) , - .out ( left_grid_pin_27_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_109 ) ) ; -cby_2__1__mux_tree_tapbuf_size10_3 mux_right_ipin_12 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , - chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[17] , - chany_top_in[17] } ) , - .sram ( mux_tree_tapbuf_size10_7_sram ) , - .sram_inv ( mux_right_ipin_12_undriven_sram_inv ) , - .out ( left_grid_pin_28_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_108 ) ) ; -cby_2__1__mux_tree_tapbuf_size10_4 mux_right_ipin_15 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , - chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , - chany_top_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_8_sram ) , - .sram_inv ( mux_right_ipin_15_undriven_sram_inv ) , - .out ( left_grid_pin_31_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_111 ) ) ; -cby_2__1__mux_tree_tapbuf_size10_mem_0 mem_left_ipin_0 ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cby_2__1__mux_tree_tapbuf_size10_mem_1 mem_right_ipin_0 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cby_2__1__mux_tree_tapbuf_size10_mem_5 mem_right_ipin_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cby_2__1__mux_tree_tapbuf_size10_mem_6 mem_right_ipin_4 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cby_2__1__mux_tree_tapbuf_size10_mem_7 mem_right_ipin_7 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cby_2__1__mux_tree_tapbuf_size10_mem mem_right_ipin_8 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cby_2__1__mux_tree_tapbuf_size10_mem_2 mem_right_ipin_11 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cby_2__1__mux_tree_tapbuf_size10_mem_3 mem_right_ipin_12 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cby_2__1__mux_tree_tapbuf_size10_mem_4 mem_right_ipin_15 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , - .mem_out ( mux_tree_tapbuf_size10_8_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cby_2__1__mux_tree_tapbuf_size8_0 mux_right_ipin_1 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , - chany_bottom_in[14] , chany_top_in[14] } ) , - .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_right_ipin_1_undriven_sram_inv ) , - .out ( left_grid_pin_17_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_111 ) ) ; -cby_2__1__mux_tree_tapbuf_size8_4 mux_right_ipin_2 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , - chany_bottom_in[15] , chany_top_in[15] } ) , - .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_right_ipin_2_undriven_sram_inv ) , - .out ( left_grid_pin_18_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_108 ) ) ; -cby_2__1__mux_tree_tapbuf_size8_5 mux_right_ipin_5 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , - chany_bottom_in[18] , chany_top_in[18] } ) , - .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_right_ipin_5_undriven_sram_inv ) , - .out ( left_grid_pin_21_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_111 ) ) ; -cby_2__1__mux_tree_tapbuf_size8_6 mux_right_ipin_6 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[11] , chany_top_in[11] , - chany_bottom_in[19] , chany_top_in[19] } ) , - .sram ( mux_tree_tapbuf_size8_3_sram ) , - .sram_inv ( mux_right_ipin_6_undriven_sram_inv ) , - .out ( left_grid_pin_22_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_110 ) ) ; -cby_2__1__mux_tree_tapbuf_size8 mux_right_ipin_9 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , - chany_bottom_in[14] , chany_top_in[14] } ) , - .sram ( mux_tree_tapbuf_size8_4_sram ) , - .sram_inv ( mux_right_ipin_9_undriven_sram_inv ) , - .out ( left_grid_pin_25_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_111 ) ) ; -cby_2__1__mux_tree_tapbuf_size8_1 mux_right_ipin_10 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , - chany_bottom_in[15] , chany_top_in[15] } ) , - .sram ( mux_tree_tapbuf_size8_5_sram ) , - .sram_inv ( mux_right_ipin_10_undriven_sram_inv ) , - .out ( left_grid_pin_26_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_108 ) ) ; -cby_2__1__mux_tree_tapbuf_size8_2 mux_right_ipin_13 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , - chany_bottom_in[18] , chany_top_in[18] } ) , - .sram ( mux_tree_tapbuf_size8_6_sram ) , - .sram_inv ( mux_right_ipin_13_undriven_sram_inv ) , - .out ( left_grid_pin_29_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_111 ) ) ; -cby_2__1__mux_tree_tapbuf_size8_3 mux_right_ipin_14 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[11] , chany_top_in[11] , - chany_bottom_in[19] , chany_top_in[19] } ) , - .sram ( mux_tree_tapbuf_size8_7_sram ) , - .sram_inv ( mux_right_ipin_14_undriven_sram_inv ) , - .out ( left_grid_pin_30_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_110 ) ) ; -cby_2__1__mux_tree_tapbuf_size8_mem_0 mem_right_ipin_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cby_2__1__mux_tree_tapbuf_size8_mem_4 mem_right_ipin_2 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cby_2__1__mux_tree_tapbuf_size8_mem_5 mem_right_ipin_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cby_2__1__mux_tree_tapbuf_size8_mem_6 mem_right_ipin_6 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cby_2__1__mux_tree_tapbuf_size8_mem mem_right_ipin_9 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cby_2__1__mux_tree_tapbuf_size8_mem_1 mem_right_ipin_10 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cby_2__1__mux_tree_tapbuf_size8_mem_2 mem_right_ipin_13 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cby_2__1__mux_tree_tapbuf_size8_mem_3 mem_right_ipin_14 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cby_2__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , - .io_outpad ( left_width_0_height_0__pin_0_ ) , - .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_8_ } ) , - .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf0 ( ropt_net_114 ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1668 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1669 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1670 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1671 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1672 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1673 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1674 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1675 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1676 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1677 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1678 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1679 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1680 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1681 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1682 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_bottom_in[0] ) , - .X ( ropt_net_115 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chany_bottom_in[1] ) , - .X ( chany_top_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_bottom_in[2] ) , - .X ( chany_top_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_bottom_in[3] ) , - .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chany_bottom_in[4] ) , - .X ( chany_top_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_bottom_in[6] ) , - .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chany_bottom_in[8] ) , - .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_691 ( .A ( ropt_net_114 ) , - .X ( left_width_0_height_0__pin_1_upper[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_689 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_116 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__11 ( .A ( chany_bottom_in[11] ) , - .X ( aps_rename_3_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__12 ( .A ( chany_bottom_in[12] ) , - .X ( aps_rename_4_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chany_bottom_in[13] ) , - .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__14 ( .A ( chany_bottom_in[14] ) , - .X ( aps_rename_5_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__15 ( .A ( chany_bottom_in[15] ) , - .X ( aps_rename_6_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chany_bottom_in[16] ) , - .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_692 ( .A ( ropt_net_115 ) , - .X ( chany_top_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chany_bottom_in[18] ) , - .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chany_top_in[0] ) , - .X ( chany_bottom_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chany_top_in[1] ) , - .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chany_top_in[2] ) , - .X ( chany_bottom_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chany_top_in[3] ) , - .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chany_top_in[5] ) , - .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_690 ( - .A ( chany_bottom_in[17] ) , .X ( chany_top_out[17] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chany_top_in[7] ) , - .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_693 ( .A ( ropt_net_116 ) , - .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chany_top_in[9] ) , - .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_694 ( .A ( ropt_net_117 ) , - .X ( left_width_0_height_0__pin_1_lower[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_32__31 ( .A ( chany_top_in[11] ) , - .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_36__35 ( .A ( chany_top_in[15] ) , - .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_37__36 ( .A ( chany_top_in[16] ) , - .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_39__38 ( .A ( chany_top_in[18] ) , - .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_41__40 ( .A ( aps_rename_8_ ) , - .X ( aps_rename_9_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_66 ( .A ( chany_bottom_in[5] ) , - .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_67 ( .A ( chany_bottom_in[7] ) , - .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_74 ( .A ( chany_top_in[8] ) , - .X ( chany_bottom_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_77 ( .A ( chany_top_in[17] ) , - .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_78 ( .A ( aps_rename_9_ ) , - .X ( ropt_net_117 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_82 ( .A ( chany_bottom_in[19] ) , - .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_83 ( .A ( chany_top_in[10] ) , - .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_85 ( .A ( aps_rename_3_ ) , - .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_86 ( .A ( aps_rename_4_ ) , - .X ( chany_top_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_87 ( .A ( aps_rename_5_ ) , - .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_88 ( .A ( aps_rename_6_ ) , - .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_90 ( .A ( chany_top_in[12] ) , - .X ( chany_bottom_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_94 ( .A ( chany_top_in[4] ) , - .X ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_95 ( .A ( chany_top_in[6] ) , - .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_96 ( .A ( chany_top_in[14] ) , - .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_97 ( .A ( chany_top_in[19] ) , - .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_98 ( .A ( chany_bottom_in[10] ) , - .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_99 ( .A ( chany_top_in[13] ) , - .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y0 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y0 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x36800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x552000y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x515200y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x593400y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x55200y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x101200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x119600y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x59800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x110400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x381800y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x469200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x289800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x354200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x519800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x529000y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x151800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x243800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x446200y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x506000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x515200y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x156400y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x391000y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x36800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x138000y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x547400y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x593400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x161000y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x326600y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x188600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x207000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x432400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x510600y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x556600y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x588800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x36800y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x271400y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x506000y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x55200y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x87400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x174800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x308200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x326600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x335800y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x391000y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x547400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x556600y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x184000y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x345000y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x400200y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x55200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x64400y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x110400y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x142600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x151800y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x197800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x207000y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x542800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x142600y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x285200y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x556600y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/cby_2__1__icv_in_design.pt.v b/FPGA22_HIER_SKY_PNR/modules/verilog/cby_2__1__icv_in_design.pt.v deleted file mode 100644 index 6e25fde..0000000 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/cby_2__1__icv_in_design.pt.v +++ /dev/null @@ -1,1689 +0,0 @@ -// -// -// -// -// -// -module cby_2__1__direct_interc ( in , out ) ; -input [0:0] in ; -output [0:0] out ; - -assign out[0] = in[0] ; -endmodule - - -module cby_2__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( prog_clk , - ccff_head , ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:0] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_20__60 ( .A ( mem_out[0] ) , - .X ( net_net_80 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_80 ( .A ( net_net_80 ) , - .X ( net_net_79 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_101 ( .A ( net_net_79 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_2__1__EMBEDDED_IO ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , - FPGA_OUT , FPGA_DIR , p_abuf0 ) ; -input SOC_IN ; -output SOC_OUT ; -output SOC_DIR ; -output FPGA_IN ; -input FPGA_OUT ; -input FPGA_DIR ; -output p_abuf0 ; - -assign SOC_OUT = FPGA_OUT ; - -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__58 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 FTB_19__59 ( .A ( FPGA_DIR ) , - .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_62 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; -endmodule - - -module cby_2__1__logical_tile_io_mode_physical__iopad ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] iopad_outpad ; -input [0:0] ccff_head ; -output [0:0] iopad_inpad ; -output [0:0] ccff_tail ; -output p_abuf0 ; - -wire [0:0] EMBEDDED_IO_0_en ; - -cby_2__1__EMBEDDED_IO EMBEDDED_IO_0_ ( - .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , - .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , - .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , - .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; -cby_2__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxtp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) ) ; -endmodule - - -module cby_2__1__logical_tile_io_mode_io_ ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , - ccff_tail , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] io_outpad ; -input [0:0] ccff_head ; -output [0:0] io_inpad ; -output [0:0] ccff_tail ; -output p_abuf0 ; - -cby_2__1__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , - .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , - .p_abuf0 ( p_abuf0 ) ) ; -cby_2__1__direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( io_outpad ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__57 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__56 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__55 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__54 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__53 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__52 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__51 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__50 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_4 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__49 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__48 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__47 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__46 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__45 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__44 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__43 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__42 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__41 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cby_2__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module cby_2__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , - chany_bottom_out , chany_top_out , right_grid_pin_0_ , left_grid_pin_16_ , - left_grid_pin_17_ , left_grid_pin_18_ , left_grid_pin_19_ , - left_grid_pin_20_ , left_grid_pin_21_ , left_grid_pin_22_ , - left_grid_pin_23_ , left_grid_pin_24_ , left_grid_pin_25_ , - left_grid_pin_26_ , left_grid_pin_27_ , left_grid_pin_28_ , - left_grid_pin_29_ , left_grid_pin_30_ , left_grid_pin_31_ , ccff_tail , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , left_width_0_height_0__pin_0_ , - left_width_0_height_0__pin_1_upper , left_width_0_height_0__pin_1_lower ) ; -input [0:0] prog_clk ; -input [0:19] chany_bottom_in ; -input [0:19] chany_top_in ; -input [0:0] ccff_head ; -output [0:19] chany_bottom_out ; -output [0:19] chany_top_out ; -output [0:0] right_grid_pin_0_ ; -output [0:0] left_grid_pin_16_ ; -output [0:0] left_grid_pin_17_ ; -output [0:0] left_grid_pin_18_ ; -output [0:0] left_grid_pin_19_ ; -output [0:0] left_grid_pin_20_ ; -output [0:0] left_grid_pin_21_ ; -output [0:0] left_grid_pin_22_ ; -output [0:0] left_grid_pin_23_ ; -output [0:0] left_grid_pin_24_ ; -output [0:0] left_grid_pin_25_ ; -output [0:0] left_grid_pin_26_ ; -output [0:0] left_grid_pin_27_ ; -output [0:0] left_grid_pin_28_ ; -output [0:0] left_grid_pin_29_ ; -output [0:0] left_grid_pin_30_ ; -output [0:0] left_grid_pin_31_ ; -output [0:0] ccff_tail ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] left_width_0_height_0__pin_0_ ; -output [0:0] left_width_0_height_0__pin_1_upper ; -output [0:0] left_width_0_height_0__pin_1_lower ; - -wire ropt_net_114 ; -wire [0:3] mux_left_ipin_0_undriven_sram_inv ; -wire [0:3] mux_right_ipin_0_undriven_sram_inv ; -wire [0:3] mux_right_ipin_10_undriven_sram_inv ; -wire [0:3] mux_right_ipin_11_undriven_sram_inv ; -wire [0:3] mux_right_ipin_12_undriven_sram_inv ; -wire [0:3] mux_right_ipin_13_undriven_sram_inv ; -wire [0:3] mux_right_ipin_14_undriven_sram_inv ; -wire [0:3] mux_right_ipin_15_undriven_sram_inv ; -wire [0:3] mux_right_ipin_1_undriven_sram_inv ; -wire [0:3] mux_right_ipin_2_undriven_sram_inv ; -wire [0:3] mux_right_ipin_3_undriven_sram_inv ; -wire [0:3] mux_right_ipin_4_undriven_sram_inv ; -wire [0:3] mux_right_ipin_5_undriven_sram_inv ; -wire [0:3] mux_right_ipin_6_undriven_sram_inv ; -wire [0:3] mux_right_ipin_7_undriven_sram_inv ; -wire [0:3] mux_right_ipin_8_undriven_sram_inv ; -wire [0:3] mux_right_ipin_9_undriven_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:3] mux_tree_tapbuf_size10_2_sram ; -wire [0:3] mux_tree_tapbuf_size10_3_sram ; -wire [0:3] mux_tree_tapbuf_size10_4_sram ; -wire [0:3] mux_tree_tapbuf_size10_5_sram ; -wire [0:3] mux_tree_tapbuf_size10_6_sram ; -wire [0:3] mux_tree_tapbuf_size10_7_sram ; -wire [0:3] mux_tree_tapbuf_size10_8_sram ; -wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:3] mux_tree_tapbuf_size8_2_sram ; -wire [0:3] mux_tree_tapbuf_size8_3_sram ; -wire [0:3] mux_tree_tapbuf_size8_4_sram ; -wire [0:3] mux_tree_tapbuf_size8_5_sram ; -wire [0:3] mux_tree_tapbuf_size8_6_sram ; -wire [0:3] mux_tree_tapbuf_size8_7_sram ; -wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ; -// - -cby_2__1__mux_tree_tapbuf_size10_0 mux_left_ipin_0 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , - chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , - chany_top_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_left_ipin_0_undriven_sram_inv ) , - .out ( right_grid_pin_0_ ) , .p0 ( optlc_net_111 ) ) ; -cby_2__1__mux_tree_tapbuf_size10_1 mux_right_ipin_0 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , - chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[17] , - chany_top_in[17] } ) , - .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_right_ipin_0_undriven_sram_inv ) , - .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_110 ) ) ; -cby_2__1__mux_tree_tapbuf_size10_5 mux_right_ipin_3 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , - chany_bottom_in[8] , chany_top_in[8] , chany_bottom_in[14] , - chany_top_in[14] } ) , - .sram ( mux_tree_tapbuf_size10_2_sram ) , - .sram_inv ( mux_right_ipin_3_undriven_sram_inv ) , - .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_109 ) ) ; -cby_2__1__mux_tree_tapbuf_size10_6 mux_right_ipin_4 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , - chany_bottom_in[9] , chany_top_in[9] , chany_bottom_in[15] , - chany_top_in[15] } ) , - .sram ( mux_tree_tapbuf_size10_3_sram ) , - .sram_inv ( mux_right_ipin_4_undriven_sram_inv ) , - .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_108 ) ) ; -cby_2__1__mux_tree_tapbuf_size10_7 mux_right_ipin_7 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[8] , chany_top_in[8] , - chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[18] , - chany_top_in[18] } ) , - .sram ( mux_tree_tapbuf_size10_4_sram ) , - .sram_inv ( mux_right_ipin_7_undriven_sram_inv ) , - .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_109 ) ) ; -cby_2__1__mux_tree_tapbuf_size10 mux_right_ipin_8 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , - chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[19] , - chany_top_in[19] } ) , - .sram ( mux_tree_tapbuf_size10_5_sram ) , - .sram_inv ( mux_right_ipin_8_undriven_sram_inv ) , - .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_108 ) ) ; -cby_2__1__mux_tree_tapbuf_size10_2 mux_right_ipin_11 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , - chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[16] , - chany_top_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_6_sram ) , - .sram_inv ( mux_right_ipin_11_undriven_sram_inv ) , - .out ( left_grid_pin_27_ ) , .p0 ( optlc_net_109 ) ) ; -cby_2__1__mux_tree_tapbuf_size10_3 mux_right_ipin_12 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , - chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[17] , - chany_top_in[17] } ) , - .sram ( mux_tree_tapbuf_size10_7_sram ) , - .sram_inv ( mux_right_ipin_12_undriven_sram_inv ) , - .out ( left_grid_pin_28_ ) , .p0 ( optlc_net_108 ) ) ; -cby_2__1__mux_tree_tapbuf_size10_4 mux_right_ipin_15 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , - chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , - chany_top_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_8_sram ) , - .sram_inv ( mux_right_ipin_15_undriven_sram_inv ) , - .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_111 ) ) ; -cby_2__1__mux_tree_tapbuf_size10_mem_0 mem_left_ipin_0 ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; -cby_2__1__mux_tree_tapbuf_size10_mem_1 mem_right_ipin_0 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ; -cby_2__1__mux_tree_tapbuf_size10_mem_5 mem_right_ipin_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ; -cby_2__1__mux_tree_tapbuf_size10_mem_6 mem_right_ipin_4 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ; -cby_2__1__mux_tree_tapbuf_size10_mem_7 mem_right_ipin_7 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ; -cby_2__1__mux_tree_tapbuf_size10_mem mem_right_ipin_8 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ; -cby_2__1__mux_tree_tapbuf_size10_mem_2 mem_right_ipin_11 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ; -cby_2__1__mux_tree_tapbuf_size10_mem_3 mem_right_ipin_12 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ; -cby_2__1__mux_tree_tapbuf_size10_mem_4 mem_right_ipin_15 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , - .mem_out ( mux_tree_tapbuf_size10_8_sram ) ) ; -cby_2__1__mux_tree_tapbuf_size8_0 mux_right_ipin_1 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , - chany_bottom_in[14] , chany_top_in[14] } ) , - .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_right_ipin_1_undriven_sram_inv ) , - .out ( left_grid_pin_17_ ) , .p0 ( optlc_net_111 ) ) ; -cby_2__1__mux_tree_tapbuf_size8_4 mux_right_ipin_2 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , - chany_bottom_in[15] , chany_top_in[15] } ) , - .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_right_ipin_2_undriven_sram_inv ) , - .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_108 ) ) ; -cby_2__1__mux_tree_tapbuf_size8_5 mux_right_ipin_5 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , - chany_bottom_in[18] , chany_top_in[18] } ) , - .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_right_ipin_5_undriven_sram_inv ) , - .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_111 ) ) ; -cby_2__1__mux_tree_tapbuf_size8_6 mux_right_ipin_6 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[11] , chany_top_in[11] , - chany_bottom_in[19] , chany_top_in[19] } ) , - .sram ( mux_tree_tapbuf_size8_3_sram ) , - .sram_inv ( mux_right_ipin_6_undriven_sram_inv ) , - .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_110 ) ) ; -cby_2__1__mux_tree_tapbuf_size8 mux_right_ipin_9 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , - chany_bottom_in[14] , chany_top_in[14] } ) , - .sram ( mux_tree_tapbuf_size8_4_sram ) , - .sram_inv ( mux_right_ipin_9_undriven_sram_inv ) , - .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_111 ) ) ; -cby_2__1__mux_tree_tapbuf_size8_1 mux_right_ipin_10 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , - chany_bottom_in[15] , chany_top_in[15] } ) , - .sram ( mux_tree_tapbuf_size8_5_sram ) , - .sram_inv ( mux_right_ipin_10_undriven_sram_inv ) , - .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_108 ) ) ; -cby_2__1__mux_tree_tapbuf_size8_2 mux_right_ipin_13 ( - .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , - chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , - chany_bottom_in[18] , chany_top_in[18] } ) , - .sram ( mux_tree_tapbuf_size8_6_sram ) , - .sram_inv ( mux_right_ipin_13_undriven_sram_inv ) , - .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_111 ) ) ; -cby_2__1__mux_tree_tapbuf_size8_3 mux_right_ipin_14 ( - .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , - chany_top_in[3] , chany_bottom_in[11] , chany_top_in[11] , - chany_bottom_in[19] , chany_top_in[19] } ) , - .sram ( mux_tree_tapbuf_size8_7_sram ) , - .sram_inv ( mux_right_ipin_14_undriven_sram_inv ) , - .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_110 ) ) ; -cby_2__1__mux_tree_tapbuf_size8_mem_0 mem_right_ipin_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ; -cby_2__1__mux_tree_tapbuf_size8_mem_4 mem_right_ipin_2 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ; -cby_2__1__mux_tree_tapbuf_size8_mem_5 mem_right_ipin_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ; -cby_2__1__mux_tree_tapbuf_size8_mem_6 mem_right_ipin_6 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_3_sram ) ) ; -cby_2__1__mux_tree_tapbuf_size8_mem mem_right_ipin_9 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_4_sram ) ) ; -cby_2__1__mux_tree_tapbuf_size8_mem_1 mem_right_ipin_10 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_5_sram ) ) ; -cby_2__1__mux_tree_tapbuf_size8_mem_2 mem_right_ipin_13 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_6_sram ) ) ; -cby_2__1__mux_tree_tapbuf_size8_mem_3 mem_right_ipin_14 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_7_sram ) ) ; -cby_2__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , - .io_outpad ( left_width_0_height_0__pin_0_ ) , - .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_8_ } ) , - .ccff_tail ( ccff_tail ) , .p_abuf0 ( ropt_net_114 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_bottom_in[0] ) , - .X ( ropt_net_115 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chany_bottom_in[1] ) , - .X ( chany_top_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_bottom_in[2] ) , - .X ( chany_top_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_bottom_in[3] ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chany_bottom_in[4] ) , - .X ( chany_top_out[4] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_108 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_bottom_in[6] ) , - .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_109 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chany_bottom_in[8] ) , - .X ( chany_top_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_691 ( .A ( ropt_net_114 ) , - .X ( left_width_0_height_0__pin_1_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_689 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_116 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__11 ( .A ( chany_bottom_in[11] ) , - .X ( aps_rename_3_ ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__12 ( .A ( chany_bottom_in[12] ) , - .X ( aps_rename_4_ ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chany_bottom_in[13] ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__14 ( .A ( chany_bottom_in[14] ) , - .X ( aps_rename_5_ ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__15 ( .A ( chany_bottom_in[15] ) , - .X ( aps_rename_6_ ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chany_bottom_in[16] ) , - .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_692 ( .A ( ropt_net_115 ) , - .X ( chany_top_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chany_bottom_in[18] ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_110 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chany_top_in[0] ) , - .X ( chany_bottom_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chany_top_in[1] ) , - .X ( chany_bottom_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chany_top_in[2] ) , - .X ( chany_bottom_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chany_top_in[3] ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_111 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chany_top_in[5] ) , - .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_690 ( - .A ( chany_bottom_in[17] ) , .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chany_top_in[7] ) , - .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_693 ( .A ( ropt_net_116 ) , - .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chany_top_in[9] ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_694 ( .A ( ropt_net_117 ) , - .X ( left_width_0_height_0__pin_1_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_32__31 ( .A ( chany_top_in[11] ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_36__35 ( .A ( chany_top_in[15] ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_37__36 ( .A ( chany_top_in[16] ) , - .X ( chany_bottom_out[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_39__38 ( .A ( chany_top_in[18] ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_41__40 ( .A ( aps_rename_8_ ) , - .X ( aps_rename_9_ ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_66 ( .A ( chany_bottom_in[5] ) , - .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_67 ( .A ( chany_bottom_in[7] ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_74 ( .A ( chany_top_in[8] ) , - .X ( chany_bottom_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_77 ( .A ( chany_top_in[17] ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_78 ( .A ( aps_rename_9_ ) , - .X ( ropt_net_117 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_82 ( .A ( chany_bottom_in[19] ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_83 ( .A ( chany_top_in[10] ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_85 ( .A ( aps_rename_3_ ) , - .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_86 ( .A ( aps_rename_4_ ) , - .X ( chany_top_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_87 ( .A ( aps_rename_5_ ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_88 ( .A ( aps_rename_6_ ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_90 ( .A ( chany_top_in[12] ) , - .X ( chany_bottom_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_94 ( .A ( chany_top_in[4] ) , - .X ( chany_bottom_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_95 ( .A ( chany_top_in[6] ) , - .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_96 ( .A ( chany_top_in[14] ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_97 ( .A ( chany_top_in[19] ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_98 ( .A ( chany_bottom_in[10] ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_99 ( .A ( chany_top_in[13] ) , - .X ( chany_bottom_out[13] ) ) ; -endmodule - - diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__0__icv_in_design.fm.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__0__icv_in_design.fm.v deleted file mode 100644 index 5df43c6..0000000 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__0__icv_in_design.fm.v +++ /dev/null @@ -1,1268 +0,0 @@ -// -// -// -// -// -// -module sb_0__0__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__39 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__38 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__37 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__36 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__0__const1 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sb_0__0__const1 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -endmodule - - -module sb_0__0__const1_18 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sb_0__0__const1_18 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -endmodule - - -module sb_0__0__const1_17 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sb_0__0__const1_17 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -endmodule - - -module sb_0__0__const1_16 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sb_0__0__const1_16 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__35 ( .A ( mem_out[1] ) , - .X ( net_aps_35 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_62 ( .A ( net_aps_35 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__34 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__33 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__32 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__31 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__30 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__29 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__28 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__27 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__26 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__25 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__24 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__23 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__22 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__21 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__20 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__0__const1_15 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_0__0__const1_15 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__0__const1_14 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_0__0__const1_14 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__0__const1_13 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_0__0__const1_13 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__0__const1_12 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -sb_0__0__const1_12 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_0__0__const1_11 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_0__0__const1_11 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__0__const1_10 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_0__0__const1_10 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__0__const1_9 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_0__0__const1_9 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__0__const1_8 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_0__0__const1_8 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__0__const1_7 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_0__0__const1_7 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__0__const1_6 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_0__0__const1_6 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_41 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_0__0__const1_5 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_0__0__const1_5 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__0__const1_4 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_0__0__const1_4 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_40 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_0__0__const1_3 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_0__0__const1_3 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__0__const1_2 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_0__0__const1_2 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__0__const1_1 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_0__0__const1_1 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__0__const1_0 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_0__0__const1_0 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__0_ ( prog_clk , chany_top_in , top_left_grid_pin_1_ , - chanx_right_in , right_bottom_grid_pin_1_ , right_bottom_grid_pin_3_ , - right_bottom_grid_pin_5_ , right_bottom_grid_pin_7_ , - right_bottom_grid_pin_9_ , right_bottom_grid_pin_11_ , ccff_head , - chany_top_out , chanx_right_out , ccff_tail ) ; -input [0:0] prog_clk ; -input [0:19] chany_top_in ; -input [0:0] top_left_grid_pin_1_ ; -input [0:19] chanx_right_in ; -input [0:0] right_bottom_grid_pin_1_ ; -input [0:0] right_bottom_grid_pin_3_ ; -input [0:0] right_bottom_grid_pin_5_ ; -input [0:0] right_bottom_grid_pin_7_ ; -input [0:0] right_bottom_grid_pin_9_ ; -input [0:0] right_bottom_grid_pin_11_ ; -input [0:0] ccff_head ; -output [0:19] chany_top_out ; -output [0:19] chanx_right_out ; -output [0:0] ccff_tail ; - -wire [0:2] mux_right_track_0_undriven_sram_inv ; -wire [0:1] mux_right_track_10_undriven_sram_inv ; -wire [0:1] mux_right_track_12_undriven_sram_inv ; -wire [0:1] mux_right_track_14_undriven_sram_inv ; -wire [0:1] mux_right_track_16_undriven_sram_inv ; -wire [0:1] mux_right_track_18_undriven_sram_inv ; -wire [0:1] mux_right_track_24_undriven_sram_inv ; -wire [0:1] mux_right_track_26_undriven_sram_inv ; -wire [0:1] mux_right_track_28_undriven_sram_inv ; -wire [0:2] mux_right_track_2_undriven_sram_inv ; -wire [0:1] mux_right_track_30_undriven_sram_inv ; -wire [0:1] mux_right_track_32_undriven_sram_inv ; -wire [0:1] mux_right_track_34_undriven_sram_inv ; -wire [0:2] mux_right_track_4_undriven_sram_inv ; -wire [0:2] mux_right_track_6_undriven_sram_inv ; -wire [0:1] mux_right_track_8_undriven_sram_inv ; -wire [0:1] mux_top_track_0_undriven_sram_inv ; -wire [0:1] mux_top_track_24_undriven_sram_inv ; -wire [0:1] mux_top_track_4_undriven_sram_inv ; -wire [0:1] mux_top_track_8_undriven_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_10_sram ; -wire [0:1] mux_tree_tapbuf_size2_11_sram ; -wire [0:1] mux_tree_tapbuf_size2_12_sram ; -wire [0:1] mux_tree_tapbuf_size2_13_sram ; -wire [0:1] mux_tree_tapbuf_size2_14_sram ; -wire [0:1] mux_tree_tapbuf_size2_15_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_5_sram ; -wire [0:1] mux_tree_tapbuf_size2_6_sram ; -wire [0:1] mux_tree_tapbuf_size2_7_sram ; -wire [0:1] mux_tree_tapbuf_size2_8_sram ; -wire [0:1] mux_tree_tapbuf_size2_9_sram ; -wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size4_0_sram ; -wire [0:2] mux_tree_tapbuf_size4_1_sram ; -wire [0:2] mux_tree_tapbuf_size4_2_sram ; -wire [0:2] mux_tree_tapbuf_size4_3_sram ; -wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; -// - -sb_0__0__mux_tree_tapbuf_size2_12 mux_top_track_0 ( - .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] } ) , - .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_top_track_0_undriven_sram_inv ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_80 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_14 mux_top_track_4 ( - .in ( { top_left_grid_pin_1_[0] , chanx_right_in[3] } ) , - .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_top_track_4_undriven_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_80 ) ) ; -sb_0__0__mux_tree_tapbuf_size2 mux_top_track_8 ( - .in ( { top_left_grid_pin_1_[0] , chanx_right_in[5] } ) , - .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_top_track_8_undriven_sram_inv ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_80 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_13 mux_top_track_24 ( - .in ( { top_left_grid_pin_1_[0] , chanx_right_in[13] } ) , - .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_top_track_24_undriven_sram_inv ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_81 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_11 mux_right_track_8 ( - .in ( { chany_top_in[3] , right_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_right_track_8_undriven_sram_inv ) , - .out ( { ropt_net_83 } ) , - .p0 ( optlc_net_81 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_0 mux_right_track_10 ( - .in ( { chany_top_in[4] , right_bottom_grid_pin_3_[0] } ) , - .sram ( mux_tree_tapbuf_size2_5_sram ) , - .sram_inv ( mux_right_track_10_undriven_sram_inv ) , - .out ( chanx_right_out[5] ) , .p0 ( optlc_net_81 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_1 mux_right_track_12 ( - .in ( { chany_top_in[5] , right_bottom_grid_pin_5_[0] } ) , - .sram ( mux_tree_tapbuf_size2_6_sram ) , - .sram_inv ( mux_right_track_12_undriven_sram_inv ) , - .out ( { ropt_net_84 } ) , - .p0 ( optlc_net_78 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_2 mux_right_track_14 ( - .in ( { chany_top_in[6] , right_bottom_grid_pin_7_[0] } ) , - .sram ( mux_tree_tapbuf_size2_7_sram ) , - .sram_inv ( mux_right_track_14_undriven_sram_inv ) , - .out ( chanx_right_out[7] ) , .p0 ( optlc_net_78 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_3 mux_right_track_16 ( - .in ( { chany_top_in[7] , right_bottom_grid_pin_9_[0] } ) , - .sram ( mux_tree_tapbuf_size2_8_sram ) , - .sram_inv ( mux_right_track_16_undriven_sram_inv ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_78 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_4 mux_right_track_18 ( - .in ( { chany_top_in[8] , right_bottom_grid_pin_11_[0] } ) , - .sram ( mux_tree_tapbuf_size2_9_sram ) , - .sram_inv ( mux_right_track_18_undriven_sram_inv ) , - .out ( chanx_right_out[9] ) , .p0 ( optlc_net_81 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_5 mux_right_track_24 ( - .in ( { chany_top_in[11] , right_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size2_10_sram ) , - .sram_inv ( mux_right_track_24_undriven_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_79 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_6 mux_right_track_26 ( - .in ( { chany_top_in[12] , right_bottom_grid_pin_3_[0] } ) , - .sram ( mux_tree_tapbuf_size2_11_sram ) , - .sram_inv ( mux_right_track_26_undriven_sram_inv ) , - .out ( chanx_right_out[13] ) , .p0 ( optlc_net_79 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_7 mux_right_track_28 ( - .in ( { chany_top_in[13] , right_bottom_grid_pin_5_[0] } ) , - .sram ( mux_tree_tapbuf_size2_12_sram ) , - .sram_inv ( mux_right_track_28_undriven_sram_inv ) , - .out ( chanx_right_out[14] ) , .p0 ( optlc_net_79 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_8 mux_right_track_30 ( - .in ( { chany_top_in[14] , right_bottom_grid_pin_7_[0] } ) , - .sram ( mux_tree_tapbuf_size2_13_sram ) , - .sram_inv ( mux_right_track_30_undriven_sram_inv ) , - .out ( chanx_right_out[15] ) , .p0 ( optlc_net_78 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_9 mux_right_track_32 ( - .in ( { chany_top_in[15] , right_bottom_grid_pin_9_[0] } ) , - .sram ( mux_tree_tapbuf_size2_14_sram ) , - .sram_inv ( mux_right_track_32_undriven_sram_inv ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_78 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_10 mux_right_track_34 ( - .in ( { chany_top_in[16] , right_bottom_grid_pin_11_[0] } ) , - .sram ( mux_tree_tapbuf_size2_15_sram ) , - .sram_inv ( mux_right_track_34_undriven_sram_inv ) , - .out ( chanx_right_out[17] ) , .p0 ( optlc_net_78 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_12 mem_top_track_0 ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_14 mem_top_track_4 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_13 mem_top_track_24 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_11 mem_right_track_8 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_0 mem_right_track_10 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_1 mem_right_track_12 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_2 mem_right_track_14 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_3 mem_right_track_16 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_4 mem_right_track_18 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_5 mem_right_track_24 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_6 mem_right_track_26 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_11_sram ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_7 mem_right_track_28 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_12_sram ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_8 mem_right_track_30 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_13_sram ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_9 mem_right_track_32 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_14_sram ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_10 mem_right_track_34 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .ccff_tail ( { ropt_net_85 } ) , - .mem_out ( mux_tree_tapbuf_size2_15_sram ) ) ; -sb_0__0__mux_tree_tapbuf_size4_0 mux_right_track_0 ( - .in ( { chany_top_in[19] , right_bottom_grid_pin_1_[0] , - right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] } ) , - .sram ( mux_tree_tapbuf_size4_0_sram ) , - .sram_inv ( mux_right_track_0_undriven_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_78 ) ) ; -sb_0__0__mux_tree_tapbuf_size4_1 mux_right_track_2 ( - .in ( { chany_top_in[0] , right_bottom_grid_pin_3_[0] , - right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_11_[0] } ) , - .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_right_track_2_undriven_sram_inv ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_79 ) ) ; -sb_0__0__mux_tree_tapbuf_size4_2 mux_right_track_4 ( - .in ( { chany_top_in[1] , right_bottom_grid_pin_1_[0] , - right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] } ) , - .sram ( mux_tree_tapbuf_size4_2_sram ) , - .sram_inv ( mux_right_track_4_undriven_sram_inv ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_79 ) ) ; -sb_0__0__mux_tree_tapbuf_size4 mux_right_track_6 ( - .in ( { chany_top_in[2] , right_bottom_grid_pin_3_[0] , - right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_11_[0] } ) , - .sram ( mux_tree_tapbuf_size4_3_sram ) , - .sram_inv ( mux_right_track_6_undriven_sram_inv ) , - .out ( chanx_right_out[3] ) , .p0 ( optlc_net_79 ) ) ; -sb_0__0__mux_tree_tapbuf_size4_mem_0 mem_right_track_0 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ; -sb_0__0__mux_tree_tapbuf_size4_mem_1 mem_right_track_2 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ; -sb_0__0__mux_tree_tapbuf_size4_mem_2 mem_right_track_4 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ; -sb_0__0__mux_tree_tapbuf_size4_mem mem_right_track_6 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__0 ( .A ( chany_top_in[9] ) , - .X ( ropt_net_94 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_76 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_78 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_78 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_79 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_80 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_80 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chanx_right_in[0] ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_82 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_81 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_685 ( .A ( ropt_net_83 ) , - .X ( chanx_right_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_686 ( .A ( ropt_net_84 ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_687 ( .A ( ropt_net_85 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_688 ( .A ( chany_top_in[18] ) , - .X ( ropt_net_103 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_689 ( .A ( chanx_right_in[6] ) , - .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_690 ( .A ( chanx_right_in[15] ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_691 ( .A ( chanx_right_in[18] ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_692 ( .A ( ropt_net_90 ) , - .X ( ropt_net_99 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chanx_right_in[14] ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_693 ( .A ( ropt_net_91 ) , - .X ( ropt_net_98 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_694 ( .A ( ropt_net_92 ) , - .X ( ropt_net_100 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_695 ( .A ( ropt_net_93 ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_696 ( .A ( ropt_net_94 ) , - .X ( ropt_net_101 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_697 ( .A ( ropt_net_98 ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_46 ( .A ( chany_top_in[17] ) , - .X ( ropt_net_91 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_698 ( .A ( ropt_net_99 ) , - .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_48 ( .A ( chanx_right_in[2] ) , - .X ( chany_top_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_49 ( .A ( chanx_right_in[4] ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_699 ( .A ( ropt_net_100 ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_51 ( .A ( chanx_right_in[7] ) , - .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_52 ( .A ( chanx_right_in[8] ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_53 ( .A ( chanx_right_in[9] ) , - .X ( chany_top_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_54 ( .A ( chanx_right_in[10] ) , - .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_55 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_92 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_56 ( .A ( chanx_right_in[12] ) , - .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_700 ( .A ( ropt_net_101 ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_58 ( .A ( chanx_right_in[16] ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_59 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_90 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_701 ( .A ( ropt_net_102 ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_61 ( .A ( chanx_right_in[19] ) , - .X ( ropt_net_102 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_702 ( .A ( ropt_net_103 ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_67 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_93 ) ) ; -endmodule - - diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__0__icv_in_design.lvs.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__0__icv_in_design.lvs.v deleted file mode 100644 index 4a381c8..0000000 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__0__icv_in_design.lvs.v +++ /dev/null @@ -1,3166 +0,0 @@ -// -// -// -// -// -// -module sb_0__0__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__39 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__38 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__37 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__36 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__35 ( .A ( mem_out[1] ) , - .X ( net_aps_35 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_62 ( .A ( net_aps_35 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__34 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__33 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__32 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__31 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__30 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__29 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__28 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__27 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__26 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__25 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__24 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__23 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__22 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__21 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__20 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_41 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_40 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0_ ( prog_clk , chany_top_in , top_left_grid_pin_1_ , - chanx_right_in , right_bottom_grid_pin_1_ , right_bottom_grid_pin_3_ , - right_bottom_grid_pin_5_ , right_bottom_grid_pin_7_ , - right_bottom_grid_pin_9_ , right_bottom_grid_pin_11_ , ccff_head , - chany_top_out , chanx_right_out , ccff_tail , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:19] chany_top_in ; -input [0:0] top_left_grid_pin_1_ ; -input [0:19] chanx_right_in ; -input [0:0] right_bottom_grid_pin_1_ ; -input [0:0] right_bottom_grid_pin_3_ ; -input [0:0] right_bottom_grid_pin_5_ ; -input [0:0] right_bottom_grid_pin_7_ ; -input [0:0] right_bottom_grid_pin_9_ ; -input [0:0] right_bottom_grid_pin_11_ ; -input [0:0] ccff_head ; -output [0:19] chany_top_out ; -output [0:19] chanx_right_out ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; - -wire [0:2] mux_right_track_0_undriven_sram_inv ; -wire [0:1] mux_right_track_10_undriven_sram_inv ; -wire [0:1] mux_right_track_12_undriven_sram_inv ; -wire [0:1] mux_right_track_14_undriven_sram_inv ; -wire [0:1] mux_right_track_16_undriven_sram_inv ; -wire [0:1] mux_right_track_18_undriven_sram_inv ; -wire [0:1] mux_right_track_24_undriven_sram_inv ; -wire [0:1] mux_right_track_26_undriven_sram_inv ; -wire [0:1] mux_right_track_28_undriven_sram_inv ; -wire [0:2] mux_right_track_2_undriven_sram_inv ; -wire [0:1] mux_right_track_30_undriven_sram_inv ; -wire [0:1] mux_right_track_32_undriven_sram_inv ; -wire [0:1] mux_right_track_34_undriven_sram_inv ; -wire [0:2] mux_right_track_4_undriven_sram_inv ; -wire [0:2] mux_right_track_6_undriven_sram_inv ; -wire [0:1] mux_right_track_8_undriven_sram_inv ; -wire [0:1] mux_top_track_0_undriven_sram_inv ; -wire [0:1] mux_top_track_24_undriven_sram_inv ; -wire [0:1] mux_top_track_4_undriven_sram_inv ; -wire [0:1] mux_top_track_8_undriven_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_10_sram ; -wire [0:1] mux_tree_tapbuf_size2_11_sram ; -wire [0:1] mux_tree_tapbuf_size2_12_sram ; -wire [0:1] mux_tree_tapbuf_size2_13_sram ; -wire [0:1] mux_tree_tapbuf_size2_14_sram ; -wire [0:1] mux_tree_tapbuf_size2_15_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_5_sram ; -wire [0:1] mux_tree_tapbuf_size2_6_sram ; -wire [0:1] mux_tree_tapbuf_size2_7_sram ; -wire [0:1] mux_tree_tapbuf_size2_8_sram ; -wire [0:1] mux_tree_tapbuf_size2_9_sram ; -wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size4_0_sram ; -wire [0:2] mux_tree_tapbuf_size4_1_sram ; -wire [0:2] mux_tree_tapbuf_size4_2_sram ; -wire [0:2] mux_tree_tapbuf_size4_3_sram ; -wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; -supply1 VDD ; -supply0 VSS ; -// - -sb_0__0__mux_tree_tapbuf_size2_12 mux_top_track_0 ( - .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] } ) , - .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_top_track_0_undriven_sram_inv ) , - .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_80 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_14 mux_top_track_4 ( - .in ( { top_left_grid_pin_1_[0] , chanx_right_in[3] } ) , - .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_top_track_4_undriven_sram_inv ) , - .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_80 ) ) ; -sb_0__0__mux_tree_tapbuf_size2 mux_top_track_8 ( - .in ( { top_left_grid_pin_1_[0] , chanx_right_in[5] } ) , - .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_top_track_8_undriven_sram_inv ) , - .out ( chany_top_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_80 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_13 mux_top_track_24 ( - .in ( { top_left_grid_pin_1_[0] , chanx_right_in[13] } ) , - .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_top_track_24_undriven_sram_inv ) , - .out ( chany_top_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_81 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_11 mux_right_track_8 ( - .in ( { chany_top_in[3] , right_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_right_track_8_undriven_sram_inv ) , - .out ( { ropt_net_83 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_81 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_0 mux_right_track_10 ( - .in ( { chany_top_in[4] , right_bottom_grid_pin_3_[0] } ) , - .sram ( mux_tree_tapbuf_size2_5_sram ) , - .sram_inv ( mux_right_track_10_undriven_sram_inv ) , - .out ( chanx_right_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_81 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_1 mux_right_track_12 ( - .in ( { chany_top_in[5] , right_bottom_grid_pin_5_[0] } ) , - .sram ( mux_tree_tapbuf_size2_6_sram ) , - .sram_inv ( mux_right_track_12_undriven_sram_inv ) , - .out ( { ropt_net_84 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_78 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_2 mux_right_track_14 ( - .in ( { chany_top_in[6] , right_bottom_grid_pin_7_[0] } ) , - .sram ( mux_tree_tapbuf_size2_7_sram ) , - .sram_inv ( mux_right_track_14_undriven_sram_inv ) , - .out ( chanx_right_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_78 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_3 mux_right_track_16 ( - .in ( { chany_top_in[7] , right_bottom_grid_pin_9_[0] } ) , - .sram ( mux_tree_tapbuf_size2_8_sram ) , - .sram_inv ( mux_right_track_16_undriven_sram_inv ) , - .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_78 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_4 mux_right_track_18 ( - .in ( { chany_top_in[8] , right_bottom_grid_pin_11_[0] } ) , - .sram ( mux_tree_tapbuf_size2_9_sram ) , - .sram_inv ( mux_right_track_18_undriven_sram_inv ) , - .out ( chanx_right_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_81 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_5 mux_right_track_24 ( - .in ( { chany_top_in[11] , right_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size2_10_sram ) , - .sram_inv ( mux_right_track_24_undriven_sram_inv ) , - .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_79 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_6 mux_right_track_26 ( - .in ( { chany_top_in[12] , right_bottom_grid_pin_3_[0] } ) , - .sram ( mux_tree_tapbuf_size2_11_sram ) , - .sram_inv ( mux_right_track_26_undriven_sram_inv ) , - .out ( chanx_right_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_79 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_7 mux_right_track_28 ( - .in ( { chany_top_in[13] , right_bottom_grid_pin_5_[0] } ) , - .sram ( mux_tree_tapbuf_size2_12_sram ) , - .sram_inv ( mux_right_track_28_undriven_sram_inv ) , - .out ( chanx_right_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_79 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_8 mux_right_track_30 ( - .in ( { chany_top_in[14] , right_bottom_grid_pin_7_[0] } ) , - .sram ( mux_tree_tapbuf_size2_13_sram ) , - .sram_inv ( mux_right_track_30_undriven_sram_inv ) , - .out ( chanx_right_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_78 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_9 mux_right_track_32 ( - .in ( { chany_top_in[15] , right_bottom_grid_pin_9_[0] } ) , - .sram ( mux_tree_tapbuf_size2_14_sram ) , - .sram_inv ( mux_right_track_32_undriven_sram_inv ) , - .out ( chanx_right_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_78 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_10 mux_right_track_34 ( - .in ( { chany_top_in[16] , right_bottom_grid_pin_11_[0] } ) , - .sram ( mux_tree_tapbuf_size2_15_sram ) , - .sram_inv ( mux_right_track_34_undriven_sram_inv ) , - .out ( chanx_right_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_78 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_12 mem_top_track_0 ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_14 mem_top_track_4 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_13 mem_top_track_24 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_11 mem_right_track_8 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_0 mem_right_track_10 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_1 mem_right_track_12 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_2 mem_right_track_14 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_3 mem_right_track_16 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_8_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_4 mem_right_track_18 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_9_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_5 mem_right_track_24 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_10_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_6 mem_right_track_26 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_11_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_7 mem_right_track_28 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_12_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_8 mem_right_track_30 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_13_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_9 mem_right_track_32 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_14_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_10 mem_right_track_34 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .ccff_tail ( { ropt_net_85 } ) , - .mem_out ( mux_tree_tapbuf_size2_15_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__0__mux_tree_tapbuf_size4_0 mux_right_track_0 ( - .in ( { chany_top_in[19] , right_bottom_grid_pin_1_[0] , - right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] } ) , - .sram ( mux_tree_tapbuf_size4_0_sram ) , - .sram_inv ( mux_right_track_0_undriven_sram_inv ) , - .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_78 ) ) ; -sb_0__0__mux_tree_tapbuf_size4_1 mux_right_track_2 ( - .in ( { chany_top_in[0] , right_bottom_grid_pin_3_[0] , - right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_11_[0] } ) , - .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_right_track_2_undriven_sram_inv ) , - .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_79 ) ) ; -sb_0__0__mux_tree_tapbuf_size4_2 mux_right_track_4 ( - .in ( { chany_top_in[1] , right_bottom_grid_pin_1_[0] , - right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] } ) , - .sram ( mux_tree_tapbuf_size4_2_sram ) , - .sram_inv ( mux_right_track_4_undriven_sram_inv ) , - .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_79 ) ) ; -sb_0__0__mux_tree_tapbuf_size4 mux_right_track_6 ( - .in ( { chany_top_in[2] , right_bottom_grid_pin_3_[0] , - right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_11_[0] } ) , - .sram ( mux_tree_tapbuf_size4_3_sram ) , - .sram_inv ( mux_right_track_6_undriven_sram_inv ) , - .out ( chanx_right_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_79 ) ) ; -sb_0__0__mux_tree_tapbuf_size4_mem_0 mem_right_track_0 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__0__mux_tree_tapbuf_size4_mem_1 mem_right_track_2 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__0__mux_tree_tapbuf_size4_mem_2 mem_right_track_4 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__0__mux_tree_tapbuf_size4_mem mem_right_track_6 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1227 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1228 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1229 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1230 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1231 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1232 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1233 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1234 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1235 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1236 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1237 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1238 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1239 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1240 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1241 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1242 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1243 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1244 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1245 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1246 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1247 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1248 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1249 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1250 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1251 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1252 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1253 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1254 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1255 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1256 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1257 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1258 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1259 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1260 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1261 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1262 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__0 ( .A ( chany_top_in[9] ) , - .X ( ropt_net_94 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_76 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_78 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_78 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_79 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_80 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_80 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chanx_right_in[0] ) , - .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_82 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_81 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_685 ( .A ( ropt_net_83 ) , - .X ( chanx_right_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_686 ( .A ( ropt_net_84 ) , - .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_687 ( .A ( ropt_net_85 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_688 ( .A ( chany_top_in[18] ) , - .X ( ropt_net_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_689 ( .A ( chanx_right_in[6] ) , - .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_690 ( .A ( chanx_right_in[15] ) , - .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_691 ( .A ( chanx_right_in[18] ) , - .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_692 ( .A ( ropt_net_90 ) , - .X ( ropt_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chanx_right_in[14] ) , - .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_693 ( .A ( ropt_net_91 ) , - .X ( ropt_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_694 ( .A ( ropt_net_92 ) , - .X ( ropt_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_695 ( .A ( ropt_net_93 ) , - .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_696 ( .A ( ropt_net_94 ) , - .X ( ropt_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_697 ( .A ( ropt_net_98 ) , - .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_46 ( .A ( chany_top_in[17] ) , - .X ( ropt_net_91 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_698 ( .A ( ropt_net_99 ) , - .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_48 ( .A ( chanx_right_in[2] ) , - .X ( chany_top_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_49 ( .A ( chanx_right_in[4] ) , - .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_699 ( .A ( ropt_net_100 ) , - .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_51 ( .A ( chanx_right_in[7] ) , - .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_52 ( .A ( chanx_right_in[8] ) , - .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_53 ( .A ( chanx_right_in[9] ) , - .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_54 ( .A ( chanx_right_in[10] ) , - .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_55 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_56 ( .A ( chanx_right_in[12] ) , - .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_700 ( .A ( ropt_net_101 ) , - .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_58 ( .A ( chanx_right_in[16] ) , - .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_59 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_90 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_701 ( .A ( ropt_net_102 ) , - .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_61 ( .A ( chanx_right_in[19] ) , - .X ( ropt_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_702 ( .A ( ropt_net_103 ) , - .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_67 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_93 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y0 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y0 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x220800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x358800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x331200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x349600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x358800y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x395600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x432400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x469200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x506000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x653200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x763600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x837200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x754400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x791200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x828000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x892400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x368000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x386400y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x823400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x860200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x538200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x731400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x768200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x805000y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x892400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x368000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x460000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x496800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x515200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x565800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x602600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x639400y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x749800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x786600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x805000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x427800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x639400y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x754400y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x892400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x147200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x165600y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x501400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x519800y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x561200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x570400y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x717600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x800400y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x349600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x391000y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x437000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x455400y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x533600y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x648600y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x763600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x828000y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x860200y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x892400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x331200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x349600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x395600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x473800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x561200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x611800y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x657800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x791200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x800400y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x846400y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x147200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x165600y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x211600y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x257600y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x303600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x312800y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x358800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x432400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x515200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x524400y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x570400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x630200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x680800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x731400y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x777400y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x823400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x874000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x220800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x303600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x340400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x377200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x414000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x584200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x621000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x754400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x791200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x128800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x211600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x248400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x358800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x501400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x552000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x561200y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x639400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x657800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x667000y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x892400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x248400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x395600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x414000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x496800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x607200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x616400y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x128800y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x207000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x243800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x326600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x363400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x409400y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x487600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x496800y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x653200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x892400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x147200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x207000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x243800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x749800y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x464600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x483000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x529000y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x809600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x828000y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x878600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x92000y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x133400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x170200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x207000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x216200y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x368000y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x414000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x450800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x575000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x667000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x763600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x782000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x184000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x193200y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x271400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x308200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x345000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x391000y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x510600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x529000y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x570400y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x690000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x708400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x717600y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x795800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x814200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x823400y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x855600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x892400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x331200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x340400y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x496800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x570400y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x680800y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x763600y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x841800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x184000y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x266800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x285200y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x335800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y870400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x124200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x161000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x197800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x234600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x271400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x308200y870400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x386400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x147200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x165600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x220800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x276000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x340400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y897600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x391000y897600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x464600y897600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x138000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x174800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y952000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y952000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__0__icv_in_design.pt.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__0__icv_in_design.pt.v deleted file mode 100644 index f9ba787..0000000 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__0__icv_in_design.pt.v +++ /dev/null @@ -1,1128 +0,0 @@ -// -// -// -// -// -// -module sb_0__0__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__39 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__38 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__37 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__36 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__35 ( .A ( mem_out[1] ) , - .X ( net_aps_35 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_62 ( .A ( net_aps_35 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__34 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__33 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__32 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__31 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__30 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__29 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__28 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__27 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__26 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__25 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__24 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__23 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__22 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__21 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__20 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_41 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_40 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__0_ ( prog_clk , chany_top_in , top_left_grid_pin_1_ , - chanx_right_in , right_bottom_grid_pin_1_ , right_bottom_grid_pin_3_ , - right_bottom_grid_pin_5_ , right_bottom_grid_pin_7_ , - right_bottom_grid_pin_9_ , right_bottom_grid_pin_11_ , ccff_head , - chany_top_out , chanx_right_out , ccff_tail ) ; -input [0:0] prog_clk ; -input [0:19] chany_top_in ; -input [0:0] top_left_grid_pin_1_ ; -input [0:19] chanx_right_in ; -input [0:0] right_bottom_grid_pin_1_ ; -input [0:0] right_bottom_grid_pin_3_ ; -input [0:0] right_bottom_grid_pin_5_ ; -input [0:0] right_bottom_grid_pin_7_ ; -input [0:0] right_bottom_grid_pin_9_ ; -input [0:0] right_bottom_grid_pin_11_ ; -input [0:0] ccff_head ; -output [0:19] chany_top_out ; -output [0:19] chanx_right_out ; -output [0:0] ccff_tail ; - -wire [0:2] mux_right_track_0_undriven_sram_inv ; -wire [0:1] mux_right_track_10_undriven_sram_inv ; -wire [0:1] mux_right_track_12_undriven_sram_inv ; -wire [0:1] mux_right_track_14_undriven_sram_inv ; -wire [0:1] mux_right_track_16_undriven_sram_inv ; -wire [0:1] mux_right_track_18_undriven_sram_inv ; -wire [0:1] mux_right_track_24_undriven_sram_inv ; -wire [0:1] mux_right_track_26_undriven_sram_inv ; -wire [0:1] mux_right_track_28_undriven_sram_inv ; -wire [0:2] mux_right_track_2_undriven_sram_inv ; -wire [0:1] mux_right_track_30_undriven_sram_inv ; -wire [0:1] mux_right_track_32_undriven_sram_inv ; -wire [0:1] mux_right_track_34_undriven_sram_inv ; -wire [0:2] mux_right_track_4_undriven_sram_inv ; -wire [0:2] mux_right_track_6_undriven_sram_inv ; -wire [0:1] mux_right_track_8_undriven_sram_inv ; -wire [0:1] mux_top_track_0_undriven_sram_inv ; -wire [0:1] mux_top_track_24_undriven_sram_inv ; -wire [0:1] mux_top_track_4_undriven_sram_inv ; -wire [0:1] mux_top_track_8_undriven_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_10_sram ; -wire [0:1] mux_tree_tapbuf_size2_11_sram ; -wire [0:1] mux_tree_tapbuf_size2_12_sram ; -wire [0:1] mux_tree_tapbuf_size2_13_sram ; -wire [0:1] mux_tree_tapbuf_size2_14_sram ; -wire [0:1] mux_tree_tapbuf_size2_15_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_5_sram ; -wire [0:1] mux_tree_tapbuf_size2_6_sram ; -wire [0:1] mux_tree_tapbuf_size2_7_sram ; -wire [0:1] mux_tree_tapbuf_size2_8_sram ; -wire [0:1] mux_tree_tapbuf_size2_9_sram ; -wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size4_0_sram ; -wire [0:2] mux_tree_tapbuf_size4_1_sram ; -wire [0:2] mux_tree_tapbuf_size4_2_sram ; -wire [0:2] mux_tree_tapbuf_size4_3_sram ; -wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; -// - -sb_0__0__mux_tree_tapbuf_size2_12 mux_top_track_0 ( - .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] } ) , - .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_top_track_0_undriven_sram_inv ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_80 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_14 mux_top_track_4 ( - .in ( { top_left_grid_pin_1_[0] , chanx_right_in[3] } ) , - .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_top_track_4_undriven_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_80 ) ) ; -sb_0__0__mux_tree_tapbuf_size2 mux_top_track_8 ( - .in ( { top_left_grid_pin_1_[0] , chanx_right_in[5] } ) , - .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_top_track_8_undriven_sram_inv ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_80 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_13 mux_top_track_24 ( - .in ( { top_left_grid_pin_1_[0] , chanx_right_in[13] } ) , - .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_top_track_24_undriven_sram_inv ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_81 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_11 mux_right_track_8 ( - .in ( { chany_top_in[3] , right_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_right_track_8_undriven_sram_inv ) , - .out ( { ropt_net_83 } ) , - .p0 ( optlc_net_81 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_0 mux_right_track_10 ( - .in ( { chany_top_in[4] , right_bottom_grid_pin_3_[0] } ) , - .sram ( mux_tree_tapbuf_size2_5_sram ) , - .sram_inv ( mux_right_track_10_undriven_sram_inv ) , - .out ( chanx_right_out[5] ) , .p0 ( optlc_net_81 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_1 mux_right_track_12 ( - .in ( { chany_top_in[5] , right_bottom_grid_pin_5_[0] } ) , - .sram ( mux_tree_tapbuf_size2_6_sram ) , - .sram_inv ( mux_right_track_12_undriven_sram_inv ) , - .out ( { ropt_net_84 } ) , - .p0 ( optlc_net_78 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_2 mux_right_track_14 ( - .in ( { chany_top_in[6] , right_bottom_grid_pin_7_[0] } ) , - .sram ( mux_tree_tapbuf_size2_7_sram ) , - .sram_inv ( mux_right_track_14_undriven_sram_inv ) , - .out ( chanx_right_out[7] ) , .p0 ( optlc_net_78 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_3 mux_right_track_16 ( - .in ( { chany_top_in[7] , right_bottom_grid_pin_9_[0] } ) , - .sram ( mux_tree_tapbuf_size2_8_sram ) , - .sram_inv ( mux_right_track_16_undriven_sram_inv ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_78 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_4 mux_right_track_18 ( - .in ( { chany_top_in[8] , right_bottom_grid_pin_11_[0] } ) , - .sram ( mux_tree_tapbuf_size2_9_sram ) , - .sram_inv ( mux_right_track_18_undriven_sram_inv ) , - .out ( chanx_right_out[9] ) , .p0 ( optlc_net_81 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_5 mux_right_track_24 ( - .in ( { chany_top_in[11] , right_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size2_10_sram ) , - .sram_inv ( mux_right_track_24_undriven_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_79 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_6 mux_right_track_26 ( - .in ( { chany_top_in[12] , right_bottom_grid_pin_3_[0] } ) , - .sram ( mux_tree_tapbuf_size2_11_sram ) , - .sram_inv ( mux_right_track_26_undriven_sram_inv ) , - .out ( chanx_right_out[13] ) , .p0 ( optlc_net_79 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_7 mux_right_track_28 ( - .in ( { chany_top_in[13] , right_bottom_grid_pin_5_[0] } ) , - .sram ( mux_tree_tapbuf_size2_12_sram ) , - .sram_inv ( mux_right_track_28_undriven_sram_inv ) , - .out ( chanx_right_out[14] ) , .p0 ( optlc_net_79 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_8 mux_right_track_30 ( - .in ( { chany_top_in[14] , right_bottom_grid_pin_7_[0] } ) , - .sram ( mux_tree_tapbuf_size2_13_sram ) , - .sram_inv ( mux_right_track_30_undriven_sram_inv ) , - .out ( chanx_right_out[15] ) , .p0 ( optlc_net_78 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_9 mux_right_track_32 ( - .in ( { chany_top_in[15] , right_bottom_grid_pin_9_[0] } ) , - .sram ( mux_tree_tapbuf_size2_14_sram ) , - .sram_inv ( mux_right_track_32_undriven_sram_inv ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_78 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_10 mux_right_track_34 ( - .in ( { chany_top_in[16] , right_bottom_grid_pin_11_[0] } ) , - .sram ( mux_tree_tapbuf_size2_15_sram ) , - .sram_inv ( mux_right_track_34_undriven_sram_inv ) , - .out ( chanx_right_out[17] ) , .p0 ( optlc_net_78 ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_12 mem_top_track_0 ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_14 mem_top_track_4 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_13 mem_top_track_24 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_11 mem_right_track_8 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_0 mem_right_track_10 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_1 mem_right_track_12 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_2 mem_right_track_14 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_3 mem_right_track_16 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_4 mem_right_track_18 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_5 mem_right_track_24 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_6 mem_right_track_26 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_11_sram ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_7 mem_right_track_28 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_12_sram ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_8 mem_right_track_30 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_13_sram ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_9 mem_right_track_32 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_14_sram ) ) ; -sb_0__0__mux_tree_tapbuf_size2_mem_10 mem_right_track_34 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .ccff_tail ( { ropt_net_85 } ) , - .mem_out ( mux_tree_tapbuf_size2_15_sram ) ) ; -sb_0__0__mux_tree_tapbuf_size4_0 mux_right_track_0 ( - .in ( { chany_top_in[19] , right_bottom_grid_pin_1_[0] , - right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] } ) , - .sram ( mux_tree_tapbuf_size4_0_sram ) , - .sram_inv ( mux_right_track_0_undriven_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_78 ) ) ; -sb_0__0__mux_tree_tapbuf_size4_1 mux_right_track_2 ( - .in ( { chany_top_in[0] , right_bottom_grid_pin_3_[0] , - right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_11_[0] } ) , - .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_right_track_2_undriven_sram_inv ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_79 ) ) ; -sb_0__0__mux_tree_tapbuf_size4_2 mux_right_track_4 ( - .in ( { chany_top_in[1] , right_bottom_grid_pin_1_[0] , - right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] } ) , - .sram ( mux_tree_tapbuf_size4_2_sram ) , - .sram_inv ( mux_right_track_4_undriven_sram_inv ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_79 ) ) ; -sb_0__0__mux_tree_tapbuf_size4 mux_right_track_6 ( - .in ( { chany_top_in[2] , right_bottom_grid_pin_3_[0] , - right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_11_[0] } ) , - .sram ( mux_tree_tapbuf_size4_3_sram ) , - .sram_inv ( mux_right_track_6_undriven_sram_inv ) , - .out ( chanx_right_out[3] ) , .p0 ( optlc_net_79 ) ) ; -sb_0__0__mux_tree_tapbuf_size4_mem_0 mem_right_track_0 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ; -sb_0__0__mux_tree_tapbuf_size4_mem_1 mem_right_track_2 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ; -sb_0__0__mux_tree_tapbuf_size4_mem_2 mem_right_track_4 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ; -sb_0__0__mux_tree_tapbuf_size4_mem mem_right_track_6 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__0 ( .A ( chany_top_in[9] ) , - .X ( ropt_net_94 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_76 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_78 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_78 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_79 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_80 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_80 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chanx_right_in[0] ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_82 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_81 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_685 ( .A ( ropt_net_83 ) , - .X ( chanx_right_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_686 ( .A ( ropt_net_84 ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_687 ( .A ( ropt_net_85 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_688 ( .A ( chany_top_in[18] ) , - .X ( ropt_net_103 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_689 ( .A ( chanx_right_in[6] ) , - .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_690 ( .A ( chanx_right_in[15] ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_691 ( .A ( chanx_right_in[18] ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_692 ( .A ( ropt_net_90 ) , - .X ( ropt_net_99 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chanx_right_in[14] ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_693 ( .A ( ropt_net_91 ) , - .X ( ropt_net_98 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_694 ( .A ( ropt_net_92 ) , - .X ( ropt_net_100 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_695 ( .A ( ropt_net_93 ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_696 ( .A ( ropt_net_94 ) , - .X ( ropt_net_101 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_697 ( .A ( ropt_net_98 ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_46 ( .A ( chany_top_in[17] ) , - .X ( ropt_net_91 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_698 ( .A ( ropt_net_99 ) , - .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_48 ( .A ( chanx_right_in[2] ) , - .X ( chany_top_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_49 ( .A ( chanx_right_in[4] ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_699 ( .A ( ropt_net_100 ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_51 ( .A ( chanx_right_in[7] ) , - .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_52 ( .A ( chanx_right_in[8] ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_53 ( .A ( chanx_right_in[9] ) , - .X ( chany_top_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_54 ( .A ( chanx_right_in[10] ) , - .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_55 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_92 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_56 ( .A ( chanx_right_in[12] ) , - .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_700 ( .A ( ropt_net_101 ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_58 ( .A ( chanx_right_in[16] ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_59 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_90 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_701 ( .A ( ropt_net_102 ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_61 ( .A ( chanx_right_in[19] ) , - .X ( ropt_net_102 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_702 ( .A ( ropt_net_103 ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_67 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_93 ) ) ; -endmodule - - diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__1__icv_in_design.fm.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__1__icv_in_design.fm.v deleted file mode 100644 index 3af8e7b..0000000 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__1__icv_in_design.fm.v +++ /dev/null @@ -1,2390 +0,0 @@ -// -// -// -// -// -// -module sb_0__1__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__59 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__58 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__57 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__56 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__55 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__54 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__const1 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_0__1__const1 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__1__const1_31 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_0__1__const1_31 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__1__const1_30 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -sb_0__1__const1_30 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_0__1__const1_29 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_0__1__const1_29 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__1__const1_28 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_0__1__const1_28 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__1__const1_27 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_0__1__const1_27 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_127 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_27__53 ( .A ( mem_out[1] ) , - .X ( net_net_86 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_85 ( .A ( net_net_86 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__52 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__51 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__50 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__49 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__const1_26 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sb_0__1__const1_26 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_0__1__const1_25 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sb_0__1__const1_25 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_0__1__const1_24 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sb_0__1__const1_24 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_0__1__const1_23 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sb_0__1__const1_23 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_0__1__const1_22 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sb_0__1__const1_22 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__48 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__47 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__46 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__const1_21 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sb_0__1__const1_21 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_0__1__const1_20 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sb_0__1__const1_20 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_0__1__const1_19 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sb_0__1__const1_19 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size4_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__45 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__44 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__43 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__42 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size4_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__41 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__40 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size4_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__39 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__const1_18 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sb_0__1__const1_18 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -endmodule - - -module sb_0__1__const1_17 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sb_0__1__const1_17 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_126 ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_0__1__const1_16 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sb_0__1__const1_16 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -endmodule - - -module sb_0__1__const1_15 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sb_0__1__const1_15 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -endmodule - - -module sb_0__1__const1_14 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sb_0__1__const1_14 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_65 ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_0__1__const1_13 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sb_0__1__const1_13 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -endmodule - - -module sb_0__1__const1_12 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size4_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sb_0__1__const1_12 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_124 ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size5_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__38 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__37 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size5_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__36 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size5_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__35 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__34 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__const1_11 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -sb_0__1__const1_11 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -endmodule - - -module sb_0__1__const1_10 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -sb_0__1__const1_10 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -endmodule - - -module sb_0__1__const1_9 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -sb_0__1__const1_9 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -endmodule - - -module sb_0__1__const1_8 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size5_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -sb_0__1__const1_8 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -endmodule - - -module sb_0__1__const1_7 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -sb_0__1__const1_7 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_63 ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( BUF_net_63 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_123 ( .A ( BUF_net_63 ) , - .X ( out[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__33 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__32 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__31 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__30 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__29 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__28 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__27 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__const1_6 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sb_0__1__const1_6 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module sb_0__1__const1_5 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sb_0__1__const1_5 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_62 ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( BUF_net_62 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_122 ( .A ( BUF_net_62 ) , - .X ( out[0] ) ) ; -endmodule - - -module sb_0__1__const1_4 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sb_0__1__const1_4 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module sb_0__1__const1_3 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sb_0__1__const1_3 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module sb_0__1__const1_2 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -sb_0__1__const1_2 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_0__1__const1_1 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sb_0__1__const1_1 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module sb_0__1__const1_0 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sb_0__1__const1_0 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module sb_0__1_ ( prog_clk , chany_top_in , top_left_grid_pin_1_ , - chanx_right_in , right_bottom_grid_pin_34_ , right_bottom_grid_pin_35_ , - right_bottom_grid_pin_36_ , right_bottom_grid_pin_37_ , - right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ , - right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ , chany_bottom_in , - bottom_left_grid_pin_1_ , ccff_head , chany_top_out , chanx_right_out , - chany_bottom_out , ccff_tail , prog_clk__FEEDTHRU_1 ) ; -input [0:0] prog_clk ; -input [0:19] chany_top_in ; -input [0:0] top_left_grid_pin_1_ ; -input [0:19] chanx_right_in ; -input [0:0] right_bottom_grid_pin_34_ ; -input [0:0] right_bottom_grid_pin_35_ ; -input [0:0] right_bottom_grid_pin_36_ ; -input [0:0] right_bottom_grid_pin_37_ ; -input [0:0] right_bottom_grid_pin_38_ ; -input [0:0] right_bottom_grid_pin_39_ ; -input [0:0] right_bottom_grid_pin_40_ ; -input [0:0] right_bottom_grid_pin_41_ ; -input [0:19] chany_bottom_in ; -input [0:0] bottom_left_grid_pin_1_ ; -input [0:0] ccff_head ; -output [0:19] chany_top_out ; -output [0:19] chanx_right_out ; -output [0:19] chany_bottom_out ; -output [0:0] ccff_tail ; -output [0:0] prog_clk__FEEDTHRU_1 ; - -wire [0:2] mux_bottom_track_17_undriven_sram_inv ; -wire [0:2] mux_bottom_track_1_undriven_sram_inv ; -wire [0:2] mux_bottom_track_25_undriven_sram_inv ; -wire [0:1] mux_bottom_track_33_undriven_sram_inv ; -wire [0:2] mux_bottom_track_3_undriven_sram_inv ; -wire [0:2] mux_bottom_track_5_undriven_sram_inv ; -wire [0:2] mux_bottom_track_9_undriven_sram_inv ; -wire [0:2] mux_right_track_0_undriven_sram_inv ; -wire [0:2] mux_right_track_10_undriven_sram_inv ; -wire [0:2] mux_right_track_12_undriven_sram_inv ; -wire [0:2] mux_right_track_14_undriven_sram_inv ; -wire [0:1] mux_right_track_16_undriven_sram_inv ; -wire [0:1] mux_right_track_18_undriven_sram_inv ; -wire [0:1] mux_right_track_20_undriven_sram_inv ; -wire [0:1] mux_right_track_22_undriven_sram_inv ; -wire [0:2] mux_right_track_24_undriven_sram_inv ; -wire [0:1] mux_right_track_26_undriven_sram_inv ; -wire [0:1] mux_right_track_28_undriven_sram_inv ; -wire [0:2] mux_right_track_2_undriven_sram_inv ; -wire [0:1] mux_right_track_30_undriven_sram_inv ; -wire [0:1] mux_right_track_32_undriven_sram_inv ; -wire [0:1] mux_right_track_34_undriven_sram_inv ; -wire [0:1] mux_right_track_36_undriven_sram_inv ; -wire [0:2] mux_right_track_4_undriven_sram_inv ; -wire [0:2] mux_right_track_6_undriven_sram_inv ; -wire [0:2] mux_right_track_8_undriven_sram_inv ; -wire [0:2] mux_top_track_0_undriven_sram_inv ; -wire [0:2] mux_top_track_16_undriven_sram_inv ; -wire [0:2] mux_top_track_24_undriven_sram_inv ; -wire [0:2] mux_top_track_2_undriven_sram_inv ; -wire [0:2] mux_top_track_32_undriven_sram_inv ; -wire [0:2] mux_top_track_4_undriven_sram_inv ; -wire [0:2] mux_top_track_8_undriven_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_5_sram ; -wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; -wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:1] mux_tree_tapbuf_size3_2_sram ; -wire [0:1] mux_tree_tapbuf_size3_3_sram ; -wire [0:1] mux_tree_tapbuf_size3_4_sram ; -wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size4_0_sram ; -wire [0:2] mux_tree_tapbuf_size4_1_sram ; -wire [0:2] mux_tree_tapbuf_size4_2_sram ; -wire [0:2] mux_tree_tapbuf_size4_3_sram ; -wire [0:2] mux_tree_tapbuf_size4_4_sram ; -wire [0:2] mux_tree_tapbuf_size4_5_sram ; -wire [0:2] mux_tree_tapbuf_size4_6_sram ; -wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_6_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size5_0_sram ; -wire [0:2] mux_tree_tapbuf_size5_1_sram ; -wire [0:2] mux_tree_tapbuf_size5_2_sram ; -wire [0:2] mux_tree_tapbuf_size5_3_sram ; -wire [0:2] mux_tree_tapbuf_size5_4_sram ; -wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size6_1_sram ; -wire [0:2] mux_tree_tapbuf_size6_2_sram ; -wire [0:2] mux_tree_tapbuf_size6_3_sram ; -wire [0:2] mux_tree_tapbuf_size6_4_sram ; -wire [0:2] mux_tree_tapbuf_size6_5_sram ; -wire [0:2] mux_tree_tapbuf_size6_6_sram ; -wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_6_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size7_0_sram ; -wire [0:2] mux_tree_tapbuf_size7_1_sram ; -wire [0:2] mux_tree_tapbuf_size7_2_sram ; -wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; -// - -sb_0__1__mux_tree_tapbuf_size6_4 mux_top_track_0 ( - .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] , chanx_right_in[8] , - chanx_right_in[15] , chany_bottom_in[2] , chany_bottom_in[12] } ) , - .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_top_track_0_undriven_sram_inv ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_156 ) ) ; -sb_0__1__mux_tree_tapbuf_size6_5 mux_top_track_4 ( - .in ( { top_left_grid_pin_1_[0] , chanx_right_in[3] , chanx_right_in[10] , - chanx_right_in[17] , chany_bottom_in[5] , chany_bottom_in[14] } ) , - .sram ( mux_tree_tapbuf_size6_1_sram ) , - .sram_inv ( mux_top_track_4_undriven_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_156 ) ) ; -sb_0__1__mux_tree_tapbuf_size6 mux_top_track_8 ( - .in ( { top_left_grid_pin_1_[0] , chanx_right_in[4] , chanx_right_in[11] , - chanx_right_in[18] , chany_bottom_in[6] , chany_bottom_in[16] } ) , - .sram ( mux_tree_tapbuf_size6_2_sram ) , - .sram_inv ( mux_top_track_8_undriven_sram_inv ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_157 ) ) ; -sb_0__1__mux_tree_tapbuf_size6_3 mux_right_track_0 ( - .in ( { chany_top_in[2] , right_bottom_grid_pin_34_[0] , - right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , - right_bottom_grid_pin_40_[0] , chany_bottom_in[2] } ) , - .sram ( mux_tree_tapbuf_size6_3_sram ) , - .sram_inv ( mux_right_track_0_undriven_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_152 ) ) ; -sb_0__1__mux_tree_tapbuf_size6_0 mux_bottom_track_1 ( - .in ( { chany_top_in[2] , chany_top_in[12] , chanx_right_in[5] , - chanx_right_in[12] , chanx_right_in[19] , bottom_left_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size6_4_sram ) , - .sram_inv ( mux_bottom_track_1_undriven_sram_inv ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_155 ) ) ; -sb_0__1__mux_tree_tapbuf_size6_1 mux_bottom_track_5 ( - .in ( { chany_top_in[5] , chany_top_in[14] , chanx_right_in[3] , - chanx_right_in[10] , chanx_right_in[17] , bottom_left_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size6_5_sram ) , - .sram_inv ( mux_bottom_track_5_undriven_sram_inv ) , - .out ( { ropt_net_167 } ) , - .p0 ( optlc_net_151 ) ) ; -sb_0__1__mux_tree_tapbuf_size6_2 mux_bottom_track_9 ( - .in ( { chany_top_in[6] , chany_top_in[16] , chanx_right_in[2] , - chanx_right_in[9] , chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size6_6_sram ) , - .sram_inv ( mux_bottom_track_9_undriven_sram_inv ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_151 ) ) ; -sb_0__1__mux_tree_tapbuf_size6_mem_4 mem_top_track_0 ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size6_mem_5 mem_top_track_4 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size6_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_2_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size6_mem_3 mem_right_track_0 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_3_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_4_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size6_mem_1 mem_bottom_track_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_5_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size6_mem_2 mem_bottom_track_9 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_6_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size5 mux_top_track_2 ( - .in ( { chanx_right_in[2] , chanx_right_in[9] , chanx_right_in[16] , - chany_bottom_in[4] , chany_bottom_in[13] } ) , - .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_top_track_2_undriven_sram_inv ) , - .out ( { ropt_net_168 } ) , - .p0 ( optlc_net_156 ) ) ; -sb_0__1__mux_tree_tapbuf_size5_3 mux_top_track_16 ( - .in ( { chanx_right_in[5] , chanx_right_in[12] , chanx_right_in[19] , - chany_bottom_in[8] , chany_bottom_in[17] } ) , - .sram ( mux_tree_tapbuf_size5_1_sram ) , - .sram_inv ( mux_top_track_16_undriven_sram_inv ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_157 ) ) ; -sb_0__1__mux_tree_tapbuf_size5_2 mux_bottom_track_3 ( - .in ( { chany_top_in[4] , chany_top_in[13] , chanx_right_in[4] , - chanx_right_in[11] , chanx_right_in[18] } ) , - .sram ( mux_tree_tapbuf_size5_2_sram ) , - .sram_inv ( mux_bottom_track_3_undriven_sram_inv ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_155 ) ) ; -sb_0__1__mux_tree_tapbuf_size5_0 mux_bottom_track_17 ( - .in ( { chany_top_in[8] , chany_top_in[17] , chanx_right_in[1] , - chanx_right_in[8] , chanx_right_in[15] } ) , - .sram ( mux_tree_tapbuf_size5_3_sram ) , - .sram_inv ( mux_bottom_track_17_undriven_sram_inv ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_151 ) ) ; -sb_0__1__mux_tree_tapbuf_size5_1 mux_bottom_track_25 ( - .in ( { chany_top_in[9] , chany_top_in[18] , chanx_right_in[0] , - chanx_right_in[7] , chanx_right_in[14] } ) , - .sram ( mux_tree_tapbuf_size5_4_sram ) , - .sram_inv ( mux_bottom_track_25_undriven_sram_inv ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_154 ) ) ; -sb_0__1__mux_tree_tapbuf_size5_mem mem_top_track_2 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size5_mem_3 mem_top_track_16 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size5_mem_2 mem_bottom_track_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_2_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size5_mem_0 mem_bottom_track_17 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_3_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size5_mem_1 mem_bottom_track_25 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_4_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size4_5 mux_top_track_24 ( - .in ( { chanx_right_in[6] , chanx_right_in[13] , chany_bottom_in[9] , - chany_bottom_in[18] } ) , - .sram ( mux_tree_tapbuf_size4_0_sram ) , - .sram_inv ( mux_top_track_24_undriven_sram_inv ) , - .out ( { ropt_net_160 } ) , - .p0 ( optlc_net_153 ) ) ; -sb_0__1__mux_tree_tapbuf_size4 mux_top_track_32 ( - .in ( { chanx_right_in[0] , chanx_right_in[7] , chanx_right_in[14] , - chany_bottom_in[10] } ) , - .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_top_track_32_undriven_sram_inv ) , - .out ( chany_top_out[16] ) , .p0 ( optlc_net_153 ) ) ; -sb_0__1__mux_tree_tapbuf_size4_4 mux_right_track_8 ( - .in ( { chany_top_in[7] , chany_top_in[8] , right_bottom_grid_pin_34_[0] , - chany_bottom_in[8] } ) , - .sram ( mux_tree_tapbuf_size4_2_sram ) , - .sram_inv ( mux_right_track_8_undriven_sram_inv ) , - .out ( { ropt_net_163 } ) , - .p0 ( optlc_net_153 ) ) ; -sb_0__1__mux_tree_tapbuf_size4_0 mux_right_track_10 ( - .in ( { chany_top_in[9] , chany_top_in[11] , - right_bottom_grid_pin_35_[0] , chany_bottom_in[9] } ) , - .sram ( mux_tree_tapbuf_size4_3_sram ) , - .sram_inv ( mux_right_track_10_undriven_sram_inv ) , - .out ( chanx_right_out[5] ) , .p0 ( optlc_net_155 ) ) ; -sb_0__1__mux_tree_tapbuf_size4_1 mux_right_track_12 ( - .in ( { chany_top_in[10] , chany_top_in[15] , - right_bottom_grid_pin_36_[0] , chany_bottom_in[10] } ) , - .sram ( mux_tree_tapbuf_size4_4_sram ) , - .sram_inv ( mux_right_track_12_undriven_sram_inv ) , - .out ( chanx_right_out[6] ) , .p0 ( optlc_net_153 ) ) ; -sb_0__1__mux_tree_tapbuf_size4_2 mux_right_track_14 ( - .in ( { chany_top_in[12] , chany_top_in[19] , - right_bottom_grid_pin_37_[0] , chany_bottom_in[12] } ) , - .sram ( mux_tree_tapbuf_size4_5_sram ) , - .sram_inv ( mux_right_track_14_undriven_sram_inv ) , - .out ( { ropt_net_166 } ) , - .p0 ( optlc_net_155 ) ) ; -sb_0__1__mux_tree_tapbuf_size4_3 mux_right_track_24 ( - .in ( { chany_top_in[18] , right_bottom_grid_pin_34_[0] , - chany_bottom_in[18] , chany_bottom_in[19] } ) , - .sram ( mux_tree_tapbuf_size4_6_sram ) , - .sram_inv ( mux_right_track_24_undriven_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_154 ) ) ; -sb_0__1__mux_tree_tapbuf_size4_mem_5 mem_top_track_24 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size4_mem mem_top_track_32 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size4_mem_4 mem_right_track_8 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size4_mem_0 mem_right_track_10 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size4_mem_1 mem_right_track_12 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_4_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size4_mem_2 mem_right_track_14 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_5_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size4_mem_3 mem_right_track_24 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_6_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size7_0 mux_right_track_2 ( - .in ( { chany_top_in[0] , chany_top_in[4] , right_bottom_grid_pin_35_[0] , - right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , - right_bottom_grid_pin_41_[0] , chany_bottom_in[4] } ) , - .sram ( mux_tree_tapbuf_size7_0_sram ) , - .sram_inv ( mux_right_track_2_undriven_sram_inv ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_151 ) ) ; -sb_0__1__mux_tree_tapbuf_size7_1 mux_right_track_4 ( - .in ( { chany_top_in[1] , chany_top_in[5] , right_bottom_grid_pin_34_[0] , - right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , - right_bottom_grid_pin_40_[0] , chany_bottom_in[5] } ) , - .sram ( mux_tree_tapbuf_size7_1_sram ) , - .sram_inv ( mux_right_track_4_undriven_sram_inv ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_152 ) ) ; -sb_0__1__mux_tree_tapbuf_size7 mux_right_track_6 ( - .in ( { chany_top_in[3] , chany_top_in[6] , right_bottom_grid_pin_35_[0] , - right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , - right_bottom_grid_pin_41_[0] , chany_bottom_in[6] } ) , - .sram ( mux_tree_tapbuf_size7_2_sram ) , - .sram_inv ( mux_right_track_6_undriven_sram_inv ) , - .out ( chanx_right_out[3] ) , .p0 ( optlc_net_153 ) ) ; -sb_0__1__mux_tree_tapbuf_size7_mem_0 mem_right_track_2 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size7_mem_1 mem_right_track_4 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size7_mem mem_right_track_6 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size3_1 mux_right_track_16 ( - .in ( { chany_top_in[13] , right_bottom_grid_pin_38_[0] , - chany_bottom_in[13] } ) , - .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_right_track_16_undriven_sram_inv ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_151 ) ) ; -sb_0__1__mux_tree_tapbuf_size3_2 mux_right_track_18 ( - .in ( { chany_top_in[14] , right_bottom_grid_pin_39_[0] , - chany_bottom_in[14] } ) , - .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_right_track_18_undriven_sram_inv ) , - .out ( chanx_right_out[9] ) , .p0 ( optlc_net_152 ) ) ; -sb_0__1__mux_tree_tapbuf_size3_3 mux_right_track_20 ( - .in ( { chany_top_in[16] , right_bottom_grid_pin_40_[0] , - chany_bottom_in[16] } ) , - .sram ( mux_tree_tapbuf_size3_2_sram ) , - .sram_inv ( mux_right_track_20_undriven_sram_inv ) , - .out ( chanx_right_out[10] ) , .p0 ( optlc_net_152 ) ) ; -sb_0__1__mux_tree_tapbuf_size3 mux_right_track_22 ( - .in ( { chany_top_in[17] , right_bottom_grid_pin_41_[0] , - chany_bottom_in[17] } ) , - .sram ( mux_tree_tapbuf_size3_3_sram ) , - .sram_inv ( mux_right_track_22_undriven_sram_inv ) , - .out ( chanx_right_out[11] ) , .p0 ( optlc_net_154 ) ) ; -sb_0__1__mux_tree_tapbuf_size3_0 mux_bottom_track_33 ( - .in ( { chany_top_in[10] , chanx_right_in[6] , chanx_right_in[13] } ) , - .sram ( mux_tree_tapbuf_size3_4_sram ) , - .sram_inv ( mux_bottom_track_33_undriven_sram_inv ) , - .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_152 ) ) ; -sb_0__1__mux_tree_tapbuf_size3_mem_1 mem_right_track_16 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size3_mem_2 mem_right_track_18 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size3_mem_3 mem_right_track_20 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size3_mem mem_right_track_22 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_33 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , - .ccff_tail ( { ropt_net_179 } ) , - .mem_out ( mux_tree_tapbuf_size3_4_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size2_0 mux_right_track_26 ( - .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[15] } ) , - .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_right_track_26_undriven_sram_inv ) , - .out ( { ropt_net_173 } ) , - .p0 ( optlc_net_152 ) ) ; -sb_0__1__mux_tree_tapbuf_size2_1 mux_right_track_28 ( - .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[11] } ) , - .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_right_track_28_undriven_sram_inv ) , - .out ( chanx_right_out[14] ) , .p0 ( optlc_net_152 ) ) ; -sb_0__1__mux_tree_tapbuf_size2_2 mux_right_track_30 ( - .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[7] } ) , - .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_right_track_30_undriven_sram_inv ) , - .out ( chanx_right_out[15] ) , .p0 ( optlc_net_152 ) ) ; -sb_0__1__mux_tree_tapbuf_size2_3 mux_right_track_32 ( - .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[3] } ) , - .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_right_track_32_undriven_sram_inv ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_152 ) ) ; -sb_0__1__mux_tree_tapbuf_size2_4 mux_right_track_34 ( - .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[1] } ) , - .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_right_track_34_undriven_sram_inv ) , - .out ( chanx_right_out[17] ) , .p0 ( optlc_net_151 ) ) ; -sb_0__1__mux_tree_tapbuf_size2 mux_right_track_36 ( - .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[0] } ) , - .sram ( mux_tree_tapbuf_size2_5_sram ) , - .sram_inv ( mux_right_track_36_undriven_sram_inv ) , - .out ( chanx_right_out[18] ) , .p0 ( optlc_net_151 ) ) ; -sb_0__1__mux_tree_tapbuf_size2_mem_0 mem_right_track_26 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size2_mem_1 mem_right_track_28 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size2_mem_2 mem_right_track_30 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size2_mem_3 mem_right_track_32 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size2_mem_4 mem_right_track_34 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size2_mem mem_right_track_36 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_top_in[2] ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( ropt_net_182 ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_137 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_151 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_top_in[6] ) , - .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_141 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_152 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_144 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_153 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_top_in[10] ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_146 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_154 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , - .HI ( optlc_net_155 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chany_top_in[14] ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chany_top_in[16] ) , - .X ( ropt_net_180 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_151 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , - .HI ( optlc_net_156 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_153 ( .LO ( SYNOPSYS_UNCONNECTED_7 ) , - .HI ( optlc_net_157 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_814 ( .A ( ropt_net_183 ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__clkbuf_1 prog_clk_0__bip420 ( .A ( prog_clk[0] ) , - .X ( ctsbuf_net_1159 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_792 ( .A ( ropt_net_160 ) , - .X ( ropt_net_184 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chany_bottom_in[5] ) , - .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chany_bottom_in[6] ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chany_bottom_in[8] ) , - .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_184 ) , - .X ( chany_top_out[12] ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_345765 ( .A ( ctsbuf_net_1159 ) , - .X ( prog_clk__FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_816 ( .A ( ropt_net_185 ) , - .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( chany_top_in[18] ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chany_bottom_in[14] ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_25__24 ( .A ( chany_bottom_in[16] ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_817 ( .A ( ropt_net_186 ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_162 ) , - .X ( ropt_net_185 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_73 ( .A ( chany_top_in[4] ) , - .X ( BUF_net_73 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_818 ( .A ( ropt_net_187 ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_163 ) , - .X ( ropt_net_188 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_820 ( .A ( ropt_net_188 ) , - .X ( chanx_right_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_826 ( .A ( ropt_net_189 ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_827 ( .A ( ropt_net_190 ) , - .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_164 ) , - .X ( ropt_net_182 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( - .A ( right_bottom_grid_pin_41_[0] ) , .X ( ropt_net_191 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_166 ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_82 ( .A ( chany_bottom_in[10] ) , - .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_829 ( .A ( ropt_net_191 ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_192 ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_167 ) , - .X ( chany_bottom_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_168 ) , - .X ( chany_top_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_169 ) , - .X ( ropt_net_183 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_170 ) , - .X ( ropt_net_187 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_803 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_192 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_193 ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_804 ( .A ( chany_top_in[17] ) , - .X ( ropt_net_193 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( .A ( ropt_net_173 ) , - .X ( ropt_net_190 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_113 ( .A ( chany_top_in[8] ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_117 ( .A ( BUF_net_73 ) , - .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_118 ( .A ( chany_bottom_in[2] ) , - .X ( ropt_net_189 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_128 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_162 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( chany_top_in[9] ) , - .X ( ropt_net_186 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_131 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_164 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_133 ( .A ( chany_bottom_in[13] ) , - .X ( ropt_net_170 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_134 ( .A ( chany_bottom_in[18] ) , - .X ( ropt_net_169 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_807 ( .A ( chany_top_in[12] ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_808 ( - .A ( chany_bottom_in[17] ) , .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_809 ( .A ( chany_bottom_in[4] ) , - .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_810 ( - .A ( chany_bottom_in[12] ) , .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_179 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_180 ) , - .X ( chany_bottom_out[17] ) ) ; -endmodule - - diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__1__icv_in_design.lvs.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__1__icv_in_design.lvs.v deleted file mode 100644 index e4ffb0d..0000000 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__1__icv_in_design.lvs.v +++ /dev/null @@ -1,4446 +0,0 @@ -// -// -// -// -// -// -module sb_0__1__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__59 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__58 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__57 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__56 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__55 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__54 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_127 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_27__53 ( .A ( mem_out[1] ) , - .X ( net_net_86 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_85 ( .A ( net_net_86 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__52 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__51 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__50 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__49 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__48 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__47 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__46 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size4_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__45 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__44 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__43 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__42 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size4_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__41 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__40 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size4_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__39 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_126 ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_65 ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size4_5 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_124 ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size5_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__38 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__37 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size5_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__36 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size5_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__35 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__34 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size5_3 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_63 ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( BUF_net_63 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_123 ( .A ( BUF_net_63 ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__33 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__32 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__31 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__30 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__29 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__28 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__27 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_62 ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( BUF_net_62 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_122 ( .A ( BUF_net_62 ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6_3 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6_5 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6_4 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1_ ( prog_clk , chany_top_in , top_left_grid_pin_1_ , - chanx_right_in , right_bottom_grid_pin_34_ , right_bottom_grid_pin_35_ , - right_bottom_grid_pin_36_ , right_bottom_grid_pin_37_ , - right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ , - right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ , chany_bottom_in , - bottom_left_grid_pin_1_ , ccff_head , chany_top_out , chanx_right_out , - chany_bottom_out , ccff_tail , VDD , VSS , prog_clk__FEEDTHRU_1 ) ; -input [0:0] prog_clk ; -input [0:19] chany_top_in ; -input [0:0] top_left_grid_pin_1_ ; -input [0:19] chanx_right_in ; -input [0:0] right_bottom_grid_pin_34_ ; -input [0:0] right_bottom_grid_pin_35_ ; -input [0:0] right_bottom_grid_pin_36_ ; -input [0:0] right_bottom_grid_pin_37_ ; -input [0:0] right_bottom_grid_pin_38_ ; -input [0:0] right_bottom_grid_pin_39_ ; -input [0:0] right_bottom_grid_pin_40_ ; -input [0:0] right_bottom_grid_pin_41_ ; -input [0:19] chany_bottom_in ; -input [0:0] bottom_left_grid_pin_1_ ; -input [0:0] ccff_head ; -output [0:19] chany_top_out ; -output [0:19] chanx_right_out ; -output [0:19] chany_bottom_out ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; -output [0:0] prog_clk__FEEDTHRU_1 ; - -wire [0:2] mux_bottom_track_17_undriven_sram_inv ; -wire [0:2] mux_bottom_track_1_undriven_sram_inv ; -wire [0:2] mux_bottom_track_25_undriven_sram_inv ; -wire [0:1] mux_bottom_track_33_undriven_sram_inv ; -wire [0:2] mux_bottom_track_3_undriven_sram_inv ; -wire [0:2] mux_bottom_track_5_undriven_sram_inv ; -wire [0:2] mux_bottom_track_9_undriven_sram_inv ; -wire [0:2] mux_right_track_0_undriven_sram_inv ; -wire [0:2] mux_right_track_10_undriven_sram_inv ; -wire [0:2] mux_right_track_12_undriven_sram_inv ; -wire [0:2] mux_right_track_14_undriven_sram_inv ; -wire [0:1] mux_right_track_16_undriven_sram_inv ; -wire [0:1] mux_right_track_18_undriven_sram_inv ; -wire [0:1] mux_right_track_20_undriven_sram_inv ; -wire [0:1] mux_right_track_22_undriven_sram_inv ; -wire [0:2] mux_right_track_24_undriven_sram_inv ; -wire [0:1] mux_right_track_26_undriven_sram_inv ; -wire [0:1] mux_right_track_28_undriven_sram_inv ; -wire [0:2] mux_right_track_2_undriven_sram_inv ; -wire [0:1] mux_right_track_30_undriven_sram_inv ; -wire [0:1] mux_right_track_32_undriven_sram_inv ; -wire [0:1] mux_right_track_34_undriven_sram_inv ; -wire [0:1] mux_right_track_36_undriven_sram_inv ; -wire [0:2] mux_right_track_4_undriven_sram_inv ; -wire [0:2] mux_right_track_6_undriven_sram_inv ; -wire [0:2] mux_right_track_8_undriven_sram_inv ; -wire [0:2] mux_top_track_0_undriven_sram_inv ; -wire [0:2] mux_top_track_16_undriven_sram_inv ; -wire [0:2] mux_top_track_24_undriven_sram_inv ; -wire [0:2] mux_top_track_2_undriven_sram_inv ; -wire [0:2] mux_top_track_32_undriven_sram_inv ; -wire [0:2] mux_top_track_4_undriven_sram_inv ; -wire [0:2] mux_top_track_8_undriven_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_5_sram ; -wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; -wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:1] mux_tree_tapbuf_size3_2_sram ; -wire [0:1] mux_tree_tapbuf_size3_3_sram ; -wire [0:1] mux_tree_tapbuf_size3_4_sram ; -wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size4_0_sram ; -wire [0:2] mux_tree_tapbuf_size4_1_sram ; -wire [0:2] mux_tree_tapbuf_size4_2_sram ; -wire [0:2] mux_tree_tapbuf_size4_3_sram ; -wire [0:2] mux_tree_tapbuf_size4_4_sram ; -wire [0:2] mux_tree_tapbuf_size4_5_sram ; -wire [0:2] mux_tree_tapbuf_size4_6_sram ; -wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_6_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size5_0_sram ; -wire [0:2] mux_tree_tapbuf_size5_1_sram ; -wire [0:2] mux_tree_tapbuf_size5_2_sram ; -wire [0:2] mux_tree_tapbuf_size5_3_sram ; -wire [0:2] mux_tree_tapbuf_size5_4_sram ; -wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size6_1_sram ; -wire [0:2] mux_tree_tapbuf_size6_2_sram ; -wire [0:2] mux_tree_tapbuf_size6_3_sram ; -wire [0:2] mux_tree_tapbuf_size6_4_sram ; -wire [0:2] mux_tree_tapbuf_size6_5_sram ; -wire [0:2] mux_tree_tapbuf_size6_6_sram ; -wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_6_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size7_0_sram ; -wire [0:2] mux_tree_tapbuf_size7_1_sram ; -wire [0:2] mux_tree_tapbuf_size7_2_sram ; -wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; -supply1 VDD ; -supply0 VSS ; -// - -sb_0__1__mux_tree_tapbuf_size6_4 mux_top_track_0 ( - .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] , chanx_right_in[8] , - chanx_right_in[15] , chany_bottom_in[2] , chany_bottom_in[12] } ) , - .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_top_track_0_undriven_sram_inv ) , - .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_156 ) ) ; -sb_0__1__mux_tree_tapbuf_size6_5 mux_top_track_4 ( - .in ( { top_left_grid_pin_1_[0] , chanx_right_in[3] , chanx_right_in[10] , - chanx_right_in[17] , chany_bottom_in[5] , chany_bottom_in[14] } ) , - .sram ( mux_tree_tapbuf_size6_1_sram ) , - .sram_inv ( mux_top_track_4_undriven_sram_inv ) , - .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_156 ) ) ; -sb_0__1__mux_tree_tapbuf_size6 mux_top_track_8 ( - .in ( { top_left_grid_pin_1_[0] , chanx_right_in[4] , chanx_right_in[11] , - chanx_right_in[18] , chany_bottom_in[6] , chany_bottom_in[16] } ) , - .sram ( mux_tree_tapbuf_size6_2_sram ) , - .sram_inv ( mux_top_track_8_undriven_sram_inv ) , - .out ( chany_top_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_157 ) ) ; -sb_0__1__mux_tree_tapbuf_size6_3 mux_right_track_0 ( - .in ( { chany_top_in[2] , right_bottom_grid_pin_34_[0] , - right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , - right_bottom_grid_pin_40_[0] , chany_bottom_in[2] } ) , - .sram ( mux_tree_tapbuf_size6_3_sram ) , - .sram_inv ( mux_right_track_0_undriven_sram_inv ) , - .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_152 ) ) ; -sb_0__1__mux_tree_tapbuf_size6_0 mux_bottom_track_1 ( - .in ( { chany_top_in[2] , chany_top_in[12] , chanx_right_in[5] , - chanx_right_in[12] , chanx_right_in[19] , bottom_left_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size6_4_sram ) , - .sram_inv ( mux_bottom_track_1_undriven_sram_inv ) , - .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_155 ) ) ; -sb_0__1__mux_tree_tapbuf_size6_1 mux_bottom_track_5 ( - .in ( { chany_top_in[5] , chany_top_in[14] , chanx_right_in[3] , - chanx_right_in[10] , chanx_right_in[17] , bottom_left_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size6_5_sram ) , - .sram_inv ( mux_bottom_track_5_undriven_sram_inv ) , - .out ( { ropt_net_167 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_151 ) ) ; -sb_0__1__mux_tree_tapbuf_size6_2 mux_bottom_track_9 ( - .in ( { chany_top_in[6] , chany_top_in[16] , chanx_right_in[2] , - chanx_right_in[9] , chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size6_6_sram ) , - .sram_inv ( mux_bottom_track_9_undriven_sram_inv ) , - .out ( chany_bottom_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_151 ) ) ; -sb_0__1__mux_tree_tapbuf_size6_mem_4 mem_top_track_0 ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__1__mux_tree_tapbuf_size6_mem_5 mem_top_track_4 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__1__mux_tree_tapbuf_size6_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__1__mux_tree_tapbuf_size6_mem_3 mem_right_track_0 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__1__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__1__mux_tree_tapbuf_size6_mem_1 mem_bottom_track_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__1__mux_tree_tapbuf_size6_mem_2 mem_bottom_track_9 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__1__mux_tree_tapbuf_size5 mux_top_track_2 ( - .in ( { chanx_right_in[2] , chanx_right_in[9] , chanx_right_in[16] , - chany_bottom_in[4] , chany_bottom_in[13] } ) , - .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_top_track_2_undriven_sram_inv ) , - .out ( { ropt_net_168 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_156 ) ) ; -sb_0__1__mux_tree_tapbuf_size5_3 mux_top_track_16 ( - .in ( { chanx_right_in[5] , chanx_right_in[12] , chanx_right_in[19] , - chany_bottom_in[8] , chany_bottom_in[17] } ) , - .sram ( mux_tree_tapbuf_size5_1_sram ) , - .sram_inv ( mux_top_track_16_undriven_sram_inv ) , - .out ( chany_top_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_157 ) ) ; -sb_0__1__mux_tree_tapbuf_size5_2 mux_bottom_track_3 ( - .in ( { chany_top_in[4] , chany_top_in[13] , chanx_right_in[4] , - chanx_right_in[11] , chanx_right_in[18] } ) , - .sram ( mux_tree_tapbuf_size5_2_sram ) , - .sram_inv ( mux_bottom_track_3_undriven_sram_inv ) , - .out ( chany_bottom_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_155 ) ) ; -sb_0__1__mux_tree_tapbuf_size5_0 mux_bottom_track_17 ( - .in ( { chany_top_in[8] , chany_top_in[17] , chanx_right_in[1] , - chanx_right_in[8] , chanx_right_in[15] } ) , - .sram ( mux_tree_tapbuf_size5_3_sram ) , - .sram_inv ( mux_bottom_track_17_undriven_sram_inv ) , - .out ( chany_bottom_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_151 ) ) ; -sb_0__1__mux_tree_tapbuf_size5_1 mux_bottom_track_25 ( - .in ( { chany_top_in[9] , chany_top_in[18] , chanx_right_in[0] , - chanx_right_in[7] , chanx_right_in[14] } ) , - .sram ( mux_tree_tapbuf_size5_4_sram ) , - .sram_inv ( mux_bottom_track_25_undriven_sram_inv ) , - .out ( chany_bottom_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_154 ) ) ; -sb_0__1__mux_tree_tapbuf_size5_mem mem_top_track_2 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__1__mux_tree_tapbuf_size5_mem_3 mem_top_track_16 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__1__mux_tree_tapbuf_size5_mem_2 mem_bottom_track_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__1__mux_tree_tapbuf_size5_mem_0 mem_bottom_track_17 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__1__mux_tree_tapbuf_size5_mem_1 mem_bottom_track_25 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__1__mux_tree_tapbuf_size4_5 mux_top_track_24 ( - .in ( { chanx_right_in[6] , chanx_right_in[13] , chany_bottom_in[9] , - chany_bottom_in[18] } ) , - .sram ( mux_tree_tapbuf_size4_0_sram ) , - .sram_inv ( mux_top_track_24_undriven_sram_inv ) , - .out ( { ropt_net_160 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_153 ) ) ; -sb_0__1__mux_tree_tapbuf_size4 mux_top_track_32 ( - .in ( { chanx_right_in[0] , chanx_right_in[7] , chanx_right_in[14] , - chany_bottom_in[10] } ) , - .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_top_track_32_undriven_sram_inv ) , - .out ( chany_top_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_153 ) ) ; -sb_0__1__mux_tree_tapbuf_size4_4 mux_right_track_8 ( - .in ( { chany_top_in[7] , chany_top_in[8] , right_bottom_grid_pin_34_[0] , - chany_bottom_in[8] } ) , - .sram ( mux_tree_tapbuf_size4_2_sram ) , - .sram_inv ( mux_right_track_8_undriven_sram_inv ) , - .out ( { ropt_net_163 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_153 ) ) ; -sb_0__1__mux_tree_tapbuf_size4_0 mux_right_track_10 ( - .in ( { chany_top_in[9] , chany_top_in[11] , - right_bottom_grid_pin_35_[0] , chany_bottom_in[9] } ) , - .sram ( mux_tree_tapbuf_size4_3_sram ) , - .sram_inv ( mux_right_track_10_undriven_sram_inv ) , - .out ( chanx_right_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_155 ) ) ; -sb_0__1__mux_tree_tapbuf_size4_1 mux_right_track_12 ( - .in ( { chany_top_in[10] , chany_top_in[15] , - right_bottom_grid_pin_36_[0] , chany_bottom_in[10] } ) , - .sram ( mux_tree_tapbuf_size4_4_sram ) , - .sram_inv ( mux_right_track_12_undriven_sram_inv ) , - .out ( chanx_right_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_153 ) ) ; -sb_0__1__mux_tree_tapbuf_size4_2 mux_right_track_14 ( - .in ( { chany_top_in[12] , chany_top_in[19] , - right_bottom_grid_pin_37_[0] , chany_bottom_in[12] } ) , - .sram ( mux_tree_tapbuf_size4_5_sram ) , - .sram_inv ( mux_right_track_14_undriven_sram_inv ) , - .out ( { ropt_net_166 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_155 ) ) ; -sb_0__1__mux_tree_tapbuf_size4_3 mux_right_track_24 ( - .in ( { chany_top_in[18] , right_bottom_grid_pin_34_[0] , - chany_bottom_in[18] , chany_bottom_in[19] } ) , - .sram ( mux_tree_tapbuf_size4_6_sram ) , - .sram_inv ( mux_right_track_24_undriven_sram_inv ) , - .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_154 ) ) ; -sb_0__1__mux_tree_tapbuf_size4_mem_5 mem_top_track_24 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__1__mux_tree_tapbuf_size4_mem mem_top_track_32 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__1__mux_tree_tapbuf_size4_mem_4 mem_right_track_8 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__1__mux_tree_tapbuf_size4_mem_0 mem_right_track_10 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__1__mux_tree_tapbuf_size4_mem_1 mem_right_track_12 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__1__mux_tree_tapbuf_size4_mem_2 mem_right_track_14 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__1__mux_tree_tapbuf_size4_mem_3 mem_right_track_24 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__1__mux_tree_tapbuf_size7_0 mux_right_track_2 ( - .in ( { chany_top_in[0] , chany_top_in[4] , right_bottom_grid_pin_35_[0] , - right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , - right_bottom_grid_pin_41_[0] , chany_bottom_in[4] } ) , - .sram ( mux_tree_tapbuf_size7_0_sram ) , - .sram_inv ( mux_right_track_2_undriven_sram_inv ) , - .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_151 ) ) ; -sb_0__1__mux_tree_tapbuf_size7_1 mux_right_track_4 ( - .in ( { chany_top_in[1] , chany_top_in[5] , right_bottom_grid_pin_34_[0] , - right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , - right_bottom_grid_pin_40_[0] , chany_bottom_in[5] } ) , - .sram ( mux_tree_tapbuf_size7_1_sram ) , - .sram_inv ( mux_right_track_4_undriven_sram_inv ) , - .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_152 ) ) ; -sb_0__1__mux_tree_tapbuf_size7 mux_right_track_6 ( - .in ( { chany_top_in[3] , chany_top_in[6] , right_bottom_grid_pin_35_[0] , - right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , - right_bottom_grid_pin_41_[0] , chany_bottom_in[6] } ) , - .sram ( mux_tree_tapbuf_size7_2_sram ) , - .sram_inv ( mux_right_track_6_undriven_sram_inv ) , - .out ( chanx_right_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_153 ) ) ; -sb_0__1__mux_tree_tapbuf_size7_mem_0 mem_right_track_2 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__1__mux_tree_tapbuf_size7_mem_1 mem_right_track_4 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__1__mux_tree_tapbuf_size7_mem mem_right_track_6 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__1__mux_tree_tapbuf_size3_1 mux_right_track_16 ( - .in ( { chany_top_in[13] , right_bottom_grid_pin_38_[0] , - chany_bottom_in[13] } ) , - .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_right_track_16_undriven_sram_inv ) , - .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_151 ) ) ; -sb_0__1__mux_tree_tapbuf_size3_2 mux_right_track_18 ( - .in ( { chany_top_in[14] , right_bottom_grid_pin_39_[0] , - chany_bottom_in[14] } ) , - .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_right_track_18_undriven_sram_inv ) , - .out ( chanx_right_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_152 ) ) ; -sb_0__1__mux_tree_tapbuf_size3_3 mux_right_track_20 ( - .in ( { chany_top_in[16] , right_bottom_grid_pin_40_[0] , - chany_bottom_in[16] } ) , - .sram ( mux_tree_tapbuf_size3_2_sram ) , - .sram_inv ( mux_right_track_20_undriven_sram_inv ) , - .out ( chanx_right_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_152 ) ) ; -sb_0__1__mux_tree_tapbuf_size3 mux_right_track_22 ( - .in ( { chany_top_in[17] , right_bottom_grid_pin_41_[0] , - chany_bottom_in[17] } ) , - .sram ( mux_tree_tapbuf_size3_3_sram ) , - .sram_inv ( mux_right_track_22_undriven_sram_inv ) , - .out ( chanx_right_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_154 ) ) ; -sb_0__1__mux_tree_tapbuf_size3_0 mux_bottom_track_33 ( - .in ( { chany_top_in[10] , chanx_right_in[6] , chanx_right_in[13] } ) , - .sram ( mux_tree_tapbuf_size3_4_sram ) , - .sram_inv ( mux_bottom_track_33_undriven_sram_inv ) , - .out ( chany_bottom_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_152 ) ) ; -sb_0__1__mux_tree_tapbuf_size3_mem_1 mem_right_track_16 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__1__mux_tree_tapbuf_size3_mem_2 mem_right_track_18 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__1__mux_tree_tapbuf_size3_mem_3 mem_right_track_20 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__1__mux_tree_tapbuf_size3_mem mem_right_track_22 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__1__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_33 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , - .ccff_tail ( { ropt_net_179 } ) , - .mem_out ( mux_tree_tapbuf_size3_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__1__mux_tree_tapbuf_size2_0 mux_right_track_26 ( - .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[15] } ) , - .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_right_track_26_undriven_sram_inv ) , - .out ( { ropt_net_173 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_152 ) ) ; -sb_0__1__mux_tree_tapbuf_size2_1 mux_right_track_28 ( - .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[11] } ) , - .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_right_track_28_undriven_sram_inv ) , - .out ( chanx_right_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_152 ) ) ; -sb_0__1__mux_tree_tapbuf_size2_2 mux_right_track_30 ( - .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[7] } ) , - .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_right_track_30_undriven_sram_inv ) , - .out ( chanx_right_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_152 ) ) ; -sb_0__1__mux_tree_tapbuf_size2_3 mux_right_track_32 ( - .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[3] } ) , - .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_right_track_32_undriven_sram_inv ) , - .out ( chanx_right_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_152 ) ) ; -sb_0__1__mux_tree_tapbuf_size2_4 mux_right_track_34 ( - .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[1] } ) , - .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_right_track_34_undriven_sram_inv ) , - .out ( chanx_right_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_151 ) ) ; -sb_0__1__mux_tree_tapbuf_size2 mux_right_track_36 ( - .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[0] } ) , - .sram ( mux_tree_tapbuf_size2_5_sram ) , - .sram_inv ( mux_right_track_36_undriven_sram_inv ) , - .out ( chanx_right_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_151 ) ) ; -sb_0__1__mux_tree_tapbuf_size2_mem_0 mem_right_track_26 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__1__mux_tree_tapbuf_size2_mem_1 mem_right_track_28 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__1__mux_tree_tapbuf_size2_mem_2 mem_right_track_30 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__1__mux_tree_tapbuf_size2_mem_3 mem_right_track_32 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__1__mux_tree_tapbuf_size2_mem_4 mem_right_track_34 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__1__mux_tree_tapbuf_size2_mem mem_right_track_36 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1264 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1265 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1266 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1267 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1268 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1269 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1270 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1271 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1272 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1273 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1274 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1275 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1276 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1277 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1278 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1279 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1280 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1281 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1282 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1283 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1284 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1285 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1286 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1287 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1288 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1289 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1290 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1291 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1292 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1293 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1294 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1295 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1296 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1297 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1298 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1299 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1300 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1301 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_top_in[2] ) , - .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( ropt_net_182 ) , - .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_137 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_top_in[6] ) , - .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_141 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_144 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_top_in[10] ) , - .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_146 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , - .HI ( optlc_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chany_top_in[14] ) , - .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chany_top_in[16] ) , - .X ( ropt_net_180 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_151 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , - .HI ( optlc_net_156 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_153 ( .LO ( SYNOPSYS_UNCONNECTED_7 ) , - .HI ( optlc_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_814 ( .A ( ropt_net_183 ) , - .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__clkbuf_1 prog_clk_0__bip420 ( .A ( prog_clk[0] ) , - .X ( ctsbuf_net_1159 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_792 ( .A ( ropt_net_160 ) , - .X ( ropt_net_184 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chany_bottom_in[5] ) , - .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chany_bottom_in[6] ) , - .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chany_bottom_in[8] ) , - .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_184 ) , - .X ( chany_top_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_345765 ( .A ( ctsbuf_net_1159 ) , - .X ( prog_clk__FEEDTHRU_1[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_816 ( .A ( ropt_net_185 ) , - .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( chany_top_in[18] ) , - .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chany_bottom_in[14] ) , - .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_25__24 ( .A ( chany_bottom_in[16] ) , - .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_817 ( .A ( ropt_net_186 ) , - .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_162 ) , - .X ( ropt_net_185 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_73 ( .A ( chany_top_in[4] ) , - .X ( BUF_net_73 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_818 ( .A ( ropt_net_187 ) , - .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_163 ) , - .X ( ropt_net_188 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_820 ( .A ( ropt_net_188 ) , - .X ( chanx_right_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_826 ( .A ( ropt_net_189 ) , - .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_827 ( .A ( ropt_net_190 ) , - .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_164 ) , - .X ( ropt_net_182 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( - .A ( right_bottom_grid_pin_41_[0] ) , .X ( ropt_net_191 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_166 ) , - .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_82 ( .A ( chany_bottom_in[10] ) , - .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_829 ( .A ( ropt_net_191 ) , - .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_192 ) , - .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_167 ) , - .X ( chany_bottom_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_168 ) , - .X ( chany_top_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_169 ) , - .X ( ropt_net_183 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_170 ) , - .X ( ropt_net_187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_803 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_192 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_193 ) , - .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_804 ( .A ( chany_top_in[17] ) , - .X ( ropt_net_193 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( .A ( ropt_net_173 ) , - .X ( ropt_net_190 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_113 ( .A ( chany_top_in[8] ) , - .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_117 ( .A ( BUF_net_73 ) , - .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_118 ( .A ( chany_bottom_in[2] ) , - .X ( ropt_net_189 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_128 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_162 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( chany_top_in[9] ) , - .X ( ropt_net_186 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_131 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_164 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_133 ( .A ( chany_bottom_in[13] ) , - .X ( ropt_net_170 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_134 ( .A ( chany_bottom_in[18] ) , - .X ( ropt_net_169 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_807 ( .A ( chany_top_in[12] ) , - .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_808 ( - .A ( chany_bottom_in[17] ) , .X ( chany_top_out[18] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_809 ( .A ( chany_bottom_in[4] ) , - .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_810 ( - .A ( chany_bottom_in[12] ) , .X ( chany_top_out[13] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_179 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_180 ) , - .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y0 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y0 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x36800y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x216200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x271400y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x266800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x322000y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x358800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x395600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x202400y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x248400y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x289800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x326600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x345000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x510600y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x92000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x101200y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x142600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x179400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x197800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x207000y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x322000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x340400y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x386400y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x432400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x598000y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x851000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x147200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x165600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x174800y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x220800y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x266800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x285200y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x363400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x464600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x524400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x722200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x731400y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x253000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x289800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x372600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x409400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x437000y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x552000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x570400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x731400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x768200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x777400y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x294400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x312800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x322000y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x478400y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x524400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x722200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x740600y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x892400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x147200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x239200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x478400y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x556600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x565800y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x611800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x621000y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x703800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x713000y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x832600y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x165600y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x211600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x230000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x299000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x349600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x409400y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x487600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x506000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x515200y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x533600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x584200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x602600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x726800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x892400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x147200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x156400y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x234600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x271400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x289800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x299000y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x354200y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x432400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x469200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x487600y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x565800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x625600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x676200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x722200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x731400y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x809600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x828000y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x243800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x335800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x418600y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x460000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x478400y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x556600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x575000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x740600y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x782000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x791200y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x832600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x851000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x147200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x239200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x276000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x349600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x450800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x460000y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x506000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x524400y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x570400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x777400y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x823400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x860200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x147200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x156400y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x308200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x345000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x510600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x519800y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x565800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x575000y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x621000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x639400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x648600y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x694600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x805000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x823400y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x855600y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x110400y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x156400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x193200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x266800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x303600y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x349600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x418600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x437000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x446200y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x492200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x501400y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x547400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x584200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x602600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x685400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x731400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x749800y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x782000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x828000y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x82800y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x124200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x133400y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x211600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x220800y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x266800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x303600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x363400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x391000y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x469200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x506000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x542800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x602600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x621000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x630200y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x708400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x726800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x55200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x105800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x128800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x188600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x225400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x262200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x299000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x335800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x372600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x409400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x427800y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x469200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x487600y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x533600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x542800y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x588800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x598000y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x644000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x653200y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x699200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x749800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x805000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x92000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x101200y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x179400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x294400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x312800y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x358800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x464600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x483000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x492200y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x575000y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x653200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x731400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x740600y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x786600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x795800y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x837200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x855600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x892400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x133400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x170200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x207000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x243800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x345000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x381800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x400200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x450800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x460000y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x506000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x524400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x533600y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x611800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x630200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x639400y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x722200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x841800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x128800y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x207000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x243800y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x358800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x547400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x584200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x634800y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x680800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x690000y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x736000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x768200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x786600y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x832600y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x892400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x147200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x266800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x303600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x340400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x423200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x519800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x575000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x828000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x837200y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x220800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x239200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x248400y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x289800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x326600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x335800y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x409400y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x455400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x492200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x501400y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x616400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x634800y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x676200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x763600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x855600y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x147200y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x225400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x243800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x331200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x381800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x418600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x455400y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x501400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x519800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x529000y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x575000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x593400y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x639400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x763600y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x809600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x828000y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x165600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x216200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x253000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x427800y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x473800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x492200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x501400y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x547400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x565800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x616400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x749800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x786600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x823400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x133400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x170200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x207000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x368000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x386400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x395600y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x473800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x483000y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x561200y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x639400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x676200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x713000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x731400y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x851000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x110400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x119600y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x161000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x197800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x207000y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x253000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x289800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x308200y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x354200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x418600y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x501400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x519800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x529000y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x611800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x703800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x722200y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x768200y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x892400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x184000y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x262200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x299000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x335800y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x414000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x450800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x469200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x478400y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x561200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x579600y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x625600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x644000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x653200y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x699200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x708400y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x754400y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x147200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x193200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x266800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x276000y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x354200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x427800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x487600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x496800y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x515200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x565800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x575000y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x657800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x708400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x717600y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x892400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x128800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x211600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x220800y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x266800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x303600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x340400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x450800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x469200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x519800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x529000y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x575000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x593400y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x772800y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x818800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x828000y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x147200y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x225400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x262200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x335800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x418600y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x501400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x519800y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x653200y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x892400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x110400y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x151800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x188600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x266800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x303600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x312800y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x358800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x377200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x460000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x478400y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x524400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x542800y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x588800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x717600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x726800y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x128800y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x354200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x473800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x492200y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x575000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x648600y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x763600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x800400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x147200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x197800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x234600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x285200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x303600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x312800y870400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x358800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x377200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x542800y870400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x708400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x828000y870400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y870400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x151800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x188600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x207000y897600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x285200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x303600y897600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x400200y897600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x515200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x680800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x699200y897600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x786600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x805000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x814200y897600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x892400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x188600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x225400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x262200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x331200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x423200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x460000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x478400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x565800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x616400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x625600y924800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x703800y924800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x749800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x786600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x823400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x860200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y924800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x73600y952000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x105800y952000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x193200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x230000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x294400y952000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x335800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x450800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x501400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x851000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y952000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y979200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x55200y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x64400y1006400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x197800y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x234600y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x271400y1006400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x322000y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x340400y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x349600y1006400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x36800y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x220800y1033600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x271400y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x280600y1033600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y1060800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y1060800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__1__icv_in_design.pt.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__1__icv_in_design.pt.v deleted file mode 100644 index 0143dae..0000000 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__1__icv_in_design.pt.v +++ /dev/null @@ -1,2159 +0,0 @@ -// -// -// -// -// -// -module sb_0__1__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__59 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__58 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__57 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__56 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__55 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__54 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_127 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_27__53 ( .A ( mem_out[1] ) , - .X ( net_net_86 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_85 ( .A ( net_net_86 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__52 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__51 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__50 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__49 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__48 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__47 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__46 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size4_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__45 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__44 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__43 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__42 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size4_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__41 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__40 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size4_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__39 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_126 ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_65 ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size4_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_124 ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size5_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__38 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__37 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size5_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__36 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size5_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__35 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__34 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size5_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_63 ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( BUF_net_63 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_123 ( .A ( BUF_net_63 ) , - .X ( out[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__33 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__32 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__31 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__30 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__29 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__28 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__27 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_62 ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( BUF_net_62 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_122 ( .A ( BUF_net_62 ) , - .X ( out[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module sb_0__1_ ( prog_clk , chany_top_in , top_left_grid_pin_1_ , - chanx_right_in , right_bottom_grid_pin_34_ , right_bottom_grid_pin_35_ , - right_bottom_grid_pin_36_ , right_bottom_grid_pin_37_ , - right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ , - right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ , chany_bottom_in , - bottom_left_grid_pin_1_ , ccff_head , chany_top_out , chanx_right_out , - chany_bottom_out , ccff_tail , prog_clk__FEEDTHRU_1 ) ; -input [0:0] prog_clk ; -input [0:19] chany_top_in ; -input [0:0] top_left_grid_pin_1_ ; -input [0:19] chanx_right_in ; -input [0:0] right_bottom_grid_pin_34_ ; -input [0:0] right_bottom_grid_pin_35_ ; -input [0:0] right_bottom_grid_pin_36_ ; -input [0:0] right_bottom_grid_pin_37_ ; -input [0:0] right_bottom_grid_pin_38_ ; -input [0:0] right_bottom_grid_pin_39_ ; -input [0:0] right_bottom_grid_pin_40_ ; -input [0:0] right_bottom_grid_pin_41_ ; -input [0:19] chany_bottom_in ; -input [0:0] bottom_left_grid_pin_1_ ; -input [0:0] ccff_head ; -output [0:19] chany_top_out ; -output [0:19] chanx_right_out ; -output [0:19] chany_bottom_out ; -output [0:0] ccff_tail ; -output [0:0] prog_clk__FEEDTHRU_1 ; - -wire [0:2] mux_bottom_track_17_undriven_sram_inv ; -wire [0:2] mux_bottom_track_1_undriven_sram_inv ; -wire [0:2] mux_bottom_track_25_undriven_sram_inv ; -wire [0:1] mux_bottom_track_33_undriven_sram_inv ; -wire [0:2] mux_bottom_track_3_undriven_sram_inv ; -wire [0:2] mux_bottom_track_5_undriven_sram_inv ; -wire [0:2] mux_bottom_track_9_undriven_sram_inv ; -wire [0:2] mux_right_track_0_undriven_sram_inv ; -wire [0:2] mux_right_track_10_undriven_sram_inv ; -wire [0:2] mux_right_track_12_undriven_sram_inv ; -wire [0:2] mux_right_track_14_undriven_sram_inv ; -wire [0:1] mux_right_track_16_undriven_sram_inv ; -wire [0:1] mux_right_track_18_undriven_sram_inv ; -wire [0:1] mux_right_track_20_undriven_sram_inv ; -wire [0:1] mux_right_track_22_undriven_sram_inv ; -wire [0:2] mux_right_track_24_undriven_sram_inv ; -wire [0:1] mux_right_track_26_undriven_sram_inv ; -wire [0:1] mux_right_track_28_undriven_sram_inv ; -wire [0:2] mux_right_track_2_undriven_sram_inv ; -wire [0:1] mux_right_track_30_undriven_sram_inv ; -wire [0:1] mux_right_track_32_undriven_sram_inv ; -wire [0:1] mux_right_track_34_undriven_sram_inv ; -wire [0:1] mux_right_track_36_undriven_sram_inv ; -wire [0:2] mux_right_track_4_undriven_sram_inv ; -wire [0:2] mux_right_track_6_undriven_sram_inv ; -wire [0:2] mux_right_track_8_undriven_sram_inv ; -wire [0:2] mux_top_track_0_undriven_sram_inv ; -wire [0:2] mux_top_track_16_undriven_sram_inv ; -wire [0:2] mux_top_track_24_undriven_sram_inv ; -wire [0:2] mux_top_track_2_undriven_sram_inv ; -wire [0:2] mux_top_track_32_undriven_sram_inv ; -wire [0:2] mux_top_track_4_undriven_sram_inv ; -wire [0:2] mux_top_track_8_undriven_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_5_sram ; -wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; -wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:1] mux_tree_tapbuf_size3_2_sram ; -wire [0:1] mux_tree_tapbuf_size3_3_sram ; -wire [0:1] mux_tree_tapbuf_size3_4_sram ; -wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size4_0_sram ; -wire [0:2] mux_tree_tapbuf_size4_1_sram ; -wire [0:2] mux_tree_tapbuf_size4_2_sram ; -wire [0:2] mux_tree_tapbuf_size4_3_sram ; -wire [0:2] mux_tree_tapbuf_size4_4_sram ; -wire [0:2] mux_tree_tapbuf_size4_5_sram ; -wire [0:2] mux_tree_tapbuf_size4_6_sram ; -wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_6_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size5_0_sram ; -wire [0:2] mux_tree_tapbuf_size5_1_sram ; -wire [0:2] mux_tree_tapbuf_size5_2_sram ; -wire [0:2] mux_tree_tapbuf_size5_3_sram ; -wire [0:2] mux_tree_tapbuf_size5_4_sram ; -wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size6_1_sram ; -wire [0:2] mux_tree_tapbuf_size6_2_sram ; -wire [0:2] mux_tree_tapbuf_size6_3_sram ; -wire [0:2] mux_tree_tapbuf_size6_4_sram ; -wire [0:2] mux_tree_tapbuf_size6_5_sram ; -wire [0:2] mux_tree_tapbuf_size6_6_sram ; -wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_6_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size7_0_sram ; -wire [0:2] mux_tree_tapbuf_size7_1_sram ; -wire [0:2] mux_tree_tapbuf_size7_2_sram ; -wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; -// - -sb_0__1__mux_tree_tapbuf_size6_4 mux_top_track_0 ( - .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] , chanx_right_in[8] , - chanx_right_in[15] , chany_bottom_in[2] , chany_bottom_in[12] } ) , - .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_top_track_0_undriven_sram_inv ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_156 ) ) ; -sb_0__1__mux_tree_tapbuf_size6_5 mux_top_track_4 ( - .in ( { top_left_grid_pin_1_[0] , chanx_right_in[3] , chanx_right_in[10] , - chanx_right_in[17] , chany_bottom_in[5] , chany_bottom_in[14] } ) , - .sram ( mux_tree_tapbuf_size6_1_sram ) , - .sram_inv ( mux_top_track_4_undriven_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_156 ) ) ; -sb_0__1__mux_tree_tapbuf_size6 mux_top_track_8 ( - .in ( { top_left_grid_pin_1_[0] , chanx_right_in[4] , chanx_right_in[11] , - chanx_right_in[18] , chany_bottom_in[6] , chany_bottom_in[16] } ) , - .sram ( mux_tree_tapbuf_size6_2_sram ) , - .sram_inv ( mux_top_track_8_undriven_sram_inv ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_157 ) ) ; -sb_0__1__mux_tree_tapbuf_size6_3 mux_right_track_0 ( - .in ( { chany_top_in[2] , right_bottom_grid_pin_34_[0] , - right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , - right_bottom_grid_pin_40_[0] , chany_bottom_in[2] } ) , - .sram ( mux_tree_tapbuf_size6_3_sram ) , - .sram_inv ( mux_right_track_0_undriven_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_152 ) ) ; -sb_0__1__mux_tree_tapbuf_size6_0 mux_bottom_track_1 ( - .in ( { chany_top_in[2] , chany_top_in[12] , chanx_right_in[5] , - chanx_right_in[12] , chanx_right_in[19] , bottom_left_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size6_4_sram ) , - .sram_inv ( mux_bottom_track_1_undriven_sram_inv ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_155 ) ) ; -sb_0__1__mux_tree_tapbuf_size6_1 mux_bottom_track_5 ( - .in ( { chany_top_in[5] , chany_top_in[14] , chanx_right_in[3] , - chanx_right_in[10] , chanx_right_in[17] , bottom_left_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size6_5_sram ) , - .sram_inv ( mux_bottom_track_5_undriven_sram_inv ) , - .out ( { ropt_net_167 } ) , - .p0 ( optlc_net_151 ) ) ; -sb_0__1__mux_tree_tapbuf_size6_2 mux_bottom_track_9 ( - .in ( { chany_top_in[6] , chany_top_in[16] , chanx_right_in[2] , - chanx_right_in[9] , chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size6_6_sram ) , - .sram_inv ( mux_bottom_track_9_undriven_sram_inv ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_151 ) ) ; -sb_0__1__mux_tree_tapbuf_size6_mem_4 mem_top_track_0 ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size6_mem_5 mem_top_track_4 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size6_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_2_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size6_mem_3 mem_right_track_0 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_3_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_4_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size6_mem_1 mem_bottom_track_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_5_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size6_mem_2 mem_bottom_track_9 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_6_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size5 mux_top_track_2 ( - .in ( { chanx_right_in[2] , chanx_right_in[9] , chanx_right_in[16] , - chany_bottom_in[4] , chany_bottom_in[13] } ) , - .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_top_track_2_undriven_sram_inv ) , - .out ( { ropt_net_168 } ) , - .p0 ( optlc_net_156 ) ) ; -sb_0__1__mux_tree_tapbuf_size5_3 mux_top_track_16 ( - .in ( { chanx_right_in[5] , chanx_right_in[12] , chanx_right_in[19] , - chany_bottom_in[8] , chany_bottom_in[17] } ) , - .sram ( mux_tree_tapbuf_size5_1_sram ) , - .sram_inv ( mux_top_track_16_undriven_sram_inv ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_157 ) ) ; -sb_0__1__mux_tree_tapbuf_size5_2 mux_bottom_track_3 ( - .in ( { chany_top_in[4] , chany_top_in[13] , chanx_right_in[4] , - chanx_right_in[11] , chanx_right_in[18] } ) , - .sram ( mux_tree_tapbuf_size5_2_sram ) , - .sram_inv ( mux_bottom_track_3_undriven_sram_inv ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_155 ) ) ; -sb_0__1__mux_tree_tapbuf_size5_0 mux_bottom_track_17 ( - .in ( { chany_top_in[8] , chany_top_in[17] , chanx_right_in[1] , - chanx_right_in[8] , chanx_right_in[15] } ) , - .sram ( mux_tree_tapbuf_size5_3_sram ) , - .sram_inv ( mux_bottom_track_17_undriven_sram_inv ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_151 ) ) ; -sb_0__1__mux_tree_tapbuf_size5_1 mux_bottom_track_25 ( - .in ( { chany_top_in[9] , chany_top_in[18] , chanx_right_in[0] , - chanx_right_in[7] , chanx_right_in[14] } ) , - .sram ( mux_tree_tapbuf_size5_4_sram ) , - .sram_inv ( mux_bottom_track_25_undriven_sram_inv ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_154 ) ) ; -sb_0__1__mux_tree_tapbuf_size5_mem mem_top_track_2 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size5_mem_3 mem_top_track_16 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size5_mem_2 mem_bottom_track_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_2_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size5_mem_0 mem_bottom_track_17 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_3_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size5_mem_1 mem_bottom_track_25 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_4_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size4_5 mux_top_track_24 ( - .in ( { chanx_right_in[6] , chanx_right_in[13] , chany_bottom_in[9] , - chany_bottom_in[18] } ) , - .sram ( mux_tree_tapbuf_size4_0_sram ) , - .sram_inv ( mux_top_track_24_undriven_sram_inv ) , - .out ( { ropt_net_160 } ) , - .p0 ( optlc_net_153 ) ) ; -sb_0__1__mux_tree_tapbuf_size4 mux_top_track_32 ( - .in ( { chanx_right_in[0] , chanx_right_in[7] , chanx_right_in[14] , - chany_bottom_in[10] } ) , - .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_top_track_32_undriven_sram_inv ) , - .out ( chany_top_out[16] ) , .p0 ( optlc_net_153 ) ) ; -sb_0__1__mux_tree_tapbuf_size4_4 mux_right_track_8 ( - .in ( { chany_top_in[7] , chany_top_in[8] , right_bottom_grid_pin_34_[0] , - chany_bottom_in[8] } ) , - .sram ( mux_tree_tapbuf_size4_2_sram ) , - .sram_inv ( mux_right_track_8_undriven_sram_inv ) , - .out ( { ropt_net_163 } ) , - .p0 ( optlc_net_153 ) ) ; -sb_0__1__mux_tree_tapbuf_size4_0 mux_right_track_10 ( - .in ( { chany_top_in[9] , chany_top_in[11] , - right_bottom_grid_pin_35_[0] , chany_bottom_in[9] } ) , - .sram ( mux_tree_tapbuf_size4_3_sram ) , - .sram_inv ( mux_right_track_10_undriven_sram_inv ) , - .out ( chanx_right_out[5] ) , .p0 ( optlc_net_155 ) ) ; -sb_0__1__mux_tree_tapbuf_size4_1 mux_right_track_12 ( - .in ( { chany_top_in[10] , chany_top_in[15] , - right_bottom_grid_pin_36_[0] , chany_bottom_in[10] } ) , - .sram ( mux_tree_tapbuf_size4_4_sram ) , - .sram_inv ( mux_right_track_12_undriven_sram_inv ) , - .out ( chanx_right_out[6] ) , .p0 ( optlc_net_153 ) ) ; -sb_0__1__mux_tree_tapbuf_size4_2 mux_right_track_14 ( - .in ( { chany_top_in[12] , chany_top_in[19] , - right_bottom_grid_pin_37_[0] , chany_bottom_in[12] } ) , - .sram ( mux_tree_tapbuf_size4_5_sram ) , - .sram_inv ( mux_right_track_14_undriven_sram_inv ) , - .out ( { ropt_net_166 } ) , - .p0 ( optlc_net_155 ) ) ; -sb_0__1__mux_tree_tapbuf_size4_3 mux_right_track_24 ( - .in ( { chany_top_in[18] , right_bottom_grid_pin_34_[0] , - chany_bottom_in[18] , chany_bottom_in[19] } ) , - .sram ( mux_tree_tapbuf_size4_6_sram ) , - .sram_inv ( mux_right_track_24_undriven_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_154 ) ) ; -sb_0__1__mux_tree_tapbuf_size4_mem_5 mem_top_track_24 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size4_mem mem_top_track_32 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size4_mem_4 mem_right_track_8 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size4_mem_0 mem_right_track_10 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size4_mem_1 mem_right_track_12 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_4_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size4_mem_2 mem_right_track_14 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_5_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size4_mem_3 mem_right_track_24 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_6_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size7_0 mux_right_track_2 ( - .in ( { chany_top_in[0] , chany_top_in[4] , right_bottom_grid_pin_35_[0] , - right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , - right_bottom_grid_pin_41_[0] , chany_bottom_in[4] } ) , - .sram ( mux_tree_tapbuf_size7_0_sram ) , - .sram_inv ( mux_right_track_2_undriven_sram_inv ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_151 ) ) ; -sb_0__1__mux_tree_tapbuf_size7_1 mux_right_track_4 ( - .in ( { chany_top_in[1] , chany_top_in[5] , right_bottom_grid_pin_34_[0] , - right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , - right_bottom_grid_pin_40_[0] , chany_bottom_in[5] } ) , - .sram ( mux_tree_tapbuf_size7_1_sram ) , - .sram_inv ( mux_right_track_4_undriven_sram_inv ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_152 ) ) ; -sb_0__1__mux_tree_tapbuf_size7 mux_right_track_6 ( - .in ( { chany_top_in[3] , chany_top_in[6] , right_bottom_grid_pin_35_[0] , - right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , - right_bottom_grid_pin_41_[0] , chany_bottom_in[6] } ) , - .sram ( mux_tree_tapbuf_size7_2_sram ) , - .sram_inv ( mux_right_track_6_undriven_sram_inv ) , - .out ( chanx_right_out[3] ) , .p0 ( optlc_net_153 ) ) ; -sb_0__1__mux_tree_tapbuf_size7_mem_0 mem_right_track_2 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size7_mem_1 mem_right_track_4 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size7_mem mem_right_track_6 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size3_1 mux_right_track_16 ( - .in ( { chany_top_in[13] , right_bottom_grid_pin_38_[0] , - chany_bottom_in[13] } ) , - .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_right_track_16_undriven_sram_inv ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_151 ) ) ; -sb_0__1__mux_tree_tapbuf_size3_2 mux_right_track_18 ( - .in ( { chany_top_in[14] , right_bottom_grid_pin_39_[0] , - chany_bottom_in[14] } ) , - .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_right_track_18_undriven_sram_inv ) , - .out ( chanx_right_out[9] ) , .p0 ( optlc_net_152 ) ) ; -sb_0__1__mux_tree_tapbuf_size3_3 mux_right_track_20 ( - .in ( { chany_top_in[16] , right_bottom_grid_pin_40_[0] , - chany_bottom_in[16] } ) , - .sram ( mux_tree_tapbuf_size3_2_sram ) , - .sram_inv ( mux_right_track_20_undriven_sram_inv ) , - .out ( chanx_right_out[10] ) , .p0 ( optlc_net_152 ) ) ; -sb_0__1__mux_tree_tapbuf_size3 mux_right_track_22 ( - .in ( { chany_top_in[17] , right_bottom_grid_pin_41_[0] , - chany_bottom_in[17] } ) , - .sram ( mux_tree_tapbuf_size3_3_sram ) , - .sram_inv ( mux_right_track_22_undriven_sram_inv ) , - .out ( chanx_right_out[11] ) , .p0 ( optlc_net_154 ) ) ; -sb_0__1__mux_tree_tapbuf_size3_0 mux_bottom_track_33 ( - .in ( { chany_top_in[10] , chanx_right_in[6] , chanx_right_in[13] } ) , - .sram ( mux_tree_tapbuf_size3_4_sram ) , - .sram_inv ( mux_bottom_track_33_undriven_sram_inv ) , - .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_152 ) ) ; -sb_0__1__mux_tree_tapbuf_size3_mem_1 mem_right_track_16 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size3_mem_2 mem_right_track_18 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size3_mem_3 mem_right_track_20 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size3_mem mem_right_track_22 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_33 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , - .ccff_tail ( { ropt_net_179 } ) , - .mem_out ( mux_tree_tapbuf_size3_4_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size2_0 mux_right_track_26 ( - .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[15] } ) , - .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_right_track_26_undriven_sram_inv ) , - .out ( { ropt_net_173 } ) , - .p0 ( optlc_net_152 ) ) ; -sb_0__1__mux_tree_tapbuf_size2_1 mux_right_track_28 ( - .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[11] } ) , - .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_right_track_28_undriven_sram_inv ) , - .out ( chanx_right_out[14] ) , .p0 ( optlc_net_152 ) ) ; -sb_0__1__mux_tree_tapbuf_size2_2 mux_right_track_30 ( - .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[7] } ) , - .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_right_track_30_undriven_sram_inv ) , - .out ( chanx_right_out[15] ) , .p0 ( optlc_net_152 ) ) ; -sb_0__1__mux_tree_tapbuf_size2_3 mux_right_track_32 ( - .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[3] } ) , - .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_right_track_32_undriven_sram_inv ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_152 ) ) ; -sb_0__1__mux_tree_tapbuf_size2_4 mux_right_track_34 ( - .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[1] } ) , - .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_right_track_34_undriven_sram_inv ) , - .out ( chanx_right_out[17] ) , .p0 ( optlc_net_151 ) ) ; -sb_0__1__mux_tree_tapbuf_size2 mux_right_track_36 ( - .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[0] } ) , - .sram ( mux_tree_tapbuf_size2_5_sram ) , - .sram_inv ( mux_right_track_36_undriven_sram_inv ) , - .out ( chanx_right_out[18] ) , .p0 ( optlc_net_151 ) ) ; -sb_0__1__mux_tree_tapbuf_size2_mem_0 mem_right_track_26 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size2_mem_1 mem_right_track_28 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size2_mem_2 mem_right_track_30 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size2_mem_3 mem_right_track_32 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size2_mem_4 mem_right_track_34 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ; -sb_0__1__mux_tree_tapbuf_size2_mem mem_right_track_36 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_top_in[2] ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( ropt_net_182 ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_137 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_151 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_top_in[6] ) , - .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_141 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_152 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_144 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_153 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_top_in[10] ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_146 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_154 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , - .HI ( optlc_net_155 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chany_top_in[14] ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chany_top_in[16] ) , - .X ( ropt_net_180 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_151 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , - .HI ( optlc_net_156 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_153 ( .LO ( SYNOPSYS_UNCONNECTED_7 ) , - .HI ( optlc_net_157 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_814 ( .A ( ropt_net_183 ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__clkbuf_1 prog_clk_0__bip420 ( .A ( prog_clk[0] ) , - .X ( ctsbuf_net_1159 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_792 ( .A ( ropt_net_160 ) , - .X ( ropt_net_184 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chany_bottom_in[5] ) , - .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chany_bottom_in[6] ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chany_bottom_in[8] ) , - .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_184 ) , - .X ( chany_top_out[12] ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_345765 ( .A ( ctsbuf_net_1159 ) , - .X ( prog_clk__FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_816 ( .A ( ropt_net_185 ) , - .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( chany_top_in[18] ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chany_bottom_in[14] ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_25__24 ( .A ( chany_bottom_in[16] ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_817 ( .A ( ropt_net_186 ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_162 ) , - .X ( ropt_net_185 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_73 ( .A ( chany_top_in[4] ) , - .X ( BUF_net_73 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_818 ( .A ( ropt_net_187 ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_163 ) , - .X ( ropt_net_188 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_820 ( .A ( ropt_net_188 ) , - .X ( chanx_right_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_826 ( .A ( ropt_net_189 ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_827 ( .A ( ropt_net_190 ) , - .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_164 ) , - .X ( ropt_net_182 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( - .A ( right_bottom_grid_pin_41_[0] ) , .X ( ropt_net_191 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_166 ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_82 ( .A ( chany_bottom_in[10] ) , - .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_829 ( .A ( ropt_net_191 ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_192 ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_167 ) , - .X ( chany_bottom_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_168 ) , - .X ( chany_top_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_169 ) , - .X ( ropt_net_183 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_170 ) , - .X ( ropt_net_187 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_803 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_192 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_193 ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_804 ( .A ( chany_top_in[17] ) , - .X ( ropt_net_193 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( .A ( ropt_net_173 ) , - .X ( ropt_net_190 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_113 ( .A ( chany_top_in[8] ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_117 ( .A ( BUF_net_73 ) , - .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_118 ( .A ( chany_bottom_in[2] ) , - .X ( ropt_net_189 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_128 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_162 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( chany_top_in[9] ) , - .X ( ropt_net_186 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_131 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_164 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_133 ( .A ( chany_bottom_in[13] ) , - .X ( ropt_net_170 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_134 ( .A ( chany_bottom_in[18] ) , - .X ( ropt_net_169 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_807 ( .A ( chany_top_in[12] ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_808 ( - .A ( chany_bottom_in[17] ) , .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_809 ( .A ( chany_bottom_in[4] ) , - .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_810 ( - .A ( chany_bottom_in[12] ) , .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_179 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_180 ) , - .X ( chany_bottom_out[17] ) ) ; -endmodule - - diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__2__icv_in_design.fm.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__2__icv_in_design.fm.v deleted file mode 100644 index 25dc3c8..0000000 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__2__icv_in_design.fm.v +++ /dev/null @@ -1,1543 +0,0 @@ -// -// -// -// -// -// -module sb_0__2__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_24__40 ( .A ( mem_out[1] ) , - .X ( net_net_64 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_89 ( .A ( net_net_64 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__39 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__38 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__37 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__36 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__35 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__34 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__33 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__32 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__31 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__30 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__29 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__28 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__27 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__26 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__25 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__24 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__23 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__const1 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_0__2__const1 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__2__const1_22 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_0__2__const1_22 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__2__const1_21 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_0__2__const1_21 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__2__const1_20 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_0__2__const1_20 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__2__const1_19 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_0__2__const1_19 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__2__const1_18 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_0__2__const1_18 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__2__const1_17 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_0__2__const1_17 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__2__const1_16 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -sb_0__2__const1_16 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_0__2__const1_15 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_0__2__const1_15 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__2__const1_14 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -sb_0__2__const1_14 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_0__2__const1_13 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_0__2__const1_13 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__2__const1_12 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_0__2__const1_12 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__2__const1_11 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_0__2__const1_11 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__2__const1_10 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_0__2__const1_10 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__2__const1_9 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_0__2__const1_9 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_43 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_0__2__const1_8 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_0__2__const1_8 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__2__const1_7 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_0__2__const1_7 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__2__const1_6 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_0__2__const1_6 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__22 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__21 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__const1_5 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sb_0__2__const1_5 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_0__2__const1_4 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sb_0__2__const1_4 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__20 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__19 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__const1_3 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -sb_0__2__const1_3 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -endmodule - - -module sb_0__2__const1_2 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -sb_0__2__const1_2 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__18 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__17 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__const1_1 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sb_0__2__const1_1 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module sb_0__2__const1_0 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sb_0__2__const1_0 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module sb_0__2_ ( prog_clk , chanx_right_in , right_top_grid_pin_1_ , - right_bottom_grid_pin_34_ , right_bottom_grid_pin_35_ , - right_bottom_grid_pin_36_ , right_bottom_grid_pin_37_ , - right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ , - right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ , chany_bottom_in , - bottom_left_grid_pin_1_ , ccff_head , chanx_right_out , chany_bottom_out , - ccff_tail , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , SC_OUT_BOT ) ; -input [0:0] prog_clk ; -input [0:19] chanx_right_in ; -input [0:0] right_top_grid_pin_1_ ; -input [0:0] right_bottom_grid_pin_34_ ; -input [0:0] right_bottom_grid_pin_35_ ; -input [0:0] right_bottom_grid_pin_36_ ; -input [0:0] right_bottom_grid_pin_37_ ; -input [0:0] right_bottom_grid_pin_38_ ; -input [0:0] right_bottom_grid_pin_39_ ; -input [0:0] right_bottom_grid_pin_40_ ; -input [0:0] right_bottom_grid_pin_41_ ; -input [0:19] chany_bottom_in ; -input [0:0] bottom_left_grid_pin_1_ ; -input [0:0] ccff_head ; -output [0:19] chanx_right_out ; -output [0:19] chany_bottom_out ; -output [0:0] ccff_tail ; -input SC_IN_TOP ; -input SC_IN_BOT ; -output SC_OUT_TOP ; -output SC_OUT_BOT ; - -wire [0:1] mux_bottom_track_1_undriven_sram_inv ; -wire [0:1] mux_bottom_track_25_undriven_sram_inv ; -wire [0:1] mux_bottom_track_5_undriven_sram_inv ; -wire [0:1] mux_bottom_track_9_undriven_sram_inv ; -wire [0:2] mux_right_track_0_undriven_sram_inv ; -wire [0:1] mux_right_track_10_undriven_sram_inv ; -wire [0:1] mux_right_track_12_undriven_sram_inv ; -wire [0:1] mux_right_track_14_undriven_sram_inv ; -wire [0:1] mux_right_track_16_undriven_sram_inv ; -wire [0:1] mux_right_track_18_undriven_sram_inv ; -wire [0:1] mux_right_track_20_undriven_sram_inv ; -wire [0:1] mux_right_track_22_undriven_sram_inv ; -wire [0:1] mux_right_track_24_undriven_sram_inv ; -wire [0:1] mux_right_track_26_undriven_sram_inv ; -wire [0:1] mux_right_track_28_undriven_sram_inv ; -wire [0:2] mux_right_track_2_undriven_sram_inv ; -wire [0:1] mux_right_track_30_undriven_sram_inv ; -wire [0:1] mux_right_track_32_undriven_sram_inv ; -wire [0:1] mux_right_track_34_undriven_sram_inv ; -wire [0:1] mux_right_track_36_undriven_sram_inv ; -wire [0:1] mux_right_track_38_undriven_sram_inv ; -wire [0:2] mux_right_track_4_undriven_sram_inv ; -wire [0:2] mux_right_track_6_undriven_sram_inv ; -wire [0:1] mux_right_track_8_undriven_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_10_sram ; -wire [0:1] mux_tree_tapbuf_size2_11_sram ; -wire [0:1] mux_tree_tapbuf_size2_12_sram ; -wire [0:1] mux_tree_tapbuf_size2_13_sram ; -wire [0:1] mux_tree_tapbuf_size2_14_sram ; -wire [0:1] mux_tree_tapbuf_size2_15_sram ; -wire [0:1] mux_tree_tapbuf_size2_16_sram ; -wire [0:1] mux_tree_tapbuf_size2_17_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_5_sram ; -wire [0:1] mux_tree_tapbuf_size2_6_sram ; -wire [0:1] mux_tree_tapbuf_size2_7_sram ; -wire [0:1] mux_tree_tapbuf_size2_8_sram ; -wire [0:1] mux_tree_tapbuf_size2_9_sram ; -wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; -wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size5_0_sram ; -wire [0:2] mux_tree_tapbuf_size5_1_sram ; -wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size6_1_sram ; -wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; -// - -assign SC_IN_TOP = SC_IN_BOT ; - -sb_0__2__mux_tree_tapbuf_size6_0 mux_right_track_0 ( - .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] , - right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , - right_bottom_grid_pin_41_[0] , chany_bottom_in[18] } ) , - .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_right_track_0_undriven_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_114 ) ) ; -sb_0__2__mux_tree_tapbuf_size6 mux_right_track_4 ( - .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] , - right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , - right_bottom_grid_pin_41_[0] , chany_bottom_in[16] } ) , - .sram ( mux_tree_tapbuf_size6_1_sram ) , - .sram_inv ( mux_right_track_4_undriven_sram_inv ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_115 ) ) ; -sb_0__2__mux_tree_tapbuf_size6_mem_0 mem_right_track_0 ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size6_mem mem_right_track_4 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size5_0 mux_right_track_2 ( - .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , - right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , - chany_bottom_in[17] } ) , - .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_right_track_2_undriven_sram_inv ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_116 ) ) ; -sb_0__2__mux_tree_tapbuf_size5 mux_right_track_6 ( - .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , - right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , - chany_bottom_in[15] } ) , - .sram ( mux_tree_tapbuf_size5_1_sram ) , - .sram_inv ( mux_right_track_6_undriven_sram_inv ) , - .out ( chanx_right_out[3] ) , .p0 ( optlc_net_116 ) ) ; -sb_0__2__mux_tree_tapbuf_size5_mem_0 mem_right_track_2 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size5_mem mem_right_track_6 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size3 mux_right_track_8 ( - .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_41_[0] , - chany_bottom_in[14] } ) , - .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_right_track_8_undriven_sram_inv ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_116 ) ) ; -sb_0__2__mux_tree_tapbuf_size3_0 mux_right_track_24 ( - .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_41_[0] , - chany_bottom_in[6] } ) , - .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_right_track_24_undriven_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_116 ) ) ; -sb_0__2__mux_tree_tapbuf_size3_mem mem_right_track_8 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size3_mem_0 mem_right_track_24 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size2_4 mux_right_track_10 ( - .in ( { right_bottom_grid_pin_34_[0] , chany_bottom_in[13] } ) , - .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_right_track_10_undriven_sram_inv ) , - .out ( chanx_right_out[5] ) , .p0 ( optlc_net_116 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_5 mux_right_track_12 ( - .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[12] } ) , - .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_right_track_12_undriven_sram_inv ) , - .out ( chanx_right_out[6] ) , .p0 ( optlc_net_114 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_6 mux_right_track_14 ( - .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[11] } ) , - .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_right_track_14_undriven_sram_inv ) , - .out ( chanx_right_out[7] ) , .p0 ( optlc_net_115 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_7 mux_right_track_16 ( - .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[10] } ) , - .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_right_track_16_undriven_sram_inv ) , - .out ( { ropt_net_125 } ) , - .p0 ( optlc_net_117 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_8 mux_right_track_18 ( - .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[9] } ) , - .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_right_track_18_undriven_sram_inv ) , - .out ( chanx_right_out[9] ) , .p0 ( optlc_net_117 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_9 mux_right_track_20 ( - .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[8] } ) , - .sram ( mux_tree_tapbuf_size2_5_sram ) , - .sram_inv ( mux_right_track_20_undriven_sram_inv ) , - .out ( chanx_right_out[10] ) , .p0 ( optlc_net_114 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_10 mux_right_track_22 ( - .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[7] } ) , - .sram ( mux_tree_tapbuf_size2_6_sram ) , - .sram_inv ( mux_right_track_22_undriven_sram_inv ) , - .out ( chanx_right_out[11] ) , .p0 ( optlc_net_114 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_11 mux_right_track_26 ( - .in ( { right_bottom_grid_pin_34_[0] , chany_bottom_in[5] } ) , - .sram ( mux_tree_tapbuf_size2_7_sram ) , - .sram_inv ( mux_right_track_26_undriven_sram_inv ) , - .out ( chanx_right_out[13] ) , .p0 ( optlc_net_115 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_12 mux_right_track_28 ( - .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[4] } ) , - .sram ( mux_tree_tapbuf_size2_8_sram ) , - .sram_inv ( mux_right_track_28_undriven_sram_inv ) , - .out ( { ropt_net_122 } ) , - .p0 ( optlc_net_117 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_13 mux_right_track_30 ( - .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[3] } ) , - .sram ( mux_tree_tapbuf_size2_9_sram ) , - .sram_inv ( mux_right_track_30_undriven_sram_inv ) , - .out ( chanx_right_out[15] ) , .p0 ( optlc_net_117 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_14 mux_right_track_32 ( - .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[2] } ) , - .sram ( mux_tree_tapbuf_size2_10_sram ) , - .sram_inv ( mux_right_track_32_undriven_sram_inv ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_117 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_15 mux_right_track_34 ( - .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[1] } ) , - .sram ( mux_tree_tapbuf_size2_11_sram ) , - .sram_inv ( mux_right_track_34_undriven_sram_inv ) , - .out ( chanx_right_out[17] ) , .p0 ( optlc_net_117 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_16 mux_right_track_36 ( - .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[0] } ) , - .sram ( mux_tree_tapbuf_size2_12_sram ) , - .sram_inv ( mux_right_track_36_undriven_sram_inv ) , - .out ( chanx_right_out[18] ) , .p0 ( optlc_net_114 ) ) ; -sb_0__2__mux_tree_tapbuf_size2 mux_right_track_38 ( - .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[19] } ) , - .sram ( mux_tree_tapbuf_size2_13_sram ) , - .sram_inv ( mux_right_track_38_undriven_sram_inv ) , - .out ( chanx_right_out[19] ) , .p0 ( optlc_net_114 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_0 mux_bottom_track_1 ( - .in ( { chanx_right_in[18] , bottom_left_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size2_14_sram ) , - .sram_inv ( mux_bottom_track_1_undriven_sram_inv ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_114 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_2 mux_bottom_track_5 ( - .in ( { chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size2_15_sram ) , - .sram_inv ( mux_bottom_track_5_undriven_sram_inv ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_114 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_3 mux_bottom_track_9 ( - .in ( { chanx_right_in[14] , bottom_left_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size2_16_sram ) , - .sram_inv ( mux_bottom_track_9_undriven_sram_inv ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_114 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_1 mux_bottom_track_25 ( - .in ( { chanx_right_in[6] , bottom_left_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size2_17_sram ) , - .sram_inv ( mux_bottom_track_25_undriven_sram_inv ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_116 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_4 mem_right_track_10 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_5 mem_right_track_12 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_6 mem_right_track_14 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_7 mem_right_track_16 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_8 mem_right_track_18 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_9 mem_right_track_20 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_10 mem_right_track_22 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_11 mem_right_track_26 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_12 mem_right_track_28 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_13 mem_right_track_30 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_14 mem_right_track_32 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_15 mem_right_track_34 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_11_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_16 mem_right_track_36 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_12_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem mem_right_track_38 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_13_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_0 mem_bottom_track_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_14_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_2 mem_bottom_track_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_15_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_3 mem_bottom_track_9 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_16_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_1 mem_bottom_track_25 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_17_sram ) ) ; -sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_114 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_115 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_116 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_113 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_117 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_716 ( .A ( chanx_right_in[3] ) , - .X ( ropt_net_138 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_717 ( .A ( ropt_net_120 ) , - .X ( ropt_net_145 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_718 ( .A ( chanx_right_in[12] ) , - .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_122 ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_123 ) , - .X ( ropt_net_144 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( ropt_net_136 ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_137 ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_721 ( .A ( chanx_right_in[2] ) , - .X ( chany_bottom_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_138 ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_125 ) , - .X ( ropt_net_142 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_723 ( .A ( chanx_right_in[17] ) , - .X ( chany_bottom_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_724 ( .A ( ropt_net_127 ) , - .X ( ropt_net_140 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_17__16 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_120 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( chanx_right_in[19] ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( chanx_right_in[11] ) , - .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_741 ( .A ( ropt_net_139 ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_140 ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_744 ( .A ( ropt_net_141 ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_52 ( .A ( chanx_right_in[5] ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_746 ( .A ( ropt_net_142 ) , - .X ( chanx_right_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_747 ( .A ( ropt_net_143 ) , - .X ( chany_bottom_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_748 ( .A ( ropt_net_144 ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( .A ( ropt_net_145 ) , - .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_59 ( .A ( chanx_right_in[13] ) , - .X ( BUF_net_59 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_60 ( .A ( chanx_right_in[15] ) , - .X ( BUF_net_60 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( ropt_net_130 ) , - .X ( ropt_net_136 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( .A ( ropt_net_131 ) , - .X ( ropt_net_137 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( chanx_right_in[7] ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_133 ) , - .X ( ropt_net_141 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_86 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_143 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_88 ( .A ( BUF_net_59 ) , - .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_92 ( .A ( chanx_right_in[0] ) , - .X ( ropt_net_133 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_93 ( .A ( chanx_right_in[1] ) , - .X ( ropt_net_131 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_96 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_127 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_99 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_123 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_100 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_130 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_102 ( .A ( BUF_net_60 ) , - .X ( ropt_net_139 ) ) ; -endmodule - - diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__2__icv_in_design.lvs.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__2__icv_in_design.lvs.v deleted file mode 100644 index 6e9bee1..0000000 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__2__icv_in_design.lvs.v +++ /dev/null @@ -1,3466 +0,0 @@ -// -// -// -// -// -// -module sb_0__2__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_24__40 ( .A ( mem_out[1] ) , - .X ( net_net_64 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_89 ( .A ( net_net_64 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__39 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__38 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__37 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__36 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__35 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__34 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__33 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__32 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__31 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__30 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__29 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__28 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__27 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__26 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__25 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__24 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__23 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_43 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__22 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__21 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__20 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__19 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__18 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__17 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__2_ ( prog_clk , chanx_right_in , right_top_grid_pin_1_ , - right_bottom_grid_pin_34_ , right_bottom_grid_pin_35_ , - right_bottom_grid_pin_36_ , right_bottom_grid_pin_37_ , - right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ , - right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ , chany_bottom_in , - bottom_left_grid_pin_1_ , ccff_head , chanx_right_out , chany_bottom_out , - ccff_tail , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , SC_OUT_BOT , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:19] chanx_right_in ; -input [0:0] right_top_grid_pin_1_ ; -input [0:0] right_bottom_grid_pin_34_ ; -input [0:0] right_bottom_grid_pin_35_ ; -input [0:0] right_bottom_grid_pin_36_ ; -input [0:0] right_bottom_grid_pin_37_ ; -input [0:0] right_bottom_grid_pin_38_ ; -input [0:0] right_bottom_grid_pin_39_ ; -input [0:0] right_bottom_grid_pin_40_ ; -input [0:0] right_bottom_grid_pin_41_ ; -input [0:19] chany_bottom_in ; -input [0:0] bottom_left_grid_pin_1_ ; -input [0:0] ccff_head ; -output [0:19] chanx_right_out ; -output [0:19] chany_bottom_out ; -output [0:0] ccff_tail ; -input SC_IN_TOP ; -input SC_IN_BOT ; -output SC_OUT_TOP ; -output SC_OUT_BOT ; -input VDD ; -input VSS ; - -wire [0:1] mux_bottom_track_1_undriven_sram_inv ; -wire [0:1] mux_bottom_track_25_undriven_sram_inv ; -wire [0:1] mux_bottom_track_5_undriven_sram_inv ; -wire [0:1] mux_bottom_track_9_undriven_sram_inv ; -wire [0:2] mux_right_track_0_undriven_sram_inv ; -wire [0:1] mux_right_track_10_undriven_sram_inv ; -wire [0:1] mux_right_track_12_undriven_sram_inv ; -wire [0:1] mux_right_track_14_undriven_sram_inv ; -wire [0:1] mux_right_track_16_undriven_sram_inv ; -wire [0:1] mux_right_track_18_undriven_sram_inv ; -wire [0:1] mux_right_track_20_undriven_sram_inv ; -wire [0:1] mux_right_track_22_undriven_sram_inv ; -wire [0:1] mux_right_track_24_undriven_sram_inv ; -wire [0:1] mux_right_track_26_undriven_sram_inv ; -wire [0:1] mux_right_track_28_undriven_sram_inv ; -wire [0:2] mux_right_track_2_undriven_sram_inv ; -wire [0:1] mux_right_track_30_undriven_sram_inv ; -wire [0:1] mux_right_track_32_undriven_sram_inv ; -wire [0:1] mux_right_track_34_undriven_sram_inv ; -wire [0:1] mux_right_track_36_undriven_sram_inv ; -wire [0:1] mux_right_track_38_undriven_sram_inv ; -wire [0:2] mux_right_track_4_undriven_sram_inv ; -wire [0:2] mux_right_track_6_undriven_sram_inv ; -wire [0:1] mux_right_track_8_undriven_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_10_sram ; -wire [0:1] mux_tree_tapbuf_size2_11_sram ; -wire [0:1] mux_tree_tapbuf_size2_12_sram ; -wire [0:1] mux_tree_tapbuf_size2_13_sram ; -wire [0:1] mux_tree_tapbuf_size2_14_sram ; -wire [0:1] mux_tree_tapbuf_size2_15_sram ; -wire [0:1] mux_tree_tapbuf_size2_16_sram ; -wire [0:1] mux_tree_tapbuf_size2_17_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_5_sram ; -wire [0:1] mux_tree_tapbuf_size2_6_sram ; -wire [0:1] mux_tree_tapbuf_size2_7_sram ; -wire [0:1] mux_tree_tapbuf_size2_8_sram ; -wire [0:1] mux_tree_tapbuf_size2_9_sram ; -wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; -wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size5_0_sram ; -wire [0:2] mux_tree_tapbuf_size5_1_sram ; -wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size6_1_sram ; -wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; -supply1 VDD ; -supply0 VSS ; -// - -assign SC_IN_TOP = SC_IN_BOT ; - -sb_0__2__mux_tree_tapbuf_size6_0 mux_right_track_0 ( - .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] , - right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , - right_bottom_grid_pin_41_[0] , chany_bottom_in[18] } ) , - .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_right_track_0_undriven_sram_inv ) , - .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_114 ) ) ; -sb_0__2__mux_tree_tapbuf_size6 mux_right_track_4 ( - .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] , - right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , - right_bottom_grid_pin_41_[0] , chany_bottom_in[16] } ) , - .sram ( mux_tree_tapbuf_size6_1_sram ) , - .sram_inv ( mux_right_track_4_undriven_sram_inv ) , - .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_115 ) ) ; -sb_0__2__mux_tree_tapbuf_size6_mem_0 mem_right_track_0 ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__2__mux_tree_tapbuf_size6_mem mem_right_track_4 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__2__mux_tree_tapbuf_size5_0 mux_right_track_2 ( - .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , - right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , - chany_bottom_in[17] } ) , - .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_right_track_2_undriven_sram_inv ) , - .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_116 ) ) ; -sb_0__2__mux_tree_tapbuf_size5 mux_right_track_6 ( - .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , - right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , - chany_bottom_in[15] } ) , - .sram ( mux_tree_tapbuf_size5_1_sram ) , - .sram_inv ( mux_right_track_6_undriven_sram_inv ) , - .out ( chanx_right_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_116 ) ) ; -sb_0__2__mux_tree_tapbuf_size5_mem_0 mem_right_track_2 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__2__mux_tree_tapbuf_size5_mem mem_right_track_6 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__2__mux_tree_tapbuf_size3 mux_right_track_8 ( - .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_41_[0] , - chany_bottom_in[14] } ) , - .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_right_track_8_undriven_sram_inv ) , - .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_116 ) ) ; -sb_0__2__mux_tree_tapbuf_size3_0 mux_right_track_24 ( - .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_41_[0] , - chany_bottom_in[6] } ) , - .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_right_track_24_undriven_sram_inv ) , - .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_116 ) ) ; -sb_0__2__mux_tree_tapbuf_size3_mem mem_right_track_8 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__2__mux_tree_tapbuf_size3_mem_0 mem_right_track_24 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__2__mux_tree_tapbuf_size2_4 mux_right_track_10 ( - .in ( { right_bottom_grid_pin_34_[0] , chany_bottom_in[13] } ) , - .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_right_track_10_undriven_sram_inv ) , - .out ( chanx_right_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_116 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_5 mux_right_track_12 ( - .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[12] } ) , - .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_right_track_12_undriven_sram_inv ) , - .out ( chanx_right_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_114 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_6 mux_right_track_14 ( - .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[11] } ) , - .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_right_track_14_undriven_sram_inv ) , - .out ( chanx_right_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_115 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_7 mux_right_track_16 ( - .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[10] } ) , - .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_right_track_16_undriven_sram_inv ) , - .out ( { ropt_net_125 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_117 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_8 mux_right_track_18 ( - .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[9] } ) , - .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_right_track_18_undriven_sram_inv ) , - .out ( chanx_right_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_117 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_9 mux_right_track_20 ( - .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[8] } ) , - .sram ( mux_tree_tapbuf_size2_5_sram ) , - .sram_inv ( mux_right_track_20_undriven_sram_inv ) , - .out ( chanx_right_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_114 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_10 mux_right_track_22 ( - .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[7] } ) , - .sram ( mux_tree_tapbuf_size2_6_sram ) , - .sram_inv ( mux_right_track_22_undriven_sram_inv ) , - .out ( chanx_right_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_114 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_11 mux_right_track_26 ( - .in ( { right_bottom_grid_pin_34_[0] , chany_bottom_in[5] } ) , - .sram ( mux_tree_tapbuf_size2_7_sram ) , - .sram_inv ( mux_right_track_26_undriven_sram_inv ) , - .out ( chanx_right_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_115 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_12 mux_right_track_28 ( - .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[4] } ) , - .sram ( mux_tree_tapbuf_size2_8_sram ) , - .sram_inv ( mux_right_track_28_undriven_sram_inv ) , - .out ( { ropt_net_122 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_117 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_13 mux_right_track_30 ( - .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[3] } ) , - .sram ( mux_tree_tapbuf_size2_9_sram ) , - .sram_inv ( mux_right_track_30_undriven_sram_inv ) , - .out ( chanx_right_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_117 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_14 mux_right_track_32 ( - .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[2] } ) , - .sram ( mux_tree_tapbuf_size2_10_sram ) , - .sram_inv ( mux_right_track_32_undriven_sram_inv ) , - .out ( chanx_right_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_117 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_15 mux_right_track_34 ( - .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[1] } ) , - .sram ( mux_tree_tapbuf_size2_11_sram ) , - .sram_inv ( mux_right_track_34_undriven_sram_inv ) , - .out ( chanx_right_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_117 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_16 mux_right_track_36 ( - .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[0] } ) , - .sram ( mux_tree_tapbuf_size2_12_sram ) , - .sram_inv ( mux_right_track_36_undriven_sram_inv ) , - .out ( chanx_right_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_114 ) ) ; -sb_0__2__mux_tree_tapbuf_size2 mux_right_track_38 ( - .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[19] } ) , - .sram ( mux_tree_tapbuf_size2_13_sram ) , - .sram_inv ( mux_right_track_38_undriven_sram_inv ) , - .out ( chanx_right_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_114 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_0 mux_bottom_track_1 ( - .in ( { chanx_right_in[18] , bottom_left_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size2_14_sram ) , - .sram_inv ( mux_bottom_track_1_undriven_sram_inv ) , - .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_114 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_2 mux_bottom_track_5 ( - .in ( { chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size2_15_sram ) , - .sram_inv ( mux_bottom_track_5_undriven_sram_inv ) , - .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_114 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_3 mux_bottom_track_9 ( - .in ( { chanx_right_in[14] , bottom_left_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size2_16_sram ) , - .sram_inv ( mux_bottom_track_9_undriven_sram_inv ) , - .out ( chany_bottom_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_114 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_1 mux_bottom_track_25 ( - .in ( { chanx_right_in[6] , bottom_left_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size2_17_sram ) , - .sram_inv ( mux_bottom_track_25_undriven_sram_inv ) , - .out ( chany_bottom_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_116 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_4 mem_right_track_10 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_5 mem_right_track_12 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_6 mem_right_track_14 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_7 mem_right_track_16 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_8 mem_right_track_18 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_9 mem_right_track_20 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_10 mem_right_track_22 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_11 mem_right_track_26 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_12 mem_right_track_28 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_8_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_13 mem_right_track_30 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_9_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_14 mem_right_track_32 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_10_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_15 mem_right_track_34 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_11_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_16 mem_right_track_36 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_12_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem mem_right_track_38 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_13_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_0 mem_bottom_track_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_14_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_2 mem_bottom_track_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_15_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_3 mem_bottom_track_9 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_16_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_1 mem_bottom_track_25 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_17_sram ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1303 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1304 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1305 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1306 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1307 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1308 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1309 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1310 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1311 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1312 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1313 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1314 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1315 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1316 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1317 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1318 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1319 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1320 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1321 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1322 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1323 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1324 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1325 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1326 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1327 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1328 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1329 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1330 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1331 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1332 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1333 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1334 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1335 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1336 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1337 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1338 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_114 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_115 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_116 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_113 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_117 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_716 ( .A ( chanx_right_in[3] ) , - .X ( ropt_net_138 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_717 ( .A ( ropt_net_120 ) , - .X ( ropt_net_145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_718 ( .A ( chanx_right_in[12] ) , - .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_122 ) , - .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_123 ) , - .X ( ropt_net_144 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( ropt_net_136 ) , - .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_137 ) , - .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_721 ( .A ( chanx_right_in[2] ) , - .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_138 ) , - .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_125 ) , - .X ( ropt_net_142 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_723 ( .A ( chanx_right_in[17] ) , - .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_724 ( .A ( ropt_net_127 ) , - .X ( ropt_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_17__16 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_120 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( chanx_right_in[19] ) , - .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( chanx_right_in[11] ) , - .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_741 ( .A ( ropt_net_139 ) , - .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_140 ) , - .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_744 ( .A ( ropt_net_141 ) , - .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_52 ( .A ( chanx_right_in[5] ) , - .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_746 ( .A ( ropt_net_142 ) , - .X ( chanx_right_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_747 ( .A ( ropt_net_143 ) , - .X ( chany_bottom_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_748 ( .A ( ropt_net_144 ) , - .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( .A ( ropt_net_145 ) , - .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_59 ( .A ( chanx_right_in[13] ) , - .X ( BUF_net_59 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_60 ( .A ( chanx_right_in[15] ) , - .X ( BUF_net_60 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( ropt_net_130 ) , - .X ( ropt_net_136 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( .A ( ropt_net_131 ) , - .X ( ropt_net_137 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( chanx_right_in[7] ) , - .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_133 ) , - .X ( ropt_net_141 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_86 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_88 ( .A ( BUF_net_59 ) , - .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_92 ( .A ( chanx_right_in[0] ) , - .X ( ropt_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_93 ( .A ( chanx_right_in[1] ) , - .X ( ropt_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y0 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_96 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_99 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_100 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_130 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_102 ( .A ( BUF_net_60 ) , - .X ( ropt_net_139 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y0 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x248400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x437000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x36800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x138000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x174800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x211600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x230000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x239200y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x55200y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x216200y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x335800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x345000y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x110400y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x151800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x170200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x262200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x331200y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x588800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x708400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x782000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x818800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x855600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x165600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x184000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x234600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x271400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x308200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x345000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x754400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x805000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x841800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x851000y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x110400y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x188600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x225400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x303600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x322000y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x368000y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x414000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x450800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x469200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x703800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x722200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x731400y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x777400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x795800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x805000y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x73600y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x119600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x156400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x174800y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x285200y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x478400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x524400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x542800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x625600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x680800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x731400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x768200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x818800y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x864800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x901600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x92000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x174800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x211600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x262200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x299000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x308200y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x354200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x372600y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x418600y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x547400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x565800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x575000y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x621000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x703800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x722200y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x768200y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x846400y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x92000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x174800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x211600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x248400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x358800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x464600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x483000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x565800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x602600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x639400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x805000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x855600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x892400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x128800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x138000y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x184000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x234600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x271400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x368000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x533600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x552000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x561200y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x685400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x703800y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x745200y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x791200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x92000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x101200y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x142600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x161000y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x202400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x239200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x276000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x294400y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x340400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x414000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x432400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x483000y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x565800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x630200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x713000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x749800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x860200y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x892400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x110400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x156400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x193200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x211600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x220800y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x299000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x335800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x354200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x437000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x473800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x510600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x519800y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x598000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x616400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x625600y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x708400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x745200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x754400y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x800400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x846400y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x128800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x138000y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x363400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x538200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x625600y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x667000y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x713000y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x846400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x243800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x317400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x326600y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x460000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x496800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x515200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x524400y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x607200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x616400y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x699200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x717600y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x763600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x800400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x846400y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x202400y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x354200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x427800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x496800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x680800y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x805000y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x874000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x331200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x423200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x460000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x496800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x556600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x722200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x740600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x354200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x832600y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x892400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x211600y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x289800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x326600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x363400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x400200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x437000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x473800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x510600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x547400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x584200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x657800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x694600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x294400y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x464600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x483000y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x565800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x602600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x621000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x703800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x832600y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x864800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x901600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x220800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x239200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x248400y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x331200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x349600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x432400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x547400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x584200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x621000y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x639400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x648600y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x694600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x731400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x768200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x786600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x276000y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x354200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x427800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x446200y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x524400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x542800y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x809600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x818800y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x331200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x349600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x358800y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x437000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x473800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x510600y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x588800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x607200y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x671600y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x749800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x786600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x823400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x860200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x510600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x547400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x639400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x713000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x768200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x805000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x823400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x878600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x368000y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x409400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x446200y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x492200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x565800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x602600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x621000y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x809600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x828000y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x418600y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x460000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x496800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x515200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x524400y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x602600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x639400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x676200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x713000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x749800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x786600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x823400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x892400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x892400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x809600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x828000y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x878600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y870400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y870400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y897600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y897600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y924800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y924800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y952000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y952000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__2__icv_in_design.pt.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__2__icv_in_design.pt.v deleted file mode 100644 index b147b8a..0000000 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__2__icv_in_design.pt.v +++ /dev/null @@ -1,1375 +0,0 @@ -// -// -// -// -// -// -module sb_0__2__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_24__40 ( .A ( mem_out[1] ) , - .X ( net_net_64 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_89 ( .A ( net_net_64 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__39 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__38 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__37 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__36 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__35 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__34 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__33 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__32 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__31 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__30 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__29 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__28 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__27 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__26 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__25 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__24 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__23 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_43 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__22 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__21 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__20 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__19 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__18 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__17 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module sb_0__2__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module sb_0__2_ ( prog_clk , chanx_right_in , right_top_grid_pin_1_ , - right_bottom_grid_pin_34_ , right_bottom_grid_pin_35_ , - right_bottom_grid_pin_36_ , right_bottom_grid_pin_37_ , - right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ , - right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ , chany_bottom_in , - bottom_left_grid_pin_1_ , ccff_head , chanx_right_out , chany_bottom_out , - ccff_tail , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , SC_OUT_BOT ) ; -input [0:0] prog_clk ; -input [0:19] chanx_right_in ; -input [0:0] right_top_grid_pin_1_ ; -input [0:0] right_bottom_grid_pin_34_ ; -input [0:0] right_bottom_grid_pin_35_ ; -input [0:0] right_bottom_grid_pin_36_ ; -input [0:0] right_bottom_grid_pin_37_ ; -input [0:0] right_bottom_grid_pin_38_ ; -input [0:0] right_bottom_grid_pin_39_ ; -input [0:0] right_bottom_grid_pin_40_ ; -input [0:0] right_bottom_grid_pin_41_ ; -input [0:19] chany_bottom_in ; -input [0:0] bottom_left_grid_pin_1_ ; -input [0:0] ccff_head ; -output [0:19] chanx_right_out ; -output [0:19] chany_bottom_out ; -output [0:0] ccff_tail ; -input SC_IN_TOP ; -input SC_IN_BOT ; -output SC_OUT_TOP ; -output SC_OUT_BOT ; - -wire [0:1] mux_bottom_track_1_undriven_sram_inv ; -wire [0:1] mux_bottom_track_25_undriven_sram_inv ; -wire [0:1] mux_bottom_track_5_undriven_sram_inv ; -wire [0:1] mux_bottom_track_9_undriven_sram_inv ; -wire [0:2] mux_right_track_0_undriven_sram_inv ; -wire [0:1] mux_right_track_10_undriven_sram_inv ; -wire [0:1] mux_right_track_12_undriven_sram_inv ; -wire [0:1] mux_right_track_14_undriven_sram_inv ; -wire [0:1] mux_right_track_16_undriven_sram_inv ; -wire [0:1] mux_right_track_18_undriven_sram_inv ; -wire [0:1] mux_right_track_20_undriven_sram_inv ; -wire [0:1] mux_right_track_22_undriven_sram_inv ; -wire [0:1] mux_right_track_24_undriven_sram_inv ; -wire [0:1] mux_right_track_26_undriven_sram_inv ; -wire [0:1] mux_right_track_28_undriven_sram_inv ; -wire [0:2] mux_right_track_2_undriven_sram_inv ; -wire [0:1] mux_right_track_30_undriven_sram_inv ; -wire [0:1] mux_right_track_32_undriven_sram_inv ; -wire [0:1] mux_right_track_34_undriven_sram_inv ; -wire [0:1] mux_right_track_36_undriven_sram_inv ; -wire [0:1] mux_right_track_38_undriven_sram_inv ; -wire [0:2] mux_right_track_4_undriven_sram_inv ; -wire [0:2] mux_right_track_6_undriven_sram_inv ; -wire [0:1] mux_right_track_8_undriven_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_10_sram ; -wire [0:1] mux_tree_tapbuf_size2_11_sram ; -wire [0:1] mux_tree_tapbuf_size2_12_sram ; -wire [0:1] mux_tree_tapbuf_size2_13_sram ; -wire [0:1] mux_tree_tapbuf_size2_14_sram ; -wire [0:1] mux_tree_tapbuf_size2_15_sram ; -wire [0:1] mux_tree_tapbuf_size2_16_sram ; -wire [0:1] mux_tree_tapbuf_size2_17_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_5_sram ; -wire [0:1] mux_tree_tapbuf_size2_6_sram ; -wire [0:1] mux_tree_tapbuf_size2_7_sram ; -wire [0:1] mux_tree_tapbuf_size2_8_sram ; -wire [0:1] mux_tree_tapbuf_size2_9_sram ; -wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; -wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size5_0_sram ; -wire [0:2] mux_tree_tapbuf_size5_1_sram ; -wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size6_1_sram ; -wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; -// - -assign SC_IN_TOP = SC_IN_BOT ; - -sb_0__2__mux_tree_tapbuf_size6_0 mux_right_track_0 ( - .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] , - right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , - right_bottom_grid_pin_41_[0] , chany_bottom_in[18] } ) , - .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_right_track_0_undriven_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_114 ) ) ; -sb_0__2__mux_tree_tapbuf_size6 mux_right_track_4 ( - .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] , - right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , - right_bottom_grid_pin_41_[0] , chany_bottom_in[16] } ) , - .sram ( mux_tree_tapbuf_size6_1_sram ) , - .sram_inv ( mux_right_track_4_undriven_sram_inv ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_115 ) ) ; -sb_0__2__mux_tree_tapbuf_size6_mem_0 mem_right_track_0 ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size6_mem mem_right_track_4 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size5_0 mux_right_track_2 ( - .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , - right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , - chany_bottom_in[17] } ) , - .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_right_track_2_undriven_sram_inv ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_116 ) ) ; -sb_0__2__mux_tree_tapbuf_size5 mux_right_track_6 ( - .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , - right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , - chany_bottom_in[15] } ) , - .sram ( mux_tree_tapbuf_size5_1_sram ) , - .sram_inv ( mux_right_track_6_undriven_sram_inv ) , - .out ( chanx_right_out[3] ) , .p0 ( optlc_net_116 ) ) ; -sb_0__2__mux_tree_tapbuf_size5_mem_0 mem_right_track_2 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size5_mem mem_right_track_6 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size3 mux_right_track_8 ( - .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_41_[0] , - chany_bottom_in[14] } ) , - .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_right_track_8_undriven_sram_inv ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_116 ) ) ; -sb_0__2__mux_tree_tapbuf_size3_0 mux_right_track_24 ( - .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_41_[0] , - chany_bottom_in[6] } ) , - .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_right_track_24_undriven_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_116 ) ) ; -sb_0__2__mux_tree_tapbuf_size3_mem mem_right_track_8 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size3_mem_0 mem_right_track_24 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size2_4 mux_right_track_10 ( - .in ( { right_bottom_grid_pin_34_[0] , chany_bottom_in[13] } ) , - .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_right_track_10_undriven_sram_inv ) , - .out ( chanx_right_out[5] ) , .p0 ( optlc_net_116 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_5 mux_right_track_12 ( - .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[12] } ) , - .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_right_track_12_undriven_sram_inv ) , - .out ( chanx_right_out[6] ) , .p0 ( optlc_net_114 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_6 mux_right_track_14 ( - .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[11] } ) , - .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_right_track_14_undriven_sram_inv ) , - .out ( chanx_right_out[7] ) , .p0 ( optlc_net_115 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_7 mux_right_track_16 ( - .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[10] } ) , - .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_right_track_16_undriven_sram_inv ) , - .out ( { ropt_net_125 } ) , - .p0 ( optlc_net_117 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_8 mux_right_track_18 ( - .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[9] } ) , - .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_right_track_18_undriven_sram_inv ) , - .out ( chanx_right_out[9] ) , .p0 ( optlc_net_117 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_9 mux_right_track_20 ( - .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[8] } ) , - .sram ( mux_tree_tapbuf_size2_5_sram ) , - .sram_inv ( mux_right_track_20_undriven_sram_inv ) , - .out ( chanx_right_out[10] ) , .p0 ( optlc_net_114 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_10 mux_right_track_22 ( - .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[7] } ) , - .sram ( mux_tree_tapbuf_size2_6_sram ) , - .sram_inv ( mux_right_track_22_undriven_sram_inv ) , - .out ( chanx_right_out[11] ) , .p0 ( optlc_net_114 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_11 mux_right_track_26 ( - .in ( { right_bottom_grid_pin_34_[0] , chany_bottom_in[5] } ) , - .sram ( mux_tree_tapbuf_size2_7_sram ) , - .sram_inv ( mux_right_track_26_undriven_sram_inv ) , - .out ( chanx_right_out[13] ) , .p0 ( optlc_net_115 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_12 mux_right_track_28 ( - .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[4] } ) , - .sram ( mux_tree_tapbuf_size2_8_sram ) , - .sram_inv ( mux_right_track_28_undriven_sram_inv ) , - .out ( { ropt_net_122 } ) , - .p0 ( optlc_net_117 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_13 mux_right_track_30 ( - .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[3] } ) , - .sram ( mux_tree_tapbuf_size2_9_sram ) , - .sram_inv ( mux_right_track_30_undriven_sram_inv ) , - .out ( chanx_right_out[15] ) , .p0 ( optlc_net_117 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_14 mux_right_track_32 ( - .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[2] } ) , - .sram ( mux_tree_tapbuf_size2_10_sram ) , - .sram_inv ( mux_right_track_32_undriven_sram_inv ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_117 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_15 mux_right_track_34 ( - .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[1] } ) , - .sram ( mux_tree_tapbuf_size2_11_sram ) , - .sram_inv ( mux_right_track_34_undriven_sram_inv ) , - .out ( chanx_right_out[17] ) , .p0 ( optlc_net_117 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_16 mux_right_track_36 ( - .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[0] } ) , - .sram ( mux_tree_tapbuf_size2_12_sram ) , - .sram_inv ( mux_right_track_36_undriven_sram_inv ) , - .out ( chanx_right_out[18] ) , .p0 ( optlc_net_114 ) ) ; -sb_0__2__mux_tree_tapbuf_size2 mux_right_track_38 ( - .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[19] } ) , - .sram ( mux_tree_tapbuf_size2_13_sram ) , - .sram_inv ( mux_right_track_38_undriven_sram_inv ) , - .out ( chanx_right_out[19] ) , .p0 ( optlc_net_114 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_0 mux_bottom_track_1 ( - .in ( { chanx_right_in[18] , bottom_left_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size2_14_sram ) , - .sram_inv ( mux_bottom_track_1_undriven_sram_inv ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_114 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_2 mux_bottom_track_5 ( - .in ( { chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size2_15_sram ) , - .sram_inv ( mux_bottom_track_5_undriven_sram_inv ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_114 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_3 mux_bottom_track_9 ( - .in ( { chanx_right_in[14] , bottom_left_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size2_16_sram ) , - .sram_inv ( mux_bottom_track_9_undriven_sram_inv ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_114 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_1 mux_bottom_track_25 ( - .in ( { chanx_right_in[6] , bottom_left_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size2_17_sram ) , - .sram_inv ( mux_bottom_track_25_undriven_sram_inv ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_116 ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_4 mem_right_track_10 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_5 mem_right_track_12 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_6 mem_right_track_14 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_7 mem_right_track_16 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_8 mem_right_track_18 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_9 mem_right_track_20 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_10 mem_right_track_22 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_11 mem_right_track_26 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_12 mem_right_track_28 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_13 mem_right_track_30 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_14 mem_right_track_32 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_15 mem_right_track_34 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_11_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_16 mem_right_track_36 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_12_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem mem_right_track_38 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_13_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_0 mem_bottom_track_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_14_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_2 mem_bottom_track_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_15_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_3 mem_bottom_track_9 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_16_sram ) ) ; -sb_0__2__mux_tree_tapbuf_size2_mem_1 mem_bottom_track_25 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_17_sram ) ) ; -sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_114 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_115 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_116 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_113 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_117 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_716 ( .A ( chanx_right_in[3] ) , - .X ( ropt_net_138 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_717 ( .A ( ropt_net_120 ) , - .X ( ropt_net_145 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_718 ( .A ( chanx_right_in[12] ) , - .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_122 ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_123 ) , - .X ( ropt_net_144 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( ropt_net_136 ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_137 ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_721 ( .A ( chanx_right_in[2] ) , - .X ( chany_bottom_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_138 ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_125 ) , - .X ( ropt_net_142 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_723 ( .A ( chanx_right_in[17] ) , - .X ( chany_bottom_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_724 ( .A ( ropt_net_127 ) , - .X ( ropt_net_140 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_17__16 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_120 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( chanx_right_in[19] ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( chanx_right_in[11] ) , - .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_741 ( .A ( ropt_net_139 ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_140 ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_744 ( .A ( ropt_net_141 ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_52 ( .A ( chanx_right_in[5] ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_746 ( .A ( ropt_net_142 ) , - .X ( chanx_right_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_747 ( .A ( ropt_net_143 ) , - .X ( chany_bottom_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_748 ( .A ( ropt_net_144 ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( .A ( ropt_net_145 ) , - .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_59 ( .A ( chanx_right_in[13] ) , - .X ( BUF_net_59 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_60 ( .A ( chanx_right_in[15] ) , - .X ( BUF_net_60 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( ropt_net_130 ) , - .X ( ropt_net_136 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( .A ( ropt_net_131 ) , - .X ( ropt_net_137 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( chanx_right_in[7] ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_133 ) , - .X ( ropt_net_141 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_86 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_143 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_88 ( .A ( BUF_net_59 ) , - .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_92 ( .A ( chanx_right_in[0] ) , - .X ( ropt_net_133 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_93 ( .A ( chanx_right_in[1] ) , - .X ( ropt_net_131 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_96 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_127 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_99 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_123 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_100 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_130 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_102 ( .A ( BUF_net_60 ) , - .X ( ropt_net_139 ) ) ; -endmodule - - diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__0__icv_in_design.fm.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__0__icv_in_design.fm.v deleted file mode 100644 index adff765..0000000 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__0__icv_in_design.fm.v +++ /dev/null @@ -1,2302 +0,0 @@ -// -// -// -// -// -// -module sb_1__0__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__60 ( .A ( mem_out[2] ) , - .X ( net_net_84 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_84 ( .A ( net_net_84 ) , - .X ( net_net_83 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_103 ( .A ( net_net_83 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__59 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__const1 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -sb_1__0__const1 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -endmodule - - -module sb_1__0__const1_26 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -sb_1__0__const1_26 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__58 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__57 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__const1_25 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sb_1__0__const1_25 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module sb_1__0__const1_24 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sb_1__0__const1_24 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size11_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__56 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size11_mem ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__55 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__const1_23 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size11_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:10] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sb_1__0__const1_23 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[10] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -endmodule - - -module sb_1__0__const1_22 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size11 ( in , sram , sram_inv , out , p0 ) ; -input [0:10] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sb_1__0__const1_22 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[10] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__54 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__const1_21 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_1__0__const1_21 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__53 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size3_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__52 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size3_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__51 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__50 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__49 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__48 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__47 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__const1_20 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sb_1__0__const1_20 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_1__0__const1_19 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size3_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sb_1__0__const1_19 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_1__0__const1_18 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size3_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sb_1__0__const1_18 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_1__0__const1_17 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sb_1__0__const1_17 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_1__0__const1_16 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sb_1__0__const1_16 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_1__0__const1_15 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sb_1__0__const1_15 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_1__0__const1_14 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sb_1__0__const1_14 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__46 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__45 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__const1_13 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sb_1__0__const1_13 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -endmodule - - -module sb_1__0__const1_12 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sb_1__0__const1_12 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__44 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__43 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__42 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__41 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__40 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__39 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__38 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__37 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__36 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__const1_11 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sb_1__0__const1_11 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_1__0__const1_10 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sb_1__0__const1_10 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_1__0__const1_9 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sb_1__0__const1_9 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_1__0__const1_8 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sb_1__0__const1_8 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_1__0__const1_7 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sb_1__0__const1_7 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_1__0__const1_6 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sb_1__0__const1_6 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_1__0__const1_5 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sb_1__0__const1_5 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_1__0__const1_4 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_7 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sb_1__0__const1_4 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_1__0__const1_3 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sb_1__0__const1_3 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__35 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__34 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__33 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__const1_2 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sb_1__0__const1_2 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module sb_1__0__const1_1 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sb_1__0__const1_1 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module sb_1__0__const1_0 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sb_1__0__const1_0 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module sb_1__0_ ( prog_clk , chany_top_in , top_left_grid_pin_42_ , - top_left_grid_pin_43_ , top_left_grid_pin_44_ , top_left_grid_pin_45_ , - top_left_grid_pin_46_ , top_left_grid_pin_47_ , top_left_grid_pin_48_ , - top_left_grid_pin_49_ , chanx_right_in , right_bottom_grid_pin_1_ , - right_bottom_grid_pin_3_ , right_bottom_grid_pin_5_ , - right_bottom_grid_pin_7_ , right_bottom_grid_pin_9_ , - right_bottom_grid_pin_11_ , chanx_left_in , left_bottom_grid_pin_1_ , - left_bottom_grid_pin_3_ , left_bottom_grid_pin_5_ , - left_bottom_grid_pin_7_ , left_bottom_grid_pin_9_ , - left_bottom_grid_pin_11_ , ccff_head , chany_top_out , chanx_right_out , - chanx_left_out , ccff_tail , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , - SC_OUT_BOT , prog_clk__FEEDTHRU_1 , prog_clk__FEEDTHRU_2 ) ; -input [0:0] prog_clk ; -input [0:19] chany_top_in ; -input [0:0] top_left_grid_pin_42_ ; -input [0:0] top_left_grid_pin_43_ ; -input [0:0] top_left_grid_pin_44_ ; -input [0:0] top_left_grid_pin_45_ ; -input [0:0] top_left_grid_pin_46_ ; -input [0:0] top_left_grid_pin_47_ ; -input [0:0] top_left_grid_pin_48_ ; -input [0:0] top_left_grid_pin_49_ ; -input [0:19] chanx_right_in ; -input [0:0] right_bottom_grid_pin_1_ ; -input [0:0] right_bottom_grid_pin_3_ ; -input [0:0] right_bottom_grid_pin_5_ ; -input [0:0] right_bottom_grid_pin_7_ ; -input [0:0] right_bottom_grid_pin_9_ ; -input [0:0] right_bottom_grid_pin_11_ ; -input [0:19] chanx_left_in ; -input [0:0] left_bottom_grid_pin_1_ ; -input [0:0] left_bottom_grid_pin_3_ ; -input [0:0] left_bottom_grid_pin_5_ ; -input [0:0] left_bottom_grid_pin_7_ ; -input [0:0] left_bottom_grid_pin_9_ ; -input [0:0] left_bottom_grid_pin_11_ ; -input [0:0] ccff_head ; -output [0:19] chany_top_out ; -output [0:19] chanx_right_out ; -output [0:19] chanx_left_out ; -output [0:0] ccff_tail ; -input SC_IN_TOP ; -input SC_IN_BOT ; -output SC_OUT_TOP ; -output SC_OUT_BOT ; -output [0:0] prog_clk__FEEDTHRU_1 ; -output [0:0] prog_clk__FEEDTHRU_2 ; - -wire [0:2] mux_left_track_17_undriven_sram_inv ; -wire [0:3] mux_left_track_1_undriven_sram_inv ; -wire [0:2] mux_left_track_25_undriven_sram_inv ; -wire [0:2] mux_left_track_33_undriven_sram_inv ; -wire [0:2] mux_left_track_3_undriven_sram_inv ; -wire [0:3] mux_left_track_5_undriven_sram_inv ; -wire [0:2] mux_left_track_9_undriven_sram_inv ; -wire [0:2] mux_right_track_0_undriven_sram_inv ; -wire [0:2] mux_right_track_16_undriven_sram_inv ; -wire [0:2] mux_right_track_24_undriven_sram_inv ; -wire [0:3] mux_right_track_2_undriven_sram_inv ; -wire [0:2] mux_right_track_32_undriven_sram_inv ; -wire [0:3] mux_right_track_4_undriven_sram_inv ; -wire [0:2] mux_right_track_8_undriven_sram_inv ; -wire [0:3] mux_top_track_0_undriven_sram_inv ; -wire [0:2] mux_top_track_10_undriven_sram_inv ; -wire [0:1] mux_top_track_12_undriven_sram_inv ; -wire [0:1] mux_top_track_14_undriven_sram_inv ; -wire [0:1] mux_top_track_16_undriven_sram_inv ; -wire [0:1] mux_top_track_18_undriven_sram_inv ; -wire [0:1] mux_top_track_20_undriven_sram_inv ; -wire [0:1] mux_top_track_22_undriven_sram_inv ; -wire [0:1] mux_top_track_24_undriven_sram_inv ; -wire [0:2] mux_top_track_2_undriven_sram_inv ; -wire [0:1] mux_top_track_38_undriven_sram_inv ; -wire [0:2] mux_top_track_4_undriven_sram_inv ; -wire [0:2] mux_top_track_6_undriven_sram_inv ; -wire [0:2] mux_top_track_8_undriven_sram_inv ; -wire [0:3] mux_tree_tapbuf_size11_0_sram ; -wire [0:3] mux_tree_tapbuf_size11_1_sram ; -wire [0:0] mux_tree_tapbuf_size11_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size11_mem_1_ccff_tail ; -wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; -wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:1] mux_tree_tapbuf_size3_2_sram ; -wire [0:1] mux_tree_tapbuf_size3_3_sram ; -wire [0:1] mux_tree_tapbuf_size3_4_sram ; -wire [0:1] mux_tree_tapbuf_size3_5_sram ; -wire [0:1] mux_tree_tapbuf_size3_6_sram ; -wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size4_0_sram ; -wire [0:2] mux_tree_tapbuf_size4_1_sram ; -wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size5_0_sram ; -wire [0:2] mux_tree_tapbuf_size5_1_sram ; -wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size6_1_sram ; -wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size7_0_sram ; -wire [0:2] mux_tree_tapbuf_size7_1_sram ; -wire [0:2] mux_tree_tapbuf_size7_2_sram ; -wire [0:2] mux_tree_tapbuf_size7_3_sram ; -wire [0:2] mux_tree_tapbuf_size7_4_sram ; -wire [0:2] mux_tree_tapbuf_size7_5_sram ; -wire [0:2] mux_tree_tapbuf_size7_6_sram ; -wire [0:2] mux_tree_tapbuf_size7_7_sram ; -wire [0:2] mux_tree_tapbuf_size7_8_sram ; -wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_7_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_8_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:3] mux_tree_tapbuf_size8_2_sram ; -wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; -// - -assign SC_IN_TOP = SC_IN_BOT ; -assign prog_clk__FEEDTHRU_1[0] = prog_clk__FEEDTHRU_2[0] ; - -sb_1__0__mux_tree_tapbuf_size8 mux_top_track_0 ( - .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , - top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , - chanx_right_in[1] , chanx_right_in[2] , chanx_left_in[0] , - chanx_left_in[2] } ) , - .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_top_track_0_undriven_sram_inv ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_120 ) ) ; -sb_1__0__mux_tree_tapbuf_size8_1 mux_right_track_2 ( - .in ( { chany_top_in[0] , chany_top_in[7] , chany_top_in[14] , - right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_7_[0] , - right_bottom_grid_pin_11_[0] , chanx_left_in[4] , chanx_left_in[13] } ) , - .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_right_track_2_undriven_sram_inv ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_123 ) ) ; -sb_1__0__mux_tree_tapbuf_size8_0 mux_left_track_1 ( - .in ( { chany_top_in[0] , chany_top_in[7] , chany_top_in[14] , - chanx_right_in[2] , chanx_right_in[12] , left_bottom_grid_pin_1_[0] , - left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] } ) , - .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_left_track_1_undriven_sram_inv ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_120 ) ) ; -sb_1__0__mux_tree_tapbuf_size8_mem mem_top_track_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size8_mem_1 mem_right_track_2 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size8_mem_0 mem_left_track_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size7_6 mux_top_track_2 ( - .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , - top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , - chanx_right_in[3] , chanx_right_in[4] , chanx_left_in[4] } ) , - .sram ( mux_tree_tapbuf_size7_0_sram ) , - .sram_inv ( mux_top_track_2_undriven_sram_inv ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_121 ) ) ; -sb_1__0__mux_tree_tapbuf_size7_7 mux_top_track_4 ( - .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , - top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , - chanx_right_in[5] , chanx_right_in[7] , chanx_left_in[5] } ) , - .sram ( mux_tree_tapbuf_size7_1_sram ) , - .sram_inv ( mux_top_track_4_undriven_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_122 ) ) ; -sb_1__0__mux_tree_tapbuf_size7 mux_top_track_6 ( - .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , - top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , - chanx_right_in[6] , chanx_right_in[11] , chanx_left_in[6] } ) , - .sram ( mux_tree_tapbuf_size7_2_sram ) , - .sram_inv ( mux_top_track_6_undriven_sram_inv ) , - .out ( chany_top_out[3] ) , .p0 ( optlc_net_122 ) ) ; -sb_1__0__mux_tree_tapbuf_size7_3 mux_right_track_0 ( - .in ( { chany_top_in[6] , chany_top_in[13] , right_bottom_grid_pin_1_[0] , - right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] , - chanx_left_in[2] , chanx_left_in[12] } ) , - .sram ( mux_tree_tapbuf_size7_3_sram ) , - .sram_inv ( mux_right_track_0_undriven_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_121 ) ) ; -sb_1__0__mux_tree_tapbuf_size7_5 mux_right_track_8 ( - .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , - right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_9_[0] , - chanx_left_in[6] , chanx_left_in[16] } ) , - .sram ( mux_tree_tapbuf_size7_4_sram ) , - .sram_inv ( mux_right_track_8_undriven_sram_inv ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_124 ) ) ; -sb_1__0__mux_tree_tapbuf_size7_4 mux_right_track_16 ( - .in ( { chany_top_in[3] , chany_top_in[10] , chany_top_in[17] , - right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_11_[0] , - chanx_left_in[8] , chanx_left_in[17] } ) , - .sram ( mux_tree_tapbuf_size7_5_sram ) , - .sram_inv ( mux_right_track_16_undriven_sram_inv ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_124 ) ) ; -sb_1__0__mux_tree_tapbuf_size7_1 mux_left_track_3 ( - .in ( { chany_top_in[6] , chany_top_in[13] , chanx_right_in[4] , - chanx_right_in[13] , left_bottom_grid_pin_3_[0] , - left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] } ) , - .sram ( mux_tree_tapbuf_size7_6_sram ) , - .sram_inv ( mux_left_track_3_undriven_sram_inv ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_120 ) ) ; -sb_1__0__mux_tree_tapbuf_size7_2 mux_left_track_9 ( - .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , - chanx_right_in[6] , chanx_right_in[16] , left_bottom_grid_pin_1_[0] , - left_bottom_grid_pin_9_[0] } ) , - .sram ( mux_tree_tapbuf_size7_7_sram ) , - .sram_inv ( mux_left_track_9_undriven_sram_inv ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_120 ) ) ; -sb_1__0__mux_tree_tapbuf_size7_0 mux_left_track_17 ( - .in ( { chany_top_in[3] , chany_top_in[10] , chany_top_in[17] , - chanx_right_in[8] , chanx_right_in[17] , left_bottom_grid_pin_3_[0] , - left_bottom_grid_pin_11_[0] } ) , - .sram ( mux_tree_tapbuf_size7_8_sram ) , - .sram_inv ( mux_left_track_17_undriven_sram_inv ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_120 ) ) ; -sb_1__0__mux_tree_tapbuf_size7_mem_6 mem_top_track_2 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size7_mem_7 mem_top_track_4 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size7_mem mem_top_track_6 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size7_mem_3 mem_right_track_0 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_3_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size7_mem_5 mem_right_track_8 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size11_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_4_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size7_mem_4 mem_right_track_16 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_5_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size7_mem_1 mem_left_track_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_6_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size7_mem_2 mem_left_track_9 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size11_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_7_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size7_mem_0 mem_left_track_17 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_8_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_8_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size4 mux_top_track_8 ( - .in ( { top_left_grid_pin_42_[0] , chanx_right_in[8] , - chanx_right_in[15] , chanx_left_in[8] } ) , - .sram ( mux_tree_tapbuf_size4_0_sram ) , - .sram_inv ( mux_top_track_8_undriven_sram_inv ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_122 ) ) ; -sb_1__0__mux_tree_tapbuf_size4_0 mux_top_track_10 ( - .in ( { top_left_grid_pin_43_[0] , chanx_right_in[9] , - chanx_right_in[19] , chanx_left_in[9] } ) , - .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_top_track_10_undriven_sram_inv ) , - .out ( chany_top_out[5] ) , .p0 ( optlc_net_124 ) ) ; -sb_1__0__mux_tree_tapbuf_size4_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size4_mem_0 mem_top_track_10 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size3_0 mux_top_track_12 ( - .in ( { top_left_grid_pin_44_[0] , chanx_right_in[10] , - chanx_left_in[10] } ) , - .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_top_track_12_undriven_sram_inv ) , - .out ( chany_top_out[6] ) , .p0 ( optlc_net_121 ) ) ; -sb_1__0__mux_tree_tapbuf_size3_1 mux_top_track_14 ( - .in ( { top_left_grid_pin_45_[0] , chanx_right_in[12] , - chanx_left_in[12] } ) , - .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_top_track_14_undriven_sram_inv ) , - .out ( chany_top_out[7] ) , .p0 ( optlc_net_121 ) ) ; -sb_1__0__mux_tree_tapbuf_size3_2 mux_top_track_16 ( - .in ( { top_left_grid_pin_46_[0] , chanx_right_in[13] , - chanx_left_in[13] } ) , - .sram ( mux_tree_tapbuf_size3_2_sram ) , - .sram_inv ( mux_top_track_16_undriven_sram_inv ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_120 ) ) ; -sb_1__0__mux_tree_tapbuf_size3_3 mux_top_track_18 ( - .in ( { top_left_grid_pin_47_[0] , chanx_right_in[14] , - chanx_left_in[14] } ) , - .sram ( mux_tree_tapbuf_size3_3_sram ) , - .sram_inv ( mux_top_track_18_undriven_sram_inv ) , - .out ( chany_top_out[9] ) , .p0 ( optlc_net_121 ) ) ; -sb_1__0__mux_tree_tapbuf_size3_4 mux_top_track_20 ( - .in ( { top_left_grid_pin_48_[0] , chanx_right_in[16] , - chanx_left_in[16] } ) , - .sram ( mux_tree_tapbuf_size3_4_sram ) , - .sram_inv ( mux_top_track_20_undriven_sram_inv ) , - .out ( chany_top_out[10] ) , .p0 ( optlc_net_122 ) ) ; -sb_1__0__mux_tree_tapbuf_size3_5 mux_top_track_22 ( - .in ( { top_left_grid_pin_49_[0] , chanx_right_in[17] , - chanx_left_in[17] } ) , - .sram ( mux_tree_tapbuf_size3_5_sram ) , - .sram_inv ( mux_top_track_22_undriven_sram_inv ) , - .out ( chany_top_out[11] ) , .p0 ( optlc_net_122 ) ) ; -sb_1__0__mux_tree_tapbuf_size3 mux_top_track_24 ( - .in ( { top_left_grid_pin_42_[0] , chanx_right_in[18] , - chanx_left_in[18] } ) , - .sram ( mux_tree_tapbuf_size3_6_sram ) , - .sram_inv ( mux_top_track_24_undriven_sram_inv ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_121 ) ) ; -sb_1__0__mux_tree_tapbuf_size3_mem_0 mem_top_track_12 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size3_mem_1 mem_top_track_14 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size3_mem_2 mem_top_track_16 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size3_mem_3 mem_top_track_18 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size3_mem_4 mem_top_track_20 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_4_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size3_mem_5 mem_top_track_22 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_5_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size3_mem mem_top_track_24 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_6_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size2 mux_top_track_38 ( - .in ( { chanx_right_in[0] , chanx_left_in[1] } ) , - .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_top_track_38_undriven_sram_inv ) , - .out ( chany_top_out[19] ) , .p0 ( optlc_net_121 ) ) ; -sb_1__0__mux_tree_tapbuf_size2_mem mem_top_track_38 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size11 mux_right_track_4 ( - .in ( { chany_top_in[1] , chany_top_in[8] , chany_top_in[15] , - right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_3_[0] , - right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_7_[0] , - right_bottom_grid_pin_9_[0] , right_bottom_grid_pin_11_[0] , - chanx_left_in[5] , chanx_left_in[14] } ) , - .sram ( mux_tree_tapbuf_size11_0_sram ) , - .sram_inv ( mux_right_track_4_undriven_sram_inv ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_123 ) ) ; -sb_1__0__mux_tree_tapbuf_size11_0 mux_left_track_5 ( - .in ( { chany_top_in[5] , chany_top_in[12] , chany_top_in[19] , - chanx_right_in[5] , chanx_right_in[14] , left_bottom_grid_pin_1_[0] , - left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_5_[0] , - left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_9_[0] , - left_bottom_grid_pin_11_[0] } ) , - .sram ( mux_tree_tapbuf_size11_1_sram ) , - .sram_inv ( mux_left_track_5_undriven_sram_inv ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_120 ) ) ; -sb_1__0__mux_tree_tapbuf_size11_mem mem_right_track_4 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size11_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size11_0_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size11_mem_0 mem_left_track_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size11_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size11_1_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size6 mux_right_track_24 ( - .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , - right_bottom_grid_pin_5_[0] , chanx_left_in[9] , chanx_left_in[18] } ) , - .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_right_track_24_undriven_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_124 ) ) ; -sb_1__0__mux_tree_tapbuf_size6_0 mux_left_track_25 ( - .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , - chanx_right_in[9] , chanx_right_in[18] , left_bottom_grid_pin_5_[0] } ) , - .sram ( mux_tree_tapbuf_size6_1_sram ) , - .sram_inv ( mux_left_track_25_undriven_sram_inv ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_122 ) ) ; -sb_1__0__mux_tree_tapbuf_size6_mem mem_right_track_24 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size6_mem_0 mem_left_track_25 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_8_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size5 mux_right_track_32 ( - .in ( { chany_top_in[5] , chany_top_in[12] , chany_top_in[19] , - right_bottom_grid_pin_7_[0] , chanx_left_in[10] } ) , - .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_right_track_32_undriven_sram_inv ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_121 ) ) ; -sb_1__0__mux_tree_tapbuf_size5_0 mux_left_track_33 ( - .in ( { chany_top_in[1] , chany_top_in[8] , chany_top_in[15] , - chanx_right_in[10] , left_bottom_grid_pin_7_[0] } ) , - .sram ( mux_tree_tapbuf_size5_1_sram ) , - .sram_inv ( mux_left_track_33_undriven_sram_inv ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_120 ) ) ; -sb_1__0__mux_tree_tapbuf_size5_mem mem_right_track_32 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size5_mem_0 mem_left_track_33 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .ccff_tail ( { ropt_net_147 } ) , - .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ; -sky130_fd_sc_hd__conb_1 optlc_114 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_120 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chanx_right_in[2] ) , - .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_145 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__3 ( .A ( chanx_right_in[5] ) , - .X ( ropt_net_154 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_121 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_161 ) , - .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_122 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_121 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_123 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__8 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_158 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_162 ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__10 ( .A ( chanx_right_in[14] ) , - .X ( ropt_net_151 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_123 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , - .HI ( optlc_net_124 ) ) ; -sky130_fd_sc_hd__clkbuf_1 prog_clk_0__bip390 ( .A ( prog_clk[0] ) , - .X ( prog_clk__FEEDTHRU_2_0_0 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( .A ( ropt_net_129 ) , - .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chanx_left_in[2] ) , - .X ( ropt_net_152 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_165 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( chanx_left_in[19] ) , - .X ( ropt_net_169 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chanx_left_in[5] ) , - .X ( ropt_net_150 ) ) ; -sky130_fd_sc_hd__buf_8 cts_buf_368758 ( .A ( prog_clk__FEEDTHRU_2_0_0 ) , - .X ( prog_clk__FEEDTHRU_2[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_784 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_179 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_785 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_175 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__21 ( .A ( chanx_left_in[9] ) , - .X ( ropt_net_148 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chanx_left_in[10] ) , - .X ( ropt_net_155 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_134 ) , - .X ( ropt_net_171 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_787 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_176 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_788 ( .A ( chanx_left_in[12] ) , - .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_137 ) , - .X ( ropt_net_163 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( chanx_right_in[18] ) , - .X ( ropt_net_174 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_821 ( .A ( ropt_net_163 ) , - .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_822 ( .A ( ropt_net_164 ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( chanx_left_in[13] ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( chanx_left_in[16] ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_129 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( chanx_right_in[6] ) , - .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_178 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_823 ( .A ( ropt_net_165 ) , - .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_166 ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_825 ( .A ( ropt_net_167 ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_826 ( .A ( ropt_net_168 ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_70 ( .A ( chanx_left_in[3] ) , - .X ( ropt_net_143 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_71 ( .A ( chanx_left_in[4] ) , - .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_72 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_157 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_73 ( .A ( chanx_left_in[7] ) , - .X ( ropt_net_160 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_74 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_156 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_75 ( .A ( chanx_left_in[11] ) , - .X ( ropt_net_137 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_827 ( .A ( ropt_net_169 ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_170 ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_78 ( .A ( chanx_left_in[14] ) , - .X ( ropt_net_159 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_79 ( .A ( chanx_left_in[15] ) , - .X ( ropt_net_146 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_143 ) , - .X ( ropt_net_164 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_830 ( .A ( ropt_net_171 ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_832 ( .A ( ropt_net_172 ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_177 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( ropt_net_145 ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_146 ) , - .X ( ropt_net_167 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_147 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_148 ) , - .X ( ropt_net_172 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_149 ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_150 ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_833 ( .A ( ropt_net_173 ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_99 ( .A ( top_left_grid_pin_43_[0] ) , - .X ( ropt_net_149 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_837 ( .A ( ropt_net_174 ) , - .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_151 ) , - .X ( ropt_net_161 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_105 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_153 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_152 ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_107 ( .A ( chanx_right_in[16] ) , - .X ( ropt_net_134 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_153 ) , - .X ( ropt_net_162 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_154 ) , - .X ( ropt_net_166 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_155 ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_156 ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_157 ) , - .X ( ropt_net_173 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_810 ( .A ( ropt_net_158 ) , - .X ( ropt_net_170 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_159 ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_160 ) , - .X ( ropt_net_168 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_838 ( .A ( ropt_net_175 ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_839 ( .A ( ropt_net_176 ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_840 ( .A ( ropt_net_177 ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_841 ( .A ( ropt_net_178 ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_842 ( .A ( ropt_net_179 ) , - .X ( chanx_right_out[19] ) ) ; -endmodule - - diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__0__icv_in_design.lvs.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__0__icv_in_design.lvs.v deleted file mode 100644 index feaa59e..0000000 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__0__icv_in_design.lvs.v +++ /dev/null @@ -1,4507 +0,0 @@ -// -// -// -// -// -// -module sb_1__0__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__60 ( .A ( mem_out[2] ) , - .X ( net_net_84 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_84 ( .A ( net_net_84 ) , - .X ( net_net_83 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_103 ( .A ( net_net_83 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__59 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__58 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__57 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size11_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__56 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size11_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__55 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size11_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:10] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[10] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size11 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:10] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[10] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__54 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__53 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size3_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__52 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size3_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__51 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__50 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__49 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__48 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__47 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size3_5 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size3_4 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__46 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__45 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__44 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__43 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__42 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__41 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__40 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__39 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__38 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__37 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__36 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_7 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_6 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__35 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__34 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__33 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__0_ ( prog_clk , chany_top_in , top_left_grid_pin_42_ , - top_left_grid_pin_43_ , top_left_grid_pin_44_ , top_left_grid_pin_45_ , - top_left_grid_pin_46_ , top_left_grid_pin_47_ , top_left_grid_pin_48_ , - top_left_grid_pin_49_ , chanx_right_in , right_bottom_grid_pin_1_ , - right_bottom_grid_pin_3_ , right_bottom_grid_pin_5_ , - right_bottom_grid_pin_7_ , right_bottom_grid_pin_9_ , - right_bottom_grid_pin_11_ , chanx_left_in , left_bottom_grid_pin_1_ , - left_bottom_grid_pin_3_ , left_bottom_grid_pin_5_ , - left_bottom_grid_pin_7_ , left_bottom_grid_pin_9_ , - left_bottom_grid_pin_11_ , ccff_head , chany_top_out , chanx_right_out , - chanx_left_out , ccff_tail , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , - SC_OUT_BOT , VDD , VSS , prog_clk__FEEDTHRU_1 , prog_clk__FEEDTHRU_2 ) ; -input [0:0] prog_clk ; -input [0:19] chany_top_in ; -input [0:0] top_left_grid_pin_42_ ; -input [0:0] top_left_grid_pin_43_ ; -input [0:0] top_left_grid_pin_44_ ; -input [0:0] top_left_grid_pin_45_ ; -input [0:0] top_left_grid_pin_46_ ; -input [0:0] top_left_grid_pin_47_ ; -input [0:0] top_left_grid_pin_48_ ; -input [0:0] top_left_grid_pin_49_ ; -input [0:19] chanx_right_in ; -input [0:0] right_bottom_grid_pin_1_ ; -input [0:0] right_bottom_grid_pin_3_ ; -input [0:0] right_bottom_grid_pin_5_ ; -input [0:0] right_bottom_grid_pin_7_ ; -input [0:0] right_bottom_grid_pin_9_ ; -input [0:0] right_bottom_grid_pin_11_ ; -input [0:19] chanx_left_in ; -input [0:0] left_bottom_grid_pin_1_ ; -input [0:0] left_bottom_grid_pin_3_ ; -input [0:0] left_bottom_grid_pin_5_ ; -input [0:0] left_bottom_grid_pin_7_ ; -input [0:0] left_bottom_grid_pin_9_ ; -input [0:0] left_bottom_grid_pin_11_ ; -input [0:0] ccff_head ; -output [0:19] chany_top_out ; -output [0:19] chanx_right_out ; -output [0:19] chanx_left_out ; -output [0:0] ccff_tail ; -input SC_IN_TOP ; -input SC_IN_BOT ; -output SC_OUT_TOP ; -output SC_OUT_BOT ; -input VDD ; -input VSS ; -output [0:0] prog_clk__FEEDTHRU_1 ; -output [0:0] prog_clk__FEEDTHRU_2 ; - -wire [0:2] mux_left_track_17_undriven_sram_inv ; -wire [0:3] mux_left_track_1_undriven_sram_inv ; -wire [0:2] mux_left_track_25_undriven_sram_inv ; -wire [0:2] mux_left_track_33_undriven_sram_inv ; -wire [0:2] mux_left_track_3_undriven_sram_inv ; -wire [0:3] mux_left_track_5_undriven_sram_inv ; -wire [0:2] mux_left_track_9_undriven_sram_inv ; -wire [0:2] mux_right_track_0_undriven_sram_inv ; -wire [0:2] mux_right_track_16_undriven_sram_inv ; -wire [0:2] mux_right_track_24_undriven_sram_inv ; -wire [0:3] mux_right_track_2_undriven_sram_inv ; -wire [0:2] mux_right_track_32_undriven_sram_inv ; -wire [0:3] mux_right_track_4_undriven_sram_inv ; -wire [0:2] mux_right_track_8_undriven_sram_inv ; -wire [0:3] mux_top_track_0_undriven_sram_inv ; -wire [0:2] mux_top_track_10_undriven_sram_inv ; -wire [0:1] mux_top_track_12_undriven_sram_inv ; -wire [0:1] mux_top_track_14_undriven_sram_inv ; -wire [0:1] mux_top_track_16_undriven_sram_inv ; -wire [0:1] mux_top_track_18_undriven_sram_inv ; -wire [0:1] mux_top_track_20_undriven_sram_inv ; -wire [0:1] mux_top_track_22_undriven_sram_inv ; -wire [0:1] mux_top_track_24_undriven_sram_inv ; -wire [0:2] mux_top_track_2_undriven_sram_inv ; -wire [0:1] mux_top_track_38_undriven_sram_inv ; -wire [0:2] mux_top_track_4_undriven_sram_inv ; -wire [0:2] mux_top_track_6_undriven_sram_inv ; -wire [0:2] mux_top_track_8_undriven_sram_inv ; -wire [0:3] mux_tree_tapbuf_size11_0_sram ; -wire [0:3] mux_tree_tapbuf_size11_1_sram ; -wire [0:0] mux_tree_tapbuf_size11_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size11_mem_1_ccff_tail ; -wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; -wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:1] mux_tree_tapbuf_size3_2_sram ; -wire [0:1] mux_tree_tapbuf_size3_3_sram ; -wire [0:1] mux_tree_tapbuf_size3_4_sram ; -wire [0:1] mux_tree_tapbuf_size3_5_sram ; -wire [0:1] mux_tree_tapbuf_size3_6_sram ; -wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size4_0_sram ; -wire [0:2] mux_tree_tapbuf_size4_1_sram ; -wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size5_0_sram ; -wire [0:2] mux_tree_tapbuf_size5_1_sram ; -wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size6_1_sram ; -wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size7_0_sram ; -wire [0:2] mux_tree_tapbuf_size7_1_sram ; -wire [0:2] mux_tree_tapbuf_size7_2_sram ; -wire [0:2] mux_tree_tapbuf_size7_3_sram ; -wire [0:2] mux_tree_tapbuf_size7_4_sram ; -wire [0:2] mux_tree_tapbuf_size7_5_sram ; -wire [0:2] mux_tree_tapbuf_size7_6_sram ; -wire [0:2] mux_tree_tapbuf_size7_7_sram ; -wire [0:2] mux_tree_tapbuf_size7_8_sram ; -wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_7_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_8_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:3] mux_tree_tapbuf_size8_2_sram ; -wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; -supply1 VDD ; -supply0 VSS ; -// - -assign SC_IN_TOP = SC_IN_BOT ; -assign prog_clk__FEEDTHRU_1[0] = prog_clk__FEEDTHRU_2[0] ; - -sb_1__0__mux_tree_tapbuf_size8 mux_top_track_0 ( - .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , - top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , - chanx_right_in[1] , chanx_right_in[2] , chanx_left_in[0] , - chanx_left_in[2] } ) , - .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_top_track_0_undriven_sram_inv ) , - .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_120 ) ) ; -sb_1__0__mux_tree_tapbuf_size8_1 mux_right_track_2 ( - .in ( { chany_top_in[0] , chany_top_in[7] , chany_top_in[14] , - right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_7_[0] , - right_bottom_grid_pin_11_[0] , chanx_left_in[4] , chanx_left_in[13] } ) , - .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_right_track_2_undriven_sram_inv ) , - .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_123 ) ) ; -sb_1__0__mux_tree_tapbuf_size8_0 mux_left_track_1 ( - .in ( { chany_top_in[0] , chany_top_in[7] , chany_top_in[14] , - chanx_right_in[2] , chanx_right_in[12] , left_bottom_grid_pin_1_[0] , - left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] } ) , - .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_left_track_1_undriven_sram_inv ) , - .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_120 ) ) ; -sb_1__0__mux_tree_tapbuf_size8_mem mem_top_track_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__0__mux_tree_tapbuf_size8_mem_1 mem_right_track_2 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__0__mux_tree_tapbuf_size8_mem_0 mem_left_track_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__0__mux_tree_tapbuf_size7_6 mux_top_track_2 ( - .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , - top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , - chanx_right_in[3] , chanx_right_in[4] , chanx_left_in[4] } ) , - .sram ( mux_tree_tapbuf_size7_0_sram ) , - .sram_inv ( mux_top_track_2_undriven_sram_inv ) , - .out ( chany_top_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_121 ) ) ; -sb_1__0__mux_tree_tapbuf_size7_7 mux_top_track_4 ( - .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , - top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , - chanx_right_in[5] , chanx_right_in[7] , chanx_left_in[5] } ) , - .sram ( mux_tree_tapbuf_size7_1_sram ) , - .sram_inv ( mux_top_track_4_undriven_sram_inv ) , - .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_122 ) ) ; -sb_1__0__mux_tree_tapbuf_size7 mux_top_track_6 ( - .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , - top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , - chanx_right_in[6] , chanx_right_in[11] , chanx_left_in[6] } ) , - .sram ( mux_tree_tapbuf_size7_2_sram ) , - .sram_inv ( mux_top_track_6_undriven_sram_inv ) , - .out ( chany_top_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_122 ) ) ; -sb_1__0__mux_tree_tapbuf_size7_3 mux_right_track_0 ( - .in ( { chany_top_in[6] , chany_top_in[13] , right_bottom_grid_pin_1_[0] , - right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] , - chanx_left_in[2] , chanx_left_in[12] } ) , - .sram ( mux_tree_tapbuf_size7_3_sram ) , - .sram_inv ( mux_right_track_0_undriven_sram_inv ) , - .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_121 ) ) ; -sb_1__0__mux_tree_tapbuf_size7_5 mux_right_track_8 ( - .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , - right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_9_[0] , - chanx_left_in[6] , chanx_left_in[16] } ) , - .sram ( mux_tree_tapbuf_size7_4_sram ) , - .sram_inv ( mux_right_track_8_undriven_sram_inv ) , - .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_124 ) ) ; -sb_1__0__mux_tree_tapbuf_size7_4 mux_right_track_16 ( - .in ( { chany_top_in[3] , chany_top_in[10] , chany_top_in[17] , - right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_11_[0] , - chanx_left_in[8] , chanx_left_in[17] } ) , - .sram ( mux_tree_tapbuf_size7_5_sram ) , - .sram_inv ( mux_right_track_16_undriven_sram_inv ) , - .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_124 ) ) ; -sb_1__0__mux_tree_tapbuf_size7_1 mux_left_track_3 ( - .in ( { chany_top_in[6] , chany_top_in[13] , chanx_right_in[4] , - chanx_right_in[13] , left_bottom_grid_pin_3_[0] , - left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] } ) , - .sram ( mux_tree_tapbuf_size7_6_sram ) , - .sram_inv ( mux_left_track_3_undriven_sram_inv ) , - .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_120 ) ) ; -sb_1__0__mux_tree_tapbuf_size7_2 mux_left_track_9 ( - .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , - chanx_right_in[6] , chanx_right_in[16] , left_bottom_grid_pin_1_[0] , - left_bottom_grid_pin_9_[0] } ) , - .sram ( mux_tree_tapbuf_size7_7_sram ) , - .sram_inv ( mux_left_track_9_undriven_sram_inv ) , - .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_120 ) ) ; -sb_1__0__mux_tree_tapbuf_size7_0 mux_left_track_17 ( - .in ( { chany_top_in[3] , chany_top_in[10] , chany_top_in[17] , - chanx_right_in[8] , chanx_right_in[17] , left_bottom_grid_pin_3_[0] , - left_bottom_grid_pin_11_[0] } ) , - .sram ( mux_tree_tapbuf_size7_8_sram ) , - .sram_inv ( mux_left_track_17_undriven_sram_inv ) , - .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_120 ) ) ; -sb_1__0__mux_tree_tapbuf_size7_mem_6 mem_top_track_2 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__0__mux_tree_tapbuf_size7_mem_7 mem_top_track_4 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__0__mux_tree_tapbuf_size7_mem mem_top_track_6 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__0__mux_tree_tapbuf_size7_mem_3 mem_right_track_0 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__0__mux_tree_tapbuf_size7_mem_5 mem_right_track_8 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size11_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__0__mux_tree_tapbuf_size7_mem_4 mem_right_track_16 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__0__mux_tree_tapbuf_size7_mem_1 mem_left_track_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__0__mux_tree_tapbuf_size7_mem_2 mem_left_track_9 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size11_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__0__mux_tree_tapbuf_size7_mem_0 mem_left_track_17 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_8_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_8_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__0__mux_tree_tapbuf_size4 mux_top_track_8 ( - .in ( { top_left_grid_pin_42_[0] , chanx_right_in[8] , - chanx_right_in[15] , chanx_left_in[8] } ) , - .sram ( mux_tree_tapbuf_size4_0_sram ) , - .sram_inv ( mux_top_track_8_undriven_sram_inv ) , - .out ( chany_top_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_122 ) ) ; -sb_1__0__mux_tree_tapbuf_size4_0 mux_top_track_10 ( - .in ( { top_left_grid_pin_43_[0] , chanx_right_in[9] , - chanx_right_in[19] , chanx_left_in[9] } ) , - .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_top_track_10_undriven_sram_inv ) , - .out ( chany_top_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_124 ) ) ; -sb_1__0__mux_tree_tapbuf_size4_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__0__mux_tree_tapbuf_size4_mem_0 mem_top_track_10 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__0__mux_tree_tapbuf_size3_0 mux_top_track_12 ( - .in ( { top_left_grid_pin_44_[0] , chanx_right_in[10] , - chanx_left_in[10] } ) , - .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_top_track_12_undriven_sram_inv ) , - .out ( chany_top_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_121 ) ) ; -sb_1__0__mux_tree_tapbuf_size3_1 mux_top_track_14 ( - .in ( { top_left_grid_pin_45_[0] , chanx_right_in[12] , - chanx_left_in[12] } ) , - .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_top_track_14_undriven_sram_inv ) , - .out ( chany_top_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_121 ) ) ; -sb_1__0__mux_tree_tapbuf_size3_2 mux_top_track_16 ( - .in ( { top_left_grid_pin_46_[0] , chanx_right_in[13] , - chanx_left_in[13] } ) , - .sram ( mux_tree_tapbuf_size3_2_sram ) , - .sram_inv ( mux_top_track_16_undriven_sram_inv ) , - .out ( chany_top_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_120 ) ) ; -sb_1__0__mux_tree_tapbuf_size3_3 mux_top_track_18 ( - .in ( { top_left_grid_pin_47_[0] , chanx_right_in[14] , - chanx_left_in[14] } ) , - .sram ( mux_tree_tapbuf_size3_3_sram ) , - .sram_inv ( mux_top_track_18_undriven_sram_inv ) , - .out ( chany_top_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_121 ) ) ; -sb_1__0__mux_tree_tapbuf_size3_4 mux_top_track_20 ( - .in ( { top_left_grid_pin_48_[0] , chanx_right_in[16] , - chanx_left_in[16] } ) , - .sram ( mux_tree_tapbuf_size3_4_sram ) , - .sram_inv ( mux_top_track_20_undriven_sram_inv ) , - .out ( chany_top_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_122 ) ) ; -sb_1__0__mux_tree_tapbuf_size3_5 mux_top_track_22 ( - .in ( { top_left_grid_pin_49_[0] , chanx_right_in[17] , - chanx_left_in[17] } ) , - .sram ( mux_tree_tapbuf_size3_5_sram ) , - .sram_inv ( mux_top_track_22_undriven_sram_inv ) , - .out ( chany_top_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_122 ) ) ; -sb_1__0__mux_tree_tapbuf_size3 mux_top_track_24 ( - .in ( { top_left_grid_pin_42_[0] , chanx_right_in[18] , - chanx_left_in[18] } ) , - .sram ( mux_tree_tapbuf_size3_6_sram ) , - .sram_inv ( mux_top_track_24_undriven_sram_inv ) , - .out ( chany_top_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_121 ) ) ; -sb_1__0__mux_tree_tapbuf_size3_mem_0 mem_top_track_12 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__0__mux_tree_tapbuf_size3_mem_1 mem_top_track_14 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__0__mux_tree_tapbuf_size3_mem_2 mem_top_track_16 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__0__mux_tree_tapbuf_size3_mem_3 mem_top_track_18 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__0__mux_tree_tapbuf_size3_mem_4 mem_top_track_20 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__0__mux_tree_tapbuf_size3_mem_5 mem_top_track_22 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__0__mux_tree_tapbuf_size3_mem mem_top_track_24 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__0__mux_tree_tapbuf_size2 mux_top_track_38 ( - .in ( { chanx_right_in[0] , chanx_left_in[1] } ) , - .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_top_track_38_undriven_sram_inv ) , - .out ( chany_top_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_121 ) ) ; -sb_1__0__mux_tree_tapbuf_size2_mem mem_top_track_38 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__0__mux_tree_tapbuf_size11 mux_right_track_4 ( - .in ( { chany_top_in[1] , chany_top_in[8] , chany_top_in[15] , - right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_3_[0] , - right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_7_[0] , - right_bottom_grid_pin_9_[0] , right_bottom_grid_pin_11_[0] , - chanx_left_in[5] , chanx_left_in[14] } ) , - .sram ( mux_tree_tapbuf_size11_0_sram ) , - .sram_inv ( mux_right_track_4_undriven_sram_inv ) , - .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_123 ) ) ; -sb_1__0__mux_tree_tapbuf_size11_0 mux_left_track_5 ( - .in ( { chany_top_in[5] , chany_top_in[12] , chany_top_in[19] , - chanx_right_in[5] , chanx_right_in[14] , left_bottom_grid_pin_1_[0] , - left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_5_[0] , - left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_9_[0] , - left_bottom_grid_pin_11_[0] } ) , - .sram ( mux_tree_tapbuf_size11_1_sram ) , - .sram_inv ( mux_left_track_5_undriven_sram_inv ) , - .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_120 ) ) ; -sb_1__0__mux_tree_tapbuf_size11_mem mem_right_track_4 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size11_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size11_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__0__mux_tree_tapbuf_size11_mem_0 mem_left_track_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size11_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size11_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__0__mux_tree_tapbuf_size6 mux_right_track_24 ( - .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , - right_bottom_grid_pin_5_[0] , chanx_left_in[9] , chanx_left_in[18] } ) , - .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_right_track_24_undriven_sram_inv ) , - .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_124 ) ) ; -sb_1__0__mux_tree_tapbuf_size6_0 mux_left_track_25 ( - .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , - chanx_right_in[9] , chanx_right_in[18] , left_bottom_grid_pin_5_[0] } ) , - .sram ( mux_tree_tapbuf_size6_1_sram ) , - .sram_inv ( mux_left_track_25_undriven_sram_inv ) , - .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_122 ) ) ; -sb_1__0__mux_tree_tapbuf_size6_mem mem_right_track_24 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__0__mux_tree_tapbuf_size6_mem_0 mem_left_track_25 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_8_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__0__mux_tree_tapbuf_size5 mux_right_track_32 ( - .in ( { chany_top_in[5] , chany_top_in[12] , chany_top_in[19] , - right_bottom_grid_pin_7_[0] , chanx_left_in[10] } ) , - .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_right_track_32_undriven_sram_inv ) , - .out ( chanx_right_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_121 ) ) ; -sb_1__0__mux_tree_tapbuf_size5_0 mux_left_track_33 ( - .in ( { chany_top_in[1] , chany_top_in[8] , chany_top_in[15] , - chanx_right_in[10] , left_bottom_grid_pin_7_[0] } ) , - .sram ( mux_tree_tapbuf_size5_1_sram ) , - .sram_inv ( mux_left_track_33_undriven_sram_inv ) , - .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_120 ) ) ; -sb_1__0__mux_tree_tapbuf_size5_mem mem_right_track_32 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__0__mux_tree_tapbuf_size5_mem_0 mem_left_track_33 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .ccff_tail ( { ropt_net_147 } ) , - .mem_out ( mux_tree_tapbuf_size5_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1340 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1341 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1342 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1343 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1344 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1345 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1346 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1347 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1348 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1349 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1350 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1351 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1352 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1353 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1354 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1355 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1356 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1357 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1358 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1359 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1360 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1361 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1362 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1363 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1364 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1365 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1366 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1367 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1368 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1369 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1370 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1371 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1372 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1373 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1374 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1375 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1376 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1377 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__conb_1 optlc_114 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_120 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chanx_right_in[2] ) , - .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__3 ( .A ( chanx_right_in[5] ) , - .X ( ropt_net_154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_161 ) , - .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_121 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__8 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_158 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_162 ) , - .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__10 ( .A ( chanx_right_in[14] ) , - .X ( ropt_net_151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_123 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , - .HI ( optlc_net_124 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__clkbuf_1 prog_clk_0__bip390 ( .A ( prog_clk[0] ) , - .X ( prog_clk__FEEDTHRU_2_0_0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( .A ( ropt_net_129 ) , - .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chanx_left_in[2] ) , - .X ( ropt_net_152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( chanx_left_in[19] ) , - .X ( ropt_net_169 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chanx_left_in[5] ) , - .X ( ropt_net_150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 cts_buf_368758 ( .A ( prog_clk__FEEDTHRU_2_0_0 ) , - .X ( prog_clk__FEEDTHRU_2[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_784 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_179 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_785 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_175 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__21 ( .A ( chanx_left_in[9] ) , - .X ( ropt_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chanx_left_in[10] ) , - .X ( ropt_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_134 ) , - .X ( ropt_net_171 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_787 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_176 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_788 ( .A ( chanx_left_in[12] ) , - .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_137 ) , - .X ( ropt_net_163 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( chanx_right_in[18] ) , - .X ( ropt_net_174 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_821 ( .A ( ropt_net_163 ) , - .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_822 ( .A ( ropt_net_164 ) , - .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( chanx_left_in[13] ) , - .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( chanx_left_in[16] ) , - .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( chanx_right_in[6] ) , - .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_178 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_823 ( .A ( ropt_net_165 ) , - .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_166 ) , - .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_825 ( .A ( ropt_net_167 ) , - .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_826 ( .A ( ropt_net_168 ) , - .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_70 ( .A ( chanx_left_in[3] ) , - .X ( ropt_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_71 ( .A ( chanx_left_in[4] ) , - .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_72 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_73 ( .A ( chanx_left_in[7] ) , - .X ( ropt_net_160 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_74 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_156 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_75 ( .A ( chanx_left_in[11] ) , - .X ( ropt_net_137 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_827 ( .A ( ropt_net_169 ) , - .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_170 ) , - .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_78 ( .A ( chanx_left_in[14] ) , - .X ( ropt_net_159 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_79 ( .A ( chanx_left_in[15] ) , - .X ( ropt_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_143 ) , - .X ( ropt_net_164 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_830 ( .A ( ropt_net_171 ) , - .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_832 ( .A ( ropt_net_172 ) , - .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_177 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( ropt_net_145 ) , - .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_146 ) , - .X ( ropt_net_167 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_147 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_148 ) , - .X ( ropt_net_172 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_149 ) , - .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_150 ) , - .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_833 ( .A ( ropt_net_173 ) , - .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_99 ( .A ( top_left_grid_pin_43_[0] ) , - .X ( ropt_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_837 ( .A ( ropt_net_174 ) , - .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_151 ) , - .X ( ropt_net_161 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_105 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_152 ) , - .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_107 ( .A ( chanx_right_in[16] ) , - .X ( ropt_net_134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_153 ) , - .X ( ropt_net_162 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_154 ) , - .X ( ropt_net_166 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_155 ) , - .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_156 ) , - .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_157 ) , - .X ( ropt_net_173 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_810 ( .A ( ropt_net_158 ) , - .X ( ropt_net_170 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_159 ) , - .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_160 ) , - .X ( ropt_net_168 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_838 ( .A ( ropt_net_175 ) , - .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_839 ( .A ( ropt_net_176 ) , - .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_840 ( .A ( ropt_net_177 ) , - .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_841 ( .A ( ropt_net_178 ) , - .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_842 ( .A ( ropt_net_179 ) , - .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y0 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1145400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1163800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1173000y0 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x538200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x754400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x791200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x828000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x864800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x901600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x938400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x975200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1012000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1048800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1085600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1122400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1159200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x754400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x791200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x828000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1145400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1163800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1173000y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1163800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1173000y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x147200y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x188600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x225400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x262200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x299000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x335800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x372600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x409400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x851000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1145400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1163800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1173000y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1163800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1173000y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x515200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x607200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x851000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1145400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1163800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1173000y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x611800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x621000y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x667000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x685400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x731400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x768200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x841800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x878600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x915400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x952200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x989000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1025800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1062600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1099400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1136200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1173000y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x128800y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x161000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x197800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x234600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x271400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x289800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x409400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x519800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x538200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x851000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1145400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1163800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1173000y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x105800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x142600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x179400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x216200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x234600y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x354200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x653200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x690000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x708400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x717600y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x910800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x947600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x984400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1021200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1058000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1094800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1131600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x340400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x349600y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x625600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x644000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x653200y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x887800y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1048800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1085600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1122400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1159200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x73600y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x115000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x151800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x188600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x225400y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x271400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x280600y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x358800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x418600y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x722200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x740600y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x786600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x823400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x860200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x878600y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1016600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1076400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1094800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x147200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x165600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x404800y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x483000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x501400y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x579600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x598000y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x754400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x763600y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x805000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x823400y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1136200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1173000y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x92000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x101200y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x179400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x216200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x253000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x289800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x437000y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x625600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x644000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x694600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x713000y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x869400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x887800y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x966000y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1044200y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1085600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x36800y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x69000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x78200y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x124200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x142600y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x423200y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x501400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x593400y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x639400y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x685400y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x772800y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1007400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1025800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1035000y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1081000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1099400y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x55200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x92000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x101200y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x331200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x464600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x483000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x492200y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x759000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x786600y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x832600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x851000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x860200y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x979800y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1025800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1044200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1053400y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1094800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x101200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x138000y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x381800y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x427800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x524400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x542800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x676200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x713000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x795800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x805000y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x851000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x924600y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1002800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1012000y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1058000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x197800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x234600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x326600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x363400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x427800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x570400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x648600y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x694600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x713000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x722200y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x846400y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x933800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x165600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x202400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x239200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x308200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x326600y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x423200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x460000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x478400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x565800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x602600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x639400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x657800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x708400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x782000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x800400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x809600y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x855600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x970600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1021200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1058000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x101200y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x271400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x289800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x473800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x510600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x588800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x607200y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x653200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x690000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x708400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x717600y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x795800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x814200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x901600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x984400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1002800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1053400y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x202400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x239200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x257600y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x335800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x372600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x519800y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x565800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x584200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x593400y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x639400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x749800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x887800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x938400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1016600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1035000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1044200y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1090200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1099400y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x151800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x243800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x294400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x312800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x363400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x510600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x529000y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x644000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x690000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x740600y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x786600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x805000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x924600y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1002800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1163800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1173000y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x220800y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x262200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x331200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x349600y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x579600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x598000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x607200y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x759000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x786600y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x828000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x929200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x966000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1002800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1012000y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1058000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x142600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x179400y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x225400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x308200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x345000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x432400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x450800y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x565800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x662400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x680800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x731400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x782000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x800400y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x878600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x151800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x161000y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x239200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x289800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x299000y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x377200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x395600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x404800y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x450800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x579600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x588800y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x634800y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x713000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x823400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x860200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x956800y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1035000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1053400y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x161000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x197800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x234600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x271400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x289800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x427800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x492200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x529000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x538200y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x584200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x602600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x611800y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x657800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x694600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x745200y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x791200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x800400y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x878600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x897000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x989000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x303600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x312800y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x358800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x409400y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x455400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x492200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x542800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x561200y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x644000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x653200y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x694600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x731400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x740600y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x795800y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x841800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x961400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1012000y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x234600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x345000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x437000y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x515200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x533600y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x579600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x639400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x722200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x740600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x823400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x860200y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x901600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x938400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x326600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x386400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x478400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x496800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x547400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x556600y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x602600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x639400y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x795800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x814200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x823400y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1035000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1053400y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x294400y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x427800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x446200y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x602600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x680800y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x763600y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x920000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x966000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1002800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1012000y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x202400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x239200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x368000y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x483000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x501400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x547400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x584200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x621000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x657800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x676200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x795800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x814200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x823400y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x924600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x391000y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x515200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x524400y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x570400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x657800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x708400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x892400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x929200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x966000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1002800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1039600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1076400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1113200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x331200y870400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x483000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y870400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x418600y897600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x846400y897600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x892400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x432400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x607200y924800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x841800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y924800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y952000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y952000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__0__icv_in_design.pt.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__0__icv_in_design.pt.v deleted file mode 100644 index ec9c14b..0000000 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__0__icv_in_design.pt.v +++ /dev/null @@ -1,2106 +0,0 @@ -// -// -// -// -// -// -module sb_1__0__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__60 ( .A ( mem_out[2] ) , - .X ( net_net_84 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_84 ( .A ( net_net_84 ) , - .X ( net_net_83 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_103 ( .A ( net_net_83 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__59 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__58 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__57 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size11_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__56 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size11_mem ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__55 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size11_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:10] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[10] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size11 ( in , sram , sram_inv , out , p0 ) ; -input [0:10] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[10] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__54 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__53 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size3_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__52 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size3_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__51 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__50 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__49 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__48 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__47 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size3_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size3_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__46 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__45 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__44 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__43 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__42 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__41 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__40 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__39 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__38 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__37 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__36 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_7 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size7_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__35 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__34 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__33 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module sb_1__0__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module sb_1__0_ ( prog_clk , chany_top_in , top_left_grid_pin_42_ , - top_left_grid_pin_43_ , top_left_grid_pin_44_ , top_left_grid_pin_45_ , - top_left_grid_pin_46_ , top_left_grid_pin_47_ , top_left_grid_pin_48_ , - top_left_grid_pin_49_ , chanx_right_in , right_bottom_grid_pin_1_ , - right_bottom_grid_pin_3_ , right_bottom_grid_pin_5_ , - right_bottom_grid_pin_7_ , right_bottom_grid_pin_9_ , - right_bottom_grid_pin_11_ , chanx_left_in , left_bottom_grid_pin_1_ , - left_bottom_grid_pin_3_ , left_bottom_grid_pin_5_ , - left_bottom_grid_pin_7_ , left_bottom_grid_pin_9_ , - left_bottom_grid_pin_11_ , ccff_head , chany_top_out , chanx_right_out , - chanx_left_out , ccff_tail , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , - SC_OUT_BOT , prog_clk__FEEDTHRU_1 , prog_clk__FEEDTHRU_2 ) ; -input [0:0] prog_clk ; -input [0:19] chany_top_in ; -input [0:0] top_left_grid_pin_42_ ; -input [0:0] top_left_grid_pin_43_ ; -input [0:0] top_left_grid_pin_44_ ; -input [0:0] top_left_grid_pin_45_ ; -input [0:0] top_left_grid_pin_46_ ; -input [0:0] top_left_grid_pin_47_ ; -input [0:0] top_left_grid_pin_48_ ; -input [0:0] top_left_grid_pin_49_ ; -input [0:19] chanx_right_in ; -input [0:0] right_bottom_grid_pin_1_ ; -input [0:0] right_bottom_grid_pin_3_ ; -input [0:0] right_bottom_grid_pin_5_ ; -input [0:0] right_bottom_grid_pin_7_ ; -input [0:0] right_bottom_grid_pin_9_ ; -input [0:0] right_bottom_grid_pin_11_ ; -input [0:19] chanx_left_in ; -input [0:0] left_bottom_grid_pin_1_ ; -input [0:0] left_bottom_grid_pin_3_ ; -input [0:0] left_bottom_grid_pin_5_ ; -input [0:0] left_bottom_grid_pin_7_ ; -input [0:0] left_bottom_grid_pin_9_ ; -input [0:0] left_bottom_grid_pin_11_ ; -input [0:0] ccff_head ; -output [0:19] chany_top_out ; -output [0:19] chanx_right_out ; -output [0:19] chanx_left_out ; -output [0:0] ccff_tail ; -input SC_IN_TOP ; -input SC_IN_BOT ; -output SC_OUT_TOP ; -output SC_OUT_BOT ; -output [0:0] prog_clk__FEEDTHRU_1 ; -output [0:0] prog_clk__FEEDTHRU_2 ; - -wire [0:2] mux_left_track_17_undriven_sram_inv ; -wire [0:3] mux_left_track_1_undriven_sram_inv ; -wire [0:2] mux_left_track_25_undriven_sram_inv ; -wire [0:2] mux_left_track_33_undriven_sram_inv ; -wire [0:2] mux_left_track_3_undriven_sram_inv ; -wire [0:3] mux_left_track_5_undriven_sram_inv ; -wire [0:2] mux_left_track_9_undriven_sram_inv ; -wire [0:2] mux_right_track_0_undriven_sram_inv ; -wire [0:2] mux_right_track_16_undriven_sram_inv ; -wire [0:2] mux_right_track_24_undriven_sram_inv ; -wire [0:3] mux_right_track_2_undriven_sram_inv ; -wire [0:2] mux_right_track_32_undriven_sram_inv ; -wire [0:3] mux_right_track_4_undriven_sram_inv ; -wire [0:2] mux_right_track_8_undriven_sram_inv ; -wire [0:3] mux_top_track_0_undriven_sram_inv ; -wire [0:2] mux_top_track_10_undriven_sram_inv ; -wire [0:1] mux_top_track_12_undriven_sram_inv ; -wire [0:1] mux_top_track_14_undriven_sram_inv ; -wire [0:1] mux_top_track_16_undriven_sram_inv ; -wire [0:1] mux_top_track_18_undriven_sram_inv ; -wire [0:1] mux_top_track_20_undriven_sram_inv ; -wire [0:1] mux_top_track_22_undriven_sram_inv ; -wire [0:1] mux_top_track_24_undriven_sram_inv ; -wire [0:2] mux_top_track_2_undriven_sram_inv ; -wire [0:1] mux_top_track_38_undriven_sram_inv ; -wire [0:2] mux_top_track_4_undriven_sram_inv ; -wire [0:2] mux_top_track_6_undriven_sram_inv ; -wire [0:2] mux_top_track_8_undriven_sram_inv ; -wire [0:3] mux_tree_tapbuf_size11_0_sram ; -wire [0:3] mux_tree_tapbuf_size11_1_sram ; -wire [0:0] mux_tree_tapbuf_size11_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size11_mem_1_ccff_tail ; -wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; -wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:1] mux_tree_tapbuf_size3_2_sram ; -wire [0:1] mux_tree_tapbuf_size3_3_sram ; -wire [0:1] mux_tree_tapbuf_size3_4_sram ; -wire [0:1] mux_tree_tapbuf_size3_5_sram ; -wire [0:1] mux_tree_tapbuf_size3_6_sram ; -wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size4_0_sram ; -wire [0:2] mux_tree_tapbuf_size4_1_sram ; -wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size5_0_sram ; -wire [0:2] mux_tree_tapbuf_size5_1_sram ; -wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size6_1_sram ; -wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size7_0_sram ; -wire [0:2] mux_tree_tapbuf_size7_1_sram ; -wire [0:2] mux_tree_tapbuf_size7_2_sram ; -wire [0:2] mux_tree_tapbuf_size7_3_sram ; -wire [0:2] mux_tree_tapbuf_size7_4_sram ; -wire [0:2] mux_tree_tapbuf_size7_5_sram ; -wire [0:2] mux_tree_tapbuf_size7_6_sram ; -wire [0:2] mux_tree_tapbuf_size7_7_sram ; -wire [0:2] mux_tree_tapbuf_size7_8_sram ; -wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_7_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_8_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:3] mux_tree_tapbuf_size8_2_sram ; -wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; -// - -assign SC_IN_TOP = SC_IN_BOT ; -assign prog_clk__FEEDTHRU_1[0] = prog_clk__FEEDTHRU_2[0] ; - -sb_1__0__mux_tree_tapbuf_size8 mux_top_track_0 ( - .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , - top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , - chanx_right_in[1] , chanx_right_in[2] , chanx_left_in[0] , - chanx_left_in[2] } ) , - .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_top_track_0_undriven_sram_inv ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_120 ) ) ; -sb_1__0__mux_tree_tapbuf_size8_1 mux_right_track_2 ( - .in ( { chany_top_in[0] , chany_top_in[7] , chany_top_in[14] , - right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_7_[0] , - right_bottom_grid_pin_11_[0] , chanx_left_in[4] , chanx_left_in[13] } ) , - .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_right_track_2_undriven_sram_inv ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_123 ) ) ; -sb_1__0__mux_tree_tapbuf_size8_0 mux_left_track_1 ( - .in ( { chany_top_in[0] , chany_top_in[7] , chany_top_in[14] , - chanx_right_in[2] , chanx_right_in[12] , left_bottom_grid_pin_1_[0] , - left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] } ) , - .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_left_track_1_undriven_sram_inv ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_120 ) ) ; -sb_1__0__mux_tree_tapbuf_size8_mem mem_top_track_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size8_mem_1 mem_right_track_2 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size8_mem_0 mem_left_track_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size7_6 mux_top_track_2 ( - .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , - top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , - chanx_right_in[3] , chanx_right_in[4] , chanx_left_in[4] } ) , - .sram ( mux_tree_tapbuf_size7_0_sram ) , - .sram_inv ( mux_top_track_2_undriven_sram_inv ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_121 ) ) ; -sb_1__0__mux_tree_tapbuf_size7_7 mux_top_track_4 ( - .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , - top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , - chanx_right_in[5] , chanx_right_in[7] , chanx_left_in[5] } ) , - .sram ( mux_tree_tapbuf_size7_1_sram ) , - .sram_inv ( mux_top_track_4_undriven_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_122 ) ) ; -sb_1__0__mux_tree_tapbuf_size7 mux_top_track_6 ( - .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , - top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , - chanx_right_in[6] , chanx_right_in[11] , chanx_left_in[6] } ) , - .sram ( mux_tree_tapbuf_size7_2_sram ) , - .sram_inv ( mux_top_track_6_undriven_sram_inv ) , - .out ( chany_top_out[3] ) , .p0 ( optlc_net_122 ) ) ; -sb_1__0__mux_tree_tapbuf_size7_3 mux_right_track_0 ( - .in ( { chany_top_in[6] , chany_top_in[13] , right_bottom_grid_pin_1_[0] , - right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] , - chanx_left_in[2] , chanx_left_in[12] } ) , - .sram ( mux_tree_tapbuf_size7_3_sram ) , - .sram_inv ( mux_right_track_0_undriven_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_121 ) ) ; -sb_1__0__mux_tree_tapbuf_size7_5 mux_right_track_8 ( - .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , - right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_9_[0] , - chanx_left_in[6] , chanx_left_in[16] } ) , - .sram ( mux_tree_tapbuf_size7_4_sram ) , - .sram_inv ( mux_right_track_8_undriven_sram_inv ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_124 ) ) ; -sb_1__0__mux_tree_tapbuf_size7_4 mux_right_track_16 ( - .in ( { chany_top_in[3] , chany_top_in[10] , chany_top_in[17] , - right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_11_[0] , - chanx_left_in[8] , chanx_left_in[17] } ) , - .sram ( mux_tree_tapbuf_size7_5_sram ) , - .sram_inv ( mux_right_track_16_undriven_sram_inv ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_124 ) ) ; -sb_1__0__mux_tree_tapbuf_size7_1 mux_left_track_3 ( - .in ( { chany_top_in[6] , chany_top_in[13] , chanx_right_in[4] , - chanx_right_in[13] , left_bottom_grid_pin_3_[0] , - left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] } ) , - .sram ( mux_tree_tapbuf_size7_6_sram ) , - .sram_inv ( mux_left_track_3_undriven_sram_inv ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_120 ) ) ; -sb_1__0__mux_tree_tapbuf_size7_2 mux_left_track_9 ( - .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , - chanx_right_in[6] , chanx_right_in[16] , left_bottom_grid_pin_1_[0] , - left_bottom_grid_pin_9_[0] } ) , - .sram ( mux_tree_tapbuf_size7_7_sram ) , - .sram_inv ( mux_left_track_9_undriven_sram_inv ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_120 ) ) ; -sb_1__0__mux_tree_tapbuf_size7_0 mux_left_track_17 ( - .in ( { chany_top_in[3] , chany_top_in[10] , chany_top_in[17] , - chanx_right_in[8] , chanx_right_in[17] , left_bottom_grid_pin_3_[0] , - left_bottom_grid_pin_11_[0] } ) , - .sram ( mux_tree_tapbuf_size7_8_sram ) , - .sram_inv ( mux_left_track_17_undriven_sram_inv ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_120 ) ) ; -sb_1__0__mux_tree_tapbuf_size7_mem_6 mem_top_track_2 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size7_mem_7 mem_top_track_4 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size7_mem mem_top_track_6 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size7_mem_3 mem_right_track_0 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_3_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size7_mem_5 mem_right_track_8 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size11_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_4_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size7_mem_4 mem_right_track_16 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_5_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size7_mem_1 mem_left_track_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_6_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size7_mem_2 mem_left_track_9 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size11_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_7_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size7_mem_0 mem_left_track_17 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_8_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_8_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size4 mux_top_track_8 ( - .in ( { top_left_grid_pin_42_[0] , chanx_right_in[8] , - chanx_right_in[15] , chanx_left_in[8] } ) , - .sram ( mux_tree_tapbuf_size4_0_sram ) , - .sram_inv ( mux_top_track_8_undriven_sram_inv ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_122 ) ) ; -sb_1__0__mux_tree_tapbuf_size4_0 mux_top_track_10 ( - .in ( { top_left_grid_pin_43_[0] , chanx_right_in[9] , - chanx_right_in[19] , chanx_left_in[9] } ) , - .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_top_track_10_undriven_sram_inv ) , - .out ( chany_top_out[5] ) , .p0 ( optlc_net_124 ) ) ; -sb_1__0__mux_tree_tapbuf_size4_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size4_mem_0 mem_top_track_10 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size3_0 mux_top_track_12 ( - .in ( { top_left_grid_pin_44_[0] , chanx_right_in[10] , - chanx_left_in[10] } ) , - .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_top_track_12_undriven_sram_inv ) , - .out ( chany_top_out[6] ) , .p0 ( optlc_net_121 ) ) ; -sb_1__0__mux_tree_tapbuf_size3_1 mux_top_track_14 ( - .in ( { top_left_grid_pin_45_[0] , chanx_right_in[12] , - chanx_left_in[12] } ) , - .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_top_track_14_undriven_sram_inv ) , - .out ( chany_top_out[7] ) , .p0 ( optlc_net_121 ) ) ; -sb_1__0__mux_tree_tapbuf_size3_2 mux_top_track_16 ( - .in ( { top_left_grid_pin_46_[0] , chanx_right_in[13] , - chanx_left_in[13] } ) , - .sram ( mux_tree_tapbuf_size3_2_sram ) , - .sram_inv ( mux_top_track_16_undriven_sram_inv ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_120 ) ) ; -sb_1__0__mux_tree_tapbuf_size3_3 mux_top_track_18 ( - .in ( { top_left_grid_pin_47_[0] , chanx_right_in[14] , - chanx_left_in[14] } ) , - .sram ( mux_tree_tapbuf_size3_3_sram ) , - .sram_inv ( mux_top_track_18_undriven_sram_inv ) , - .out ( chany_top_out[9] ) , .p0 ( optlc_net_121 ) ) ; -sb_1__0__mux_tree_tapbuf_size3_4 mux_top_track_20 ( - .in ( { top_left_grid_pin_48_[0] , chanx_right_in[16] , - chanx_left_in[16] } ) , - .sram ( mux_tree_tapbuf_size3_4_sram ) , - .sram_inv ( mux_top_track_20_undriven_sram_inv ) , - .out ( chany_top_out[10] ) , .p0 ( optlc_net_122 ) ) ; -sb_1__0__mux_tree_tapbuf_size3_5 mux_top_track_22 ( - .in ( { top_left_grid_pin_49_[0] , chanx_right_in[17] , - chanx_left_in[17] } ) , - .sram ( mux_tree_tapbuf_size3_5_sram ) , - .sram_inv ( mux_top_track_22_undriven_sram_inv ) , - .out ( chany_top_out[11] ) , .p0 ( optlc_net_122 ) ) ; -sb_1__0__mux_tree_tapbuf_size3 mux_top_track_24 ( - .in ( { top_left_grid_pin_42_[0] , chanx_right_in[18] , - chanx_left_in[18] } ) , - .sram ( mux_tree_tapbuf_size3_6_sram ) , - .sram_inv ( mux_top_track_24_undriven_sram_inv ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_121 ) ) ; -sb_1__0__mux_tree_tapbuf_size3_mem_0 mem_top_track_12 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size3_mem_1 mem_top_track_14 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size3_mem_2 mem_top_track_16 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size3_mem_3 mem_top_track_18 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size3_mem_4 mem_top_track_20 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_4_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size3_mem_5 mem_top_track_22 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_5_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size3_mem mem_top_track_24 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_6_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size2 mux_top_track_38 ( - .in ( { chanx_right_in[0] , chanx_left_in[1] } ) , - .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_top_track_38_undriven_sram_inv ) , - .out ( chany_top_out[19] ) , .p0 ( optlc_net_121 ) ) ; -sb_1__0__mux_tree_tapbuf_size2_mem mem_top_track_38 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size11 mux_right_track_4 ( - .in ( { chany_top_in[1] , chany_top_in[8] , chany_top_in[15] , - right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_3_[0] , - right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_7_[0] , - right_bottom_grid_pin_9_[0] , right_bottom_grid_pin_11_[0] , - chanx_left_in[5] , chanx_left_in[14] } ) , - .sram ( mux_tree_tapbuf_size11_0_sram ) , - .sram_inv ( mux_right_track_4_undriven_sram_inv ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_123 ) ) ; -sb_1__0__mux_tree_tapbuf_size11_0 mux_left_track_5 ( - .in ( { chany_top_in[5] , chany_top_in[12] , chany_top_in[19] , - chanx_right_in[5] , chanx_right_in[14] , left_bottom_grid_pin_1_[0] , - left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_5_[0] , - left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_9_[0] , - left_bottom_grid_pin_11_[0] } ) , - .sram ( mux_tree_tapbuf_size11_1_sram ) , - .sram_inv ( mux_left_track_5_undriven_sram_inv ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_120 ) ) ; -sb_1__0__mux_tree_tapbuf_size11_mem mem_right_track_4 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size11_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size11_0_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size11_mem_0 mem_left_track_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size11_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size11_1_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size6 mux_right_track_24 ( - .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , - right_bottom_grid_pin_5_[0] , chanx_left_in[9] , chanx_left_in[18] } ) , - .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_right_track_24_undriven_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_124 ) ) ; -sb_1__0__mux_tree_tapbuf_size6_0 mux_left_track_25 ( - .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , - chanx_right_in[9] , chanx_right_in[18] , left_bottom_grid_pin_5_[0] } ) , - .sram ( mux_tree_tapbuf_size6_1_sram ) , - .sram_inv ( mux_left_track_25_undriven_sram_inv ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_122 ) ) ; -sb_1__0__mux_tree_tapbuf_size6_mem mem_right_track_24 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size6_mem_0 mem_left_track_25 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_8_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size5 mux_right_track_32 ( - .in ( { chany_top_in[5] , chany_top_in[12] , chany_top_in[19] , - right_bottom_grid_pin_7_[0] , chanx_left_in[10] } ) , - .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_right_track_32_undriven_sram_inv ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_121 ) ) ; -sb_1__0__mux_tree_tapbuf_size5_0 mux_left_track_33 ( - .in ( { chany_top_in[1] , chany_top_in[8] , chany_top_in[15] , - chanx_right_in[10] , left_bottom_grid_pin_7_[0] } ) , - .sram ( mux_tree_tapbuf_size5_1_sram ) , - .sram_inv ( mux_left_track_33_undriven_sram_inv ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_120 ) ) ; -sb_1__0__mux_tree_tapbuf_size5_mem mem_right_track_32 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ; -sb_1__0__mux_tree_tapbuf_size5_mem_0 mem_left_track_33 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .ccff_tail ( { ropt_net_147 } ) , - .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ; -sky130_fd_sc_hd__conb_1 optlc_114 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_120 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chanx_right_in[2] ) , - .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_145 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__3 ( .A ( chanx_right_in[5] ) , - .X ( ropt_net_154 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_121 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_161 ) , - .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_122 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_121 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_123 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__8 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_158 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_162 ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__10 ( .A ( chanx_right_in[14] ) , - .X ( ropt_net_151 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_123 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , - .HI ( optlc_net_124 ) ) ; -sky130_fd_sc_hd__clkbuf_1 prog_clk_0__bip390 ( .A ( prog_clk[0] ) , - .X ( prog_clk__FEEDTHRU_2_0_0 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( .A ( ropt_net_129 ) , - .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chanx_left_in[2] ) , - .X ( ropt_net_152 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_165 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( chanx_left_in[19] ) , - .X ( ropt_net_169 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chanx_left_in[5] ) , - .X ( ropt_net_150 ) ) ; -sky130_fd_sc_hd__buf_8 cts_buf_368758 ( .A ( prog_clk__FEEDTHRU_2_0_0 ) , - .X ( prog_clk__FEEDTHRU_2[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_784 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_179 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_785 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_175 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__21 ( .A ( chanx_left_in[9] ) , - .X ( ropt_net_148 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chanx_left_in[10] ) , - .X ( ropt_net_155 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_134 ) , - .X ( ropt_net_171 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_787 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_176 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_788 ( .A ( chanx_left_in[12] ) , - .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_137 ) , - .X ( ropt_net_163 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( chanx_right_in[18] ) , - .X ( ropt_net_174 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_821 ( .A ( ropt_net_163 ) , - .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_822 ( .A ( ropt_net_164 ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( chanx_left_in[13] ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( chanx_left_in[16] ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_129 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( chanx_right_in[6] ) , - .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_178 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_823 ( .A ( ropt_net_165 ) , - .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_166 ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_825 ( .A ( ropt_net_167 ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_826 ( .A ( ropt_net_168 ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_70 ( .A ( chanx_left_in[3] ) , - .X ( ropt_net_143 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_71 ( .A ( chanx_left_in[4] ) , - .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_72 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_157 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_73 ( .A ( chanx_left_in[7] ) , - .X ( ropt_net_160 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_74 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_156 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_75 ( .A ( chanx_left_in[11] ) , - .X ( ropt_net_137 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_827 ( .A ( ropt_net_169 ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_170 ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_78 ( .A ( chanx_left_in[14] ) , - .X ( ropt_net_159 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_79 ( .A ( chanx_left_in[15] ) , - .X ( ropt_net_146 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_143 ) , - .X ( ropt_net_164 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_830 ( .A ( ropt_net_171 ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_832 ( .A ( ropt_net_172 ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_177 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( ropt_net_145 ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_146 ) , - .X ( ropt_net_167 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_147 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_148 ) , - .X ( ropt_net_172 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_149 ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_150 ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_833 ( .A ( ropt_net_173 ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_99 ( .A ( top_left_grid_pin_43_[0] ) , - .X ( ropt_net_149 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_837 ( .A ( ropt_net_174 ) , - .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_151 ) , - .X ( ropt_net_161 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_105 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_153 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_152 ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_107 ( .A ( chanx_right_in[16] ) , - .X ( ropt_net_134 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_153 ) , - .X ( ropt_net_162 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_154 ) , - .X ( ropt_net_166 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_155 ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_156 ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_157 ) , - .X ( ropt_net_173 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_810 ( .A ( ropt_net_158 ) , - .X ( ropt_net_170 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_159 ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_160 ) , - .X ( ropt_net_168 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_838 ( .A ( ropt_net_175 ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_839 ( .A ( ropt_net_176 ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_840 ( .A ( ropt_net_177 ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_841 ( .A ( ropt_net_178 ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_842 ( .A ( ropt_net_179 ) , - .X ( chanx_right_out[19] ) ) ; -endmodule - - diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__1__icv_in_design.fm.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__1__icv_in_design.fm.v deleted file mode 100644 index 0d7b2b7..0000000 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__1__icv_in_design.fm.v +++ /dev/null @@ -1,3123 +0,0 @@ -// -// -// -// -// -// -module sb_1__1__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_28__81 ( .A ( mem_out[2] ) , - .X ( net_net_100 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_100 ( .A ( net_net_100 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__80 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__79 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__78 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__const1 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sb_1__1__const1 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_1__1__const1_26 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sb_1__1__const1_26 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_1__1__const1_25 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sb_1__1__const1_25 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_1__1__const1_24 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sb_1__1__const1_24 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__77 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__76 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__75 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__74 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__73 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__72 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__71 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__70 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_mem_8 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__69 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_mem_10 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__68 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_mem_9 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__67 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__66 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__const1_23 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sb_1__1__const1_23 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module sb_1__1__const1_22 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sb_1__1__const1_22 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module sb_1__1__const1_21 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sb_1__1__const1_21 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module sb_1__1__const1_20 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sb_1__1__const1_20 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module sb_1__1__const1_19 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sb_1__1__const1_19 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module sb_1__1__const1_18 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sb_1__1__const1_18 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module sb_1__1__const1_17 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sb_1__1__const1_17 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module sb_1__1__const1_16 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sb_1__1__const1_16 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module sb_1__1__const1_15 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_8 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sb_1__1__const1_15 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module sb_1__1__const1_14 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_10 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sb_1__1__const1_14 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module sb_1__1__const1_13 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_9 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sb_1__1__const1_13 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module sb_1__1__const1_12 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sb_1__1__const1_12 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size16_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:4] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__65 ( .A ( mem_out[4] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size16_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:4] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__64 ( .A ( mem_out[4] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size16_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:4] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__63 ( .A ( mem_out[4] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size16_mem ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:4] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__62 ( .A ( mem_out[4] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__const1_11 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size16_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:15] in ; -input [0:4] sram ; -input [0:4] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sb_1__1__const1_11 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l5_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_1__1__const1_10 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size16_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:15] in ; -input [0:4] sram ; -input [0:4] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_15_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sb_1__1__const1_10 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , - .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_83 ( - .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( BUF_net_83 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_128 ( .A ( BUF_net_83 ) , - .X ( out[0] ) ) ; -endmodule - - -module sb_1__1__const1_9 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size16_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:15] in ; -input [0:4] sram ; -input [0:4] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_15_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sb_1__1__const1_9 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , - .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) ) ; -endmodule - - -module sb_1__1__const1_8 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size16 ( in , sram , sram_inv , out , p0 ) ; -input [0:15] in ; -input [0:4] sram ; -input [0:4] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_15_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sb_1__1__const1_8 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , - .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__61 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__60 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__59 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__58 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__57 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__56 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_mem ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__55 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__54 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__const1_7 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:11] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sb_1__1__const1_7 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -endmodule - - -module sb_1__1__const1_6 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:11] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sb_1__1__const1_6 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_127 ( - .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_1__1__const1_5 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:11] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sb_1__1__const1_5 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -endmodule - - -module sb_1__1__const1_4 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:11] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sb_1__1__const1_4 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -endmodule - - -module sb_1__1__const1_3 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:11] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sb_1__1__const1_3 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -endmodule - - -module sb_1__1__const1_2 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:11] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sb_1__1__const1_2 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -endmodule - - -module sb_1__1__const1_1 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12 ( in , sram , sram_inv , out , p0 ) ; -input [0:11] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sb_1__1__const1_1 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -endmodule - - -module sb_1__1__const1_0 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:11] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sb_1__1__const1_0 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -endmodule - - -module sb_1__1_ ( prog_clk , chany_top_in , top_left_grid_pin_42_ , - top_left_grid_pin_43_ , top_left_grid_pin_44_ , top_left_grid_pin_45_ , - top_left_grid_pin_46_ , top_left_grid_pin_47_ , top_left_grid_pin_48_ , - top_left_grid_pin_49_ , chanx_right_in , right_bottom_grid_pin_34_ , - right_bottom_grid_pin_35_ , right_bottom_grid_pin_36_ , - right_bottom_grid_pin_37_ , right_bottom_grid_pin_38_ , - right_bottom_grid_pin_39_ , right_bottom_grid_pin_40_ , - right_bottom_grid_pin_41_ , chany_bottom_in , bottom_left_grid_pin_42_ , - bottom_left_grid_pin_43_ , bottom_left_grid_pin_44_ , - bottom_left_grid_pin_45_ , bottom_left_grid_pin_46_ , - bottom_left_grid_pin_47_ , bottom_left_grid_pin_48_ , - bottom_left_grid_pin_49_ , chanx_left_in , left_bottom_grid_pin_34_ , - left_bottom_grid_pin_35_ , left_bottom_grid_pin_36_ , - left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , - left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , - left_bottom_grid_pin_41_ , ccff_head , chany_top_out , chanx_right_out , - chany_bottom_out , chanx_left_out , ccff_tail , prog_clk__FEEDTHRU_1 , - Test_en__FEEDTHRU_0 , Test_en__FEEDTHRU_1 , clk__FEEDTHRU_0 , - clk__FEEDTHRU_1 , - grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 , - grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) ; -input [0:0] prog_clk ; -input [0:19] chany_top_in ; -input [0:0] top_left_grid_pin_42_ ; -input [0:0] top_left_grid_pin_43_ ; -input [0:0] top_left_grid_pin_44_ ; -input [0:0] top_left_grid_pin_45_ ; -input [0:0] top_left_grid_pin_46_ ; -input [0:0] top_left_grid_pin_47_ ; -input [0:0] top_left_grid_pin_48_ ; -input [0:0] top_left_grid_pin_49_ ; -input [0:19] chanx_right_in ; -input [0:0] right_bottom_grid_pin_34_ ; -input [0:0] right_bottom_grid_pin_35_ ; -input [0:0] right_bottom_grid_pin_36_ ; -input [0:0] right_bottom_grid_pin_37_ ; -input [0:0] right_bottom_grid_pin_38_ ; -input [0:0] right_bottom_grid_pin_39_ ; -input [0:0] right_bottom_grid_pin_40_ ; -input [0:0] right_bottom_grid_pin_41_ ; -input [0:19] chany_bottom_in ; -input [0:0] bottom_left_grid_pin_42_ ; -input [0:0] bottom_left_grid_pin_43_ ; -input [0:0] bottom_left_grid_pin_44_ ; -input [0:0] bottom_left_grid_pin_45_ ; -input [0:0] bottom_left_grid_pin_46_ ; -input [0:0] bottom_left_grid_pin_47_ ; -input [0:0] bottom_left_grid_pin_48_ ; -input [0:0] bottom_left_grid_pin_49_ ; -input [0:19] chanx_left_in ; -input [0:0] left_bottom_grid_pin_34_ ; -input [0:0] left_bottom_grid_pin_35_ ; -input [0:0] left_bottom_grid_pin_36_ ; -input [0:0] left_bottom_grid_pin_37_ ; -input [0:0] left_bottom_grid_pin_38_ ; -input [0:0] left_bottom_grid_pin_39_ ; -input [0:0] left_bottom_grid_pin_40_ ; -input [0:0] left_bottom_grid_pin_41_ ; -input [0:0] ccff_head ; -output [0:19] chany_top_out ; -output [0:19] chanx_right_out ; -output [0:19] chany_bottom_out ; -output [0:19] chanx_left_out ; -output [0:0] ccff_tail ; -output [0:0] prog_clk__FEEDTHRU_1 ; -input [0:0] Test_en__FEEDTHRU_0 ; -output [0:0] Test_en__FEEDTHRU_1 ; -input [0:0] clk__FEEDTHRU_0 ; -output [0:0] clk__FEEDTHRU_1 ; -input [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ; -output [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ; - -wire [0:3] mux_bottom_track_17_undriven_sram_inv ; -wire [0:3] mux_bottom_track_1_undriven_sram_inv ; -wire [0:3] mux_bottom_track_25_undriven_sram_inv ; -wire [0:2] mux_bottom_track_33_undriven_sram_inv ; -wire [0:3] mux_bottom_track_3_undriven_sram_inv ; -wire [0:4] mux_bottom_track_5_undriven_sram_inv ; -wire [0:3] mux_bottom_track_9_undriven_sram_inv ; -wire [0:3] mux_left_track_17_undriven_sram_inv ; -wire [0:3] mux_left_track_1_undriven_sram_inv ; -wire [0:3] mux_left_track_25_undriven_sram_inv ; -wire [0:2] mux_left_track_33_undriven_sram_inv ; -wire [0:3] mux_left_track_3_undriven_sram_inv ; -wire [0:4] mux_left_track_5_undriven_sram_inv ; -wire [0:3] mux_left_track_9_undriven_sram_inv ; -wire [0:3] mux_right_track_0_undriven_sram_inv ; -wire [0:3] mux_right_track_16_undriven_sram_inv ; -wire [0:3] mux_right_track_24_undriven_sram_inv ; -wire [0:3] mux_right_track_2_undriven_sram_inv ; -wire [0:2] mux_right_track_32_undriven_sram_inv ; -wire [0:4] mux_right_track_4_undriven_sram_inv ; -wire [0:3] mux_right_track_8_undriven_sram_inv ; -wire [0:3] mux_top_track_0_undriven_sram_inv ; -wire [0:3] mux_top_track_16_undriven_sram_inv ; -wire [0:3] mux_top_track_24_undriven_sram_inv ; -wire [0:3] mux_top_track_2_undriven_sram_inv ; -wire [0:2] mux_top_track_32_undriven_sram_inv ; -wire [0:4] mux_top_track_4_undriven_sram_inv ; -wire [0:3] mux_top_track_8_undriven_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_10_sram ; -wire [0:3] mux_tree_tapbuf_size10_11_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:3] mux_tree_tapbuf_size10_2_sram ; -wire [0:3] mux_tree_tapbuf_size10_3_sram ; -wire [0:3] mux_tree_tapbuf_size10_4_sram ; -wire [0:3] mux_tree_tapbuf_size10_5_sram ; -wire [0:3] mux_tree_tapbuf_size10_6_sram ; -wire [0:3] mux_tree_tapbuf_size10_7_sram ; -wire [0:3] mux_tree_tapbuf_size10_8_sram ; -wire [0:3] mux_tree_tapbuf_size10_9_sram ; -wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_10_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_11_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_8_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_9_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size12_0_sram ; -wire [0:3] mux_tree_tapbuf_size12_1_sram ; -wire [0:3] mux_tree_tapbuf_size12_2_sram ; -wire [0:3] mux_tree_tapbuf_size12_3_sram ; -wire [0:3] mux_tree_tapbuf_size12_4_sram ; -wire [0:3] mux_tree_tapbuf_size12_5_sram ; -wire [0:3] mux_tree_tapbuf_size12_6_sram ; -wire [0:3] mux_tree_tapbuf_size12_7_sram ; -wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size12_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size12_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail ; -wire [0:4] mux_tree_tapbuf_size16_0_sram ; -wire [0:4] mux_tree_tapbuf_size16_1_sram ; -wire [0:4] mux_tree_tapbuf_size16_2_sram ; -wire [0:4] mux_tree_tapbuf_size16_3_sram ; -wire [0:0] mux_tree_tapbuf_size16_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size16_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size16_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size16_mem_3_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size7_0_sram ; -wire [0:2] mux_tree_tapbuf_size7_1_sram ; -wire [0:2] mux_tree_tapbuf_size7_2_sram ; -wire [0:2] mux_tree_tapbuf_size7_3_sram ; -wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; -// - -assign clk__FEEDTHRU_1[0] = clk__FEEDTHRU_0[0] ; - -sb_1__1__mux_tree_tapbuf_size12_6 mux_top_track_0 ( - .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , - top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , - chanx_right_in[1] , chanx_right_in[2] , chanx_right_in[12] , - chany_bottom_in[2] , chany_bottom_in[12] , chanx_left_in[0] , - chanx_left_in[2] , chanx_left_in[12] } ) , - .sram ( mux_tree_tapbuf_size12_0_sram ) , - .sram_inv ( mux_top_track_0_undriven_sram_inv ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_145 ) ) ; -sb_1__1__mux_tree_tapbuf_size12 mux_top_track_2 ( - .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , - top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , - chanx_right_in[3] , chanx_right_in[4] , chanx_right_in[13] , - chany_bottom_in[4] , chany_bottom_in[13] , chanx_left_in[4] , - chanx_left_in[13] , chanx_left_in[19] } ) , - .sram ( mux_tree_tapbuf_size12_1_sram ) , - .sram_inv ( mux_top_track_2_undriven_sram_inv ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_149 ) ) ; -sb_1__1__mux_tree_tapbuf_size12_4 mux_right_track_0 ( - .in ( { chany_top_in[2] , chany_top_in[12] , chany_top_in[19] , - right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , - right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , - chany_bottom_in[2] , chany_bottom_in[12] , chany_bottom_in[15] , - chanx_left_in[2] , chanx_left_in[12] } ) , - .sram ( mux_tree_tapbuf_size12_2_sram ) , - .sram_inv ( mux_right_track_0_undriven_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_145 ) ) ; -sb_1__1__mux_tree_tapbuf_size12_5 mux_right_track_2 ( - .in ( { chany_top_in[0] , chany_top_in[4] , chany_top_in[13] , - right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , - right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] , - chany_bottom_in[4] , chany_bottom_in[11] , chany_bottom_in[13] , - chanx_left_in[4] , chanx_left_in[13] } ) , - .sram ( mux_tree_tapbuf_size12_3_sram ) , - .sram_inv ( mux_right_track_2_undriven_sram_inv ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_146 ) ) ; -sb_1__1__mux_tree_tapbuf_size12_0 mux_bottom_track_1 ( - .in ( { chany_top_in[2] , chany_top_in[12] , chanx_right_in[2] , - chanx_right_in[12] , chanx_right_in[15] , - bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , - bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , - chanx_left_in[1] , chanx_left_in[2] , chanx_left_in[12] } ) , - .sram ( mux_tree_tapbuf_size12_4_sram ) , - .sram_inv ( mux_bottom_track_1_undriven_sram_inv ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_147 ) ) ; -sb_1__1__mux_tree_tapbuf_size12_1 mux_bottom_track_3 ( - .in ( { chany_top_in[4] , chany_top_in[13] , chanx_right_in[4] , - chanx_right_in[11] , chanx_right_in[13] , - bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , - bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , - chanx_left_in[3] , chanx_left_in[4] , chanx_left_in[13] } ) , - .sram ( mux_tree_tapbuf_size12_5_sram ) , - .sram_inv ( mux_bottom_track_3_undriven_sram_inv ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_147 ) ) ; -sb_1__1__mux_tree_tapbuf_size12_2 mux_left_track_1 ( - .in ( { chany_top_in[0] , chany_top_in[2] , chany_top_in[12] , - chanx_right_in[2] , chanx_right_in[12] , chany_bottom_in[2] , - chany_bottom_in[12] , chany_bottom_in[19] , - left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , - left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , - .sram ( mux_tree_tapbuf_size12_6_sram ) , - .sram_inv ( mux_left_track_1_undriven_sram_inv ) , - .out ( { ropt_net_158 } ) , - .p0 ( optlc_net_147 ) ) ; -sb_1__1__mux_tree_tapbuf_size12_3 mux_left_track_3 ( - .in ( { chany_top_in[4] , chany_top_in[13] , chany_top_in[19] , - chanx_right_in[4] , chanx_right_in[13] , chany_bottom_in[0] , - chany_bottom_in[4] , chany_bottom_in[13] , - left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , - left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , - .sram ( mux_tree_tapbuf_size12_7_sram ) , - .sram_inv ( mux_left_track_3_undriven_sram_inv ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_148 ) ) ; -sb_1__1__mux_tree_tapbuf_size12_mem_6 mem_top_track_0 ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_0_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size12_mem mem_top_track_2 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_1_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size12_mem_4 mem_right_track_0 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_2_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size12_mem_5 mem_right_track_2 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_3_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size12_mem_0 mem_bottom_track_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_4_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size12_mem_1 mem_bottom_track_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_5_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size12_mem_2 mem_left_track_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_6_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size12_mem_3 mem_left_track_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_7_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size16 mux_top_track_4 ( - .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_43_[0] , - top_left_grid_pin_44_[0] , top_left_grid_pin_45_[0] , - top_left_grid_pin_46_[0] , top_left_grid_pin_47_[0] , - top_left_grid_pin_48_[0] , top_left_grid_pin_49_[0] , - chanx_right_in[5] , chanx_right_in[7] , chanx_right_in[14] , - chany_bottom_in[5] , chany_bottom_in[14] , chanx_left_in[5] , - chanx_left_in[14] , chanx_left_in[15] } ) , - .sram ( mux_tree_tapbuf_size16_0_sram ) , - .sram_inv ( mux_top_track_4_undriven_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_149 ) ) ; -sb_1__1__mux_tree_tapbuf_size16_2 mux_right_track_4 ( - .in ( { chany_top_in[1] , chany_top_in[5] , chany_top_in[14] , - right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_35_[0] , - right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_37_[0] , - right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_39_[0] , - right_bottom_grid_pin_40_[0] , right_bottom_grid_pin_41_[0] , - chany_bottom_in[5] , chany_bottom_in[7] , chany_bottom_in[14] , - chanx_left_in[5] , chanx_left_in[14] } ) , - .sram ( mux_tree_tapbuf_size16_1_sram ) , - .sram_inv ( mux_right_track_4_undriven_sram_inv ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_146 ) ) ; -sb_1__1__mux_tree_tapbuf_size16_0 mux_bottom_track_5 ( - .in ( { chany_top_in[5] , chany_top_in[14] , chanx_right_in[5] , - chanx_right_in[7] , chanx_right_in[14] , bottom_left_grid_pin_42_[0] , - bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_44_[0] , - bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_46_[0] , - bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_48_[0] , - bottom_left_grid_pin_49_[0] , chanx_left_in[5] , chanx_left_in[7] , - chanx_left_in[14] } ) , - .sram ( mux_tree_tapbuf_size16_2_sram ) , - .sram_inv ( mux_bottom_track_5_undriven_sram_inv ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_148 ) ) ; -sb_1__1__mux_tree_tapbuf_size16_1 mux_left_track_5 ( - .in ( { chany_top_in[5] , chany_top_in[14] , chany_top_in[15] , - chanx_right_in[5] , chanx_right_in[14] , chany_bottom_in[1] , - chany_bottom_in[5] , chany_bottom_in[14] , - left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_35_[0] , - left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_37_[0] , - left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_39_[0] , - left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_41_[0] } ) , - .sram ( mux_tree_tapbuf_size16_3_sram ) , - .sram_inv ( mux_left_track_5_undriven_sram_inv ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_148 ) ) ; -sb_1__1__mux_tree_tapbuf_size16_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size16_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size16_0_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size16_mem_2 mem_right_track_4 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size16_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size16_1_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size16_mem_0 mem_bottom_track_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size16_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size16_2_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size16_mem_1 mem_left_track_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size16_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size16_3_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size10 mux_top_track_8 ( - .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_46_[0] , - chanx_right_in[6] , chanx_right_in[11] , chanx_right_in[16] , - chany_bottom_in[6] , chany_bottom_in[16] , chanx_left_in[6] , - chanx_left_in[11] , chanx_left_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_top_track_8_undriven_sram_inv ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_145 ) ) ; -sb_1__1__mux_tree_tapbuf_size10_9 mux_top_track_16 ( - .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_47_[0] , - chanx_right_in[8] , chanx_right_in[15] , chanx_right_in[17] , - chany_bottom_in[8] , chany_bottom_in[17] , chanx_left_in[7] , - chanx_left_in[8] , chanx_left_in[17] } ) , - .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_top_track_16_undriven_sram_inv ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_148 ) ) ; -sb_1__1__mux_tree_tapbuf_size10_10 mux_top_track_24 ( - .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_48_[0] , - chanx_right_in[9] , chanx_right_in[18] , chanx_right_in[19] , - chany_bottom_in[9] , chany_bottom_in[18] , chanx_left_in[3] , - chanx_left_in[9] , chanx_left_in[18] } ) , - .sram ( mux_tree_tapbuf_size10_2_sram ) , - .sram_inv ( mux_top_track_24_undriven_sram_inv ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_145 ) ) ; -sb_1__1__mux_tree_tapbuf_size10_8 mux_right_track_8 ( - .in ( { chany_top_in[3] , chany_top_in[6] , chany_top_in[16] , - right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_38_[0] , - chany_bottom_in[3] , chany_bottom_in[6] , chany_bottom_in[16] , - chanx_left_in[6] , chanx_left_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_3_sram ) , - .sram_inv ( mux_right_track_8_undriven_sram_inv ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_146 ) ) ; -sb_1__1__mux_tree_tapbuf_size10_6 mux_right_track_16 ( - .in ( { chany_top_in[7] , chany_top_in[8] , chany_top_in[17] , - right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_39_[0] , - chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[17] , - chanx_left_in[8] , chanx_left_in[17] } ) , - .sram ( mux_tree_tapbuf_size10_4_sram ) , - .sram_inv ( mux_right_track_16_undriven_sram_inv ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_146 ) ) ; -sb_1__1__mux_tree_tapbuf_size10_7 mux_right_track_24 ( - .in ( { chany_top_in[9] , chany_top_in[11] , chany_top_in[18] , - right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_40_[0] , - chany_bottom_in[0] , chany_bottom_in[9] , chany_bottom_in[18] , - chanx_left_in[9] , chanx_left_in[18] } ) , - .sram ( mux_tree_tapbuf_size10_5_sram ) , - .sram_inv ( mux_right_track_24_undriven_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_145 ) ) ; -sb_1__1__mux_tree_tapbuf_size10_2 mux_bottom_track_9 ( - .in ( { chany_top_in[6] , chany_top_in[16] , chanx_right_in[3] , - chanx_right_in[6] , chanx_right_in[16] , bottom_left_grid_pin_42_[0] , - bottom_left_grid_pin_46_[0] , chanx_left_in[6] , chanx_left_in[11] , - chanx_left_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_6_sram ) , - .sram_inv ( mux_bottom_track_9_undriven_sram_inv ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_147 ) ) ; -sb_1__1__mux_tree_tapbuf_size10_0 mux_bottom_track_17 ( - .in ( { chany_top_in[8] , chany_top_in[17] , chanx_right_in[1] , - chanx_right_in[8] , chanx_right_in[17] , bottom_left_grid_pin_43_[0] , - bottom_left_grid_pin_47_[0] , chanx_left_in[8] , chanx_left_in[15] , - chanx_left_in[17] } ) , - .sram ( mux_tree_tapbuf_size10_7_sram ) , - .sram_inv ( mux_bottom_track_17_undriven_sram_inv ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_146 ) ) ; -sb_1__1__mux_tree_tapbuf_size10_1 mux_bottom_track_25 ( - .in ( { chany_top_in[9] , chany_top_in[18] , chanx_right_in[0] , - chanx_right_in[9] , chanx_right_in[18] , bottom_left_grid_pin_44_[0] , - bottom_left_grid_pin_48_[0] , chanx_left_in[9] , chanx_left_in[18] , - chanx_left_in[19] } ) , - .sram ( mux_tree_tapbuf_size10_8_sram ) , - .sram_inv ( mux_bottom_track_25_undriven_sram_inv ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_145 ) ) ; -sb_1__1__mux_tree_tapbuf_size10_5 mux_left_track_9 ( - .in ( { chany_top_in[6] , chany_top_in[11] , chany_top_in[16] , - chanx_right_in[6] , chanx_right_in[16] , chany_bottom_in[3] , - chany_bottom_in[6] , chany_bottom_in[16] , - left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_38_[0] } ) , - .sram ( mux_tree_tapbuf_size10_9_sram ) , - .sram_inv ( mux_left_track_9_undriven_sram_inv ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_147 ) ) ; -sb_1__1__mux_tree_tapbuf_size10_3 mux_left_track_17 ( - .in ( { chany_top_in[7] , chany_top_in[8] , chany_top_in[17] , - chanx_right_in[8] , chanx_right_in[17] , chany_bottom_in[7] , - chany_bottom_in[8] , chany_bottom_in[17] , - left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_39_[0] } ) , - .sram ( mux_tree_tapbuf_size10_10_sram ) , - .sram_inv ( mux_left_track_17_undriven_sram_inv ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_148 ) ) ; -sb_1__1__mux_tree_tapbuf_size10_4 mux_left_track_25 ( - .in ( { chany_top_in[3] , chany_top_in[9] , chany_top_in[18] , - chanx_right_in[9] , chanx_right_in[18] , chany_bottom_in[9] , - chany_bottom_in[11] , chany_bottom_in[18] , - left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_40_[0] } ) , - .sram ( mux_tree_tapbuf_size10_11_sram ) , - .sram_inv ( mux_left_track_25_undriven_sram_inv ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_147 ) ) ; -sb_1__1__mux_tree_tapbuf_size10_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size16_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size10_mem_9 mem_top_track_16 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size10_mem_10 mem_top_track_24 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size10_mem_8 mem_right_track_8 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size16_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size10_mem_6 mem_right_track_16 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size10_mem_7 mem_right_track_24 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size10_mem_2 mem_bottom_track_9 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size16_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size10_mem_0 mem_bottom_track_17 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size10_mem_1 mem_bottom_track_25 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_8_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size10_mem_5 mem_left_track_9 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size16_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_9_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_9_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size10_mem_3 mem_left_track_17 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_9_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_10_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_10_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size10_mem_4 mem_left_track_25 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_10_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_11_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size7 mux_top_track_32 ( - .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_49_[0] , - chanx_right_in[0] , chanx_right_in[10] , chany_bottom_in[10] , - chanx_left_in[1] , chanx_left_in[10] } ) , - .sram ( mux_tree_tapbuf_size7_0_sram ) , - .sram_inv ( mux_top_track_32_undriven_sram_inv ) , - .out ( chany_top_out[16] ) , .p0 ( optlc_net_145 ) ) ; -sb_1__1__mux_tree_tapbuf_size7_2 mux_right_track_32 ( - .in ( { chany_top_in[10] , chany_top_in[15] , - right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_41_[0] , - chany_bottom_in[10] , chany_bottom_in[19] , chanx_left_in[10] } ) , - .sram ( mux_tree_tapbuf_size7_1_sram ) , - .sram_inv ( mux_right_track_32_undriven_sram_inv ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_146 ) ) ; -sb_1__1__mux_tree_tapbuf_size7_0 mux_bottom_track_33 ( - .in ( { chany_top_in[10] , chanx_right_in[10] , chanx_right_in[19] , - bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_49_[0] , - chanx_left_in[0] , chanx_left_in[10] } ) , - .sram ( mux_tree_tapbuf_size7_2_sram ) , - .sram_inv ( mux_bottom_track_33_undriven_sram_inv ) , - .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_147 ) ) ; -sb_1__1__mux_tree_tapbuf_size7_1 mux_left_track_33 ( - .in ( { chany_top_in[1] , chany_top_in[10] , chanx_right_in[10] , - chany_bottom_in[10] , chany_bottom_in[15] , - left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_41_[0] } ) , - .sram ( mux_tree_tapbuf_size7_3_sram ) , - .sram_inv ( mux_left_track_33_undriven_sram_inv ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_148 ) ) ; -sb_1__1__mux_tree_tapbuf_size7_mem mem_top_track_32 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size7_mem_2 mem_right_track_32 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size7_mem_0 mem_bottom_track_33 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size7_mem_1 mem_left_track_33 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , - .ccff_tail ( { ropt_net_155 } ) , - .mem_out ( mux_tree_tapbuf_size7_3_sram ) ) ; -sky130_fd_sc_hd__conb_1 optlc_140 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_145 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_142 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_146 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__2 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_179 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_top_in[6] ) , - .X ( ropt_net_194 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chany_top_in[8] ) , - .X ( ropt_net_178 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chany_top_in[9] ) , - .X ( ropt_net_170 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_top_in[10] ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chany_top_in[12] ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__8 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_174 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chany_top_in[14] ) , - .X ( ropt_net_196 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__10 ( .A ( chany_top_in[16] ) , - .X ( ropt_net_166 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__11 ( .A ( chany_top_in[17] ) , - .X ( ropt_net_197 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__12 ( .A ( chany_top_in[18] ) , - .X ( ropt_net_189 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_855 ( .A ( ropt_net_200 ) , - .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_144 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_147 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_146 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_148 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , - .HI ( optlc_net_149 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_198 ) ) ; -sky130_fd_sc_hd__clkbuf_1 prog_clk_0__bip415 ( .A ( prog_clk[0] ) , - .X ( ctsbuf_net_1151 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_20__19 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_192 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_right_in[12] ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( chanx_left_in[14] ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_23__22 ( .A ( chanx_right_in[14] ) , - .X ( ropt_net_173 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chanx_right_in[16] ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_25__24 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_184 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_26__25 ( .A ( chanx_right_in[18] ) , - .X ( ropt_net_165 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chany_bottom_in[2] ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_28__27 ( .A ( chany_bottom_in[4] ) , - .X ( ropt_net_171 ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_359774 ( .A ( ctsbuf_net_1151 ) , - .X ( prog_clk__FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_802 ( .A ( chanx_left_in[5] ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_856 ( .A ( ropt_net_201 ) , - .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_32__31 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_187 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_33__32 ( .A ( chany_bottom_in[10] ) , - .X ( ropt_net_193 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_154 ) , - .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_35__34 ( .A ( chany_bottom_in[13] ) , - .X ( ropt_net_199 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_804 ( .A ( ropt_net_155 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_37__36 ( .A ( chany_bottom_in[16] ) , - .X ( ropt_net_186 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_858 ( .A ( ropt_net_202 ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_39__38 ( .A ( chany_bottom_in[18] ) , - .X ( ropt_net_182 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( - .A ( Test_en__FEEDTHRU_0[0] ) , .X ( ropt_net_225 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( chanx_right_in[4] ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_807 ( .A ( ropt_net_158 ) , - .X ( ropt_net_224 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_808 ( .A ( chanx_right_in[5] ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( chanx_right_in[2] ) , - .X ( ropt_net_201 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_810 ( .A ( chany_bottom_in[6] ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_46__45 ( .A ( chanx_left_in[10] ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_47__46 ( .A ( chanx_left_in[12] ) , - .X ( ropt_net_185 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_48__47 ( .A ( chanx_left_in[13] ) , - .X ( ropt_net_169 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_811 ( .A ( chany_bottom_in[5] ) , - .X ( ropt_net_227 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_50__49 ( .A ( chanx_left_in[16] ) , - .X ( ropt_net_181 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_51__50 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_183 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_52__51 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_172 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_860 ( .A ( ropt_net_203 ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_812 ( - .A ( chany_bottom_in[17] ) , .X ( ropt_net_226 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_85 ( .A ( chany_top_in[4] ) , - .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_861 ( .A ( ropt_net_204 ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_862 ( .A ( ropt_net_205 ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_88 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_176 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( chanx_left_in[2] ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_165 ) , - .X ( ropt_net_210 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_91 ( .A ( chany_bottom_in[8] ) , - .X ( ropt_net_154 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_863 ( .A ( ropt_net_206 ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_166 ) , - .X ( ropt_net_223 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_167 ) , - .X ( ropt_net_206 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_95 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_180 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_96 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_177 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_97 ( .A ( chanx_left_in[9] ) , - .X ( ropt_net_168 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_864 ( .A ( ropt_net_207 ) , - .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_817 ( .A ( ropt_net_168 ) , - .X ( ropt_net_220 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_169 ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_170 ) , - .X ( ropt_net_208 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_171 ) , - .X ( ropt_net_200 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_172 ) , - .X ( ropt_net_215 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_108 ( .A ( chanx_left_in[4] ) , - .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_173 ) , - .X ( ropt_net_207 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_174 ) , - .X ( ropt_net_216 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_175 ) , - .X ( ropt_net_204 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_119 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_195 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_120 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_191 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_121 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_167 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_122 ( .A ( chany_bottom_in[12] ) , - .X ( ropt_net_188 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_123 ( .A ( chany_bottom_in[14] ) , - .X ( ropt_net_175 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_865 ( .A ( ropt_net_208 ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( ropt_net_176 ) , - .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_867 ( .A ( ropt_net_209 ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_868 ( .A ( ropt_net_210 ) , - .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_826 ( .A ( ropt_net_177 ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_871 ( .A ( ropt_net_211 ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_875 ( .A ( ropt_net_212 ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_876 ( .A ( ropt_net_213 ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_827 ( .A ( ropt_net_178 ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_136 ( - .A ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] ) , - .X ( ropt_net_190 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_179 ) , - .X ( ropt_net_219 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_829 ( .A ( ropt_net_180 ) , - .X ( ropt_net_209 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_181 ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_182 ) , - .X ( ropt_net_214 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_832 ( .A ( ropt_net_183 ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_833 ( .A ( ropt_net_184 ) , - .X ( ropt_net_222 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_834 ( .A ( ropt_net_185 ) , - .X ( ropt_net_218 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_835 ( .A ( ropt_net_186 ) , - .X ( ropt_net_205 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_836 ( .A ( ropt_net_187 ) , - .X ( ropt_net_211 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_837 ( .A ( ropt_net_188 ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_838 ( .A ( ropt_net_189 ) , - .X ( ropt_net_203 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_839 ( .A ( ropt_net_190 ) , - .X ( ropt_net_221 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_840 ( .A ( ropt_net_191 ) , - .X ( ropt_net_212 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_841 ( .A ( ropt_net_192 ) , - .X ( ropt_net_213 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_842 ( .A ( ropt_net_193 ) , - .X ( ropt_net_217 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_843 ( .A ( ropt_net_194 ) , - .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_844 ( .A ( ropt_net_195 ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_845 ( .A ( ropt_net_196 ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_846 ( .A ( ropt_net_197 ) , - .X ( ropt_net_202 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_849 ( .A ( ropt_net_198 ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_851 ( .A ( ropt_net_199 ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_878 ( .A ( ropt_net_214 ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_880 ( .A ( ropt_net_215 ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_881 ( .A ( ropt_net_216 ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_882 ( .A ( ropt_net_217 ) , - .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_883 ( .A ( ropt_net_218 ) , - .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_885 ( .A ( ropt_net_219 ) , - .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_886 ( .A ( ropt_net_220 ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_887 ( .A ( ropt_net_221 ) , - .X ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_888 ( .A ( ropt_net_222 ) , - .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_890 ( .A ( ropt_net_223 ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_893 ( .A ( ropt_net_224 ) , - .X ( chanx_left_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_897 ( .A ( ropt_net_225 ) , - .X ( Test_en__FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_898 ( .A ( ropt_net_226 ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_899 ( .A ( ropt_net_227 ) , - .X ( chany_top_out[6] ) ) ; -endmodule - - diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__1__icv_in_design.lvs.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__1__icv_in_design.lvs.v deleted file mode 100644 index 02e5af4..0000000 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__1__icv_in_design.lvs.v +++ /dev/null @@ -1,5223 +0,0 @@ -// -// -// -// -// -// -module sb_1__1__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_28__81 ( .A ( mem_out[2] ) , - .X ( net_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_100 ( .A ( net_net_100 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__80 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__79 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__78 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__77 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__76 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__75 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__74 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__73 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__72 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__71 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__70 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_mem_8 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__69 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_mem_10 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__68 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_mem_9 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__67 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__66 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_8 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_10 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_9 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size16_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:4] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__65 ( .A ( mem_out[4] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size16_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:4] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__64 ( .A ( mem_out[4] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size16_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:4] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__63 ( .A ( mem_out[4] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size16_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:4] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__62 ( .A ( mem_out[4] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size16_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:15] in ; -input [0:4] sram ; -input [0:4] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l5_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size16_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:15] in ; -input [0:4] sram ; -input [0:4] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_15_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , - .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_83 ( - .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( BUF_net_83 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_128 ( .A ( BUF_net_83 ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size16_2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:15] in ; -input [0:4] sram ; -input [0:4] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_15_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , - .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size16 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:15] in ; -input [0:4] sram ; -input [0:4] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_15_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , - .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__61 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__60 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__59 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__58 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__57 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__56 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__55 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__54 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_3 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:11] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:11] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_127 ( - .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:11] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:11] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_5 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:11] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_4 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:11] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:11] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_6 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:11] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__1_ ( prog_clk , chany_top_in , top_left_grid_pin_42_ , - top_left_grid_pin_43_ , top_left_grid_pin_44_ , top_left_grid_pin_45_ , - top_left_grid_pin_46_ , top_left_grid_pin_47_ , top_left_grid_pin_48_ , - top_left_grid_pin_49_ , chanx_right_in , right_bottom_grid_pin_34_ , - right_bottom_grid_pin_35_ , right_bottom_grid_pin_36_ , - right_bottom_grid_pin_37_ , right_bottom_grid_pin_38_ , - right_bottom_grid_pin_39_ , right_bottom_grid_pin_40_ , - right_bottom_grid_pin_41_ , chany_bottom_in , bottom_left_grid_pin_42_ , - bottom_left_grid_pin_43_ , bottom_left_grid_pin_44_ , - bottom_left_grid_pin_45_ , bottom_left_grid_pin_46_ , - bottom_left_grid_pin_47_ , bottom_left_grid_pin_48_ , - bottom_left_grid_pin_49_ , chanx_left_in , left_bottom_grid_pin_34_ , - left_bottom_grid_pin_35_ , left_bottom_grid_pin_36_ , - left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , - left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , - left_bottom_grid_pin_41_ , ccff_head , chany_top_out , chanx_right_out , - chany_bottom_out , chanx_left_out , ccff_tail , VDD , VSS , - prog_clk__FEEDTHRU_1 , Test_en__FEEDTHRU_0 , Test_en__FEEDTHRU_1 , - clk__FEEDTHRU_0 , clk__FEEDTHRU_1 , - grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 , - grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) ; -input [0:0] prog_clk ; -input [0:19] chany_top_in ; -input [0:0] top_left_grid_pin_42_ ; -input [0:0] top_left_grid_pin_43_ ; -input [0:0] top_left_grid_pin_44_ ; -input [0:0] top_left_grid_pin_45_ ; -input [0:0] top_left_grid_pin_46_ ; -input [0:0] top_left_grid_pin_47_ ; -input [0:0] top_left_grid_pin_48_ ; -input [0:0] top_left_grid_pin_49_ ; -input [0:19] chanx_right_in ; -input [0:0] right_bottom_grid_pin_34_ ; -input [0:0] right_bottom_grid_pin_35_ ; -input [0:0] right_bottom_grid_pin_36_ ; -input [0:0] right_bottom_grid_pin_37_ ; -input [0:0] right_bottom_grid_pin_38_ ; -input [0:0] right_bottom_grid_pin_39_ ; -input [0:0] right_bottom_grid_pin_40_ ; -input [0:0] right_bottom_grid_pin_41_ ; -input [0:19] chany_bottom_in ; -input [0:0] bottom_left_grid_pin_42_ ; -input [0:0] bottom_left_grid_pin_43_ ; -input [0:0] bottom_left_grid_pin_44_ ; -input [0:0] bottom_left_grid_pin_45_ ; -input [0:0] bottom_left_grid_pin_46_ ; -input [0:0] bottom_left_grid_pin_47_ ; -input [0:0] bottom_left_grid_pin_48_ ; -input [0:0] bottom_left_grid_pin_49_ ; -input [0:19] chanx_left_in ; -input [0:0] left_bottom_grid_pin_34_ ; -input [0:0] left_bottom_grid_pin_35_ ; -input [0:0] left_bottom_grid_pin_36_ ; -input [0:0] left_bottom_grid_pin_37_ ; -input [0:0] left_bottom_grid_pin_38_ ; -input [0:0] left_bottom_grid_pin_39_ ; -input [0:0] left_bottom_grid_pin_40_ ; -input [0:0] left_bottom_grid_pin_41_ ; -input [0:0] ccff_head ; -output [0:19] chany_top_out ; -output [0:19] chanx_right_out ; -output [0:19] chany_bottom_out ; -output [0:19] chanx_left_out ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; -output [0:0] prog_clk__FEEDTHRU_1 ; -input [0:0] Test_en__FEEDTHRU_0 ; -output [0:0] Test_en__FEEDTHRU_1 ; -input [0:0] clk__FEEDTHRU_0 ; -output [0:0] clk__FEEDTHRU_1 ; -input [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ; -output [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ; - -wire [0:3] mux_bottom_track_17_undriven_sram_inv ; -wire [0:3] mux_bottom_track_1_undriven_sram_inv ; -wire [0:3] mux_bottom_track_25_undriven_sram_inv ; -wire [0:2] mux_bottom_track_33_undriven_sram_inv ; -wire [0:3] mux_bottom_track_3_undriven_sram_inv ; -wire [0:4] mux_bottom_track_5_undriven_sram_inv ; -wire [0:3] mux_bottom_track_9_undriven_sram_inv ; -wire [0:3] mux_left_track_17_undriven_sram_inv ; -wire [0:3] mux_left_track_1_undriven_sram_inv ; -wire [0:3] mux_left_track_25_undriven_sram_inv ; -wire [0:2] mux_left_track_33_undriven_sram_inv ; -wire [0:3] mux_left_track_3_undriven_sram_inv ; -wire [0:4] mux_left_track_5_undriven_sram_inv ; -wire [0:3] mux_left_track_9_undriven_sram_inv ; -wire [0:3] mux_right_track_0_undriven_sram_inv ; -wire [0:3] mux_right_track_16_undriven_sram_inv ; -wire [0:3] mux_right_track_24_undriven_sram_inv ; -wire [0:3] mux_right_track_2_undriven_sram_inv ; -wire [0:2] mux_right_track_32_undriven_sram_inv ; -wire [0:4] mux_right_track_4_undriven_sram_inv ; -wire [0:3] mux_right_track_8_undriven_sram_inv ; -wire [0:3] mux_top_track_0_undriven_sram_inv ; -wire [0:3] mux_top_track_16_undriven_sram_inv ; -wire [0:3] mux_top_track_24_undriven_sram_inv ; -wire [0:3] mux_top_track_2_undriven_sram_inv ; -wire [0:2] mux_top_track_32_undriven_sram_inv ; -wire [0:4] mux_top_track_4_undriven_sram_inv ; -wire [0:3] mux_top_track_8_undriven_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_10_sram ; -wire [0:3] mux_tree_tapbuf_size10_11_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:3] mux_tree_tapbuf_size10_2_sram ; -wire [0:3] mux_tree_tapbuf_size10_3_sram ; -wire [0:3] mux_tree_tapbuf_size10_4_sram ; -wire [0:3] mux_tree_tapbuf_size10_5_sram ; -wire [0:3] mux_tree_tapbuf_size10_6_sram ; -wire [0:3] mux_tree_tapbuf_size10_7_sram ; -wire [0:3] mux_tree_tapbuf_size10_8_sram ; -wire [0:3] mux_tree_tapbuf_size10_9_sram ; -wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_10_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_11_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_8_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_9_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size12_0_sram ; -wire [0:3] mux_tree_tapbuf_size12_1_sram ; -wire [0:3] mux_tree_tapbuf_size12_2_sram ; -wire [0:3] mux_tree_tapbuf_size12_3_sram ; -wire [0:3] mux_tree_tapbuf_size12_4_sram ; -wire [0:3] mux_tree_tapbuf_size12_5_sram ; -wire [0:3] mux_tree_tapbuf_size12_6_sram ; -wire [0:3] mux_tree_tapbuf_size12_7_sram ; -wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size12_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size12_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail ; -wire [0:4] mux_tree_tapbuf_size16_0_sram ; -wire [0:4] mux_tree_tapbuf_size16_1_sram ; -wire [0:4] mux_tree_tapbuf_size16_2_sram ; -wire [0:4] mux_tree_tapbuf_size16_3_sram ; -wire [0:0] mux_tree_tapbuf_size16_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size16_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size16_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size16_mem_3_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size7_0_sram ; -wire [0:2] mux_tree_tapbuf_size7_1_sram ; -wire [0:2] mux_tree_tapbuf_size7_2_sram ; -wire [0:2] mux_tree_tapbuf_size7_3_sram ; -wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; -supply1 VDD ; -supply0 VSS ; -// - -assign clk__FEEDTHRU_1[0] = clk__FEEDTHRU_0[0] ; - -sb_1__1__mux_tree_tapbuf_size12_6 mux_top_track_0 ( - .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , - top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , - chanx_right_in[1] , chanx_right_in[2] , chanx_right_in[12] , - chany_bottom_in[2] , chany_bottom_in[12] , chanx_left_in[0] , - chanx_left_in[2] , chanx_left_in[12] } ) , - .sram ( mux_tree_tapbuf_size12_0_sram ) , - .sram_inv ( mux_top_track_0_undriven_sram_inv ) , - .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_145 ) ) ; -sb_1__1__mux_tree_tapbuf_size12 mux_top_track_2 ( - .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , - top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , - chanx_right_in[3] , chanx_right_in[4] , chanx_right_in[13] , - chany_bottom_in[4] , chany_bottom_in[13] , chanx_left_in[4] , - chanx_left_in[13] , chanx_left_in[19] } ) , - .sram ( mux_tree_tapbuf_size12_1_sram ) , - .sram_inv ( mux_top_track_2_undriven_sram_inv ) , - .out ( chany_top_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_149 ) ) ; -sb_1__1__mux_tree_tapbuf_size12_4 mux_right_track_0 ( - .in ( { chany_top_in[2] , chany_top_in[12] , chany_top_in[19] , - right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , - right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , - chany_bottom_in[2] , chany_bottom_in[12] , chany_bottom_in[15] , - chanx_left_in[2] , chanx_left_in[12] } ) , - .sram ( mux_tree_tapbuf_size12_2_sram ) , - .sram_inv ( mux_right_track_0_undriven_sram_inv ) , - .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_145 ) ) ; -sb_1__1__mux_tree_tapbuf_size12_5 mux_right_track_2 ( - .in ( { chany_top_in[0] , chany_top_in[4] , chany_top_in[13] , - right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , - right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] , - chany_bottom_in[4] , chany_bottom_in[11] , chany_bottom_in[13] , - chanx_left_in[4] , chanx_left_in[13] } ) , - .sram ( mux_tree_tapbuf_size12_3_sram ) , - .sram_inv ( mux_right_track_2_undriven_sram_inv ) , - .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_146 ) ) ; -sb_1__1__mux_tree_tapbuf_size12_0 mux_bottom_track_1 ( - .in ( { chany_top_in[2] , chany_top_in[12] , chanx_right_in[2] , - chanx_right_in[12] , chanx_right_in[15] , - bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , - bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , - chanx_left_in[1] , chanx_left_in[2] , chanx_left_in[12] } ) , - .sram ( mux_tree_tapbuf_size12_4_sram ) , - .sram_inv ( mux_bottom_track_1_undriven_sram_inv ) , - .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_147 ) ) ; -sb_1__1__mux_tree_tapbuf_size12_1 mux_bottom_track_3 ( - .in ( { chany_top_in[4] , chany_top_in[13] , chanx_right_in[4] , - chanx_right_in[11] , chanx_right_in[13] , - bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , - bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , - chanx_left_in[3] , chanx_left_in[4] , chanx_left_in[13] } ) , - .sram ( mux_tree_tapbuf_size12_5_sram ) , - .sram_inv ( mux_bottom_track_3_undriven_sram_inv ) , - .out ( chany_bottom_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_147 ) ) ; -sb_1__1__mux_tree_tapbuf_size12_2 mux_left_track_1 ( - .in ( { chany_top_in[0] , chany_top_in[2] , chany_top_in[12] , - chanx_right_in[2] , chanx_right_in[12] , chany_bottom_in[2] , - chany_bottom_in[12] , chany_bottom_in[19] , - left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , - left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , - .sram ( mux_tree_tapbuf_size12_6_sram ) , - .sram_inv ( mux_left_track_1_undriven_sram_inv ) , - .out ( { ropt_net_158 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_147 ) ) ; -sb_1__1__mux_tree_tapbuf_size12_3 mux_left_track_3 ( - .in ( { chany_top_in[4] , chany_top_in[13] , chany_top_in[19] , - chanx_right_in[4] , chanx_right_in[13] , chany_bottom_in[0] , - chany_bottom_in[4] , chany_bottom_in[13] , - left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , - left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , - .sram ( mux_tree_tapbuf_size12_7_sram ) , - .sram_inv ( mux_left_track_3_undriven_sram_inv ) , - .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_148 ) ) ; -sb_1__1__mux_tree_tapbuf_size12_mem_6 mem_top_track_0 ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__1__mux_tree_tapbuf_size12_mem mem_top_track_2 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__1__mux_tree_tapbuf_size12_mem_4 mem_right_track_0 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__1__mux_tree_tapbuf_size12_mem_5 mem_right_track_2 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__1__mux_tree_tapbuf_size12_mem_0 mem_bottom_track_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__1__mux_tree_tapbuf_size12_mem_1 mem_bottom_track_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__1__mux_tree_tapbuf_size12_mem_2 mem_left_track_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__1__mux_tree_tapbuf_size12_mem_3 mem_left_track_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__1__mux_tree_tapbuf_size16 mux_top_track_4 ( - .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_43_[0] , - top_left_grid_pin_44_[0] , top_left_grid_pin_45_[0] , - top_left_grid_pin_46_[0] , top_left_grid_pin_47_[0] , - top_left_grid_pin_48_[0] , top_left_grid_pin_49_[0] , - chanx_right_in[5] , chanx_right_in[7] , chanx_right_in[14] , - chany_bottom_in[5] , chany_bottom_in[14] , chanx_left_in[5] , - chanx_left_in[14] , chanx_left_in[15] } ) , - .sram ( mux_tree_tapbuf_size16_0_sram ) , - .sram_inv ( mux_top_track_4_undriven_sram_inv ) , - .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_149 ) ) ; -sb_1__1__mux_tree_tapbuf_size16_2 mux_right_track_4 ( - .in ( { chany_top_in[1] , chany_top_in[5] , chany_top_in[14] , - right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_35_[0] , - right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_37_[0] , - right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_39_[0] , - right_bottom_grid_pin_40_[0] , right_bottom_grid_pin_41_[0] , - chany_bottom_in[5] , chany_bottom_in[7] , chany_bottom_in[14] , - chanx_left_in[5] , chanx_left_in[14] } ) , - .sram ( mux_tree_tapbuf_size16_1_sram ) , - .sram_inv ( mux_right_track_4_undriven_sram_inv ) , - .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_146 ) ) ; -sb_1__1__mux_tree_tapbuf_size16_0 mux_bottom_track_5 ( - .in ( { chany_top_in[5] , chany_top_in[14] , chanx_right_in[5] , - chanx_right_in[7] , chanx_right_in[14] , bottom_left_grid_pin_42_[0] , - bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_44_[0] , - bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_46_[0] , - bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_48_[0] , - bottom_left_grid_pin_49_[0] , chanx_left_in[5] , chanx_left_in[7] , - chanx_left_in[14] } ) , - .sram ( mux_tree_tapbuf_size16_2_sram ) , - .sram_inv ( mux_bottom_track_5_undriven_sram_inv ) , - .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_148 ) ) ; -sb_1__1__mux_tree_tapbuf_size16_1 mux_left_track_5 ( - .in ( { chany_top_in[5] , chany_top_in[14] , chany_top_in[15] , - chanx_right_in[5] , chanx_right_in[14] , chany_bottom_in[1] , - chany_bottom_in[5] , chany_bottom_in[14] , - left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_35_[0] , - left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_37_[0] , - left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_39_[0] , - left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_41_[0] } ) , - .sram ( mux_tree_tapbuf_size16_3_sram ) , - .sram_inv ( mux_left_track_5_undriven_sram_inv ) , - .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_148 ) ) ; -sb_1__1__mux_tree_tapbuf_size16_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size16_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size16_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__1__mux_tree_tapbuf_size16_mem_2 mem_right_track_4 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size16_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size16_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__1__mux_tree_tapbuf_size16_mem_0 mem_bottom_track_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size16_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size16_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__1__mux_tree_tapbuf_size16_mem_1 mem_left_track_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size16_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size16_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__1__mux_tree_tapbuf_size10 mux_top_track_8 ( - .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_46_[0] , - chanx_right_in[6] , chanx_right_in[11] , chanx_right_in[16] , - chany_bottom_in[6] , chany_bottom_in[16] , chanx_left_in[6] , - chanx_left_in[11] , chanx_left_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_top_track_8_undriven_sram_inv ) , - .out ( chany_top_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_145 ) ) ; -sb_1__1__mux_tree_tapbuf_size10_9 mux_top_track_16 ( - .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_47_[0] , - chanx_right_in[8] , chanx_right_in[15] , chanx_right_in[17] , - chany_bottom_in[8] , chany_bottom_in[17] , chanx_left_in[7] , - chanx_left_in[8] , chanx_left_in[17] } ) , - .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_top_track_16_undriven_sram_inv ) , - .out ( chany_top_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_148 ) ) ; -sb_1__1__mux_tree_tapbuf_size10_10 mux_top_track_24 ( - .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_48_[0] , - chanx_right_in[9] , chanx_right_in[18] , chanx_right_in[19] , - chany_bottom_in[9] , chany_bottom_in[18] , chanx_left_in[3] , - chanx_left_in[9] , chanx_left_in[18] } ) , - .sram ( mux_tree_tapbuf_size10_2_sram ) , - .sram_inv ( mux_top_track_24_undriven_sram_inv ) , - .out ( chany_top_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_145 ) ) ; -sb_1__1__mux_tree_tapbuf_size10_8 mux_right_track_8 ( - .in ( { chany_top_in[3] , chany_top_in[6] , chany_top_in[16] , - right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_38_[0] , - chany_bottom_in[3] , chany_bottom_in[6] , chany_bottom_in[16] , - chanx_left_in[6] , chanx_left_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_3_sram ) , - .sram_inv ( mux_right_track_8_undriven_sram_inv ) , - .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_146 ) ) ; -sb_1__1__mux_tree_tapbuf_size10_6 mux_right_track_16 ( - .in ( { chany_top_in[7] , chany_top_in[8] , chany_top_in[17] , - right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_39_[0] , - chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[17] , - chanx_left_in[8] , chanx_left_in[17] } ) , - .sram ( mux_tree_tapbuf_size10_4_sram ) , - .sram_inv ( mux_right_track_16_undriven_sram_inv ) , - .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_146 ) ) ; -sb_1__1__mux_tree_tapbuf_size10_7 mux_right_track_24 ( - .in ( { chany_top_in[9] , chany_top_in[11] , chany_top_in[18] , - right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_40_[0] , - chany_bottom_in[0] , chany_bottom_in[9] , chany_bottom_in[18] , - chanx_left_in[9] , chanx_left_in[18] } ) , - .sram ( mux_tree_tapbuf_size10_5_sram ) , - .sram_inv ( mux_right_track_24_undriven_sram_inv ) , - .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_145 ) ) ; -sb_1__1__mux_tree_tapbuf_size10_2 mux_bottom_track_9 ( - .in ( { chany_top_in[6] , chany_top_in[16] , chanx_right_in[3] , - chanx_right_in[6] , chanx_right_in[16] , bottom_left_grid_pin_42_[0] , - bottom_left_grid_pin_46_[0] , chanx_left_in[6] , chanx_left_in[11] , - chanx_left_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_6_sram ) , - .sram_inv ( mux_bottom_track_9_undriven_sram_inv ) , - .out ( chany_bottom_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_147 ) ) ; -sb_1__1__mux_tree_tapbuf_size10_0 mux_bottom_track_17 ( - .in ( { chany_top_in[8] , chany_top_in[17] , chanx_right_in[1] , - chanx_right_in[8] , chanx_right_in[17] , bottom_left_grid_pin_43_[0] , - bottom_left_grid_pin_47_[0] , chanx_left_in[8] , chanx_left_in[15] , - chanx_left_in[17] } ) , - .sram ( mux_tree_tapbuf_size10_7_sram ) , - .sram_inv ( mux_bottom_track_17_undriven_sram_inv ) , - .out ( chany_bottom_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_146 ) ) ; -sb_1__1__mux_tree_tapbuf_size10_1 mux_bottom_track_25 ( - .in ( { chany_top_in[9] , chany_top_in[18] , chanx_right_in[0] , - chanx_right_in[9] , chanx_right_in[18] , bottom_left_grid_pin_44_[0] , - bottom_left_grid_pin_48_[0] , chanx_left_in[9] , chanx_left_in[18] , - chanx_left_in[19] } ) , - .sram ( mux_tree_tapbuf_size10_8_sram ) , - .sram_inv ( mux_bottom_track_25_undriven_sram_inv ) , - .out ( chany_bottom_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_145 ) ) ; -sb_1__1__mux_tree_tapbuf_size10_5 mux_left_track_9 ( - .in ( { chany_top_in[6] , chany_top_in[11] , chany_top_in[16] , - chanx_right_in[6] , chanx_right_in[16] , chany_bottom_in[3] , - chany_bottom_in[6] , chany_bottom_in[16] , - left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_38_[0] } ) , - .sram ( mux_tree_tapbuf_size10_9_sram ) , - .sram_inv ( mux_left_track_9_undriven_sram_inv ) , - .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_147 ) ) ; -sb_1__1__mux_tree_tapbuf_size10_3 mux_left_track_17 ( - .in ( { chany_top_in[7] , chany_top_in[8] , chany_top_in[17] , - chanx_right_in[8] , chanx_right_in[17] , chany_bottom_in[7] , - chany_bottom_in[8] , chany_bottom_in[17] , - left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_39_[0] } ) , - .sram ( mux_tree_tapbuf_size10_10_sram ) , - .sram_inv ( mux_left_track_17_undriven_sram_inv ) , - .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_148 ) ) ; -sb_1__1__mux_tree_tapbuf_size10_4 mux_left_track_25 ( - .in ( { chany_top_in[3] , chany_top_in[9] , chany_top_in[18] , - chanx_right_in[9] , chanx_right_in[18] , chany_bottom_in[9] , - chany_bottom_in[11] , chany_bottom_in[18] , - left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_40_[0] } ) , - .sram ( mux_tree_tapbuf_size10_11_sram ) , - .sram_inv ( mux_left_track_25_undriven_sram_inv ) , - .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_147 ) ) ; -sb_1__1__mux_tree_tapbuf_size10_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size16_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__1__mux_tree_tapbuf_size10_mem_9 mem_top_track_16 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__1__mux_tree_tapbuf_size10_mem_10 mem_top_track_24 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__1__mux_tree_tapbuf_size10_mem_8 mem_right_track_8 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size16_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__1__mux_tree_tapbuf_size10_mem_6 mem_right_track_16 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__1__mux_tree_tapbuf_size10_mem_7 mem_right_track_24 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__1__mux_tree_tapbuf_size10_mem_2 mem_bottom_track_9 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size16_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__1__mux_tree_tapbuf_size10_mem_0 mem_bottom_track_17 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__1__mux_tree_tapbuf_size10_mem_1 mem_bottom_track_25 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_8_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__1__mux_tree_tapbuf_size10_mem_5 mem_left_track_9 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size16_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_9_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_9_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__1__mux_tree_tapbuf_size10_mem_3 mem_left_track_17 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_9_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_10_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_10_sram ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -sb_1__1__mux_tree_tapbuf_size10_mem_4 mem_left_track_25 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_10_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_11_sram ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -sb_1__1__mux_tree_tapbuf_size7 mux_top_track_32 ( - .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_49_[0] , - chanx_right_in[0] , chanx_right_in[10] , chany_bottom_in[10] , - chanx_left_in[1] , chanx_left_in[10] } ) , - .sram ( mux_tree_tapbuf_size7_0_sram ) , - .sram_inv ( mux_top_track_32_undriven_sram_inv ) , - .out ( chany_top_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_145 ) ) ; -sb_1__1__mux_tree_tapbuf_size7_2 mux_right_track_32 ( - .in ( { chany_top_in[10] , chany_top_in[15] , - right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_41_[0] , - chany_bottom_in[10] , chany_bottom_in[19] , chanx_left_in[10] } ) , - .sram ( mux_tree_tapbuf_size7_1_sram ) , - .sram_inv ( mux_right_track_32_undriven_sram_inv ) , - .out ( chanx_right_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_146 ) ) ; -sb_1__1__mux_tree_tapbuf_size7_0 mux_bottom_track_33 ( - .in ( { chany_top_in[10] , chanx_right_in[10] , chanx_right_in[19] , - bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_49_[0] , - chanx_left_in[0] , chanx_left_in[10] } ) , - .sram ( mux_tree_tapbuf_size7_2_sram ) , - .sram_inv ( mux_bottom_track_33_undriven_sram_inv ) , - .out ( chany_bottom_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_147 ) ) ; -sb_1__1__mux_tree_tapbuf_size7_1 mux_left_track_33 ( - .in ( { chany_top_in[1] , chany_top_in[10] , chanx_right_in[10] , - chany_bottom_in[10] , chany_bottom_in[15] , - left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_41_[0] } ) , - .sram ( mux_tree_tapbuf_size7_3_sram ) , - .sram_inv ( mux_left_track_33_undriven_sram_inv ) , - .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_148 ) ) ; -sb_1__1__mux_tree_tapbuf_size7_mem mem_top_track_32 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__1__mux_tree_tapbuf_size7_mem_2 mem_right_track_32 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__1__mux_tree_tapbuf_size7_mem_0 mem_bottom_track_33 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__1__mux_tree_tapbuf_size7_mem_1 mem_left_track_33 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , - .ccff_tail ( { ropt_net_155 } ) , - .mem_out ( mux_tree_tapbuf_size7_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1379 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1380 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1381 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1382 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1383 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1384 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1385 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1386 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1387 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1388 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1389 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1390 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1391 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1392 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1393 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1394 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1395 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1396 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1397 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1398 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1399 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1400 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1401 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1402 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1403 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1404 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1405 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1406 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1407 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1408 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1409 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1410 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1411 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1412 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1413 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1414 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1415 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1416 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1417 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1418 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1419 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1420 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__conb_1 optlc_140 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_142 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__2 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_179 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_top_in[6] ) , - .X ( ropt_net_194 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chany_top_in[8] ) , - .X ( ropt_net_178 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chany_top_in[9] ) , - .X ( ropt_net_170 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_top_in[10] ) , - .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chany_top_in[12] ) , - .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__8 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_174 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chany_top_in[14] ) , - .X ( ropt_net_196 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__10 ( .A ( chany_top_in[16] ) , - .X ( ropt_net_166 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__11 ( .A ( chany_top_in[17] ) , - .X ( ropt_net_197 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__12 ( .A ( chany_top_in[18] ) , - .X ( ropt_net_189 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_855 ( .A ( ropt_net_200 ) , - .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_144 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_146 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , - .HI ( optlc_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_198 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__clkbuf_1 prog_clk_0__bip415 ( .A ( prog_clk[0] ) , - .X ( ctsbuf_net_1151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_20__19 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_192 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_right_in[12] ) , - .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( chanx_left_in[14] ) , - .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_23__22 ( .A ( chanx_right_in[14] ) , - .X ( ropt_net_173 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chanx_right_in[16] ) , - .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_25__24 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_184 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_26__25 ( .A ( chanx_right_in[18] ) , - .X ( ropt_net_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chany_bottom_in[2] ) , - .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_28__27 ( .A ( chany_bottom_in[4] ) , - .X ( ropt_net_171 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_359774 ( .A ( ctsbuf_net_1151 ) , - .X ( prog_clk__FEEDTHRU_1[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_802 ( .A ( chanx_left_in[5] ) , - .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_856 ( .A ( ropt_net_201 ) , - .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_32__31 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_33__32 ( .A ( chany_bottom_in[10] ) , - .X ( ropt_net_193 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_154 ) , - .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_35__34 ( .A ( chany_bottom_in[13] ) , - .X ( ropt_net_199 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_804 ( .A ( ropt_net_155 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_37__36 ( .A ( chany_bottom_in[16] ) , - .X ( ropt_net_186 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_858 ( .A ( ropt_net_202 ) , - .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_39__38 ( .A ( chany_bottom_in[18] ) , - .X ( ropt_net_182 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( - .A ( Test_en__FEEDTHRU_0[0] ) , .X ( ropt_net_225 ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( chanx_right_in[4] ) , - .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_807 ( .A ( ropt_net_158 ) , - .X ( ropt_net_224 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_808 ( .A ( chanx_right_in[5] ) , - .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( chanx_right_in[2] ) , - .X ( ropt_net_201 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_810 ( .A ( chany_bottom_in[6] ) , - .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_46__45 ( .A ( chanx_left_in[10] ) , - .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_47__46 ( .A ( chanx_left_in[12] ) , - .X ( ropt_net_185 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_48__47 ( .A ( chanx_left_in[13] ) , - .X ( ropt_net_169 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_811 ( .A ( chany_bottom_in[5] ) , - .X ( ropt_net_227 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_50__49 ( .A ( chanx_left_in[16] ) , - .X ( ropt_net_181 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_51__50 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_183 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_52__51 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_172 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_860 ( .A ( ropt_net_203 ) , - .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_812 ( - .A ( chany_bottom_in[17] ) , .X ( ropt_net_226 ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_85 ( .A ( chany_top_in[4] ) , - .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_861 ( .A ( ropt_net_204 ) , - .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_862 ( .A ( ropt_net_205 ) , - .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_88 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_176 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( chanx_left_in[2] ) , - .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_165 ) , - .X ( ropt_net_210 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_91 ( .A ( chany_bottom_in[8] ) , - .X ( ropt_net_154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_863 ( .A ( ropt_net_206 ) , - .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_166 ) , - .X ( ropt_net_223 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_167 ) , - .X ( ropt_net_206 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_95 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_180 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_96 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_177 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_97 ( .A ( chanx_left_in[9] ) , - .X ( ropt_net_168 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_864 ( .A ( ropt_net_207 ) , - .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_817 ( .A ( ropt_net_168 ) , - .X ( ropt_net_220 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_169 ) , - .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_170 ) , - .X ( ropt_net_208 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_171 ) , - .X ( ropt_net_200 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_172 ) , - .X ( ropt_net_215 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_108 ( .A ( chanx_left_in[4] ) , - .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_173 ) , - .X ( ropt_net_207 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_174 ) , - .X ( ropt_net_216 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_175 ) , - .X ( ropt_net_204 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_119 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_195 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_120 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_191 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_121 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_167 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_122 ( .A ( chany_bottom_in[12] ) , - .X ( ropt_net_188 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_123 ( .A ( chany_bottom_in[14] ) , - .X ( ropt_net_175 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_865 ( .A ( ropt_net_208 ) , - .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( ropt_net_176 ) , - .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_867 ( .A ( ropt_net_209 ) , - .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_868 ( .A ( ropt_net_210 ) , - .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_826 ( .A ( ropt_net_177 ) , - .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_871 ( .A ( ropt_net_211 ) , - .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_875 ( .A ( ropt_net_212 ) , - .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_876 ( .A ( ropt_net_213 ) , - .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_827 ( .A ( ropt_net_178 ) , - .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_136 ( - .A ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] ) , - .X ( ropt_net_190 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_179 ) , - .X ( ropt_net_219 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_829 ( .A ( ropt_net_180 ) , - .X ( ropt_net_209 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_181 ) , - .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_182 ) , - .X ( ropt_net_214 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_832 ( .A ( ropt_net_183 ) , - .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_833 ( .A ( ropt_net_184 ) , - .X ( ropt_net_222 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_834 ( .A ( ropt_net_185 ) , - .X ( ropt_net_218 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_835 ( .A ( ropt_net_186 ) , - .X ( ropt_net_205 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_836 ( .A ( ropt_net_187 ) , - .X ( ropt_net_211 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_837 ( .A ( ropt_net_188 ) , - .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_838 ( .A ( ropt_net_189 ) , - .X ( ropt_net_203 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_839 ( .A ( ropt_net_190 ) , - .X ( ropt_net_221 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_840 ( .A ( ropt_net_191 ) , - .X ( ropt_net_212 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_841 ( .A ( ropt_net_192 ) , - .X ( ropt_net_213 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_842 ( .A ( ropt_net_193 ) , - .X ( ropt_net_217 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_843 ( .A ( ropt_net_194 ) , - .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_844 ( .A ( ropt_net_195 ) , - .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_845 ( .A ( ropt_net_196 ) , - .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_846 ( .A ( ropt_net_197 ) , - .X ( ropt_net_202 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_849 ( .A ( ropt_net_198 ) , - .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_851 ( .A ( ropt_net_199 ) , - .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_878 ( .A ( ropt_net_214 ) , - .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_880 ( .A ( ropt_net_215 ) , - .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_881 ( .A ( ropt_net_216 ) , - .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_882 ( .A ( ropt_net_217 ) , - .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_883 ( .A ( ropt_net_218 ) , - .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_885 ( .A ( ropt_net_219 ) , - .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_886 ( .A ( ropt_net_220 ) , - .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_887 ( .A ( ropt_net_221 ) , - .X ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_888 ( .A ( ropt_net_222 ) , - .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_890 ( .A ( ropt_net_223 ) , - .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_893 ( .A ( ropt_net_224 ) , - .X ( chanx_left_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_897 ( .A ( ropt_net_225 ) , - .X ( Test_en__FEEDTHRU_1[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_898 ( .A ( ropt_net_226 ) , - .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_899 ( .A ( ropt_net_227 ) , - .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y0 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y0 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x326600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x892400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x358800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x892400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x345000y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x441600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x492200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x510600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x519800y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x598000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x607200y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1145400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1163800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1173000y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x92000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x142600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x151800y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x197800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x248400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x299000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x335800y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x391000y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x437000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x446200y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x524400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x542800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x552000y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x630200y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x717600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x726800y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x993600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1044200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1094800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1145400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1163800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1173000y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x147200y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x193200y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x239200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x358800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x377200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x423200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x441600y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x487600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x506000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x552000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x602600y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x644000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x694600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x786600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x906200y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x952200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x961400y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1007400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1058000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1094800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1131600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x92000y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x138000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x174800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x211600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x230000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x299000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x492200y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x607200y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x685400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x694600y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x777400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x795800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x846400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x892400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x910800y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1067200y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1113200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x128800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x138000y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x312800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x381800y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x478400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x529000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x579600y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x625600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x722200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x851000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x887800y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x966000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1016600y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1104000y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x36800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x184000y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x230000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x432400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x441600y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x487600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x496800y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x579600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x588800y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x676200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x685400y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x731400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x740600y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x892400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x36800y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x78200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x87400y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x216200y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x262200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x299000y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x377200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x455400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x492200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x529000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x588800y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x754400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x837200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x887800y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x933800y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x979800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1030400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1048800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1058000y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1099400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1136200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1173000y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x101200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x138000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x174800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x211600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x248400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x257600y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x303600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x340400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x432400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x450800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x460000y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x506000y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x630200y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x676200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x713000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x749800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x768200y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x814200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x823400y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x869400y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x947600y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x110400y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x239200y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x460000y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x506000y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x588800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x639400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x717600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x768200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x805000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x814200y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x860200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x887800y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x933800y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x979800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1067200y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1145400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1163800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1173000y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x184000y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x262200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x363400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x473800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x510600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x529000y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x547400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x598000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x616400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x625600y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x722200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x731400y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x777400y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x823400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x998200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1016600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x188600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x225400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x271400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x308200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x345000y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x391000y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x437000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x515200y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x860200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x887800y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1007400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1025800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x105800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x115000y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x161000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x170200y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x248400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x285200y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x363400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x519800y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x565800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x616400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x634800y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x676200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x694600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x786600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x920000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1016600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1025800y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x73600y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x119600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x138000y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x216200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x276000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x409400y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x455400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x492200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x565800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x602600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x639400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x722200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x740600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x749800y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x795800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x814200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x887800y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x961400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1071800y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x73600y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x216200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x253000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x303600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x322000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x418600y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x588800y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x713000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x722200y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x768200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x777400y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x823400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x860200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x984400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x271400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x289800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x556600y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x602600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x657800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x694600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x713000y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x791200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x193200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x230000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x248400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x257600y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x303600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x312800y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x358800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x515200y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x561200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x570400y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x616400y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x662400y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x708400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x717600y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x814200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x897000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x975200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x299000y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x345000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x381800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x441600y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x529000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x579600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x598000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x740600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x759000y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x805000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1012000y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x188600y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x234600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x285200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x294400y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x501400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x510600y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x556600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x680800y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x795800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x878600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x915400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1016600y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x174800y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x220800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x303600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x340400y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x460000y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x506000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x524400y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x570400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x621000y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x828000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1085600y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x105800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x115000y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x202400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x239200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x322000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x340400y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x469200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x556600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x565800y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x611800y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x699200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x708400y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x749800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x786600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x823400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x860200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x869400y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x947600y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1025800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1044200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1053400y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x87400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x105800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x156400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x193200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x253000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x289800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x299000y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x345000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x510600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x519800y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x565800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x602600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x639400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x740600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x749800y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x887800y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x970600y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1016600y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x101200y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x326600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x335800y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x538200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x556600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x607200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x657800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x694600y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x846400y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x892400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x929200y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x975200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x993600y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x73600y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x110400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x119600y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x165600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x211600y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x358800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x478400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x644000y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x690000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x749800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x759000y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x805000y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x851000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x956800y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x220800y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x312800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x331200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x340400y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x400200y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x671600y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x717600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x736000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x745200y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x791200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x809600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x860200y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x906200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x924600y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x970600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x989000y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1071800y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x165600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x225400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x271400y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x317400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x326600y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x460000y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x506000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x524400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x575000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x699200y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x777400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x887800y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x933800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x998200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1016600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1025800y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x193200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x271400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x308200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x326600y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x473800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x483000y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x565800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x630200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x680800y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x699200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x717600y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x832600y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x966000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x984400y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1030400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1122400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1159200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x82800y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x395600y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x441600y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x487600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x538200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x722200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x731400y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x814200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x823400y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x906200y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x993600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1076400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1094800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1136200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1173000y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x147200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x165600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x257600y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x345000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x538200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x588800y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x731400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x768200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x777400y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x823400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x841800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x851000y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x989000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1090200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1136200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1173000y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x119600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x128800y870400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x207000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x243800y870400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x289800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x326600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x335800y870400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x561200y870400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x639400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x648600y870400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x694600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x713000y870400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x759000y870400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x805000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x814200y870400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x860200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x970600y870400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1163800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1173000y870400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x285200y897600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y897600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x473800y897600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x519800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x602600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x621000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x680800y897600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x924600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y897600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x92000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x142600y924800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x188600y924800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x432400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x607200y924800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x726800y924800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y924800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x961400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1062600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1099400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1136200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1173000y924800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x335800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x400200y952000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x892400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x929200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x966000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1002800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1039600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1076400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1113200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x331200y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x423200y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x460000y979200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y979200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x358800y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y1006400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x400200y1006400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x432400y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x892400y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x285200y1033600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y1033600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y1060800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y1060800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__1__icv_in_design.pt.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__1__icv_in_design.pt.v deleted file mode 100644 index bfc1ff6..0000000 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__1__icv_in_design.pt.v +++ /dev/null @@ -1,2927 +0,0 @@ -// -// -// -// -// -// -module sb_1__1__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_28__81 ( .A ( mem_out[2] ) , - .X ( net_net_100 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_100 ( .A ( net_net_100 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__80 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__79 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__78 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__77 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__76 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__75 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__74 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__73 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__72 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__71 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__70 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_mem_8 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__69 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_mem_10 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__68 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_mem_9 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__67 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__66 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_8 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_10 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10_9 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size16_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:4] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__65 ( .A ( mem_out[4] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size16_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:4] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__64 ( .A ( mem_out[4] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size16_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:4] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__63 ( .A ( mem_out[4] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size16_mem ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:4] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__62 ( .A ( mem_out[4] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size16_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:15] in ; -input [0:4] sram ; -input [0:4] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l5_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size16_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:15] in ; -input [0:4] sram ; -input [0:4] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_15_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , - .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_83 ( - .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( BUF_net_83 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_128 ( .A ( BUF_net_83 ) , - .X ( out[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size16_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:15] in ; -input [0:4] sram ; -input [0:4] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_15_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , - .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size16 ( in , sram , sram_inv , out , p0 ) ; -input [0:15] in ; -input [0:4] sram ; -input [0:4] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_15_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , - .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__61 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__60 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__59 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__58 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__57 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__56 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_mem ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__55 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__54 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:11] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:11] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_127 ( - .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:11] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:11] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:11] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:11] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12 ( in , sram , sram_inv , out , p0 ) ; -input [0:11] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -endmodule - - -module sb_1__1__mux_tree_tapbuf_size12_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:11] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -endmodule - - -module sb_1__1_ ( prog_clk , chany_top_in , top_left_grid_pin_42_ , - top_left_grid_pin_43_ , top_left_grid_pin_44_ , top_left_grid_pin_45_ , - top_left_grid_pin_46_ , top_left_grid_pin_47_ , top_left_grid_pin_48_ , - top_left_grid_pin_49_ , chanx_right_in , right_bottom_grid_pin_34_ , - right_bottom_grid_pin_35_ , right_bottom_grid_pin_36_ , - right_bottom_grid_pin_37_ , right_bottom_grid_pin_38_ , - right_bottom_grid_pin_39_ , right_bottom_grid_pin_40_ , - right_bottom_grid_pin_41_ , chany_bottom_in , bottom_left_grid_pin_42_ , - bottom_left_grid_pin_43_ , bottom_left_grid_pin_44_ , - bottom_left_grid_pin_45_ , bottom_left_grid_pin_46_ , - bottom_left_grid_pin_47_ , bottom_left_grid_pin_48_ , - bottom_left_grid_pin_49_ , chanx_left_in , left_bottom_grid_pin_34_ , - left_bottom_grid_pin_35_ , left_bottom_grid_pin_36_ , - left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , - left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , - left_bottom_grid_pin_41_ , ccff_head , chany_top_out , chanx_right_out , - chany_bottom_out , chanx_left_out , ccff_tail , prog_clk__FEEDTHRU_1 , - Test_en__FEEDTHRU_0 , Test_en__FEEDTHRU_1 , clk__FEEDTHRU_0 , - clk__FEEDTHRU_1 , - grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 , - grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) ; -input [0:0] prog_clk ; -input [0:19] chany_top_in ; -input [0:0] top_left_grid_pin_42_ ; -input [0:0] top_left_grid_pin_43_ ; -input [0:0] top_left_grid_pin_44_ ; -input [0:0] top_left_grid_pin_45_ ; -input [0:0] top_left_grid_pin_46_ ; -input [0:0] top_left_grid_pin_47_ ; -input [0:0] top_left_grid_pin_48_ ; -input [0:0] top_left_grid_pin_49_ ; -input [0:19] chanx_right_in ; -input [0:0] right_bottom_grid_pin_34_ ; -input [0:0] right_bottom_grid_pin_35_ ; -input [0:0] right_bottom_grid_pin_36_ ; -input [0:0] right_bottom_grid_pin_37_ ; -input [0:0] right_bottom_grid_pin_38_ ; -input [0:0] right_bottom_grid_pin_39_ ; -input [0:0] right_bottom_grid_pin_40_ ; -input [0:0] right_bottom_grid_pin_41_ ; -input [0:19] chany_bottom_in ; -input [0:0] bottom_left_grid_pin_42_ ; -input [0:0] bottom_left_grid_pin_43_ ; -input [0:0] bottom_left_grid_pin_44_ ; -input [0:0] bottom_left_grid_pin_45_ ; -input [0:0] bottom_left_grid_pin_46_ ; -input [0:0] bottom_left_grid_pin_47_ ; -input [0:0] bottom_left_grid_pin_48_ ; -input [0:0] bottom_left_grid_pin_49_ ; -input [0:19] chanx_left_in ; -input [0:0] left_bottom_grid_pin_34_ ; -input [0:0] left_bottom_grid_pin_35_ ; -input [0:0] left_bottom_grid_pin_36_ ; -input [0:0] left_bottom_grid_pin_37_ ; -input [0:0] left_bottom_grid_pin_38_ ; -input [0:0] left_bottom_grid_pin_39_ ; -input [0:0] left_bottom_grid_pin_40_ ; -input [0:0] left_bottom_grid_pin_41_ ; -input [0:0] ccff_head ; -output [0:19] chany_top_out ; -output [0:19] chanx_right_out ; -output [0:19] chany_bottom_out ; -output [0:19] chanx_left_out ; -output [0:0] ccff_tail ; -output [0:0] prog_clk__FEEDTHRU_1 ; -input [0:0] Test_en__FEEDTHRU_0 ; -output [0:0] Test_en__FEEDTHRU_1 ; -input [0:0] clk__FEEDTHRU_0 ; -output [0:0] clk__FEEDTHRU_1 ; -input [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ; -output [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ; - -wire [0:3] mux_bottom_track_17_undriven_sram_inv ; -wire [0:3] mux_bottom_track_1_undriven_sram_inv ; -wire [0:3] mux_bottom_track_25_undriven_sram_inv ; -wire [0:2] mux_bottom_track_33_undriven_sram_inv ; -wire [0:3] mux_bottom_track_3_undriven_sram_inv ; -wire [0:4] mux_bottom_track_5_undriven_sram_inv ; -wire [0:3] mux_bottom_track_9_undriven_sram_inv ; -wire [0:3] mux_left_track_17_undriven_sram_inv ; -wire [0:3] mux_left_track_1_undriven_sram_inv ; -wire [0:3] mux_left_track_25_undriven_sram_inv ; -wire [0:2] mux_left_track_33_undriven_sram_inv ; -wire [0:3] mux_left_track_3_undriven_sram_inv ; -wire [0:4] mux_left_track_5_undriven_sram_inv ; -wire [0:3] mux_left_track_9_undriven_sram_inv ; -wire [0:3] mux_right_track_0_undriven_sram_inv ; -wire [0:3] mux_right_track_16_undriven_sram_inv ; -wire [0:3] mux_right_track_24_undriven_sram_inv ; -wire [0:3] mux_right_track_2_undriven_sram_inv ; -wire [0:2] mux_right_track_32_undriven_sram_inv ; -wire [0:4] mux_right_track_4_undriven_sram_inv ; -wire [0:3] mux_right_track_8_undriven_sram_inv ; -wire [0:3] mux_top_track_0_undriven_sram_inv ; -wire [0:3] mux_top_track_16_undriven_sram_inv ; -wire [0:3] mux_top_track_24_undriven_sram_inv ; -wire [0:3] mux_top_track_2_undriven_sram_inv ; -wire [0:2] mux_top_track_32_undriven_sram_inv ; -wire [0:4] mux_top_track_4_undriven_sram_inv ; -wire [0:3] mux_top_track_8_undriven_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_10_sram ; -wire [0:3] mux_tree_tapbuf_size10_11_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:3] mux_tree_tapbuf_size10_2_sram ; -wire [0:3] mux_tree_tapbuf_size10_3_sram ; -wire [0:3] mux_tree_tapbuf_size10_4_sram ; -wire [0:3] mux_tree_tapbuf_size10_5_sram ; -wire [0:3] mux_tree_tapbuf_size10_6_sram ; -wire [0:3] mux_tree_tapbuf_size10_7_sram ; -wire [0:3] mux_tree_tapbuf_size10_8_sram ; -wire [0:3] mux_tree_tapbuf_size10_9_sram ; -wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_10_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_11_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_8_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_9_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size12_0_sram ; -wire [0:3] mux_tree_tapbuf_size12_1_sram ; -wire [0:3] mux_tree_tapbuf_size12_2_sram ; -wire [0:3] mux_tree_tapbuf_size12_3_sram ; -wire [0:3] mux_tree_tapbuf_size12_4_sram ; -wire [0:3] mux_tree_tapbuf_size12_5_sram ; -wire [0:3] mux_tree_tapbuf_size12_6_sram ; -wire [0:3] mux_tree_tapbuf_size12_7_sram ; -wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size12_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size12_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail ; -wire [0:4] mux_tree_tapbuf_size16_0_sram ; -wire [0:4] mux_tree_tapbuf_size16_1_sram ; -wire [0:4] mux_tree_tapbuf_size16_2_sram ; -wire [0:4] mux_tree_tapbuf_size16_3_sram ; -wire [0:0] mux_tree_tapbuf_size16_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size16_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size16_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size16_mem_3_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size7_0_sram ; -wire [0:2] mux_tree_tapbuf_size7_1_sram ; -wire [0:2] mux_tree_tapbuf_size7_2_sram ; -wire [0:2] mux_tree_tapbuf_size7_3_sram ; -wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; -// - -assign clk__FEEDTHRU_1[0] = clk__FEEDTHRU_0[0] ; - -sb_1__1__mux_tree_tapbuf_size12_6 mux_top_track_0 ( - .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , - top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , - chanx_right_in[1] , chanx_right_in[2] , chanx_right_in[12] , - chany_bottom_in[2] , chany_bottom_in[12] , chanx_left_in[0] , - chanx_left_in[2] , chanx_left_in[12] } ) , - .sram ( mux_tree_tapbuf_size12_0_sram ) , - .sram_inv ( mux_top_track_0_undriven_sram_inv ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_145 ) ) ; -sb_1__1__mux_tree_tapbuf_size12 mux_top_track_2 ( - .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , - top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , - chanx_right_in[3] , chanx_right_in[4] , chanx_right_in[13] , - chany_bottom_in[4] , chany_bottom_in[13] , chanx_left_in[4] , - chanx_left_in[13] , chanx_left_in[19] } ) , - .sram ( mux_tree_tapbuf_size12_1_sram ) , - .sram_inv ( mux_top_track_2_undriven_sram_inv ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_149 ) ) ; -sb_1__1__mux_tree_tapbuf_size12_4 mux_right_track_0 ( - .in ( { chany_top_in[2] , chany_top_in[12] , chany_top_in[19] , - right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , - right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , - chany_bottom_in[2] , chany_bottom_in[12] , chany_bottom_in[15] , - chanx_left_in[2] , chanx_left_in[12] } ) , - .sram ( mux_tree_tapbuf_size12_2_sram ) , - .sram_inv ( mux_right_track_0_undriven_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_145 ) ) ; -sb_1__1__mux_tree_tapbuf_size12_5 mux_right_track_2 ( - .in ( { chany_top_in[0] , chany_top_in[4] , chany_top_in[13] , - right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , - right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] , - chany_bottom_in[4] , chany_bottom_in[11] , chany_bottom_in[13] , - chanx_left_in[4] , chanx_left_in[13] } ) , - .sram ( mux_tree_tapbuf_size12_3_sram ) , - .sram_inv ( mux_right_track_2_undriven_sram_inv ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_146 ) ) ; -sb_1__1__mux_tree_tapbuf_size12_0 mux_bottom_track_1 ( - .in ( { chany_top_in[2] , chany_top_in[12] , chanx_right_in[2] , - chanx_right_in[12] , chanx_right_in[15] , - bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , - bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , - chanx_left_in[1] , chanx_left_in[2] , chanx_left_in[12] } ) , - .sram ( mux_tree_tapbuf_size12_4_sram ) , - .sram_inv ( mux_bottom_track_1_undriven_sram_inv ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_147 ) ) ; -sb_1__1__mux_tree_tapbuf_size12_1 mux_bottom_track_3 ( - .in ( { chany_top_in[4] , chany_top_in[13] , chanx_right_in[4] , - chanx_right_in[11] , chanx_right_in[13] , - bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , - bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , - chanx_left_in[3] , chanx_left_in[4] , chanx_left_in[13] } ) , - .sram ( mux_tree_tapbuf_size12_5_sram ) , - .sram_inv ( mux_bottom_track_3_undriven_sram_inv ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_147 ) ) ; -sb_1__1__mux_tree_tapbuf_size12_2 mux_left_track_1 ( - .in ( { chany_top_in[0] , chany_top_in[2] , chany_top_in[12] , - chanx_right_in[2] , chanx_right_in[12] , chany_bottom_in[2] , - chany_bottom_in[12] , chany_bottom_in[19] , - left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , - left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , - .sram ( mux_tree_tapbuf_size12_6_sram ) , - .sram_inv ( mux_left_track_1_undriven_sram_inv ) , - .out ( { ropt_net_158 } ) , - .p0 ( optlc_net_147 ) ) ; -sb_1__1__mux_tree_tapbuf_size12_3 mux_left_track_3 ( - .in ( { chany_top_in[4] , chany_top_in[13] , chany_top_in[19] , - chanx_right_in[4] , chanx_right_in[13] , chany_bottom_in[0] , - chany_bottom_in[4] , chany_bottom_in[13] , - left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , - left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , - .sram ( mux_tree_tapbuf_size12_7_sram ) , - .sram_inv ( mux_left_track_3_undriven_sram_inv ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_148 ) ) ; -sb_1__1__mux_tree_tapbuf_size12_mem_6 mem_top_track_0 ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_0_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size12_mem mem_top_track_2 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_1_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size12_mem_4 mem_right_track_0 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_2_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size12_mem_5 mem_right_track_2 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_3_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size12_mem_0 mem_bottom_track_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_4_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size12_mem_1 mem_bottom_track_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_5_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size12_mem_2 mem_left_track_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_6_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size12_mem_3 mem_left_track_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size12_7_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size16 mux_top_track_4 ( - .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_43_[0] , - top_left_grid_pin_44_[0] , top_left_grid_pin_45_[0] , - top_left_grid_pin_46_[0] , top_left_grid_pin_47_[0] , - top_left_grid_pin_48_[0] , top_left_grid_pin_49_[0] , - chanx_right_in[5] , chanx_right_in[7] , chanx_right_in[14] , - chany_bottom_in[5] , chany_bottom_in[14] , chanx_left_in[5] , - chanx_left_in[14] , chanx_left_in[15] } ) , - .sram ( mux_tree_tapbuf_size16_0_sram ) , - .sram_inv ( mux_top_track_4_undriven_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_149 ) ) ; -sb_1__1__mux_tree_tapbuf_size16_2 mux_right_track_4 ( - .in ( { chany_top_in[1] , chany_top_in[5] , chany_top_in[14] , - right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_35_[0] , - right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_37_[0] , - right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_39_[0] , - right_bottom_grid_pin_40_[0] , right_bottom_grid_pin_41_[0] , - chany_bottom_in[5] , chany_bottom_in[7] , chany_bottom_in[14] , - chanx_left_in[5] , chanx_left_in[14] } ) , - .sram ( mux_tree_tapbuf_size16_1_sram ) , - .sram_inv ( mux_right_track_4_undriven_sram_inv ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_146 ) ) ; -sb_1__1__mux_tree_tapbuf_size16_0 mux_bottom_track_5 ( - .in ( { chany_top_in[5] , chany_top_in[14] , chanx_right_in[5] , - chanx_right_in[7] , chanx_right_in[14] , bottom_left_grid_pin_42_[0] , - bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_44_[0] , - bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_46_[0] , - bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_48_[0] , - bottom_left_grid_pin_49_[0] , chanx_left_in[5] , chanx_left_in[7] , - chanx_left_in[14] } ) , - .sram ( mux_tree_tapbuf_size16_2_sram ) , - .sram_inv ( mux_bottom_track_5_undriven_sram_inv ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_148 ) ) ; -sb_1__1__mux_tree_tapbuf_size16_1 mux_left_track_5 ( - .in ( { chany_top_in[5] , chany_top_in[14] , chany_top_in[15] , - chanx_right_in[5] , chanx_right_in[14] , chany_bottom_in[1] , - chany_bottom_in[5] , chany_bottom_in[14] , - left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_35_[0] , - left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_37_[0] , - left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_39_[0] , - left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_41_[0] } ) , - .sram ( mux_tree_tapbuf_size16_3_sram ) , - .sram_inv ( mux_left_track_5_undriven_sram_inv ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_148 ) ) ; -sb_1__1__mux_tree_tapbuf_size16_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size16_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size16_0_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size16_mem_2 mem_right_track_4 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size16_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size16_1_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size16_mem_0 mem_bottom_track_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size16_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size16_2_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size16_mem_1 mem_left_track_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size16_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size16_3_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size10 mux_top_track_8 ( - .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_46_[0] , - chanx_right_in[6] , chanx_right_in[11] , chanx_right_in[16] , - chany_bottom_in[6] , chany_bottom_in[16] , chanx_left_in[6] , - chanx_left_in[11] , chanx_left_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_top_track_8_undriven_sram_inv ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_145 ) ) ; -sb_1__1__mux_tree_tapbuf_size10_9 mux_top_track_16 ( - .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_47_[0] , - chanx_right_in[8] , chanx_right_in[15] , chanx_right_in[17] , - chany_bottom_in[8] , chany_bottom_in[17] , chanx_left_in[7] , - chanx_left_in[8] , chanx_left_in[17] } ) , - .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_top_track_16_undriven_sram_inv ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_148 ) ) ; -sb_1__1__mux_tree_tapbuf_size10_10 mux_top_track_24 ( - .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_48_[0] , - chanx_right_in[9] , chanx_right_in[18] , chanx_right_in[19] , - chany_bottom_in[9] , chany_bottom_in[18] , chanx_left_in[3] , - chanx_left_in[9] , chanx_left_in[18] } ) , - .sram ( mux_tree_tapbuf_size10_2_sram ) , - .sram_inv ( mux_top_track_24_undriven_sram_inv ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_145 ) ) ; -sb_1__1__mux_tree_tapbuf_size10_8 mux_right_track_8 ( - .in ( { chany_top_in[3] , chany_top_in[6] , chany_top_in[16] , - right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_38_[0] , - chany_bottom_in[3] , chany_bottom_in[6] , chany_bottom_in[16] , - chanx_left_in[6] , chanx_left_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_3_sram ) , - .sram_inv ( mux_right_track_8_undriven_sram_inv ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_146 ) ) ; -sb_1__1__mux_tree_tapbuf_size10_6 mux_right_track_16 ( - .in ( { chany_top_in[7] , chany_top_in[8] , chany_top_in[17] , - right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_39_[0] , - chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[17] , - chanx_left_in[8] , chanx_left_in[17] } ) , - .sram ( mux_tree_tapbuf_size10_4_sram ) , - .sram_inv ( mux_right_track_16_undriven_sram_inv ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_146 ) ) ; -sb_1__1__mux_tree_tapbuf_size10_7 mux_right_track_24 ( - .in ( { chany_top_in[9] , chany_top_in[11] , chany_top_in[18] , - right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_40_[0] , - chany_bottom_in[0] , chany_bottom_in[9] , chany_bottom_in[18] , - chanx_left_in[9] , chanx_left_in[18] } ) , - .sram ( mux_tree_tapbuf_size10_5_sram ) , - .sram_inv ( mux_right_track_24_undriven_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_145 ) ) ; -sb_1__1__mux_tree_tapbuf_size10_2 mux_bottom_track_9 ( - .in ( { chany_top_in[6] , chany_top_in[16] , chanx_right_in[3] , - chanx_right_in[6] , chanx_right_in[16] , bottom_left_grid_pin_42_[0] , - bottom_left_grid_pin_46_[0] , chanx_left_in[6] , chanx_left_in[11] , - chanx_left_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_6_sram ) , - .sram_inv ( mux_bottom_track_9_undriven_sram_inv ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_147 ) ) ; -sb_1__1__mux_tree_tapbuf_size10_0 mux_bottom_track_17 ( - .in ( { chany_top_in[8] , chany_top_in[17] , chanx_right_in[1] , - chanx_right_in[8] , chanx_right_in[17] , bottom_left_grid_pin_43_[0] , - bottom_left_grid_pin_47_[0] , chanx_left_in[8] , chanx_left_in[15] , - chanx_left_in[17] } ) , - .sram ( mux_tree_tapbuf_size10_7_sram ) , - .sram_inv ( mux_bottom_track_17_undriven_sram_inv ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_146 ) ) ; -sb_1__1__mux_tree_tapbuf_size10_1 mux_bottom_track_25 ( - .in ( { chany_top_in[9] , chany_top_in[18] , chanx_right_in[0] , - chanx_right_in[9] , chanx_right_in[18] , bottom_left_grid_pin_44_[0] , - bottom_left_grid_pin_48_[0] , chanx_left_in[9] , chanx_left_in[18] , - chanx_left_in[19] } ) , - .sram ( mux_tree_tapbuf_size10_8_sram ) , - .sram_inv ( mux_bottom_track_25_undriven_sram_inv ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_145 ) ) ; -sb_1__1__mux_tree_tapbuf_size10_5 mux_left_track_9 ( - .in ( { chany_top_in[6] , chany_top_in[11] , chany_top_in[16] , - chanx_right_in[6] , chanx_right_in[16] , chany_bottom_in[3] , - chany_bottom_in[6] , chany_bottom_in[16] , - left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_38_[0] } ) , - .sram ( mux_tree_tapbuf_size10_9_sram ) , - .sram_inv ( mux_left_track_9_undriven_sram_inv ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_147 ) ) ; -sb_1__1__mux_tree_tapbuf_size10_3 mux_left_track_17 ( - .in ( { chany_top_in[7] , chany_top_in[8] , chany_top_in[17] , - chanx_right_in[8] , chanx_right_in[17] , chany_bottom_in[7] , - chany_bottom_in[8] , chany_bottom_in[17] , - left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_39_[0] } ) , - .sram ( mux_tree_tapbuf_size10_10_sram ) , - .sram_inv ( mux_left_track_17_undriven_sram_inv ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_148 ) ) ; -sb_1__1__mux_tree_tapbuf_size10_4 mux_left_track_25 ( - .in ( { chany_top_in[3] , chany_top_in[9] , chany_top_in[18] , - chanx_right_in[9] , chanx_right_in[18] , chany_bottom_in[9] , - chany_bottom_in[11] , chany_bottom_in[18] , - left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_40_[0] } ) , - .sram ( mux_tree_tapbuf_size10_11_sram ) , - .sram_inv ( mux_left_track_25_undriven_sram_inv ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_147 ) ) ; -sb_1__1__mux_tree_tapbuf_size10_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size16_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size10_mem_9 mem_top_track_16 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size10_mem_10 mem_top_track_24 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size10_mem_8 mem_right_track_8 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size16_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size10_mem_6 mem_right_track_16 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size10_mem_7 mem_right_track_24 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size10_mem_2 mem_bottom_track_9 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size16_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size10_mem_0 mem_bottom_track_17 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size10_mem_1 mem_bottom_track_25 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_8_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size10_mem_5 mem_left_track_9 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size16_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_9_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_9_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size10_mem_3 mem_left_track_17 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_9_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_10_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_10_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size10_mem_4 mem_left_track_25 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_10_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_11_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size7 mux_top_track_32 ( - .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_49_[0] , - chanx_right_in[0] , chanx_right_in[10] , chany_bottom_in[10] , - chanx_left_in[1] , chanx_left_in[10] } ) , - .sram ( mux_tree_tapbuf_size7_0_sram ) , - .sram_inv ( mux_top_track_32_undriven_sram_inv ) , - .out ( chany_top_out[16] ) , .p0 ( optlc_net_145 ) ) ; -sb_1__1__mux_tree_tapbuf_size7_2 mux_right_track_32 ( - .in ( { chany_top_in[10] , chany_top_in[15] , - right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_41_[0] , - chany_bottom_in[10] , chany_bottom_in[19] , chanx_left_in[10] } ) , - .sram ( mux_tree_tapbuf_size7_1_sram ) , - .sram_inv ( mux_right_track_32_undriven_sram_inv ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_146 ) ) ; -sb_1__1__mux_tree_tapbuf_size7_0 mux_bottom_track_33 ( - .in ( { chany_top_in[10] , chanx_right_in[10] , chanx_right_in[19] , - bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_49_[0] , - chanx_left_in[0] , chanx_left_in[10] } ) , - .sram ( mux_tree_tapbuf_size7_2_sram ) , - .sram_inv ( mux_bottom_track_33_undriven_sram_inv ) , - .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_147 ) ) ; -sb_1__1__mux_tree_tapbuf_size7_1 mux_left_track_33 ( - .in ( { chany_top_in[1] , chany_top_in[10] , chanx_right_in[10] , - chany_bottom_in[10] , chany_bottom_in[15] , - left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_41_[0] } ) , - .sram ( mux_tree_tapbuf_size7_3_sram ) , - .sram_inv ( mux_left_track_33_undriven_sram_inv ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_148 ) ) ; -sb_1__1__mux_tree_tapbuf_size7_mem mem_top_track_32 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size7_mem_2 mem_right_track_32 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size7_mem_0 mem_bottom_track_33 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ; -sb_1__1__mux_tree_tapbuf_size7_mem_1 mem_left_track_33 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , - .ccff_tail ( { ropt_net_155 } ) , - .mem_out ( mux_tree_tapbuf_size7_3_sram ) ) ; -sky130_fd_sc_hd__conb_1 optlc_140 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_145 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_142 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_146 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__2 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_179 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_top_in[6] ) , - .X ( ropt_net_194 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chany_top_in[8] ) , - .X ( ropt_net_178 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chany_top_in[9] ) , - .X ( ropt_net_170 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_top_in[10] ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chany_top_in[12] ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__8 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_174 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chany_top_in[14] ) , - .X ( ropt_net_196 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__10 ( .A ( chany_top_in[16] ) , - .X ( ropt_net_166 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__11 ( .A ( chany_top_in[17] ) , - .X ( ropt_net_197 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__12 ( .A ( chany_top_in[18] ) , - .X ( ropt_net_189 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_855 ( .A ( ropt_net_200 ) , - .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_144 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_147 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_146 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_148 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , - .HI ( optlc_net_149 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_198 ) ) ; -sky130_fd_sc_hd__clkbuf_1 prog_clk_0__bip415 ( .A ( prog_clk[0] ) , - .X ( ctsbuf_net_1151 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_20__19 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_192 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_right_in[12] ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( chanx_left_in[14] ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_23__22 ( .A ( chanx_right_in[14] ) , - .X ( ropt_net_173 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chanx_right_in[16] ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_25__24 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_184 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_26__25 ( .A ( chanx_right_in[18] ) , - .X ( ropt_net_165 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chany_bottom_in[2] ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_28__27 ( .A ( chany_bottom_in[4] ) , - .X ( ropt_net_171 ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_359774 ( .A ( ctsbuf_net_1151 ) , - .X ( prog_clk__FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_802 ( .A ( chanx_left_in[5] ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_856 ( .A ( ropt_net_201 ) , - .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_32__31 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_187 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_33__32 ( .A ( chany_bottom_in[10] ) , - .X ( ropt_net_193 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_154 ) , - .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_35__34 ( .A ( chany_bottom_in[13] ) , - .X ( ropt_net_199 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_804 ( .A ( ropt_net_155 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_37__36 ( .A ( chany_bottom_in[16] ) , - .X ( ropt_net_186 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_858 ( .A ( ropt_net_202 ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_39__38 ( .A ( chany_bottom_in[18] ) , - .X ( ropt_net_182 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( - .A ( Test_en__FEEDTHRU_0[0] ) , .X ( ropt_net_225 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( chanx_right_in[4] ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_807 ( .A ( ropt_net_158 ) , - .X ( ropt_net_224 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_808 ( .A ( chanx_right_in[5] ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( chanx_right_in[2] ) , - .X ( ropt_net_201 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_810 ( .A ( chany_bottom_in[6] ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_46__45 ( .A ( chanx_left_in[10] ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_47__46 ( .A ( chanx_left_in[12] ) , - .X ( ropt_net_185 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_48__47 ( .A ( chanx_left_in[13] ) , - .X ( ropt_net_169 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_811 ( .A ( chany_bottom_in[5] ) , - .X ( ropt_net_227 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_50__49 ( .A ( chanx_left_in[16] ) , - .X ( ropt_net_181 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_51__50 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_183 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_52__51 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_172 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_860 ( .A ( ropt_net_203 ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_812 ( - .A ( chany_bottom_in[17] ) , .X ( ropt_net_226 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_85 ( .A ( chany_top_in[4] ) , - .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_861 ( .A ( ropt_net_204 ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_862 ( .A ( ropt_net_205 ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_88 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_176 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( chanx_left_in[2] ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_165 ) , - .X ( ropt_net_210 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_91 ( .A ( chany_bottom_in[8] ) , - .X ( ropt_net_154 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_863 ( .A ( ropt_net_206 ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_166 ) , - .X ( ropt_net_223 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_167 ) , - .X ( ropt_net_206 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_95 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_180 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_96 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_177 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_97 ( .A ( chanx_left_in[9] ) , - .X ( ropt_net_168 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_864 ( .A ( ropt_net_207 ) , - .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_817 ( .A ( ropt_net_168 ) , - .X ( ropt_net_220 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_169 ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_170 ) , - .X ( ropt_net_208 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_171 ) , - .X ( ropt_net_200 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_172 ) , - .X ( ropt_net_215 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_108 ( .A ( chanx_left_in[4] ) , - .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_173 ) , - .X ( ropt_net_207 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_174 ) , - .X ( ropt_net_216 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_175 ) , - .X ( ropt_net_204 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_119 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_195 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_120 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_191 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_121 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_167 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_122 ( .A ( chany_bottom_in[12] ) , - .X ( ropt_net_188 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_123 ( .A ( chany_bottom_in[14] ) , - .X ( ropt_net_175 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_865 ( .A ( ropt_net_208 ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( ropt_net_176 ) , - .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_867 ( .A ( ropt_net_209 ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_868 ( .A ( ropt_net_210 ) , - .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_826 ( .A ( ropt_net_177 ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_871 ( .A ( ropt_net_211 ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_875 ( .A ( ropt_net_212 ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_876 ( .A ( ropt_net_213 ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_827 ( .A ( ropt_net_178 ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_136 ( - .A ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] ) , - .X ( ropt_net_190 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_179 ) , - .X ( ropt_net_219 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_829 ( .A ( ropt_net_180 ) , - .X ( ropt_net_209 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_181 ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_182 ) , - .X ( ropt_net_214 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_832 ( .A ( ropt_net_183 ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_833 ( .A ( ropt_net_184 ) , - .X ( ropt_net_222 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_834 ( .A ( ropt_net_185 ) , - .X ( ropt_net_218 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_835 ( .A ( ropt_net_186 ) , - .X ( ropt_net_205 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_836 ( .A ( ropt_net_187 ) , - .X ( ropt_net_211 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_837 ( .A ( ropt_net_188 ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_838 ( .A ( ropt_net_189 ) , - .X ( ropt_net_203 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_839 ( .A ( ropt_net_190 ) , - .X ( ropt_net_221 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_840 ( .A ( ropt_net_191 ) , - .X ( ropt_net_212 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_841 ( .A ( ropt_net_192 ) , - .X ( ropt_net_213 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_842 ( .A ( ropt_net_193 ) , - .X ( ropt_net_217 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_843 ( .A ( ropt_net_194 ) , - .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_844 ( .A ( ropt_net_195 ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_845 ( .A ( ropt_net_196 ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_846 ( .A ( ropt_net_197 ) , - .X ( ropt_net_202 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_849 ( .A ( ropt_net_198 ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_851 ( .A ( ropt_net_199 ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_878 ( .A ( ropt_net_214 ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_880 ( .A ( ropt_net_215 ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_881 ( .A ( ropt_net_216 ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_882 ( .A ( ropt_net_217 ) , - .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_883 ( .A ( ropt_net_218 ) , - .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_885 ( .A ( ropt_net_219 ) , - .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_886 ( .A ( ropt_net_220 ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_887 ( .A ( ropt_net_221 ) , - .X ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_888 ( .A ( ropt_net_222 ) , - .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_890 ( .A ( ropt_net_223 ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_893 ( .A ( ropt_net_224 ) , - .X ( chanx_left_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_897 ( .A ( ropt_net_225 ) , - .X ( Test_en__FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_898 ( .A ( ropt_net_226 ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_899 ( .A ( ropt_net_227 ) , - .X ( chany_top_out[6] ) ) ; -endmodule - - diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__2__icv_in_design.fm.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__2__icv_in_design.fm.v deleted file mode 100644 index fd41205..0000000 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__2__icv_in_design.fm.v +++ /dev/null @@ -1,2431 +0,0 @@ -// -// -// -// -// -// -module sb_1__2__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_28__62 ( .A ( mem_out[2] ) , - .X ( net_net_120 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_120 ( .A ( net_net_120 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__const1 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sb_1__2__const1 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__61 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__const1_26 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_1__2__const1_26 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__60 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size3_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__59 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__58 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__57 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__56 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__55 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__const1_25 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sb_1__2__const1_25 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_1__2__const1_24 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size3_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sb_1__2__const1_24 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_1__2__const1_23 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sb_1__2__const1_23 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_1__2__const1_22 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_1__2__const1_22 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_1__2__const1_21 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_1__2__const1_21 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_1__2__const1_20 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sb_1__2__const1_20 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__54 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__53 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__52 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__const1_19 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sb_1__2__const1_19 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_1__2__const1_18 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sb_1__2__const1_18 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -endmodule - - -module sb_1__2__const1_17 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sb_1__2__const1_17 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_126 ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__51 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__const1_16 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -sb_1__2__const1_16 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__50 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__49 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__48 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__47 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__46 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__45 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__44 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__43 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__const1_15 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sb_1__2__const1_15 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_1__2__const1_14 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sb_1__2__const1_14 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_1__2__const1_13 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sb_1__2__const1_13 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_1__2__const1_12 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sb_1__2__const1_12 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_125 ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_1__2__const1_11 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sb_1__2__const1_11 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_1__2__const1_10 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sb_1__2__const1_10 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_1__2__const1_9 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sb_1__2__const1_9 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_1__2__const1_8 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sb_1__2__const1_8 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__42 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__41 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__const1_7 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sb_1__2__const1_7 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module sb_1__2__const1_6 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sb_1__2__const1_6 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size14_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__40 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size14_mem ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__39 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__const1_5 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size14_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:13] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sb_1__2__const1_5 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; -endmodule - - -module sb_1__2__const1_4 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size14 ( in , sram , sram_inv , out , p0 ) ; -input [0:13] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sb_1__2__const1_4 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size9_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__38 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size9_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__37 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size9_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__36 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__const1_3 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size9_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:8] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; - -sb_1__2__const1_3 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -endmodule - - -module sb_1__2__const1_2 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size9_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:8] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; - -sb_1__2__const1_2 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -endmodule - - -module sb_1__2__const1_1 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , p0 ) ; -input [0:8] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; - -sb_1__2__const1_1 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__35 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__const1_0 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sb_1__2__const1_0 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module sb_1__2_ ( prog_clk , chanx_right_in , right_top_grid_pin_1_ , - right_bottom_grid_pin_34_ , right_bottom_grid_pin_35_ , - right_bottom_grid_pin_36_ , right_bottom_grid_pin_37_ , - right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ , - right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ , chany_bottom_in , - bottom_left_grid_pin_42_ , bottom_left_grid_pin_43_ , - bottom_left_grid_pin_44_ , bottom_left_grid_pin_45_ , - bottom_left_grid_pin_46_ , bottom_left_grid_pin_47_ , - bottom_left_grid_pin_48_ , bottom_left_grid_pin_49_ , chanx_left_in , - left_top_grid_pin_1_ , left_bottom_grid_pin_34_ , - left_bottom_grid_pin_35_ , left_bottom_grid_pin_36_ , - left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , - left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , - left_bottom_grid_pin_41_ , ccff_head , chanx_right_out , - chany_bottom_out , chanx_left_out , ccff_tail , SC_IN_TOP , SC_IN_BOT , - SC_OUT_TOP , SC_OUT_BOT , Test_en__FEEDTHRU_0 , Test_en__FEEDTHRU_1 , - Test_en__FEEDTHRU_2 , clk__FEEDTHRU_0 , clk__FEEDTHRU_1 , - clk__FEEDTHRU_2 ) ; -input [0:0] prog_clk ; -input [0:19] chanx_right_in ; -input [0:0] right_top_grid_pin_1_ ; -input [0:0] right_bottom_grid_pin_34_ ; -input [0:0] right_bottom_grid_pin_35_ ; -input [0:0] right_bottom_grid_pin_36_ ; -input [0:0] right_bottom_grid_pin_37_ ; -input [0:0] right_bottom_grid_pin_38_ ; -input [0:0] right_bottom_grid_pin_39_ ; -input [0:0] right_bottom_grid_pin_40_ ; -input [0:0] right_bottom_grid_pin_41_ ; -input [0:19] chany_bottom_in ; -input [0:0] bottom_left_grid_pin_42_ ; -input [0:0] bottom_left_grid_pin_43_ ; -input [0:0] bottom_left_grid_pin_44_ ; -input [0:0] bottom_left_grid_pin_45_ ; -input [0:0] bottom_left_grid_pin_46_ ; -input [0:0] bottom_left_grid_pin_47_ ; -input [0:0] bottom_left_grid_pin_48_ ; -input [0:0] bottom_left_grid_pin_49_ ; -input [0:19] chanx_left_in ; -input [0:0] left_top_grid_pin_1_ ; -input [0:0] left_bottom_grid_pin_34_ ; -input [0:0] left_bottom_grid_pin_35_ ; -input [0:0] left_bottom_grid_pin_36_ ; -input [0:0] left_bottom_grid_pin_37_ ; -input [0:0] left_bottom_grid_pin_38_ ; -input [0:0] left_bottom_grid_pin_39_ ; -input [0:0] left_bottom_grid_pin_40_ ; -input [0:0] left_bottom_grid_pin_41_ ; -input [0:0] ccff_head ; -output [0:19] chanx_right_out ; -output [0:19] chany_bottom_out ; -output [0:19] chanx_left_out ; -output [0:0] ccff_tail ; -input SC_IN_TOP ; -input SC_IN_BOT ; -output SC_OUT_TOP ; -output SC_OUT_BOT ; -input [0:0] Test_en__FEEDTHRU_0 ; -output [0:0] Test_en__FEEDTHRU_1 ; -output [0:0] Test_en__FEEDTHRU_2 ; -input [0:0] clk__FEEDTHRU_0 ; -output [0:0] clk__FEEDTHRU_1 ; -output [0:0] clk__FEEDTHRU_2 ; - -wire [0:2] mux_bottom_track_11_undriven_sram_inv ; -wire [0:1] mux_bottom_track_13_undriven_sram_inv ; -wire [0:1] mux_bottom_track_15_undriven_sram_inv ; -wire [0:1] mux_bottom_track_17_undriven_sram_inv ; -wire [0:1] mux_bottom_track_19_undriven_sram_inv ; -wire [0:2] mux_bottom_track_1_undriven_sram_inv ; -wire [0:1] mux_bottom_track_21_undriven_sram_inv ; -wire [0:1] mux_bottom_track_23_undriven_sram_inv ; -wire [0:2] mux_bottom_track_25_undriven_sram_inv ; -wire [0:1] mux_bottom_track_27_undriven_sram_inv ; -wire [0:2] mux_bottom_track_3_undriven_sram_inv ; -wire [0:2] mux_bottom_track_5_undriven_sram_inv ; -wire [0:2] mux_bottom_track_7_undriven_sram_inv ; -wire [0:2] mux_bottom_track_9_undriven_sram_inv ; -wire [0:2] mux_left_track_17_undriven_sram_inv ; -wire [0:3] mux_left_track_1_undriven_sram_inv ; -wire [0:2] mux_left_track_25_undriven_sram_inv ; -wire [0:2] mux_left_track_33_undriven_sram_inv ; -wire [0:3] mux_left_track_3_undriven_sram_inv ; -wire [0:3] mux_left_track_5_undriven_sram_inv ; -wire [0:3] mux_left_track_9_undriven_sram_inv ; -wire [0:3] mux_right_track_0_undriven_sram_inv ; -wire [0:2] mux_right_track_16_undriven_sram_inv ; -wire [0:2] mux_right_track_24_undriven_sram_inv ; -wire [0:3] mux_right_track_2_undriven_sram_inv ; -wire [0:2] mux_right_track_32_undriven_sram_inv ; -wire [0:3] mux_right_track_4_undriven_sram_inv ; -wire [0:3] mux_right_track_8_undriven_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size14_0_sram ; -wire [0:3] mux_tree_tapbuf_size14_1_sram ; -wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail ; -wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; -wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:1] mux_tree_tapbuf_size3_2_sram ; -wire [0:1] mux_tree_tapbuf_size3_3_sram ; -wire [0:1] mux_tree_tapbuf_size3_4_sram ; -wire [0:1] mux_tree_tapbuf_size3_5_sram ; -wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size4_0_sram ; -wire [0:2] mux_tree_tapbuf_size4_1_sram ; -wire [0:2] mux_tree_tapbuf_size4_2_sram ; -wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size5_0_sram ; -wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size7_0_sram ; -wire [0:2] mux_tree_tapbuf_size7_1_sram ; -wire [0:2] mux_tree_tapbuf_size7_2_sram ; -wire [0:2] mux_tree_tapbuf_size7_3_sram ; -wire [0:2] mux_tree_tapbuf_size7_4_sram ; -wire [0:2] mux_tree_tapbuf_size7_5_sram ; -wire [0:2] mux_tree_tapbuf_size7_6_sram ; -wire [0:2] mux_tree_tapbuf_size7_7_sram ; -wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_7_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size9_0_sram ; -wire [0:3] mux_tree_tapbuf_size9_1_sram ; -wire [0:3] mux_tree_tapbuf_size9_2_sram ; -wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size9_mem_2_ccff_tail ; -// - -assign SC_IN_TOP = SC_IN_BOT ; -assign clk__FEEDTHRU_1[0] = clk__FEEDTHRU_0[0] ; -assign clk__FEEDTHRU_2[0] = clk__FEEDTHRU_0[0] ; - -sb_1__2__mux_tree_tapbuf_size10 mux_right_track_0 ( - .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] , - right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , - right_bottom_grid_pin_41_[0] , chany_bottom_in[5] , - chany_bottom_in[12] , chany_bottom_in[19] , chanx_left_in[2] , - chanx_left_in[12] } ) , - .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_right_track_0_undriven_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_157 ) ) ; -sb_1__2__mux_tree_tapbuf_size10_mem mem_right_track_0 ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size9 mux_right_track_2 ( - .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , - right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , - chany_bottom_in[4] , chany_bottom_in[11] , chany_bottom_in[18] , - chanx_left_in[4] , chanx_left_in[13] } ) , - .sram ( mux_tree_tapbuf_size9_0_sram ) , - .sram_inv ( mux_right_track_2_undriven_sram_inv ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_157 ) ) ; -sb_1__2__mux_tree_tapbuf_size9_0 mux_left_track_1 ( - .in ( { chanx_right_in[2] , chanx_right_in[12] , chany_bottom_in[6] , - chany_bottom_in[13] , left_top_grid_pin_1_[0] , - left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , - left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , - .sram ( mux_tree_tapbuf_size9_1_sram ) , - .sram_inv ( mux_left_track_1_undriven_sram_inv ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_155 ) ) ; -sb_1__2__mux_tree_tapbuf_size9_1 mux_left_track_3 ( - .in ( { chanx_right_in[4] , chanx_right_in[13] , chany_bottom_in[0] , - chany_bottom_in[7] , chany_bottom_in[14] , - left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , - left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , - .sram ( mux_tree_tapbuf_size9_2_sram ) , - .sram_inv ( mux_left_track_3_undriven_sram_inv ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_154 ) ) ; -sb_1__2__mux_tree_tapbuf_size9_mem mem_right_track_2 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size9_0_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size9_mem_0 mem_left_track_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size9_1_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size9_mem_1 mem_left_track_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size9_2_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size14 mux_right_track_4 ( - .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_34_[0] , - right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_36_[0] , - right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_38_[0] , - right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_40_[0] , - right_bottom_grid_pin_41_[0] , chany_bottom_in[3] , - chany_bottom_in[10] , chany_bottom_in[17] , chanx_left_in[5] , - chanx_left_in[14] } ) , - .sram ( mux_tree_tapbuf_size14_0_sram ) , - .sram_inv ( mux_right_track_4_undriven_sram_inv ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_157 ) ) ; -sb_1__2__mux_tree_tapbuf_size14_0 mux_left_track_5 ( - .in ( { chanx_right_in[5] , chanx_right_in[14] , chany_bottom_in[1] , - chany_bottom_in[8] , chany_bottom_in[15] , left_top_grid_pin_1_[0] , - left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_35_[0] , - left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_37_[0] , - left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_39_[0] , - left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_41_[0] } ) , - .sram ( mux_tree_tapbuf_size14_1_sram ) , - .sram_inv ( mux_left_track_5_undriven_sram_inv ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_154 ) ) ; -sb_1__2__mux_tree_tapbuf_size14_mem mem_right_track_4 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size14_0_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size14_mem_0 mem_left_track_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size14_1_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size8 mux_right_track_8 ( - .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_37_[0] , - right_bottom_grid_pin_41_[0] , chany_bottom_in[2] , - chany_bottom_in[9] , chany_bottom_in[16] , chanx_left_in[6] , - chanx_left_in[16] } ) , - .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_right_track_8_undriven_sram_inv ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_153 ) ) ; -sb_1__2__mux_tree_tapbuf_size8_0 mux_left_track_9 ( - .in ( { chanx_right_in[6] , chanx_right_in[16] , chany_bottom_in[2] , - chany_bottom_in[9] , chany_bottom_in[16] , left_top_grid_pin_1_[0] , - left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_41_[0] } ) , - .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_left_track_9_undriven_sram_inv ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_155 ) ) ; -sb_1__2__mux_tree_tapbuf_size8_mem mem_right_track_8 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size8_mem_0 mem_left_track_9 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size7_6 mux_right_track_16 ( - .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_38_[0] , - chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[15] , - chanx_left_in[8] , chanx_left_in[17] } ) , - .sram ( mux_tree_tapbuf_size7_0_sram ) , - .sram_inv ( mux_right_track_16_undriven_sram_inv ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_153 ) ) ; -sb_1__2__mux_tree_tapbuf_size7 mux_right_track_24 ( - .in ( { right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_39_[0] , - chany_bottom_in[0] , chany_bottom_in[7] , chany_bottom_in[14] , - chanx_left_in[9] , chanx_left_in[18] } ) , - .sram ( mux_tree_tapbuf_size7_1_sram ) , - .sram_inv ( mux_right_track_24_undriven_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_153 ) ) ; -sb_1__2__mux_tree_tapbuf_size7_0 mux_bottom_track_1 ( - .in ( { chanx_right_in[2] , bottom_left_grid_pin_42_[0] , - bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , - bottom_left_grid_pin_48_[0] , chanx_left_in[1] , chanx_left_in[2] } ) , - .sram ( mux_tree_tapbuf_size7_2_sram ) , - .sram_inv ( mux_bottom_track_1_undriven_sram_inv ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_155 ) ) ; -sb_1__2__mux_tree_tapbuf_size7_1 mux_bottom_track_3 ( - .in ( { chanx_right_in[4] , bottom_left_grid_pin_43_[0] , - bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , - bottom_left_grid_pin_49_[0] , chanx_left_in[3] , chanx_left_in[4] } ) , - .sram ( mux_tree_tapbuf_size7_3_sram ) , - .sram_inv ( mux_bottom_track_3_undriven_sram_inv ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_156 ) ) ; -sb_1__2__mux_tree_tapbuf_size7_2 mux_bottom_track_5 ( - .in ( { chanx_right_in[5] , bottom_left_grid_pin_42_[0] , - bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , - bottom_left_grid_pin_48_[0] , chanx_left_in[5] , chanx_left_in[7] } ) , - .sram ( mux_tree_tapbuf_size7_4_sram ) , - .sram_inv ( mux_bottom_track_5_undriven_sram_inv ) , - .out ( { ropt_net_169 } ) , - .p0 ( optlc_net_154 ) ) ; -sb_1__2__mux_tree_tapbuf_size7_3 mux_bottom_track_7 ( - .in ( { chanx_right_in[6] , bottom_left_grid_pin_43_[0] , - bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , - bottom_left_grid_pin_49_[0] , chanx_left_in[6] , chanx_left_in[11] } ) , - .sram ( mux_tree_tapbuf_size7_5_sram ) , - .sram_inv ( mux_bottom_track_7_undriven_sram_inv ) , - .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_154 ) ) ; -sb_1__2__mux_tree_tapbuf_size7_4 mux_left_track_17 ( - .in ( { chanx_right_in[8] , chanx_right_in[17] , chany_bottom_in[3] , - chany_bottom_in[10] , chany_bottom_in[17] , - left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_38_[0] } ) , - .sram ( mux_tree_tapbuf_size7_6_sram ) , - .sram_inv ( mux_left_track_17_undriven_sram_inv ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_155 ) ) ; -sb_1__2__mux_tree_tapbuf_size7_5 mux_left_track_25 ( - .in ( { chanx_right_in[9] , chanx_right_in[18] , chany_bottom_in[4] , - chany_bottom_in[11] , chany_bottom_in[18] , - left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_39_[0] } ) , - .sram ( mux_tree_tapbuf_size7_7_sram ) , - .sram_inv ( mux_left_track_25_undriven_sram_inv ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_156 ) ) ; -sb_1__2__mux_tree_tapbuf_size7_mem_6 mem_right_track_16 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size7_mem mem_right_track_24 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size7_mem_0 mem_bottom_track_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size7_mem_1 mem_bottom_track_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_3_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size7_mem_2 mem_bottom_track_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_4_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size7_mem_3 mem_bottom_track_7 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_5_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size7_mem_4 mem_left_track_17 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_6_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size7_mem_5 mem_left_track_25 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_7_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size5 mux_right_track_32 ( - .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_40_[0] , - chany_bottom_in[6] , chany_bottom_in[13] , chanx_left_in[10] } ) , - .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_right_track_32_undriven_sram_inv ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_153 ) ) ; -sb_1__2__mux_tree_tapbuf_size5_mem mem_right_track_32 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size4 mux_bottom_track_9 ( - .in ( { chanx_right_in[8] , bottom_left_grid_pin_42_[0] , - chanx_left_in[8] , chanx_left_in[15] } ) , - .sram ( mux_tree_tapbuf_size4_0_sram ) , - .sram_inv ( mux_bottom_track_9_undriven_sram_inv ) , - .out ( { ropt_net_168 } ) , - .p0 ( optlc_net_154 ) ) ; -sb_1__2__mux_tree_tapbuf_size4_0 mux_bottom_track_11 ( - .in ( { chanx_right_in[9] , bottom_left_grid_pin_43_[0] , - chanx_left_in[9] , chanx_left_in[19] } ) , - .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_bottom_track_11_undriven_sram_inv ) , - .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_154 ) ) ; -sb_1__2__mux_tree_tapbuf_size4_1 mux_bottom_track_25 ( - .in ( { chanx_right_in[18] , chanx_right_in[19] , - bottom_left_grid_pin_42_[0] , chanx_left_in[18] } ) , - .sram ( mux_tree_tapbuf_size4_2_sram ) , - .sram_inv ( mux_bottom_track_25_undriven_sram_inv ) , - .out ( { ropt_net_162 } ) , - .p0 ( optlc_net_153 ) ) ; -sb_1__2__mux_tree_tapbuf_size4_mem mem_bottom_track_9 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size4_mem_0 mem_bottom_track_11 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size4_mem_1 mem_bottom_track_25 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size3_0 mux_bottom_track_13 ( - .in ( { chanx_right_in[10] , bottom_left_grid_pin_44_[0] , - chanx_left_in[10] } ) , - .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_bottom_track_13_undriven_sram_inv ) , - .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_156 ) ) ; -sb_1__2__mux_tree_tapbuf_size3_1 mux_bottom_track_15 ( - .in ( { chanx_right_in[12] , bottom_left_grid_pin_45_[0] , - chanx_left_in[12] } ) , - .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_bottom_track_15_undriven_sram_inv ) , - .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_156 ) ) ; -sb_1__2__mux_tree_tapbuf_size3_2 mux_bottom_track_17 ( - .in ( { chanx_right_in[13] , bottom_left_grid_pin_46_[0] , - chanx_left_in[13] } ) , - .sram ( mux_tree_tapbuf_size3_2_sram ) , - .sram_inv ( mux_bottom_track_17_undriven_sram_inv ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_156 ) ) ; -sb_1__2__mux_tree_tapbuf_size3_3 mux_bottom_track_19 ( - .in ( { chanx_right_in[14] , bottom_left_grid_pin_47_[0] , - chanx_left_in[14] } ) , - .sram ( mux_tree_tapbuf_size3_3_sram ) , - .sram_inv ( mux_bottom_track_19_undriven_sram_inv ) , - .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_156 ) ) ; -sb_1__2__mux_tree_tapbuf_size3_4 mux_bottom_track_21 ( - .in ( { chanx_right_in[16] , bottom_left_grid_pin_48_[0] , - chanx_left_in[16] } ) , - .sram ( mux_tree_tapbuf_size3_4_sram ) , - .sram_inv ( mux_bottom_track_21_undriven_sram_inv ) , - .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_156 ) ) ; -sb_1__2__mux_tree_tapbuf_size3 mux_bottom_track_23 ( - .in ( { chanx_right_in[17] , bottom_left_grid_pin_49_[0] , - chanx_left_in[17] } ) , - .sram ( mux_tree_tapbuf_size3_5_sram ) , - .sram_inv ( mux_bottom_track_23_undriven_sram_inv ) , - .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_153 ) ) ; -sb_1__2__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_13 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size3_mem_1 mem_bottom_track_15 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size3_mem_2 mem_bottom_track_17 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size3_mem_3 mem_bottom_track_19 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size3_mem_4 mem_bottom_track_21 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_4_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size3_mem mem_bottom_track_23 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_5_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size2 mux_bottom_track_27 ( - .in ( { chanx_right_in[15] , bottom_left_grid_pin_43_[0] } ) , - .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_bottom_track_27_undriven_sram_inv ) , - .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_153 ) ) ; -sb_1__2__mux_tree_tapbuf_size2_mem mem_bottom_track_27 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size6 mux_left_track_33 ( - .in ( { chanx_right_in[10] , chany_bottom_in[5] , chany_bottom_in[12] , - chany_bottom_in[19] , left_bottom_grid_pin_36_[0] , - left_bottom_grid_pin_40_[0] } ) , - .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_left_track_33_undriven_sram_inv ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_154 ) ) ; -sb_1__2__mux_tree_tapbuf_size6_mem mem_left_track_33 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , - .ccff_tail ( { ropt_net_164 } ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_811 ( .A ( ropt_net_193 ) , - .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_153 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_150 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_154 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_152 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_155 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__4 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_179 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chanx_right_in[5] ) , - .X ( ropt_net_188 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__6 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_177 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_154 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_156 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_191 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_187 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_156 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , - .HI ( optlc_net_157 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( chanx_right_in[2] ) , - .X ( ropt_net_194 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_159 ) , - .X ( ropt_net_205 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( .A ( ropt_net_160 ) , - .X ( ropt_net_209 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chanx_right_in[14] ) , - .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_194 ) , - .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__16 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_184 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( chanx_right_in[18] ) , - .X ( ropt_net_211 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_162 ) , - .X ( ropt_net_204 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_163 ) , - .X ( ropt_net_197 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__20 ( .A ( chanx_left_in[4] ) , - .X ( ropt_net_189 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( ropt_net_195 ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( ropt_net_164 ) , - .X ( ropt_net_208 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_165 ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_25__24 ( .A ( chanx_left_in[9] ) , - .X ( ropt_net_182 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_26__25 ( .A ( chanx_left_in[10] ) , - .X ( ropt_net_186 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( - .A ( Test_en__FEEDTHRU_0[0] ) , .X ( ropt_net_215 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_782 ( - .A ( Test_en__FEEDTHRU_0[0] ) , .X ( ropt_net_216 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_783 ( .A ( ropt_net_168 ) , - .X ( ropt_net_210 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_784 ( .A ( ropt_net_169 ) , - .X ( ropt_net_214 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_31__30 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_180 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_785 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_213 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_160 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_196 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_814 ( .A ( ropt_net_196 ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_816 ( .A ( ropt_net_197 ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_787 ( .A ( chanx_left_in[5] ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_173 ) , - .X ( ropt_net_199 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_75 ( .A ( chanx_right_in[3] ) , - .X ( BUF_net_75 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( chanx_left_in[18] ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_818 ( .A ( ropt_net_198 ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_78 ( .A ( chanx_right_in[11] ) , - .X ( BUF_net_78 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_819 ( .A ( ropt_net_199 ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( chanx_left_in[6] ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_822 ( .A ( ropt_net_200 ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_212 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_823 ( .A ( ropt_net_201 ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_84 ( .A ( chanx_left_in[2] ) , - .X ( BUF_net_84 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_792 ( .A ( ropt_net_177 ) , - .X ( ropt_net_193 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_86 ( .A ( chanx_left_in[8] ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_178 ) , - .X ( ropt_net_202 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_179 ) , - .X ( ropt_net_198 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_180 ) , - .X ( ropt_net_201 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_90 ( .A ( chanx_left_in[16] ) , - .X ( ropt_net_183 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_181 ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_824 ( .A ( ropt_net_202 ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_826 ( .A ( ropt_net_203 ) , - .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_100 ( .A ( chanx_right_in[0] ) , - .X ( ropt_net_163 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( ropt_net_182 ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_183 ) , - .X ( ropt_net_195 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_184 ) , - .X ( ropt_net_206 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_185 ) , - .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_186 ) , - .X ( ropt_net_200 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_187 ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_188 ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_189 ) , - .X ( ropt_net_203 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_190 ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_191 ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_827 ( .A ( ropt_net_204 ) , - .X ( chany_bottom_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_828 ( .A ( ropt_net_205 ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_113 ( .A ( chanx_left_in[12] ) , - .X ( ropt_net_185 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_829 ( .A ( ropt_net_206 ) , - .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_830 ( .A ( ropt_net_207 ) , - .X ( chany_bottom_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_208 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_832 ( .A ( ropt_net_209 ) , - .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_122 ( .A ( chanx_right_in[16] ) , - .X ( ropt_net_159 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_834 ( .A ( ropt_net_210 ) , - .X ( chany_bottom_out[4] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_129 ( .A ( chanx_right_in[1] ) , - .X ( ropt_net_173 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_835 ( .A ( ropt_net_211 ) , - .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_131 ( .A ( BUF_net_75 ) , - .X ( ropt_net_207 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_132 ( .A ( chanx_right_in[7] ) , - .X ( ropt_net_190 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_836 ( .A ( ropt_net_212 ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_134 ( .A ( BUF_net_78 ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_837 ( .A ( ropt_net_213 ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_839 ( .A ( ropt_net_214 ) , - .X ( chany_bottom_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_840 ( .A ( ropt_net_215 ) , - .X ( Test_en__FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_138 ( .A ( chanx_left_in[0] ) , - .X ( ropt_net_165 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_139 ( .A ( BUF_net_84 ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_841 ( .A ( ropt_net_216 ) , - .X ( Test_en__FEEDTHRU_2[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_141 ( .A ( chanx_left_in[13] ) , - .X ( ropt_net_181 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_142 ( .A ( chanx_left_in[14] ) , - .X ( ropt_net_178 ) ) ; -endmodule - - diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__2__icv_in_design.lvs.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__2__icv_in_design.lvs.v deleted file mode 100644 index e5c31b3..0000000 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__2__icv_in_design.lvs.v +++ /dev/null @@ -1,4553 +0,0 @@ -// -// -// -// -// -// -module sb_1__2__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_28__62 ( .A ( mem_out[2] ) , - .X ( net_net_120 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_120 ( .A ( net_net_120 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__61 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__60 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size3_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__59 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__58 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__57 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__56 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__55 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size3_4 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__54 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__53 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__52 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_126 ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__51 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__50 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__49 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__48 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__47 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__46 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__45 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__44 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__43 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_125 ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_6 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__42 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__41 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size14_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__40 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size14_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__39 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size14_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:13] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size14 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:13] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size9_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__38 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size9_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__37 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size9_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__36 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size9_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:8] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size9_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:8] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:8] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__35 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2_ ( prog_clk , chanx_right_in , right_top_grid_pin_1_ , - right_bottom_grid_pin_34_ , right_bottom_grid_pin_35_ , - right_bottom_grid_pin_36_ , right_bottom_grid_pin_37_ , - right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ , - right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ , chany_bottom_in , - bottom_left_grid_pin_42_ , bottom_left_grid_pin_43_ , - bottom_left_grid_pin_44_ , bottom_left_grid_pin_45_ , - bottom_left_grid_pin_46_ , bottom_left_grid_pin_47_ , - bottom_left_grid_pin_48_ , bottom_left_grid_pin_49_ , chanx_left_in , - left_top_grid_pin_1_ , left_bottom_grid_pin_34_ , - left_bottom_grid_pin_35_ , left_bottom_grid_pin_36_ , - left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , - left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , - left_bottom_grid_pin_41_ , ccff_head , chanx_right_out , - chany_bottom_out , chanx_left_out , ccff_tail , SC_IN_TOP , SC_IN_BOT , - SC_OUT_TOP , SC_OUT_BOT , VDD , VSS , Test_en__FEEDTHRU_0 , - Test_en__FEEDTHRU_1 , Test_en__FEEDTHRU_2 , clk__FEEDTHRU_0 , - clk__FEEDTHRU_1 , clk__FEEDTHRU_2 ) ; -input [0:0] prog_clk ; -input [0:19] chanx_right_in ; -input [0:0] right_top_grid_pin_1_ ; -input [0:0] right_bottom_grid_pin_34_ ; -input [0:0] right_bottom_grid_pin_35_ ; -input [0:0] right_bottom_grid_pin_36_ ; -input [0:0] right_bottom_grid_pin_37_ ; -input [0:0] right_bottom_grid_pin_38_ ; -input [0:0] right_bottom_grid_pin_39_ ; -input [0:0] right_bottom_grid_pin_40_ ; -input [0:0] right_bottom_grid_pin_41_ ; -input [0:19] chany_bottom_in ; -input [0:0] bottom_left_grid_pin_42_ ; -input [0:0] bottom_left_grid_pin_43_ ; -input [0:0] bottom_left_grid_pin_44_ ; -input [0:0] bottom_left_grid_pin_45_ ; -input [0:0] bottom_left_grid_pin_46_ ; -input [0:0] bottom_left_grid_pin_47_ ; -input [0:0] bottom_left_grid_pin_48_ ; -input [0:0] bottom_left_grid_pin_49_ ; -input [0:19] chanx_left_in ; -input [0:0] left_top_grid_pin_1_ ; -input [0:0] left_bottom_grid_pin_34_ ; -input [0:0] left_bottom_grid_pin_35_ ; -input [0:0] left_bottom_grid_pin_36_ ; -input [0:0] left_bottom_grid_pin_37_ ; -input [0:0] left_bottom_grid_pin_38_ ; -input [0:0] left_bottom_grid_pin_39_ ; -input [0:0] left_bottom_grid_pin_40_ ; -input [0:0] left_bottom_grid_pin_41_ ; -input [0:0] ccff_head ; -output [0:19] chanx_right_out ; -output [0:19] chany_bottom_out ; -output [0:19] chanx_left_out ; -output [0:0] ccff_tail ; -input SC_IN_TOP ; -input SC_IN_BOT ; -output SC_OUT_TOP ; -output SC_OUT_BOT ; -input VDD ; -input VSS ; -input [0:0] Test_en__FEEDTHRU_0 ; -output [0:0] Test_en__FEEDTHRU_1 ; -output [0:0] Test_en__FEEDTHRU_2 ; -input [0:0] clk__FEEDTHRU_0 ; -output [0:0] clk__FEEDTHRU_1 ; -output [0:0] clk__FEEDTHRU_2 ; - -wire [0:2] mux_bottom_track_11_undriven_sram_inv ; -wire [0:1] mux_bottom_track_13_undriven_sram_inv ; -wire [0:1] mux_bottom_track_15_undriven_sram_inv ; -wire [0:1] mux_bottom_track_17_undriven_sram_inv ; -wire [0:1] mux_bottom_track_19_undriven_sram_inv ; -wire [0:2] mux_bottom_track_1_undriven_sram_inv ; -wire [0:1] mux_bottom_track_21_undriven_sram_inv ; -wire [0:1] mux_bottom_track_23_undriven_sram_inv ; -wire [0:2] mux_bottom_track_25_undriven_sram_inv ; -wire [0:1] mux_bottom_track_27_undriven_sram_inv ; -wire [0:2] mux_bottom_track_3_undriven_sram_inv ; -wire [0:2] mux_bottom_track_5_undriven_sram_inv ; -wire [0:2] mux_bottom_track_7_undriven_sram_inv ; -wire [0:2] mux_bottom_track_9_undriven_sram_inv ; -wire [0:2] mux_left_track_17_undriven_sram_inv ; -wire [0:3] mux_left_track_1_undriven_sram_inv ; -wire [0:2] mux_left_track_25_undriven_sram_inv ; -wire [0:2] mux_left_track_33_undriven_sram_inv ; -wire [0:3] mux_left_track_3_undriven_sram_inv ; -wire [0:3] mux_left_track_5_undriven_sram_inv ; -wire [0:3] mux_left_track_9_undriven_sram_inv ; -wire [0:3] mux_right_track_0_undriven_sram_inv ; -wire [0:2] mux_right_track_16_undriven_sram_inv ; -wire [0:2] mux_right_track_24_undriven_sram_inv ; -wire [0:3] mux_right_track_2_undriven_sram_inv ; -wire [0:2] mux_right_track_32_undriven_sram_inv ; -wire [0:3] mux_right_track_4_undriven_sram_inv ; -wire [0:3] mux_right_track_8_undriven_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size14_0_sram ; -wire [0:3] mux_tree_tapbuf_size14_1_sram ; -wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail ; -wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; -wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:1] mux_tree_tapbuf_size3_2_sram ; -wire [0:1] mux_tree_tapbuf_size3_3_sram ; -wire [0:1] mux_tree_tapbuf_size3_4_sram ; -wire [0:1] mux_tree_tapbuf_size3_5_sram ; -wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size4_0_sram ; -wire [0:2] mux_tree_tapbuf_size4_1_sram ; -wire [0:2] mux_tree_tapbuf_size4_2_sram ; -wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size5_0_sram ; -wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size7_0_sram ; -wire [0:2] mux_tree_tapbuf_size7_1_sram ; -wire [0:2] mux_tree_tapbuf_size7_2_sram ; -wire [0:2] mux_tree_tapbuf_size7_3_sram ; -wire [0:2] mux_tree_tapbuf_size7_4_sram ; -wire [0:2] mux_tree_tapbuf_size7_5_sram ; -wire [0:2] mux_tree_tapbuf_size7_6_sram ; -wire [0:2] mux_tree_tapbuf_size7_7_sram ; -wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_7_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size9_0_sram ; -wire [0:3] mux_tree_tapbuf_size9_1_sram ; -wire [0:3] mux_tree_tapbuf_size9_2_sram ; -wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size9_mem_2_ccff_tail ; -supply1 VDD ; -supply0 VSS ; -// - -assign SC_IN_TOP = SC_IN_BOT ; -assign clk__FEEDTHRU_1[0] = clk__FEEDTHRU_0[0] ; -assign clk__FEEDTHRU_2[0] = clk__FEEDTHRU_0[0] ; - -sb_1__2__mux_tree_tapbuf_size10 mux_right_track_0 ( - .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] , - right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , - right_bottom_grid_pin_41_[0] , chany_bottom_in[5] , - chany_bottom_in[12] , chany_bottom_in[19] , chanx_left_in[2] , - chanx_left_in[12] } ) , - .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_right_track_0_undriven_sram_inv ) , - .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_157 ) ) ; -sb_1__2__mux_tree_tapbuf_size10_mem mem_right_track_0 ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__2__mux_tree_tapbuf_size9 mux_right_track_2 ( - .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , - right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , - chany_bottom_in[4] , chany_bottom_in[11] , chany_bottom_in[18] , - chanx_left_in[4] , chanx_left_in[13] } ) , - .sram ( mux_tree_tapbuf_size9_0_sram ) , - .sram_inv ( mux_right_track_2_undriven_sram_inv ) , - .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_157 ) ) ; -sb_1__2__mux_tree_tapbuf_size9_0 mux_left_track_1 ( - .in ( { chanx_right_in[2] , chanx_right_in[12] , chany_bottom_in[6] , - chany_bottom_in[13] , left_top_grid_pin_1_[0] , - left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , - left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , - .sram ( mux_tree_tapbuf_size9_1_sram ) , - .sram_inv ( mux_left_track_1_undriven_sram_inv ) , - .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_155 ) ) ; -sb_1__2__mux_tree_tapbuf_size9_1 mux_left_track_3 ( - .in ( { chanx_right_in[4] , chanx_right_in[13] , chany_bottom_in[0] , - chany_bottom_in[7] , chany_bottom_in[14] , - left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , - left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , - .sram ( mux_tree_tapbuf_size9_2_sram ) , - .sram_inv ( mux_left_track_3_undriven_sram_inv ) , - .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_154 ) ) ; -sb_1__2__mux_tree_tapbuf_size9_mem mem_right_track_2 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size9_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__2__mux_tree_tapbuf_size9_mem_0 mem_left_track_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size9_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__2__mux_tree_tapbuf_size9_mem_1 mem_left_track_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size9_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__2__mux_tree_tapbuf_size14 mux_right_track_4 ( - .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_34_[0] , - right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_36_[0] , - right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_38_[0] , - right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_40_[0] , - right_bottom_grid_pin_41_[0] , chany_bottom_in[3] , - chany_bottom_in[10] , chany_bottom_in[17] , chanx_left_in[5] , - chanx_left_in[14] } ) , - .sram ( mux_tree_tapbuf_size14_0_sram ) , - .sram_inv ( mux_right_track_4_undriven_sram_inv ) , - .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_157 ) ) ; -sb_1__2__mux_tree_tapbuf_size14_0 mux_left_track_5 ( - .in ( { chanx_right_in[5] , chanx_right_in[14] , chany_bottom_in[1] , - chany_bottom_in[8] , chany_bottom_in[15] , left_top_grid_pin_1_[0] , - left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_35_[0] , - left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_37_[0] , - left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_39_[0] , - left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_41_[0] } ) , - .sram ( mux_tree_tapbuf_size14_1_sram ) , - .sram_inv ( mux_left_track_5_undriven_sram_inv ) , - .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_154 ) ) ; -sb_1__2__mux_tree_tapbuf_size14_mem mem_right_track_4 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size14_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__2__mux_tree_tapbuf_size14_mem_0 mem_left_track_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size14_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__2__mux_tree_tapbuf_size8 mux_right_track_8 ( - .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_37_[0] , - right_bottom_grid_pin_41_[0] , chany_bottom_in[2] , - chany_bottom_in[9] , chany_bottom_in[16] , chanx_left_in[6] , - chanx_left_in[16] } ) , - .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_right_track_8_undriven_sram_inv ) , - .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_153 ) ) ; -sb_1__2__mux_tree_tapbuf_size8_0 mux_left_track_9 ( - .in ( { chanx_right_in[6] , chanx_right_in[16] , chany_bottom_in[2] , - chany_bottom_in[9] , chany_bottom_in[16] , left_top_grid_pin_1_[0] , - left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_41_[0] } ) , - .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_left_track_9_undriven_sram_inv ) , - .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_155 ) ) ; -sb_1__2__mux_tree_tapbuf_size8_mem mem_right_track_8 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__2__mux_tree_tapbuf_size8_mem_0 mem_left_track_9 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__2__mux_tree_tapbuf_size7_6 mux_right_track_16 ( - .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_38_[0] , - chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[15] , - chanx_left_in[8] , chanx_left_in[17] } ) , - .sram ( mux_tree_tapbuf_size7_0_sram ) , - .sram_inv ( mux_right_track_16_undriven_sram_inv ) , - .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_153 ) ) ; -sb_1__2__mux_tree_tapbuf_size7 mux_right_track_24 ( - .in ( { right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_39_[0] , - chany_bottom_in[0] , chany_bottom_in[7] , chany_bottom_in[14] , - chanx_left_in[9] , chanx_left_in[18] } ) , - .sram ( mux_tree_tapbuf_size7_1_sram ) , - .sram_inv ( mux_right_track_24_undriven_sram_inv ) , - .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_153 ) ) ; -sb_1__2__mux_tree_tapbuf_size7_0 mux_bottom_track_1 ( - .in ( { chanx_right_in[2] , bottom_left_grid_pin_42_[0] , - bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , - bottom_left_grid_pin_48_[0] , chanx_left_in[1] , chanx_left_in[2] } ) , - .sram ( mux_tree_tapbuf_size7_2_sram ) , - .sram_inv ( mux_bottom_track_1_undriven_sram_inv ) , - .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_155 ) ) ; -sb_1__2__mux_tree_tapbuf_size7_1 mux_bottom_track_3 ( - .in ( { chanx_right_in[4] , bottom_left_grid_pin_43_[0] , - bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , - bottom_left_grid_pin_49_[0] , chanx_left_in[3] , chanx_left_in[4] } ) , - .sram ( mux_tree_tapbuf_size7_3_sram ) , - .sram_inv ( mux_bottom_track_3_undriven_sram_inv ) , - .out ( chany_bottom_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_156 ) ) ; -sb_1__2__mux_tree_tapbuf_size7_2 mux_bottom_track_5 ( - .in ( { chanx_right_in[5] , bottom_left_grid_pin_42_[0] , - bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , - bottom_left_grid_pin_48_[0] , chanx_left_in[5] , chanx_left_in[7] } ) , - .sram ( mux_tree_tapbuf_size7_4_sram ) , - .sram_inv ( mux_bottom_track_5_undriven_sram_inv ) , - .out ( { ropt_net_169 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_154 ) ) ; -sb_1__2__mux_tree_tapbuf_size7_3 mux_bottom_track_7 ( - .in ( { chanx_right_in[6] , bottom_left_grid_pin_43_[0] , - bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , - bottom_left_grid_pin_49_[0] , chanx_left_in[6] , chanx_left_in[11] } ) , - .sram ( mux_tree_tapbuf_size7_5_sram ) , - .sram_inv ( mux_bottom_track_7_undriven_sram_inv ) , - .out ( chany_bottom_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_154 ) ) ; -sb_1__2__mux_tree_tapbuf_size7_4 mux_left_track_17 ( - .in ( { chanx_right_in[8] , chanx_right_in[17] , chany_bottom_in[3] , - chany_bottom_in[10] , chany_bottom_in[17] , - left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_38_[0] } ) , - .sram ( mux_tree_tapbuf_size7_6_sram ) , - .sram_inv ( mux_left_track_17_undriven_sram_inv ) , - .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_155 ) ) ; -sb_1__2__mux_tree_tapbuf_size7_5 mux_left_track_25 ( - .in ( { chanx_right_in[9] , chanx_right_in[18] , chany_bottom_in[4] , - chany_bottom_in[11] , chany_bottom_in[18] , - left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_39_[0] } ) , - .sram ( mux_tree_tapbuf_size7_7_sram ) , - .sram_inv ( mux_left_track_25_undriven_sram_inv ) , - .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_156 ) ) ; -sb_1__2__mux_tree_tapbuf_size7_mem_6 mem_right_track_16 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__2__mux_tree_tapbuf_size7_mem mem_right_track_24 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__2__mux_tree_tapbuf_size7_mem_0 mem_bottom_track_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__2__mux_tree_tapbuf_size7_mem_1 mem_bottom_track_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__2__mux_tree_tapbuf_size7_mem_2 mem_bottom_track_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__2__mux_tree_tapbuf_size7_mem_3 mem_bottom_track_7 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__2__mux_tree_tapbuf_size7_mem_4 mem_left_track_17 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__2__mux_tree_tapbuf_size7_mem_5 mem_left_track_25 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__2__mux_tree_tapbuf_size5 mux_right_track_32 ( - .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_40_[0] , - chany_bottom_in[6] , chany_bottom_in[13] , chanx_left_in[10] } ) , - .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_right_track_32_undriven_sram_inv ) , - .out ( chanx_right_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_153 ) ) ; -sb_1__2__mux_tree_tapbuf_size5_mem mem_right_track_32 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__2__mux_tree_tapbuf_size4 mux_bottom_track_9 ( - .in ( { chanx_right_in[8] , bottom_left_grid_pin_42_[0] , - chanx_left_in[8] , chanx_left_in[15] } ) , - .sram ( mux_tree_tapbuf_size4_0_sram ) , - .sram_inv ( mux_bottom_track_9_undriven_sram_inv ) , - .out ( { ropt_net_168 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_154 ) ) ; -sb_1__2__mux_tree_tapbuf_size4_0 mux_bottom_track_11 ( - .in ( { chanx_right_in[9] , bottom_left_grid_pin_43_[0] , - chanx_left_in[9] , chanx_left_in[19] } ) , - .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_bottom_track_11_undriven_sram_inv ) , - .out ( chany_bottom_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_154 ) ) ; -sb_1__2__mux_tree_tapbuf_size4_1 mux_bottom_track_25 ( - .in ( { chanx_right_in[18] , chanx_right_in[19] , - bottom_left_grid_pin_42_[0] , chanx_left_in[18] } ) , - .sram ( mux_tree_tapbuf_size4_2_sram ) , - .sram_inv ( mux_bottom_track_25_undriven_sram_inv ) , - .out ( { ropt_net_162 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_153 ) ) ; -sb_1__2__mux_tree_tapbuf_size4_mem mem_bottom_track_9 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__2__mux_tree_tapbuf_size4_mem_0 mem_bottom_track_11 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__2__mux_tree_tapbuf_size4_mem_1 mem_bottom_track_25 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__2__mux_tree_tapbuf_size3_0 mux_bottom_track_13 ( - .in ( { chanx_right_in[10] , bottom_left_grid_pin_44_[0] , - chanx_left_in[10] } ) , - .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_bottom_track_13_undriven_sram_inv ) , - .out ( chany_bottom_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_156 ) ) ; -sb_1__2__mux_tree_tapbuf_size3_1 mux_bottom_track_15 ( - .in ( { chanx_right_in[12] , bottom_left_grid_pin_45_[0] , - chanx_left_in[12] } ) , - .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_bottom_track_15_undriven_sram_inv ) , - .out ( chany_bottom_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_156 ) ) ; -sb_1__2__mux_tree_tapbuf_size3_2 mux_bottom_track_17 ( - .in ( { chanx_right_in[13] , bottom_left_grid_pin_46_[0] , - chanx_left_in[13] } ) , - .sram ( mux_tree_tapbuf_size3_2_sram ) , - .sram_inv ( mux_bottom_track_17_undriven_sram_inv ) , - .out ( chany_bottom_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_156 ) ) ; -sb_1__2__mux_tree_tapbuf_size3_3 mux_bottom_track_19 ( - .in ( { chanx_right_in[14] , bottom_left_grid_pin_47_[0] , - chanx_left_in[14] } ) , - .sram ( mux_tree_tapbuf_size3_3_sram ) , - .sram_inv ( mux_bottom_track_19_undriven_sram_inv ) , - .out ( chany_bottom_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_156 ) ) ; -sb_1__2__mux_tree_tapbuf_size3_4 mux_bottom_track_21 ( - .in ( { chanx_right_in[16] , bottom_left_grid_pin_48_[0] , - chanx_left_in[16] } ) , - .sram ( mux_tree_tapbuf_size3_4_sram ) , - .sram_inv ( mux_bottom_track_21_undriven_sram_inv ) , - .out ( chany_bottom_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_156 ) ) ; -sb_1__2__mux_tree_tapbuf_size3 mux_bottom_track_23 ( - .in ( { chanx_right_in[17] , bottom_left_grid_pin_49_[0] , - chanx_left_in[17] } ) , - .sram ( mux_tree_tapbuf_size3_5_sram ) , - .sram_inv ( mux_bottom_track_23_undriven_sram_inv ) , - .out ( chany_bottom_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_153 ) ) ; -sb_1__2__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_13 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__2__mux_tree_tapbuf_size3_mem_1 mem_bottom_track_15 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__2__mux_tree_tapbuf_size3_mem_2 mem_bottom_track_17 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__2__mux_tree_tapbuf_size3_mem_3 mem_bottom_track_19 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__2__mux_tree_tapbuf_size3_mem_4 mem_bottom_track_21 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__2__mux_tree_tapbuf_size3_mem mem_bottom_track_23 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__2__mux_tree_tapbuf_size2 mux_bottom_track_27 ( - .in ( { chanx_right_in[15] , bottom_left_grid_pin_43_[0] } ) , - .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_bottom_track_27_undriven_sram_inv ) , - .out ( chany_bottom_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_153 ) ) ; -sb_1__2__mux_tree_tapbuf_size2_mem mem_bottom_track_27 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__2__mux_tree_tapbuf_size6 mux_left_track_33 ( - .in ( { chanx_right_in[10] , chany_bottom_in[5] , chany_bottom_in[12] , - chany_bottom_in[19] , left_bottom_grid_pin_36_[0] , - left_bottom_grid_pin_40_[0] } ) , - .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_left_track_33_undriven_sram_inv ) , - .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_154 ) ) ; -sb_1__2__mux_tree_tapbuf_size6_mem mem_left_track_33 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , - .ccff_tail ( { ropt_net_164 } ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1422 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1423 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1424 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1425 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1426 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1427 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1428 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1429 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1430 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1431 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1432 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1433 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1434 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1435 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1436 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1437 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1438 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1439 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1440 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1441 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1442 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1443 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1444 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1445 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1446 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1447 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1448 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1449 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1450 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1451 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1452 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1453 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1454 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1455 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1456 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1457 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1458 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1459 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_811 ( .A ( ropt_net_193 ) , - .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_150 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_152 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__4 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_179 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chanx_right_in[5] ) , - .X ( ropt_net_188 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__6 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_177 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_154 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_156 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_191 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_156 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , - .HI ( optlc_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( chanx_right_in[2] ) , - .X ( ropt_net_194 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_159 ) , - .X ( ropt_net_205 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( .A ( ropt_net_160 ) , - .X ( ropt_net_209 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chanx_right_in[14] ) , - .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_194 ) , - .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__16 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_184 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( chanx_right_in[18] ) , - .X ( ropt_net_211 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_162 ) , - .X ( ropt_net_204 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_163 ) , - .X ( ropt_net_197 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__20 ( .A ( chanx_left_in[4] ) , - .X ( ropt_net_189 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( ropt_net_195 ) , - .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( ropt_net_164 ) , - .X ( ropt_net_208 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_165 ) , - .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_25__24 ( .A ( chanx_left_in[9] ) , - .X ( ropt_net_182 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_26__25 ( .A ( chanx_left_in[10] ) , - .X ( ropt_net_186 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( - .A ( Test_en__FEEDTHRU_0[0] ) , .X ( ropt_net_215 ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_782 ( - .A ( Test_en__FEEDTHRU_0[0] ) , .X ( ropt_net_216 ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_783 ( .A ( ropt_net_168 ) , - .X ( ropt_net_210 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_784 ( .A ( ropt_net_169 ) , - .X ( ropt_net_214 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_31__30 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_180 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_785 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_213 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_160 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_196 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_814 ( .A ( ropt_net_196 ) , - .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_816 ( .A ( ropt_net_197 ) , - .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_787 ( .A ( chanx_left_in[5] ) , - .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_173 ) , - .X ( ropt_net_199 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_75 ( .A ( chanx_right_in[3] ) , - .X ( BUF_net_75 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( chanx_left_in[18] ) , - .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_818 ( .A ( ropt_net_198 ) , - .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_78 ( .A ( chanx_right_in[11] ) , - .X ( BUF_net_78 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_819 ( .A ( ropt_net_199 ) , - .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( chanx_left_in[6] ) , - .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_822 ( .A ( ropt_net_200 ) , - .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_212 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_823 ( .A ( ropt_net_201 ) , - .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_84 ( .A ( chanx_left_in[2] ) , - .X ( BUF_net_84 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_792 ( .A ( ropt_net_177 ) , - .X ( ropt_net_193 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_86 ( .A ( chanx_left_in[8] ) , - .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_178 ) , - .X ( ropt_net_202 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_179 ) , - .X ( ropt_net_198 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_180 ) , - .X ( ropt_net_201 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_90 ( .A ( chanx_left_in[16] ) , - .X ( ropt_net_183 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_181 ) , - .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_824 ( .A ( ropt_net_202 ) , - .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_826 ( .A ( ropt_net_203 ) , - .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_100 ( .A ( chanx_right_in[0] ) , - .X ( ropt_net_163 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( ropt_net_182 ) , - .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_183 ) , - .X ( ropt_net_195 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_184 ) , - .X ( ropt_net_206 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_185 ) , - .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_186 ) , - .X ( ropt_net_200 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_187 ) , - .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_188 ) , - .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_189 ) , - .X ( ropt_net_203 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_190 ) , - .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_191 ) , - .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_827 ( .A ( ropt_net_204 ) , - .X ( chany_bottom_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_828 ( .A ( ropt_net_205 ) , - .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_113 ( .A ( chanx_left_in[12] ) , - .X ( ropt_net_185 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_829 ( .A ( ropt_net_206 ) , - .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_830 ( .A ( ropt_net_207 ) , - .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_208 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_832 ( .A ( ropt_net_209 ) , - .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_122 ( .A ( chanx_right_in[16] ) , - .X ( ropt_net_159 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_834 ( .A ( ropt_net_210 ) , - .X ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_129 ( .A ( chanx_right_in[1] ) , - .X ( ropt_net_173 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_835 ( .A ( ropt_net_211 ) , - .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_131 ( .A ( BUF_net_75 ) , - .X ( ropt_net_207 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_132 ( .A ( chanx_right_in[7] ) , - .X ( ropt_net_190 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_836 ( .A ( ropt_net_212 ) , - .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_134 ( .A ( BUF_net_78 ) , - .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_837 ( .A ( ropt_net_213 ) , - .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_839 ( .A ( ropt_net_214 ) , - .X ( chany_bottom_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_840 ( .A ( ropt_net_215 ) , - .X ( Test_en__FEEDTHRU_1[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_138 ( .A ( chanx_left_in[0] ) , - .X ( ropt_net_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_139 ( .A ( BUF_net_84 ) , - .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_841 ( .A ( ropt_net_216 ) , - .X ( Test_en__FEEDTHRU_2[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_141 ( .A ( chanx_left_in[13] ) , - .X ( ropt_net_181 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_142 ( .A ( chanx_left_in[14] ) , - .X ( ropt_net_178 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y0 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y0 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x294400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x312800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x690000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x892400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x331200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x349600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x358800y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x680800y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x285200y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x317400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x335800y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x400200y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x892400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x358800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x377200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x427800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x487600y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1145400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1163800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1173000y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x193200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x202400y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x248400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x340400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x501400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x510600y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x611800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x621000y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x800400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x818800y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x170200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x207000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x303600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x322000y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x409400y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x450800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x460000y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x506000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x542800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x552000y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x699200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x708400y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x754400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x998200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1058000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x142600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x161000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x170200y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x216200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x253000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x478400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x496800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x506000y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x552000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x570400y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x722200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x740600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x749800y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x975200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1012000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1048800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1145400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1163800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1173000y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x36800y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x115000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x276000y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x358800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x418600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x469200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x519800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x529000y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x644000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x653200y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x699200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x717600y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1085600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x101200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x138000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x156400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x207000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x225400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x234600y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x322000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x432400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x469200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x519800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x565800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x602600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x653200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x772800y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x961400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x970600y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1058000y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x188600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x197800y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x243800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x427800y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x473800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x510600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x547400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x565800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x616400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x625600y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x708400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x768200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x851000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x906200y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x952200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x989000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x998200y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x69000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x78200y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x358800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x432400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x483000y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x529000y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x680800y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x759000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x924600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x933800y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x161000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x202400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x239200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x312800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x552000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x561200y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x851000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1108600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1117800y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x179400y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x197800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x464600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x483000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x565800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x602600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x611800y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x726800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x989000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1039600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1090200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1099400y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x119600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x253000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x289800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x349600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x409400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x478400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x496800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x547400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x607200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x625600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x634800y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x713000y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x791200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x828000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x837200y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x998200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x147200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x248400y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x303600y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x349600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x427800y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x506000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x584200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x593400y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x639400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x676200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x713000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x731400y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x777400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x837200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x929200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x966000y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x230000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x239200y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x395600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x414000y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x460000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x690000y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x731400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x749800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x759000y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x354200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x409400y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x524400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x533600y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x579600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x648600y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x726800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x745200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x754400y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x800400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x883200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x933800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x952200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1002800y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x234600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x253000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x303600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x395600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x483000y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x565800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x625600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x676200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x713000y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x759000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x777400y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x823400y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x841800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x906200y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x984400y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x161000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x197800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x234600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x253000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x303600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x340400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x432400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x450800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x501400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x519800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x529000y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x575000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x717600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x814200y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x901600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x984400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1021200y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1099400y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x188600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x207000y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x285200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x386400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x423200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x460000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x478400y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x736000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x754400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x887800y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x929200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x966000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1007400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1025800y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x119600y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x207000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x243800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x299000y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x345000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x432400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x469200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x547400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x657800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x713000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x749800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x837200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1067200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1117800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1154600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1173000y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x156400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x193200y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x271400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x308200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x345000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x455400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x492200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x565800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x602600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x639400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x676200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x713000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x749800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x786600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x795800y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x841800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x998200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1016600y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1062600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1099400y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1131600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x147200y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x193200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x266800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x285200y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x418600y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x496800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x570400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x653200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x690000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x699200y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1067200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1085600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x151800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x188600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x225400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x262200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x299000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x335800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x372600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x409400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x450800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x671600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x690000y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x768200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x841800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x924600y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1002800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1039600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1076400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1094800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x115000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x151800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x188600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x248400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x285200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x303600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x312800y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x358800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x427800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1025800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1062600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1099400y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x156400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x193200y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x271400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x308200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x345000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x395600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x432400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x469200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x708400y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x786600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x823400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x860200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x887800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x897000y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1016600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1035000y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1081000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1099400y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x110400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x119600y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x197800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x207000y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x248400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x358800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x464600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x483000y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x565800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x740600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x897000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1117800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1154600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1173000y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x36800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x285200y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x464600y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x616400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x634800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x754400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x791200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x998200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1016600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x36800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x46000y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x78200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x115000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x124200y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x170200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x207000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x243800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x262200y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x308200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x358800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x501400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x510600y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x552000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x561200y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x639400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x754400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x823400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x860200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x897000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1117800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1154600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1173000y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x101200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x138000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x174800y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x216200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x266800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x414000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x708400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x782000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x818800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x855600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1145400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1163800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1173000y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x220800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x239200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x358800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x538200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x708400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x782000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x818800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x855600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x892400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x929200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x966000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1002800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1039600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1076400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1113200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y870400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1145400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1163800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1173000y870400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y897600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1163800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1173000y897600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x515200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x533600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x542800y924800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x708400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x782000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x818800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x855600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y924800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1145400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1163800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1173000y924800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y952000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1145400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1163800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1173000y952000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__2__icv_in_design.pt.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__2__icv_in_design.pt.v deleted file mode 100644 index 804da25..0000000 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__2__icv_in_design.pt.v +++ /dev/null @@ -1,2235 +0,0 @@ -// -// -// -// -// -// -module sb_1__2__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_28__62 ( .A ( mem_out[2] ) , - .X ( net_net_120 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_120 ( .A ( net_net_120 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__61 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__60 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size3_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__59 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__58 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__57 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__56 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__55 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size3_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__54 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__53 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__52 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_126 ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__51 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__50 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__49 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__48 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__47 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__46 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__45 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__44 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__43 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_125 ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size7_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__42 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__41 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size14_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__40 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size14_mem ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__39 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size14_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:13] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size14 ( in , sram , sram_inv , out , p0 ) ; -input [0:13] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size9_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__38 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size9_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__37 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size9_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__36 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size9_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:8] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size9_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:8] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , p0 ) ; -input [0:8] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__35 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module sb_1__2_ ( prog_clk , chanx_right_in , right_top_grid_pin_1_ , - right_bottom_grid_pin_34_ , right_bottom_grid_pin_35_ , - right_bottom_grid_pin_36_ , right_bottom_grid_pin_37_ , - right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ , - right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ , chany_bottom_in , - bottom_left_grid_pin_42_ , bottom_left_grid_pin_43_ , - bottom_left_grid_pin_44_ , bottom_left_grid_pin_45_ , - bottom_left_grid_pin_46_ , bottom_left_grid_pin_47_ , - bottom_left_grid_pin_48_ , bottom_left_grid_pin_49_ , chanx_left_in , - left_top_grid_pin_1_ , left_bottom_grid_pin_34_ , - left_bottom_grid_pin_35_ , left_bottom_grid_pin_36_ , - left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , - left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , - left_bottom_grid_pin_41_ , ccff_head , chanx_right_out , - chany_bottom_out , chanx_left_out , ccff_tail , SC_IN_TOP , SC_IN_BOT , - SC_OUT_TOP , SC_OUT_BOT , Test_en__FEEDTHRU_0 , Test_en__FEEDTHRU_1 , - Test_en__FEEDTHRU_2 , clk__FEEDTHRU_0 , clk__FEEDTHRU_1 , - clk__FEEDTHRU_2 ) ; -input [0:0] prog_clk ; -input [0:19] chanx_right_in ; -input [0:0] right_top_grid_pin_1_ ; -input [0:0] right_bottom_grid_pin_34_ ; -input [0:0] right_bottom_grid_pin_35_ ; -input [0:0] right_bottom_grid_pin_36_ ; -input [0:0] right_bottom_grid_pin_37_ ; -input [0:0] right_bottom_grid_pin_38_ ; -input [0:0] right_bottom_grid_pin_39_ ; -input [0:0] right_bottom_grid_pin_40_ ; -input [0:0] right_bottom_grid_pin_41_ ; -input [0:19] chany_bottom_in ; -input [0:0] bottom_left_grid_pin_42_ ; -input [0:0] bottom_left_grid_pin_43_ ; -input [0:0] bottom_left_grid_pin_44_ ; -input [0:0] bottom_left_grid_pin_45_ ; -input [0:0] bottom_left_grid_pin_46_ ; -input [0:0] bottom_left_grid_pin_47_ ; -input [0:0] bottom_left_grid_pin_48_ ; -input [0:0] bottom_left_grid_pin_49_ ; -input [0:19] chanx_left_in ; -input [0:0] left_top_grid_pin_1_ ; -input [0:0] left_bottom_grid_pin_34_ ; -input [0:0] left_bottom_grid_pin_35_ ; -input [0:0] left_bottom_grid_pin_36_ ; -input [0:0] left_bottom_grid_pin_37_ ; -input [0:0] left_bottom_grid_pin_38_ ; -input [0:0] left_bottom_grid_pin_39_ ; -input [0:0] left_bottom_grid_pin_40_ ; -input [0:0] left_bottom_grid_pin_41_ ; -input [0:0] ccff_head ; -output [0:19] chanx_right_out ; -output [0:19] chany_bottom_out ; -output [0:19] chanx_left_out ; -output [0:0] ccff_tail ; -input SC_IN_TOP ; -input SC_IN_BOT ; -output SC_OUT_TOP ; -output SC_OUT_BOT ; -input [0:0] Test_en__FEEDTHRU_0 ; -output [0:0] Test_en__FEEDTHRU_1 ; -output [0:0] Test_en__FEEDTHRU_2 ; -input [0:0] clk__FEEDTHRU_0 ; -output [0:0] clk__FEEDTHRU_1 ; -output [0:0] clk__FEEDTHRU_2 ; - -wire [0:2] mux_bottom_track_11_undriven_sram_inv ; -wire [0:1] mux_bottom_track_13_undriven_sram_inv ; -wire [0:1] mux_bottom_track_15_undriven_sram_inv ; -wire [0:1] mux_bottom_track_17_undriven_sram_inv ; -wire [0:1] mux_bottom_track_19_undriven_sram_inv ; -wire [0:2] mux_bottom_track_1_undriven_sram_inv ; -wire [0:1] mux_bottom_track_21_undriven_sram_inv ; -wire [0:1] mux_bottom_track_23_undriven_sram_inv ; -wire [0:2] mux_bottom_track_25_undriven_sram_inv ; -wire [0:1] mux_bottom_track_27_undriven_sram_inv ; -wire [0:2] mux_bottom_track_3_undriven_sram_inv ; -wire [0:2] mux_bottom_track_5_undriven_sram_inv ; -wire [0:2] mux_bottom_track_7_undriven_sram_inv ; -wire [0:2] mux_bottom_track_9_undriven_sram_inv ; -wire [0:2] mux_left_track_17_undriven_sram_inv ; -wire [0:3] mux_left_track_1_undriven_sram_inv ; -wire [0:2] mux_left_track_25_undriven_sram_inv ; -wire [0:2] mux_left_track_33_undriven_sram_inv ; -wire [0:3] mux_left_track_3_undriven_sram_inv ; -wire [0:3] mux_left_track_5_undriven_sram_inv ; -wire [0:3] mux_left_track_9_undriven_sram_inv ; -wire [0:3] mux_right_track_0_undriven_sram_inv ; -wire [0:2] mux_right_track_16_undriven_sram_inv ; -wire [0:2] mux_right_track_24_undriven_sram_inv ; -wire [0:3] mux_right_track_2_undriven_sram_inv ; -wire [0:2] mux_right_track_32_undriven_sram_inv ; -wire [0:3] mux_right_track_4_undriven_sram_inv ; -wire [0:3] mux_right_track_8_undriven_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size14_0_sram ; -wire [0:3] mux_tree_tapbuf_size14_1_sram ; -wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail ; -wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; -wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:1] mux_tree_tapbuf_size3_2_sram ; -wire [0:1] mux_tree_tapbuf_size3_3_sram ; -wire [0:1] mux_tree_tapbuf_size3_4_sram ; -wire [0:1] mux_tree_tapbuf_size3_5_sram ; -wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size4_0_sram ; -wire [0:2] mux_tree_tapbuf_size4_1_sram ; -wire [0:2] mux_tree_tapbuf_size4_2_sram ; -wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size5_0_sram ; -wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size7_0_sram ; -wire [0:2] mux_tree_tapbuf_size7_1_sram ; -wire [0:2] mux_tree_tapbuf_size7_2_sram ; -wire [0:2] mux_tree_tapbuf_size7_3_sram ; -wire [0:2] mux_tree_tapbuf_size7_4_sram ; -wire [0:2] mux_tree_tapbuf_size7_5_sram ; -wire [0:2] mux_tree_tapbuf_size7_6_sram ; -wire [0:2] mux_tree_tapbuf_size7_7_sram ; -wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_7_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size9_0_sram ; -wire [0:3] mux_tree_tapbuf_size9_1_sram ; -wire [0:3] mux_tree_tapbuf_size9_2_sram ; -wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size9_mem_2_ccff_tail ; -// - -assign SC_IN_TOP = SC_IN_BOT ; -assign clk__FEEDTHRU_1[0] = clk__FEEDTHRU_0[0] ; -assign clk__FEEDTHRU_2[0] = clk__FEEDTHRU_0[0] ; - -sb_1__2__mux_tree_tapbuf_size10 mux_right_track_0 ( - .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] , - right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , - right_bottom_grid_pin_41_[0] , chany_bottom_in[5] , - chany_bottom_in[12] , chany_bottom_in[19] , chanx_left_in[2] , - chanx_left_in[12] } ) , - .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_right_track_0_undriven_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_157 ) ) ; -sb_1__2__mux_tree_tapbuf_size10_mem mem_right_track_0 ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size9 mux_right_track_2 ( - .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , - right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , - chany_bottom_in[4] , chany_bottom_in[11] , chany_bottom_in[18] , - chanx_left_in[4] , chanx_left_in[13] } ) , - .sram ( mux_tree_tapbuf_size9_0_sram ) , - .sram_inv ( mux_right_track_2_undriven_sram_inv ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_157 ) ) ; -sb_1__2__mux_tree_tapbuf_size9_0 mux_left_track_1 ( - .in ( { chanx_right_in[2] , chanx_right_in[12] , chany_bottom_in[6] , - chany_bottom_in[13] , left_top_grid_pin_1_[0] , - left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , - left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , - .sram ( mux_tree_tapbuf_size9_1_sram ) , - .sram_inv ( mux_left_track_1_undriven_sram_inv ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_155 ) ) ; -sb_1__2__mux_tree_tapbuf_size9_1 mux_left_track_3 ( - .in ( { chanx_right_in[4] , chanx_right_in[13] , chany_bottom_in[0] , - chany_bottom_in[7] , chany_bottom_in[14] , - left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , - left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , - .sram ( mux_tree_tapbuf_size9_2_sram ) , - .sram_inv ( mux_left_track_3_undriven_sram_inv ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_154 ) ) ; -sb_1__2__mux_tree_tapbuf_size9_mem mem_right_track_2 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size9_0_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size9_mem_0 mem_left_track_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size9_1_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size9_mem_1 mem_left_track_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size9_2_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size14 mux_right_track_4 ( - .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_34_[0] , - right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_36_[0] , - right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_38_[0] , - right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_40_[0] , - right_bottom_grid_pin_41_[0] , chany_bottom_in[3] , - chany_bottom_in[10] , chany_bottom_in[17] , chanx_left_in[5] , - chanx_left_in[14] } ) , - .sram ( mux_tree_tapbuf_size14_0_sram ) , - .sram_inv ( mux_right_track_4_undriven_sram_inv ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_157 ) ) ; -sb_1__2__mux_tree_tapbuf_size14_0 mux_left_track_5 ( - .in ( { chanx_right_in[5] , chanx_right_in[14] , chany_bottom_in[1] , - chany_bottom_in[8] , chany_bottom_in[15] , left_top_grid_pin_1_[0] , - left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_35_[0] , - left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_37_[0] , - left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_39_[0] , - left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_41_[0] } ) , - .sram ( mux_tree_tapbuf_size14_1_sram ) , - .sram_inv ( mux_left_track_5_undriven_sram_inv ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_154 ) ) ; -sb_1__2__mux_tree_tapbuf_size14_mem mem_right_track_4 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size14_0_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size14_mem_0 mem_left_track_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size14_1_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size8 mux_right_track_8 ( - .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_37_[0] , - right_bottom_grid_pin_41_[0] , chany_bottom_in[2] , - chany_bottom_in[9] , chany_bottom_in[16] , chanx_left_in[6] , - chanx_left_in[16] } ) , - .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_right_track_8_undriven_sram_inv ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_153 ) ) ; -sb_1__2__mux_tree_tapbuf_size8_0 mux_left_track_9 ( - .in ( { chanx_right_in[6] , chanx_right_in[16] , chany_bottom_in[2] , - chany_bottom_in[9] , chany_bottom_in[16] , left_top_grid_pin_1_[0] , - left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_41_[0] } ) , - .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_left_track_9_undriven_sram_inv ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_155 ) ) ; -sb_1__2__mux_tree_tapbuf_size8_mem mem_right_track_8 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size8_mem_0 mem_left_track_9 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size7_6 mux_right_track_16 ( - .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_38_[0] , - chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[15] , - chanx_left_in[8] , chanx_left_in[17] } ) , - .sram ( mux_tree_tapbuf_size7_0_sram ) , - .sram_inv ( mux_right_track_16_undriven_sram_inv ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_153 ) ) ; -sb_1__2__mux_tree_tapbuf_size7 mux_right_track_24 ( - .in ( { right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_39_[0] , - chany_bottom_in[0] , chany_bottom_in[7] , chany_bottom_in[14] , - chanx_left_in[9] , chanx_left_in[18] } ) , - .sram ( mux_tree_tapbuf_size7_1_sram ) , - .sram_inv ( mux_right_track_24_undriven_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_153 ) ) ; -sb_1__2__mux_tree_tapbuf_size7_0 mux_bottom_track_1 ( - .in ( { chanx_right_in[2] , bottom_left_grid_pin_42_[0] , - bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , - bottom_left_grid_pin_48_[0] , chanx_left_in[1] , chanx_left_in[2] } ) , - .sram ( mux_tree_tapbuf_size7_2_sram ) , - .sram_inv ( mux_bottom_track_1_undriven_sram_inv ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_155 ) ) ; -sb_1__2__mux_tree_tapbuf_size7_1 mux_bottom_track_3 ( - .in ( { chanx_right_in[4] , bottom_left_grid_pin_43_[0] , - bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , - bottom_left_grid_pin_49_[0] , chanx_left_in[3] , chanx_left_in[4] } ) , - .sram ( mux_tree_tapbuf_size7_3_sram ) , - .sram_inv ( mux_bottom_track_3_undriven_sram_inv ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_156 ) ) ; -sb_1__2__mux_tree_tapbuf_size7_2 mux_bottom_track_5 ( - .in ( { chanx_right_in[5] , bottom_left_grid_pin_42_[0] , - bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , - bottom_left_grid_pin_48_[0] , chanx_left_in[5] , chanx_left_in[7] } ) , - .sram ( mux_tree_tapbuf_size7_4_sram ) , - .sram_inv ( mux_bottom_track_5_undriven_sram_inv ) , - .out ( { ropt_net_169 } ) , - .p0 ( optlc_net_154 ) ) ; -sb_1__2__mux_tree_tapbuf_size7_3 mux_bottom_track_7 ( - .in ( { chanx_right_in[6] , bottom_left_grid_pin_43_[0] , - bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , - bottom_left_grid_pin_49_[0] , chanx_left_in[6] , chanx_left_in[11] } ) , - .sram ( mux_tree_tapbuf_size7_5_sram ) , - .sram_inv ( mux_bottom_track_7_undriven_sram_inv ) , - .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_154 ) ) ; -sb_1__2__mux_tree_tapbuf_size7_4 mux_left_track_17 ( - .in ( { chanx_right_in[8] , chanx_right_in[17] , chany_bottom_in[3] , - chany_bottom_in[10] , chany_bottom_in[17] , - left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_38_[0] } ) , - .sram ( mux_tree_tapbuf_size7_6_sram ) , - .sram_inv ( mux_left_track_17_undriven_sram_inv ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_155 ) ) ; -sb_1__2__mux_tree_tapbuf_size7_5 mux_left_track_25 ( - .in ( { chanx_right_in[9] , chanx_right_in[18] , chany_bottom_in[4] , - chany_bottom_in[11] , chany_bottom_in[18] , - left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_39_[0] } ) , - .sram ( mux_tree_tapbuf_size7_7_sram ) , - .sram_inv ( mux_left_track_25_undriven_sram_inv ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_156 ) ) ; -sb_1__2__mux_tree_tapbuf_size7_mem_6 mem_right_track_16 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size7_mem mem_right_track_24 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size7_mem_0 mem_bottom_track_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size7_mem_1 mem_bottom_track_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_3_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size7_mem_2 mem_bottom_track_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_4_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size7_mem_3 mem_bottom_track_7 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_5_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size7_mem_4 mem_left_track_17 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_6_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size7_mem_5 mem_left_track_25 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_7_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size5 mux_right_track_32 ( - .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_40_[0] , - chany_bottom_in[6] , chany_bottom_in[13] , chanx_left_in[10] } ) , - .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_right_track_32_undriven_sram_inv ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_153 ) ) ; -sb_1__2__mux_tree_tapbuf_size5_mem mem_right_track_32 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size4 mux_bottom_track_9 ( - .in ( { chanx_right_in[8] , bottom_left_grid_pin_42_[0] , - chanx_left_in[8] , chanx_left_in[15] } ) , - .sram ( mux_tree_tapbuf_size4_0_sram ) , - .sram_inv ( mux_bottom_track_9_undriven_sram_inv ) , - .out ( { ropt_net_168 } ) , - .p0 ( optlc_net_154 ) ) ; -sb_1__2__mux_tree_tapbuf_size4_0 mux_bottom_track_11 ( - .in ( { chanx_right_in[9] , bottom_left_grid_pin_43_[0] , - chanx_left_in[9] , chanx_left_in[19] } ) , - .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_bottom_track_11_undriven_sram_inv ) , - .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_154 ) ) ; -sb_1__2__mux_tree_tapbuf_size4_1 mux_bottom_track_25 ( - .in ( { chanx_right_in[18] , chanx_right_in[19] , - bottom_left_grid_pin_42_[0] , chanx_left_in[18] } ) , - .sram ( mux_tree_tapbuf_size4_2_sram ) , - .sram_inv ( mux_bottom_track_25_undriven_sram_inv ) , - .out ( { ropt_net_162 } ) , - .p0 ( optlc_net_153 ) ) ; -sb_1__2__mux_tree_tapbuf_size4_mem mem_bottom_track_9 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size4_mem_0 mem_bottom_track_11 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size4_mem_1 mem_bottom_track_25 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size3_0 mux_bottom_track_13 ( - .in ( { chanx_right_in[10] , bottom_left_grid_pin_44_[0] , - chanx_left_in[10] } ) , - .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_bottom_track_13_undriven_sram_inv ) , - .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_156 ) ) ; -sb_1__2__mux_tree_tapbuf_size3_1 mux_bottom_track_15 ( - .in ( { chanx_right_in[12] , bottom_left_grid_pin_45_[0] , - chanx_left_in[12] } ) , - .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_bottom_track_15_undriven_sram_inv ) , - .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_156 ) ) ; -sb_1__2__mux_tree_tapbuf_size3_2 mux_bottom_track_17 ( - .in ( { chanx_right_in[13] , bottom_left_grid_pin_46_[0] , - chanx_left_in[13] } ) , - .sram ( mux_tree_tapbuf_size3_2_sram ) , - .sram_inv ( mux_bottom_track_17_undriven_sram_inv ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_156 ) ) ; -sb_1__2__mux_tree_tapbuf_size3_3 mux_bottom_track_19 ( - .in ( { chanx_right_in[14] , bottom_left_grid_pin_47_[0] , - chanx_left_in[14] } ) , - .sram ( mux_tree_tapbuf_size3_3_sram ) , - .sram_inv ( mux_bottom_track_19_undriven_sram_inv ) , - .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_156 ) ) ; -sb_1__2__mux_tree_tapbuf_size3_4 mux_bottom_track_21 ( - .in ( { chanx_right_in[16] , bottom_left_grid_pin_48_[0] , - chanx_left_in[16] } ) , - .sram ( mux_tree_tapbuf_size3_4_sram ) , - .sram_inv ( mux_bottom_track_21_undriven_sram_inv ) , - .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_156 ) ) ; -sb_1__2__mux_tree_tapbuf_size3 mux_bottom_track_23 ( - .in ( { chanx_right_in[17] , bottom_left_grid_pin_49_[0] , - chanx_left_in[17] } ) , - .sram ( mux_tree_tapbuf_size3_5_sram ) , - .sram_inv ( mux_bottom_track_23_undriven_sram_inv ) , - .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_153 ) ) ; -sb_1__2__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_13 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size3_mem_1 mem_bottom_track_15 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size3_mem_2 mem_bottom_track_17 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size3_mem_3 mem_bottom_track_19 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size3_mem_4 mem_bottom_track_21 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_4_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size3_mem mem_bottom_track_23 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_5_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size2 mux_bottom_track_27 ( - .in ( { chanx_right_in[15] , bottom_left_grid_pin_43_[0] } ) , - .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_bottom_track_27_undriven_sram_inv ) , - .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_153 ) ) ; -sb_1__2__mux_tree_tapbuf_size2_mem mem_bottom_track_27 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; -sb_1__2__mux_tree_tapbuf_size6 mux_left_track_33 ( - .in ( { chanx_right_in[10] , chany_bottom_in[5] , chany_bottom_in[12] , - chany_bottom_in[19] , left_bottom_grid_pin_36_[0] , - left_bottom_grid_pin_40_[0] } ) , - .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_left_track_33_undriven_sram_inv ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_154 ) ) ; -sb_1__2__mux_tree_tapbuf_size6_mem mem_left_track_33 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , - .ccff_tail ( { ropt_net_164 } ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_811 ( .A ( ropt_net_193 ) , - .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_153 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_150 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_154 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_152 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_155 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__4 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_179 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chanx_right_in[5] ) , - .X ( ropt_net_188 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__6 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_177 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_154 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_156 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_191 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_187 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_156 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , - .HI ( optlc_net_157 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( chanx_right_in[2] ) , - .X ( ropt_net_194 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_159 ) , - .X ( ropt_net_205 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( .A ( ropt_net_160 ) , - .X ( ropt_net_209 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chanx_right_in[14] ) , - .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_194 ) , - .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__16 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_184 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( chanx_right_in[18] ) , - .X ( ropt_net_211 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_162 ) , - .X ( ropt_net_204 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_163 ) , - .X ( ropt_net_197 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__20 ( .A ( chanx_left_in[4] ) , - .X ( ropt_net_189 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( ropt_net_195 ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( ropt_net_164 ) , - .X ( ropt_net_208 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_165 ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_25__24 ( .A ( chanx_left_in[9] ) , - .X ( ropt_net_182 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_26__25 ( .A ( chanx_left_in[10] ) , - .X ( ropt_net_186 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( - .A ( Test_en__FEEDTHRU_0[0] ) , .X ( ropt_net_215 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_782 ( - .A ( Test_en__FEEDTHRU_0[0] ) , .X ( ropt_net_216 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_783 ( .A ( ropt_net_168 ) , - .X ( ropt_net_210 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_784 ( .A ( ropt_net_169 ) , - .X ( ropt_net_214 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_31__30 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_180 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_785 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_213 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_160 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_196 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_814 ( .A ( ropt_net_196 ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_816 ( .A ( ropt_net_197 ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_787 ( .A ( chanx_left_in[5] ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_173 ) , - .X ( ropt_net_199 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_75 ( .A ( chanx_right_in[3] ) , - .X ( BUF_net_75 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( chanx_left_in[18] ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_818 ( .A ( ropt_net_198 ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_78 ( .A ( chanx_right_in[11] ) , - .X ( BUF_net_78 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_819 ( .A ( ropt_net_199 ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( chanx_left_in[6] ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_822 ( .A ( ropt_net_200 ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_212 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_823 ( .A ( ropt_net_201 ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_84 ( .A ( chanx_left_in[2] ) , - .X ( BUF_net_84 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_792 ( .A ( ropt_net_177 ) , - .X ( ropt_net_193 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_86 ( .A ( chanx_left_in[8] ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_178 ) , - .X ( ropt_net_202 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_179 ) , - .X ( ropt_net_198 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_180 ) , - .X ( ropt_net_201 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_90 ( .A ( chanx_left_in[16] ) , - .X ( ropt_net_183 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_181 ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_824 ( .A ( ropt_net_202 ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_826 ( .A ( ropt_net_203 ) , - .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_100 ( .A ( chanx_right_in[0] ) , - .X ( ropt_net_163 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( ropt_net_182 ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_183 ) , - .X ( ropt_net_195 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_184 ) , - .X ( ropt_net_206 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_185 ) , - .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_186 ) , - .X ( ropt_net_200 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_187 ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_188 ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_189 ) , - .X ( ropt_net_203 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_190 ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_191 ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_827 ( .A ( ropt_net_204 ) , - .X ( chany_bottom_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_828 ( .A ( ropt_net_205 ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_113 ( .A ( chanx_left_in[12] ) , - .X ( ropt_net_185 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_829 ( .A ( ropt_net_206 ) , - .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_830 ( .A ( ropt_net_207 ) , - .X ( chany_bottom_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_208 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_832 ( .A ( ropt_net_209 ) , - .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_122 ( .A ( chanx_right_in[16] ) , - .X ( ropt_net_159 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_834 ( .A ( ropt_net_210 ) , - .X ( chany_bottom_out[4] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_129 ( .A ( chanx_right_in[1] ) , - .X ( ropt_net_173 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_835 ( .A ( ropt_net_211 ) , - .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_131 ( .A ( BUF_net_75 ) , - .X ( ropt_net_207 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_132 ( .A ( chanx_right_in[7] ) , - .X ( ropt_net_190 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_836 ( .A ( ropt_net_212 ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_134 ( .A ( BUF_net_78 ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_837 ( .A ( ropt_net_213 ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_839 ( .A ( ropt_net_214 ) , - .X ( chany_bottom_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_840 ( .A ( ropt_net_215 ) , - .X ( Test_en__FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_138 ( .A ( chanx_left_in[0] ) , - .X ( ropt_net_165 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_139 ( .A ( BUF_net_84 ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_841 ( .A ( ropt_net_216 ) , - .X ( Test_en__FEEDTHRU_2[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_141 ( .A ( chanx_left_in[13] ) , - .X ( ropt_net_181 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_142 ( .A ( chanx_left_in[14] ) , - .X ( ropt_net_178 ) ) ; -endmodule - - diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__0__icv_in_design.fm.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__0__icv_in_design.fm.v deleted file mode 100644 index 1123cf1..0000000 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__0__icv_in_design.fm.v +++ /dev/null @@ -1,1900 +0,0 @@ -// -// -// -// -// -// -module sb_2__0__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__39 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__38 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__37 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__36 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__const1 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sb_2__0__const1 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -endmodule - - -module sb_2__0__const1_28 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sb_2__0__const1_28 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -endmodule - - -module sb_2__0__const1_27 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sb_2__0__const1_27 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -endmodule - - -module sb_2__0__const1_26 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sb_2__0__const1_26 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__35 ( .A ( mem_out[1] ) , - .X ( net_net_64 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_64 ( .A ( net_net_64 ) , - .X ( net_net_63 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_92 ( .A ( net_net_63 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__34 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__33 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__32 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__31 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__30 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__29 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__28 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__27 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__26 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__25 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__24 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__23 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_18 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__22 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_17 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__21 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__20 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__19 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__18 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__17 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__16 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__const1_25 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -sb_2__0__const1_25 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_2__0__const1_24 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__0__const1_24 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__0__const1_23 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__0__const1_23 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__0__const1_22 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__0__const1_22 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_51 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_2__0__const1_21 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -sb_2__0__const1_21 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_2__0__const1_20 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__0__const1_20 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__0__const1_19 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -sb_2__0__const1_19 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_2__0__const1_18 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -sb_2__0__const1_18 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_2__0__const1_17 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__0__const1_17 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__0__const1_16 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__0__const1_16 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__0__const1_15 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__0__const1_15 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__0__const1_14 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__0__const1_14 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__0__const1_13 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__0__const1_13 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__0__const1_12 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__0__const1_12 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__0__const1_11 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__0__const1_11 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__0__const1_10 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__0__const1_10 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__0__const1_9 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__0__const1_9 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__0__const1_8 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__0__const1_8 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__0__const1_7 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__0__const1_7 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__0__const1_6 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__0__const1_6 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__15 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__14 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__const1_5 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sb_2__0__const1_5 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_2__0__const1_4 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sb_2__0__const1_4 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__13 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__12 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__const1_3 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -sb_2__0__const1_3 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -endmodule - - -module sb_2__0__const1_2 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -sb_2__0__const1_2 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__11 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__10 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__const1_1 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sb_2__0__const1_1 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module sb_2__0__const1_0 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sb_2__0__const1_0 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module sb_2__0_ ( prog_clk , chany_top_in , top_left_grid_pin_42_ , - top_left_grid_pin_43_ , top_left_grid_pin_44_ , top_left_grid_pin_45_ , - top_left_grid_pin_46_ , top_left_grid_pin_47_ , top_left_grid_pin_48_ , - top_left_grid_pin_49_ , top_right_grid_pin_1_ , chanx_left_in , - left_bottom_grid_pin_1_ , left_bottom_grid_pin_3_ , - left_bottom_grid_pin_5_ , left_bottom_grid_pin_7_ , - left_bottom_grid_pin_9_ , left_bottom_grid_pin_11_ , ccff_head , - chany_top_out , chanx_left_out , ccff_tail ) ; -input [0:0] prog_clk ; -input [0:19] chany_top_in ; -input [0:0] top_left_grid_pin_42_ ; -input [0:0] top_left_grid_pin_43_ ; -input [0:0] top_left_grid_pin_44_ ; -input [0:0] top_left_grid_pin_45_ ; -input [0:0] top_left_grid_pin_46_ ; -input [0:0] top_left_grid_pin_47_ ; -input [0:0] top_left_grid_pin_48_ ; -input [0:0] top_left_grid_pin_49_ ; -input [0:0] top_right_grid_pin_1_ ; -input [0:19] chanx_left_in ; -input [0:0] left_bottom_grid_pin_1_ ; -input [0:0] left_bottom_grid_pin_3_ ; -input [0:0] left_bottom_grid_pin_5_ ; -input [0:0] left_bottom_grid_pin_7_ ; -input [0:0] left_bottom_grid_pin_9_ ; -input [0:0] left_bottom_grid_pin_11_ ; -input [0:0] ccff_head ; -output [0:19] chany_top_out ; -output [0:19] chanx_left_out ; -output [0:0] ccff_tail ; - -wire [0:1] mux_left_track_11_undriven_sram_inv ; -wire [0:1] mux_left_track_13_undriven_sram_inv ; -wire [0:1] mux_left_track_15_undriven_sram_inv ; -wire [0:1] mux_left_track_17_undriven_sram_inv ; -wire [0:1] mux_left_track_19_undriven_sram_inv ; -wire [0:2] mux_left_track_1_undriven_sram_inv ; -wire [0:1] mux_left_track_25_undriven_sram_inv ; -wire [0:1] mux_left_track_27_undriven_sram_inv ; -wire [0:1] mux_left_track_29_undriven_sram_inv ; -wire [0:1] mux_left_track_31_undriven_sram_inv ; -wire [0:1] mux_left_track_33_undriven_sram_inv ; -wire [0:1] mux_left_track_35_undriven_sram_inv ; -wire [0:2] mux_left_track_3_undriven_sram_inv ; -wire [0:2] mux_left_track_5_undriven_sram_inv ; -wire [0:2] mux_left_track_7_undriven_sram_inv ; -wire [0:1] mux_left_track_9_undriven_sram_inv ; -wire [0:2] mux_top_track_0_undriven_sram_inv ; -wire [0:1] mux_top_track_10_undriven_sram_inv ; -wire [0:1] mux_top_track_12_undriven_sram_inv ; -wire [0:1] mux_top_track_14_undriven_sram_inv ; -wire [0:1] mux_top_track_16_undriven_sram_inv ; -wire [0:1] mux_top_track_18_undriven_sram_inv ; -wire [0:1] mux_top_track_20_undriven_sram_inv ; -wire [0:1] mux_top_track_22_undriven_sram_inv ; -wire [0:1] mux_top_track_24_undriven_sram_inv ; -wire [0:1] mux_top_track_26_undriven_sram_inv ; -wire [0:2] mux_top_track_2_undriven_sram_inv ; -wire [0:2] mux_top_track_4_undriven_sram_inv ; -wire [0:2] mux_top_track_6_undriven_sram_inv ; -wire [0:1] mux_top_track_8_undriven_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_10_sram ; -wire [0:1] mux_tree_tapbuf_size2_11_sram ; -wire [0:1] mux_tree_tapbuf_size2_12_sram ; -wire [0:1] mux_tree_tapbuf_size2_13_sram ; -wire [0:1] mux_tree_tapbuf_size2_14_sram ; -wire [0:1] mux_tree_tapbuf_size2_15_sram ; -wire [0:1] mux_tree_tapbuf_size2_16_sram ; -wire [0:1] mux_tree_tapbuf_size2_17_sram ; -wire [0:1] mux_tree_tapbuf_size2_18_sram ; -wire [0:1] mux_tree_tapbuf_size2_19_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_5_sram ; -wire [0:1] mux_tree_tapbuf_size2_6_sram ; -wire [0:1] mux_tree_tapbuf_size2_7_sram ; -wire [0:1] mux_tree_tapbuf_size2_8_sram ; -wire [0:1] mux_tree_tapbuf_size2_9_sram ; -wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; -wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size4_0_sram ; -wire [0:2] mux_tree_tapbuf_size4_1_sram ; -wire [0:2] mux_tree_tapbuf_size4_2_sram ; -wire [0:2] mux_tree_tapbuf_size4_3_sram ; -wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size5_0_sram ; -wire [0:2] mux_tree_tapbuf_size5_1_sram ; -wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size6_1_sram ; -wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; -// - -sb_2__0__mux_tree_tapbuf_size6_0 mux_top_track_0 ( - .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , - top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , - top_right_grid_pin_1_[0] , chanx_left_in[0] } ) , - .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_top_track_0_undriven_sram_inv ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_120 ) ) ; -sb_2__0__mux_tree_tapbuf_size6 mux_top_track_4 ( - .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , - top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , - top_right_grid_pin_1_[0] , chanx_left_in[18] } ) , - .sram ( mux_tree_tapbuf_size6_1_sram ) , - .sram_inv ( mux_top_track_4_undriven_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_119 ) ) ; -sb_2__0__mux_tree_tapbuf_size6_mem_0 mem_top_track_0 ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size6_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size5_0 mux_top_track_2 ( - .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , - top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , - chanx_left_in[19] } ) , - .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_top_track_2_undriven_sram_inv ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_120 ) ) ; -sb_2__0__mux_tree_tapbuf_size5 mux_top_track_6 ( - .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , - top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , - chanx_left_in[17] } ) , - .sram ( mux_tree_tapbuf_size5_1_sram ) , - .sram_inv ( mux_top_track_6_undriven_sram_inv ) , - .out ( chany_top_out[3] ) , .p0 ( optlc_net_121 ) ) ; -sb_2__0__mux_tree_tapbuf_size5_mem_0 mem_top_track_2 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size5_mem mem_top_track_6 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size3 mux_top_track_8 ( - .in ( { top_left_grid_pin_42_[0] , top_right_grid_pin_1_[0] , - chanx_left_in[16] } ) , - .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_top_track_8_undriven_sram_inv ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_121 ) ) ; -sb_2__0__mux_tree_tapbuf_size3_0 mux_top_track_24 ( - .in ( { top_left_grid_pin_42_[0] , top_right_grid_pin_1_[0] , - chanx_left_in[8] } ) , - .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_top_track_24_undriven_sram_inv ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_119 ) ) ; -sb_2__0__mux_tree_tapbuf_size3_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size3_mem_0 mem_top_track_24 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size2_12 mux_top_track_10 ( - .in ( { top_left_grid_pin_43_[0] , chanx_left_in[15] } ) , - .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_top_track_10_undriven_sram_inv ) , - .out ( chany_top_out[5] ) , .p0 ( optlc_net_119 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_13 mux_top_track_12 ( - .in ( { top_left_grid_pin_44_[0] , chanx_left_in[14] } ) , - .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_top_track_12_undriven_sram_inv ) , - .out ( chany_top_out[6] ) , .p0 ( optlc_net_120 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_14 mux_top_track_14 ( - .in ( { top_left_grid_pin_45_[0] , chanx_left_in[13] } ) , - .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_top_track_14_undriven_sram_inv ) , - .out ( chany_top_out[7] ) , .p0 ( optlc_net_120 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_15 mux_top_track_16 ( - .in ( { top_left_grid_pin_46_[0] , chanx_left_in[12] } ) , - .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_top_track_16_undriven_sram_inv ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_120 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_16 mux_top_track_18 ( - .in ( { top_left_grid_pin_47_[0] , chanx_left_in[11] } ) , - .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_top_track_18_undriven_sram_inv ) , - .out ( chany_top_out[9] ) , .p0 ( optlc_net_121 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_17 mux_top_track_20 ( - .in ( { top_left_grid_pin_48_[0] , chanx_left_in[10] } ) , - .sram ( mux_tree_tapbuf_size2_5_sram ) , - .sram_inv ( mux_top_track_20_undriven_sram_inv ) , - .out ( chany_top_out[10] ) , .p0 ( optlc_net_119 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_18 mux_top_track_22 ( - .in ( { top_left_grid_pin_49_[0] , chanx_left_in[9] } ) , - .sram ( mux_tree_tapbuf_size2_6_sram ) , - .sram_inv ( mux_top_track_22_undriven_sram_inv ) , - .out ( chany_top_out[11] ) , .p0 ( optlc_net_119 ) ) ; -sb_2__0__mux_tree_tapbuf_size2 mux_top_track_26 ( - .in ( { top_left_grid_pin_43_[0] , chanx_left_in[7] } ) , - .sram ( mux_tree_tapbuf_size2_7_sram ) , - .sram_inv ( mux_top_track_26_undriven_sram_inv ) , - .out ( chany_top_out[13] ) , .p0 ( optlc_net_120 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_11 mux_left_track_9 ( - .in ( { chany_top_in[16] , left_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size2_8_sram ) , - .sram_inv ( mux_left_track_9_undriven_sram_inv ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_122 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_0 mux_left_track_11 ( - .in ( { chany_top_in[15] , left_bottom_grid_pin_3_[0] } ) , - .sram ( mux_tree_tapbuf_size2_9_sram ) , - .sram_inv ( mux_left_track_11_undriven_sram_inv ) , - .out ( chanx_left_out[5] ) , .p0 ( optlc_net_120 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_1 mux_left_track_13 ( - .in ( { chany_top_in[14] , left_bottom_grid_pin_5_[0] } ) , - .sram ( mux_tree_tapbuf_size2_10_sram ) , - .sram_inv ( mux_left_track_13_undriven_sram_inv ) , - .out ( chanx_left_out[6] ) , .p0 ( optlc_net_120 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_2 mux_left_track_15 ( - .in ( { chany_top_in[13] , left_bottom_grid_pin_7_[0] } ) , - .sram ( mux_tree_tapbuf_size2_11_sram ) , - .sram_inv ( mux_left_track_15_undriven_sram_inv ) , - .out ( chanx_left_out[7] ) , .p0 ( optlc_net_119 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_3 mux_left_track_17 ( - .in ( { chany_top_in[12] , left_bottom_grid_pin_9_[0] } ) , - .sram ( mux_tree_tapbuf_size2_12_sram ) , - .sram_inv ( mux_left_track_17_undriven_sram_inv ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_121 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_4 mux_left_track_19 ( - .in ( { chany_top_in[11] , left_bottom_grid_pin_11_[0] } ) , - .sram ( mux_tree_tapbuf_size2_13_sram ) , - .sram_inv ( mux_left_track_19_undriven_sram_inv ) , - .out ( chanx_left_out[9] ) , .p0 ( optlc_net_119 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_5 mux_left_track_25 ( - .in ( { chany_top_in[8] , left_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size2_14_sram ) , - .sram_inv ( mux_left_track_25_undriven_sram_inv ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_120 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_6 mux_left_track_27 ( - .in ( { chany_top_in[7] , left_bottom_grid_pin_3_[0] } ) , - .sram ( mux_tree_tapbuf_size2_15_sram ) , - .sram_inv ( mux_left_track_27_undriven_sram_inv ) , - .out ( chanx_left_out[13] ) , .p0 ( optlc_net_122 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_7 mux_left_track_29 ( - .in ( { chany_top_in[6] , left_bottom_grid_pin_5_[0] } ) , - .sram ( mux_tree_tapbuf_size2_16_sram ) , - .sram_inv ( mux_left_track_29_undriven_sram_inv ) , - .out ( { ropt_net_126 } ) , - .p0 ( optlc_net_119 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_8 mux_left_track_31 ( - .in ( { chany_top_in[5] , left_bottom_grid_pin_7_[0] } ) , - .sram ( mux_tree_tapbuf_size2_17_sram ) , - .sram_inv ( mux_left_track_31_undriven_sram_inv ) , - .out ( chanx_left_out[15] ) , .p0 ( optlc_net_122 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_9 mux_left_track_33 ( - .in ( { chany_top_in[4] , left_bottom_grid_pin_9_[0] } ) , - .sram ( mux_tree_tapbuf_size2_18_sram ) , - .sram_inv ( mux_left_track_33_undriven_sram_inv ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_119 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_10 mux_left_track_35 ( - .in ( { chany_top_in[3] , left_bottom_grid_pin_11_[0] } ) , - .sram ( mux_tree_tapbuf_size2_19_sram ) , - .sram_inv ( mux_left_track_35_undriven_sram_inv ) , - .out ( chanx_left_out[17] ) , .p0 ( optlc_net_121 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_12 mem_top_track_10 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_13 mem_top_track_12 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_14 mem_top_track_14 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_15 mem_top_track_16 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_16 mem_top_track_18 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_17 mem_top_track_20 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_18 mem_top_track_22 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem mem_top_track_26 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_11 mem_left_track_9 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_0 mem_left_track_11 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_1 mem_left_track_13 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_2 mem_left_track_15 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_11_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_3 mem_left_track_17 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_12_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_4 mem_left_track_19 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_13_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_5 mem_left_track_25 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_14_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_6 mem_left_track_27 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_15_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_7 mem_left_track_29 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_16_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_8 mem_left_track_31 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_17_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_9 mem_left_track_33 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_18_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_10 mem_left_track_35 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , - .ccff_tail ( { ropt_net_130 } ) , - .mem_out ( mux_tree_tapbuf_size2_19_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size4_0 mux_left_track_1 ( - .in ( { chany_top_in[0] , left_bottom_grid_pin_1_[0] , - left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] } ) , - .sram ( mux_tree_tapbuf_size4_0_sram ) , - .sram_inv ( mux_left_track_1_undriven_sram_inv ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_122 ) ) ; -sb_2__0__mux_tree_tapbuf_size4_1 mux_left_track_3 ( - .in ( { chany_top_in[19] , left_bottom_grid_pin_3_[0] , - left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] } ) , - .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_left_track_3_undriven_sram_inv ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_122 ) ) ; -sb_2__0__mux_tree_tapbuf_size4_2 mux_left_track_5 ( - .in ( { chany_top_in[18] , left_bottom_grid_pin_1_[0] , - left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] } ) , - .sram ( mux_tree_tapbuf_size4_2_sram ) , - .sram_inv ( mux_left_track_5_undriven_sram_inv ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_122 ) ) ; -sb_2__0__mux_tree_tapbuf_size4 mux_left_track_7 ( - .in ( { chany_top_in[17] , left_bottom_grid_pin_3_[0] , - left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] } ) , - .sram ( mux_tree_tapbuf_size4_3_sram ) , - .sram_inv ( mux_left_track_7_undriven_sram_inv ) , - .out ( chanx_left_out[3] ) , .p0 ( optlc_net_122 ) ) ; -sb_2__0__mux_tree_tapbuf_size4_mem_0 mem_left_track_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size4_mem_1 mem_left_track_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size4_mem_2 mem_left_track_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size4_mem mem_left_track_7 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_139 ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_708 ( .A ( ropt_net_126 ) , - .X ( ropt_net_139 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_721 ( .A ( ropt_net_140 ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_141 ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__4 ( .A ( chanx_left_in[1] ) , - .X ( ropt_net_133 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_119 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_120 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_121 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__8 ( .A ( chanx_left_in[5] ) , - .X ( ropt_net_134 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__9 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_137 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_723 ( .A ( ropt_net_142 ) , - .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_122 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( ropt_net_143 ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( ropt_net_144 ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( ropt_net_145 ) , - .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_78 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_132 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( ropt_net_146 ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_728 ( .A ( ropt_net_147 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_86 ( .A ( chanx_left_in[2] ) , - .X ( ropt_net_136 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_87 ( .A ( chanx_left_in[3] ) , - .X ( ropt_net_131 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_88 ( .A ( chanx_left_in[4] ) , - .X ( ropt_net_135 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_709 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_148 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_710 ( .A ( chany_top_in[9] ) , - .X ( ropt_net_149 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_711 ( .A ( chany_top_in[1] ) , - .X ( ropt_net_150 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_712 ( .A ( ropt_net_130 ) , - .X ( ropt_net_147 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_713 ( .A ( ropt_net_131 ) , - .X ( ropt_net_141 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_714 ( .A ( ropt_net_132 ) , - .X ( ropt_net_142 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_715 ( .A ( ropt_net_133 ) , - .X ( ropt_net_144 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_716 ( .A ( ropt_net_134 ) , - .X ( ropt_net_140 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_717 ( .A ( ropt_net_135 ) , - .X ( ropt_net_145 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_718 ( .A ( ropt_net_136 ) , - .X ( ropt_net_146 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_137 ) , - .X ( ropt_net_143 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_148 ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_730 ( .A ( ropt_net_149 ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_150 ) , - .X ( chanx_left_out[19] ) ) ; -endmodule - - diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__0__icv_in_design.lvs.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__0__icv_in_design.lvs.v deleted file mode 100644 index 5b4d894..0000000 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__0__icv_in_design.lvs.v +++ /dev/null @@ -1,3803 +0,0 @@ -// -// -// -// -// -// -module sb_2__0__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__39 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__38 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__37 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__36 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__35 ( .A ( mem_out[1] ) , - .X ( net_net_64 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_64 ( .A ( net_net_64 ) , - .X ( net_net_63 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_92 ( .A ( net_net_63 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__34 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__33 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__32 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__31 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__30 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__29 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__28 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__27 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__26 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__25 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__24 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__23 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_18 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__22 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_17 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__21 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__20 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__19 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__18 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__17 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__16 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_51 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__15 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__14 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__13 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__12 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__11 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__10 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__0_ ( prog_clk , chany_top_in , top_left_grid_pin_42_ , - top_left_grid_pin_43_ , top_left_grid_pin_44_ , top_left_grid_pin_45_ , - top_left_grid_pin_46_ , top_left_grid_pin_47_ , top_left_grid_pin_48_ , - top_left_grid_pin_49_ , top_right_grid_pin_1_ , chanx_left_in , - left_bottom_grid_pin_1_ , left_bottom_grid_pin_3_ , - left_bottom_grid_pin_5_ , left_bottom_grid_pin_7_ , - left_bottom_grid_pin_9_ , left_bottom_grid_pin_11_ , ccff_head , - chany_top_out , chanx_left_out , ccff_tail , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:19] chany_top_in ; -input [0:0] top_left_grid_pin_42_ ; -input [0:0] top_left_grid_pin_43_ ; -input [0:0] top_left_grid_pin_44_ ; -input [0:0] top_left_grid_pin_45_ ; -input [0:0] top_left_grid_pin_46_ ; -input [0:0] top_left_grid_pin_47_ ; -input [0:0] top_left_grid_pin_48_ ; -input [0:0] top_left_grid_pin_49_ ; -input [0:0] top_right_grid_pin_1_ ; -input [0:19] chanx_left_in ; -input [0:0] left_bottom_grid_pin_1_ ; -input [0:0] left_bottom_grid_pin_3_ ; -input [0:0] left_bottom_grid_pin_5_ ; -input [0:0] left_bottom_grid_pin_7_ ; -input [0:0] left_bottom_grid_pin_9_ ; -input [0:0] left_bottom_grid_pin_11_ ; -input [0:0] ccff_head ; -output [0:19] chany_top_out ; -output [0:19] chanx_left_out ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; - -wire [0:1] mux_left_track_11_undriven_sram_inv ; -wire [0:1] mux_left_track_13_undriven_sram_inv ; -wire [0:1] mux_left_track_15_undriven_sram_inv ; -wire [0:1] mux_left_track_17_undriven_sram_inv ; -wire [0:1] mux_left_track_19_undriven_sram_inv ; -wire [0:2] mux_left_track_1_undriven_sram_inv ; -wire [0:1] mux_left_track_25_undriven_sram_inv ; -wire [0:1] mux_left_track_27_undriven_sram_inv ; -wire [0:1] mux_left_track_29_undriven_sram_inv ; -wire [0:1] mux_left_track_31_undriven_sram_inv ; -wire [0:1] mux_left_track_33_undriven_sram_inv ; -wire [0:1] mux_left_track_35_undriven_sram_inv ; -wire [0:2] mux_left_track_3_undriven_sram_inv ; -wire [0:2] mux_left_track_5_undriven_sram_inv ; -wire [0:2] mux_left_track_7_undriven_sram_inv ; -wire [0:1] mux_left_track_9_undriven_sram_inv ; -wire [0:2] mux_top_track_0_undriven_sram_inv ; -wire [0:1] mux_top_track_10_undriven_sram_inv ; -wire [0:1] mux_top_track_12_undriven_sram_inv ; -wire [0:1] mux_top_track_14_undriven_sram_inv ; -wire [0:1] mux_top_track_16_undriven_sram_inv ; -wire [0:1] mux_top_track_18_undriven_sram_inv ; -wire [0:1] mux_top_track_20_undriven_sram_inv ; -wire [0:1] mux_top_track_22_undriven_sram_inv ; -wire [0:1] mux_top_track_24_undriven_sram_inv ; -wire [0:1] mux_top_track_26_undriven_sram_inv ; -wire [0:2] mux_top_track_2_undriven_sram_inv ; -wire [0:2] mux_top_track_4_undriven_sram_inv ; -wire [0:2] mux_top_track_6_undriven_sram_inv ; -wire [0:1] mux_top_track_8_undriven_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_10_sram ; -wire [0:1] mux_tree_tapbuf_size2_11_sram ; -wire [0:1] mux_tree_tapbuf_size2_12_sram ; -wire [0:1] mux_tree_tapbuf_size2_13_sram ; -wire [0:1] mux_tree_tapbuf_size2_14_sram ; -wire [0:1] mux_tree_tapbuf_size2_15_sram ; -wire [0:1] mux_tree_tapbuf_size2_16_sram ; -wire [0:1] mux_tree_tapbuf_size2_17_sram ; -wire [0:1] mux_tree_tapbuf_size2_18_sram ; -wire [0:1] mux_tree_tapbuf_size2_19_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_5_sram ; -wire [0:1] mux_tree_tapbuf_size2_6_sram ; -wire [0:1] mux_tree_tapbuf_size2_7_sram ; -wire [0:1] mux_tree_tapbuf_size2_8_sram ; -wire [0:1] mux_tree_tapbuf_size2_9_sram ; -wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; -wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size4_0_sram ; -wire [0:2] mux_tree_tapbuf_size4_1_sram ; -wire [0:2] mux_tree_tapbuf_size4_2_sram ; -wire [0:2] mux_tree_tapbuf_size4_3_sram ; -wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size5_0_sram ; -wire [0:2] mux_tree_tapbuf_size5_1_sram ; -wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size6_1_sram ; -wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; -supply1 VDD ; -supply0 VSS ; -// - -sb_2__0__mux_tree_tapbuf_size6_0 mux_top_track_0 ( - .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , - top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , - top_right_grid_pin_1_[0] , chanx_left_in[0] } ) , - .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_top_track_0_undriven_sram_inv ) , - .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_120 ) ) ; -sb_2__0__mux_tree_tapbuf_size6 mux_top_track_4 ( - .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , - top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , - top_right_grid_pin_1_[0] , chanx_left_in[18] } ) , - .sram ( mux_tree_tapbuf_size6_1_sram ) , - .sram_inv ( mux_top_track_4_undriven_sram_inv ) , - .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_119 ) ) ; -sb_2__0__mux_tree_tapbuf_size6_mem_0 mem_top_track_0 ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__0__mux_tree_tapbuf_size6_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__0__mux_tree_tapbuf_size5_0 mux_top_track_2 ( - .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , - top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , - chanx_left_in[19] } ) , - .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_top_track_2_undriven_sram_inv ) , - .out ( chany_top_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_120 ) ) ; -sb_2__0__mux_tree_tapbuf_size5 mux_top_track_6 ( - .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , - top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , - chanx_left_in[17] } ) , - .sram ( mux_tree_tapbuf_size5_1_sram ) , - .sram_inv ( mux_top_track_6_undriven_sram_inv ) , - .out ( chany_top_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_121 ) ) ; -sb_2__0__mux_tree_tapbuf_size5_mem_0 mem_top_track_2 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__0__mux_tree_tapbuf_size5_mem mem_top_track_6 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__0__mux_tree_tapbuf_size3 mux_top_track_8 ( - .in ( { top_left_grid_pin_42_[0] , top_right_grid_pin_1_[0] , - chanx_left_in[16] } ) , - .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_top_track_8_undriven_sram_inv ) , - .out ( chany_top_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_121 ) ) ; -sb_2__0__mux_tree_tapbuf_size3_0 mux_top_track_24 ( - .in ( { top_left_grid_pin_42_[0] , top_right_grid_pin_1_[0] , - chanx_left_in[8] } ) , - .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_top_track_24_undriven_sram_inv ) , - .out ( chany_top_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_119 ) ) ; -sb_2__0__mux_tree_tapbuf_size3_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__0__mux_tree_tapbuf_size3_mem_0 mem_top_track_24 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__0__mux_tree_tapbuf_size2_12 mux_top_track_10 ( - .in ( { top_left_grid_pin_43_[0] , chanx_left_in[15] } ) , - .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_top_track_10_undriven_sram_inv ) , - .out ( chany_top_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_119 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_13 mux_top_track_12 ( - .in ( { top_left_grid_pin_44_[0] , chanx_left_in[14] } ) , - .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_top_track_12_undriven_sram_inv ) , - .out ( chany_top_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_120 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_14 mux_top_track_14 ( - .in ( { top_left_grid_pin_45_[0] , chanx_left_in[13] } ) , - .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_top_track_14_undriven_sram_inv ) , - .out ( chany_top_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_120 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_15 mux_top_track_16 ( - .in ( { top_left_grid_pin_46_[0] , chanx_left_in[12] } ) , - .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_top_track_16_undriven_sram_inv ) , - .out ( chany_top_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_120 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_16 mux_top_track_18 ( - .in ( { top_left_grid_pin_47_[0] , chanx_left_in[11] } ) , - .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_top_track_18_undriven_sram_inv ) , - .out ( chany_top_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_121 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_17 mux_top_track_20 ( - .in ( { top_left_grid_pin_48_[0] , chanx_left_in[10] } ) , - .sram ( mux_tree_tapbuf_size2_5_sram ) , - .sram_inv ( mux_top_track_20_undriven_sram_inv ) , - .out ( chany_top_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_119 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_18 mux_top_track_22 ( - .in ( { top_left_grid_pin_49_[0] , chanx_left_in[9] } ) , - .sram ( mux_tree_tapbuf_size2_6_sram ) , - .sram_inv ( mux_top_track_22_undriven_sram_inv ) , - .out ( chany_top_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_119 ) ) ; -sb_2__0__mux_tree_tapbuf_size2 mux_top_track_26 ( - .in ( { top_left_grid_pin_43_[0] , chanx_left_in[7] } ) , - .sram ( mux_tree_tapbuf_size2_7_sram ) , - .sram_inv ( mux_top_track_26_undriven_sram_inv ) , - .out ( chany_top_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_120 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_11 mux_left_track_9 ( - .in ( { chany_top_in[16] , left_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size2_8_sram ) , - .sram_inv ( mux_left_track_9_undriven_sram_inv ) , - .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_122 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_0 mux_left_track_11 ( - .in ( { chany_top_in[15] , left_bottom_grid_pin_3_[0] } ) , - .sram ( mux_tree_tapbuf_size2_9_sram ) , - .sram_inv ( mux_left_track_11_undriven_sram_inv ) , - .out ( chanx_left_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_120 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_1 mux_left_track_13 ( - .in ( { chany_top_in[14] , left_bottom_grid_pin_5_[0] } ) , - .sram ( mux_tree_tapbuf_size2_10_sram ) , - .sram_inv ( mux_left_track_13_undriven_sram_inv ) , - .out ( chanx_left_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_120 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_2 mux_left_track_15 ( - .in ( { chany_top_in[13] , left_bottom_grid_pin_7_[0] } ) , - .sram ( mux_tree_tapbuf_size2_11_sram ) , - .sram_inv ( mux_left_track_15_undriven_sram_inv ) , - .out ( chanx_left_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_119 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_3 mux_left_track_17 ( - .in ( { chany_top_in[12] , left_bottom_grid_pin_9_[0] } ) , - .sram ( mux_tree_tapbuf_size2_12_sram ) , - .sram_inv ( mux_left_track_17_undriven_sram_inv ) , - .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_121 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_4 mux_left_track_19 ( - .in ( { chany_top_in[11] , left_bottom_grid_pin_11_[0] } ) , - .sram ( mux_tree_tapbuf_size2_13_sram ) , - .sram_inv ( mux_left_track_19_undriven_sram_inv ) , - .out ( chanx_left_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_119 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_5 mux_left_track_25 ( - .in ( { chany_top_in[8] , left_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size2_14_sram ) , - .sram_inv ( mux_left_track_25_undriven_sram_inv ) , - .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_120 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_6 mux_left_track_27 ( - .in ( { chany_top_in[7] , left_bottom_grid_pin_3_[0] } ) , - .sram ( mux_tree_tapbuf_size2_15_sram ) , - .sram_inv ( mux_left_track_27_undriven_sram_inv ) , - .out ( chanx_left_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_122 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_7 mux_left_track_29 ( - .in ( { chany_top_in[6] , left_bottom_grid_pin_5_[0] } ) , - .sram ( mux_tree_tapbuf_size2_16_sram ) , - .sram_inv ( mux_left_track_29_undriven_sram_inv ) , - .out ( { ropt_net_126 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_119 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_8 mux_left_track_31 ( - .in ( { chany_top_in[5] , left_bottom_grid_pin_7_[0] } ) , - .sram ( mux_tree_tapbuf_size2_17_sram ) , - .sram_inv ( mux_left_track_31_undriven_sram_inv ) , - .out ( chanx_left_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_122 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_9 mux_left_track_33 ( - .in ( { chany_top_in[4] , left_bottom_grid_pin_9_[0] } ) , - .sram ( mux_tree_tapbuf_size2_18_sram ) , - .sram_inv ( mux_left_track_33_undriven_sram_inv ) , - .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_119 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_10 mux_left_track_35 ( - .in ( { chany_top_in[3] , left_bottom_grid_pin_11_[0] } ) , - .sram ( mux_tree_tapbuf_size2_19_sram ) , - .sram_inv ( mux_left_track_35_undriven_sram_inv ) , - .out ( chanx_left_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_121 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_12 mem_top_track_10 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_13 mem_top_track_12 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_14 mem_top_track_14 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_15 mem_top_track_16 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_16 mem_top_track_18 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_17 mem_top_track_20 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_18 mem_top_track_22 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem mem_top_track_26 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_11 mem_left_track_9 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_8_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_0 mem_left_track_11 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_9_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_1 mem_left_track_13 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_10_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_2 mem_left_track_15 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_11_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_3 mem_left_track_17 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_12_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_4 mem_left_track_19 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_13_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_5 mem_left_track_25 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_14_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_6 mem_left_track_27 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_15_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_7 mem_left_track_29 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_16_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_8 mem_left_track_31 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_17_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_9 mem_left_track_33 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_18_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_10 mem_left_track_35 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , - .ccff_tail ( { ropt_net_130 } ) , - .mem_out ( mux_tree_tapbuf_size2_19_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__0__mux_tree_tapbuf_size4_0 mux_left_track_1 ( - .in ( { chany_top_in[0] , left_bottom_grid_pin_1_[0] , - left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] } ) , - .sram ( mux_tree_tapbuf_size4_0_sram ) , - .sram_inv ( mux_left_track_1_undriven_sram_inv ) , - .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_122 ) ) ; -sb_2__0__mux_tree_tapbuf_size4_1 mux_left_track_3 ( - .in ( { chany_top_in[19] , left_bottom_grid_pin_3_[0] , - left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] } ) , - .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_left_track_3_undriven_sram_inv ) , - .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_122 ) ) ; -sb_2__0__mux_tree_tapbuf_size4_2 mux_left_track_5 ( - .in ( { chany_top_in[18] , left_bottom_grid_pin_1_[0] , - left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] } ) , - .sram ( mux_tree_tapbuf_size4_2_sram ) , - .sram_inv ( mux_left_track_5_undriven_sram_inv ) , - .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_122 ) ) ; -sb_2__0__mux_tree_tapbuf_size4 mux_left_track_7 ( - .in ( { chany_top_in[17] , left_bottom_grid_pin_3_[0] , - left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] } ) , - .sram ( mux_tree_tapbuf_size4_3_sram ) , - .sram_inv ( mux_left_track_7_undriven_sram_inv ) , - .out ( chanx_left_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_122 ) ) ; -sb_2__0__mux_tree_tapbuf_size4_mem_0 mem_left_track_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__0__mux_tree_tapbuf_size4_mem_1 mem_left_track_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__0__mux_tree_tapbuf_size4_mem_2 mem_left_track_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__0__mux_tree_tapbuf_size4_mem mem_left_track_7 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1461 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1462 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1463 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1464 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1465 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1466 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1467 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1468 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1469 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1470 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1471 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1472 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1473 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1474 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1475 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1476 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1477 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1478 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1479 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1480 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1481 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1482 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1483 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1484 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1485 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1486 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1487 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1488 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1489 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1490 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1491 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1492 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1493 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1494 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1495 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1496 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1497 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1498 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_139 ) , - .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_708 ( .A ( ropt_net_126 ) , - .X ( ropt_net_139 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_721 ( .A ( ropt_net_140 ) , - .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_141 ) , - .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__4 ( .A ( chanx_left_in[1] ) , - .X ( ropt_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_119 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_120 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__8 ( .A ( chanx_left_in[5] ) , - .X ( ropt_net_134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__9 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_137 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_723 ( .A ( ropt_net_142 ) , - .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( ropt_net_143 ) , - .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( ropt_net_144 ) , - .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( ropt_net_145 ) , - .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_78 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( ropt_net_146 ) , - .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_728 ( .A ( ropt_net_147 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_86 ( .A ( chanx_left_in[2] ) , - .X ( ropt_net_136 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_87 ( .A ( chanx_left_in[3] ) , - .X ( ropt_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_88 ( .A ( chanx_left_in[4] ) , - .X ( ropt_net_135 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_709 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_710 ( .A ( chany_top_in[9] ) , - .X ( ropt_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_711 ( .A ( chany_top_in[1] ) , - .X ( ropt_net_150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_712 ( .A ( ropt_net_130 ) , - .X ( ropt_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_713 ( .A ( ropt_net_131 ) , - .X ( ropt_net_141 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_714 ( .A ( ropt_net_132 ) , - .X ( ropt_net_142 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_715 ( .A ( ropt_net_133 ) , - .X ( ropt_net_144 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_716 ( .A ( ropt_net_134 ) , - .X ( ropt_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_717 ( .A ( ropt_net_135 ) , - .X ( ropt_net_145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_718 ( .A ( ropt_net_136 ) , - .X ( ropt_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_137 ) , - .X ( ropt_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_148 ) , - .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_730 ( .A ( ropt_net_149 ) , - .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_150 ) , - .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y0 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y0 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x285200y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x303600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x340400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x220800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x239200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x285200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x92000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x101200y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x138000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x174800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x211600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x248400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x358800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x312800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x349600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x386400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x423200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x460000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x496800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x754400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x791200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x828000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x115000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x266800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x303600y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x427800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x188600y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x473800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x510600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x547400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x584200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x657800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x694600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x731400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x768200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x841800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x69000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x105800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x142600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x179400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x216200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x253000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x289800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x326600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x363400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x427800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x446200y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x708400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x782000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x818800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x855600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x892400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x36800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x46000y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x207000y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x349600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x473800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x510600y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x82800y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x165600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x202400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x239200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x248400y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x492200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x547400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x639400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x676200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x713000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x749800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x786600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x823400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x860200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x897000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x101200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x138000y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x184000y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x262200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x299000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x317400y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x391000y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x437000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x473800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x524400y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x754400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x791200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x828000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x36800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x46000y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x124200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x161000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x207000y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x253000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x271400y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x349600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x418600y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x496800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x542800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x561200y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x754400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x791200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x828000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x864800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x901600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x110400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x202400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x239200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x276000y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x395600y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x496800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x533600y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x579600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x588800y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x55200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x138000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x174800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x211600y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x289800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x299000y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x400200y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x515200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x598000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x763600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x837200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x874000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x92000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x220800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x303600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x340400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x377200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x414000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x524400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x575000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x616400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x703800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x722200y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x768200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x841800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x147200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x165600y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x253000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x289800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x432400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x450800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x460000y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x575000y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x644000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x662400y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x119600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x156400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x193200y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x358800y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x547400y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x593400y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x676200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x694600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x786600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x823400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x860200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x36800y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x78200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x87400y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x207000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x243800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x358800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x598000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x616400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x625600y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x703800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x722200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x731400y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x110400y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x151800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x211600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x538200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x556600y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x754400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x105800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x142600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x179400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x197800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x207000y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x363400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x524400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x542800y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x625600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x634800y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x717600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x768200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x841800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x878600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x69000y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x234600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x271400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x395600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x625600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x634800y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x653200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x837200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x147200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x165600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x216200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x409400y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x487600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x570400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x588800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x598000y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x676200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x713000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x749800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x768200y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x124200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x161000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x197800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x248400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x266800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x289800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x299000y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x345000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x381800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x432400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x469200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x506000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x616400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x625600y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x671600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x690000y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x768200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x841800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x110400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x161000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x197800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x216200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x299000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x335800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x391000y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x469200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x519800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x538200y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x584200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x657800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x694600y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x818800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x855600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x892400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x115000y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x193200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x230000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x248400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x257600y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x409400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x593400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x611800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x703800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x754400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x860200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x105800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x142600y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x188600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x207000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x216200y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x303600y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x409400y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x556600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x565800y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x736000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x128800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x174800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x184000y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x266800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x317400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x763600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x823400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x860200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x294400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x354200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x437000y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x625600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x644000y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x690000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x736000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x818800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x855600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x892400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x437000y870400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y870400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x538200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x547400y870400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x625600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x791200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x828000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y870400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y870400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x312800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x322000y897600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x455400y897600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x506000y897600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x611800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x630200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x639400y897600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x800400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x864800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x901600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x386400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x598000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x607200y924800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x639400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x814200y924800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y924800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y924800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y952000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y952000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__0__icv_in_design.pt.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__0__icv_in_design.pt.v deleted file mode 100644 index 7f406ab..0000000 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__0__icv_in_design.pt.v +++ /dev/null @@ -1,1690 +0,0 @@ -// -// -// -// -// -// -module sb_2__0__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__39 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__38 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__37 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__36 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__35 ( .A ( mem_out[1] ) , - .X ( net_net_64 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_64 ( .A ( net_net_64 ) , - .X ( net_net_63 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_92 ( .A ( net_net_63 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__34 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__33 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__32 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__31 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__30 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__29 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__28 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__27 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__26 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__25 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__24 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__23 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_18 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__22 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_17 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__21 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__20 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__19 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__18 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__17 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__16 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_51 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__15 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__14 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__13 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__12 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__11 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__10 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module sb_2__0__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module sb_2__0_ ( prog_clk , chany_top_in , top_left_grid_pin_42_ , - top_left_grid_pin_43_ , top_left_grid_pin_44_ , top_left_grid_pin_45_ , - top_left_grid_pin_46_ , top_left_grid_pin_47_ , top_left_grid_pin_48_ , - top_left_grid_pin_49_ , top_right_grid_pin_1_ , chanx_left_in , - left_bottom_grid_pin_1_ , left_bottom_grid_pin_3_ , - left_bottom_grid_pin_5_ , left_bottom_grid_pin_7_ , - left_bottom_grid_pin_9_ , left_bottom_grid_pin_11_ , ccff_head , - chany_top_out , chanx_left_out , ccff_tail ) ; -input [0:0] prog_clk ; -input [0:19] chany_top_in ; -input [0:0] top_left_grid_pin_42_ ; -input [0:0] top_left_grid_pin_43_ ; -input [0:0] top_left_grid_pin_44_ ; -input [0:0] top_left_grid_pin_45_ ; -input [0:0] top_left_grid_pin_46_ ; -input [0:0] top_left_grid_pin_47_ ; -input [0:0] top_left_grid_pin_48_ ; -input [0:0] top_left_grid_pin_49_ ; -input [0:0] top_right_grid_pin_1_ ; -input [0:19] chanx_left_in ; -input [0:0] left_bottom_grid_pin_1_ ; -input [0:0] left_bottom_grid_pin_3_ ; -input [0:0] left_bottom_grid_pin_5_ ; -input [0:0] left_bottom_grid_pin_7_ ; -input [0:0] left_bottom_grid_pin_9_ ; -input [0:0] left_bottom_grid_pin_11_ ; -input [0:0] ccff_head ; -output [0:19] chany_top_out ; -output [0:19] chanx_left_out ; -output [0:0] ccff_tail ; - -wire [0:1] mux_left_track_11_undriven_sram_inv ; -wire [0:1] mux_left_track_13_undriven_sram_inv ; -wire [0:1] mux_left_track_15_undriven_sram_inv ; -wire [0:1] mux_left_track_17_undriven_sram_inv ; -wire [0:1] mux_left_track_19_undriven_sram_inv ; -wire [0:2] mux_left_track_1_undriven_sram_inv ; -wire [0:1] mux_left_track_25_undriven_sram_inv ; -wire [0:1] mux_left_track_27_undriven_sram_inv ; -wire [0:1] mux_left_track_29_undriven_sram_inv ; -wire [0:1] mux_left_track_31_undriven_sram_inv ; -wire [0:1] mux_left_track_33_undriven_sram_inv ; -wire [0:1] mux_left_track_35_undriven_sram_inv ; -wire [0:2] mux_left_track_3_undriven_sram_inv ; -wire [0:2] mux_left_track_5_undriven_sram_inv ; -wire [0:2] mux_left_track_7_undriven_sram_inv ; -wire [0:1] mux_left_track_9_undriven_sram_inv ; -wire [0:2] mux_top_track_0_undriven_sram_inv ; -wire [0:1] mux_top_track_10_undriven_sram_inv ; -wire [0:1] mux_top_track_12_undriven_sram_inv ; -wire [0:1] mux_top_track_14_undriven_sram_inv ; -wire [0:1] mux_top_track_16_undriven_sram_inv ; -wire [0:1] mux_top_track_18_undriven_sram_inv ; -wire [0:1] mux_top_track_20_undriven_sram_inv ; -wire [0:1] mux_top_track_22_undriven_sram_inv ; -wire [0:1] mux_top_track_24_undriven_sram_inv ; -wire [0:1] mux_top_track_26_undriven_sram_inv ; -wire [0:2] mux_top_track_2_undriven_sram_inv ; -wire [0:2] mux_top_track_4_undriven_sram_inv ; -wire [0:2] mux_top_track_6_undriven_sram_inv ; -wire [0:1] mux_top_track_8_undriven_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_10_sram ; -wire [0:1] mux_tree_tapbuf_size2_11_sram ; -wire [0:1] mux_tree_tapbuf_size2_12_sram ; -wire [0:1] mux_tree_tapbuf_size2_13_sram ; -wire [0:1] mux_tree_tapbuf_size2_14_sram ; -wire [0:1] mux_tree_tapbuf_size2_15_sram ; -wire [0:1] mux_tree_tapbuf_size2_16_sram ; -wire [0:1] mux_tree_tapbuf_size2_17_sram ; -wire [0:1] mux_tree_tapbuf_size2_18_sram ; -wire [0:1] mux_tree_tapbuf_size2_19_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_5_sram ; -wire [0:1] mux_tree_tapbuf_size2_6_sram ; -wire [0:1] mux_tree_tapbuf_size2_7_sram ; -wire [0:1] mux_tree_tapbuf_size2_8_sram ; -wire [0:1] mux_tree_tapbuf_size2_9_sram ; -wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; -wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size4_0_sram ; -wire [0:2] mux_tree_tapbuf_size4_1_sram ; -wire [0:2] mux_tree_tapbuf_size4_2_sram ; -wire [0:2] mux_tree_tapbuf_size4_3_sram ; -wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size5_0_sram ; -wire [0:2] mux_tree_tapbuf_size5_1_sram ; -wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size6_1_sram ; -wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; -// - -sb_2__0__mux_tree_tapbuf_size6_0 mux_top_track_0 ( - .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , - top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , - top_right_grid_pin_1_[0] , chanx_left_in[0] } ) , - .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_top_track_0_undriven_sram_inv ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_120 ) ) ; -sb_2__0__mux_tree_tapbuf_size6 mux_top_track_4 ( - .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , - top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , - top_right_grid_pin_1_[0] , chanx_left_in[18] } ) , - .sram ( mux_tree_tapbuf_size6_1_sram ) , - .sram_inv ( mux_top_track_4_undriven_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_119 ) ) ; -sb_2__0__mux_tree_tapbuf_size6_mem_0 mem_top_track_0 ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size6_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size5_0 mux_top_track_2 ( - .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , - top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , - chanx_left_in[19] } ) , - .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_top_track_2_undriven_sram_inv ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_120 ) ) ; -sb_2__0__mux_tree_tapbuf_size5 mux_top_track_6 ( - .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , - top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , - chanx_left_in[17] } ) , - .sram ( mux_tree_tapbuf_size5_1_sram ) , - .sram_inv ( mux_top_track_6_undriven_sram_inv ) , - .out ( chany_top_out[3] ) , .p0 ( optlc_net_121 ) ) ; -sb_2__0__mux_tree_tapbuf_size5_mem_0 mem_top_track_2 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size5_mem mem_top_track_6 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size3 mux_top_track_8 ( - .in ( { top_left_grid_pin_42_[0] , top_right_grid_pin_1_[0] , - chanx_left_in[16] } ) , - .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_top_track_8_undriven_sram_inv ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_121 ) ) ; -sb_2__0__mux_tree_tapbuf_size3_0 mux_top_track_24 ( - .in ( { top_left_grid_pin_42_[0] , top_right_grid_pin_1_[0] , - chanx_left_in[8] } ) , - .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_top_track_24_undriven_sram_inv ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_119 ) ) ; -sb_2__0__mux_tree_tapbuf_size3_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size3_mem_0 mem_top_track_24 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size2_12 mux_top_track_10 ( - .in ( { top_left_grid_pin_43_[0] , chanx_left_in[15] } ) , - .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_top_track_10_undriven_sram_inv ) , - .out ( chany_top_out[5] ) , .p0 ( optlc_net_119 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_13 mux_top_track_12 ( - .in ( { top_left_grid_pin_44_[0] , chanx_left_in[14] } ) , - .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_top_track_12_undriven_sram_inv ) , - .out ( chany_top_out[6] ) , .p0 ( optlc_net_120 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_14 mux_top_track_14 ( - .in ( { top_left_grid_pin_45_[0] , chanx_left_in[13] } ) , - .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_top_track_14_undriven_sram_inv ) , - .out ( chany_top_out[7] ) , .p0 ( optlc_net_120 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_15 mux_top_track_16 ( - .in ( { top_left_grid_pin_46_[0] , chanx_left_in[12] } ) , - .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_top_track_16_undriven_sram_inv ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_120 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_16 mux_top_track_18 ( - .in ( { top_left_grid_pin_47_[0] , chanx_left_in[11] } ) , - .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_top_track_18_undriven_sram_inv ) , - .out ( chany_top_out[9] ) , .p0 ( optlc_net_121 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_17 mux_top_track_20 ( - .in ( { top_left_grid_pin_48_[0] , chanx_left_in[10] } ) , - .sram ( mux_tree_tapbuf_size2_5_sram ) , - .sram_inv ( mux_top_track_20_undriven_sram_inv ) , - .out ( chany_top_out[10] ) , .p0 ( optlc_net_119 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_18 mux_top_track_22 ( - .in ( { top_left_grid_pin_49_[0] , chanx_left_in[9] } ) , - .sram ( mux_tree_tapbuf_size2_6_sram ) , - .sram_inv ( mux_top_track_22_undriven_sram_inv ) , - .out ( chany_top_out[11] ) , .p0 ( optlc_net_119 ) ) ; -sb_2__0__mux_tree_tapbuf_size2 mux_top_track_26 ( - .in ( { top_left_grid_pin_43_[0] , chanx_left_in[7] } ) , - .sram ( mux_tree_tapbuf_size2_7_sram ) , - .sram_inv ( mux_top_track_26_undriven_sram_inv ) , - .out ( chany_top_out[13] ) , .p0 ( optlc_net_120 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_11 mux_left_track_9 ( - .in ( { chany_top_in[16] , left_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size2_8_sram ) , - .sram_inv ( mux_left_track_9_undriven_sram_inv ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_122 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_0 mux_left_track_11 ( - .in ( { chany_top_in[15] , left_bottom_grid_pin_3_[0] } ) , - .sram ( mux_tree_tapbuf_size2_9_sram ) , - .sram_inv ( mux_left_track_11_undriven_sram_inv ) , - .out ( chanx_left_out[5] ) , .p0 ( optlc_net_120 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_1 mux_left_track_13 ( - .in ( { chany_top_in[14] , left_bottom_grid_pin_5_[0] } ) , - .sram ( mux_tree_tapbuf_size2_10_sram ) , - .sram_inv ( mux_left_track_13_undriven_sram_inv ) , - .out ( chanx_left_out[6] ) , .p0 ( optlc_net_120 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_2 mux_left_track_15 ( - .in ( { chany_top_in[13] , left_bottom_grid_pin_7_[0] } ) , - .sram ( mux_tree_tapbuf_size2_11_sram ) , - .sram_inv ( mux_left_track_15_undriven_sram_inv ) , - .out ( chanx_left_out[7] ) , .p0 ( optlc_net_119 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_3 mux_left_track_17 ( - .in ( { chany_top_in[12] , left_bottom_grid_pin_9_[0] } ) , - .sram ( mux_tree_tapbuf_size2_12_sram ) , - .sram_inv ( mux_left_track_17_undriven_sram_inv ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_121 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_4 mux_left_track_19 ( - .in ( { chany_top_in[11] , left_bottom_grid_pin_11_[0] } ) , - .sram ( mux_tree_tapbuf_size2_13_sram ) , - .sram_inv ( mux_left_track_19_undriven_sram_inv ) , - .out ( chanx_left_out[9] ) , .p0 ( optlc_net_119 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_5 mux_left_track_25 ( - .in ( { chany_top_in[8] , left_bottom_grid_pin_1_[0] } ) , - .sram ( mux_tree_tapbuf_size2_14_sram ) , - .sram_inv ( mux_left_track_25_undriven_sram_inv ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_120 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_6 mux_left_track_27 ( - .in ( { chany_top_in[7] , left_bottom_grid_pin_3_[0] } ) , - .sram ( mux_tree_tapbuf_size2_15_sram ) , - .sram_inv ( mux_left_track_27_undriven_sram_inv ) , - .out ( chanx_left_out[13] ) , .p0 ( optlc_net_122 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_7 mux_left_track_29 ( - .in ( { chany_top_in[6] , left_bottom_grid_pin_5_[0] } ) , - .sram ( mux_tree_tapbuf_size2_16_sram ) , - .sram_inv ( mux_left_track_29_undriven_sram_inv ) , - .out ( { ropt_net_126 } ) , - .p0 ( optlc_net_119 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_8 mux_left_track_31 ( - .in ( { chany_top_in[5] , left_bottom_grid_pin_7_[0] } ) , - .sram ( mux_tree_tapbuf_size2_17_sram ) , - .sram_inv ( mux_left_track_31_undriven_sram_inv ) , - .out ( chanx_left_out[15] ) , .p0 ( optlc_net_122 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_9 mux_left_track_33 ( - .in ( { chany_top_in[4] , left_bottom_grid_pin_9_[0] } ) , - .sram ( mux_tree_tapbuf_size2_18_sram ) , - .sram_inv ( mux_left_track_33_undriven_sram_inv ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_119 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_10 mux_left_track_35 ( - .in ( { chany_top_in[3] , left_bottom_grid_pin_11_[0] } ) , - .sram ( mux_tree_tapbuf_size2_19_sram ) , - .sram_inv ( mux_left_track_35_undriven_sram_inv ) , - .out ( chanx_left_out[17] ) , .p0 ( optlc_net_121 ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_12 mem_top_track_10 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_13 mem_top_track_12 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_14 mem_top_track_14 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_15 mem_top_track_16 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_16 mem_top_track_18 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_17 mem_top_track_20 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_18 mem_top_track_22 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem mem_top_track_26 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_11 mem_left_track_9 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_0 mem_left_track_11 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_1 mem_left_track_13 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_2 mem_left_track_15 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_11_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_3 mem_left_track_17 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_12_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_4 mem_left_track_19 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_13_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_5 mem_left_track_25 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_14_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_6 mem_left_track_27 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_15_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_7 mem_left_track_29 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_16_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_8 mem_left_track_31 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_17_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_9 mem_left_track_33 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_18_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size2_mem_10 mem_left_track_35 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , - .ccff_tail ( { ropt_net_130 } ) , - .mem_out ( mux_tree_tapbuf_size2_19_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size4_0 mux_left_track_1 ( - .in ( { chany_top_in[0] , left_bottom_grid_pin_1_[0] , - left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] } ) , - .sram ( mux_tree_tapbuf_size4_0_sram ) , - .sram_inv ( mux_left_track_1_undriven_sram_inv ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_122 ) ) ; -sb_2__0__mux_tree_tapbuf_size4_1 mux_left_track_3 ( - .in ( { chany_top_in[19] , left_bottom_grid_pin_3_[0] , - left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] } ) , - .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_left_track_3_undriven_sram_inv ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_122 ) ) ; -sb_2__0__mux_tree_tapbuf_size4_2 mux_left_track_5 ( - .in ( { chany_top_in[18] , left_bottom_grid_pin_1_[0] , - left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] } ) , - .sram ( mux_tree_tapbuf_size4_2_sram ) , - .sram_inv ( mux_left_track_5_undriven_sram_inv ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_122 ) ) ; -sb_2__0__mux_tree_tapbuf_size4 mux_left_track_7 ( - .in ( { chany_top_in[17] , left_bottom_grid_pin_3_[0] , - left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] } ) , - .sram ( mux_tree_tapbuf_size4_3_sram ) , - .sram_inv ( mux_left_track_7_undriven_sram_inv ) , - .out ( chanx_left_out[3] ) , .p0 ( optlc_net_122 ) ) ; -sb_2__0__mux_tree_tapbuf_size4_mem_0 mem_left_track_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size4_mem_1 mem_left_track_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size4_mem_2 mem_left_track_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ; -sb_2__0__mux_tree_tapbuf_size4_mem mem_left_track_7 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_139 ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_708 ( .A ( ropt_net_126 ) , - .X ( ropt_net_139 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_721 ( .A ( ropt_net_140 ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_141 ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__4 ( .A ( chanx_left_in[1] ) , - .X ( ropt_net_133 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_119 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_120 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_121 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__8 ( .A ( chanx_left_in[5] ) , - .X ( ropt_net_134 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__9 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_137 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_723 ( .A ( ropt_net_142 ) , - .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_122 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( ropt_net_143 ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( ropt_net_144 ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( ropt_net_145 ) , - .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_78 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_132 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( ropt_net_146 ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_728 ( .A ( ropt_net_147 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_86 ( .A ( chanx_left_in[2] ) , - .X ( ropt_net_136 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_87 ( .A ( chanx_left_in[3] ) , - .X ( ropt_net_131 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_88 ( .A ( chanx_left_in[4] ) , - .X ( ropt_net_135 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_709 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_148 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_710 ( .A ( chany_top_in[9] ) , - .X ( ropt_net_149 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_711 ( .A ( chany_top_in[1] ) , - .X ( ropt_net_150 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_712 ( .A ( ropt_net_130 ) , - .X ( ropt_net_147 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_713 ( .A ( ropt_net_131 ) , - .X ( ropt_net_141 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_714 ( .A ( ropt_net_132 ) , - .X ( ropt_net_142 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_715 ( .A ( ropt_net_133 ) , - .X ( ropt_net_144 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_716 ( .A ( ropt_net_134 ) , - .X ( ropt_net_140 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_717 ( .A ( ropt_net_135 ) , - .X ( ropt_net_145 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_718 ( .A ( ropt_net_136 ) , - .X ( ropt_net_146 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_137 ) , - .X ( ropt_net_143 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_148 ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_730 ( .A ( ropt_net_149 ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_150 ) , - .X ( chanx_left_out[19] ) ) ; -endmodule - - diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__1__icv_in_design.fm.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__1__icv_in_design.fm.v deleted file mode 100644 index d9e0f8e..0000000 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__1__icv_in_design.fm.v +++ /dev/null @@ -1,2690 +0,0 @@ -// -// -// -// -// -// -module sb_2__1__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__60 ( .A ( mem_out[1] ) , - .X ( net_net_79 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_78 ( .A ( net_net_79 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__59 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__58 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__57 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__56 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__55 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__const1 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__1__const1 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__1__const1_31 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__1__const1_31 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__1__const1_30 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__1__const1_30 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__1__const1_29 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__1__const1_29 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__1__const1_28 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__1__const1_28 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__1__const1_27 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__1__const1_27 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__54 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__53 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__52 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__51 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__50 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__const1_26 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sb_2__1__const1_26 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_2__1__const1_25 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sb_2__1__const1_25 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_2__1__const1_24 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sb_2__1__const1_24 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_2__1__const1_23 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sb_2__1__const1_23 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_2__1__const1_22 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sb_2__1__const1_22 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_67 ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__49 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__48 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__47 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__46 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__const1_21 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sb_2__1__const1_21 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -endmodule - - -module sb_2__1__const1_20 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sb_2__1__const1_20 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_65 ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( BUF_net_65 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_107 ( .A ( BUF_net_65 ) , - .X ( out[0] ) ) ; -endmodule - - -module sb_2__1__const1_19 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sb_2__1__const1_19 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -endmodule - - -module sb_2__1__const1_18 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sb_2__1__const1_18 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size9_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__45 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__const1_17 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , p0 ) ; -input [0:8] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; - -sb_2__1__const1_17 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_106 ( - .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__44 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__43 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__42 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__const1_16 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sb_2__1__const1_16 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module sb_2__1__const1_15 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sb_2__1__const1_15 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module sb_2__1__const1_14 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sb_2__1__const1_14 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__41 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__40 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__39 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__38 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__37 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__36 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__35 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__const1_13 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sb_2__1__const1_13 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_2__1__const1_12 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sb_2__1__const1_12 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_2__1__const1_11 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sb_2__1__const1_11 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_2__1__const1_10 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sb_2__1__const1_10 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_2__1__const1_9 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sb_2__1__const1_9 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_2__1__const1_8 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sb_2__1__const1_8 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_2__1__const1_7 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sb_2__1__const1_7 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size14_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__34 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size14_mem ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__33 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__const1_6 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size14_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:13] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sb_2__1__const1_6 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; -endmodule - - -module sb_2__1__const1_5 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size14 ( in , sram , sram_inv , out , p0 ) ; -input [0:13] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sb_2__1__const1_5 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__32 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__31 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__30 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__const1_4 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sb_2__1__const1_4 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module sb_2__1__const1_3 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sb_2__1__const1_3 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module sb_2__1__const1_2 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sb_2__1__const1_2 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__29 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__28 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__const1_1 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sb_2__1__const1_1 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module sb_2__1__const1_0 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sb_2__1__const1_0 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module sb_2__1_ ( prog_clk , chany_top_in , top_left_grid_pin_42_ , - top_left_grid_pin_43_ , top_left_grid_pin_44_ , top_left_grid_pin_45_ , - top_left_grid_pin_46_ , top_left_grid_pin_47_ , top_left_grid_pin_48_ , - top_left_grid_pin_49_ , top_right_grid_pin_1_ , chany_bottom_in , - bottom_right_grid_pin_1_ , bottom_left_grid_pin_42_ , - bottom_left_grid_pin_43_ , bottom_left_grid_pin_44_ , - bottom_left_grid_pin_45_ , bottom_left_grid_pin_46_ , - bottom_left_grid_pin_47_ , bottom_left_grid_pin_48_ , - bottom_left_grid_pin_49_ , chanx_left_in , left_bottom_grid_pin_34_ , - left_bottom_grid_pin_35_ , left_bottom_grid_pin_36_ , - left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , - left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , - left_bottom_grid_pin_41_ , ccff_head , chany_top_out , chany_bottom_out , - chanx_left_out , ccff_tail , Test_en__FEEDTHRU_0 , Test_en__FEEDTHRU_1 , - clk__FEEDTHRU_0 , clk__FEEDTHRU_1 ) ; -input [0:0] prog_clk ; -input [0:19] chany_top_in ; -input [0:0] top_left_grid_pin_42_ ; -input [0:0] top_left_grid_pin_43_ ; -input [0:0] top_left_grid_pin_44_ ; -input [0:0] top_left_grid_pin_45_ ; -input [0:0] top_left_grid_pin_46_ ; -input [0:0] top_left_grid_pin_47_ ; -input [0:0] top_left_grid_pin_48_ ; -input [0:0] top_left_grid_pin_49_ ; -input [0:0] top_right_grid_pin_1_ ; -input [0:19] chany_bottom_in ; -input [0:0] bottom_right_grid_pin_1_ ; -input [0:0] bottom_left_grid_pin_42_ ; -input [0:0] bottom_left_grid_pin_43_ ; -input [0:0] bottom_left_grid_pin_44_ ; -input [0:0] bottom_left_grid_pin_45_ ; -input [0:0] bottom_left_grid_pin_46_ ; -input [0:0] bottom_left_grid_pin_47_ ; -input [0:0] bottom_left_grid_pin_48_ ; -input [0:0] bottom_left_grid_pin_49_ ; -input [0:19] chanx_left_in ; -input [0:0] left_bottom_grid_pin_34_ ; -input [0:0] left_bottom_grid_pin_35_ ; -input [0:0] left_bottom_grid_pin_36_ ; -input [0:0] left_bottom_grid_pin_37_ ; -input [0:0] left_bottom_grid_pin_38_ ; -input [0:0] left_bottom_grid_pin_39_ ; -input [0:0] left_bottom_grid_pin_40_ ; -input [0:0] left_bottom_grid_pin_41_ ; -input [0:0] ccff_head ; -output [0:19] chany_top_out ; -output [0:19] chany_bottom_out ; -output [0:19] chanx_left_out ; -output [0:0] ccff_tail ; -input [0:0] Test_en__FEEDTHRU_0 ; -output [0:0] Test_en__FEEDTHRU_1 ; -input [0:0] clk__FEEDTHRU_0 ; -output [0:0] clk__FEEDTHRU_1 ; - -wire [0:2] mux_bottom_track_17_undriven_sram_inv ; -wire [0:3] mux_bottom_track_1_undriven_sram_inv ; -wire [0:2] mux_bottom_track_25_undriven_sram_inv ; -wire [0:2] mux_bottom_track_33_undriven_sram_inv ; -wire [0:3] mux_bottom_track_3_undriven_sram_inv ; -wire [0:3] mux_bottom_track_5_undriven_sram_inv ; -wire [0:3] mux_bottom_track_9_undriven_sram_inv ; -wire [0:2] mux_left_track_11_undriven_sram_inv ; -wire [0:2] mux_left_track_13_undriven_sram_inv ; -wire [0:2] mux_left_track_15_undriven_sram_inv ; -wire [0:1] mux_left_track_17_undriven_sram_inv ; -wire [0:1] mux_left_track_19_undriven_sram_inv ; -wire [0:2] mux_left_track_1_undriven_sram_inv ; -wire [0:1] mux_left_track_21_undriven_sram_inv ; -wire [0:1] mux_left_track_23_undriven_sram_inv ; -wire [0:1] mux_left_track_25_undriven_sram_inv ; -wire [0:1] mux_left_track_29_undriven_sram_inv ; -wire [0:1] mux_left_track_31_undriven_sram_inv ; -wire [0:1] mux_left_track_33_undriven_sram_inv ; -wire [0:1] mux_left_track_35_undriven_sram_inv ; -wire [0:1] mux_left_track_37_undriven_sram_inv ; -wire [0:1] mux_left_track_39_undriven_sram_inv ; -wire [0:2] mux_left_track_3_undriven_sram_inv ; -wire [0:2] mux_left_track_5_undriven_sram_inv ; -wire [0:2] mux_left_track_7_undriven_sram_inv ; -wire [0:2] mux_left_track_9_undriven_sram_inv ; -wire [0:3] mux_top_track_0_undriven_sram_inv ; -wire [0:2] mux_top_track_16_undriven_sram_inv ; -wire [0:2] mux_top_track_24_undriven_sram_inv ; -wire [0:3] mux_top_track_2_undriven_sram_inv ; -wire [0:2] mux_top_track_32_undriven_sram_inv ; -wire [0:3] mux_top_track_4_undriven_sram_inv ; -wire [0:3] mux_top_track_8_undriven_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size14_0_sram ; -wire [0:3] mux_tree_tapbuf_size14_1_sram ; -wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail ; -wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_5_sram ; -wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; -wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:1] mux_tree_tapbuf_size3_2_sram ; -wire [0:1] mux_tree_tapbuf_size3_3_sram ; -wire [0:1] mux_tree_tapbuf_size3_4_sram ; -wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size4_0_sram ; -wire [0:2] mux_tree_tapbuf_size4_1_sram ; -wire [0:2] mux_tree_tapbuf_size4_2_sram ; -wire [0:2] mux_tree_tapbuf_size4_3_sram ; -wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size6_1_sram ; -wire [0:2] mux_tree_tapbuf_size6_2_sram ; -wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size7_0_sram ; -wire [0:2] mux_tree_tapbuf_size7_1_sram ; -wire [0:2] mux_tree_tapbuf_size7_2_sram ; -wire [0:2] mux_tree_tapbuf_size7_3_sram ; -wire [0:2] mux_tree_tapbuf_size7_4_sram ; -wire [0:2] mux_tree_tapbuf_size7_5_sram ; -wire [0:2] mux_tree_tapbuf_size7_6_sram ; -wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:3] mux_tree_tapbuf_size8_2_sram ; -wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size9_0_sram ; -wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ; -// - -assign clk__FEEDTHRU_1[0] = clk__FEEDTHRU_0[0] ; - -sb_2__1__mux_tree_tapbuf_size10 mux_top_track_0 ( - .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , - top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , - top_right_grid_pin_1_[0] , chany_bottom_in[2] , chany_bottom_in[12] , - chanx_left_in[0] , chanx_left_in[7] , chanx_left_in[14] } ) , - .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_top_track_0_undriven_sram_inv ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_126 ) ) ; -sb_2__1__mux_tree_tapbuf_size10_0 mux_bottom_track_1 ( - .in ( { chany_top_in[2] , chany_top_in[12] , bottom_right_grid_pin_1_[0] , - bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , - bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , - chanx_left_in[1] , chanx_left_in[8] , chanx_left_in[15] } ) , - .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_bottom_track_1_undriven_sram_inv ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_126 ) ) ; -sb_2__1__mux_tree_tapbuf_size10_mem mem_top_track_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size10_mem_0 mem_bottom_track_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size8_1 mux_top_track_2 ( - .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , - top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , - chany_bottom_in[4] , chany_bottom_in[13] , chanx_left_in[6] , - chanx_left_in[13] } ) , - .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_top_track_2_undriven_sram_inv ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_127 ) ) ; -sb_2__1__mux_tree_tapbuf_size8 mux_top_track_8 ( - .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_46_[0] , - top_right_grid_pin_1_[0] , chany_bottom_in[6] , chany_bottom_in[16] , - chanx_left_in[4] , chanx_left_in[11] , chanx_left_in[18] } ) , - .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_top_track_8_undriven_sram_inv ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_127 ) ) ; -sb_2__1__mux_tree_tapbuf_size8_0 mux_bottom_track_9 ( - .in ( { chany_top_in[6] , chany_top_in[16] , bottom_right_grid_pin_1_[0] , - bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_49_[0] , - chanx_left_in[4] , chanx_left_in[11] , chanx_left_in[18] } ) , - .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_bottom_track_9_undriven_sram_inv ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_125 ) ) ; -sb_2__1__mux_tree_tapbuf_size8_mem_1 mem_top_track_2 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size8_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size8_mem_0 mem_bottom_track_9 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size14 mux_top_track_4 ( - .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_43_[0] , - top_left_grid_pin_44_[0] , top_left_grid_pin_45_[0] , - top_left_grid_pin_46_[0] , top_left_grid_pin_47_[0] , - top_left_grid_pin_48_[0] , top_left_grid_pin_49_[0] , - top_right_grid_pin_1_[0] , chany_bottom_in[5] , chany_bottom_in[14] , - chanx_left_in[5] , chanx_left_in[12] , chanx_left_in[19] } ) , - .sram ( mux_tree_tapbuf_size14_0_sram ) , - .sram_inv ( mux_top_track_4_undriven_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_127 ) ) ; -sb_2__1__mux_tree_tapbuf_size14_0 mux_bottom_track_5 ( - .in ( { chany_top_in[5] , chany_top_in[14] , bottom_right_grid_pin_1_[0] , - bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_43_[0] , - bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_45_[0] , - bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_47_[0] , - bottom_left_grid_pin_48_[0] , bottom_left_grid_pin_49_[0] , - chanx_left_in[3] , chanx_left_in[10] , chanx_left_in[17] } ) , - .sram ( mux_tree_tapbuf_size14_1_sram ) , - .sram_inv ( mux_bottom_track_5_undriven_sram_inv ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_125 ) ) ; -sb_2__1__mux_tree_tapbuf_size14_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size14_0_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size14_mem_0 mem_bottom_track_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size14_1_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size7_5 mux_top_track_16 ( - .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_47_[0] , - chany_bottom_in[8] , chany_bottom_in[17] , chanx_left_in[3] , - chanx_left_in[10] , chanx_left_in[17] } ) , - .sram ( mux_tree_tapbuf_size7_0_sram ) , - .sram_inv ( mux_top_track_16_undriven_sram_inv ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_126 ) ) ; -sb_2__1__mux_tree_tapbuf_size7 mux_top_track_24 ( - .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_48_[0] , - chany_bottom_in[9] , chany_bottom_in[18] , chanx_left_in[2] , - chanx_left_in[9] , chanx_left_in[16] } ) , - .sram ( mux_tree_tapbuf_size7_1_sram ) , - .sram_inv ( mux_top_track_24_undriven_sram_inv ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_126 ) ) ; -sb_2__1__mux_tree_tapbuf_size7_0 mux_bottom_track_17 ( - .in ( { chany_top_in[8] , chany_top_in[17] , bottom_left_grid_pin_42_[0] , - bottom_left_grid_pin_46_[0] , chanx_left_in[5] , chanx_left_in[12] , - chanx_left_in[19] } ) , - .sram ( mux_tree_tapbuf_size7_2_sram ) , - .sram_inv ( mux_bottom_track_17_undriven_sram_inv ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_126 ) ) ; -sb_2__1__mux_tree_tapbuf_size7_1 mux_left_track_1 ( - .in ( { chany_top_in[0] , chany_top_in[2] , chany_bottom_in[2] , - left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , - left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , - .sram ( mux_tree_tapbuf_size7_3_sram ) , - .sram_inv ( mux_left_track_1_undriven_sram_inv ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_128 ) ) ; -sb_2__1__mux_tree_tapbuf_size7_2 mux_left_track_3 ( - .in ( { chany_top_in[4] , chany_bottom_in[0] , chany_bottom_in[4] , - left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , - left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , - .sram ( mux_tree_tapbuf_size7_4_sram ) , - .sram_inv ( mux_left_track_3_undriven_sram_inv ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_128 ) ) ; -sb_2__1__mux_tree_tapbuf_size7_3 mux_left_track_5 ( - .in ( { chany_top_in[5] , chany_bottom_in[1] , chany_bottom_in[5] , - left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , - left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , - .sram ( mux_tree_tapbuf_size7_5_sram ) , - .sram_inv ( mux_left_track_5_undriven_sram_inv ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_128 ) ) ; -sb_2__1__mux_tree_tapbuf_size7_4 mux_left_track_7 ( - .in ( { chany_top_in[6] , chany_bottom_in[3] , chany_bottom_in[6] , - left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , - left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , - .sram ( mux_tree_tapbuf_size7_6_sram ) , - .sram_inv ( mux_left_track_7_undriven_sram_inv ) , - .out ( chanx_left_out[3] ) , .p0 ( optlc_net_128 ) ) ; -sb_2__1__mux_tree_tapbuf_size7_mem_5 mem_top_track_16 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size7_mem mem_top_track_24 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size7_mem_0 mem_bottom_track_17 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size7_mem_1 mem_left_track_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_3_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size7_mem_2 mem_left_track_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_4_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size7_mem_3 mem_left_track_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_5_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size7_mem_4 mem_left_track_7 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_6_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size6 mux_top_track_32 ( - .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_49_[0] , - chany_bottom_in[10] , chanx_left_in[1] , chanx_left_in[8] , - chanx_left_in[15] } ) , - .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_top_track_32_undriven_sram_inv ) , - .out ( chany_top_out[16] ) , .p0 ( optlc_net_126 ) ) ; -sb_2__1__mux_tree_tapbuf_size6_0 mux_bottom_track_25 ( - .in ( { chany_top_in[9] , chany_top_in[18] , bottom_left_grid_pin_43_[0] , - bottom_left_grid_pin_47_[0] , chanx_left_in[6] , chanx_left_in[13] } ) , - .sram ( mux_tree_tapbuf_size6_1_sram ) , - .sram_inv ( mux_bottom_track_25_undriven_sram_inv ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_125 ) ) ; -sb_2__1__mux_tree_tapbuf_size6_1 mux_bottom_track_33 ( - .in ( { chany_top_in[10] , bottom_left_grid_pin_44_[0] , - bottom_left_grid_pin_48_[0] , chanx_left_in[0] , chanx_left_in[7] , - chanx_left_in[14] } ) , - .sram ( mux_tree_tapbuf_size6_2_sram ) , - .sram_inv ( mux_bottom_track_33_undriven_sram_inv ) , - .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_126 ) ) ; -sb_2__1__mux_tree_tapbuf_size6_mem mem_top_track_32 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_25 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size6_mem_1 mem_bottom_track_33 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_2_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size9 mux_bottom_track_3 ( - .in ( { chany_top_in[4] , chany_top_in[13] , bottom_left_grid_pin_42_[0] , - bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , - bottom_left_grid_pin_48_[0] , chanx_left_in[2] , chanx_left_in[9] , - chanx_left_in[16] } ) , - .sram ( mux_tree_tapbuf_size9_0_sram ) , - .sram_inv ( mux_bottom_track_3_undriven_sram_inv ) , - .out ( { ropt_net_132 } ) , - .p0 ( optlc_net_125 ) ) ; -sb_2__1__mux_tree_tapbuf_size9_mem mem_bottom_track_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size9_0_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size4 mux_left_track_9 ( - .in ( { chany_top_in[8] , chany_bottom_in[7] , chany_bottom_in[8] , - left_bottom_grid_pin_34_[0] } ) , - .sram ( mux_tree_tapbuf_size4_0_sram ) , - .sram_inv ( mux_left_track_9_undriven_sram_inv ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_128 ) ) ; -sb_2__1__mux_tree_tapbuf_size4_0 mux_left_track_11 ( - .in ( { chany_top_in[9] , chany_bottom_in[9] , chany_bottom_in[11] , - left_bottom_grid_pin_35_[0] } ) , - .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_left_track_11_undriven_sram_inv ) , - .out ( chanx_left_out[5] ) , .p0 ( optlc_net_128 ) ) ; -sb_2__1__mux_tree_tapbuf_size4_1 mux_left_track_13 ( - .in ( { chany_top_in[10] , chany_bottom_in[10] , chany_bottom_in[15] , - left_bottom_grid_pin_36_[0] } ) , - .sram ( mux_tree_tapbuf_size4_2_sram ) , - .sram_inv ( mux_left_track_13_undriven_sram_inv ) , - .out ( { ropt_net_130 } ) , - .p0 ( optlc_net_125 ) ) ; -sb_2__1__mux_tree_tapbuf_size4_2 mux_left_track_15 ( - .in ( { chany_top_in[12] , chany_bottom_in[12] , chany_bottom_in[19] , - left_bottom_grid_pin_37_[0] } ) , - .sram ( mux_tree_tapbuf_size4_3_sram ) , - .sram_inv ( mux_left_track_15_undriven_sram_inv ) , - .out ( chanx_left_out[7] ) , .p0 ( optlc_net_125 ) ) ; -sb_2__1__mux_tree_tapbuf_size4_mem mem_left_track_9 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size4_mem_0 mem_left_track_11 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size4_mem_1 mem_left_track_13 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size4_mem_2 mem_left_track_15 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size3_0 mux_left_track_17 ( - .in ( { chany_top_in[13] , chany_bottom_in[13] , - left_bottom_grid_pin_38_[0] } ) , - .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_left_track_17_undriven_sram_inv ) , - .out ( { ropt_net_131 } ) , - .p0 ( optlc_net_125 ) ) ; -sb_2__1__mux_tree_tapbuf_size3_1 mux_left_track_19 ( - .in ( { chany_top_in[14] , chany_bottom_in[14] , - left_bottom_grid_pin_39_[0] } ) , - .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_left_track_19_undriven_sram_inv ) , - .out ( chanx_left_out[9] ) , .p0 ( optlc_net_127 ) ) ; -sb_2__1__mux_tree_tapbuf_size3_2 mux_left_track_21 ( - .in ( { chany_top_in[16] , chany_bottom_in[16] , - left_bottom_grid_pin_40_[0] } ) , - .sram ( mux_tree_tapbuf_size3_2_sram ) , - .sram_inv ( mux_left_track_21_undriven_sram_inv ) , - .out ( chanx_left_out[10] ) , .p0 ( optlc_net_128 ) ) ; -sb_2__1__mux_tree_tapbuf_size3_3 mux_left_track_23 ( - .in ( { chany_top_in[17] , chany_bottom_in[17] , - left_bottom_grid_pin_41_[0] } ) , - .sram ( mux_tree_tapbuf_size3_3_sram ) , - .sram_inv ( mux_left_track_23_undriven_sram_inv ) , - .out ( chanx_left_out[11] ) , .p0 ( optlc_net_127 ) ) ; -sb_2__1__mux_tree_tapbuf_size3 mux_left_track_25 ( - .in ( { chany_top_in[18] , chany_bottom_in[18] , - left_bottom_grid_pin_34_[0] } ) , - .sram ( mux_tree_tapbuf_size3_4_sram ) , - .sram_inv ( mux_left_track_25_undriven_sram_inv ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_128 ) ) ; -sb_2__1__mux_tree_tapbuf_size3_mem_0 mem_left_track_17 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size3_mem_1 mem_left_track_19 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size3_mem_2 mem_left_track_21 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size3_mem_3 mem_left_track_23 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size3_mem mem_left_track_25 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_4_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size2_0 mux_left_track_29 ( - .in ( { chany_top_in[19] , left_bottom_grid_pin_36_[0] } ) , - .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_left_track_29_undriven_sram_inv ) , - .out ( chanx_left_out[14] ) , .p0 ( optlc_net_128 ) ) ; -sb_2__1__mux_tree_tapbuf_size2_1 mux_left_track_31 ( - .in ( { chany_top_in[15] , left_bottom_grid_pin_37_[0] } ) , - .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_left_track_31_undriven_sram_inv ) , - .out ( chanx_left_out[15] ) , .p0 ( optlc_net_127 ) ) ; -sb_2__1__mux_tree_tapbuf_size2_2 mux_left_track_33 ( - .in ( { chany_top_in[11] , left_bottom_grid_pin_38_[0] } ) , - .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_left_track_33_undriven_sram_inv ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_127 ) ) ; -sb_2__1__mux_tree_tapbuf_size2_3 mux_left_track_35 ( - .in ( { chany_top_in[7] , left_bottom_grid_pin_39_[0] } ) , - .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_left_track_35_undriven_sram_inv ) , - .out ( chanx_left_out[17] ) , .p0 ( optlc_net_127 ) ) ; -sb_2__1__mux_tree_tapbuf_size2_4 mux_left_track_37 ( - .in ( { chany_top_in[3] , left_bottom_grid_pin_40_[0] } ) , - .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_left_track_37_undriven_sram_inv ) , - .out ( chanx_left_out[18] ) , .p0 ( optlc_net_127 ) ) ; -sb_2__1__mux_tree_tapbuf_size2 mux_left_track_39 ( - .in ( { chany_top_in[1] , left_bottom_grid_pin_41_[0] } ) , - .sram ( mux_tree_tapbuf_size2_5_sram ) , - .sram_inv ( mux_left_track_39_undriven_sram_inv ) , - .out ( chanx_left_out[19] ) , .p0 ( optlc_net_127 ) ) ; -sb_2__1__mux_tree_tapbuf_size2_mem_0 mem_left_track_29 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size2_mem_1 mem_left_track_31 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size2_mem_2 mem_left_track_33 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size2_mem_3 mem_left_track_35 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size2_mem_4 mem_left_track_37 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size2_mem mem_left_track_39 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .ccff_tail ( { ropt_net_134 } ) , - .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; -sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_125 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_126 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_154 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__3 ( .A ( chany_top_in[6] ) , - .X ( ropt_net_145 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_120 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_127 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chany_top_in[9] ) , - .X ( ropt_net_156 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__6 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_153 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__7 ( .A ( chany_top_in[12] ) , - .X ( ropt_net_151 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_122 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_128 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chany_top_in[14] ) , - .X ( ropt_net_150 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chany_top_in[16] ) , - .X ( ropt_net_149 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( chany_top_in[17] ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__12 ( .A ( chany_top_in[18] ) , - .X ( ropt_net_148 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chany_bottom_in[2] ) , - .X ( ropt_net_146 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__14 ( .A ( chany_bottom_in[4] ) , - .X ( ropt_net_142 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__15 ( .A ( chany_bottom_in[5] ) , - .X ( ropt_net_144 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__16 ( .A ( chany_bottom_in[6] ) , - .X ( aps_rename_1_ ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_130 ) , - .X ( ropt_net_168 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( ropt_net_131 ) , - .X ( chanx_left_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_132 ) , - .X ( ropt_net_169 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__20 ( .A ( chany_bottom_in[12] ) , - .X ( ropt_net_158 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_161 ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_23__22 ( .A ( chany_bottom_in[14] ) , - .X ( ropt_net_139 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_162 ) , - .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_25__24 ( .A ( chany_bottom_in[17] ) , - .X ( ropt_net_143 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_26__25 ( .A ( chany_bottom_in[18] ) , - .X ( ropt_net_155 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_163 ) , - .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_133 ) , - .X ( ropt_net_173 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_759 ( .A ( ropt_net_164 ) , - .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_165 ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_166 ) , - .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( ropt_net_134 ) , - .X ( ropt_net_180 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( - .A ( chany_bottom_in[16] ) , .X ( ropt_net_182 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( - .A ( chany_bottom_in[13] ) , .X ( ropt_net_181 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( chany_top_in[13] ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_167 ) , - .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_763 ( .A ( ropt_net_168 ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_77 ( - .A ( left_bottom_grid_pin_35_[0] ) , .X ( ropt_net_133 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_81 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_157 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( chany_top_in[8] ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_766 ( .A ( ropt_net_169 ) , - .X ( chany_bottom_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_139 ) , - .X ( ropt_net_161 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_140 ) , - .X ( ropt_net_164 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( chany_bottom_in[8] ) , - .X ( ropt_net_166 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( ropt_net_170 ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_98 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_183 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_99 ( .A ( chany_top_in[4] ) , - .X ( ropt_net_140 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_100 ( .A ( Test_en__FEEDTHRU_0[0] ) , - .X ( ropt_net_152 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( ropt_net_142 ) , - .X ( ropt_net_167 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_103 ( .A ( aps_rename_1_ ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_769 ( .A ( ropt_net_171 ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_143 ) , - .X ( ropt_net_177 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_144 ) , - .X ( ropt_net_176 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_145 ) , - .X ( ropt_net_163 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_742 ( .A ( ropt_net_146 ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_172 ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_113 ( .A ( chany_bottom_in[10] ) , - .X ( ropt_net_147 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_147 ) , - .X ( ropt_net_162 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_148 ) , - .X ( ropt_net_174 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_149 ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_150 ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( ropt_net_151 ) , - .X ( ropt_net_171 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_152 ) , - .X ( ropt_net_178 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( .A ( ropt_net_153 ) , - .X ( ropt_net_179 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_154 ) , - .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_155 ) , - .X ( ropt_net_175 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_156 ) , - .X ( ropt_net_165 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_157 ) , - .X ( ropt_net_170 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_158 ) , - .X ( ropt_net_172 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_771 ( .A ( ropt_net_173 ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_772 ( .A ( ropt_net_174 ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_773 ( .A ( ropt_net_175 ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_774 ( .A ( ropt_net_176 ) , - .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( ropt_net_177 ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( ropt_net_178 ) , - .X ( Test_en__FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( ropt_net_179 ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_180 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_181 ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_182 ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_183 ) , - .X ( chany_bottom_out[3] ) ) ; -endmodule - - diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__1__icv_in_design.lvs.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__1__icv_in_design.lvs.v deleted file mode 100644 index 8dda202..0000000 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__1__icv_in_design.lvs.v +++ /dev/null @@ -1,4601 +0,0 @@ -// -// -// -// -// -// -module sb_2__1__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__60 ( .A ( mem_out[1] ) , - .X ( net_net_79 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_78 ( .A ( net_net_79 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__59 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__58 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__57 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__56 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__55 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__54 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__53 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__52 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__51 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__50 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_67 ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__49 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__48 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__47 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__46 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_65 ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( BUF_net_65 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_107 ( .A ( BUF_net_65 ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size9_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__45 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:8] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_106 ( - .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__44 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__43 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__42 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__41 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__40 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__39 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__38 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__37 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__36 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__35 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size14_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__34 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size14_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__33 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size14_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:13] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size14 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:13] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__32 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__31 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__30 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__29 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__28 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__1_ ( prog_clk , chany_top_in , top_left_grid_pin_42_ , - top_left_grid_pin_43_ , top_left_grid_pin_44_ , top_left_grid_pin_45_ , - top_left_grid_pin_46_ , top_left_grid_pin_47_ , top_left_grid_pin_48_ , - top_left_grid_pin_49_ , top_right_grid_pin_1_ , chany_bottom_in , - bottom_right_grid_pin_1_ , bottom_left_grid_pin_42_ , - bottom_left_grid_pin_43_ , bottom_left_grid_pin_44_ , - bottom_left_grid_pin_45_ , bottom_left_grid_pin_46_ , - bottom_left_grid_pin_47_ , bottom_left_grid_pin_48_ , - bottom_left_grid_pin_49_ , chanx_left_in , left_bottom_grid_pin_34_ , - left_bottom_grid_pin_35_ , left_bottom_grid_pin_36_ , - left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , - left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , - left_bottom_grid_pin_41_ , ccff_head , chany_top_out , chany_bottom_out , - chanx_left_out , ccff_tail , VDD , VSS , Test_en__FEEDTHRU_0 , - Test_en__FEEDTHRU_1 , clk__FEEDTHRU_0 , clk__FEEDTHRU_1 ) ; -input [0:0] prog_clk ; -input [0:19] chany_top_in ; -input [0:0] top_left_grid_pin_42_ ; -input [0:0] top_left_grid_pin_43_ ; -input [0:0] top_left_grid_pin_44_ ; -input [0:0] top_left_grid_pin_45_ ; -input [0:0] top_left_grid_pin_46_ ; -input [0:0] top_left_grid_pin_47_ ; -input [0:0] top_left_grid_pin_48_ ; -input [0:0] top_left_grid_pin_49_ ; -input [0:0] top_right_grid_pin_1_ ; -input [0:19] chany_bottom_in ; -input [0:0] bottom_right_grid_pin_1_ ; -input [0:0] bottom_left_grid_pin_42_ ; -input [0:0] bottom_left_grid_pin_43_ ; -input [0:0] bottom_left_grid_pin_44_ ; -input [0:0] bottom_left_grid_pin_45_ ; -input [0:0] bottom_left_grid_pin_46_ ; -input [0:0] bottom_left_grid_pin_47_ ; -input [0:0] bottom_left_grid_pin_48_ ; -input [0:0] bottom_left_grid_pin_49_ ; -input [0:19] chanx_left_in ; -input [0:0] left_bottom_grid_pin_34_ ; -input [0:0] left_bottom_grid_pin_35_ ; -input [0:0] left_bottom_grid_pin_36_ ; -input [0:0] left_bottom_grid_pin_37_ ; -input [0:0] left_bottom_grid_pin_38_ ; -input [0:0] left_bottom_grid_pin_39_ ; -input [0:0] left_bottom_grid_pin_40_ ; -input [0:0] left_bottom_grid_pin_41_ ; -input [0:0] ccff_head ; -output [0:19] chany_top_out ; -output [0:19] chany_bottom_out ; -output [0:19] chanx_left_out ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; -input [0:0] Test_en__FEEDTHRU_0 ; -output [0:0] Test_en__FEEDTHRU_1 ; -input [0:0] clk__FEEDTHRU_0 ; -output [0:0] clk__FEEDTHRU_1 ; - -wire [0:2] mux_bottom_track_17_undriven_sram_inv ; -wire [0:3] mux_bottom_track_1_undriven_sram_inv ; -wire [0:2] mux_bottom_track_25_undriven_sram_inv ; -wire [0:2] mux_bottom_track_33_undriven_sram_inv ; -wire [0:3] mux_bottom_track_3_undriven_sram_inv ; -wire [0:3] mux_bottom_track_5_undriven_sram_inv ; -wire [0:3] mux_bottom_track_9_undriven_sram_inv ; -wire [0:2] mux_left_track_11_undriven_sram_inv ; -wire [0:2] mux_left_track_13_undriven_sram_inv ; -wire [0:2] mux_left_track_15_undriven_sram_inv ; -wire [0:1] mux_left_track_17_undriven_sram_inv ; -wire [0:1] mux_left_track_19_undriven_sram_inv ; -wire [0:2] mux_left_track_1_undriven_sram_inv ; -wire [0:1] mux_left_track_21_undriven_sram_inv ; -wire [0:1] mux_left_track_23_undriven_sram_inv ; -wire [0:1] mux_left_track_25_undriven_sram_inv ; -wire [0:1] mux_left_track_29_undriven_sram_inv ; -wire [0:1] mux_left_track_31_undriven_sram_inv ; -wire [0:1] mux_left_track_33_undriven_sram_inv ; -wire [0:1] mux_left_track_35_undriven_sram_inv ; -wire [0:1] mux_left_track_37_undriven_sram_inv ; -wire [0:1] mux_left_track_39_undriven_sram_inv ; -wire [0:2] mux_left_track_3_undriven_sram_inv ; -wire [0:2] mux_left_track_5_undriven_sram_inv ; -wire [0:2] mux_left_track_7_undriven_sram_inv ; -wire [0:2] mux_left_track_9_undriven_sram_inv ; -wire [0:3] mux_top_track_0_undriven_sram_inv ; -wire [0:2] mux_top_track_16_undriven_sram_inv ; -wire [0:2] mux_top_track_24_undriven_sram_inv ; -wire [0:3] mux_top_track_2_undriven_sram_inv ; -wire [0:2] mux_top_track_32_undriven_sram_inv ; -wire [0:3] mux_top_track_4_undriven_sram_inv ; -wire [0:3] mux_top_track_8_undriven_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size14_0_sram ; -wire [0:3] mux_tree_tapbuf_size14_1_sram ; -wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail ; -wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_5_sram ; -wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; -wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:1] mux_tree_tapbuf_size3_2_sram ; -wire [0:1] mux_tree_tapbuf_size3_3_sram ; -wire [0:1] mux_tree_tapbuf_size3_4_sram ; -wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size4_0_sram ; -wire [0:2] mux_tree_tapbuf_size4_1_sram ; -wire [0:2] mux_tree_tapbuf_size4_2_sram ; -wire [0:2] mux_tree_tapbuf_size4_3_sram ; -wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size6_1_sram ; -wire [0:2] mux_tree_tapbuf_size6_2_sram ; -wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size7_0_sram ; -wire [0:2] mux_tree_tapbuf_size7_1_sram ; -wire [0:2] mux_tree_tapbuf_size7_2_sram ; -wire [0:2] mux_tree_tapbuf_size7_3_sram ; -wire [0:2] mux_tree_tapbuf_size7_4_sram ; -wire [0:2] mux_tree_tapbuf_size7_5_sram ; -wire [0:2] mux_tree_tapbuf_size7_6_sram ; -wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:3] mux_tree_tapbuf_size8_2_sram ; -wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size9_0_sram ; -wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ; -supply1 VDD ; -supply0 VSS ; -// - -assign clk__FEEDTHRU_1[0] = clk__FEEDTHRU_0[0] ; - -sb_2__1__mux_tree_tapbuf_size10 mux_top_track_0 ( - .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , - top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , - top_right_grid_pin_1_[0] , chany_bottom_in[2] , chany_bottom_in[12] , - chanx_left_in[0] , chanx_left_in[7] , chanx_left_in[14] } ) , - .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_top_track_0_undriven_sram_inv ) , - .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_126 ) ) ; -sb_2__1__mux_tree_tapbuf_size10_0 mux_bottom_track_1 ( - .in ( { chany_top_in[2] , chany_top_in[12] , bottom_right_grid_pin_1_[0] , - bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , - bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , - chanx_left_in[1] , chanx_left_in[8] , chanx_left_in[15] } ) , - .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_bottom_track_1_undriven_sram_inv ) , - .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_126 ) ) ; -sb_2__1__mux_tree_tapbuf_size10_mem mem_top_track_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__1__mux_tree_tapbuf_size10_mem_0 mem_bottom_track_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__1__mux_tree_tapbuf_size8_1 mux_top_track_2 ( - .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , - top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , - chany_bottom_in[4] , chany_bottom_in[13] , chanx_left_in[6] , - chanx_left_in[13] } ) , - .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_top_track_2_undriven_sram_inv ) , - .out ( chany_top_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_127 ) ) ; -sb_2__1__mux_tree_tapbuf_size8 mux_top_track_8 ( - .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_46_[0] , - top_right_grid_pin_1_[0] , chany_bottom_in[6] , chany_bottom_in[16] , - chanx_left_in[4] , chanx_left_in[11] , chanx_left_in[18] } ) , - .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_top_track_8_undriven_sram_inv ) , - .out ( chany_top_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_127 ) ) ; -sb_2__1__mux_tree_tapbuf_size8_0 mux_bottom_track_9 ( - .in ( { chany_top_in[6] , chany_top_in[16] , bottom_right_grid_pin_1_[0] , - bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_49_[0] , - chanx_left_in[4] , chanx_left_in[11] , chanx_left_in[18] } ) , - .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_bottom_track_9_undriven_sram_inv ) , - .out ( chany_bottom_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_125 ) ) ; -sb_2__1__mux_tree_tapbuf_size8_mem_1 mem_top_track_2 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__1__mux_tree_tapbuf_size8_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__1__mux_tree_tapbuf_size8_mem_0 mem_bottom_track_9 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__1__mux_tree_tapbuf_size14 mux_top_track_4 ( - .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_43_[0] , - top_left_grid_pin_44_[0] , top_left_grid_pin_45_[0] , - top_left_grid_pin_46_[0] , top_left_grid_pin_47_[0] , - top_left_grid_pin_48_[0] , top_left_grid_pin_49_[0] , - top_right_grid_pin_1_[0] , chany_bottom_in[5] , chany_bottom_in[14] , - chanx_left_in[5] , chanx_left_in[12] , chanx_left_in[19] } ) , - .sram ( mux_tree_tapbuf_size14_0_sram ) , - .sram_inv ( mux_top_track_4_undriven_sram_inv ) , - .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_127 ) ) ; -sb_2__1__mux_tree_tapbuf_size14_0 mux_bottom_track_5 ( - .in ( { chany_top_in[5] , chany_top_in[14] , bottom_right_grid_pin_1_[0] , - bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_43_[0] , - bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_45_[0] , - bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_47_[0] , - bottom_left_grid_pin_48_[0] , bottom_left_grid_pin_49_[0] , - chanx_left_in[3] , chanx_left_in[10] , chanx_left_in[17] } ) , - .sram ( mux_tree_tapbuf_size14_1_sram ) , - .sram_inv ( mux_bottom_track_5_undriven_sram_inv ) , - .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_125 ) ) ; -sb_2__1__mux_tree_tapbuf_size14_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size14_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__1__mux_tree_tapbuf_size14_mem_0 mem_bottom_track_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size14_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__1__mux_tree_tapbuf_size7_5 mux_top_track_16 ( - .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_47_[0] , - chany_bottom_in[8] , chany_bottom_in[17] , chanx_left_in[3] , - chanx_left_in[10] , chanx_left_in[17] } ) , - .sram ( mux_tree_tapbuf_size7_0_sram ) , - .sram_inv ( mux_top_track_16_undriven_sram_inv ) , - .out ( chany_top_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_126 ) ) ; -sb_2__1__mux_tree_tapbuf_size7 mux_top_track_24 ( - .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_48_[0] , - chany_bottom_in[9] , chany_bottom_in[18] , chanx_left_in[2] , - chanx_left_in[9] , chanx_left_in[16] } ) , - .sram ( mux_tree_tapbuf_size7_1_sram ) , - .sram_inv ( mux_top_track_24_undriven_sram_inv ) , - .out ( chany_top_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_126 ) ) ; -sb_2__1__mux_tree_tapbuf_size7_0 mux_bottom_track_17 ( - .in ( { chany_top_in[8] , chany_top_in[17] , bottom_left_grid_pin_42_[0] , - bottom_left_grid_pin_46_[0] , chanx_left_in[5] , chanx_left_in[12] , - chanx_left_in[19] } ) , - .sram ( mux_tree_tapbuf_size7_2_sram ) , - .sram_inv ( mux_bottom_track_17_undriven_sram_inv ) , - .out ( chany_bottom_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_126 ) ) ; -sb_2__1__mux_tree_tapbuf_size7_1 mux_left_track_1 ( - .in ( { chany_top_in[0] , chany_top_in[2] , chany_bottom_in[2] , - left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , - left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , - .sram ( mux_tree_tapbuf_size7_3_sram ) , - .sram_inv ( mux_left_track_1_undriven_sram_inv ) , - .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_128 ) ) ; -sb_2__1__mux_tree_tapbuf_size7_2 mux_left_track_3 ( - .in ( { chany_top_in[4] , chany_bottom_in[0] , chany_bottom_in[4] , - left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , - left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , - .sram ( mux_tree_tapbuf_size7_4_sram ) , - .sram_inv ( mux_left_track_3_undriven_sram_inv ) , - .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_128 ) ) ; -sb_2__1__mux_tree_tapbuf_size7_3 mux_left_track_5 ( - .in ( { chany_top_in[5] , chany_bottom_in[1] , chany_bottom_in[5] , - left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , - left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , - .sram ( mux_tree_tapbuf_size7_5_sram ) , - .sram_inv ( mux_left_track_5_undriven_sram_inv ) , - .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_128 ) ) ; -sb_2__1__mux_tree_tapbuf_size7_4 mux_left_track_7 ( - .in ( { chany_top_in[6] , chany_bottom_in[3] , chany_bottom_in[6] , - left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , - left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , - .sram ( mux_tree_tapbuf_size7_6_sram ) , - .sram_inv ( mux_left_track_7_undriven_sram_inv ) , - .out ( chanx_left_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_128 ) ) ; -sb_2__1__mux_tree_tapbuf_size7_mem_5 mem_top_track_16 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__1__mux_tree_tapbuf_size7_mem mem_top_track_24 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__1__mux_tree_tapbuf_size7_mem_0 mem_bottom_track_17 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__1__mux_tree_tapbuf_size7_mem_1 mem_left_track_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__1__mux_tree_tapbuf_size7_mem_2 mem_left_track_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__1__mux_tree_tapbuf_size7_mem_3 mem_left_track_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__1__mux_tree_tapbuf_size7_mem_4 mem_left_track_7 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__1__mux_tree_tapbuf_size6 mux_top_track_32 ( - .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_49_[0] , - chany_bottom_in[10] , chanx_left_in[1] , chanx_left_in[8] , - chanx_left_in[15] } ) , - .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_top_track_32_undriven_sram_inv ) , - .out ( chany_top_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_126 ) ) ; -sb_2__1__mux_tree_tapbuf_size6_0 mux_bottom_track_25 ( - .in ( { chany_top_in[9] , chany_top_in[18] , bottom_left_grid_pin_43_[0] , - bottom_left_grid_pin_47_[0] , chanx_left_in[6] , chanx_left_in[13] } ) , - .sram ( mux_tree_tapbuf_size6_1_sram ) , - .sram_inv ( mux_bottom_track_25_undriven_sram_inv ) , - .out ( chany_bottom_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_125 ) ) ; -sb_2__1__mux_tree_tapbuf_size6_1 mux_bottom_track_33 ( - .in ( { chany_top_in[10] , bottom_left_grid_pin_44_[0] , - bottom_left_grid_pin_48_[0] , chanx_left_in[0] , chanx_left_in[7] , - chanx_left_in[14] } ) , - .sram ( mux_tree_tapbuf_size6_2_sram ) , - .sram_inv ( mux_bottom_track_33_undriven_sram_inv ) , - .out ( chany_bottom_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_126 ) ) ; -sb_2__1__mux_tree_tapbuf_size6_mem mem_top_track_32 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__1__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_25 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__1__mux_tree_tapbuf_size6_mem_1 mem_bottom_track_33 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__1__mux_tree_tapbuf_size9 mux_bottom_track_3 ( - .in ( { chany_top_in[4] , chany_top_in[13] , bottom_left_grid_pin_42_[0] , - bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , - bottom_left_grid_pin_48_[0] , chanx_left_in[2] , chanx_left_in[9] , - chanx_left_in[16] } ) , - .sram ( mux_tree_tapbuf_size9_0_sram ) , - .sram_inv ( mux_bottom_track_3_undriven_sram_inv ) , - .out ( { ropt_net_132 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_125 ) ) ; -sb_2__1__mux_tree_tapbuf_size9_mem mem_bottom_track_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size9_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__1__mux_tree_tapbuf_size4 mux_left_track_9 ( - .in ( { chany_top_in[8] , chany_bottom_in[7] , chany_bottom_in[8] , - left_bottom_grid_pin_34_[0] } ) , - .sram ( mux_tree_tapbuf_size4_0_sram ) , - .sram_inv ( mux_left_track_9_undriven_sram_inv ) , - .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_128 ) ) ; -sb_2__1__mux_tree_tapbuf_size4_0 mux_left_track_11 ( - .in ( { chany_top_in[9] , chany_bottom_in[9] , chany_bottom_in[11] , - left_bottom_grid_pin_35_[0] } ) , - .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_left_track_11_undriven_sram_inv ) , - .out ( chanx_left_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_128 ) ) ; -sb_2__1__mux_tree_tapbuf_size4_1 mux_left_track_13 ( - .in ( { chany_top_in[10] , chany_bottom_in[10] , chany_bottom_in[15] , - left_bottom_grid_pin_36_[0] } ) , - .sram ( mux_tree_tapbuf_size4_2_sram ) , - .sram_inv ( mux_left_track_13_undriven_sram_inv ) , - .out ( { ropt_net_130 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_125 ) ) ; -sb_2__1__mux_tree_tapbuf_size4_2 mux_left_track_15 ( - .in ( { chany_top_in[12] , chany_bottom_in[12] , chany_bottom_in[19] , - left_bottom_grid_pin_37_[0] } ) , - .sram ( mux_tree_tapbuf_size4_3_sram ) , - .sram_inv ( mux_left_track_15_undriven_sram_inv ) , - .out ( chanx_left_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_125 ) ) ; -sb_2__1__mux_tree_tapbuf_size4_mem mem_left_track_9 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__1__mux_tree_tapbuf_size4_mem_0 mem_left_track_11 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__1__mux_tree_tapbuf_size4_mem_1 mem_left_track_13 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__1__mux_tree_tapbuf_size4_mem_2 mem_left_track_15 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__1__mux_tree_tapbuf_size3_0 mux_left_track_17 ( - .in ( { chany_top_in[13] , chany_bottom_in[13] , - left_bottom_grid_pin_38_[0] } ) , - .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_left_track_17_undriven_sram_inv ) , - .out ( { ropt_net_131 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_125 ) ) ; -sb_2__1__mux_tree_tapbuf_size3_1 mux_left_track_19 ( - .in ( { chany_top_in[14] , chany_bottom_in[14] , - left_bottom_grid_pin_39_[0] } ) , - .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_left_track_19_undriven_sram_inv ) , - .out ( chanx_left_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_127 ) ) ; -sb_2__1__mux_tree_tapbuf_size3_2 mux_left_track_21 ( - .in ( { chany_top_in[16] , chany_bottom_in[16] , - left_bottom_grid_pin_40_[0] } ) , - .sram ( mux_tree_tapbuf_size3_2_sram ) , - .sram_inv ( mux_left_track_21_undriven_sram_inv ) , - .out ( chanx_left_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_128 ) ) ; -sb_2__1__mux_tree_tapbuf_size3_3 mux_left_track_23 ( - .in ( { chany_top_in[17] , chany_bottom_in[17] , - left_bottom_grid_pin_41_[0] } ) , - .sram ( mux_tree_tapbuf_size3_3_sram ) , - .sram_inv ( mux_left_track_23_undriven_sram_inv ) , - .out ( chanx_left_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_127 ) ) ; -sb_2__1__mux_tree_tapbuf_size3 mux_left_track_25 ( - .in ( { chany_top_in[18] , chany_bottom_in[18] , - left_bottom_grid_pin_34_[0] } ) , - .sram ( mux_tree_tapbuf_size3_4_sram ) , - .sram_inv ( mux_left_track_25_undriven_sram_inv ) , - .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_128 ) ) ; -sb_2__1__mux_tree_tapbuf_size3_mem_0 mem_left_track_17 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__1__mux_tree_tapbuf_size3_mem_1 mem_left_track_19 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__1__mux_tree_tapbuf_size3_mem_2 mem_left_track_21 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__1__mux_tree_tapbuf_size3_mem_3 mem_left_track_23 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__1__mux_tree_tapbuf_size3_mem mem_left_track_25 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__1__mux_tree_tapbuf_size2_0 mux_left_track_29 ( - .in ( { chany_top_in[19] , left_bottom_grid_pin_36_[0] } ) , - .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_left_track_29_undriven_sram_inv ) , - .out ( chanx_left_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_128 ) ) ; -sb_2__1__mux_tree_tapbuf_size2_1 mux_left_track_31 ( - .in ( { chany_top_in[15] , left_bottom_grid_pin_37_[0] } ) , - .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_left_track_31_undriven_sram_inv ) , - .out ( chanx_left_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_127 ) ) ; -sb_2__1__mux_tree_tapbuf_size2_2 mux_left_track_33 ( - .in ( { chany_top_in[11] , left_bottom_grid_pin_38_[0] } ) , - .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_left_track_33_undriven_sram_inv ) , - .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_127 ) ) ; -sb_2__1__mux_tree_tapbuf_size2_3 mux_left_track_35 ( - .in ( { chany_top_in[7] , left_bottom_grid_pin_39_[0] } ) , - .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_left_track_35_undriven_sram_inv ) , - .out ( chanx_left_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_127 ) ) ; -sb_2__1__mux_tree_tapbuf_size2_4 mux_left_track_37 ( - .in ( { chany_top_in[3] , left_bottom_grid_pin_40_[0] } ) , - .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_left_track_37_undriven_sram_inv ) , - .out ( chanx_left_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_127 ) ) ; -sb_2__1__mux_tree_tapbuf_size2 mux_left_track_39 ( - .in ( { chany_top_in[1] , left_bottom_grid_pin_41_[0] } ) , - .sram ( mux_tree_tapbuf_size2_5_sram ) , - .sram_inv ( mux_left_track_39_undriven_sram_inv ) , - .out ( chanx_left_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_127 ) ) ; -sb_2__1__mux_tree_tapbuf_size2_mem_0 mem_left_track_29 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__1__mux_tree_tapbuf_size2_mem_1 mem_left_track_31 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__1__mux_tree_tapbuf_size2_mem_2 mem_left_track_33 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__1__mux_tree_tapbuf_size2_mem_3 mem_left_track_35 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__1__mux_tree_tapbuf_size2_mem_4 mem_left_track_37 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__1__mux_tree_tapbuf_size2_mem mem_left_track_39 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .ccff_tail ( { ropt_net_134 } ) , - .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1500 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1501 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1502 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1503 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1504 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1505 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1506 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1507 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1508 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1509 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1510 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1511 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1512 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1513 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1514 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1515 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1516 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1517 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1518 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1519 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1520 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1521 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1522 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1523 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1524 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1525 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1526 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1527 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1528 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1529 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1530 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1531 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1532 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1533 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1534 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1535 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1536 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1537 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1538 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1539 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1540 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1541 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_126 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__3 ( .A ( chany_top_in[6] ) , - .X ( ropt_net_145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_120 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chany_top_in[9] ) , - .X ( ropt_net_156 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__6 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__7 ( .A ( chany_top_in[12] ) , - .X ( ropt_net_151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_122 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chany_top_in[14] ) , - .X ( ropt_net_150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chany_top_in[16] ) , - .X ( ropt_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( chany_top_in[17] ) , - .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__12 ( .A ( chany_top_in[18] ) , - .X ( ropt_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chany_bottom_in[2] ) , - .X ( ropt_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__14 ( .A ( chany_bottom_in[4] ) , - .X ( ropt_net_142 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__15 ( .A ( chany_bottom_in[5] ) , - .X ( ropt_net_144 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__16 ( .A ( chany_bottom_in[6] ) , - .X ( aps_rename_1_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_130 ) , - .X ( ropt_net_168 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( ropt_net_131 ) , - .X ( chanx_left_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_132 ) , - .X ( ropt_net_169 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__20 ( .A ( chany_bottom_in[12] ) , - .X ( ropt_net_158 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_161 ) , - .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_23__22 ( .A ( chany_bottom_in[14] ) , - .X ( ropt_net_139 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_162 ) , - .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_25__24 ( .A ( chany_bottom_in[17] ) , - .X ( ropt_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_26__25 ( .A ( chany_bottom_in[18] ) , - .X ( ropt_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_163 ) , - .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_133 ) , - .X ( ropt_net_173 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_759 ( .A ( ropt_net_164 ) , - .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_165 ) , - .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_166 ) , - .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( ropt_net_134 ) , - .X ( ropt_net_180 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( - .A ( chany_bottom_in[16] ) , .X ( ropt_net_182 ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( - .A ( chany_bottom_in[13] ) , .X ( ropt_net_181 ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( chany_top_in[13] ) , - .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_167 ) , - .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_763 ( .A ( ropt_net_168 ) , - .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_77 ( - .A ( left_bottom_grid_pin_35_[0] ) , .X ( ropt_net_133 ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_81 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( chany_top_in[8] ) , - .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_766 ( .A ( ropt_net_169 ) , - .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_139 ) , - .X ( ropt_net_161 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_140 ) , - .X ( ropt_net_164 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( chany_bottom_in[8] ) , - .X ( ropt_net_166 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( ropt_net_170 ) , - .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_98 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_183 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_99 ( .A ( chany_top_in[4] ) , - .X ( ropt_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_100 ( .A ( Test_en__FEEDTHRU_0[0] ) , - .X ( ropt_net_152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( ropt_net_142 ) , - .X ( ropt_net_167 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_103 ( .A ( aps_rename_1_ ) , - .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_769 ( .A ( ropt_net_171 ) , - .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_143 ) , - .X ( ropt_net_177 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_144 ) , - .X ( ropt_net_176 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_145 ) , - .X ( ropt_net_163 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_742 ( .A ( ropt_net_146 ) , - .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_172 ) , - .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_113 ( .A ( chany_bottom_in[10] ) , - .X ( ropt_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_147 ) , - .X ( ropt_net_162 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_148 ) , - .X ( ropt_net_174 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_149 ) , - .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_150 ) , - .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( ropt_net_151 ) , - .X ( ropt_net_171 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_152 ) , - .X ( ropt_net_178 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( .A ( ropt_net_153 ) , - .X ( ropt_net_179 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_154 ) , - .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_155 ) , - .X ( ropt_net_175 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_156 ) , - .X ( ropt_net_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_157 ) , - .X ( ropt_net_170 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_158 ) , - .X ( ropt_net_172 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_771 ( .A ( ropt_net_173 ) , - .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_772 ( .A ( ropt_net_174 ) , - .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_773 ( .A ( ropt_net_175 ) , - .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_774 ( .A ( ropt_net_176 ) , - .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( ropt_net_177 ) , - .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( ropt_net_178 ) , - .X ( Test_en__FEEDTHRU_1[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( ropt_net_179 ) , - .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_180 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_181 ) , - .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_182 ) , - .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_183 ) , - .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y0 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y0 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x285200y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x285200y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x625600y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x717600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x331200y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x841800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x878600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x630200y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x717600y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x759000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x860200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x220800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x510600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x685400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x703800y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x823400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x860200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x897000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x105800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x115000y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x161000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x179400y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x225400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x317400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x326600y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x579600y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x736000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x786600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x69000y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x115000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x151800y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x197800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x483000y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x529000y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x837200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x874000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x101200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x151800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x161000y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x207000y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x253000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x303600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x312800y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x358800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x395600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x404800y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x450800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x524400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x533600y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x579600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x588800y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x713000y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x795800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x115000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x165600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x216200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x266800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x326600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x335800y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x450800y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x496800y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x575000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x630200y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x676200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x694600y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x860200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x897000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x59800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x170200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x207000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x322000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x372600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x409400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x487600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x496800y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x653200y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x777400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x795800y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x837200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x101200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x179400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x188600y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x285200y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x538200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x671600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x731400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x749800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x82800y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x165600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x174800y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x506000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x588800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x607200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x736000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x754400y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x55200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x64400y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x147200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x165600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x216200y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x271400y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x317400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x501400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x584200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x694600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x754400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x791200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x874000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x101200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x138000y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x285200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x335800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x354200y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x400200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x418600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x662400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x717600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x736000y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x823400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x860200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x239200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x289800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x308200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x358800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x492200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x529000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x547400y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x625600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x708400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x726800y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x809600y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x161000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x179400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x188600y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x234600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x285200y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x331200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x349600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x358800y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x404800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x455400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x506000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x515200y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x561200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x579600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x722200y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x768200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x786600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x147200y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x193200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x266800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x303600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x322000y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x363400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x473800y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x515200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x575000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x699200y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x745200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x754400y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x874000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x73600y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x138000y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x289800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x423200y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x469200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x487600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x496800y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x611800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x630200y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x676200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x713000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x749800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x786600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x805000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x814200y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x855600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x124200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x409400y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x487600y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x565800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x575000y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x621000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x630200y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x676200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x726800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x786600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x878600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x73600y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x105800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x115000y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x147200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x197800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x276000y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x322000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x331200y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x423200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x441600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x492200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x510600y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x630200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x639400y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x717600y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x96600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x105800y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x138000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x174800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x234600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x271400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x308200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x450800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x487600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x547400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x565800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x671600y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x713000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x731400y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x814200y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x892400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x55200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x119600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x179400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x262200y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x340400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x358800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x409400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x496800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x570400y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x759000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x786600y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x828000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x179400y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x225400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x276000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x303600y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x455400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x547400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x556600y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x662400y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x708400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x717600y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x69000y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x115000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x151800y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x239200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x322000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x340400y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x460000y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x657800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x713000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x731400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x782000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x55200y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x133400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x170200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x207000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x225400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x308200y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x354200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x538200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x593400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x602600y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x621000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x639400y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x754400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x791200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x828000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x864800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x901600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x220800y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x266800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x317400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x335800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x345000y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x423200y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x469200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x478400y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x524400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x542800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x552000y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x703800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x722200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x110400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x161000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x179400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x202400y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x248400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x299000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x358800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x432400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x450800y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x565800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x575000y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x621000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x630200y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x749800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x786600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x823400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x860200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x897000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x128800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x414000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x506000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x579600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x639400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x676200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x713000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x722200y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x768200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x777400y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x855600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x105800y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x202400y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x285200y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x331200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x391000y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x437000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x510600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x529000y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x740600y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x818800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x855600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x892400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x69000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x202400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x239200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x276000y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x354200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x372600y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x460000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x478400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x487600y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x565800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x584200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x593400y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x639400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x731400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x823400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x860200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x69000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x179400y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x308200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x326600y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x427800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x455400y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x492200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x510600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x519800y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x565800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x584200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x708400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x717600y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x763600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x823400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x860200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x897000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x294400y870400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x340400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x358800y870400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x556600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x575000y870400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x621000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x722200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x740600y870400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x818800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x855600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y870400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y870400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x156400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x193200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y897600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x391000y897600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x478400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x496800y897600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x611800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x722200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x731400y897600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x101200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x138000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x230000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x248400y924800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x335800y924800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x556600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x616400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x634800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x644000y924800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y924800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x285200y952000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x322000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x680800y952000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y952000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x579600y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x598000y979200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y979200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y979200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x285200y1006400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x575000y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x593400y1006400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x763600y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x837200y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x874000y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y1033600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y1060800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y1060800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__1__icv_in_design.pt.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__1__icv_in_design.pt.v deleted file mode 100644 index 0dfd962..0000000 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__1__icv_in_design.pt.v +++ /dev/null @@ -1,2459 +0,0 @@ -// -// -// -// -// -// -module sb_2__1__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__60 ( .A ( mem_out[1] ) , - .X ( net_net_79 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_78 ( .A ( net_net_79 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__59 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__58 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__57 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__56 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__55 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__54 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__53 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__52 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__51 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__50 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_67 ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__49 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__48 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__47 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__46 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_65 ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( BUF_net_65 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_107 ( .A ( BUF_net_65 ) , - .X ( out[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size9_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__45 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , p0 ) ; -input [0:8] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_106 ( - .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__44 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__43 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__42 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__41 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__40 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__39 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__38 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__37 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__36 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__35 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size14_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__34 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size14_mem ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__33 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size14_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:13] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size14 ( in , sram , sram_inv , out , p0 ) ; -input [0:13] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__32 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__31 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__30 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__29 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__28 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module sb_2__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module sb_2__1_ ( prog_clk , chany_top_in , top_left_grid_pin_42_ , - top_left_grid_pin_43_ , top_left_grid_pin_44_ , top_left_grid_pin_45_ , - top_left_grid_pin_46_ , top_left_grid_pin_47_ , top_left_grid_pin_48_ , - top_left_grid_pin_49_ , top_right_grid_pin_1_ , chany_bottom_in , - bottom_right_grid_pin_1_ , bottom_left_grid_pin_42_ , - bottom_left_grid_pin_43_ , bottom_left_grid_pin_44_ , - bottom_left_grid_pin_45_ , bottom_left_grid_pin_46_ , - bottom_left_grid_pin_47_ , bottom_left_grid_pin_48_ , - bottom_left_grid_pin_49_ , chanx_left_in , left_bottom_grid_pin_34_ , - left_bottom_grid_pin_35_ , left_bottom_grid_pin_36_ , - left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , - left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , - left_bottom_grid_pin_41_ , ccff_head , chany_top_out , chany_bottom_out , - chanx_left_out , ccff_tail , Test_en__FEEDTHRU_0 , Test_en__FEEDTHRU_1 , - clk__FEEDTHRU_0 , clk__FEEDTHRU_1 ) ; -input [0:0] prog_clk ; -input [0:19] chany_top_in ; -input [0:0] top_left_grid_pin_42_ ; -input [0:0] top_left_grid_pin_43_ ; -input [0:0] top_left_grid_pin_44_ ; -input [0:0] top_left_grid_pin_45_ ; -input [0:0] top_left_grid_pin_46_ ; -input [0:0] top_left_grid_pin_47_ ; -input [0:0] top_left_grid_pin_48_ ; -input [0:0] top_left_grid_pin_49_ ; -input [0:0] top_right_grid_pin_1_ ; -input [0:19] chany_bottom_in ; -input [0:0] bottom_right_grid_pin_1_ ; -input [0:0] bottom_left_grid_pin_42_ ; -input [0:0] bottom_left_grid_pin_43_ ; -input [0:0] bottom_left_grid_pin_44_ ; -input [0:0] bottom_left_grid_pin_45_ ; -input [0:0] bottom_left_grid_pin_46_ ; -input [0:0] bottom_left_grid_pin_47_ ; -input [0:0] bottom_left_grid_pin_48_ ; -input [0:0] bottom_left_grid_pin_49_ ; -input [0:19] chanx_left_in ; -input [0:0] left_bottom_grid_pin_34_ ; -input [0:0] left_bottom_grid_pin_35_ ; -input [0:0] left_bottom_grid_pin_36_ ; -input [0:0] left_bottom_grid_pin_37_ ; -input [0:0] left_bottom_grid_pin_38_ ; -input [0:0] left_bottom_grid_pin_39_ ; -input [0:0] left_bottom_grid_pin_40_ ; -input [0:0] left_bottom_grid_pin_41_ ; -input [0:0] ccff_head ; -output [0:19] chany_top_out ; -output [0:19] chany_bottom_out ; -output [0:19] chanx_left_out ; -output [0:0] ccff_tail ; -input [0:0] Test_en__FEEDTHRU_0 ; -output [0:0] Test_en__FEEDTHRU_1 ; -input [0:0] clk__FEEDTHRU_0 ; -output [0:0] clk__FEEDTHRU_1 ; - -wire [0:2] mux_bottom_track_17_undriven_sram_inv ; -wire [0:3] mux_bottom_track_1_undriven_sram_inv ; -wire [0:2] mux_bottom_track_25_undriven_sram_inv ; -wire [0:2] mux_bottom_track_33_undriven_sram_inv ; -wire [0:3] mux_bottom_track_3_undriven_sram_inv ; -wire [0:3] mux_bottom_track_5_undriven_sram_inv ; -wire [0:3] mux_bottom_track_9_undriven_sram_inv ; -wire [0:2] mux_left_track_11_undriven_sram_inv ; -wire [0:2] mux_left_track_13_undriven_sram_inv ; -wire [0:2] mux_left_track_15_undriven_sram_inv ; -wire [0:1] mux_left_track_17_undriven_sram_inv ; -wire [0:1] mux_left_track_19_undriven_sram_inv ; -wire [0:2] mux_left_track_1_undriven_sram_inv ; -wire [0:1] mux_left_track_21_undriven_sram_inv ; -wire [0:1] mux_left_track_23_undriven_sram_inv ; -wire [0:1] mux_left_track_25_undriven_sram_inv ; -wire [0:1] mux_left_track_29_undriven_sram_inv ; -wire [0:1] mux_left_track_31_undriven_sram_inv ; -wire [0:1] mux_left_track_33_undriven_sram_inv ; -wire [0:1] mux_left_track_35_undriven_sram_inv ; -wire [0:1] mux_left_track_37_undriven_sram_inv ; -wire [0:1] mux_left_track_39_undriven_sram_inv ; -wire [0:2] mux_left_track_3_undriven_sram_inv ; -wire [0:2] mux_left_track_5_undriven_sram_inv ; -wire [0:2] mux_left_track_7_undriven_sram_inv ; -wire [0:2] mux_left_track_9_undriven_sram_inv ; -wire [0:3] mux_top_track_0_undriven_sram_inv ; -wire [0:2] mux_top_track_16_undriven_sram_inv ; -wire [0:2] mux_top_track_24_undriven_sram_inv ; -wire [0:3] mux_top_track_2_undriven_sram_inv ; -wire [0:2] mux_top_track_32_undriven_sram_inv ; -wire [0:3] mux_top_track_4_undriven_sram_inv ; -wire [0:3] mux_top_track_8_undriven_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size14_0_sram ; -wire [0:3] mux_tree_tapbuf_size14_1_sram ; -wire [0:0] mux_tree_tapbuf_size14_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size14_mem_1_ccff_tail ; -wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_5_sram ; -wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; -wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:1] mux_tree_tapbuf_size3_2_sram ; -wire [0:1] mux_tree_tapbuf_size3_3_sram ; -wire [0:1] mux_tree_tapbuf_size3_4_sram ; -wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size4_0_sram ; -wire [0:2] mux_tree_tapbuf_size4_1_sram ; -wire [0:2] mux_tree_tapbuf_size4_2_sram ; -wire [0:2] mux_tree_tapbuf_size4_3_sram ; -wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size6_1_sram ; -wire [0:2] mux_tree_tapbuf_size6_2_sram ; -wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size7_0_sram ; -wire [0:2] mux_tree_tapbuf_size7_1_sram ; -wire [0:2] mux_tree_tapbuf_size7_2_sram ; -wire [0:2] mux_tree_tapbuf_size7_3_sram ; -wire [0:2] mux_tree_tapbuf_size7_4_sram ; -wire [0:2] mux_tree_tapbuf_size7_5_sram ; -wire [0:2] mux_tree_tapbuf_size7_6_sram ; -wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:3] mux_tree_tapbuf_size8_2_sram ; -wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size9_0_sram ; -wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ; -// - -assign clk__FEEDTHRU_1[0] = clk__FEEDTHRU_0[0] ; - -sb_2__1__mux_tree_tapbuf_size10 mux_top_track_0 ( - .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , - top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , - top_right_grid_pin_1_[0] , chany_bottom_in[2] , chany_bottom_in[12] , - chanx_left_in[0] , chanx_left_in[7] , chanx_left_in[14] } ) , - .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_top_track_0_undriven_sram_inv ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_126 ) ) ; -sb_2__1__mux_tree_tapbuf_size10_0 mux_bottom_track_1 ( - .in ( { chany_top_in[2] , chany_top_in[12] , bottom_right_grid_pin_1_[0] , - bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , - bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , - chanx_left_in[1] , chanx_left_in[8] , chanx_left_in[15] } ) , - .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_bottom_track_1_undriven_sram_inv ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_126 ) ) ; -sb_2__1__mux_tree_tapbuf_size10_mem mem_top_track_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size10_mem_0 mem_bottom_track_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size8_1 mux_top_track_2 ( - .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , - top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , - chany_bottom_in[4] , chany_bottom_in[13] , chanx_left_in[6] , - chanx_left_in[13] } ) , - .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_top_track_2_undriven_sram_inv ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_127 ) ) ; -sb_2__1__mux_tree_tapbuf_size8 mux_top_track_8 ( - .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_46_[0] , - top_right_grid_pin_1_[0] , chany_bottom_in[6] , chany_bottom_in[16] , - chanx_left_in[4] , chanx_left_in[11] , chanx_left_in[18] } ) , - .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_top_track_8_undriven_sram_inv ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_127 ) ) ; -sb_2__1__mux_tree_tapbuf_size8_0 mux_bottom_track_9 ( - .in ( { chany_top_in[6] , chany_top_in[16] , bottom_right_grid_pin_1_[0] , - bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_49_[0] , - chanx_left_in[4] , chanx_left_in[11] , chanx_left_in[18] } ) , - .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_bottom_track_9_undriven_sram_inv ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_125 ) ) ; -sb_2__1__mux_tree_tapbuf_size8_mem_1 mem_top_track_2 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size8_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size8_mem_0 mem_bottom_track_9 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size14 mux_top_track_4 ( - .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_43_[0] , - top_left_grid_pin_44_[0] , top_left_grid_pin_45_[0] , - top_left_grid_pin_46_[0] , top_left_grid_pin_47_[0] , - top_left_grid_pin_48_[0] , top_left_grid_pin_49_[0] , - top_right_grid_pin_1_[0] , chany_bottom_in[5] , chany_bottom_in[14] , - chanx_left_in[5] , chanx_left_in[12] , chanx_left_in[19] } ) , - .sram ( mux_tree_tapbuf_size14_0_sram ) , - .sram_inv ( mux_top_track_4_undriven_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_127 ) ) ; -sb_2__1__mux_tree_tapbuf_size14_0 mux_bottom_track_5 ( - .in ( { chany_top_in[5] , chany_top_in[14] , bottom_right_grid_pin_1_[0] , - bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_43_[0] , - bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_45_[0] , - bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_47_[0] , - bottom_left_grid_pin_48_[0] , bottom_left_grid_pin_49_[0] , - chanx_left_in[3] , chanx_left_in[10] , chanx_left_in[17] } ) , - .sram ( mux_tree_tapbuf_size14_1_sram ) , - .sram_inv ( mux_bottom_track_5_undriven_sram_inv ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_125 ) ) ; -sb_2__1__mux_tree_tapbuf_size14_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size14_0_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size14_mem_0 mem_bottom_track_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size14_1_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size7_5 mux_top_track_16 ( - .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_47_[0] , - chany_bottom_in[8] , chany_bottom_in[17] , chanx_left_in[3] , - chanx_left_in[10] , chanx_left_in[17] } ) , - .sram ( mux_tree_tapbuf_size7_0_sram ) , - .sram_inv ( mux_top_track_16_undriven_sram_inv ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_126 ) ) ; -sb_2__1__mux_tree_tapbuf_size7 mux_top_track_24 ( - .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_48_[0] , - chany_bottom_in[9] , chany_bottom_in[18] , chanx_left_in[2] , - chanx_left_in[9] , chanx_left_in[16] } ) , - .sram ( mux_tree_tapbuf_size7_1_sram ) , - .sram_inv ( mux_top_track_24_undriven_sram_inv ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_126 ) ) ; -sb_2__1__mux_tree_tapbuf_size7_0 mux_bottom_track_17 ( - .in ( { chany_top_in[8] , chany_top_in[17] , bottom_left_grid_pin_42_[0] , - bottom_left_grid_pin_46_[0] , chanx_left_in[5] , chanx_left_in[12] , - chanx_left_in[19] } ) , - .sram ( mux_tree_tapbuf_size7_2_sram ) , - .sram_inv ( mux_bottom_track_17_undriven_sram_inv ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_126 ) ) ; -sb_2__1__mux_tree_tapbuf_size7_1 mux_left_track_1 ( - .in ( { chany_top_in[0] , chany_top_in[2] , chany_bottom_in[2] , - left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , - left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , - .sram ( mux_tree_tapbuf_size7_3_sram ) , - .sram_inv ( mux_left_track_1_undriven_sram_inv ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_128 ) ) ; -sb_2__1__mux_tree_tapbuf_size7_2 mux_left_track_3 ( - .in ( { chany_top_in[4] , chany_bottom_in[0] , chany_bottom_in[4] , - left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , - left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , - .sram ( mux_tree_tapbuf_size7_4_sram ) , - .sram_inv ( mux_left_track_3_undriven_sram_inv ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_128 ) ) ; -sb_2__1__mux_tree_tapbuf_size7_3 mux_left_track_5 ( - .in ( { chany_top_in[5] , chany_bottom_in[1] , chany_bottom_in[5] , - left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , - left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , - .sram ( mux_tree_tapbuf_size7_5_sram ) , - .sram_inv ( mux_left_track_5_undriven_sram_inv ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_128 ) ) ; -sb_2__1__mux_tree_tapbuf_size7_4 mux_left_track_7 ( - .in ( { chany_top_in[6] , chany_bottom_in[3] , chany_bottom_in[6] , - left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , - left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , - .sram ( mux_tree_tapbuf_size7_6_sram ) , - .sram_inv ( mux_left_track_7_undriven_sram_inv ) , - .out ( chanx_left_out[3] ) , .p0 ( optlc_net_128 ) ) ; -sb_2__1__mux_tree_tapbuf_size7_mem_5 mem_top_track_16 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size7_mem mem_top_track_24 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size7_mem_0 mem_bottom_track_17 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size7_mem_1 mem_left_track_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_3_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size7_mem_2 mem_left_track_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_4_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size7_mem_3 mem_left_track_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_5_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size7_mem_4 mem_left_track_7 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size7_6_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size6 mux_top_track_32 ( - .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_49_[0] , - chany_bottom_in[10] , chanx_left_in[1] , chanx_left_in[8] , - chanx_left_in[15] } ) , - .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_top_track_32_undriven_sram_inv ) , - .out ( chany_top_out[16] ) , .p0 ( optlc_net_126 ) ) ; -sb_2__1__mux_tree_tapbuf_size6_0 mux_bottom_track_25 ( - .in ( { chany_top_in[9] , chany_top_in[18] , bottom_left_grid_pin_43_[0] , - bottom_left_grid_pin_47_[0] , chanx_left_in[6] , chanx_left_in[13] } ) , - .sram ( mux_tree_tapbuf_size6_1_sram ) , - .sram_inv ( mux_bottom_track_25_undriven_sram_inv ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_125 ) ) ; -sb_2__1__mux_tree_tapbuf_size6_1 mux_bottom_track_33 ( - .in ( { chany_top_in[10] , bottom_left_grid_pin_44_[0] , - bottom_left_grid_pin_48_[0] , chanx_left_in[0] , chanx_left_in[7] , - chanx_left_in[14] } ) , - .sram ( mux_tree_tapbuf_size6_2_sram ) , - .sram_inv ( mux_bottom_track_33_undriven_sram_inv ) , - .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_126 ) ) ; -sb_2__1__mux_tree_tapbuf_size6_mem mem_top_track_32 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_25 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size6_mem_1 mem_bottom_track_33 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_2_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size9 mux_bottom_track_3 ( - .in ( { chany_top_in[4] , chany_top_in[13] , bottom_left_grid_pin_42_[0] , - bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , - bottom_left_grid_pin_48_[0] , chanx_left_in[2] , chanx_left_in[9] , - chanx_left_in[16] } ) , - .sram ( mux_tree_tapbuf_size9_0_sram ) , - .sram_inv ( mux_bottom_track_3_undriven_sram_inv ) , - .out ( { ropt_net_132 } ) , - .p0 ( optlc_net_125 ) ) ; -sb_2__1__mux_tree_tapbuf_size9_mem mem_bottom_track_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size9_0_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size4 mux_left_track_9 ( - .in ( { chany_top_in[8] , chany_bottom_in[7] , chany_bottom_in[8] , - left_bottom_grid_pin_34_[0] } ) , - .sram ( mux_tree_tapbuf_size4_0_sram ) , - .sram_inv ( mux_left_track_9_undriven_sram_inv ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_128 ) ) ; -sb_2__1__mux_tree_tapbuf_size4_0 mux_left_track_11 ( - .in ( { chany_top_in[9] , chany_bottom_in[9] , chany_bottom_in[11] , - left_bottom_grid_pin_35_[0] } ) , - .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_left_track_11_undriven_sram_inv ) , - .out ( chanx_left_out[5] ) , .p0 ( optlc_net_128 ) ) ; -sb_2__1__mux_tree_tapbuf_size4_1 mux_left_track_13 ( - .in ( { chany_top_in[10] , chany_bottom_in[10] , chany_bottom_in[15] , - left_bottom_grid_pin_36_[0] } ) , - .sram ( mux_tree_tapbuf_size4_2_sram ) , - .sram_inv ( mux_left_track_13_undriven_sram_inv ) , - .out ( { ropt_net_130 } ) , - .p0 ( optlc_net_125 ) ) ; -sb_2__1__mux_tree_tapbuf_size4_2 mux_left_track_15 ( - .in ( { chany_top_in[12] , chany_bottom_in[12] , chany_bottom_in[19] , - left_bottom_grid_pin_37_[0] } ) , - .sram ( mux_tree_tapbuf_size4_3_sram ) , - .sram_inv ( mux_left_track_15_undriven_sram_inv ) , - .out ( chanx_left_out[7] ) , .p0 ( optlc_net_125 ) ) ; -sb_2__1__mux_tree_tapbuf_size4_mem mem_left_track_9 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size4_mem_0 mem_left_track_11 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size4_mem_1 mem_left_track_13 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size4_mem_2 mem_left_track_15 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size3_0 mux_left_track_17 ( - .in ( { chany_top_in[13] , chany_bottom_in[13] , - left_bottom_grid_pin_38_[0] } ) , - .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_left_track_17_undriven_sram_inv ) , - .out ( { ropt_net_131 } ) , - .p0 ( optlc_net_125 ) ) ; -sb_2__1__mux_tree_tapbuf_size3_1 mux_left_track_19 ( - .in ( { chany_top_in[14] , chany_bottom_in[14] , - left_bottom_grid_pin_39_[0] } ) , - .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_left_track_19_undriven_sram_inv ) , - .out ( chanx_left_out[9] ) , .p0 ( optlc_net_127 ) ) ; -sb_2__1__mux_tree_tapbuf_size3_2 mux_left_track_21 ( - .in ( { chany_top_in[16] , chany_bottom_in[16] , - left_bottom_grid_pin_40_[0] } ) , - .sram ( mux_tree_tapbuf_size3_2_sram ) , - .sram_inv ( mux_left_track_21_undriven_sram_inv ) , - .out ( chanx_left_out[10] ) , .p0 ( optlc_net_128 ) ) ; -sb_2__1__mux_tree_tapbuf_size3_3 mux_left_track_23 ( - .in ( { chany_top_in[17] , chany_bottom_in[17] , - left_bottom_grid_pin_41_[0] } ) , - .sram ( mux_tree_tapbuf_size3_3_sram ) , - .sram_inv ( mux_left_track_23_undriven_sram_inv ) , - .out ( chanx_left_out[11] ) , .p0 ( optlc_net_127 ) ) ; -sb_2__1__mux_tree_tapbuf_size3 mux_left_track_25 ( - .in ( { chany_top_in[18] , chany_bottom_in[18] , - left_bottom_grid_pin_34_[0] } ) , - .sram ( mux_tree_tapbuf_size3_4_sram ) , - .sram_inv ( mux_left_track_25_undriven_sram_inv ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_128 ) ) ; -sb_2__1__mux_tree_tapbuf_size3_mem_0 mem_left_track_17 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size3_mem_1 mem_left_track_19 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size3_mem_2 mem_left_track_21 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size3_mem_3 mem_left_track_23 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size3_mem mem_left_track_25 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_4_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size2_0 mux_left_track_29 ( - .in ( { chany_top_in[19] , left_bottom_grid_pin_36_[0] } ) , - .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_left_track_29_undriven_sram_inv ) , - .out ( chanx_left_out[14] ) , .p0 ( optlc_net_128 ) ) ; -sb_2__1__mux_tree_tapbuf_size2_1 mux_left_track_31 ( - .in ( { chany_top_in[15] , left_bottom_grid_pin_37_[0] } ) , - .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_left_track_31_undriven_sram_inv ) , - .out ( chanx_left_out[15] ) , .p0 ( optlc_net_127 ) ) ; -sb_2__1__mux_tree_tapbuf_size2_2 mux_left_track_33 ( - .in ( { chany_top_in[11] , left_bottom_grid_pin_38_[0] } ) , - .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_left_track_33_undriven_sram_inv ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_127 ) ) ; -sb_2__1__mux_tree_tapbuf_size2_3 mux_left_track_35 ( - .in ( { chany_top_in[7] , left_bottom_grid_pin_39_[0] } ) , - .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_left_track_35_undriven_sram_inv ) , - .out ( chanx_left_out[17] ) , .p0 ( optlc_net_127 ) ) ; -sb_2__1__mux_tree_tapbuf_size2_4 mux_left_track_37 ( - .in ( { chany_top_in[3] , left_bottom_grid_pin_40_[0] } ) , - .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_left_track_37_undriven_sram_inv ) , - .out ( chanx_left_out[18] ) , .p0 ( optlc_net_127 ) ) ; -sb_2__1__mux_tree_tapbuf_size2 mux_left_track_39 ( - .in ( { chany_top_in[1] , left_bottom_grid_pin_41_[0] } ) , - .sram ( mux_tree_tapbuf_size2_5_sram ) , - .sram_inv ( mux_left_track_39_undriven_sram_inv ) , - .out ( chanx_left_out[19] ) , .p0 ( optlc_net_127 ) ) ; -sb_2__1__mux_tree_tapbuf_size2_mem_0 mem_left_track_29 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size2_mem_1 mem_left_track_31 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size2_mem_2 mem_left_track_33 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size2_mem_3 mem_left_track_35 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size2_mem_4 mem_left_track_37 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ; -sb_2__1__mux_tree_tapbuf_size2_mem mem_left_track_39 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .ccff_tail ( { ropt_net_134 } ) , - .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; -sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_125 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_126 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_154 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__3 ( .A ( chany_top_in[6] ) , - .X ( ropt_net_145 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_120 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_127 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chany_top_in[9] ) , - .X ( ropt_net_156 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__6 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_153 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__7 ( .A ( chany_top_in[12] ) , - .X ( ropt_net_151 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_122 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_128 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chany_top_in[14] ) , - .X ( ropt_net_150 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chany_top_in[16] ) , - .X ( ropt_net_149 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( chany_top_in[17] ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__12 ( .A ( chany_top_in[18] ) , - .X ( ropt_net_148 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chany_bottom_in[2] ) , - .X ( ropt_net_146 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__14 ( .A ( chany_bottom_in[4] ) , - .X ( ropt_net_142 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__15 ( .A ( chany_bottom_in[5] ) , - .X ( ropt_net_144 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__16 ( .A ( chany_bottom_in[6] ) , - .X ( aps_rename_1_ ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_130 ) , - .X ( ropt_net_168 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( ropt_net_131 ) , - .X ( chanx_left_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_132 ) , - .X ( ropt_net_169 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__20 ( .A ( chany_bottom_in[12] ) , - .X ( ropt_net_158 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_161 ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_23__22 ( .A ( chany_bottom_in[14] ) , - .X ( ropt_net_139 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_162 ) , - .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_25__24 ( .A ( chany_bottom_in[17] ) , - .X ( ropt_net_143 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_26__25 ( .A ( chany_bottom_in[18] ) , - .X ( ropt_net_155 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_163 ) , - .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_133 ) , - .X ( ropt_net_173 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_759 ( .A ( ropt_net_164 ) , - .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_165 ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_166 ) , - .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( ropt_net_134 ) , - .X ( ropt_net_180 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( - .A ( chany_bottom_in[16] ) , .X ( ropt_net_182 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( - .A ( chany_bottom_in[13] ) , .X ( ropt_net_181 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( chany_top_in[13] ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_167 ) , - .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_763 ( .A ( ropt_net_168 ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_77 ( - .A ( left_bottom_grid_pin_35_[0] ) , .X ( ropt_net_133 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_81 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_157 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( chany_top_in[8] ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_766 ( .A ( ropt_net_169 ) , - .X ( chany_bottom_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_139 ) , - .X ( ropt_net_161 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_140 ) , - .X ( ropt_net_164 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( chany_bottom_in[8] ) , - .X ( ropt_net_166 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( ropt_net_170 ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_98 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_183 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_99 ( .A ( chany_top_in[4] ) , - .X ( ropt_net_140 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_100 ( .A ( Test_en__FEEDTHRU_0[0] ) , - .X ( ropt_net_152 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( ropt_net_142 ) , - .X ( ropt_net_167 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_103 ( .A ( aps_rename_1_ ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_769 ( .A ( ropt_net_171 ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_143 ) , - .X ( ropt_net_177 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_144 ) , - .X ( ropt_net_176 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_145 ) , - .X ( ropt_net_163 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_742 ( .A ( ropt_net_146 ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_172 ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_113 ( .A ( chany_bottom_in[10] ) , - .X ( ropt_net_147 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_147 ) , - .X ( ropt_net_162 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_148 ) , - .X ( ropt_net_174 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_149 ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_150 ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( ropt_net_151 ) , - .X ( ropt_net_171 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_152 ) , - .X ( ropt_net_178 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( .A ( ropt_net_153 ) , - .X ( ropt_net_179 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_154 ) , - .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_155 ) , - .X ( ropt_net_175 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_156 ) , - .X ( ropt_net_165 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_157 ) , - .X ( ropt_net_170 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_158 ) , - .X ( ropt_net_172 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_771 ( .A ( ropt_net_173 ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_772 ( .A ( ropt_net_174 ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_773 ( .A ( ropt_net_175 ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_774 ( .A ( ropt_net_176 ) , - .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( ropt_net_177 ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( ropt_net_178 ) , - .X ( Test_en__FEEDTHRU_1[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( ropt_net_179 ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_180 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_181 ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_182 ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_183 ) , - .X ( chany_bottom_out[3] ) ) ; -endmodule - - diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__2__icv_in_design.fm.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__2__icv_in_design.fm.v deleted file mode 100644 index 4766e13..0000000 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__2__icv_in_design.fm.v +++ /dev/null @@ -1,2202 +0,0 @@ -// -// -// -// -// -// -module sb_2__2__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_35__40 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_34__39 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__38 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__const1 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sb_2__2__const1 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_2__2__const1_33 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sb_2__2__const1_33 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_2__2__const1_32 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sb_2__2__const1_32 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__37 ( .A ( mem_out[1] ) , - .X ( net_net_51 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_51 ( .A ( net_net_51 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_22 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__36 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_21 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__35 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_20 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__34 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_19 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__33 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_18 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__32 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_17 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__31 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__30 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__29 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__28 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__27 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__26 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__25 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__24 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__23 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__22 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__21 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__20 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__19 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__18 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__17 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__16 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__15 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__14 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__const1_31 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__2__const1_31 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__const1_30 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_22 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__2__const1_30 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__const1_29 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_21 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__2__const1_29 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__const1_28 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_20 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__2__const1_28 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__const1_27 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_19 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__2__const1_27 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__const1_26 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__2__const1_26 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__const1_25 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__2__const1_25 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__const1_24 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__2__const1_24 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__const1_23 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__2__const1_23 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__const1_22 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__2__const1_22 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__const1_21 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__2__const1_21 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__const1_20 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__2__const1_20 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__const1_19 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__2__const1_19 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__const1_18 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__2__const1_18 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__const1_17 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__2__const1_17 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__const1_16 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__2__const1_16 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__const1_15 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__2__const1_15 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__const1_14 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__2__const1_14 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__const1_13 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__2__const1_13 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__const1_12 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__2__const1_12 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__const1_11 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__2__const1_11 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__const1_10 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__2__const1_10 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__const1_9 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__2__const1_9 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__const1_8 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sb_2__2__const1_8 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__13 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size5_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__12 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size5_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__11 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__10 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__const1_7 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -sb_2__2__const1_7 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -endmodule - - -module sb_2__2__const1_6 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sb_2__2__const1_6 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_2__2__const1_5 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sb_2__2__const1_5 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_2__2__const1_4 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -sb_2__2__const1_4 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__9 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size6_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__8 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__7 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__6 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__const1_3 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sb_2__2__const1_3 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module sb_2__2__const1_2 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sb_2__2__const1_2 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module sb_2__2__const1_1 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sb_2__2__const1_1 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module sb_2__2__const1_0 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sb_2__2__const1_0 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module sb_2__2_ ( prog_clk , chany_bottom_in , bottom_right_grid_pin_1_ , - bottom_left_grid_pin_42_ , bottom_left_grid_pin_43_ , - bottom_left_grid_pin_44_ , bottom_left_grid_pin_45_ , - bottom_left_grid_pin_46_ , bottom_left_grid_pin_47_ , - bottom_left_grid_pin_48_ , bottom_left_grid_pin_49_ , chanx_left_in , - left_top_grid_pin_1_ , left_bottom_grid_pin_34_ , - left_bottom_grid_pin_35_ , left_bottom_grid_pin_36_ , - left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , - left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , - left_bottom_grid_pin_41_ , ccff_head , chany_bottom_out , chanx_left_out , - ccff_tail , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , SC_OUT_BOT ) ; -input [0:0] prog_clk ; -input [0:19] chany_bottom_in ; -input [0:0] bottom_right_grid_pin_1_ ; -input [0:0] bottom_left_grid_pin_42_ ; -input [0:0] bottom_left_grid_pin_43_ ; -input [0:0] bottom_left_grid_pin_44_ ; -input [0:0] bottom_left_grid_pin_45_ ; -input [0:0] bottom_left_grid_pin_46_ ; -input [0:0] bottom_left_grid_pin_47_ ; -input [0:0] bottom_left_grid_pin_48_ ; -input [0:0] bottom_left_grid_pin_49_ ; -input [0:19] chanx_left_in ; -input [0:0] left_top_grid_pin_1_ ; -input [0:0] left_bottom_grid_pin_34_ ; -input [0:0] left_bottom_grid_pin_35_ ; -input [0:0] left_bottom_grid_pin_36_ ; -input [0:0] left_bottom_grid_pin_37_ ; -input [0:0] left_bottom_grid_pin_38_ ; -input [0:0] left_bottom_grid_pin_39_ ; -input [0:0] left_bottom_grid_pin_40_ ; -input [0:0] left_bottom_grid_pin_41_ ; -input [0:0] ccff_head ; -output [0:19] chany_bottom_out ; -output [0:19] chanx_left_out ; -output [0:0] ccff_tail ; -input SC_IN_TOP ; -input SC_IN_BOT ; -output SC_OUT_TOP ; -output SC_OUT_BOT ; - -wire [0:1] mux_bottom_track_11_undriven_sram_inv ; -wire [0:1] mux_bottom_track_13_undriven_sram_inv ; -wire [0:1] mux_bottom_track_15_undriven_sram_inv ; -wire [0:1] mux_bottom_track_17_undriven_sram_inv ; -wire [0:1] mux_bottom_track_19_undriven_sram_inv ; -wire [0:2] mux_bottom_track_1_undriven_sram_inv ; -wire [0:1] mux_bottom_track_21_undriven_sram_inv ; -wire [0:1] mux_bottom_track_23_undriven_sram_inv ; -wire [0:1] mux_bottom_track_25_undriven_sram_inv ; -wire [0:1] mux_bottom_track_27_undriven_sram_inv ; -wire [0:1] mux_bottom_track_29_undriven_sram_inv ; -wire [0:2] mux_bottom_track_3_undriven_sram_inv ; -wire [0:2] mux_bottom_track_5_undriven_sram_inv ; -wire [0:2] mux_bottom_track_7_undriven_sram_inv ; -wire [0:1] mux_bottom_track_9_undriven_sram_inv ; -wire [0:1] mux_left_track_11_undriven_sram_inv ; -wire [0:1] mux_left_track_13_undriven_sram_inv ; -wire [0:1] mux_left_track_15_undriven_sram_inv ; -wire [0:1] mux_left_track_17_undriven_sram_inv ; -wire [0:1] mux_left_track_19_undriven_sram_inv ; -wire [0:2] mux_left_track_1_undriven_sram_inv ; -wire [0:1] mux_left_track_21_undriven_sram_inv ; -wire [0:1] mux_left_track_23_undriven_sram_inv ; -wire [0:1] mux_left_track_25_undriven_sram_inv ; -wire [0:1] mux_left_track_27_undriven_sram_inv ; -wire [0:1] mux_left_track_29_undriven_sram_inv ; -wire [0:1] mux_left_track_31_undriven_sram_inv ; -wire [0:1] mux_left_track_33_undriven_sram_inv ; -wire [0:1] mux_left_track_35_undriven_sram_inv ; -wire [0:1] mux_left_track_37_undriven_sram_inv ; -wire [0:1] mux_left_track_39_undriven_sram_inv ; -wire [0:2] mux_left_track_3_undriven_sram_inv ; -wire [0:2] mux_left_track_5_undriven_sram_inv ; -wire [0:2] mux_left_track_7_undriven_sram_inv ; -wire [0:1] mux_left_track_9_undriven_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_10_sram ; -wire [0:1] mux_tree_tapbuf_size2_11_sram ; -wire [0:1] mux_tree_tapbuf_size2_12_sram ; -wire [0:1] mux_tree_tapbuf_size2_13_sram ; -wire [0:1] mux_tree_tapbuf_size2_14_sram ; -wire [0:1] mux_tree_tapbuf_size2_15_sram ; -wire [0:1] mux_tree_tapbuf_size2_16_sram ; -wire [0:1] mux_tree_tapbuf_size2_17_sram ; -wire [0:1] mux_tree_tapbuf_size2_18_sram ; -wire [0:1] mux_tree_tapbuf_size2_19_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_20_sram ; -wire [0:1] mux_tree_tapbuf_size2_21_sram ; -wire [0:1] mux_tree_tapbuf_size2_22_sram ; -wire [0:1] mux_tree_tapbuf_size2_23_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_5_sram ; -wire [0:1] mux_tree_tapbuf_size2_6_sram ; -wire [0:1] mux_tree_tapbuf_size2_7_sram ; -wire [0:1] mux_tree_tapbuf_size2_8_sram ; -wire [0:1] mux_tree_tapbuf_size2_9_sram ; -wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_19_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_20_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_21_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_22_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; -wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:1] mux_tree_tapbuf_size3_2_sram ; -wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size5_0_sram ; -wire [0:2] mux_tree_tapbuf_size5_1_sram ; -wire [0:2] mux_tree_tapbuf_size5_2_sram ; -wire [0:2] mux_tree_tapbuf_size5_3_sram ; -wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size6_1_sram ; -wire [0:2] mux_tree_tapbuf_size6_2_sram ; -wire [0:2] mux_tree_tapbuf_size6_3_sram ; -wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ; -// - -assign SC_IN_TOP = SC_IN_BOT ; - -sb_2__2__mux_tree_tapbuf_size6_0 mux_bottom_track_1 ( - .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_43_[0] , - bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , - bottom_left_grid_pin_49_[0] , chanx_left_in[1] } ) , - .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_bottom_track_1_undriven_sram_inv ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_82 ) ) ; -sb_2__2__mux_tree_tapbuf_size6_1 mux_bottom_track_5 ( - .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_43_[0] , - bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , - bottom_left_grid_pin_49_[0] , chanx_left_in[3] } ) , - .sram ( mux_tree_tapbuf_size6_1_sram ) , - .sram_inv ( mux_bottom_track_5_undriven_sram_inv ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_84 ) ) ; -sb_2__2__mux_tree_tapbuf_size6_2 mux_left_track_1 ( - .in ( { chany_bottom_in[19] , left_top_grid_pin_1_[0] , - left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , - left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , - .sram ( mux_tree_tapbuf_size6_2_sram ) , - .sram_inv ( mux_left_track_1_undriven_sram_inv ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_83 ) ) ; -sb_2__2__mux_tree_tapbuf_size6 mux_left_track_5 ( - .in ( { chany_bottom_in[1] , left_top_grid_pin_1_[0] , - left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , - left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , - .sram ( mux_tree_tapbuf_size6_3_sram ) , - .sram_inv ( mux_left_track_5_undriven_sram_inv ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_83 ) ) ; -sb_2__2__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_1 ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size6_mem_1 mem_bottom_track_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size6_mem_2 mem_left_track_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_2_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size6_mem mem_left_track_5 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_3_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size5_0 mux_bottom_track_3 ( - .in ( { bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , - bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , - chanx_left_in[2] } ) , - .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_bottom_track_3_undriven_sram_inv ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_82 ) ) ; -sb_2__2__mux_tree_tapbuf_size5_1 mux_bottom_track_7 ( - .in ( { bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , - bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , - chanx_left_in[4] } ) , - .sram ( mux_tree_tapbuf_size5_1_sram ) , - .sram_inv ( mux_bottom_track_7_undriven_sram_inv ) , - .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_84 ) ) ; -sb_2__2__mux_tree_tapbuf_size5_2 mux_left_track_3 ( - .in ( { chany_bottom_in[0] , left_bottom_grid_pin_34_[0] , - left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , - left_bottom_grid_pin_40_[0] } ) , - .sram ( mux_tree_tapbuf_size5_2_sram ) , - .sram_inv ( mux_left_track_3_undriven_sram_inv ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_82 ) ) ; -sb_2__2__mux_tree_tapbuf_size5 mux_left_track_7 ( - .in ( { chany_bottom_in[2] , left_bottom_grid_pin_34_[0] , - left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , - left_bottom_grid_pin_40_[0] } ) , - .sram ( mux_tree_tapbuf_size5_3_sram ) , - .sram_inv ( mux_left_track_7_undriven_sram_inv ) , - .out ( chanx_left_out[3] ) , .p0 ( optlc_net_82 ) ) ; -sb_2__2__mux_tree_tapbuf_size5_mem_0 mem_bottom_track_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size5_mem_1 mem_bottom_track_7 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size5_mem_2 mem_left_track_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_2_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size5_mem mem_left_track_7 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_3_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_9 mux_bottom_track_9 ( - .in ( { bottom_right_grid_pin_1_[0] , chanx_left_in[5] } ) , - .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_bottom_track_9_undriven_sram_inv ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_84 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_0 mux_bottom_track_11 ( - .in ( { bottom_left_grid_pin_42_[0] , chanx_left_in[6] } ) , - .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_bottom_track_11_undriven_sram_inv ) , - .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_84 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_1 mux_bottom_track_13 ( - .in ( { bottom_left_grid_pin_43_[0] , chanx_left_in[7] } ) , - .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_bottom_track_13_undriven_sram_inv ) , - .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_81 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_2 mux_bottom_track_15 ( - .in ( { bottom_left_grid_pin_44_[0] , chanx_left_in[8] } ) , - .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_bottom_track_15_undriven_sram_inv ) , - .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_81 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_3 mux_bottom_track_17 ( - .in ( { bottom_left_grid_pin_45_[0] , chanx_left_in[9] } ) , - .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_bottom_track_17_undriven_sram_inv ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_81 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_4 mux_bottom_track_19 ( - .in ( { bottom_left_grid_pin_46_[0] , chanx_left_in[10] } ) , - .sram ( mux_tree_tapbuf_size2_5_sram ) , - .sram_inv ( mux_bottom_track_19_undriven_sram_inv ) , - .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_84 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_5 mux_bottom_track_21 ( - .in ( { bottom_left_grid_pin_47_[0] , chanx_left_in[11] } ) , - .sram ( mux_tree_tapbuf_size2_6_sram ) , - .sram_inv ( mux_bottom_track_21_undriven_sram_inv ) , - .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_81 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_6 mux_bottom_track_23 ( - .in ( { bottom_left_grid_pin_48_[0] , chanx_left_in[12] } ) , - .sram ( mux_tree_tapbuf_size2_7_sram ) , - .sram_inv ( mux_bottom_track_23_undriven_sram_inv ) , - .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_84 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_7 mux_bottom_track_27 ( - .in ( { bottom_left_grid_pin_42_[0] , chanx_left_in[14] } ) , - .sram ( mux_tree_tapbuf_size2_8_sram ) , - .sram_inv ( mux_bottom_track_27_undriven_sram_inv ) , - .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_84 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_8 mux_bottom_track_29 ( - .in ( { bottom_left_grid_pin_43_[0] , chanx_left_in[15] } ) , - .sram ( mux_tree_tapbuf_size2_9_sram ) , - .sram_inv ( mux_bottom_track_29_undriven_sram_inv ) , - .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_81 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_10 mux_left_track_11 ( - .in ( { chany_bottom_in[4] , left_bottom_grid_pin_34_[0] } ) , - .sram ( mux_tree_tapbuf_size2_10_sram ) , - .sram_inv ( mux_left_track_11_undriven_sram_inv ) , - .out ( chanx_left_out[5] ) , .p0 ( optlc_net_82 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_11 mux_left_track_13 ( - .in ( { chany_bottom_in[5] , left_bottom_grid_pin_35_[0] } ) , - .sram ( mux_tree_tapbuf_size2_11_sram ) , - .sram_inv ( mux_left_track_13_undriven_sram_inv ) , - .out ( chanx_left_out[6] ) , .p0 ( optlc_net_83 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_12 mux_left_track_15 ( - .in ( { chany_bottom_in[6] , left_bottom_grid_pin_36_[0] } ) , - .sram ( mux_tree_tapbuf_size2_12_sram ) , - .sram_inv ( mux_left_track_15_undriven_sram_inv ) , - .out ( chanx_left_out[7] ) , .p0 ( optlc_net_83 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_13 mux_left_track_17 ( - .in ( { chany_bottom_in[7] , left_bottom_grid_pin_37_[0] } ) , - .sram ( mux_tree_tapbuf_size2_13_sram ) , - .sram_inv ( mux_left_track_17_undriven_sram_inv ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_83 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_14 mux_left_track_19 ( - .in ( { chany_bottom_in[8] , left_bottom_grid_pin_38_[0] } ) , - .sram ( mux_tree_tapbuf_size2_14_sram ) , - .sram_inv ( mux_left_track_19_undriven_sram_inv ) , - .out ( chanx_left_out[9] ) , .p0 ( optlc_net_83 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_15 mux_left_track_21 ( - .in ( { chany_bottom_in[9] , left_bottom_grid_pin_39_[0] } ) , - .sram ( mux_tree_tapbuf_size2_15_sram ) , - .sram_inv ( mux_left_track_21_undriven_sram_inv ) , - .out ( chanx_left_out[10] ) , .p0 ( optlc_net_82 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_16 mux_left_track_23 ( - .in ( { chany_bottom_in[10] , left_bottom_grid_pin_40_[0] } ) , - .sram ( mux_tree_tapbuf_size2_16_sram ) , - .sram_inv ( mux_left_track_23_undriven_sram_inv ) , - .out ( chanx_left_out[11] ) , .p0 ( optlc_net_82 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_17 mux_left_track_27 ( - .in ( { chany_bottom_in[12] , left_bottom_grid_pin_34_[0] } ) , - .sram ( mux_tree_tapbuf_size2_17_sram ) , - .sram_inv ( mux_left_track_27_undriven_sram_inv ) , - .out ( chanx_left_out[13] ) , .p0 ( optlc_net_82 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_18 mux_left_track_29 ( - .in ( { chany_bottom_in[13] , left_bottom_grid_pin_35_[0] } ) , - .sram ( mux_tree_tapbuf_size2_18_sram ) , - .sram_inv ( mux_left_track_29_undriven_sram_inv ) , - .out ( chanx_left_out[14] ) , .p0 ( optlc_net_82 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_19 mux_left_track_31 ( - .in ( { chany_bottom_in[14] , left_bottom_grid_pin_36_[0] } ) , - .sram ( mux_tree_tapbuf_size2_19_sram ) , - .sram_inv ( mux_left_track_31_undriven_sram_inv ) , - .out ( chanx_left_out[15] ) , .p0 ( optlc_net_83 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_20 mux_left_track_33 ( - .in ( { chany_bottom_in[15] , left_bottom_grid_pin_37_[0] } ) , - .sram ( mux_tree_tapbuf_size2_20_sram ) , - .sram_inv ( mux_left_track_33_undriven_sram_inv ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_83 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_21 mux_left_track_35 ( - .in ( { chany_bottom_in[16] , left_bottom_grid_pin_38_[0] } ) , - .sram ( mux_tree_tapbuf_size2_21_sram ) , - .sram_inv ( mux_left_track_35_undriven_sram_inv ) , - .out ( chanx_left_out[17] ) , .p0 ( optlc_net_81 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_22 mux_left_track_37 ( - .in ( { chany_bottom_in[17] , left_bottom_grid_pin_39_[0] } ) , - .sram ( mux_tree_tapbuf_size2_22_sram ) , - .sram_inv ( mux_left_track_37_undriven_sram_inv ) , - .out ( chanx_left_out[18] ) , .p0 ( optlc_net_83 ) ) ; -sb_2__2__mux_tree_tapbuf_size2 mux_left_track_39 ( - .in ( { chany_bottom_in[18] , left_bottom_grid_pin_40_[0] } ) , - .sram ( mux_tree_tapbuf_size2_23_sram ) , - .sram_inv ( mux_left_track_39_undriven_sram_inv ) , - .out ( chanx_left_out[19] ) , .p0 ( optlc_net_82 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_9 mem_bottom_track_9 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_0 mem_bottom_track_11 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_1 mem_bottom_track_13 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_2 mem_bottom_track_15 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_3 mem_bottom_track_17 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_4 mem_bottom_track_19 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_5 mem_bottom_track_21 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_6 mem_bottom_track_23 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_7 mem_bottom_track_27 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_8 mem_bottom_track_29 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_10 mem_left_track_11 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_11 mem_left_track_13 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_11_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_12 mem_left_track_15 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_12_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_13 mem_left_track_17 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_13_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_14 mem_left_track_19 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_14_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_15 mem_left_track_21 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_15_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_16 mem_left_track_23 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_16_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_17 mem_left_track_27 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_17_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_18 mem_left_track_29 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_18_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_19 mem_left_track_31 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_19_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_20 mem_left_track_33 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_20_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_21 mem_left_track_35 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_21_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_22 mem_left_track_37 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_22_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem mem_left_track_39 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , - .ccff_tail ( { ropt_net_91 } ) , - .mem_out ( mux_tree_tapbuf_size2_23_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size3_0 mux_bottom_track_25 ( - .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_49_[0] , - chanx_left_in[13] } ) , - .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_bottom_track_25_undriven_sram_inv ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_84 ) ) ; -sb_2__2__mux_tree_tapbuf_size3 mux_left_track_9 ( - .in ( { chany_bottom_in[3] , left_top_grid_pin_1_[0] , - left_bottom_grid_pin_41_[0] } ) , - .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_left_track_9_undriven_sram_inv ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_82 ) ) ; -sb_2__2__mux_tree_tapbuf_size3_1 mux_left_track_25 ( - .in ( { chany_bottom_in[11] , left_top_grid_pin_1_[0] , - left_bottom_grid_pin_41_[0] } ) , - .sram ( mux_tree_tapbuf_size3_2_sram ) , - .sram_inv ( mux_left_track_25_undriven_sram_inv ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_82 ) ) ; -sb_2__2__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_25 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size3_mem mem_left_track_9 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size3_mem_1 mem_left_track_25 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_688 ( .A ( ropt_net_94 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_689 ( .A ( ropt_net_95 ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_690 ( .A ( ropt_net_96 ) , - .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__conb_1 optlc_72 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_81 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__4 ( .A ( chanx_left_in[19] ) , - .X ( ropt_net_92 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_6__5 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_86 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_691 ( .A ( ropt_net_97 ) , - .X ( chany_bottom_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_692 ( .A ( ropt_net_98 ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_693 ( .A ( ropt_net_99 ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_694 ( .A ( ropt_net_100 ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_74 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_82 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_76 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_83 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_78 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_84 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_681 ( .A ( ropt_net_86 ) , - .X ( ropt_net_96 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_682 ( .A ( chanx_left_in[0] ) , - .X ( ropt_net_98 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_683 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_100 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_684 ( .A ( chanx_left_in[16] ) , - .X ( ropt_net_99 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_685 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_97 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_686 ( .A ( ropt_net_91 ) , - .X ( ropt_net_94 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_687 ( .A ( ropt_net_92 ) , - .X ( ropt_net_95 ) ) ; -endmodule - - diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__2__icv_in_design.lvs.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__2__icv_in_design.lvs.v deleted file mode 100644 index c5e6c55..0000000 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__2__icv_in_design.lvs.v +++ /dev/null @@ -1,4155 +0,0 @@ -// -// -// -// -// -// -module sb_2__2__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_35__40 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_34__39 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__38 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__37 ( .A ( mem_out[1] ) , - .X ( net_net_51 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_51 ( .A ( net_net_51 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_22 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__36 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_21 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__35 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_20 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__34 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_19 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__33 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_18 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__32 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_17 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__31 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__30 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__29 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__28 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__27 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__26 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__25 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__24 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__23 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__22 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__21 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__20 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__19 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__18 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__17 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__16 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__15 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__14 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_22 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_21 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_20 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_19 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__13 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size5_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__12 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size5_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__11 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__10 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__9 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size6_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__8 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__7 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__6 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2_ ( prog_clk , chany_bottom_in , bottom_right_grid_pin_1_ , - bottom_left_grid_pin_42_ , bottom_left_grid_pin_43_ , - bottom_left_grid_pin_44_ , bottom_left_grid_pin_45_ , - bottom_left_grid_pin_46_ , bottom_left_grid_pin_47_ , - bottom_left_grid_pin_48_ , bottom_left_grid_pin_49_ , chanx_left_in , - left_top_grid_pin_1_ , left_bottom_grid_pin_34_ , - left_bottom_grid_pin_35_ , left_bottom_grid_pin_36_ , - left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , - left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , - left_bottom_grid_pin_41_ , ccff_head , chany_bottom_out , chanx_left_out , - ccff_tail , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , SC_OUT_BOT , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:19] chany_bottom_in ; -input [0:0] bottom_right_grid_pin_1_ ; -input [0:0] bottom_left_grid_pin_42_ ; -input [0:0] bottom_left_grid_pin_43_ ; -input [0:0] bottom_left_grid_pin_44_ ; -input [0:0] bottom_left_grid_pin_45_ ; -input [0:0] bottom_left_grid_pin_46_ ; -input [0:0] bottom_left_grid_pin_47_ ; -input [0:0] bottom_left_grid_pin_48_ ; -input [0:0] bottom_left_grid_pin_49_ ; -input [0:19] chanx_left_in ; -input [0:0] left_top_grid_pin_1_ ; -input [0:0] left_bottom_grid_pin_34_ ; -input [0:0] left_bottom_grid_pin_35_ ; -input [0:0] left_bottom_grid_pin_36_ ; -input [0:0] left_bottom_grid_pin_37_ ; -input [0:0] left_bottom_grid_pin_38_ ; -input [0:0] left_bottom_grid_pin_39_ ; -input [0:0] left_bottom_grid_pin_40_ ; -input [0:0] left_bottom_grid_pin_41_ ; -input [0:0] ccff_head ; -output [0:19] chany_bottom_out ; -output [0:19] chanx_left_out ; -output [0:0] ccff_tail ; -input SC_IN_TOP ; -input SC_IN_BOT ; -output SC_OUT_TOP ; -output SC_OUT_BOT ; -input VDD ; -input VSS ; - -wire [0:1] mux_bottom_track_11_undriven_sram_inv ; -wire [0:1] mux_bottom_track_13_undriven_sram_inv ; -wire [0:1] mux_bottom_track_15_undriven_sram_inv ; -wire [0:1] mux_bottom_track_17_undriven_sram_inv ; -wire [0:1] mux_bottom_track_19_undriven_sram_inv ; -wire [0:2] mux_bottom_track_1_undriven_sram_inv ; -wire [0:1] mux_bottom_track_21_undriven_sram_inv ; -wire [0:1] mux_bottom_track_23_undriven_sram_inv ; -wire [0:1] mux_bottom_track_25_undriven_sram_inv ; -wire [0:1] mux_bottom_track_27_undriven_sram_inv ; -wire [0:1] mux_bottom_track_29_undriven_sram_inv ; -wire [0:2] mux_bottom_track_3_undriven_sram_inv ; -wire [0:2] mux_bottom_track_5_undriven_sram_inv ; -wire [0:2] mux_bottom_track_7_undriven_sram_inv ; -wire [0:1] mux_bottom_track_9_undriven_sram_inv ; -wire [0:1] mux_left_track_11_undriven_sram_inv ; -wire [0:1] mux_left_track_13_undriven_sram_inv ; -wire [0:1] mux_left_track_15_undriven_sram_inv ; -wire [0:1] mux_left_track_17_undriven_sram_inv ; -wire [0:1] mux_left_track_19_undriven_sram_inv ; -wire [0:2] mux_left_track_1_undriven_sram_inv ; -wire [0:1] mux_left_track_21_undriven_sram_inv ; -wire [0:1] mux_left_track_23_undriven_sram_inv ; -wire [0:1] mux_left_track_25_undriven_sram_inv ; -wire [0:1] mux_left_track_27_undriven_sram_inv ; -wire [0:1] mux_left_track_29_undriven_sram_inv ; -wire [0:1] mux_left_track_31_undriven_sram_inv ; -wire [0:1] mux_left_track_33_undriven_sram_inv ; -wire [0:1] mux_left_track_35_undriven_sram_inv ; -wire [0:1] mux_left_track_37_undriven_sram_inv ; -wire [0:1] mux_left_track_39_undriven_sram_inv ; -wire [0:2] mux_left_track_3_undriven_sram_inv ; -wire [0:2] mux_left_track_5_undriven_sram_inv ; -wire [0:2] mux_left_track_7_undriven_sram_inv ; -wire [0:1] mux_left_track_9_undriven_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_10_sram ; -wire [0:1] mux_tree_tapbuf_size2_11_sram ; -wire [0:1] mux_tree_tapbuf_size2_12_sram ; -wire [0:1] mux_tree_tapbuf_size2_13_sram ; -wire [0:1] mux_tree_tapbuf_size2_14_sram ; -wire [0:1] mux_tree_tapbuf_size2_15_sram ; -wire [0:1] mux_tree_tapbuf_size2_16_sram ; -wire [0:1] mux_tree_tapbuf_size2_17_sram ; -wire [0:1] mux_tree_tapbuf_size2_18_sram ; -wire [0:1] mux_tree_tapbuf_size2_19_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_20_sram ; -wire [0:1] mux_tree_tapbuf_size2_21_sram ; -wire [0:1] mux_tree_tapbuf_size2_22_sram ; -wire [0:1] mux_tree_tapbuf_size2_23_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_5_sram ; -wire [0:1] mux_tree_tapbuf_size2_6_sram ; -wire [0:1] mux_tree_tapbuf_size2_7_sram ; -wire [0:1] mux_tree_tapbuf_size2_8_sram ; -wire [0:1] mux_tree_tapbuf_size2_9_sram ; -wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_19_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_20_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_21_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_22_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; -wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:1] mux_tree_tapbuf_size3_2_sram ; -wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size5_0_sram ; -wire [0:2] mux_tree_tapbuf_size5_1_sram ; -wire [0:2] mux_tree_tapbuf_size5_2_sram ; -wire [0:2] mux_tree_tapbuf_size5_3_sram ; -wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size6_1_sram ; -wire [0:2] mux_tree_tapbuf_size6_2_sram ; -wire [0:2] mux_tree_tapbuf_size6_3_sram ; -wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ; -supply1 VDD ; -supply0 VSS ; -// - -assign SC_IN_TOP = SC_IN_BOT ; - -sb_2__2__mux_tree_tapbuf_size6_0 mux_bottom_track_1 ( - .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_43_[0] , - bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , - bottom_left_grid_pin_49_[0] , chanx_left_in[1] } ) , - .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_bottom_track_1_undriven_sram_inv ) , - .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_82 ) ) ; -sb_2__2__mux_tree_tapbuf_size6_1 mux_bottom_track_5 ( - .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_43_[0] , - bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , - bottom_left_grid_pin_49_[0] , chanx_left_in[3] } ) , - .sram ( mux_tree_tapbuf_size6_1_sram ) , - .sram_inv ( mux_bottom_track_5_undriven_sram_inv ) , - .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_84 ) ) ; -sb_2__2__mux_tree_tapbuf_size6_2 mux_left_track_1 ( - .in ( { chany_bottom_in[19] , left_top_grid_pin_1_[0] , - left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , - left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , - .sram ( mux_tree_tapbuf_size6_2_sram ) , - .sram_inv ( mux_left_track_1_undriven_sram_inv ) , - .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_83 ) ) ; -sb_2__2__mux_tree_tapbuf_size6 mux_left_track_5 ( - .in ( { chany_bottom_in[1] , left_top_grid_pin_1_[0] , - left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , - left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , - .sram ( mux_tree_tapbuf_size6_3_sram ) , - .sram_inv ( mux_left_track_5_undriven_sram_inv ) , - .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_83 ) ) ; -sb_2__2__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_1 ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__2__mux_tree_tapbuf_size6_mem_1 mem_bottom_track_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__2__mux_tree_tapbuf_size6_mem_2 mem_left_track_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__2__mux_tree_tapbuf_size6_mem mem_left_track_5 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__2__mux_tree_tapbuf_size5_0 mux_bottom_track_3 ( - .in ( { bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , - bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , - chanx_left_in[2] } ) , - .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_bottom_track_3_undriven_sram_inv ) , - .out ( chany_bottom_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_82 ) ) ; -sb_2__2__mux_tree_tapbuf_size5_1 mux_bottom_track_7 ( - .in ( { bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , - bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , - chanx_left_in[4] } ) , - .sram ( mux_tree_tapbuf_size5_1_sram ) , - .sram_inv ( mux_bottom_track_7_undriven_sram_inv ) , - .out ( chany_bottom_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_84 ) ) ; -sb_2__2__mux_tree_tapbuf_size5_2 mux_left_track_3 ( - .in ( { chany_bottom_in[0] , left_bottom_grid_pin_34_[0] , - left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , - left_bottom_grid_pin_40_[0] } ) , - .sram ( mux_tree_tapbuf_size5_2_sram ) , - .sram_inv ( mux_left_track_3_undriven_sram_inv ) , - .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_82 ) ) ; -sb_2__2__mux_tree_tapbuf_size5 mux_left_track_7 ( - .in ( { chany_bottom_in[2] , left_bottom_grid_pin_34_[0] , - left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , - left_bottom_grid_pin_40_[0] } ) , - .sram ( mux_tree_tapbuf_size5_3_sram ) , - .sram_inv ( mux_left_track_7_undriven_sram_inv ) , - .out ( chanx_left_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_82 ) ) ; -sb_2__2__mux_tree_tapbuf_size5_mem_0 mem_bottom_track_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__2__mux_tree_tapbuf_size5_mem_1 mem_bottom_track_7 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__2__mux_tree_tapbuf_size5_mem_2 mem_left_track_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__2__mux_tree_tapbuf_size5_mem mem_left_track_7 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__2__mux_tree_tapbuf_size2_9 mux_bottom_track_9 ( - .in ( { bottom_right_grid_pin_1_[0] , chanx_left_in[5] } ) , - .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_bottom_track_9_undriven_sram_inv ) , - .out ( chany_bottom_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_84 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_0 mux_bottom_track_11 ( - .in ( { bottom_left_grid_pin_42_[0] , chanx_left_in[6] } ) , - .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_bottom_track_11_undriven_sram_inv ) , - .out ( chany_bottom_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_84 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_1 mux_bottom_track_13 ( - .in ( { bottom_left_grid_pin_43_[0] , chanx_left_in[7] } ) , - .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_bottom_track_13_undriven_sram_inv ) , - .out ( chany_bottom_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_81 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_2 mux_bottom_track_15 ( - .in ( { bottom_left_grid_pin_44_[0] , chanx_left_in[8] } ) , - .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_bottom_track_15_undriven_sram_inv ) , - .out ( chany_bottom_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_81 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_3 mux_bottom_track_17 ( - .in ( { bottom_left_grid_pin_45_[0] , chanx_left_in[9] } ) , - .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_bottom_track_17_undriven_sram_inv ) , - .out ( chany_bottom_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_81 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_4 mux_bottom_track_19 ( - .in ( { bottom_left_grid_pin_46_[0] , chanx_left_in[10] } ) , - .sram ( mux_tree_tapbuf_size2_5_sram ) , - .sram_inv ( mux_bottom_track_19_undriven_sram_inv ) , - .out ( chany_bottom_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_84 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_5 mux_bottom_track_21 ( - .in ( { bottom_left_grid_pin_47_[0] , chanx_left_in[11] } ) , - .sram ( mux_tree_tapbuf_size2_6_sram ) , - .sram_inv ( mux_bottom_track_21_undriven_sram_inv ) , - .out ( chany_bottom_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_81 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_6 mux_bottom_track_23 ( - .in ( { bottom_left_grid_pin_48_[0] , chanx_left_in[12] } ) , - .sram ( mux_tree_tapbuf_size2_7_sram ) , - .sram_inv ( mux_bottom_track_23_undriven_sram_inv ) , - .out ( chany_bottom_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_84 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_7 mux_bottom_track_27 ( - .in ( { bottom_left_grid_pin_42_[0] , chanx_left_in[14] } ) , - .sram ( mux_tree_tapbuf_size2_8_sram ) , - .sram_inv ( mux_bottom_track_27_undriven_sram_inv ) , - .out ( chany_bottom_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_84 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_8 mux_bottom_track_29 ( - .in ( { bottom_left_grid_pin_43_[0] , chanx_left_in[15] } ) , - .sram ( mux_tree_tapbuf_size2_9_sram ) , - .sram_inv ( mux_bottom_track_29_undriven_sram_inv ) , - .out ( chany_bottom_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_81 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_10 mux_left_track_11 ( - .in ( { chany_bottom_in[4] , left_bottom_grid_pin_34_[0] } ) , - .sram ( mux_tree_tapbuf_size2_10_sram ) , - .sram_inv ( mux_left_track_11_undriven_sram_inv ) , - .out ( chanx_left_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_82 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_11 mux_left_track_13 ( - .in ( { chany_bottom_in[5] , left_bottom_grid_pin_35_[0] } ) , - .sram ( mux_tree_tapbuf_size2_11_sram ) , - .sram_inv ( mux_left_track_13_undriven_sram_inv ) , - .out ( chanx_left_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_83 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_12 mux_left_track_15 ( - .in ( { chany_bottom_in[6] , left_bottom_grid_pin_36_[0] } ) , - .sram ( mux_tree_tapbuf_size2_12_sram ) , - .sram_inv ( mux_left_track_15_undriven_sram_inv ) , - .out ( chanx_left_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_83 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_13 mux_left_track_17 ( - .in ( { chany_bottom_in[7] , left_bottom_grid_pin_37_[0] } ) , - .sram ( mux_tree_tapbuf_size2_13_sram ) , - .sram_inv ( mux_left_track_17_undriven_sram_inv ) , - .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_83 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_14 mux_left_track_19 ( - .in ( { chany_bottom_in[8] , left_bottom_grid_pin_38_[0] } ) , - .sram ( mux_tree_tapbuf_size2_14_sram ) , - .sram_inv ( mux_left_track_19_undriven_sram_inv ) , - .out ( chanx_left_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_83 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_15 mux_left_track_21 ( - .in ( { chany_bottom_in[9] , left_bottom_grid_pin_39_[0] } ) , - .sram ( mux_tree_tapbuf_size2_15_sram ) , - .sram_inv ( mux_left_track_21_undriven_sram_inv ) , - .out ( chanx_left_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_82 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_16 mux_left_track_23 ( - .in ( { chany_bottom_in[10] , left_bottom_grid_pin_40_[0] } ) , - .sram ( mux_tree_tapbuf_size2_16_sram ) , - .sram_inv ( mux_left_track_23_undriven_sram_inv ) , - .out ( chanx_left_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_82 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_17 mux_left_track_27 ( - .in ( { chany_bottom_in[12] , left_bottom_grid_pin_34_[0] } ) , - .sram ( mux_tree_tapbuf_size2_17_sram ) , - .sram_inv ( mux_left_track_27_undriven_sram_inv ) , - .out ( chanx_left_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_82 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_18 mux_left_track_29 ( - .in ( { chany_bottom_in[13] , left_bottom_grid_pin_35_[0] } ) , - .sram ( mux_tree_tapbuf_size2_18_sram ) , - .sram_inv ( mux_left_track_29_undriven_sram_inv ) , - .out ( chanx_left_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_82 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_19 mux_left_track_31 ( - .in ( { chany_bottom_in[14] , left_bottom_grid_pin_36_[0] } ) , - .sram ( mux_tree_tapbuf_size2_19_sram ) , - .sram_inv ( mux_left_track_31_undriven_sram_inv ) , - .out ( chanx_left_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_83 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_20 mux_left_track_33 ( - .in ( { chany_bottom_in[15] , left_bottom_grid_pin_37_[0] } ) , - .sram ( mux_tree_tapbuf_size2_20_sram ) , - .sram_inv ( mux_left_track_33_undriven_sram_inv ) , - .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_83 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_21 mux_left_track_35 ( - .in ( { chany_bottom_in[16] , left_bottom_grid_pin_38_[0] } ) , - .sram ( mux_tree_tapbuf_size2_21_sram ) , - .sram_inv ( mux_left_track_35_undriven_sram_inv ) , - .out ( chanx_left_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_81 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_22 mux_left_track_37 ( - .in ( { chany_bottom_in[17] , left_bottom_grid_pin_39_[0] } ) , - .sram ( mux_tree_tapbuf_size2_22_sram ) , - .sram_inv ( mux_left_track_37_undriven_sram_inv ) , - .out ( chanx_left_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_83 ) ) ; -sb_2__2__mux_tree_tapbuf_size2 mux_left_track_39 ( - .in ( { chany_bottom_in[18] , left_bottom_grid_pin_40_[0] } ) , - .sram ( mux_tree_tapbuf_size2_23_sram ) , - .sram_inv ( mux_left_track_39_undriven_sram_inv ) , - .out ( chanx_left_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_82 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_9 mem_bottom_track_9 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_0 mem_bottom_track_11 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_1 mem_bottom_track_13 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_2 mem_bottom_track_15 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_3 mem_bottom_track_17 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_4 mem_bottom_track_19 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_5 mem_bottom_track_21 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_6 mem_bottom_track_23 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_7 mem_bottom_track_27 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_8_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_8 mem_bottom_track_29 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_9_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_10 mem_left_track_11 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_10_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_11 mem_left_track_13 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_11_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_12 mem_left_track_15 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_12_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_13 mem_left_track_17 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_13_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_14 mem_left_track_19 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_14_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_15 mem_left_track_21 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_15_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_16 mem_left_track_23 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_16_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_17 mem_left_track_27 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_17_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_18 mem_left_track_29 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_18_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_19 mem_left_track_31 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_19_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_20 mem_left_track_33 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_20_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_21 mem_left_track_35 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_21_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_22 mem_left_track_37 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_22_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem mem_left_track_39 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , - .ccff_tail ( { ropt_net_91 } ) , - .mem_out ( mux_tree_tapbuf_size2_23_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__2__mux_tree_tapbuf_size3_0 mux_bottom_track_25 ( - .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_49_[0] , - chanx_left_in[13] } ) , - .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_bottom_track_25_undriven_sram_inv ) , - .out ( chany_bottom_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_84 ) ) ; -sb_2__2__mux_tree_tapbuf_size3 mux_left_track_9 ( - .in ( { chany_bottom_in[3] , left_top_grid_pin_1_[0] , - left_bottom_grid_pin_41_[0] } ) , - .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_left_track_9_undriven_sram_inv ) , - .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_82 ) ) ; -sb_2__2__mux_tree_tapbuf_size3_1 mux_left_track_25 ( - .in ( { chany_bottom_in[11] , left_top_grid_pin_1_[0] , - left_bottom_grid_pin_41_[0] } ) , - .sram ( mux_tree_tapbuf_size3_2_sram ) , - .sram_inv ( mux_left_track_25_undriven_sram_inv ) , - .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_82 ) ) ; -sb_2__2__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_25 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__2__mux_tree_tapbuf_size3_mem mem_left_track_9 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__2__mux_tree_tapbuf_size3_mem_1 mem_left_track_25 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1543 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1544 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1545 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1546 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1547 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1548 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1549 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1550 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1551 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1552 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1553 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1554 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1555 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1556 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1557 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1558 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1559 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1560 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1561 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1562 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1563 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1564 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1565 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1566 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1567 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1568 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1569 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1570 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1571 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1572 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1573 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1574 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1575 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1576 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1577 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1578 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1579 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1580 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_688 ( .A ( ropt_net_94 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_689 ( .A ( ropt_net_95 ) , - .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_690 ( .A ( ropt_net_96 ) , - .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_72 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_81 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__4 ( .A ( chanx_left_in[19] ) , - .X ( ropt_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_6__5 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_86 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_691 ( .A ( ropt_net_97 ) , - .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_692 ( .A ( ropt_net_98 ) , - .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_693 ( .A ( ropt_net_99 ) , - .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_694 ( .A ( ropt_net_100 ) , - .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_74 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_82 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_76 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_83 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_78 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_84 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_681 ( .A ( ropt_net_86 ) , - .X ( ropt_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_682 ( .A ( chanx_left_in[0] ) , - .X ( ropt_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_683 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_684 ( .A ( chanx_left_in[16] ) , - .X ( ropt_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_685 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_97 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_686 ( .A ( ropt_net_91 ) , - .X ( ropt_net_94 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_687 ( .A ( ropt_net_92 ) , - .X ( ropt_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y0 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y0 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x358800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x418600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x437000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x616400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x699200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x386400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x423200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x607200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x625600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x782000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x818800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x855600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x294400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x312800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x349600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x418600y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x501400y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x570400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x653200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x690000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x708400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x759000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x768200y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x837200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x874000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x294400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x312800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x363400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x414000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x450800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x547400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x644000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x653200y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x731400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x749800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x759000y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x837200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x133400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x142600y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x188600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x239200y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x331200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x391000y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x437000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x446200y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x524400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x542800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x630200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x680800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x699200y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x133400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x193200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x340400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x349600y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x427800y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x506000y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x547400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x584200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x602600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x110400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x161000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x179400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x188600y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x266800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x303600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x322000y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x437000y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x556600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x565800y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x680800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x837200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x874000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x92000y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x138000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x156400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x207000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x225400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x276000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x312800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x331200y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x349600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x358800y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x404800y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x450800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x565800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x602600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x639400y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x754400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x791200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x828000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x101200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x179400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x239200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x276000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x294400y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x427800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x446200y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x524400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x680800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x699200y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x179400y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x345000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x395600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x404800y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x450800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x524400y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x602600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x639400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x657800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x851000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x59800y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x142600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x193200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x230000y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x345000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x400200y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x552000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x648600y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x694600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x713000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x722200y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x768200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x841800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x878600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x36800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x46000y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x92000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x128800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x179400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x239200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x276000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x312800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x381800y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x460000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x699200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x717600y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x841800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x55200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x92000y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x138000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x174800y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x437000y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x483000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x570400y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x616400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x676200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x694600y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x736000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x754400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x837200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x874000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x340400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x358800y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x437000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x519800y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x708400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x717600y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x82800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x119600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x128800y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x170200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x207000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x243800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x253000y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x299000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x317400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x538200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x556600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x565800y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x644000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x653200y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x731400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x768200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x841800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x878600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x55200y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x133400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x170200y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x331200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x349600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x358800y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x400200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x437000y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x524400y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x602600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x639400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x722200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x851000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x124200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x133400y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x179400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x299000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x515200y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x598000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x616400y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x662400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x680800y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x722200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x740600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x749800y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x828000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x864800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x901600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x59800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x96600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x188600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x225400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x262200y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x340400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x460000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x496800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x515200y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x533600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x552000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x662400y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x708400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x64400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x101200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x119600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x317400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x432400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x450800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x533600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x694600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x754400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x791200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x828000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x864800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x901600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x59800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x69000y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x211600y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x230000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x239200y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x285200y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x363400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x400200y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x731400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x740600y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x782000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x818800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x855600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x36800y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x276000y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x358800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x538200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x547400y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x708400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x782000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x818800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x855600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x892400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x782000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x818800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x855600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x138000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x174800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x211600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x248400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x322000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x473800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x492200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x579600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x598000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x749800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x786600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x823400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x860200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x897000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x55200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x92000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x110400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x119600y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x165600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x211600y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x294400y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x381800y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x575000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x593400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x754400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x791200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x828000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x59800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x96600y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x174800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x276000y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x354200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x128800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x147200y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x179400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x216200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x253000y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x299000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x317400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x326600y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x483000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x607200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x625600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x676200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x713000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x749800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x786600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x823400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x860200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x133400y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x165600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x184000y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x262200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x335800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x391000y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x510600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x529000y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x575000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x184000y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x414000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x450800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x708400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x782000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x818800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x855600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x372600y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x414000y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x492200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x565800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x602600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x639400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x676200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x713000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x749800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x786600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x823400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x860200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y816000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y843200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y870400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y870400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y897600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y897600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y924800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y924800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y952000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x887800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y952000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__2__icv_in_design.pt.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__2__icv_in_design.pt.v deleted file mode 100644 index 17a48d8..0000000 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__2__icv_in_design.pt.v +++ /dev/null @@ -1,1957 +0,0 @@ -// -// -// -// -// -// -module sb_2__2__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_35__40 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_34__39 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__38 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__37 ( .A ( mem_out[1] ) , - .X ( net_net_51 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_51 ( .A ( net_net_51 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_22 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__36 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_21 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__35 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_20 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__34 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_19 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__33 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_18 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__32 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_17 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__31 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__30 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__29 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__28 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__27 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__26 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__25 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__24 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__23 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__22 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__21 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__20 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__19 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__18 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__17 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__16 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__15 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__14 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_22 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_21 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_20 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_19 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__13 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size5_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__12 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size5_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__11 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__10 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:4] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__9 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size6_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__8 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__7 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; - -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__6 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module sb_2__2_ ( prog_clk , chany_bottom_in , bottom_right_grid_pin_1_ , - bottom_left_grid_pin_42_ , bottom_left_grid_pin_43_ , - bottom_left_grid_pin_44_ , bottom_left_grid_pin_45_ , - bottom_left_grid_pin_46_ , bottom_left_grid_pin_47_ , - bottom_left_grid_pin_48_ , bottom_left_grid_pin_49_ , chanx_left_in , - left_top_grid_pin_1_ , left_bottom_grid_pin_34_ , - left_bottom_grid_pin_35_ , left_bottom_grid_pin_36_ , - left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , - left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , - left_bottom_grid_pin_41_ , ccff_head , chany_bottom_out , chanx_left_out , - ccff_tail , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , SC_OUT_BOT ) ; -input [0:0] prog_clk ; -input [0:19] chany_bottom_in ; -input [0:0] bottom_right_grid_pin_1_ ; -input [0:0] bottom_left_grid_pin_42_ ; -input [0:0] bottom_left_grid_pin_43_ ; -input [0:0] bottom_left_grid_pin_44_ ; -input [0:0] bottom_left_grid_pin_45_ ; -input [0:0] bottom_left_grid_pin_46_ ; -input [0:0] bottom_left_grid_pin_47_ ; -input [0:0] bottom_left_grid_pin_48_ ; -input [0:0] bottom_left_grid_pin_49_ ; -input [0:19] chanx_left_in ; -input [0:0] left_top_grid_pin_1_ ; -input [0:0] left_bottom_grid_pin_34_ ; -input [0:0] left_bottom_grid_pin_35_ ; -input [0:0] left_bottom_grid_pin_36_ ; -input [0:0] left_bottom_grid_pin_37_ ; -input [0:0] left_bottom_grid_pin_38_ ; -input [0:0] left_bottom_grid_pin_39_ ; -input [0:0] left_bottom_grid_pin_40_ ; -input [0:0] left_bottom_grid_pin_41_ ; -input [0:0] ccff_head ; -output [0:19] chany_bottom_out ; -output [0:19] chanx_left_out ; -output [0:0] ccff_tail ; -input SC_IN_TOP ; -input SC_IN_BOT ; -output SC_OUT_TOP ; -output SC_OUT_BOT ; - -wire [0:1] mux_bottom_track_11_undriven_sram_inv ; -wire [0:1] mux_bottom_track_13_undriven_sram_inv ; -wire [0:1] mux_bottom_track_15_undriven_sram_inv ; -wire [0:1] mux_bottom_track_17_undriven_sram_inv ; -wire [0:1] mux_bottom_track_19_undriven_sram_inv ; -wire [0:2] mux_bottom_track_1_undriven_sram_inv ; -wire [0:1] mux_bottom_track_21_undriven_sram_inv ; -wire [0:1] mux_bottom_track_23_undriven_sram_inv ; -wire [0:1] mux_bottom_track_25_undriven_sram_inv ; -wire [0:1] mux_bottom_track_27_undriven_sram_inv ; -wire [0:1] mux_bottom_track_29_undriven_sram_inv ; -wire [0:2] mux_bottom_track_3_undriven_sram_inv ; -wire [0:2] mux_bottom_track_5_undriven_sram_inv ; -wire [0:2] mux_bottom_track_7_undriven_sram_inv ; -wire [0:1] mux_bottom_track_9_undriven_sram_inv ; -wire [0:1] mux_left_track_11_undriven_sram_inv ; -wire [0:1] mux_left_track_13_undriven_sram_inv ; -wire [0:1] mux_left_track_15_undriven_sram_inv ; -wire [0:1] mux_left_track_17_undriven_sram_inv ; -wire [0:1] mux_left_track_19_undriven_sram_inv ; -wire [0:2] mux_left_track_1_undriven_sram_inv ; -wire [0:1] mux_left_track_21_undriven_sram_inv ; -wire [0:1] mux_left_track_23_undriven_sram_inv ; -wire [0:1] mux_left_track_25_undriven_sram_inv ; -wire [0:1] mux_left_track_27_undriven_sram_inv ; -wire [0:1] mux_left_track_29_undriven_sram_inv ; -wire [0:1] mux_left_track_31_undriven_sram_inv ; -wire [0:1] mux_left_track_33_undriven_sram_inv ; -wire [0:1] mux_left_track_35_undriven_sram_inv ; -wire [0:1] mux_left_track_37_undriven_sram_inv ; -wire [0:1] mux_left_track_39_undriven_sram_inv ; -wire [0:2] mux_left_track_3_undriven_sram_inv ; -wire [0:2] mux_left_track_5_undriven_sram_inv ; -wire [0:2] mux_left_track_7_undriven_sram_inv ; -wire [0:1] mux_left_track_9_undriven_sram_inv ; -wire [0:1] mux_tree_tapbuf_size2_0_sram ; -wire [0:1] mux_tree_tapbuf_size2_10_sram ; -wire [0:1] mux_tree_tapbuf_size2_11_sram ; -wire [0:1] mux_tree_tapbuf_size2_12_sram ; -wire [0:1] mux_tree_tapbuf_size2_13_sram ; -wire [0:1] mux_tree_tapbuf_size2_14_sram ; -wire [0:1] mux_tree_tapbuf_size2_15_sram ; -wire [0:1] mux_tree_tapbuf_size2_16_sram ; -wire [0:1] mux_tree_tapbuf_size2_17_sram ; -wire [0:1] mux_tree_tapbuf_size2_18_sram ; -wire [0:1] mux_tree_tapbuf_size2_19_sram ; -wire [0:1] mux_tree_tapbuf_size2_1_sram ; -wire [0:1] mux_tree_tapbuf_size2_20_sram ; -wire [0:1] mux_tree_tapbuf_size2_21_sram ; -wire [0:1] mux_tree_tapbuf_size2_22_sram ; -wire [0:1] mux_tree_tapbuf_size2_23_sram ; -wire [0:1] mux_tree_tapbuf_size2_2_sram ; -wire [0:1] mux_tree_tapbuf_size2_3_sram ; -wire [0:1] mux_tree_tapbuf_size2_4_sram ; -wire [0:1] mux_tree_tapbuf_size2_5_sram ; -wire [0:1] mux_tree_tapbuf_size2_6_sram ; -wire [0:1] mux_tree_tapbuf_size2_7_sram ; -wire [0:1] mux_tree_tapbuf_size2_8_sram ; -wire [0:1] mux_tree_tapbuf_size2_9_sram ; -wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_19_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_20_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_21_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_22_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; -wire [0:1] mux_tree_tapbuf_size3_0_sram ; -wire [0:1] mux_tree_tapbuf_size3_1_sram ; -wire [0:1] mux_tree_tapbuf_size3_2_sram ; -wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size5_0_sram ; -wire [0:2] mux_tree_tapbuf_size5_1_sram ; -wire [0:2] mux_tree_tapbuf_size5_2_sram ; -wire [0:2] mux_tree_tapbuf_size5_3_sram ; -wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ; -wire [0:2] mux_tree_tapbuf_size6_0_sram ; -wire [0:2] mux_tree_tapbuf_size6_1_sram ; -wire [0:2] mux_tree_tapbuf_size6_2_sram ; -wire [0:2] mux_tree_tapbuf_size6_3_sram ; -wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ; -// - -assign SC_IN_TOP = SC_IN_BOT ; - -sb_2__2__mux_tree_tapbuf_size6_0 mux_bottom_track_1 ( - .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_43_[0] , - bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , - bottom_left_grid_pin_49_[0] , chanx_left_in[1] } ) , - .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_bottom_track_1_undriven_sram_inv ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_82 ) ) ; -sb_2__2__mux_tree_tapbuf_size6_1 mux_bottom_track_5 ( - .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_43_[0] , - bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , - bottom_left_grid_pin_49_[0] , chanx_left_in[3] } ) , - .sram ( mux_tree_tapbuf_size6_1_sram ) , - .sram_inv ( mux_bottom_track_5_undriven_sram_inv ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_84 ) ) ; -sb_2__2__mux_tree_tapbuf_size6_2 mux_left_track_1 ( - .in ( { chany_bottom_in[19] , left_top_grid_pin_1_[0] , - left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , - left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , - .sram ( mux_tree_tapbuf_size6_2_sram ) , - .sram_inv ( mux_left_track_1_undriven_sram_inv ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_83 ) ) ; -sb_2__2__mux_tree_tapbuf_size6 mux_left_track_5 ( - .in ( { chany_bottom_in[1] , left_top_grid_pin_1_[0] , - left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , - left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , - .sram ( mux_tree_tapbuf_size6_3_sram ) , - .sram_inv ( mux_left_track_5_undriven_sram_inv ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_83 ) ) ; -sb_2__2__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_1 ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size6_mem_1 mem_bottom_track_5 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size6_mem_2 mem_left_track_1 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_2_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size6_mem mem_left_track_5 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size6_3_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size5_0 mux_bottom_track_3 ( - .in ( { bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , - bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , - chanx_left_in[2] } ) , - .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_bottom_track_3_undriven_sram_inv ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_82 ) ) ; -sb_2__2__mux_tree_tapbuf_size5_1 mux_bottom_track_7 ( - .in ( { bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , - bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , - chanx_left_in[4] } ) , - .sram ( mux_tree_tapbuf_size5_1_sram ) , - .sram_inv ( mux_bottom_track_7_undriven_sram_inv ) , - .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_84 ) ) ; -sb_2__2__mux_tree_tapbuf_size5_2 mux_left_track_3 ( - .in ( { chany_bottom_in[0] , left_bottom_grid_pin_34_[0] , - left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , - left_bottom_grid_pin_40_[0] } ) , - .sram ( mux_tree_tapbuf_size5_2_sram ) , - .sram_inv ( mux_left_track_3_undriven_sram_inv ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_82 ) ) ; -sb_2__2__mux_tree_tapbuf_size5 mux_left_track_7 ( - .in ( { chany_bottom_in[2] , left_bottom_grid_pin_34_[0] , - left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , - left_bottom_grid_pin_40_[0] } ) , - .sram ( mux_tree_tapbuf_size5_3_sram ) , - .sram_inv ( mux_left_track_7_undriven_sram_inv ) , - .out ( chanx_left_out[3] ) , .p0 ( optlc_net_82 ) ) ; -sb_2__2__mux_tree_tapbuf_size5_mem_0 mem_bottom_track_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size5_mem_1 mem_bottom_track_7 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size5_mem_2 mem_left_track_3 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_2_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size5_mem mem_left_track_7 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size5_3_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_9 mux_bottom_track_9 ( - .in ( { bottom_right_grid_pin_1_[0] , chanx_left_in[5] } ) , - .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_bottom_track_9_undriven_sram_inv ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_84 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_0 mux_bottom_track_11 ( - .in ( { bottom_left_grid_pin_42_[0] , chanx_left_in[6] } ) , - .sram ( mux_tree_tapbuf_size2_1_sram ) , - .sram_inv ( mux_bottom_track_11_undriven_sram_inv ) , - .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_84 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_1 mux_bottom_track_13 ( - .in ( { bottom_left_grid_pin_43_[0] , chanx_left_in[7] } ) , - .sram ( mux_tree_tapbuf_size2_2_sram ) , - .sram_inv ( mux_bottom_track_13_undriven_sram_inv ) , - .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_81 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_2 mux_bottom_track_15 ( - .in ( { bottom_left_grid_pin_44_[0] , chanx_left_in[8] } ) , - .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_bottom_track_15_undriven_sram_inv ) , - .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_81 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_3 mux_bottom_track_17 ( - .in ( { bottom_left_grid_pin_45_[0] , chanx_left_in[9] } ) , - .sram ( mux_tree_tapbuf_size2_4_sram ) , - .sram_inv ( mux_bottom_track_17_undriven_sram_inv ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_81 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_4 mux_bottom_track_19 ( - .in ( { bottom_left_grid_pin_46_[0] , chanx_left_in[10] } ) , - .sram ( mux_tree_tapbuf_size2_5_sram ) , - .sram_inv ( mux_bottom_track_19_undriven_sram_inv ) , - .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_84 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_5 mux_bottom_track_21 ( - .in ( { bottom_left_grid_pin_47_[0] , chanx_left_in[11] } ) , - .sram ( mux_tree_tapbuf_size2_6_sram ) , - .sram_inv ( mux_bottom_track_21_undriven_sram_inv ) , - .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_81 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_6 mux_bottom_track_23 ( - .in ( { bottom_left_grid_pin_48_[0] , chanx_left_in[12] } ) , - .sram ( mux_tree_tapbuf_size2_7_sram ) , - .sram_inv ( mux_bottom_track_23_undriven_sram_inv ) , - .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_84 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_7 mux_bottom_track_27 ( - .in ( { bottom_left_grid_pin_42_[0] , chanx_left_in[14] } ) , - .sram ( mux_tree_tapbuf_size2_8_sram ) , - .sram_inv ( mux_bottom_track_27_undriven_sram_inv ) , - .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_84 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_8 mux_bottom_track_29 ( - .in ( { bottom_left_grid_pin_43_[0] , chanx_left_in[15] } ) , - .sram ( mux_tree_tapbuf_size2_9_sram ) , - .sram_inv ( mux_bottom_track_29_undriven_sram_inv ) , - .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_81 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_10 mux_left_track_11 ( - .in ( { chany_bottom_in[4] , left_bottom_grid_pin_34_[0] } ) , - .sram ( mux_tree_tapbuf_size2_10_sram ) , - .sram_inv ( mux_left_track_11_undriven_sram_inv ) , - .out ( chanx_left_out[5] ) , .p0 ( optlc_net_82 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_11 mux_left_track_13 ( - .in ( { chany_bottom_in[5] , left_bottom_grid_pin_35_[0] } ) , - .sram ( mux_tree_tapbuf_size2_11_sram ) , - .sram_inv ( mux_left_track_13_undriven_sram_inv ) , - .out ( chanx_left_out[6] ) , .p0 ( optlc_net_83 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_12 mux_left_track_15 ( - .in ( { chany_bottom_in[6] , left_bottom_grid_pin_36_[0] } ) , - .sram ( mux_tree_tapbuf_size2_12_sram ) , - .sram_inv ( mux_left_track_15_undriven_sram_inv ) , - .out ( chanx_left_out[7] ) , .p0 ( optlc_net_83 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_13 mux_left_track_17 ( - .in ( { chany_bottom_in[7] , left_bottom_grid_pin_37_[0] } ) , - .sram ( mux_tree_tapbuf_size2_13_sram ) , - .sram_inv ( mux_left_track_17_undriven_sram_inv ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_83 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_14 mux_left_track_19 ( - .in ( { chany_bottom_in[8] , left_bottom_grid_pin_38_[0] } ) , - .sram ( mux_tree_tapbuf_size2_14_sram ) , - .sram_inv ( mux_left_track_19_undriven_sram_inv ) , - .out ( chanx_left_out[9] ) , .p0 ( optlc_net_83 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_15 mux_left_track_21 ( - .in ( { chany_bottom_in[9] , left_bottom_grid_pin_39_[0] } ) , - .sram ( mux_tree_tapbuf_size2_15_sram ) , - .sram_inv ( mux_left_track_21_undriven_sram_inv ) , - .out ( chanx_left_out[10] ) , .p0 ( optlc_net_82 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_16 mux_left_track_23 ( - .in ( { chany_bottom_in[10] , left_bottom_grid_pin_40_[0] } ) , - .sram ( mux_tree_tapbuf_size2_16_sram ) , - .sram_inv ( mux_left_track_23_undriven_sram_inv ) , - .out ( chanx_left_out[11] ) , .p0 ( optlc_net_82 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_17 mux_left_track_27 ( - .in ( { chany_bottom_in[12] , left_bottom_grid_pin_34_[0] } ) , - .sram ( mux_tree_tapbuf_size2_17_sram ) , - .sram_inv ( mux_left_track_27_undriven_sram_inv ) , - .out ( chanx_left_out[13] ) , .p0 ( optlc_net_82 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_18 mux_left_track_29 ( - .in ( { chany_bottom_in[13] , left_bottom_grid_pin_35_[0] } ) , - .sram ( mux_tree_tapbuf_size2_18_sram ) , - .sram_inv ( mux_left_track_29_undriven_sram_inv ) , - .out ( chanx_left_out[14] ) , .p0 ( optlc_net_82 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_19 mux_left_track_31 ( - .in ( { chany_bottom_in[14] , left_bottom_grid_pin_36_[0] } ) , - .sram ( mux_tree_tapbuf_size2_19_sram ) , - .sram_inv ( mux_left_track_31_undriven_sram_inv ) , - .out ( chanx_left_out[15] ) , .p0 ( optlc_net_83 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_20 mux_left_track_33 ( - .in ( { chany_bottom_in[15] , left_bottom_grid_pin_37_[0] } ) , - .sram ( mux_tree_tapbuf_size2_20_sram ) , - .sram_inv ( mux_left_track_33_undriven_sram_inv ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_83 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_21 mux_left_track_35 ( - .in ( { chany_bottom_in[16] , left_bottom_grid_pin_38_[0] } ) , - .sram ( mux_tree_tapbuf_size2_21_sram ) , - .sram_inv ( mux_left_track_35_undriven_sram_inv ) , - .out ( chanx_left_out[17] ) , .p0 ( optlc_net_81 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_22 mux_left_track_37 ( - .in ( { chany_bottom_in[17] , left_bottom_grid_pin_39_[0] } ) , - .sram ( mux_tree_tapbuf_size2_22_sram ) , - .sram_inv ( mux_left_track_37_undriven_sram_inv ) , - .out ( chanx_left_out[18] ) , .p0 ( optlc_net_83 ) ) ; -sb_2__2__mux_tree_tapbuf_size2 mux_left_track_39 ( - .in ( { chany_bottom_in[18] , left_bottom_grid_pin_40_[0] } ) , - .sram ( mux_tree_tapbuf_size2_23_sram ) , - .sram_inv ( mux_left_track_39_undriven_sram_inv ) , - .out ( chanx_left_out[19] ) , .p0 ( optlc_net_82 ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_9 mem_bottom_track_9 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_0 mem_bottom_track_11 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_1 mem_bottom_track_13 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_2 mem_bottom_track_15 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_3 mem_bottom_track_17 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_4 mem_bottom_track_19 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_5 mem_bottom_track_21 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_6 mem_bottom_track_23 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_7 mem_bottom_track_27 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_8 mem_bottom_track_29 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_10 mem_left_track_11 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_11 mem_left_track_13 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_11_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_12 mem_left_track_15 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_12_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_13 mem_left_track_17 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_13_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_14 mem_left_track_19 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_14_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_15 mem_left_track_21 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_15_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_16 mem_left_track_23 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_16_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_17 mem_left_track_27 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_17_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_18 mem_left_track_29 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_18_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_19 mem_left_track_31 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_19_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_20 mem_left_track_33 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_20_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_21 mem_left_track_35 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_21_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem_22 mem_left_track_37 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size2_22_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size2_mem mem_left_track_39 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , - .ccff_tail ( { ropt_net_91 } ) , - .mem_out ( mux_tree_tapbuf_size2_23_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size3_0 mux_bottom_track_25 ( - .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_49_[0] , - chanx_left_in[13] } ) , - .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_bottom_track_25_undriven_sram_inv ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_84 ) ) ; -sb_2__2__mux_tree_tapbuf_size3 mux_left_track_9 ( - .in ( { chany_bottom_in[3] , left_top_grid_pin_1_[0] , - left_bottom_grid_pin_41_[0] } ) , - .sram ( mux_tree_tapbuf_size3_1_sram ) , - .sram_inv ( mux_left_track_9_undriven_sram_inv ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_82 ) ) ; -sb_2__2__mux_tree_tapbuf_size3_1 mux_left_track_25 ( - .in ( { chany_bottom_in[11] , left_top_grid_pin_1_[0] , - left_bottom_grid_pin_41_[0] } ) , - .sram ( mux_tree_tapbuf_size3_2_sram ) , - .sram_inv ( mux_left_track_25_undriven_sram_inv ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_82 ) ) ; -sb_2__2__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_25 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size3_mem mem_left_track_9 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; -sb_2__2__mux_tree_tapbuf_size3_mem_1 mem_left_track_25 ( - .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_688 ( .A ( ropt_net_94 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_689 ( .A ( ropt_net_95 ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_690 ( .A ( ropt_net_96 ) , - .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__conb_1 optlc_72 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_81 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__4 ( .A ( chanx_left_in[19] ) , - .X ( ropt_net_92 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_6__5 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_86 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_691 ( .A ( ropt_net_97 ) , - .X ( chany_bottom_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_692 ( .A ( ropt_net_98 ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_693 ( .A ( ropt_net_99 ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_694 ( .A ( ropt_net_100 ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_74 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_82 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_76 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_83 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_78 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_84 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_681 ( .A ( ropt_net_86 ) , - .X ( ropt_net_96 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_682 ( .A ( chanx_left_in[0] ) , - .X ( ropt_net_98 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_683 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_100 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_684 ( .A ( chanx_left_in[16] ) , - .X ( ropt_net_99 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_685 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_97 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_686 ( .A ( ropt_net_91 ) , - .X ( ropt_net_94 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_687 ( .A ( ropt_net_92 ) , - .X ( ropt_net_95 ) ) ; -endmodule - -